MAX1630AEAI - Maxim Integrated Products, Inc.

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

________________General Description

The MAX1630A–MAX1635A are buck-topology, step-

down, switch-mode, power-supply controllers that gener-

ate logic-supply voltages in battery-powered systems.

These high-performance, dual-/triple-output devices

include on-board power-up sequencing, power-good

signaling with delay, digital soft-start, secondary winding

control, low-dropout circuitry, internal frequency-com-

pensation networks, and automatic bootstrapping.

Up to 96% efficiency is achieved through synchronous

rectification and Maxim’s proprietary Idle Mode™ control

scheme. Efficiency is greater than 80% over a 1000:1

load-current range, which extends battery life in system-

suspend or standby mode. Excellent dynamic response

corrects output load transients caused by the latest

dynamic-clock CPUs within five 300kHz clock cycles.

Strong 1A on-board gate drivers ensure fast external

n-channel MOSFET switching.

These devices feature a logic-controlled and synchroniz-

able, fixed-frequency, pulse-width-modulation (PWM)

operating mode. This reduces noise and RF interference

in sensitive mobile communications and pen-entry appli-

cations. Asserting the SKIP pin enables fixed-frequency

mode for lowest noise under all load conditions.

The MAX1630A–MAX1635A include two PWM regulators,

adjustable from 2.5V to 5.5V with fixed 5.0V and 3.3V

modes. All these devices include secondary feedback

regulation, and the MAX1630A/MAX1632A/MAX1633A/

MAX1635A each contain 12V/120mA linear regulators.

The MAX1631A/MAX1634A include a secondary feed-

back input (SECFB), plus a control pin (STEER) that

selects which PWM (3.3V or 5V) receives the secondary

feedback signal. SECFB provides a method for adjusting

the secondary winding voltage regulation point with an

external resistor-divider, and is intended to aid in creating

auxiliary voltages other than fixed 12V.

The MAX1630A/MAX1631A/MAX1632A contain internal

output overvoltage and undervoltage protection features.

The MAX1630A family has improved RF immunity over

the MAX1630 family.

________________________Applications

Notebook and Subnotebook Computers

PDAs and Mobile Communicators

Desktop CPU Local DC-DC Converters

____________________________Features

♦96% Efficiency

♦+4.2V to +30V Input Range

♦2.5V to 5.5V Dual Adjustable Outputs

♦Selectable 3.3V and 5V Fixed or Adjustable

Outputs (Dual Mode™)

♦12V Linear Regulator

♦Adjustable Secondary Feedback

(MAX1631A/MAX1634A)

♦5V/50mA Linear Regulator Output

♦Precision 2.5V Reference Output

♦Programmable Power-Up Sequencing

♦Power-Good (RESET) Output

♦Output Overvoltage Protection

(MAX1630A/MAX1631A/MAX1632A)

♦Output Undervoltage Shutdown

(MAX1630A/MAX1631A/MAX1632A)

♦200kHz/300kHz Low-Noise, Fixed-Frequency

Operation

♦Low-Dropout, 99% Duty-Factor Operation

♦2.5mW Typical Quiescent Power (+12V Input,

Both SMPSs On)

♦4µA Typical Shutdown Current

♦28-Pin SSOP Package

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

________________________________________________________________ Maxim Integrated Products 1

LINEAR

12V

LINEAR

POWER-UP

SEQUENCE

POWER-

GOOD

3.3V

SMPS

RESETON/OFF

+5V (RTC)

+3.3V

INPUT

+5V

+12V

________________Functional Diagram

19-3518; Rev 1; 8/05

PART

MAX1630AEAI -40°C to +85°C

TEMP RANGE PIN-PACKAGE

28 SSOP

EVALUATION KIT

AVAILABLE

_______________Ordering Information

+Denotes lead-free package.

Ordering Information continued at end of data sheet.

Pin Configurations and Selector Guide appear at end of data

sheet.

Idle Mode and Dual Mode are trademarks of Maxim Integrated

Products, Inc.

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, SKIP = 0V, TA= TMIN to TMAX, unless otherwise noted.

Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

V+ to GND ..............................................................-0.3V to +36V

PGND to GND.....................................................................±0.3V

VL to GND ................................................................-0.3V to +6V

BST3, BST5 to GND ...............................................-0.3V to +36V

LX3 to BST3..............................................................-6V to +0.3V

LX5 to BST5..............................................................-6V to +0.3V

REF, SYNC, SEQ, STEER, SKIP, TIME/ON5,

SECFB, RESET to GND .......................................-0.3V to +6V

VDD to GND............................................................-0.3V to +20V

RUN/ON3, SHDN to GND.............................-0.3V to (V+ + 0.3V)

12OUT to GND ...........................................-0.3V to (VDD + 0.3V)

DL3, DL5 to PGND........................................-0.3V to (VL + 0.3V)

DH3 to LX3 ...............................................-0.3V to (BST3 + 0.3V)

DH5 to LX5 ...............................................-0.3V to (BST5 + 0.3V)

VL, REF Short to GND ................................................Momentary

12OUT Short to GND..................................................Continuous

REF Current...........................................................+5mA to -1mA

VL Current.........................................................................+50mA

12OUT Current ...............................................................+200mA

VDD Shunt Current............................................................+15mA

Operating Temperature Ranges

MAX163_ACAI ....................................................0°C to +70°C

MAX163_AEAI .................................................-40°C to +85°C

Storage Temperature Range .............................-65°C to +160°C

Continuous Power Dissipation (TA= +70°C)

SSOP (derate 9.52mW/°C above +70°C) ....................762mW

Lead Temperature (soldering, 10s) .................................+300°C

CONDITIONS

V4.2 30.0Input Voltage Range

UNITSMIN TYP MAXPARAMETER

Either SMPS

V+ = 4.2V to 30V, CSH3–CSL3 = 0V,

CSL3 tied to FB3

VREF 5.5

V2.42 2.5 2.58

3V Output Voltage in

Adjustable Mode

Output Voltage Adjust Range

Either SMPS, 5.2V < V+ < 30V %/V0.03

Either SMPS, 0V < CSH_- CSL_ < 80mV

Line Regulation

Dual Mode comparator

%-2

V0.5 1.1Adjustable-Mode Threshold Voltage

Load Regulation

SYNC = VL

From enable to 95% full current limit with respect to

fOSC (Note 1)

270 300 330

Clks512

SKIP = 0V, not tested

Soft-Start Ramp Time

mV10 25 40Idle Mode Threshold

SYNC = 0V kHz

170 200 230

Oscillator Frequency

V+ = 4.2V to 30V, 0mV < CSH3–CSL3 < 80mV,

FB3 = 0V V3.20 3.39 3.473V Output Voltage in Fixed Mode

V+ = 4.2V to 30V, CSH5–CSL5 = 0V,

CSL5 tied to FB5 V2.42 2.5 2.58

5V Output Voltage in

Adjustable Mode

V+ = 5.2V to 30V, 0mV < CSH–CSL5 < 80mV,

FB5 = 0V V4.85 5.13 5.255V Output Voltage in Fixed Mode

SYNC = VL 97 98

SYNC = 0V (Note 2) %

98 99

Maximum Duty Factor

CSH3–CSL3 or CSH5–CSL5 80 100 120

SKIP = VL or VDD < 13V or SECFB < 2.44V mV

-50 -100 -150

Current-Limit Threshold

MAIN SMPS CONTROLLERS

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, SKIP = 0V, TA= TMIN to TMAX, unless otherwise noted.

Typical values are at TA= +25°C.)

V+ = VL = 0V,

CSL3 = CSH3 = CSL5 = CSH5 = 5.5V µA0.01 10

Not tested

Current-Sense Input Leakage Current

Not tested

Rising edge, hysteresis = 1% (Note 3)

VDD < 13V or SECFB < 2.44V

V18 20

µs1

Falling edge (MAX1631A/MAX1634A)

DL Pulse Width

Falling edge (Note 3)

VDD Shunt Threshold

V2.44 2.60

V13 14

CONDITIONS

VDD Regulation Threshold

SECFB Regulation Threshold

VDD = 20V (Note 3)

VDD = 5V, off mode (Notes 3, 4) µA30VDD Leakage Current

mA10VDD Shunt Sink Current

ns200

ns200SYNC Input High Pulse Width

SYNC Input Low Pulse Width

13V < VDD < 18V, 0mA < ILOAD < 120mA V11.65 12.1 12.5012OUT Output Voltage

UNITSMIN TYP MAXPARAMETER

Not tested ns200SYNC Rise/Fall Time

kHz240 350SYNC Input Frequency Range

VDD = 18V, run mode, no 12OUT load

12OUT forced to 11V, VDD = 13V

µA50 100

mA15012OUT Current Limit

Quiescent VDD Current

Rising edge of CSL5, hysteresis = 1%

Falling edge, hysteresis = 1%

V4.2 4.5 4.7

V3.5 3.6 3.7

VL Undervoltage Lockout

Fault Threshold

VL Switchover Threshold

SHDN = V+, RUN/ON3 = TIME/ON5 = 0V,

5.3V < V+ < 30V, 0mA < ILOAD < 50mA V4.7 5.1VL Output Voltage

Falling edge V1.8 2.4

µA10REF Sink Current

REF Fault Lockout Voltage

V+ = 4V to 24V, SHDN = 0V

V+ = 4.2V to 5.5V, both SMPSs off,

includes current into SHDN

µA410

µA50 200

V+ Standby Supply Current

in Dropout

V+ Shutdown Supply Current

V+ = 5.5V to 30V, both SMPSs off,

includes current into SHDN

VL switched over to CSL5, 5V SMPS on

µA30 60

µA550V+ Operating Supply Current

V+ Standby Supply Current

0µA < ILOAD < 50µA

No external load (Note 5)

12.5

V2.45 2.5 2.55REF Output Voltage

2.5 4

Both SMPSs enabled, FB3 = FB5 = 0V,

CSL3 = CSH3 = 3.5V,

CSL5 = CSH5 = 5.3V

1.5 4

Quiescent Power Consumption

(Note 3)

MAX1631A/

MAX1634A

0mA < ILOAD < 5mA mV

100.0

REF Load Regulation

FLYBACK CONTROLLER

12V LINEAR REGULATOR (Note 3)

INTERNAL REGULATOR AND REFERENCE

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

4 _______________________________________________________________________________________

Note 1: Each of the four digital soft-start levels is tested for functionality; the steps are typically in 20mV increments.

Note 2: High duty-factor operation supports low input-to-output differential voltages, and is achieved at a lowered operating

frequency (see Overload and Dropout Operation section).

Note 3: MAX1630A/MAX1632A/MAX1633A/MAX1635A only.

Note 4: Off mode for the 12V linear regulator occurs when the SMPS that has flyback feedback (VDD) steered to it is disabled. In

situations where the main outputs are being held up by external keep-alive supplies, turning off the 12OUT regulator pre-

vents a leakage path from the output-referred flyback winding, through the rectifier, and into VDD.

Note 5: Since the reference uses VL as its supply, the reference’s V+ line-regulation error is insignificant.

ELECTRICAL CHARACTERISTICS (continued)

(V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, SKIP = 0V, TA= TMIN to TMAX, unless otherwise noted.

Typical values are at TA= +25°C.)

Typical hysteresis = +10°C

From each SMPS enabled, with respect to fOSC

°C150

Clks5000 6144 7000

With respect to unloaded output voltage

Output Undervoltage Lockout Time

Thermal Shutdown Threshold

With respect to fOSC

Falling edge, CSL_ driven 2%

below RESET trip threshold

Clks27,000 32,000 37,000

µs1.5

With respect to unloaded output voltage,

falling edge; typical hysteresis = 1%

RESET Propagation Delay

RESET Delay Time

%-7 -5.5 -4

CONDITIONS

RESET Trip Threshold

RESET, ISINK = 4mA

RUN/ON3, SKIP, TIME/ON5 (SEQ = REF),

SHDN, STEER, SYNC, SEQ; VPIN = 0V or 3.3V

V0.4

µA±1Input Leakage Current

Logic Output Low Voltage

CSL_ driven 2% above overvoltage trip threshold µs

FB3, FB5; SECFB = 2.6V

1.5Overvoltage-Fault Propagation Delay

nA150

With respect to unloaded output voltage %60 70 80

Feedback Input Leakage Current

Output Undervoltage Threshold

%4710Overvoltage Trip Threshold

RUN/ON3, SKIP, TIME/ON5 (SEQ = REF),

SHDN, STEER, SYNC

RUN/ON3, SKIP, TIME/ON5 (SEQ = REF),

SHDN, STEER, SYNC

V2.4

V0.6Logic Input Low Voltage

Logic Input High Voltage

UNITSMIN TYP MAXPARAMETER

High or low

DL3, DH3, DL5, DH5; forced to 2V

Ω1.5 7

A1Gate Driver Sink/Source Current

Gate Driver On-Resistance

RESET = 3.5V mA1Logic Output High Current

TIME/ON5 = 0V, SEQ = 0V or VL

SEQ = 0V or VL

µA2.5 3 3.5

V2.4 2.6TIME/ON5 Input Trip Level

TIME/ON5 Source Current

TIME/ON5; RUN/ON3 = 0V, SEQ = 0V or VL Ω15 80TIME/ON5 On-Resistance

FAULT DETECTION (MAX1630A/MAX1631A/MAX1632A)

INPUTS AND OUTPUTS

RESET

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

_______________________________________________________________________________________ 5

100

0.001 0.01 0.1 1 10

EFFICIENCY vs. 5V OUTPUT CURRENT

MAX1630A/35A toc01

5V OUTPUT CURRENT (A)

EFFICIENCY (%)

ON5 = 5V

ON3 = 0V

f = 300kHz

MAX1631A/MAX1634A

V+ = 6V

V+ = 15V

100

0.001 0.01 0.1 1 10

EFFICIENCY vs. 3.3V OUTPUT CURRENT

MAX1630A/35A toc02

3.3V OUTPUT CURRENT (A)

EFFICIENCY (%)

ON3 = ON5 = 5V

f = 300kHz

MAX1631A/MAX1634A

V+ = 6V

V+ = 15V

800

15 20

MAX1632A/MAX1635A

MAXIMUM 15V VDD OUTPUT

CURRENT vs. SUPPLY VOLTAGE

600

MAX1630A/35A toc03

SUPPLY VOLTAGE (V)

MAXIMUM OUTPUT CURRENT (mA)

200

400

VDD > 13V

5V REGULATING

5V LOAD = 0A

5V LOAD = 3A

500

15 20

MAX1630A/MAX1633A

MAXIMUM 15V VDD OUTPUT

CURRENT vs. SUPPLY VOLTAGE

400

MAX1630A/35A toc04

SUPPLY VOLTAGE (V)

MAXIMUM OUTPUT CURRENT (mA)

200

100

300

VDD > 13V

3.3V REGULATING

3.3V LOAD = 0A

3.3V LOAD = 3A

10,000

030

STANDBY INPUT CURRENT

vs. INPUT VOLTAGE

1000

MAX1630A/35A toc07

INPUT VOLTAGE (V)

INPUT CURRENT (μA)

510 25

100

ON3 = ON5 = 0V

NO LOAD

030

PWM MODE INPUT CURRENT

vs. INPUT VOLTAGE

MAX1630A/35A toc05

INPUT VOLTAGE (V)

INPUT CURRENT (mA)

510 25

ON3 = ON5 = 5V

SKIP = VL

NO LOAD

0.01

030

IDLE MODE INPUT CURRENT

vs. INPUT VOLTAGE

MAX1630A/35A toc06

INPUT VOLTAGE (V)

INPUT CURRENT (mA)

0.1

510 25

ON3 = ON5 = 5V

SKIP = 0V

NO LOAD

030

SHUTDOWN INPUT CURRENT

vs. INPUT VOLTAGE

MAX1630A/35A toc08

INPUT VOLTAGE (V)

INPUT CURRENT (μA)

510 25

SHDN = 0V

1000

0.001 0.1 101

MINIMUM VIN TO VOUT DIFFERENTIAL

vs. 5V OUTPUT CURRENT

100

MAX1630A/35A toc09

5V OUTPUT CURRENT (A)

MIN VIN TO VOUT DIFFERENTIAL (mV)

0.01

5V, 3A CIRCUIT

VOUT > 4.8V

f = 300kHz

__________________________________________Typical Operating Characteristics

(Circuit of Figure 1, 3A Table 1 components, TA = +25°C, unless otherwise noted.)

__________________________________________________________________________Pin Description

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

6 _______________________________________________________________________________________

____________________________________Typical Operating Characteristics (continued)

(Circuit of Figure 1, 3A Table 1 components, TA = +25°C, unless otherwise noted.)

1000

0.1

0.1 10 1000100

SWITCHING FREQUENCY

vs. LOAD CURRENT

100

MAX1630A/35A toc010

LOAD CURRENT (mA)

SWITCHING FREQUENCY (kHz)

+5V, VIN = 15V

+3.3V, VIN = 15V

+3.3V, VIN = 6V

+5V, VIN = 6V

5.00

4.90

50 60

VL REGULATOR OUTPUT VOLTAGE

vs. OUTPUT CURRENT

4.98

MAX1630A/35A toc11

OUTPUT CURRENT (mA)

VL OUTPUT VOLTAGE (V)

4.94

4.92

30 40

4.96

10 20

VIN = 15V

ON3 = ON5 = 0V

2.510

2.480

2.485

REF OUTPUT VOLTAGE

vs. OUTPUT CURRENT

2.505

MAX1630A/35A toc12

OUTPUT CURRENT (mA)

REF OUTPUT VOLTAGE (V)

2.495

2.490

2.500

VIN = 15V

ON3 = ON5 = 0V

2ms/div

STARTUP WAVEFORMS

RUN

5V/div

3.3V OUTPUT

2V/div

TIME

5V/div

5V OUTPUT

5V/div

SEQ = VL, 0.015μF CAPACITOR ON-TIME

MAX1630A/35A toc13

1CSH3 Current-Sense Input for the 3.3V SMPS. Current-limit level is 100mV referred to CSL3.

STEER

(MAX1631A/

MAX1634A)

Logic-Control Input for secondary feedback. Selects the PWM that uses a transformer and secondary

feedback signal (SECFB):

STEER = GND: 3.3V SMPS uses transformer

STEER = VL: 5V SMPS uses transformer

PIN NAME FUNCTION

2CSL3 Current-Sense Input. Also serves as the feedback input in fixed-output mode.

12OUT

(MAX1630A/

32A/33A/35A)

12V/120mA Linear Regulator Output. Input supply comes from VDD. Bypass 12OUT to GND with

1µF minimum.

3FB3

Feedback Input for the 3.3V SMPS; regulates at FB3 = REF (approx. 2.5V) in adjustable mode. FB3 is a

Dual Mode input that also selects the 3.3V fixed output voltage setting when tied to GND. Connect FB3

to a resistor-divider for adjustable-output mode.

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

_______________________________________________________________________________________ 7

_________________________________________________Pin Description (continued)

26 LX3 Switching Node (Inductor) Connection. Can swing 2V below ground without hazard.

27 DH3 Gate-Drive Output for the 3.3V, High-Side n-Channel Switch. DH3 is a floating driver output that swings

from LX3 to BST3, riding on the LX3 switching node voltage.

28 RUN/ON3 ON/OFF Control Input. See Power-Up Sequencing and ON/

OFF

Controls section.

24 DL3 Gate-Drive Output for the Low-Side Synchronous-Rectifier MOSFET. Swings 0V to VL.

25 BST3 Boost Capacitor Connection for High-Side Gate Drive (0.1µF)

SECFB

(MAX1631A/

MAX1634A)

Secondary Winding Feedback Input. Normally connected to a resistor-divider from an auxiliary output.

SECFB regulates at VSECFB = 2.5V (see Secondary Feedback Regulation Loop section). Tie to VL if not

used.

VDD

(MAX1630A/

32A/33A/35A)

Supply Voltage Input for the 12OUT Linear Regulator. Also connects to an internal resistor-divider for

secondary winding feedback, and to an 18V overvoltage shunt regulator clamp.

21 VL

5V Internal Linear-Regulator Output. VL is also the supply voltage rail for the chip. After the 5V SMPS

output has reached +4.5V (typical), VL automatically switches to the output voltage through CSL5 for

bootstrapping. Bypass to GND with 4.7µF. VL supplies up to 25mA for external loads.

22 V+ Battery Voltage Input, +4.2V to +30V. Bypass V+ to PGND close to the IC with a 0.22µF capacitor.

Connects to a linear regulator that powers VL.

23 SHDN Shutdown Control Input, Active Low. Logic threshold is set at approximately 1V. For automatic startup,

connect SHDN to V+ through a 220kΩresistor and bypass SHDN to GND with a 0.01µF capacitor.

13 CSL5 Current-Sense Input for the 5V SMPS. Also serves as the feedback input in fixed-output mode, and as

the bootstrap supply input when the voltage on CSL5/VL is > 4.5V.

14 CSH5 Current-Sense Input for the 5V SMPS. Current-limit level is 100mV referred to CSL5.

17 LX5 Switching Node (Inductor) Connection. Can swing 2V below ground without hazard.

18 BST5 Boost Capacitor Connection for High-Side Gate Drive (0.1µF)

19 DL5 Gate-Drive Output for the Low-Side Synchronous-Rectifier MOSFET. Swings 0V to VL.

20 PGND Power Ground

15 SEQ

Pin-Strap Input that Selects the SMPS Power-Up Sequence:

SEQ = GND: 5V before 3.3V, RESET output determined by both outputs

SEQ = REF: Separate ON3/ON5 controls, RESET output determined by 3.3V output

SEQ = VL: 3.3V before 5V, RESET output determined by both outputs

16 DH5 Gate-Drive Output for the 5V, High-Side n-Channel Switch. DH5 is a floating driver output that swings

from LX5 to BST5, riding on the LX5 switching node voltage.

12 FB5

Feedback Input for the 5V SMPS; regulates at FB5 = REF (approximately 2.5V) in adjustable mode. FB5

is a Dual Mode input that also selects the 5V fixed output voltage setting when tied to GND. Connect

FB5 to a resistor-divider for adjustable-output mode.

8GND Low-Noise Analog Ground and Feedback Reference Point

9REF 2.5V Reference Voltage Output. Bypass to GND with 1µF minimum.

10 SKIP Logic-Control Input that Disables Idle Mode when High. Connect to GND for normal use.

11 RESET Active-Low Timed Reset Output. RESET swings GND to VL. Goes high after a fixed 32,000 clock-cycle

delay following power-up.

6SYNC Oscillator Synchronization and Frequency Select. Tie to VL for 300kHz operation; tie to GND for 200kHz

operation. Can be driven at 240kHz to 350kHz for external synchronization.

7TIME/ON5 Dual-Purpose Timing Capacitor Pin and ON/OFF Control Input. See Power-Up Sequencing and

ON/

OFF

Controls section.

NAME FUNCTIONPIN

_______Standard Application Circuit

The basic MAX1631A/MAX1634A dual-output 3.3V/5V

buck converter (Figure 1) is easily adapted to meet a

wide range of applications with inputs up to 28V by

substituting components from Table 1. These circuits

represent a good set of tradeoffs between cost, size,

and efficiency, while staying within the worst-case

specification limits for stress-related parameters, such

as capacitor ripple current. Do not change the frequen-

cy of these circuits without first recalculating compo-

nent values (particularly inductance value at maximum

battery voltage). Adding a Schottky rectifier across

each synchronous rectifier improves the efficiency of

these circuits by approximately 1%, but this rectifier is

otherwise not needed because the MOSFETs required

for these circuits typically incorporate a high-speed sili-

con diode from drain to source. Use a Schottky rectifier

rated at a DC current equal to at least 1/3 of the load

current.

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

8 _______________________________________________________________________________________

MAX1631A

MAX1634A

V+ SHDN VLSECFB

INPUT ON/OFF

GND

REF SEQ

1μF

+2.5V ALWAYS ON

*1A SCHOTTKY DIODE REQUIRED

FOR THE MAX1631A (SEE OUTPUT

OVERVOLTAGE PROTECTION SECTION).

+5V ALWAYS ON

5V ON/OFF

3.3V ON/OFF

0.1μF

L2 R2 +3.3V OUTPUT

4.7μF

0.1μF

4.7μF

0.1μF

10Ω

0.1μF

DL3

CSH3

CSL3

FB3

RESET RESET OUTPUT

SKIP

STEER

+5V OUTPUT

C1 DL5

LX5

DH5

BST5 BST3

SYNC

DH3

LX3

PGND

CSL5

CSH5

RUN/ON3

TIME/ON5

FB5

Figure 1. Standard 3.3V/5V Application Circuit (MAX1631A/MAX1634A)

MAX1630AA–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

_______________________________________________________________________________________ 9

Input Range

Application

Table 1. Component Selection for Standard 3.3V/5V Application

Table 2. Component Suppliers

4.75V to 18V

PDA

4.75V to 28V

Notebook

4.75V to 24V

Workstation

Frequency 300kHz

1/2 IR IRF7301;

1/2 Siliconix Si9925DQ; or

1/2 Motorola MMDF3N03HD or

MMDF4N01HD (10V max)

300kHz

IR IRF7403 or IRF7401 (18V

max); Siliconix Si4412DY; or

Motorola MMSF5N03HD or

MMSF5N02HD (18V max)

200kHz

IR IRF7413 or

Siliconix Si4410DY

Q1, Q3 High-Side

MOSFETs

Q2, Q4 Low-Side

MOSFETs

1/2 IR IRF7301;

1/2 Siliconix Si9925DQ; or

1/2 Motorola MMDF3N03HD or

MMDF4N01HD (10V max)

10µF, 30V Sanyo OS-CON;

22µF, 35V AVX TPS; or

Sprague 594D

IR IRF7403 or IRF7401 (18V

max); Siliconix Si4412DY; or

Motorola MMSF5N03HD or

MMSF5N02HD (18V max)

2 x 10µF, 30V Sanyo OS-CON;

2 x 22µF, 35V AVX TPS; or

Sprague 594D

IR IRF7413 or

Siliconix Si4410DY

3 x 10µF, 30V Sanyo OS-CON;

4 x 22µF, 35V AVX TPS; or

Sprague 595D

C1, C2 Output Capacitors 220µF, 10V AVX TPS or

Sprague 595D

0.033ΩIRC LR2010-01-R033 or

Dale WSL2010-R033-F

2 x 220µF, 10V AVX TPS or

Sprague 595D

0.02ΩIRC LR2010-01-R020 or

Dale WSL2010-R020-F

4 x 220µF, 10V AVX TPS or

Sprague 595D

0.012ΩDale WSL2512-R012-FR1, R2 Resistors

C3 Input Capacitor

15µH, 2.4A Ferrite

Coilcraft DO3316P-153 or

Sumida CDRH125-150

10µH, 4A Ferrite

Coilcraft DO3316P-103 or

Sumida CDRH125-100

4.7µH, 5.5A Ferrite

Coilcraft DO3316-472 or

5.2µH, 6.5A Ferrite Sumida

CDRH127-5R2MC

L1, L2 Inductors

AVX (1) 803-626-3123

(1) 516-435-1824

FACTORY FAX

(COUNTRY CODE)

803-946-0690

516-435-1110

USA PHONE

Coilcraft (1) 847-639-1469 847-639-6400

Central

Semiconductor

COMPANY

Coiltronics (1) 561-241-9339

(1) 605-665-1627

561-241-7876

605-668-4131

International

Rectifier (IR) (1) 310-322-3332 310-322-3331

Dale

IRC (1) 512-992-3377

(1) 714-960-6492

512-992-7900

714-969-2491Matsuo

Motorola (1) 602-994-6430

(81) 3-3494-7414

FACTORY FAX

(COUNTRY CODE)

602-303-5454

805-867-2555*

USA PHONE

Siliconix (1) 408-970-3950

(1) 603-224-1430

Sanyo (81) 7-2070-1174

408-988-8000

619-661-6835

603-224-1961

Sumida (81) 3-3607-5144 847-956-0666

Sprague

TDK (1) 847-390-4428

(1) 702-831-3521

847-390-4373

702-831-0140

Transpower

Technologies

NIEC

COMPANY

Murata-Erie (1) 814-238-0490 814-237-1431

*Distributor

LOAD CURRENT

COMPONENT

MAX1630AA–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

10 ______________________________________________________________________________________

_______________Detailed Description

The MAX1630A is a dual, BiCMOS, switch-mode power-

supply controller designed primarily for buck-topology

regulators in battery-powered applications where high effi-

ciency and low quiescent supply current are critical. Light-

load efficiency is enhanced by automatic Idle Mode

operation, a variable-frequency pulse-skipping mode that

reduces transition and gate-charge losses. Each step-

down, power-switching circuit consists of two n-channel

MOSFETs, a rectifier, and an LC output filter. The output

voltage is the average AC voltage at the switching node,

which is regulated by changing the duty cycle of the

MOSFET switches. The gate-drive signal to the n-channel

high-side MOSFET must exceed the battery voltage, and

is provided by a flying-capacitor boost circuit that uses a

100nF capacitor connected to BST_.

Devices in the MAX1630A family contain 10 major circuit

blocks (Figure 2).

The two PWM controllers each consist of a Dual Mode

feedback network and multiplexer, a multi-input PWM

comparator, high-side and low-side gate drivers, and

logic. The MAX1630A/MAX1631A/MAX1632A contain

fault-protection circuits that monitor the main PWM out-

puts for undervoltage and overvoltage. A power-on

sequence block controls the power-up timing of the

main PWMs and determines whether one or both of the

outputs are monitored for undervoltage faults. The

MAX1630A/MAX1632A/MAX1633A/MAX1635A include

a secondary feedback network and 12V linear regulator

to generate a 12V output from a coupled-inductor fly-

back winding. The MAX1631A/MAX1634A have an

SECFB instead, which allows a quasi-regulated,

adjustable-output, coupled-inductor flyback winding to

be attached to either the 3.3V or the 5V main inductor.

Bias generator blocks include the 5V IC internal rail (VL)

linear regulator, 2.5V precision reference, and automatic

bootstrap switchover circuit. The PWMs share a com-

mon 200kHz/300kHz synchronizable oscillator.

These internal IC blocks are not powered directly from

the battery. Instead, the 5V VL linear regulator steps

down the battery voltage to supply both VL and the

gate drivers. The synchronous-switch gate drivers are

directly powered from VL, while the high-side switch

gate drivers are indirectly powered from VL through an

external diode-capacitor boost circuit. An automatic

bootstrap circuit turns off the +5V linear regulator and

powers the IC from the 5V PWM output voltage if the

output is above 4.5V.

PWM Controller Block

The two PWM controllers are nearly identical. The only

differences are fixed output settings (3.3V vs. 5V), the

VL/CSL5 bootstrap switch connected to the +5V PWM,

and SECFB. The heart of each current-mode PWM con-

troller is a multi-input, open-loop comparator that sums

three signals: the output voltage error signal with

respect to the reference voltage, the current-sense sig-

nal, and the slope compensation ramp (Figure 3). The

PWM controller is a direct-summing type, lacking a tra-

ditional error amplifier and the phase shift associated

with it. This direct-summing configuration approaches

ideal cycle-by-cycle control over the output voltage.

When SKIP = low, Idle Mode circuitry automatically

optimizes efficiency throughout the load current range.

Idle Mode dramatically improves light-load efficiency

by reducing the effective frequency, which reduces

switching losses. It keeps the peak inductor current

above 25% of the full current limit in an active cycle,

allowing subsequent cycles to be skipped. Idle Mode

transitions seamlessly to fixed-frequency PWM opera-

tion as load current increases.

With SKIP = high, the controller always operates in

fixed-frequency PWM mode for lowest noise. Each

pulse from the oscillator sets the main PWM latch that

turns on the high-side switch for a period determined

by the duty factor (approximately VOUT/VIN). As the

high-side switch turns off, the synchronous rectifier

latch sets; 60ns later, the low-side switch turns on. The

low-side switch stays on until the beginning of the next

clock cycle.

In PWM mode, the controller operates as a fixed-

frequency current-mode controller where the duty ratio

is set by the input/output voltage ratio. The current-

mode feedback system regulates the peak inductor

Table 3. SKIP PWM Table

Low Light

LOAD

CURRENT

Pulse-skipping, supply cur-

rent = 250µA at VIN = 12V,

discontinuous inductor

current

DESCRIPTION

Low Heavy Constant-frequency PWM,

continuous inductor current

SKIP

Idle

MODE

PWM

High Light PWM Constant-frequency PWM,

continuous inductor current

PWMHigh Heavy Constant-frequency PWM,

continuous inductor current

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

______________________________________________________________________________________ 11

LPF

60kHz

REF

1.75V

2.68V

2.388V

4.5V

REF

2.5V

REF

200kHz

300kHz

OSC

PWM

LOGIC

LINEAR

REG

BST3

DH3

LX3

DL3

+3.3V

ON/OFF

INPUT

+5V ALWAYS ON

CSL5

SHDN V+ SYNC

12V

LINEAR

REG

+12V

13V BST5 RAW +15V

DH5

DL5

PGND

CSH5

CSL5

CSH3

CSL3

FB5

RESET

SEQ

2.6V

0.6V 0.6V

GND RUN/ON3

TIME/ON5

REF

LX5 +5V

12OUT

VDD

SECFB

3.3V

PWM

LOGIC

REF

OUTPUTS

LPF

60kHz

TIMER

POWER-ON

SEQUENCE

LOGIC

FB3

MAX1632A

OV/UV

FAULT

Figure 2. MAX1632A Block Diagram

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

12 ______________________________________________________________________________________

SHOOT-

THROUGH

CONTROL

30mV

LEVEL

SHIFT

1μs

SINGLE-SHOT

MAIN PWM

COMPARATOR

OSC

LEVEL

SHIFT

CURRENT

LIMIT

SYNCHRONOUS

RECTIFIER CONTROL

REF

SHDN

-100mV

CSH_

CSL_

FROM

FEEDBACK

DIVIDER

BST_

DH_

LX_

DL_

PGND

SLOPE COMP

SKIP

REF

SECFB

COUNTER

DAC

SOFT-START

Figure 3. PWM Controller Detailed Block Diagram

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

______________________________________________________________________________________ 13

Figure 4. Main PWM Comparator Block Diagram

FB_

REF

CSH_

CSL_

SLOPE COMPENSATION

R1 R2

TO PWM

LOGIC

OUTPUT DRIVER

UNCOMPENSATED

HIGH-SPEED

LEVEL TRANSLATOR

AND BUFFER

I2 I3 VBIAS

current value as a function of the output-voltage error

signal. In continuous-conduction mode, the average

inductor current is nearly the same as the peak current,

so the circuit acts as a switch-mode transconductance

amplifier. This pushes the second output LC filter pole,

normally found in a duty-factor-controlled (voltage-

mode) PWM, to a higher frequency. To preserve inner-

loop stability and eliminate regenerative inductor

current “staircasing,” a slope compensation ramp is

summed into the main PWM comparator to make the

apparent duty factor less than 50%.

The MAX1630A family uses a relatively low loop gain,

allowing the use of lower cost output capacitors. The rel-

ative gains of the voltage-sense and current-sense

inputs are weighted by the values of current sources

that bias three differential input stages in the main PWM

comparator (Figure 4). The relative gain of the voltage

comparator to the current comparator is internally fixed

at K = 2:1. The low loop gain results in the 2% typical

load-regulation error. The low value of loop gain helps

reduce output filter capacitor size and cost by shifting

the unity-gain crossover frequency to a lower level.

The output filter capacitors (Figure 1, C1 and C2) set a

dominant pole in the feedback loop that must roll off the

loop gain to unity before encountering the zero intro-

duced by the output capacitor’s parasitic resistance

(ESR) (see the Design Procedure section). A 60kHz

pole-zero cancellation filter provides additional rolloff

above the unity-gain crossover. This internal 60kHz low-

pass compensation filter cancels the zero due to filter

capacitor ESR. The 60kHz filter is included in the loop in

both fixed-output and adjustable-output modes.

Synchronous Rectifier Driver (DL)

Synchronous rectification reduces conduction losses in

the rectifier by shunting the normal Schottky catch diode

with a low-resistance MOSFET switch. Also, the synchro-

nous rectifier ensures proper startup of the boost gate-

driver circuit. If the synchronous power MOSFETs are

omitted for cost or other reasons, replace them with a

small-signal MOSFET, such as a 2N7002.

If the circuit is operating in continuous-conduction mode,

the DL drive waveform is the complement of the DH high-

side drive waveform (with controlled dead time to prevent

cross-conduction or “shoot-through”). In discontinuous

(light-load) mode, the synchronous switch is turned off as

the inductor current falls through zero. The synchronous

rectifier works under all operating conditions, including

Idle Mode. The SECFB signal further controls the syn-

chronous switch timing to improve multiple-output cross-

regulation (see the Secondary Feedback Regulation

Loop section).

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

14 ______________________________________________________________________________________

Internal VL and REF Supplies

An internal regulator produces the +5V supply (VL) that

powers the PWM controller, logic, reference, and other

blocks within the IC. This 5V low-dropout linear regula-

tor supplies up to 25mA for external loads, with a

reserve of 25mA for supplying gate-drive power.

Bypass VL to GND with 4.7µF.

Important: Ensure that VL does not exceed 6V.

Measure VL with the main output fully loaded. If it is

pumped above 5.5V, either excessive boost diode

capacitance or excessive ripple at V+ is the probable

cause. Use only small-signal diodes for the boost cir-

cuit (10mA to 100mA Schottky or 1N4148 are pre-

ferred), and bypass V+ to PGND with 4.7µF directly at

the package pins.

The 2.5V reference (REF) is accurate to ±2% over tem-

perature, making REF useful as a precision system ref-

erence. Bypass REF to GND with 1µF minimum. REF

can supply up to 5mA for external loads. (Bypass REF

with a minimum 1µF/mA reference load current.)

However, if extremely accurate specifications for both

the main output voltages and REF are essential, avoid

loading REF more than 100µA. Loading REF reduces

the main output voltage slightly, because of the refer-

ence load-regulation error.

When the 5V main output voltage is above 4.5V, an

internal p-channel MOSFET switch connects CSL5 to

VL, while simultaneously shutting down the VL linear

regulator. This action bootstraps the IC, powering the

internal circuitry from the output voltage, rather than

through a linear regulator from the battery. Boot-

strapping reduces power dissipation due to gate

charge and quiescent losses by providing that power

from a 90%-efficient switch-mode source, rather than

from a much less efficient linear regulator.

Boost High-Side Gate-Drive Supply

(BST3 and BST5)

Gate-drive voltage for the high-side n-channel switches

is generated by a flying-capacitor boost circuit

(Figure 2). The capacitor between BST_ and LX_ is

alternately charged from the VL supply and placed par-

allel to the high-side MOSFET’s gate-source terminals.

On startup, the synchronous rectifier (low-side

MOSFET) forces LX_ to 0V and charges the boost

capacitors to 5V. On the second half-cycle, the SMPS

turns on the high-side MOSFET by closing an internal

switch between BST_ and DH_. This provides the nec-

essary enhancement voltage to turn on the high-side

switch, an action that “boosts” the 5V gate-drive signal

above the battery voltage.

Ringing at the high-side MOSFET gate (DH3 and DH5)

in discontinuous-conduction mode (light loads) is a nat-

ural operating condition. It is caused by residual ener-

gy in the tank circuit, formed by the inductor and stray

capacitance at the switching node, LX. The gate-drive

negative rail is referred to LX, so any ringing there is

directly coupled to the gate-drive output.

Current-Limiting and Current-Sense

Inputs (CSH and CSL)

The current-limit circuit resets the main PWM latch and

turns off the high-side MOSFET switch whenever the

voltage difference between CSH and CSL exceeds

100mV. This limiting is effective for both current flow

directions, putting the threshold limit at ±100mV. The

tolerance on the positive current limit is ±20%, so the

external low-value sense resistor (R1) must be sized for

80mV/IPEAK, where IPEAK is the required peak inductor

current to support the full load current, while compo-

nents must be designed to withstand continuous cur-

rent stresses of 120mV/R1.

For breadboarding or for very-high-current applications,

it may be useful to wire the current-sense inputs with a

twisted pair, rather than PC traces. (This twisted pair

need not be anything special; two pieces of wire-wrap

wire twisted together are sufficient.) This reduces the

possible noise picked up at CSH_ and CSL_, which can

cause unstable switching and reduced output current.

The CSL5 input also serves as the IC’s bootstrap sup-

ply input. Whenever VCSL5 > 4.5V, an internal switch

connects CSL5 to VL.

Oscillator Frequency and

Synchronization (SYNC)

The SYNC input controls the oscillator frequency. Low

selects 200kHz; high selects 300kHz. SYNC can also

be used to synchronize with an external 5V CMOS or

TTL clock generator. SYNC has a guaranteed 240kHz

to 350kHz capture range. A high-to-low transition on

SYNC initiates a new cycle.

300kHz operation optimizes the application circuit for

component size and cost. 200kHz operation provides

increased efficiency, lower dropout, and improved

load-transient response at low input-output voltage dif-

ferences (see the Low-Voltage Operation section).

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

______________________________________________________________________________________ 15

Table 4. Operating Modes

SEQ RUN/ON3 DESCRIPTION

XLow XAll circuit blocks turned off. Supply current = 4µA.

SHDN TIME/ON5

MODE

Shutdown

Low StandbyLowHigh Ref Both SMPSs off. Supply current = 30µA.

Low RunHigh

High RunLowHigh Ref 5V SMPS enabled/3.3V off.

High Ref 3.3V SMPS enabled/5V off.

High RunHigh

Timing capacitor StandbyLowHigh GND Both SMPSs off. Supply current = 30µA.

Timing capacitor RunHigh

Timing capacitor StandbyLowHigh VL Both SMPSs off. Supply current = 30µA.

High

High Ref Both SMPSs enabled.

GND Both SMPSs enabled. 5V enabled before 3.3V.

Timing capacitor RunHighHigh VL Both SMPSs enabled. 3.3V enabled before 5V.

X = Don’t care.

Shutdown Mode

Holding SHDN low puts the IC into its 4µA shutdown

mode. SHDN is logic input with a threshold of about 1V

(the VTH of an internal n-channel MOSFET). For auto-

matic startup, bypass SHDN to GND with a 0.01µF

capacitor and connect it to V+ through a 220kΩresistor.

Power-Up Sequencing

and ON/

OFF

Controls

Startup is controlled by RUN/ON3 and TIME/ON5 in

conjunction with SEQ. With SEQ tied to REF, the two

control inputs act as separate ON/OFF controls for

each supply. With SEQ tied to VL or GND, RUN/ON3

becomes the master ON/OFF control input and

TIME/ON5 becomes a timing pin, with the delay

between the two supplies determined by an external

capacitor. The delay is approximately 800µs/nF. The

+3.3V supply powers up first if SEQ is tied to VL, and

the +5V supply is first if SEQ is tied to GND. When driv-

ing TIME/ON5 as a control input with external logic,

always place a resistor (>1kΩ) in series with the input.

This prevents possible crowbar current due to the inter-

nal discharge pulldown transistor, which turns on in

standby mode and momentarily at the first power-up or

in shutdown mode.

RESET

Power-Good Voltage Monitor

The power-good monitor generates a system RESET sig-

nal. At first power-up, RESET is held low until both the

3.3V and 5V SMPS outputs are in regulation. At this point,

an internal timer begins counting oscillator pulses, and

RESET continues to be held low until 32,000 cycles have

elapsed. After this timeout period (107ms at 300kHz or

160ms at 200kHz), RESET is actively pulled up to VL. If

SEQ is tied to REF (for separate ON3/ON5 controls), only

the 3.3V SMPS is monitored—the 5V SMPS is ignored.

Output Undervoltage Shutdown Protection

(MAX1630A/MAX1631A/MAX1632A)

The output undervoltage lockout circuit is similar to

foldback current limiting, but employs a timer rather

than a variable current limit. Each SMPS has an under-

voltage protection circuit that is activated 6144 clock

cycles after the SMPS is enabled. If either SMPS output

is under 70% of the nominal value, both SMPSs are

latched off and their outputs are clamped to ground by

the synchronous rectifier MOSFETs (see the Output

Overvoltage Protection section). They do not restart

until SHDN or RUN/ON3 is toggled, or until V+ power is

cycled below 1V. Note that undervoltage protection can

make prototype troubleshooting difficult, since you

have only 20ms or 30ms to figure out what might be

wrong with the circuit before both SMPSs are latched

off. In extreme cases, it may be useful to substitute the

MAX1633A/MAX1634A/MAX1635A into the prototype

breadboard until the prototype is working properly.

Output Overvoltage Protection

(MAX1630A/MAX1631A/MAX1632A)

Both SMPS outputs are monitored for overvoltage. If

either output is more than 7% above the nominal regu-

lation point, both low-side gate drivers (DL_) are

latched high until SHDN or RUN/ON3 is toggled, or until

V+ power is cycled below 1V. This action turns on the

synchronous rectifiers with 100% duty, in turn rapidly

discharging the output capacitors and forcing both

SMPS outputs to ground. The DL outputs are also kept

high whenever the corresponding SMPS is disabled,

and in shutdown if VL is sustained.

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

16 ______________________________________________________________________________________

Discharging the output capacitor through the main

inductor causes the output to momentarily go below

GND. Clamp this negative pulse with a back-biased 1A

Schottky diode across the output capacitor (Figure 1).

To ensure overvoltage protection on initial power-up,

connect signal diodes from both output voltages to VL

(cathodes to VL) to eliminate the VL power-up delay.

This circuitry protects the load from accidental overvolt-

age caused by a short-circuit across the high-side

power MOSFETs. This scheme relies on the presence

of a fuse, in series with the battery, which is blown by

the resulting crowbar current. Note that the overvoltage

circuitry will interfere with external keep-alive supplies

that hold up the outputs (such as lithium backup or hot-

swap power supplies); in such cases, the MAX1633A,

MAX1634A, or MAX1635A should be used.

Low-Noise Operation (PWM Mode)

PWM mode (SKIP = high) minimizes RF and audio

interference in noise-sensitive applications (such as hi-

fi multimedia-equipped systems), cellular phones, RF

communicating computers, and electromagnetic pen-

entry systems. See the summary of operating modes in

Table 2. SKIP can be driven from an external logic

signal.

Interference due to switching noise is reduced in PWM

mode by ensuring a constant switching frequency, thus

concentrating the emissions at a known frequency out-

side the system audio or IF bands. Choose an oscillator

frequency for which switching frequency harmonics do

not overlap a sensitive frequency band. If necessary,

synchronize the oscillator to a tight-tolerance external

clock generator. To extend the output-voltage-regula-

tion range, constant operating frequency is not main-

tained under overload or dropout conditions (see the

Overload and Dropout Operation section.)

PWM mode (SKIP = high) forces two changes upon the

PWM controllers. First, it disables the minimum-current

comparator, ensuring fixed-frequency operation.

Second, it changes the detection threshold for reverse-

current limit from 0mV to -100mV, allowing the inductor

current to reverse at light loads. This results in fixed-

frequency operation and continuous inductor-current

flow. This eliminates discontinuous-mode inductor ring-

ing and improves cross regulation of transformer-

coupled multiple-output supplies, particularly in circuits

that do not use additional secondary regulation through

SECFB or VDD.

In most applications, tie SKIP to GND to minimize qui-

escent supply current. VL supply current with SKIP high

is typically 20mA, depending on external MOSFET gate

capacitance and switching losses.

Internal Digital Soft-Start Circuit

Soft-start allows a gradual increase of the internal cur-

rent-limit level at startup to reduce input surge currents.

Both SMPSs contain internal digital soft-start circuits,

each controlled by a counter, a digital-to-analog con-

verter (DAC), and a current-limit comparator. In shut-

down or standby mode, the soft-start counter is reset to

zero. When an SMPS is enabled, its counter starts

counting oscillator pulses, and the DAC begins incre-

menting the comparison voltage applied to the current-

limit comparator. The DAC output increases from 0mV to

100mV in five equal steps as the count increases to 512

clocks. As a result, the main output capacitor charges

up relatively slowly. The exact time of the output rise

depends on output capacitance and load current, and

is typically 1ms with a 300kHz oscillator.

Dropout Operation

Dropout (low input-output differential operation) is

enhanced by stretching the clock pulse width to

increase the maximum duty factor. The algorithm fol-

lows: If the output voltage (VOUT) drops out of regula-

tion without the current limit having been reached, the

SMPS skips an off-time period (extending the on-time).

At the end of the cycle, if the output is still out of regula-

tion, the SMPS skips another off-time period. This

action can continue until three off-time periods are

skipped, effectively dividing the clock frequency by as

much as four.

The typical PWM minimum off-time is 300ns, regardless

of the operating frequency. Lowering the operating fre-

quency raises the maximum duty factor above 98%.

Adjustable-Output Feedback

(Dual Mode FB)

Fixed, preset output voltages are selected when FB_ is

connected to ground. Adjusting the main output volt-

age with external resistors is simple for any of the

MAX1630A family ICs, through resistor-dividers con-

nected to FB3 and FB5 (Figure 2). Calculate the output

voltage with the following formula:

VOUT = VREF (1 + R1 / R2)

where VREF = 2.5V nominal.

The nominal output should be set approximately 1% or

2% high to make up for the MAX1630A’s -2% typical

load-regulation error. For example, if designing for a

3.0V output, use a resistor ratio that results in a nominal

output voltage of 3.05V. This slight offsetting gives the

best possible accuracy. Recommended normal values

for R2 range from 5kΩto 100kΩ. To achieve a 2.5V

nominal output, connect FB_ directly to CSL_.

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

______________________________________________________________________________________ 17

Remote output-voltage sensing, while not possible in

fixed-output mode due to the combined nature of the

voltage-sense and current-sense inputs (CSL3 and

CSL5), is easy to do in adjustable mode by using the top

of the external resistor-divider as the remote sense point.

When using adjustable mode, it is a good idea to

always set the “3.3V output” to a lower voltage than the

“5V output.” The 3.3V output must always be less than

VL, so that the voltage on CSH3 and CSL3 is within the

common-mode range of the current-sense inputs. While

VL is nominally 5V, it can be as low as 4.7V when lin-

early regulating, and as low as 4.2V when automatically

bootstrapped to CSH5.

Secondary Feedback Regulation Loop

(SECFB or VDD)

A flyback-winding control loop regulates a secondary

winding output, improving cross-regulation when the

primary output is lightly loaded or when there is a low

input-output differential voltage. If VDD or SECFB falls

below its regulation threshold, the low-side switch is

turned on for an extra 1µs. This reverses the inductor

(primary) current, pulling current from the output filter

capacitor and causing the flyback transformer to oper-

ate in forward mode. The low impedance presented by

the transformer secondary in forward mode dumps cur-

rent into the secondary output, charging up the sec-

ondary capacitor and bringing VDD or SECFB back into

regulation. The secondary feedback loop does not

improve secondary output accuracy in normal flyback

mode, where the main (primary) output is heavily

loaded. In this condition, secondary output accuracy is

determined by the secondary rectifier drop, transformer

turns ratio, and accuracy of the main output voltage. A

linear postregulator may still be needed to meet strict

output-accuracy specifications.

Devices with a 12OUT linear regulator have a VDD pin

that regulates at a fixed 13.5V, set by an internal

resistor-divider. The MAX1631A/MAX1634A have an

adjustable secondary output voltage set by an external-

resistor-divider on SECFB (Figure 5). Ordinarily, the

secondary regulation point is set 5% to 10% below the

voltage normally produced by the flyback effect. For

example, if the output voltage as determined by turns

ratio is 15V, set the feedback resistor ratio to produce

13.5V. Otherwise, the SECFB one-shot might be trig-

gered unintentionally, unnecessarily increasing supply

current and output noise.

12V Linear Regulator Output

(MAX1630A/MAX1632A/

MAX1633A/MAX1635A)

The MAX1630A/MAX1632A/MAX1633A/MAX1635A

include a 12V linear regulator output capable of deliver-

ing 120mA of output current. Typically, greater current is

available at the expense of output accuracy. If an accu-

MAX1631A

MAX1634A

POSITIVE

SECONDARY

OUTPUT

MAIN

OUTPUT

DH_

V+

SECFB

2.5V REF

1-SHOT

TRIG

DL_

WHERE VREF (NOMINAL) = 2.5V+VTRIP = VREF (1 + –––)

Figure 5. Adjusting the Secondary Output Voltage with SECFB

MAX1630A

MAX1632A

MAX1633A

MAX1635A

VDD OUTPUT

+12V OUTPUT

200mA

MAIN

OUTPUT

2N3906

0.1μF

2.2μF

10μF

10Ω

V+

VDD

12OUT

DH_

DL_

Figure 6. Increased 12V Linear Regulator Output Current

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

18 ______________________________________________________________________________________

Kool-Mµ is a registered trademark of Magnetics Div., Spang & Co.

rate output of more than 120mA is needed, an external

pass transistor can be added. Figure 6’s circuit delivers

more than 200mA. Total output current is constrained

by the V+ input voltage and the transformer primary

load (see Maximum 15V VDD Output Current vs.

Supply Voltage graphs in the Typical Operating

Characteristics).

__________________Design Procedure

The three predesigned 3V/5V standard application cir-

cuits (Figure 1 and Table 1) contain ready-to-use solu-

tions for common application needs. Also, two standard

flyback transformer circuits support the 12OUT linear

regulator in the Applications Information section. Use

the following design procedure to optimize these basic

schematics for different voltage or current require-

ments. Before beginning a design, firmly establish the

following:

• Maximum input (battery) voltage, VIN(MAX). This

value should include the worst-case conditions,

such as no-load operation when a battery charger

or AC adapter is connected but no battery is

installed. VIN(MAX) must not exceed 30V.

• Minimum input (battery) voltage, VIN(MIN). This

should be taken at full load under the lowest battery

conditions. If VIN(MIN) is less than 4.2V, use an

external circuit to externally hold VL above the VL

undervoltage lockout threshold. If the minimum

input-output difference is less than 1.5V, the filter

capacitance required to maintain good AC load

regulation increases (see Low-Voltage Operation

section).

Inductor Value

The exact inductor value is not critical and can be

freely adjusted to make trade-offs between size, cost,

and efficiency. Lower inductor values minimize size

and cost, but reduce efficiency due to higher peak-cur-

rent levels. The smallest inductor is achieved by lower-

ing the inductance until the circuit operates at the

border between continuous and discontinuous mode.

Further reducing the inductor value below this

crossover point results in discontinuous-conduction

operation even at full load. This helps lower output filter

capacitance requirements, but efficiency suffers due to

high I2R losses. On the other hand, higher inductor val-

ues mean greater efficiency, but resistive losses due to

extra wire turns will eventually exceed the benefit

gained from lower peak-current levels. Also, high

inductor values can affect load-transient response (see

the VSAG equation in the Low-Voltage Operation sec-

tion). The equations that follow are for continuous-con-

duction operation, since the MAX1630A family is

intended mainly for high-efficiency, battery-powered

applications. Refer to Appendix A in Maxim’s Battery

Management and DC-DC Converter Circuit Collection

for crossover-point and discontinuous-mode equations.

Discontinuous conduction doesn’t affect normal Idle

Mode operation.

Three key inductor parameters must be specified:

inductance value (L), peak current (IPEAK), and DC

resistance (RDC). The following equation includes a

constant, LIR, which is the ratio of inductor peak-to-

peak AC current to DC load current. A higher LIR value

allows smaller inductance, but results in higher losses

and higher ripple. A good compromise between size

and losses is found at a 30% ripple-current to load-

current ratio (LIR = 0.3), which corresponds to a peak

inductor current 1.15 times higher than the DC load

current:

where:

f = switching frequency, normally 200kHz or

300kHz

IOUT = maximum DC load current

LIR = ratio of AC to DC inductor current, typi-

cally 0.3; should be selected for >0.15

The nominal peak inductor current at full load is 1.15 x

IOUT if the above equation is used; otherwise, the peak

current can be calculated by:

The inductor’s DC resistance should be low enough that

RDC x IPEAK < 100mV, as it is a key parameter for effi-

ciency performance. If a standard off-the-shelf inductor

is not available, choose a core with an LI2rating greater

than L x IPEAK2 and wind it with the largest diameter

wire that fits the winding area. For 300kHz applications,

ferrite core material is strongly preferred; for 200kHz

applications, Kool-Mµ®(aluminum alloy) or even pow-

dered iron is acceptable. If light-load efficiency is unim-

portant (in desktop PC applications, for example), then

low-permeability iron-powder cores, such as the

Micrometals type found in Pulse Engineering’s 2.1µH

PE-53680, may be acceptable even at 300kHz. For

high-current applications, shielded-core geometries,

such as toroidal or pot core, help keep noise, EMI, and

switching-waveform jitter low.

I= I+

V (V -V

2 x f x L x V

PEAK LOAD

OUT IN(MAX) OUT

IN(MAX)

)

L = VV - V

V x f x I x LIR

OUT IN(MAX) OUT

IN(MAX) OUT

()

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

______________________________________________________________________________________ 19

Current-Sense Resistor Value

The current-sense resistor value is calculated according

to the worst-case-low current-limit threshold voltage

(from the Electrical Characteristics table) and the peak

inductor current:

Use IPEAK from the second equation in the Inductor

Value section

Use the calculated value of RSENSE to size the MOSFET

switches and specify inductor saturation-current ratings

according to the worst-case high-current-limit threshold

voltage:

Low-inductance resistors, such as surface-mount

metal-film, are recommended.

Input Capacitor Value

Connect low-ESR bulk capacitors and small ceramic

capacitors (0.1µF) directly to the drains on the high-side

MOSFETs. The bulk input filter capacitor is usually

selected according to input ripple current requirements

and voltage rating, rather than capacitor value.

Electrolytic capacitors with low enough effective series

resistance (ESR) to meet the ripple current requirement

invariably have sufficient capacitance values. Aluminum

electrolytic capacitors, such as Sanyo

OS-CON or Nichicon PL, are superior to tantalum types,

which carry the risk of power-up surge-current failure,

especially when connecting to robust AC adapters or

low-impedance batteries. RMS input ripple current

(IRMS) is determined by the input voltage and load cur-

rent, with the worst case occurring at VIN = 2 x VOUT:

Bypassing V+

Bypass the V+ input with a 4.7µF tantalum capacitor

paralleled with a 0.1µF ceramic capacitor, close to the

IC. A 10Ωseries resistor to VIN is also recommended.

Bypassing VL

Bypass the VL output with a 4.7µF tantalum capacitor

paralleled with a 0.1µF ceramic capacitor, close to the

device.

Output Filter Capacitor Value

The output filter capacitor values are generally deter-

mined by the ESR and voltage rating requirements, rather

than actual capacitance requirements for loop stability. In

other words, the low-ESR electrolytic capacitor that meets

the ESR requirement usually has more output capaci-

tance than is required for AC stability. Use only special-

ized low-ESR capacitors intended for switching-regulator

applications, such as AVX TPS, Sprague 595D, Sanyo

OS-CON, or Nichicon PL series. To ensure stability, the

capacitor must meet both minimum capacitance and

maximum ESR values as given in the following equations:

(can be multiplied by 1.5; see text below)

These equations are worst case, with 45 degrees of

phase margin to ensure jitter-free, fixed-frequency

operation and provide a nicely damped output

response for zero to full-load step changes. Some cost-

conscious designers may wish to bend these rules with

less-expensive capacitors, particularly if the load lacks

large step changes. This practice is tolerable if some

bench testing over temperature is done to verify

acceptable noise and transient response.

No well-defined boundary exists between stable and

unstable operation. As phase margin is reduced, the

first symptom is a bit of timing jitter, which shows up as

blurred edges in the switching waveforms where the

scope does not quite sync up. Technically speaking,

this jitter (usually harmless) is unstable operation, since

the duty factor varies slightly. As capacitors with higher

ESRs are used, the jitter becomes more pronounced,

and the load-transient output voltage waveform starts

looking ragged at the edges. Eventually, the load-tran-

sient waveform has enough ringing on it that the peak

noise levels exceed the allowable output voltage toler-

ance. Note that even with zero phase margin and gross

instability present, the output voltage noise never gets

much worse than IPEAK x RESR (under constant loads).

Designers of RF communicators or other noise-sensi-

tive analog equipment should be conservative and stay

within the guidelines. Designers of notebook computers

and similar commercial-temperature-range digital

systems can multiply the RESR value by a factor of 1.5

without hurting stability or transient response.

The output voltage ripple is usually dominated by the

filter capacitor’s ESR, and can be approximated as

IRIPPLE x RESR. There is also a capacitive term, so the

V (1 + V / V )

V x R x f

OUT

REF OUT IN(MIN)

OUT SENSE

RRxV

ESR SENSE OUT

REF

I = I x V(V-V)

I I

RMS LOAD OUT IN OUT

RMS LOAD

Therefore when V is X V

IN OUT

,:2

I = 120mV

PEAK(MAX) SENSE

R = 80mV

SENSE PEAK

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

20 ______________________________________________________________________________________

full equation for ripple in continuous-conduction mode

is VNOISE (P-P) = IRIPPLE x [RESR + 1/(2 x πx f x

COUT)]. In Idle Mode, the inductor current becomes

discontinuous, with high peaks and widely spaced

pulses, so the noise can actually be higher at light load

(compared to full load). In Idle Mode, calculate the out-

put ripple as follows:

Transformer Design

(for Auxiliary Outputs Only)

Buck-plus-flyback applications, sometimes called “cou-

pled-inductor” topologies, need a transformer to gener-

ate multiple output voltages. Performing the basic

electrical design is a simple task of calculating turns

ratios and adding the power delivered to the secondary

to calculate the current-sense resistor and primary

inductance. However, extremes of low input-output dif-

ferentials, widely different output loading levels, and

high turns ratios can complicate the design due to par-

asitic transformer parameters such as interwinding

capacitance, secondary resistance, and leakage

inductance. For examples of what is possible with real-

world transformers, see the Maximum Secondary

Current vs. Input Voltage graph in the Typical

Operating Characteristics section.

Power from the main and secondary outputs is combined

to get an equivalent current referred to the main output

voltage (see the Inductor Value section for parameter def-

initions). Set the current-sense resistor resistor value at

80mV / ITOTAL.

PTOTAL = The sum of the output power from all outputs

ITOTAL = PTOTAL / VOUT = The equivalent output cur-

rent referred to VOUT:

where:

VSEC = the minimum required rectified secondary out-

put voltage

VFWD = the forward drop across the secondary

rectifier

VOUT(MIN) = the minimum value of the main output

voltage (from the Electrical Characteristics)

VRECT = the on-state voltage drop across the synchro-

nous rectifier MOSFET

VSENSE = the voltage drop across the sense resistor

In positive-output applications, the transformer sec-

ondary return is often referred to the main output volt-

age, rather than to ground, to reduce the needed turns

ratio. In this case, the main output voltage must first be

subtracted from the secondary voltage to obtain VSEC.

Selecting Other Components

MOSFET Switches

The high-current n-channel MOSFETs must be logic-level

types with guaranteed on-resistance specifications at

VGS = 4.5V. Lower gate threshold specifications are bet-

ter (i.e., 2V max rather than 3V max). Drain-source break-

down voltage ratings must at least equal the maximum

input voltage, preferably with a 20% derating factor. The

best MOSFETs have the lowest on-resistance per

nanocoulomb of gate charge. Multiplying RDS(ON) x QG

provides a good figure for comparing various MOSFETs.

Newer MOSFET process technologies with dense cell

structures generally perform best. The internal gate dri-

vers tolerate >100nC total gate charge, but 70nC is a

more practical upper limit to maintain best switching

times.

In high-current applications, MOSFET package power

dissipation often becomes a dominant design factor. I2R

power losses are the greatest heat contributor for both

high-side and low-side MOSFETs. I2R losses are distrib-

uted between Q1 and Q2 according to duty factor (see

the following equations). Generally, switching losses

affect only the upper MOSFET, since the Schottky rectifier

clamps the switching node in most cases before the syn-

chronous rectifier turns on. Gate-charge losses are dissi-

pated by the driver and do not heat the MOSFET.

Calculate the temperature rise according to package

thermal-resistance specifications to ensure that both

MOSFETs are within their maximum junction temperature

at high ambient temperature. The worst-case dissipation

for the high-side MOSFET occurs at both extremes of

input voltage, and the worst-case dissipation for the low-

side MOSFET occurs at maximum input voltage:

PD(upper FET) = (I ) x R x DUTY

+ V x I x f x V x C

I20ns

PD(lower FET) = (I ) x R x (1 - DUTY)

DUTY = (V + V ) / (V - V )

LOAD 2DS(ON)

IN LOAD IN RSS

GATE

LOAD 2DS(ON)

OUT Q2 IN Q1

⎛

⎝

⎜⎞

⎠

⎟

L(primary) = V(V -V)

V x f x I x LIR

Turns Ratio N = V + V

V+V+V

OUT IN(MAX) OUT

IN(MAX) TOTAL

SEC FWD

OUT(MIN) RECT SENSE

V = 0.02 x R

0.0003 x Lx 1 / V 1 / (V - V )

(R ) x C

NOISE(P-P) ESR

SENSE

OUT IN OUT

SENSE 2OUT

[]

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

______________________________________________________________________________________ 21

where:

on-state voltage drop VQ_ = ILOAD x RDS(ON)

CRSS = MOSFET reverse transfer capacitance

IGATE =DH driver peak output current capability

(1A typical)

20ns = DH driver inherent rise/fall time

Under output short circuit, the MAX1633A/MAX1634A/

MAX1635As’ synchronous rectifier MOSFET suffers

extra stress because its duty factor can increase to

greater than 0.9. It may need to be oversized to tolerate

a continuous DC short circuit. During short circuit, the

MAX1630A/MAX1631A/MAX1632As’ output undervolt-

age shutdown protects the synchronous rectifier under

output short-circuit conditions.

To reduce EMI, add a 0.1µF ceramic capacitor from the

high-side switch drain to the low-side switch source.

Rectifier Clamp Diode

The rectifier is a clamp across the low-side MOSFET

that catches the negative inductor swing during the

60ns dead time between turning one MOSFET off and

each low-side MOSFET on. The latest generations of

MOSFETs incorporate a high-speed silicon body diode,

which serves as an adequate clamp diode if efficiency

is not of primary importance. A Schottky diode can be

placed in parallel with the body diode to reduce the for-

ward voltage drop, typically improving efficiency 1% to

2%. Use a diode with a DC current rating equal to one-

third of the load current; for example, use an MBR0530

(500mA-rated) type for loads up to 1.5A, a 1N5819 type

for loads up to 3A, or a 1N5822 type for loads up to

10A. The rectifier’s rated reverse breakdown voltage

must be at least equal to the maximum input voltage,

preferably with a 20% derating factor.

Boost-Supply Diode D2

A signal diode such as a 1N4148 works well in most

applications. If the input voltage can go below +6V, use

a small (20mA) Schottky diode for slightly improved

efficiency and dropout characteristics. Do not use large

power diodes, such as 1N5817 or 1N4001, since high

junction capacitance can pump up VL to excessive

voltages.

Rectifier Diode D3

(Transformer Secondary Diode)

The secondary diode in coupled-inductor applications

must withstand flyback voltages greater than 60V,

which usually rules out most Schottky rectifiers.

Common silicon rectifiers, such as the 1N4001, are also

prohibited because they are too slow. This often makes

fast silicon rectifiers such as the MURS120 the only

choice. The flyback voltage across the rectifier is relat-

ed to the VIN - VOUT difference, according to the trans-

former turns ratio:

where:

N = the transformer turns ratio SEC/PRI

VSEC = the maximum secondary DC output voltage

VOUT = the primary (main) output voltage

Subtract the main output voltage (VOUT) from VFLYBACK

in this equation if the secondary winding is returned to

VOUT and not to ground. The diode reverse breakdown

rating must also accommodate any ringing due to leak-

age inductance. D3’s current rating should be at least

twice the DC load current on the secondary output.

Low-Voltage Operation

Low input voltages and low input-output differential

voltages each require extra care in their design. Low

absolute input voltages can cause the VL linear regula-

tor to enter dropout and eventually shut itself off. Low

input voltages relative to the output (low VIN-VOUT dif-

ferential) can cause bad load regulation in multi-output

flyback applications (see the design equations in the

Transformer Design section). Also, low VIN-VOUT differ-

entials can also cause the output voltage to sag when

the load current changes abruptly. The amplitude of the

sag is a function of inductor value and maximum duty

factor (an Electrical Characteristics parameter, 98%

guaranteed over temperature at f = 200kHz), as follows:

The cure for low-voltage sag is to increase the output

capacitor’s value. For example, at VIN = +5.5V, VOUT =

+5V, L = 10µH, f = 200kHz, ISTEP = 3A, a total capaci-

tance of 660µF keeps the sag less than 200mV. Note

that only the capacitance requirement increases, and

the ESR requirements do not change. Therefore, the

added capacitance can be supplied by a low-cost bulk

capacitor in parallel with the normal low-ESR capacitor.

V= (I ) x L

2 x C x (V x D - V )

SAG STEP 2

OUT IN(MAX) MAX OUT

V = V + (V - V ) x N

FLYBACK SEC IN OUT

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

22 ______________________________________________________________________________________

Table 5. Low-Voltage Troubleshooting Chart

________________Applications Information

Heavy-Load Efficiency Considerations

The major efficiency-loss mechanisms under loads are,

in the usual order of importance:

•P(I2R) = I2R losses

•P(tran) = transition losses

•P(gate) = gate-charge losses

•P(diode) = diode-conduction losses

•P(cap) = capacitor ESR losses

•P(IC) = losses due to the IC’s operating supply

current

Inductor core losses are fairly low at heavy loads

because the inductor’s AC current component is small.

Therefore, they are not accounted for in this analysis.

Ferrite cores are preferred, especially at 300kHz, but

powdered cores, such as Kool-Mu, can work well:

where RDC is the DC resistance of the coil, RDS(ON) is

the MOSFET on-resistance, and RSENSE is the current-

sense resistor value. The RDS(ON) term assumes identi-

cal MOSFETs for the high-side and low-side switches,

because they time-share the inductor current. If the

MOSFETs are not identical, their losses can be estimat-

ed by averaging the losses according to duty factor:

where CRSS is the reverse transfer capacitance of the

high-side MOSFET (a data-sheet parameter), IGATE is the

DH gate-driver peak output current (1.5A typ), and 20ns

is the rise/fall time of the DH driver (20ns typ):

P(gate) = qG x f x VL

where VL is the internal-logic-supply voltage (+5V), and qG

is the sum of the gate-charge values for low-side and high-

side switches. For matched MOSFETs, qG is twice the

data-sheet value of an individual MOSFET. If VOUT is set to

less than 4.5V, replace VL in this equation with VBATT. In

this case, efficiency can be improved by connecting VL to

an efficient 5V source, such as the system +5V supply:

P(diode) = diode- conduction losses

= I x V x t x f

LOAD FWD D

PD(tran) = transition loss = V x I x f x 3

2 x

(V x C / I ) + 20ns

IN LOAD

IN RSS GATE

[]

Efficiency = P / P x 100%

= P / (P + P ) x 100%

P = P(I R) + P(tran) + P(gate) +

P(diode) + P(cap) + P(IC)

P = (I R) = (I ) x (R + R + R )

OUT IN

OUT OUT TOTAL

TOTAL 2

2LOAD 2DC DS(ON) SENSE

Use a small 20mA Schottky diode

for boost diode D2. Supply VL from

an external source.

Poor efficiency

VL linear regulator is going

into dropout and is not pro-

viding good gate-drive levels.

Supply VL from an external source

other than VIN, such as the system

+5V supply.

Does not start under load or

quits before battery is

completely dead

Low input voltage, <5V

VL output is so low that it hits

the VL UVLO threshold.

Low input voltage, <4.5V

Increase the minimum input voltage

or ignore.

Unstable—jitters between

different duty factors and

frequencies

Normal function of internal

low-dropout circuitry.

Reduce operation to 200kHz.

Reduce secondary impedances;

use a Schottky diode, if possible.

Stack secondary winding on the

main output.

Secondary output won’t

support a load

Low VIN-VOUT

differential, <0.5V

Not enough duty cycle left to

initiate forward-mode opera-

tion. Small AC current in

primary cannot store energy

for flyback operation.

Low VIN-VOUT

differential,

VIN < 1.3 x VOUT (main)

Reduce operation to 200kHz.

Reduce MOSFET on-resistance and

coil DCR.

Dropout voltage is too high

(VOUT follows VIN as VIN

decreases)

Maximum duty-cycle limits

exceeded.

Low VIN-VOUT

differential, <1V

Increase bulk output capacitance

per formula (see the Low-Voltage

Operation section). Reduce inductor

value.

SOLUTION

Limited inductor-current

slew rate per cycle.

ROOT CAUSE

Low VIN-VOUT

differential, <1.5V

CONDITION

Sag or droop in VOUT under

step-load change

SYMPTOM

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

______________________________________________________________________________________ 23

where tDis the diode-conduction time (120ns typ) and

VFWD is the forward voltage of the diode.

This power is dissipated in the MOSFET body diode if

no external Schottky diode is used:

where IRMS is the input ripple current as calculated in the

Design Procedure and Input Capacitor Value sections.

Light-Load Efficiency Considerations

Under light loads, the PWM operates in discontinuous

mode, where the inductor current discharges to zero at

some point during the switching cycle. This makes the

inductor current’s AC component high compared to the

load current, which increases core losses and I2R loss-

es in the output filter capacitors. For best light-load effi-

ciency, use MOSFETs with moderate gate-charge

levels, and use ferrite, MPP, or other low-loss core

material. Avoid powdered-iron cores; even Kool-Mu

(aluminum alloy) is not as good as ferrite.

PC Board Layout Considerations

Good PC board layout is required in order to achieve

specified noise, efficiency, and stability performance.

The PC board layout artist must be given explicit

instructions, preferably a pencil sketch showing the

placement of power-switching components and high-

current routing. Refer to the PC board layout in the

MAX1630A Evaluation Kit manual for examples. A

ground plane is essential for optimum performance. In

most applications, the circuit will be located on a

multilayer board, and full use of the four or more cop-

per layers is recommended. Use the top layer for high-

current connections, the bottom layer for quiet

connections (REF, SS, GND), and the inner layers for

an uninterrupted ground plane. Use the following step-

by-step guide:

1) Place the high-power components (Figure 1, C1,

C3, Q1, Q2, D1, L1, and R1) first, with any grounded

connections adjacent:

Priority 1: Minimize current-sense resistor trace

lengths and ensure accurate current

sensing with Kelvin connections (Figure 7).

Priority 2: Minimize ground trace lengths in the

high-current paths (discussed below).

Priority 3: Minimize other trace lengths in the high-

current paths.

Use > 5mm-wide traces.

CIN to high-side MOSFET drain: 10mm

max length.

Rectifier diode cathode to low-side

MOSFET: 5mm max length.

LX node (MOSFETs, rectifier cathode,

inductor): 15mm max length.

Ideally, surface-mount power components are butted

up to one another with their ground terminals almost

touching. These high-current grounds are then con-

nected to each other with a wide filled zone of top-layer

copper so they do not go through vias. The resulting

top-layer “subground-plane” is connected to the normal

inner-layer ground plane at the output ground termi-

nals, which ensures that the IC’s analog ground is

sensing at the supply’s output terminals without interfer-

ence from IR drops and ground noise. Other high-

current paths should also be minimized, but focusing

primarily on short ground and current-sense con-

nections eliminates about 90% of all PC board lay-

out problems (refer to the PC board layouts in the

MAX1630A Evaluation Kit manual for examples).

2) Place the IC and signal components. Keep the main

switching nodes (LX nodes) away from sensitive

analog components (current-sense traces and REF

capacitor). Place the IC and analog components on

the opposite side of the board from the power-

switching node. Important: The IC must be no far-

ther than 10mm from the current-sense resistors.

Keep the gate-drive traces (DH_, DL_, and BST_)

shorter than 20mm and route them away from CSH_,

CSL_, and REF.

3) Use a single-point star ground where the input

ground trace, power ground (subground-plane),

and normal ground plane meet at the supply’s out-

put ground terminal. Connect both IC ground pins

and all IC bypass capacitors to the normal ground

plane.

P(cap) = input capacitor ESR loss = (I ) x R

RMS 2ESR

MAX1630A

SENSE RESISTOR

HIGH-CURRENT PATH

Figure 7. Kelvin Connections for the Current-Sense Resistors

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

24 ______________________________________________________________________________________

_______________________________________________________________________________Application Circuits

RESET

FB5

MAX1630A

MAX1633A

SHDN SYNC

INPUT

+5.2V TO +24V

PGND

SEQ

REF

16 Q3

L2 R2

23 22

10Ω

621

POWER-GOOD

10 8

5V ON/OFF

SKIP

V+ VL

DL5

LX5

DH5

BST5

2.2μF

0.1μF

1μF

0.1μF

4.7μF

2.7μF

1N5819

4.7μF

12OUT

C3 C4

+12V

AT 120mA

+5V OUTPUT (3A)

+5V

ALWAYS ON

GND

+2.5V REF

1:4

0.1μF

1N5819

+3.3V

OUTPUT

(3A)

TIME/ON5

RUN/ON3

FB3

3V ON/OFF

CSL5

CSH5

CSL3

CSH3

DL3

LX3

DH3

BST3

VDD

ON/OFF

TO +3.3V OUTPUT TO +5V OUTPUT

R1 = R2 = 20mΩ

L2 = 10μH SUMIDA CDRH125-100

T1 = 10μH 1:4 TRANSFORMER

TRANSPOWER TECHNOLOGIES TTI-5902

Q1–Q4 = Si4410DY or IRF7413

C1 = 3 x 220μF 10V SPRAGUE 594D227X0010D2T

C2 = 2 x 220μF 10V SPRAGUE 594D227X0010D2T

C3 = C4 = 2 x 10μF 30V SANYO OS-CON 30SC10M

*VL DIODES AND OUTPUT SCHOTTKY DIODES REQUIRED

FOR THE MAX1630A ONLY (SEE OUTPUT OVERVOLTAGE PROTECTION

AND OUTPUT UNDERVOLTAGE SHUTDOWN PROTECTION SECTIONS).

Figure 8. Triple-Output Application for Low-Voltage Batteries (MAX1630A/MAX1633A)

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

______________________________________________________________________________________ 25

_____________________________________________________________Application Circuits (continued)

2.2μF

RESET

FB5

MAX1632A

MAX1635A

PGND

SEQ

REF

16 Q3

1:2.2

POWER-GOOD

10 8

5V ON/OFF

SKIP

DL5

LX5

DH5

BST5

VDD

2.2μF

0.1μFC2

0.1μF

1μF

1N5819

+5V OUTPUT (3A)

GND

+2.5V REF

R1 0.1μF

0.1μF

1N5819

+3.3V OUTPUT (3A)

ON/OFF

TIME/ON5

RUN/ON3

FB3

3V ON/OFF

CSL5

CSH5

CSL3

CSH3

DL3

LX3

DH3

BST3

SHDN SYNC

INPUT

+6.5V TO +28V

23 22

10Ω

621

V+ VL

0.1μF

4.7μF

12OUT

TO +3.3V OUTPUT TO +5V OUTPUT

+12V AT 120mA

+5V ALWAYS ON

R1 = R2 = 20mΩ

L1 = 10μH SUMIDA CDRH125-100

T2 = 10μH 1:2.2 TRANSFORMER

TRANSPOWER TECHNOLOGIES TTI-5870

Q1–Q4 = Si4410DY or IRF7413

C1 = 3 x 220μF 10V SPRAGUE 594D227X0010D2T

C2 = 2 x 220μF 10V SPRAGUE 594D227X0010D2T

C3 = C4 = 2 x 10μF 30V SANYO OS-CON 30SC10M

*VL DIODES AND OUTPUT SCHOTTKY DIODES REQUIRED

FOR THE MAX1632A ONLY (SEE OUTPUT OVERVOLTAGE PROTECTION

AND OUTPUT UNDERVOLTAGE SHUTDOWN PROTECTION SECTIONS).

Figure 9. Triple-Output Application for High-Voltage Batteries (MAX1632A/MAX1635A)

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

26 ______________________________________________________________________________________

OPEN

MAX1631A

MAX1634A

V+ SHDN VLSECFB

INPUT

+6V TO +24V

10Ω

ON/OFF

GND

REF SEQ SYNC

1μF

5V ALWAYS ON

ON/OFF

0.1μF

4.7μF

0.1μF

DL3

CSH3

CSL3

FB3

RESET RESET OUTPUT

SKIP

STEER

2.5V OUTPUT

C1 DL5

LX5

DH5

BST5 25

22 23 5 21

BST3

DH3

LX3

PGND

CSL5

CSH5

RUN/ON3

TIME/ON5

0Ω

FB5

0.1μF

L2 R2 +3.3V OUTPUT

R1 = R2 = 15mΩ

L1 = L2 = 6.8μH SUMIDA CDRH 127-6R8MC

Q1 = Q4 = Si4410DY or 1RF7413

C1 = C2 = 2X SANYO OS-CON 10 SA220M

C3 = 4X SANYO OS-CON 30SC10M

*VL DIODES AND OUTPUT SCHOTTKY DIODES REQUIRED

FOR THE MAX1631A ONLY (SEE OUTPUT OVERVOLTAGE PROTECTION

AND OUTPUT UNDERVOLTAGE SHUTDOWN PROTECTION SECTIONS).

OPEN

0Ω

*Q4

1N5819

Figure 10. Dual, 4A, Notebook Computer Power Supply

_____________________________________________________________Application Circuits (continued)

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

______________________________________________________________________________________ 27

________________________________________________________________________________Pin Configurations

RUN/ON3

DH3

LX3

BST3

DL3

SHDN

SEQ

V+

PGND

DL5

BST5

LX5

DH5

CSH5

CSL5

FB5

RESET

SKIP

REF

GND

TIME/ON5

SYNC

VDD

12OUT

FB3

CSL3

CSH3

SSOP SSOP

MAX1630A

MAX1632A

MAX1633A

MAX1635A

RUN/ON3

DH3

LX3

BST3

DL3

SHDN

SEQ

V+

PGND

DL5

BST5

LX5

DH5

CSH5

CSL5

FB5

RESET

SKIP

REF

GND

TIME/ON5

SYNC

SECFB

STEER

FB3

CSL3

CSH3

TOP VIEW

MAX1631A

MAX1634A

_______________________________________________________________Selector Guide

MAX1631A

MAX1633A

MAX1632A

MAX1634A

MAX1635A

DEVICE

None (SECFB input)

12V linear regulator

None (SECFB input)

12V linear regulator

AUXILIARY OUTPUT

12V linear regulator

Selectable (STEER pin)

Feeds into the 3.3V SMPS

Feeds into the 5V SMPS

Selectable (STEER pin)

Feeds into the 5V SMPS

SECONDARY FEEDBACK

Yes

MAX1630A

OVER/UNDERVOLTAGE

PROTECTION

YesFeeds into the 3.3V SMPS

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

28 ______________________________________________________________________________________

__Ordering Information (continued)

+Denotes lead-free package.

28 SSOP-40°C to +85°C

MAX1635AEAI

28 SSOP-40°C to +85°C

MAX1634AEAI

MAX1633AEAI

28 SSOP-40°C to +85°C

MAX1632AEAI

28 SSOP

PIN-PACKAGETEMP RANGE

-40°C to +85°CMAX1630AEAI+

PART

28 SSOP-40°C to +85°C

MAX1631AEAI

28 SSOP-40°C to +85°CMAX1631AEAI+

28 SSOP-40°C to +85°CMAX1632AEAI+

28 SSOP-40°C to +85°CMAX1633AEAI+

28 SSOP-40°C to +85°CMAX1634AEAI+

28 SSOP-40°C to +85°CMAX1635AEAI+

MAX1630A–MAX1635A

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

29 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

SSOP.EPS

PACKAGE OUTLINE, SSOP, 5.3 MM

21-0056 C

REV.DOCUMENT CONTROL NO.APPROVAL

PROPRIETARY INFORMATION

TITLE:

NOTES:

1. D&E DO NOT INCLUDE MOLD FLASH.

2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").

3. CONTROLLING DIMENSION: MILLIMETERS.

4. MEETS JEDEC MO150.

5. LEADS TO BE COPLANAR WITHIN 0.10 MM.

7.90

0∞

0.301

0.025

8∞

0.311

0.037

0∞

7.65

0.63

8∞

0.95

MAX

5.38

MILLIMETERS

DIM

SEE VARIATIONS

0.0256 BSC

0.010

0.004

0.205

0.002

0.015

0.008

0.212

0.008

INCHES

MIN MAX

0.078

0.65 BSC

0.25

0.09

5.20

0.05

0.38

0.20

0.21

MIN

1.73 1.99

MILLIMETERS

6.07

10.07

8.07

7.07

INCHES

0.239

0.397

0.317

0.278

MIN

0.249

0.407

0.328

0.289

MAX MIN

6.33

10.33

8.33

7.33

14L

16L

28L

24L

20L

MAX N

eA1 L

0.068

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)