TL/F/11006
Laser Beam Printer (LBP) Controller Solution Card SB-113
National Semiconductor
System Brief SB- 113
June 1990
Laser Beam Printer (LBP)
Controller Solution Card
TL/F/11006–1
FIGURE 1. A Laser Printer Block Diagram
SYSTEM DESCRIPTION
A Laser Beam Printer (LBP) can be divided into three sec-
tions: mechanics, optics, and electronics, as can be seen in
Figure 1
. The mechanics of an LBP handle the physical path
of the paper. The optics generate the laser beam and syn-
chronizing signals. The electronics control the laser printer
operation and are often referred to as the LBP formatter or
RIP (Raster Image Processor).
The LBP formatter performs computation and control tasks
aimed at transferring images, provided by the host computer
in a Page Description Language (PDL) format, to the bit-
map image that is sent to the printer optics and mechanics.
The PDL contains the instructions needed to create the im-
aged page, a task that requires a high performance 32-bit
CPU. In addition the formatter controls the operation of the
user panel and the printing engine. Inputs are received from
microswitches, sensors, and the video controller. Outputs
are fed to motors, solenoids, relays, and the video control-
ler.
Embedded processors are specifically targeted to execute
in the imaging environment. A family of processors to cover
low-to-high range LBP applications is available, with differ-
ent degrees of performance and integration. The choice of
an embedded processor for a non-impact printer controller
is of high importance. The processor should be selected by
considering its impact on the system cost and performance.
The applicability of the instruction set, integration, bus inter-
face, and development tools are important issues.
Figure 2
shows a block diagram of an LBP controller. The
choice of CPU, for high-performance printer formatters, or
for mid-range performance should have the same level of
integration, including on-chip Interrupt Control Unit (ICU),
2-channel DMA Controller (DMAC), and 3 timers/counters.
The hardware Floating Point Unit (FPU) is optional. It in-
creases the system performance, typically by 20%, when
running PostScriptTM. For small memory systems a 16-bit
data bus is provided, which is fully transparent to the inter-
nal 32-bit architecture. A 32-bit external data bus, with burst
mode, is used for high-performance systems. The control
logic, the 32-bit video shifter, the printer mechanism control,
and the keyboard display control, may all be implemented in
a system ASIC. To support RS-232 serial interface, and a
Centronics type interface. UART with parallel interface, or a
UART with FIFOs, parallel interface, and decode logic, may
be used.
PDLs are large programs requiring large amounts of memo-
ry for code, font and image storage. The code and font re-
quire 512 kBytes for a PCLTM style printer, and 1.5 MBytes
for a PostScript type printer.
Series 32000Éis a registered trademark of National Semiconductor Corporation.
PCLTM is a trademark of Hewlett Packard Corporation.
PostScriptTM is a trademark of Adobe Systems, Incorporated.
C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.