TL/F/11006
Laser Beam Printer (LBP) Controller Solution Card SB-113
National Semiconductor
System Brief SB- 113
June 1990
Laser Beam Printer (LBP)
Controller Solution Card
TL/F/110061
FIGURE 1. A Laser Printer Block Diagram
SYSTEM DESCRIPTION
A Laser Beam Printer (LBP) can be divided into three sec-
tions: mechanics, optics, and electronics, as can be seen in
Figure 1
. The mechanics of an LBP handle the physical path
of the paper. The optics generate the laser beam and syn-
chronizing signals. The electronics control the laser printer
operation and are often referred to as the LBP formatter or
RIP (Raster Image Processor).
The LBP formatter performs computation and control tasks
aimed at transferring images, provided by the host computer
in a Page Description Language (PDL) format, to the bit-
map image that is sent to the printer optics and mechanics.
The PDL contains the instructions needed to create the im-
aged page, a task that requires a high performance 32-bit
CPU. In addition the formatter controls the operation of the
user panel and the printing engine. Inputs are received from
microswitches, sensors, and the video controller. Outputs
are fed to motors, solenoids, relays, and the video control-
ler.
Embedded processors are specifically targeted to execute
in the imaging environment. A family of processors to cover
low-to-high range LBP applications is available, with differ-
ent degrees of performance and integration. The choice of
an embedded processor for a non-impact printer controller
is of high importance. The processor should be selected by
considering its impact on the system cost and performance.
The applicability of the instruction set, integration, bus inter-
face, and development tools are important issues.
Figure 2
shows a block diagram of an LBP controller. The
choice of CPU, for high-performance printer formatters, or
for mid-range performance should have the same level of
integration, including on-chip Interrupt Control Unit (ICU),
2-channel DMA Controller (DMAC), and 3 timers/counters.
The hardware Floating Point Unit (FPU) is optional. It in-
creases the system performance, typically by 20%, when
running PostScriptTM. For small memory systems a 16-bit
data bus is provided, which is fully transparent to the inter-
nal 32-bit architecture. A 32-bit external data bus, with burst
mode, is used for high-performance systems. The control
logic, the 32-bit video shifter, the printer mechanism control,
and the keyboard display control, may all be implemented in
a system ASIC. To support RS-232 serial interface, and a
Centronics type interface. UART with parallel interface, or a
UART with FIFOs, parallel interface, and decode logic, may
be used.
PDLs are large programs requiring large amounts of memo-
ry for code, font and image storage. The code and font re-
quire 512 kBytes for a PCLTM style printer, and 1.5 MBytes
for a PostScript type printer.
Series 32000Éis a registered trademark of National Semiconductor Corporation.
PCLTM is a trademark of Hewlett Packard Corporation.
PostScriptTM is a trademark of Adobe Systems, Incorporated.
C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/110062
FIGURE 2. Block Diagram of a Laser Printer Controller
2
DESIGN CHALLENGES
Performance
Get the best performance for the price.
For a solid performance of 4 to 15 pages per minute (ppm)
printer the NS32CG16, NS32CG160, and NS32FX16, are
recommended. For printers of 15 ppm and beyond the
NS32GX32 and NS32GX320 are the processors of choice.
Component Count
Reduce component count through efficient bus architecture,
integration, and code density.
Code Compactness
Series 32000ÉArchitecture code is the most compact in the
industry, and may be some 60% less is size then a generic
RISC code, which relates to fewer EPROMs in the system
for lower cost and smaller size.
Graphics Support
Graphics supported by dedicated on-chip hardware and
specialized instructions for printer operations.
KEY COMPONENTS
NS32CG16, NS32CG160, CPU Function
NS32FX16, NS32GX32 or NS32GX320, FPU Function
NS32081, NS32181 or NS32381
NS32CG821 DRAM Controller Designed to Interface with
Series 32000 Embedded Processor
NS16C451/NS16C551 UART with Parallel Interface,
(FIFOs, and Decode Logic)
EPROM Program and Font Storage
DRAM Working Space and Data Buffers
EEPROM Setup Storage
BILL OF MATERIAL OF MAJOR COMPONENTS 15 PPM LBP CONTROLLER
Function Description NSC Part Other Mfg Qty
CPU Embedded Processor NS32GX320 1
FPU Floating-Point Unit NS32381 1
Interface Serial and Parallel Interface NS16C451 1
Memory
EPROM 1 Mbyte NMC27C010 8
DRAM 4 Mbyte
EEPROM 256 Byte NMC93CS56 1
Memory Control DRAM Controller NS32CG821 1
Logic
System ASIC Interface (Note 1) 1
Note 1: The system ASIC may be designed using National’s ASIC capabilities.
3
SB-113 Laser Beam Printer (LBP) Controller Solution Card
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.