PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY BURST CellularRAMTM MT45W4MW16BFB MT45W2MW16BFB Features * * * * * Figure 1: Ball Assignment 54-Ball VFBGA Single device supports asynchronous, page, and burst operations VCC, VCCQ Voltages 1.70V-1.95V VCC 1.70V-2.25V VCCQ (Option W) 2.30V-2.70V VCCQ (Option V--contact factory) 2.70V-3.30V VCCQ (Option L--contact factory) Random Access Time: 70ns Burst Mode Write Access Continuous burst Burst Mode Read Access 4, 8, or 16 words, or continuous burst 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CRE B DQ8 UB# A3 A4 CE# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSSQ DQ11 A17 A7 DQ3 VCC E VCCQ DQ12 A21 A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 J WAIT CLK ADV# NC NC NC tCLK = 9.62ns) MAX clock rate: 104 MHz ( Burst initial latency: 39ns (4 clocks) @ 104 MHz tACLK: 6.5ns @ 104 MHz * * * Page Mode Read Access Sixteen-word page size Interpage read access: 70ns Intrapage read access: 20ns Low Power Consumption Asynchronous READ < 25mA Intrapage READ < 15mA Initial access, burst READ: (39ns [4 clocks] @ 104 MHz) < 35mA Continuous burst READ < 15mA Standby: 120A (64Mb), 110A (32MB)--standard 100A (64Mb), 90A (32Mb)--low-power option Deep power-down < 10A Low-Power Features Temperature Compensated Refresh (TCR) Partial Array Refresh (PAR) Deep Power-Down (DPD) Mode Options * * * Configuration: 4 Meg x 16 2 Meg x 16 VCC Core Voltage Supply: 1.80V - MT45WxMx16B VCCQ I/O Voltage 3.0V - MT45WxML16B 2.5V - MT45WxMV16B * * 1.8V - MT45WxMW16B Package 54-ball VFBGA 54-ball VFBGA--Lead-free Timing 60ns access 70ns access 85ns access 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN Top View (Ball Down) See Table 1 on page 6 for ball descriptions, and Figure 45 on page 52 for 54-ball mechanical drawing. Designator Options (continued) MT45W4Mx16B MT45W2Mx16B * W * L1 V1 W * FB Designator Frequency 66 MHz 80 MHz 104 MHz 6 8 11 Standby power Standard Low-power Operating Temperature Range Wireless (-25C to +85C) Industrial (-40C to +85C) None L WT IT1 BB1 1. Contact factory. -601 -70 -85 Part Number Example: MT45W2MW16BFB-706LWT 1 (c)2004 Micron Technology, Inc. All Rights Reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Wait Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Partial Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Software Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Burst Length (BCR[2:0]) Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Burst Wrap (BCR[3]) Default = Burst No Wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 WAIT Configuration (BCR[8])Default = WAIT Transitions One Clock Before Data Valid/Invalid . . . . . . . . . . . . 19 WAIT Polarity (BCR[10]) Default = WAIT Active HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Latency Counter (BCR[13:11]) Default = Three-Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Deep Power-Down (RCR[4]) Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Temperature Compensated Refresh (RCR[6:5]) Default = +85C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Page Mode Operation (RCR[7]) Default = Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Data Sheet Designation: PRELIMINARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Table 48: VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bus Operations - Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus Operations - Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 64Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 32Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Temperature Compensated Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Partial Array Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Asynchronous READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Asynchronous READ Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Asynchronous READ Timing Parameters--Page Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Burst READ Timing Parameters--Single Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Burst READ Timing Parameters--4-Word Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Burst READ Timing Parameters--4-Word Burst with LB#/UB#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Burst READ Timing Parameters--Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Burst READ Timing Parameters--BCR[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Asynchronous WRITE Timing Parameters--CE#-Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Asynchronous WRITE Timing Parameters--LB#/UB#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Asynchronous WRITE Timing Parameters--WE#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Asynchronous WRITE Timing Parameters Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Burst WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Burst WRITE Timing Parameters--BCR[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 WRITE Timing Parameters--Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 READ Timing Parameters--Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 WRITE Timing Parameters--Async WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 READ Timing Parameters--Async WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 WRITE Timing Parameters--Async WRITE Followed by Burst READ--ADV# LOW . . . . . . . . . . . . . . . . 47 READ Timing Parameters--Async WRITE Followed by Burst READ--ADV# LOW . . . . . . . . . . . . . . . . . 47 Burst READ Timing Parameters--Burst READ Followed by Async WRITE (WE#-Control) . . . . . . . . . . 48 Asynchronous WRITE Timing Parameters--Burst READ Followed by Async WRITE (WE#-Control) . 48 Burst READ Timing Parameters--Burst READ Followed by Async WRITE Using ADV# . . . . . . . . . . . . 49 Asynchronous WRITE Timing Parameters--Burst READ Followed by Async WRITE Using ADV# . . . 49 WRITE Timing Parameters--Async WRITE Followed by Async READ--ADV# LOW . . . . . . . . . . . . . . . 50 READ Timing Parameters--Async WRITE Followed by Async READ--ADV# LOW . . . . . . . . . . . . . . . . 50 WRITE Timing Parameters--Async WRITE Followed by Async READ . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 READ Timing Parameters--Async WRITE Followed by Async READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Ball Assignment 54-Ball VFBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional Block Diagram - 4 Meg x 16 and 2 Meg x 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power-Up Initialization Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Page Mode READ Operation (ADV = LOW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Burst Mode READ (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Burst Mode WRITE (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Wired or WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Refresh Collision During READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Refresh Collision During WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Configuration Register WRITE in Asynchronous Mode Followed by READ . . . . . . . . . . . . . . . . . . . . . . . 15 Configuration Register WRITE in Synchronous Mode Followed by READ . . . . . . . . . . . . . . . . . . . . . . . . 15 Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 WAIT Configuration During Burst Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Latency Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Asynchronous READ Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Single-Access Burst READ Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4-Word Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4-Word Burst READ Operation (with LB#/UB#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Continuous Burst READ with Output Delay, BCR[8] = 0(1) for End-of-Row Condition . . . . . . . . . . . . . 38 CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 LB#/UB#-Controlled Asynchronous WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Asynchronous WRITE Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Burst WRITE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Continuous Burst WRITE with Output Delay, BCR[8] = 0(1) for End-of-Row Condition . . . . . . . . . . . . 44 Burst WRITE Followed by Burst READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Asynchronous WRITE Followed By Burst READ--ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Burst READ Followed by Asynchronous WRITE (WE#-Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Burst READ Followed by Asynchronous WRITE Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Asynchronous WRITE Followed by Asynchronous READ--ADV# LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY General Description Micron CellularRAMTM products are high-speed, CMOS dynamic random access memories developed for low-power, portable applications. The MT45W4MW16BFB is a 64Mb device organized as 4 Meg x 16 bits; the MT45W2MW16BFB is a 32Mb device organized as 2 Meg x 16 bits. These devices include an industry-standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or Pseudo SRAM offerings. To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its coun- terpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. CellularRAM products include three system-accessible mechanisms used to minimize standby current. Partial array refresh (PAR) limits refresh to only that part of the DRAM array that contains essential data. Temperature compensated refresh (TCR) is used to adjust the refresh rate according to the case temperature. The refresh rate can be decreased at lower temperatures to minimize current consumption during standby. Deep powerdown (DPD) halts the refresh operation altogether and is used when no vital information is stored in the device. These three refresh mechanisms are accessed through the RCR. Figure 2: Functional Block Diagram--4 Meg x 16 and 2 Meg x 16 A[21:0] (for 64Mb) A[20:0] (for 32Mb) Address Decode Logic 4,096K x 16 (2,048K x 16) DRAM MEMORY ARRAY Input/ Output MUX and Buffers DQ[7:0] DQ[15:8] Refresh Configuration Register (RCR) Bus Configuration Register (BCR) CE# WE# OE# CLK ADV# CRE WAIT LB# UB# Control Logic NOTE: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed information. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY l 1: Table VFBGA Ball Descriptions VFBGA ASSIGNMENT SYMBOL TYPE DESCRIPTION A3, A4, A5, B3, B4, C3, C4, D4, H2, H3, H4, H5, G3, G4, F3, F4, E4, D3, H1, G2, H6, E3 J2 A[21:0] Input Address Inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the BCR or the RCR. On the 32Mb device, A21 (ball E3) is not internally connected. CLK Input J3 ADV# Input A6 CRE Input B5 CE# Input A2 OE# Input G5 WE# Input A1 B2 B6, C5, C6, D5, E5, F5, F6, G6, B1, C1, C2, D2, E2, F2, F1, G1 J1 LB# UB# DQ[15:0] Input Input Input/ Output Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is active. CLK is static (HIGH or LOW) during asynchronous access READ and WRITE operations and during PAGE READ ACCESS operations. Address Valid: Indicates that a valid address is present on the address inputs. Addresses can be latched on the rising edge of ADV# during asynchronous READ and WRITE operations. ADV# may be held LOW during asynchronous READ and WRITE operations. Configuration Register Enable: When CRE is HIGH, WRITE operations load the RCR or BCR. Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby or deep power-down mode. Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a configuration register or to the memory array. Lower Byte Enable. DQ[7:0] Upper Byte Enable. DQ[15:8] Data Inputs/Outputs. WAIT Output J4, J5, J6 D6 E1 E6 D1 NC VCC VCCQ VSS VSSQ - Supply Supply Supply Supply Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary. WAIT is also used to mask the delay associated with opening a new internal page. WAIT is asserted and should be ignored during asynchronous and page mode operations. WAIT is High-Z when CE# is HIGH. Not internally connected. Device Power Supply: (1.70V-1.95V) Power supply for device core operation. I/O Power Supply: (1.70V-1.95V) Power supply for input/output buffers. VSS must be connected to ground. VSSQ must be connected to ground. NOTE: The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. WAIT will be asserted but should be ignored during asynchronous and page mode operations. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 2: Bus Operations--Asynchronous Mode MODE POWER CLK1 ADV# CE# OE# WE# CRE LB#/ UB# WAIT2 DQ[15:0]3 NOTES Read Write Standby No Operation Configuration Register DPD Active Active Standby Idle Active X X X X X L L X X L L L H L L L X X X H H L X X L L L L L H L L X X X Low-Z Low-Z High-Z Low-Z Low-Z Data-Out Data-In High-Z X High-Z 4 4 5, 6 4, 6 Deep Power-Down X X H X X X X High-Z High-Z 7 Table 3: Bus Operations--Burst Mode MODE POWER CLK1 ADV# CE# OE# WE# CRE LB#/ UB# WAIT2 DQ[15:0]3 NOTES Async Read Async Write Standby No Operation Initial Burst Read Active Active Standby Idle Active X X X X L L X X L L L H L L L X X X X H L X X H L L L L L L L X X L Low-Z Low-Z High-Z Low-Z Low-Z Data-Out Data-In High-Z X Data-Out 4 4 5, 6 4, 6 4, 8 Initial Burst Write Active L L H L L X Low-Z Data-In 4, 8 Burst Continue Active H L X X L X Low-Z Data-In or Data-Out 4, 8 Burst Suspend Configuration Register Active Active X X L L L H H X L L H X X Low-Z Low-Z High-Z High-Z 4, 8 8 Deep Power-Down X X H X X X X High-Z High-Z 7 DPD NOTE: 1. CLK may be HIGH or LOW, but must be static during async read, async write, burst suspend, and DPD modes; and to achieve standby power during standby and active modes. 2. The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are affected. 4. The device will consume active power in this mode whenever addresses are changed. 5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve standby current. 7. DPD is maintained until RCR is reconfigured. 8. Burst mode operation is initialized through the bus configuration register (BCR[15]). 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Part-Numbering Information Micron CellularRAM devices are available in several different configurations and densities (see Figure 3). Figure 3: Part Number Chart MT 45 W 4M W 16 B FB -70 6 WT ES Production Status Micron Technology Blank = Production Product Family ES = Engineering Sample 45 = PSRAM/CellularRAM Memory MS = Mechanical Sample Operating Core Voltage Operating Temperature W = 1.70V-1.95V WT = -25C to +85C IT = -40 to +85C (contact factory) Address Locations Standby Power Options M = Megabits Blank = Standard Operating Voltage L = Low Power W = 1.70V-2.25V V = 2.30V-2.70V (contact factory) Frequency L = 2.70V-3.30V (contact factory) 6 = 66 MHz 8 = 80 MHz Bus Configuration 1 = 104 MHz (contact factory) 16 = x16 Access/Cycle Time READ/WRITE Operation Mode 60 = 60ns (contact factory) B = Asynchronous/Page/Burst 70 = 70ns 85 = 85ns Package Codes FB = VFBGA (6 x 9 grid, 0.75mm pitch, 6.0 x 8.0 x 1.0mm) 54-ball BB = Lead-free VFBGA (6 x 9 grid, 0.75mm pitch, 6.0 x 8.0 x 1.0mm) 54-ball (contact factory) Device Marking Due to the size of the package, the Micron standard part number is not printed on the top of the device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at www.micron.com/partsearch. To view the location of the abbreviated mark on the device, please refer to customer service note, CSN-11, Product Mark/ Label," at www.micron.com/csn. Valid Part Number combinations After building the part number from the part numbering chart above, please go to the Micron Part Marking Decoder Web site at www.micron.com/partsearch to verify that the part number is offered and valid. If the device required is not on this list, please contact the factory. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Functional Description In general, the MT45W4MW16BFB device and the MT45W2MW16BFB device are high-density alternatives to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The MT45W4MW16BFB device contains 67,108,864 bits organized as 4,194,304 addresses by 16 bits. The MT45W2MW16BFB contains 33,554,432 bits organized as 2,097,152 addresses by 16 bits. Both devices implement the same high-speed bus interface found on burst mode Flash products. The CellularRAM bus interface supports both asynchronous and burst mode transfers. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations (Figure 6) occur when CE#, WE#, and LB#/ UB# are driven LOW. During asynchronous WRITE operations, the OE# level is a "Don't Care," and WE# will override OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode disabled) can either use the ADV input to latch the address, or ADV can be driven LOW during the entire READ/WRITE operation. During asynchronous operation, the CLK input must be static (HIGH or LOW--no transitions). WAIT will be driven while the device is enabled and its state should be ignored. WE# LOW time must be limited to tCEM. Power-Up Initialization Figure 5: READ Operation (ADV = LOW) CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will configure the BCR and the RCR with their default settings (see Table 4 on page 17 and Table 7 on page 21). VCC and VCCQ must be applied simultaneously. When they reach a stable level at or above 1.70V, the device will require 150s to complete its self-initialization process. During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. CE# OE# WE# ADDRESS DATA Vcc VccQ DATA VALID LB#/UB# Figure 4: Power-Up Initialization Timing Vcc = 1.70V ADDRESS VALID tRC = READ Cycle Time tPU > 150s Device ready for Device Initialization normal operation DON'T CARE NOTE: ADV must remain LOW for page mode operation. Figure 6: WRITE Operation (ADV = LOW) Bus Operating Modes The MT45W4MW16BFB and MT45W2MW16BFB CellularRAM products incorporate a burst mode interface found on Flash products targeting low-power, wireless applications. This bus interface supports asynchronous, page mode, and burst mode read and write transfers. The specific interface supported is defined by the value loaded into the BCR. Page mode is controlled by the refresh configuration register (RCR[7]). CE# OE# < tCEM WE# ADDRESS DATA Asynchronous Mode DATA VALID LB#/UB# CellularRAM products power up in the asynchronous operating mode. This mode uses the industrystandard SRAM control bus (CE#, OE#, WE#, LB#/ UB#). READ operations (Figure 5) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN ADDRESS VALID tWC = WRITE Cycle Time DON'T CARE 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Page Mode READ Operation Burst Mode Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In pagemode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low-order address. Addresses A[3:0] are used to determine the members of the 16-address CellularRAM page. Any change in addresses A[4] or higher will initiate a new tAA access time. Figure 7 shows the timing for a page mode access. Page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. WRITE operations do not include comparable page mode functionality. During asynchronous page mode operation, the CLK input must be static (HIGH or LOW--no transitions). CE# must be driven HIGH upon completion of a page mode access. WAIT will be driven while the device is enabled and its state should be ignored. Page mode is enabled by setting RCR[7] to HIGH. WRITE operations do not include comparable page mode functionality. ADV must be driven LOW during all page mode read accesses. The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is latched on the next rising edge of CLK that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH, Figure 8 on page 11) or WRITE (WE# = LOW, Figure 9 on page 11). The size of a burst can be specified in the BCR as either fixed-length or continuous. Fixed-length bursts consist of four, eight, or sixteen words. Continuous bursts have the ability to start at a specified address and burst through the entire memory. The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between the processor and CellularRAM device. The WAIT output will be asserted as soon as a burst is initiated, and will be de-asserted to indicate when data is to be transferred into (or out of ) the memory. WAIT will again be asserted if the burst crosses the boundary between 128-word rows. Once the CellularRAM device has restored the previous row's data and accessed the next row, WAIT will be de-asserted and the burst can continue (see Figure 31 on page 38). The processor can access other devices without incurring the timing penalty of the initial latency for a new burst by suspending burst mode. Bursts are suspended by stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while the burst is suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT output will continue to be active, and as a result no other devices should directly share the WAIT connection to the controller. To continue the burst sequence, OE# is taken LOW, then CLK is restarted after valid data is available on the bus. The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM unless row boundaries are crossed at least every tCEM. If a burst suspension will cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle. Figure 7: Page Mode READ Operation (ADV = LOW) < tCEM CE# OE# WE# ADDRESS Add[0] tAA DATA Add[1] tAPA D[0] Add[2] tAPA D[1] Add[3] tAPA D[2] D[3] LB#/UB# DON'T CARE 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 8: Burst Mode READ (4-word burst)1 CLK A[21:0] ADDRESS VALID ADV# Latency Code 2 (3 clocks) CE# OE# WE# WAIT DQ[15:0] D[0] D[1] D[2] D[3] LB#/UB# DON'T CARE READ Burst Identified (WE# = HIGH) UNDEFINED NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Figure 9: Burst Mode WRITE (4-word burst)1 CLK A[21:0] ADDRESS VALID ADV# CE# Latency Code 2 (3 clocks) OE# WE# WAIT DQ[15:0] D[0] D[1] D[2] D[3] LB#/UB# DON'T CARE WRITE Burst Identified (WE# = LOW) NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Mixed-Mode Operation WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges. CE# must remain asserted during WAIT cycles (WAIT asserted and WAIT configuration BCR[8] = 1). Bringing CE# HIGH during WAIT cycles may cause data corruption. (Note that for BCR[8] = 0, the actual WAIT cycles end one cycle after WAIT de-asserts, and for row boundary crossings, start one cycle after the WAIT signal asserts.) The WAIT output also performs an arbitration role when a READ or WRITE operation is launched while an on-chip refresh is in progress. If a collision occurs, the WAIT pin is asserted for additional clock cycles until the refresh has completed (see Figures 11 and 12 on page 13). When the refresh operation has completed, the READ or WRITE operation will continue normally. WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary. The WAIT assertion allows time for the new row to be accessed, and permits any pending refresh operations to be performed. The device can support a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for synchronous operation. The asynchronous WRITE operation requires that the clock (CLK) remain static (HIGH or LOW) during the entire sequence. The ADV# signal can be used to latch the target address, or it can remain LOW during the entire WRITE operation. CE# must return HIGH when transitioning between mixed-mode operations. Note that the tCKA period is the same as a READ or WRITE cycle. This time is required to ensure adequate refresh. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash memory controllers. See Figure 39 on page 46 for the "Asynchronous WRITE Followed by Burst READ" timing diagram. WAIT Operation The WAIT output on a CellularRAM device is typically connected to a shared, system-level WAIT signal (see Figure 10 below). The shared WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. Figure 10: Wired or WAIT Configuration CellularRAM WAIT LB#/UB# Operation The LB# enable and UB# enable signals support byte-wide data transfers. During READ operations, the enabled byte(s) are driven onto the DQs. The DQs associated with a disabled byte are put into a High-Z state during a READ operation. During WRITE operations, any disabled bytes will not be transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW. External Pull-Up/ Pull-Down Resistor READY Processor WAIT WAIT Other Device Other Device Once a READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires additional time before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 11: Refresh Collision During READ Operation1 CLK A[21:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] VIH VIL VIH VALID ADDRESS VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High-Z VOH D[0] VOL D[1] Additional WAIT states inserted to allow refresh completion. D[2] D[3] UNDEFINED DON'T CARE NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Figure 12: Refresh Collision During WRITE Operation1 CLK A[21:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] VIH VIL VIH VIL VALID ADDRESS VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High-Z VOH D[0] VOL D[1] D[2] Additional WAIT states inserted to allow refresh completion. D[3] DON'T CARE NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Low-Power Operation Standby Mode Operation Deep Power-Down Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion of a READ or WRITE operation, or when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the address or control inputs. Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled by rewriting the RCR, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. During this 150s period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. DPD cannot be enabled or disabled by writing to the RCR using the software access sequence; the RCR should be accessed using CRE instead. Temperature Compensated Refresh Temperature compensated refresh (TCR) is used to adjust the refresh rate depending on the device operating temperature. DRAM technology requires increasingly frequent refresh operations to maintain data integrity as temperatures increase. More frequent refresh is required due to increased leakage of the DRAM capacitive storage elements as temperatures rise. A decreased refresh rate at lower temperatures will facilitate a savings in standby current. TCR allows for adequate refresh at four different temperature thresholds (+15C, +45C, +70C, and +85C). The setting selected must be for a temperature higher than the case temperature of the CellularRAM device. For example, if the case temperature is +50C, the system can minimize self refresh current consumption by selecting the +70C setting. The +15C and +45C settings would result in inadequate refreshing and cause data corruption. Configuration Registers Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up, and can be updated any time the devices are operating in a standby state. Access Using CRE The configuration registers are loaded using either a synchronous or an asynchronous WRITE operation when the configuration register enable (CRE) input is HIGH (see Figures 13 and 14 on page 15). When CRE is LOW, a READ or WRITE operation will access the memory array. The register values are placed on address pins A[21:0]. In an asynchronous WRITE, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are "Don't Care." Access using CRE is WRITE only. The BCR is accessed when A[19] is HIGH; the RCR is accessed when A[19] is LOW. Partial Array Refresh Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Tables 8 and 9 on page 22). READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new portions are available immediately upon writing to the RCR. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 13: Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY Operation CLK A[21:0] (except A19) OPCODE ADDRESS tAVH tAVS Select Control Register A191 ADDRESS tAVS CRE tAVH tVPH ADV# tVP tCBPH Initiate Control Register Access CE# tCW OE# tWP Write Address Bus Value to Control Register WE# LB#/UB# DQ[15:0] DATA VALID DON'T CARE NOTE: 1. A[19] = LOW to load RCR; A[19] = HIGH to load BCR. Figure 14: Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY Operation1 CLK Latch Control Register Value A[21:0] (except A19) OPCODE tHD tSP ADDRESS Latch Control Register Address A192 ADDRESS tSP CRE tSP ADV# tHD tHD tCBPH3 tCSP CE# OE# tSP WE# tHD LB#/UB# WAIT tCW High-Z High-Z DATA VALID DQ[15:0] DON'T CARE NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR. 3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored--additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Software Access Figure 15: Load Configuration Register Software access of the configuration registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configuration registers can be read or modified using the software sequence. The configuration registers are loaded using a fourstep sequence consisting of two asynchronous READ operations followed by two asynchronous WRITE operations (see Figure 15). The read sequence is virtually identical except that an asynchronous READ is performed during the fourth operation (see Figure 16). The address used during all READ and WRITE operations is the highest address of the CellularRAM device being accessed (3FFFFFh for 64Mb, and 1FFFFFh for 32Mb); the contents of this address are not changed by using this sequence. The data value presented during the third operation (WRITE) in the sequence defines whether the BCR or the RCR is to be accessed. If the data is 0000h, the sequence will access the RCR; if the data is 0001h, the sequence will access the BCR. During the fourth operation, the data bus is used to transfer data in to or out of the configuration registers. The use of the software sequence does not affect the ability to perform the standard (CRE-controlled) method of loading the configuration registers. However, the software nature of this access mechanism eliminates the need for the control register enable (CRE) pin. If the software mechanism is used, the CRE pin can simply be tied to VSS. The port line often used for CRE control purposes is no longer required. Software access of the RCR should not be used to enter or exit DPD. ADDRESS READ READ WRITE WRITE ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) XXXXh XXXXh CE# OE# WE# LB#/UB# DATA CR VALUE IN RCR: 0000h BCR: 0001h DON'T CARE Figure 16: Read Configuration Register ADDRESS READ READ WRITE READ ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) ADDRESS (MAX) CE# NOTE OE# WE# LB#/UB# DATA XXXXh CR VALUE OUT XXXXh RCR: 0000h BCR: 0001h DON'T CARE NOTE: CE# must be HIGH for 150ns before performing the cycle that reads a configuration register. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Bus Configuration Register The BCR is accessed using CRE and A[19] HIGH, or through the configuration register software sequence with DQ = 0001h on the third cycle. The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Table 4 on page 17 describes the control bits in the BCR. At power-up, the BCR is set to 9D4Fh. Table 4: Bus Configuration Register Definition A15 A[21:20] A19 A[18:16] 21-20 Reserved 18-16 19 Register Select Reserved 15 14 Operating Mode Must be set to "0" All must be set to "0" A14 A13 A12A11 A10 Reserved 13 12 11 Latency Counter Must be set to "0" BCR[13] BCR[12] BCR[11] 9 WAIT Polarity A7 Reserved A5 A6 7 8 WAIT Configuration (WC) Reserved Must be set to "0" A4 4 5 6 Clock Configuration (CC) Output Impedance Must be set to "0" Reserved A3 A2 A1 A0 3 2 1 0 Burst Burst Wrap (BW)* Length (BL)* Must be set to "0" Latency Counter 0 0 0 Code 0-Reserved 0 0 1 Code 1-Reserved 0 1 0 Code 2 0 1 1 Code 3 (Default) 1 0 0 Code 4-Reserved 1 0 1 Code 5-Reserved 1 1 0 Code 6-Reserved 1 1 1 Code 7-Reserved BCR[10] Burst Wrap (Note 1) BCR[3] 0 Burst wraps within the burst length 1 Burst no wrap (default) WAIT Polarity 0 Active LOW 1 Active HIGH (default) BCR[8] BCR[15] 10 A8 A9 Output Impedance BCR[5] 0 Full Drive (default) 1 1/4 Drive WAIT Configuration BCR[6] 0 Asserted during delay 1 Asserted one data cycle before delay (default) Clock Configuration 0 Not supported 1 Rising edge (default) Operation Mode 0 Synchronous burst access mode 1 Asynchronous access mode (default) BCR[2] Register Select BCR[19] 0 Select RCR 1 Select BCR BCR[1] BCR[0] Burst Length (Note 1) 0 0 1 4 words 0 1 0 8 words 0 1 1 16 words 1 1 1 Continuous burst (default) NOTE: 1. All burst WRITEs are continuous. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 5: Sequence and Burst Length BURST WRAP STARTING ADDRESS 4-WORD BURST LENGTH BCR[3] WRAP (DECIMAL) LINEAR LINEAR LINEAR LINEAR 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-... 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-4-5-6-7-... 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-5-6-7-8-... 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-6-7-8-9-... 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-7-8-9-10-... 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7-8-9-10-11-... 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-9-10-11-12- 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-10-11-12-13-... 0 Yes 8-WORD BURST LENGTH ... ... ... 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-17-18-19-20-.. 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-20-21.. 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-... 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-4-5-6-7-... 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 2-3-4-5-6-7-8-... 3 3-4-5-6 4 No CONTINUOUS BURST 14 15 1 16-WORD BURST LENGTH 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 4-5-6-7-8-9-10-... 5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20 5-6-7-8-9-10-11... 6 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21 6-7-8-9-10-11-12... 7 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13-14-...-17-18-19-20-21-22 7-8-9-10-11-12-13... ... ... ... 14 14-15-16-17-18-19-...-23-24-25-26-27-28-29 14-15-16-17-18-19-20-... 15 15-16-17-18-19-20-...-24-25-26-27-28-29-30 15-16-17-18-19-20-21-... Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength The output driver strength can be altered to adjust for different data bus loading scenarios. The reducedstrength option will be more than adequate in stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-drive-strength option is included to minimize noise generated on the data bus during READ operations. Normal output impedance should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Partial drive is approximately one-quarter full drive strength. Outputs are configured at full drive strength during testing. Burst Length (BCR[2:0]) Default = Continuous Burst Burst lengths define the number of words the device outputs during a burst READ operation. The device supports a burst length of 4, 8, or 16 words. The device can also be set in continuous burst mode where data is output sequentially without regard to address boundaries; the internal address wraps to 000000h if the device is read past the last address. WRITE bursts are always performed using continuous burst mode. Burst Wrap (BCR[3]) Default = Burst No Wrap The burst wrap option determines if a 4-, 8-, or 16word burst READ wraps within the burst length, or steps through sequential addresses. If the wrap option is not enabled, the device outputs data from sequential addresses without regard to burst boundaries; the internal address wraps to 000000h if the device is read past the last address. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively (Figures 17 and 19). When A8 = 1, the WAIT signal transitions one clock period prior to the data bus going valid or invalid (Figures 18 and 16). Figure 17: WAIT Configuration (BCR[8] = 0) WAIT Polarity (BCR[10]) Default = WAIT Active HIGH The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state. Figure 18: WAIT Configuration (BCR[8] = 1) CLK WAIT DQ[15:0] High-Z Data[0] Data[1] Data immediately valid (or invalid) NOTE: 1. Note: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 19. CLK WAIT D[15:0] High-Z Data[0] Data valid (or invalid) after one clock delay NOTE: 1. Note: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 19. Figure 19: WAIT Configuration During Burst Operation1 CLK BCR[8] = 0 DATA VALID IN CURRENT CYCLE WAIT BCR[8] = 1 DATA VALID IN NEXT CYCLE WAIT DQ[15:0] D[0] D[1] D[2] D[3] D[4] DON'T CARE NOTE: 1. Non-default BCR setting: WAIT active LOW. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Operating Mode (BCR[15]) Default = Asynchronous Operation The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation. Latency Counter (BCR[13:11]) Default = Three-Clock Latency The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred. Only latency code two (three clocks) or latency code three (four clocks) is allowed (see Table 6 and Figure 20 below). Table 6: Latency Configuration MAX INPUT CLK FREQUENCY (MHz) LATENCY CONFIGURATION CODE -701 -708 -706, -856 2 (3 clocks) 66 (15.2ns) 3 (4 clocks) - default 104 (9.62ns) 53 (18.75ns) 80 (12.5ns) 441 (22.7ns) 66 (15.2ns) NOTE: 1. Clock rates below 50 MHz are allowed as long as tCSP specifications are met. Figure 20: Latency Counter CLK A[21:0] ADV# VIH VIL VIH VIL VALID ADDRESS VIH VIL Code 2 DQ[15:0] VOH VALID OUTPUT VOL Code 3 DQ[15:0] VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT (Default) VOH VOL DON'T CARE 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 20 UNDEFINED Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Refresh Configuration Register Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Tables 8 and 9 on page 22). The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Table 7 below describes the control bits used in the RCR. At power-up, the RCR is set to 0070h. The RCR is accessed using CRE and A[19] LOW; or through the configuration register software access sequence with DQ = 0000h on the third cycle (see Configuration Registers on page 14.) Table 7: Refresh Configuration Register Mapping A[21:20] 21-20 RESERVED A19 19 Register Select A[18:8] 18-8 RESERVED A6 A7 7 PAGE 6 A5 A4 5 TCR 4 Select RCR 1 Select BCR RCR[7] A0 0 1 2 RESERVED Address Bus Read Configuration Register PAR Must be set to "0" Refresh Coverage RCR[2] RCR[1] RCR[0] 0 0 0 Full array (default) 0 0 1 Bottom 1/2 array 0 1 0 Bottom 1/4 array 0 1 1 Bottom 1/8 array Register Select 0 A1 A2 3 DPD All must be set to "0" All must be set to "0" RCR[19] A3 Page Mode Enable/Disable 1 0 0 None of array 1 0 1 Top 1/2 array 0 Page Mode Disabled (default) 1 1 0 Top 1/4 array 1 Page Mode Enable 1 1 1 Top 1/8 array RCR[6] RCR[5] Maximum Case Temp. RCR[4] Deep Power-Down 1 1 +85C (default) 0 DPD Enable 0 0 +70C 1 DPD Disable (default) 0 1 +45C 1 0 +15C 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 8: 64Mb Address Patterns for PAR (RCR[4] = 1) RCR[2] RCR[1] RCR[0] ACTIVE SECTION ADDRESS SPACE SIZE DENSITY 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Full die One-half of die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die 000000h-3FFFFFh 000000h-1FFFFFh 000000h-0FFFFFh 000000h-07FFFFh 0 200000h-3FFFFFh 300000h-3FFFFFh 380000h-3FFFFFh 4 Meg x 16 2 Meg x 16 1 Meg x 16 512K x 16 0 Meg x 16 2 Meg x 16 1 Meg x 16 521K x 16 64Mb 32Mb 16Mb 8Mb 0Mb 32Mb 16Mb 8Mb Table 9: 32Mb Address Patterns for PAR (RCR[4] = 1) RCR[2] RCR[1] RCR[0] ACTIVE SECTION ADDRESS SPACE SIZE DENSITY 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Full die One-half of die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die 000000h-1FFFFFh 000000h-0FFFFFh 000000h-07FFFFh 000000h-03FFFFh 0 100000h-1FFFFFh 180000h-1FFFFFh 1C0000h-1FFFFFh 2 Meg x 16 1 Meg x 16 512K x 16 256K x 16 0 Meg x 16 1 Meg x 16 512K x 16 256K x 16 32Mb 16Mb 8Mb 4Mb 0Mb 16Mb 8Mb 4Mb Temperature Compensated Refresh (RCR[6:5]) Default = +85C Operation The TCR bits allow for adequate refresh at four different temperature thresholds (+15C, +45C, +70C, and +85C). The setting selected must be for a temperature higher than the case temperature of the CellularRAM device. If the case temperature is +50C, the system can minimize self refresh current consumption by selecting the +70C setting. The +15C and +45C settings would result in inadequate refreshing and cause data corruption. Deep Power-Down (RCR[4]) Default = DPD Disabled The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. Deep power-down is enabled when RCR[4] = 0, and remains enabled until RCR[4] is set to "1." DPD should not be enabled or disabled with the software access sequence; instead, use CRE to access the RCR. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN Page Mode Operation (RCR[7]) Default = Disabled The page mode operation bit determines whether page mode is enabled for asynchronous READ operations. In the power-up default state, page mode is disabled. 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Absolute Maximum Ratings* *Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage to Any Ball Except VCC, VCCQ Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50V to (4.0V or VCCQ + 0.3V, whichever is less) Voltage on VCC Supply Relative to VSS . . -0.2V to +2.45V Voltage on VCCQ Supply Relative to VSS . -0.2V to +4.0V Storage Temperature (plastic). . . . . . . . -55C to +150C Operating Temperature (case) Wireless. . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C Industrial . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Soldering Temperature and Time 10s (lead only) . . . . . . . . . . . . . . . . . . . . . . . . . . . +260C Table 10: Electrical Characteristics and Operating Conditions Wireless Temperature (-25C < TC < +85C); Industrial Temperature (-40C < TC < +85C) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS 1.70 1.95 V W: 1.8V 1.70 2.25 V V: 2.5V 2.30 2.70 V L: 3.0V 2.70 3.30 V VCC Supply Voltage VCCQ I/O Supply Voltage NOTES Input High Voltage VIH 1.40 VCCQ + 0.2 V 1 Input Low Voltage VIL -0.20 0.4 V 2 0.80 VCCQ Output High Voltage IOH = -0.2mA VOH V 3 Output Low Voltage IOL = +0.2mA VOL 0.20 VCCQ V 3 VIN = 0 to VCCQ ILI 1 A OE# = VIH or Chip Disabled ILO 1 A VIN = VCCQ or 0V Chip Enabled, IOUT = 0 ICC1 -70 25 mA 4 -85 20 mA 4 mA 4 mA 4 A 5 Input Leakage Current Output Leakage Current Operating Current Asynchronous Random READ/WRITE Asynchronous Page READ ICC2 Initial Access, Burst READ/WRITE ICC3 Continuous Burst READ/WRITE Standby Current ICC1P VIN = VCCQ or 0V CE# = VCCQ ISB -70 15 -85 12 104 MHz 35 80 MHz 35 66 MHz 30 104 MHz 20 80 MHz 18 66 MHz 15 64Mb--Std 120 64Mb--Opt. L 100 32MB--Std 110 32Mb--Opt. L 90 NOTE: 1. 2. 3. 4. Input signals may overshoot to VccQ + 1.0V for periods less than 2ns during transitions. Input signals may undershoot to Vss - 1.0V for periods less than 2ns during transitions BCR[5:4] = 00b. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. 5. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85C. In order to achieve low standby current, all inputs must be driven to either VCCQ or VSS. ISB might be slightly higher for up to 500ms after power-up, or after changes to the PAR array partition. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 11: Temperature Compensated Refresh Specifications and Conditions DESCRIPTION Temperature Compensated Refresh Standby Current CONDITIONS VIN = VCCQ or 0V CE# = VCCQ SYMBOL DENSITY ITCR STANDARD LOW-POWER MAX CASE POWER OPTION TEMPERATURES (NO DESIG.) (L) 64Mb +85C +70C +45C +15C +85C +70C +45C +15C 32Mb 120 105 85 70 110 95 80 70 100 85 65 50 90 75 60 50 UNITS A A A A A A A A NOTE: ITCR (MAX) values measured with PAR set to FULL ARRAY. Table 12: Partial Array Refresh Specifications and Conditions DESCRIPTION Partial Array Refresh Standby Current CONDITIONS VIN = VCCQ or 0V, CE# = VCCQ SYMBOL DENSITY IPAR ARRAY PARTITION Full 1/2 1/4 1/8 0 Full 1/2 1/4 1/8 0 64Mb 32Mb STANDARD LOW-POWER POWER OPTION (NO DESIG.) (L) 120 115 110 105 70 110 105 100 95 70 100 95 90 85 50 90 85 80 75 50 UNITS A A A A A A A A A A NOTE: IPAR (MAX) values measured with TCR set to 85C. IPAR might be slightly higher for up to 500ms after changes to the PAR array partition. Table 13: Deep Power-Down Specifications DESCRIPTION Deep Power-Down 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN CONDITIONS SYMBOL TYP UNITS VIN = VCCQ or 0V; +25C IZZ 10 A 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 14: Capacitance DESCRIPTION Input Capacitance Input/Output Capacitance (DQ) CONDITIONS SYMBOL MIN MAX UNITS NOTES TC = +25C; f = 1 MHz; VIN = 0V CIN CIO 2.0 3.5 6 6 pF pF 1 1 NOTE: 1. These parameters are verified in device characterization and are not 100% tested. Figure 21: AC Input/Output Reference Waveform VCCQ Input 1 VCC/2 2 VCCQ/2 Test Points 3 Output VSS NOTE: 1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at VCC/2. Due to the possibility of a difference between VCC and VCCQ, the input test point may not be shown to scale. 3. Output timing ends at VCCQ/2. Figure 22: Output Load Circuit Table 15: Output Load Circuit VccQ R1 Test Point DUT 30pF R2 VCCQ R1/R2 1.8V 2.5V 3.0V 2.7K 3.7K 4.5K NOTE: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 16: Asynchronous READ Cycle Timing Requirements1 -70x PARAMETER SYMBOL Address Access Time tAA 70 85 ns ADV# Access Time t AADV 70 85 ns Page Access Time t APA 20 25 ns Address Hold from ADV# HIGH t AVH 5 5 ns Address Setup to ADV# HIGH t AVS 10 10 ns LB#/UB# Access Time tBA LB#/UB# Disable to DQ High-Z Output tBHZ LB#/UB# Enable to Low-Z Output t Maximum CE# Pulse Width tCEM CE# LOW to WAIT Valid tCEW BLZ MIN -856 MAX MIN UNITS NOTES 70 85 ns 8 8 ns 4 ns 3 8 s 2 7.5 ns 85 ns 10 10 8 1 MAX 7.5 1 70 Chip Select Access Time tCO CE# HIGH between Subsequent Asynchronous Operations tCPH 5 5 ns CE# LOW to ADV# HIGH tCVS 10 10 ns Chip Disable to DQ and WAIT High-Z Output tHZ Chip Enable to Low-Z Output tLZ Output Enable to Valid Output tOE Output Hold from Address Change tOH Output Disable to DQ High-Z Output tOHZ Output Enable to Low-Z Output tOLZ 5 Page Cycle Time tPC READ Cycle Time tRC ADV# Pulse Width LOW tVP ADV# Pulse Width HIGH tVPH 8 10 8 10 20 5 20 5 8 ns 4 ns 3 ns ns 8 ns 4 5 ns 3 20 25 ns 70 85 ns 10 10 ns 10 10 ns NOTE: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). 2. Page-mode enabled only. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 22 on page 25. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 4. Low-Z to High-Z timings are tested with the circuit shown in Figure 22 on page 25. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 17: Burst READ Cycle Timing Requirements1 -701 MIN -708 PARAMETER SYMBOL Burst to READ Access Time tABA MAX 35 CLK to Output Delay t 7 Burst OE# LOW to Output Delay t 20 CE# HIGH between Subsequent Mixed-Mode Operations Maximum CE# Pulse Width t CE# LOW to WAIT Valid t CLK Period ACLK BOE CBPH 5 MIN -706, -856 MAX MAX UNITS 46.5 56 ns 9 11 ns 20 20 ns 5 8 tCEM MIN 5 8 ns 2 8 s 2 1 7.5 1 7.5 1 7.5 ns tCLK 9.62 20 12.5 20 15 20 ns CE# Setup Time to Active CLK Edge tCSP 4 20 4.5 20 5 20 ns Hold Time from Active CLK Edge tHD 2 Chip Disable to DQ and WAIT High-Z Output CLK Rise or Fall Time tHZ CEW 2 NOTES 2 3 ns 8 8 8 ns tKHKL 1.6 1.6 1.6 ns CLK to WAIT Valid tKHTL 7 9 11 ns CLK to DQ High-Z Output tKHZ 3 8 3 8 3 8 ns 4 CLK to Low-Z Output tKLZ 2 5 2 5 2 5 ns 5 Output HOLD from CLK tKOH 2 2 2 ns CLK HIGH or LOW Time tKP 3 4 5 ns Output Disable to DQ High-Z Output tOHZ Output Enable to Low-Z Output tOLZ 5 5 Setup Time to Active CLK Edge tSP 3 3 8 8 8 4 ns 4 5 ns 5 3 ns NOTE: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). 2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. 3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. 4. Low-Z to High-Z timings are tested with the circuit shown in Figure 22 on page 25. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 5. High-Z to Low-Z timings are tested with the circuit shown in Figure 22 on page 25. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 18: Asynchronous WRITE Cycle Timing Requirements -70x PARAMETER SYMBOL Address and ADV# LOW Setup Time t 0 0 ns Address Hold from ADV# Going HIGH t 5 5 ns Address Setup to ADV# Going HIGH tAVS 10 10 ns Address Valid to End of Write t 70 85 ns LB#/UB# Select to End of Write t 70 85 ns CE# LOW to WAIT Valid t 1 Async Address-to-Burst Transition Time t CKA 70 85 ns CE# Low to ADV# HIGH tCVS 10 10 ns Chip Enable to End of Write tCW 70 85 ns Data Hold from Write Time tDH 0 0 ns Data WRITE Setup Time tDW 23 23 ns Chip Disable to WAIT High-Z Output tHZ Chip Enable to Low-Z Output tLZ End WRITE to Low-Z Output tOW ADV# Pulse Width AS AVH AW BW CEW MIN -856 MAX 7.5 MIN 1 8 MAX 7.5 8 UNITS NOTES ns ns 10 10 ns 1 5 5 ns 1 tVP 10 10 ns ADV# Pulse Width HIGH tVPH 10 10 ns ADV# Setup to End of WRITE tVS 70 85 ns WRITE Cycle Time tWC 70 85 ns WRITE to DQ High-Z Output tWHZ WRITE Pulse Width tWP 46 WRITE Pulse Width HIGH tWPH WRITE Recovery Time tWR 8 8 ns 2 55 ns 3 10 10 ns 0 0 ns NOTE: 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 22 on page 25. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 22 on page 25. The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2. 3. WE# LOW time must be limited to tCEM (8s). 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Table 19: Burst WRITE Cycle Timing Requirements -701 MAX SYMBOL CE# HIGH between Subsequent Mixed-Mode Operations Minimum CE# Pulse Width t CE# LOW to WAIT Valid t CEW 1 7.5 1 7.5 Clock Period t CLK 9.62 20 12.5 CE# Setup to CLK Active Edge t CSP 4 20 4.5 Hold Time from Active CLK Edge tHD 2 Chip Disable to WAIT High-Z Output t CLK Rise or Fall Time 5 MIN -706, -856 PARAMETER CBPH MIN -708 MAX UNITS NOTES ns 1 8 s 1 1 7.5 ns 20 15 20 ns 20 5 20 ns 5 8 tCEM MIN MAX 5 8 2 2 ns 8 8 8 ns tKHKL 1.6 1.6 1.6 ns Clock to WAIT Valid tKHTL 7 9 11 ns CLK HIGH or LOW Time tKP 3 4 5 ns Setup Time to Activate CLK Edge tSP 3 3 3 ns HZ 2 NOTE: 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY TIMING DIAGRAMS Figure 23: Initialization Period Vcc (MIN) Vcc, VccQ = 1.70V tPU Device ready for normal operation Table 20: Initialization Timing Parameters -70x PARAMETER SYMBOL Initialization Period (required before normal operations) tPU 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 30 MIN -856 MAX 150 MIN MAX UNITS 150 s NOTE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 24: Asynchronous READ tRC VIH A[21:0] VALID ADDRESS VIL tAA ADV# VIH VIL tCBPH CE# tHZ VIH VIL LB#/UB# tCO tBA VIH tBHZ VIL tOE OE# WE# tOHZ VIH VIL VIH VIL tBLZ tOLZ tLZ VOH DQ[15:0] High-Z VOL VALID OUTPUT tCEW tHZ VIH WAIT High-Z VIL High-Z DON'T CARE UNDEFINED Table 21: Asynchronous READ Timing Parameters -70x SYMBOL MIN -856 MAX MIN -70x MAX UNITS SYMBOL MIN -856 MAX MIN AA 70 85 ns 70 85 ns tLZ 8 8 ns t OE 20 20 ns 8 8 ns BHZ HZ 10 10 ns tOHZ tCBPH 5 5 ns tOLZ t 1 7.5 ns t 85 ns tBLZ CEW tCO 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 7.5 70 1 31 RC 10 8 UNITS tBA t 8 MAX t t 10 ns ns 5 5 ns 70 85 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 25: Asynchronous READ Using ADV# VIH A[21:0] VALID ADDRESS VIL tAA tAVS tVPH tAVH VIH ADV# VIL tAADV tVP tCBPH tCVS tHZ VIH CE# VIL tCO tBA tBHZ VIH LB#/UB# VIL tOE tOHZ VIH OE# VIL VIH WE# tOLZ tBLZ VIL tLZ VOH DQ[15:0] High-Z VALID OUTPUT VOL tCEW tHZ VIH WAIT High-Z VIL High-Z DON'T CARE UNDEFINED Table 22: Asynchronous READ Timing Parameters Using ADV# -70x SYMBOL tAA tAADV t AVH tAVS MIN -856 MAX MIN -70x MAX UNITS SYMBOL 70 85 ns tCO 70 85 ns tCVS 5 5 ns t 10 10 ns tLZ MIN -856 MAX MIN 70 10 UNITS 85 ns 10 8 HZ MAX 10 ns 8 10 ns ns BA 70 85 ns t OE 20 20 ns tBHZ 8 8 ns tOHZ 8 8 ns t tBLZ t CBPH tCEW 10 10 ns tOLZ 5 5 ns t ns 1 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 7.5 1 7.5 32 5 5 ns VP 10 10 ns tVPH 10 10 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 26: Page Mode READ tRC A[21:4] VIH VALID ADDRESS VIL VIH A[3:0] ADV# VALID ADDRESS VIL VALID ADDRESS VALID ADDRESS tPC tAA VIH VALID ADDRESS VIL tCEM VIH tCBPH tHZ tCO tCBPH CE# VIL LB#/UB# tBA VIH tBHZ VIL tOHZ tOE VIH OE# VIL VIH WE# tOLZ tBLZ VIL VOH DQ[15:0] tAPA tOH tLZ VALID OUTPUT High-Z VOL VALID OUTPUT tCEW VALID OUTPUT tHZ VIH WAIT VALID OUTPUT High-Z VIL High-Z DON'T CARE UNDEFINED Table 23: Asynchronous READ Timing Parameters--Page Mode Operation -70x SYMBOL MIN -856 MAX MIN -70x MAX UNITS SYMBOL tAA 70 85 ns tHZ t 20 25 ns t 70 85 ns tOE 8 8 ns t APA tBA t BHZ tBLZ tCBPH t OH 10 10 ns tOHZ 5 5 ns tOLZ 8 CEM tCEW LZ 1 tCO 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 7.5 70 1 MIN -856 MAX MIN 8 10 UNITS 8 ns 10 20 5 ns 20 5 8 5 MAX ns ns 8 ns 5 ns 8 s t PC 20 25 ns 7.5 ns tRC 70 85 ns 85 ns 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 27: Single-Access Burst READ Operation1 tCLK tKP tKP tKHKL VIH CLK A[21:0] VIL tSP VIH VALID ADDRESS VIL tSP VIH ADV# tHD tHD VIL tHD tCEM CE# tCSP VIH tHZ tABA VIL tBOE tOHZ VIH OE# VIL tSP WE# tHD tOLZ VIH VIL tHD tSP VIH LB#/UB# VIL tCEW VOH WAIT tKHTL High-Z High-Z VOL DQ[15:0] tKOH tACLK VOH VALID OUTPUT High-Z VOL READ Burst Identified (WE# = HIGH) DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 24: Burst READ Timing Parameters--Single Access -701 SYMBOL -706, -856 -708 -701 MIN MAX MIN MAX MIN MAX UNITS SYMBOL MIN MAX MIN MAX MIN MAX UNITS ABA 35 46.5 56 ns t tACLK 7 9 11 ns 20 20 20 8 8 t tBOE -706, -856 -708 8 8 8 ns tKHKL 1.6 1.6 1.6 ns ns tKHTL 7 9 11 ns 2 2 2 ns 3 4 5 ns HZ 8 s t 1 7.5 1 7.5 1 7.5 ns t 9.62 20 12.5 20 15 20 ns tOHZ t CSP 4 20 4.5 20 5 20 ns t 5 5 5 ns tHD 2 ns tSP 3 3 3 ns t CEM t CEW tCLK 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 2 2 KOH KP OLZ 34 8 8 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 28: 4-Word Burst READ Operation1 tKHKL CLK A[21:0] tKP VIL tSP VIH tHD VALID ADDRESS VIL tSP ADV# tKP tCLK VIH tHD VIH VIL tCEM CE# VIH tHD tABA tCSP VIL tCBPH tHZ tBOE OE# WE# LB#/UB# VIH VIL tOHZ tSP tHD tSP tHD tOLZ VIH VIL VIH VIL tKHTL tCEW WAIT VOH High-Z VOL High-Z tACLK DQ[15:0] VOH VALID OUTPUT High-Z VOL tKOH VALID OUTPUT VALID OUTPUT READ Burst Identified (WE# = HIGH) VALID OUTPUT DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 25: Burst READ Timing Parameters--4-Word Burst -701 SYMBOL -708 -706, -856 -701 MIN MAX MIN MAX MIN MAX UNITS SYMBOL 35 46.5 56 ns tHZ t 7 9 11 ns t 20 20 20 tABA ACLK BOE t CBPH 5 5 8 tCEM -706, -856 MIN MAX MIN MAX MIN MAX UNITS 8 8 8 ns t 1.6 1.6 1.6 ns ns t 7 9 11 ns ns t 2 2 2 ns 8 s tKP 3 4 5 ns 5 8 -708 KHKL KHTL KOH t 1 7.5 1 7.5 1 7.5 ns t t 9.62 20 12.5 20 15 20 ns t 5 5 5 ns t CSP 4 20 4.5 20 5 20 ns t 3 3 3 ns tHD 2 CEW CLK 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 2 2 8 OHZ OLZ SP 8 8 ns ns 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 29: 4-Word Burst READ Operation (with LB#/UB#)1 tCLK CLK A[21:0] VIH VIL tHD tSP VIH VALID ADDRESS VIL tHD tSP ADV# VIH VIL tCEM CE# VIH tHD tABA tCSP VIL tCBPH tHZ tBOE OE# WE# LB#/UB# VIH VIL tOHZ tSP tHD tSP tHD tOLZ VIH VIL VIH VIL tCEW WAIT tKHTL VOH High-Z VOL High-Z tKOH tACLK DQ[15:0] VOH VALID OUTPUT High-Z VOL tKHZ tKHZ tKLZ VALID OUTPUT VALID OUTPUT High-Z READ Burst Identified (WE# = HIGH) DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. BCR configured with a burst length of four. Table 26: Burst READ Timing Parameters--4-Word Burst with LB#/UB# -701 SYMBOL MIN -706, -856 -708 MAX MIN MAX MIN -701 MAX UNITS SYMBOL MIN -706, -856 -708 MAX MIN MAX MIN MAX UNITS ABA 35 46.5 56 ns t HZ 8 8 8 ns t ACLK 7 9 11 ns t KHTL 7 9 11 ns t BOE 20 20 20 ns t KHZ 3 8 3 8 3 8 ns t CBPH ns t KLZ 2 5 2 5 2 5 ns KOH 2 t t 5 8 5 8 s t 1 7.5 1 7.5 1 7.5 ns tOHZ CEM tCEW 5 8 CLK 9.62 20 12.5 20 15 20 ns t tCSP 4 20 4.5 20 5 20 ns tSP t 2 t HD 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 2 2 OLZ 2 8 2 8 ns 8 ns 5 5 5 ns 3 3 3 ns ns 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 30: READ Burst Suspend1 tCLK VIH CLK VIL tSP VIH A[21:0] VIL tHD VALID ADDRESS VALID ADDRESS tSP tHD VIH ADV# VIL tCEM tCBPH tHZ tCSP VIH CE# VIL tOHZ OE# tOHZ VIH VIL tSP VIH tHD WE# VIL tSP tHD VIH LB#/UB# VIL tBOE VOH tOLZ WAIT VOL High-Z High-Z tKOH VOH DQ[15:0] VOL VALID OUTPUT High-Z VALID OUTPUT tBOE tOLZ VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT tACLK DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 27: Burst READ Timing Parameters--Burst Suspend -701 -708 -706, -856 -701 SYMBOL MIN MAX MIN MAX MIN MAX UNITS tACLK t BOE tCBPH 9 11 ns tHD 20 20 20 ns t ns tKOH 8 s tOHZ 5 8 tCEM 5 8 -706, -856 SYMBOL MIN MAX MIN MAX MIN MAX UNITS 7 5 -708 2 2 8 HZ 2 2 8 2 8 ns 8 2 8 ns ns 8 ns CLK 9.62 20 12.5 20 15 20 ns t 5 5 5 ns tCSP 4 20 4.5 20 5 20 ns tSP 3 3 3 ns t 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN OLZ 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 31: Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition1 CLK VIH VIL tCLK A[21:0] VIH VIL ADV# VIH VIL LB#/UB# VIH VIL CE# VIH NOTE 4 VIL OE# VIH VIL WE# VIH VIL tKHTL tKHTL WAIT VOH NOTE 3 VOL DQ[15:0] VOH VALID OUTPUT VOL VALID OUTPUT VALID OUTPUT VALID OUTPUT tKOH tACLK DON'T CARE NOTE: 1. 2. 3. 4. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. WAIT will be asserted (2 x LC) cycles (BCR[8] = 0; WAIT asserted during delay). LC = Latency Code (BCR[13:11]). CE# must not remain LOW longer than tCEM. Table 28: Burst READ Timing Parameters--BCR[8] = 0 -701 -708 -706, -856 -701 SYMBOL MIN MAX MIN MAX MIN MAX UNITS 7 tACLK t CLK 9.62 20 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 9 12.5 20 15 -708 -706, -856 SYMBOL MIN MAX MIN MAX MIN MAX UNITS 11 ns tKHTL 20 ns t KOH 38 7 2 9 2 11 2 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 32: CE#-Controlled Asynchronous WRITE tWC A[21:0] VIH VALID ADDRESS VIL tAW tWR tAS VIH ADV# VIL tCW CE# VIH VIL tBW VIH LB#/UB# OE# VIL VIH VIL tWPH tWP VIH WE# VIL tDH tDW DQ[15:0] IN VIH DQ[15:0] OUT VOH High-Z VIL tWHZ tLZ WAIT VALID INPUT VOL tCEW VIH tHZ High-Z VIL High-Z DON'T CARE Table 29: Asynchronous WRITE Timing Parameters--CE#-Controlled -70x SYMBOL MIN -856 MAX MIN -70x MAX UNITS SYMBOL MIN -856 MAX MIN UNITS 8 ns AS 0 ns t tAW 70 85 ns tLZ 10 10 ns t BW 70 85 ns t 70 85 ns tCEW 1 ns tWHZ 7.5 1 7.5 8 MAX 0 t HZ WC 8 8 ns 70 85 ns tWP 46 55 ns DH 0 0 ns t 10 10 ns tDW 23 23 ns tWR 0 0 ns tCW t 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN WPH 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 33: LB#/UB#-Controlled Asynchronous WRITE tWC A[21:0] VIH VALID ADDRESS VIL tAW tAS ADV# tWR VIH VIL tCW CE# LB#/UB# OE# VIH VIL tBW VIH VIL VIH VIL tWP tWPH VIH WE# VIL tDW DQ[15:0] IN VIH DQ[15:0] OUT VOH High-Z VIL tDH VALID INPUT tWHZ tLZ VOL tCEW tHZ VIH WAIT High-Z VIL High-Z DON'T CARE Table 30: Asynchronous WRITE Timing Parameters--LB#/UB#-Controlled -70x SYMBOL MIN -856 MAX MIN -70x MAX UNITS SYMBOL MIN -856 MAX MIN UNITS 8 ns 0 0 ns tHZ AW 70 85 ns t LZ 10 10 ns tBW 70 85 ns tWC 70 85 ns ns tWHZ 46 55 ns 10 10 ns 0 0 ns tAS t tCEW 1 7.5 1 7.5 8 MAX tCW 70 85 ns tWP tDH 0 0 ns tWPH 23 23 ns t t DW 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 40 WR 8 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 34: WE#-Controlled Asynchronous WRITE tWC VIH A[21:0] VALID ADDRESS VIL tAW tWR VIH ADV# VIL tCW VIH CE# VIL tBW VIH LB#/UB# VIL VIH OE# VIL tAS tWP tWPH VIH WE# VIL tDH tDW DQ[15:0] IN VIH High-Z VIL tOW tWHZ tLZ DQ[15:0] OUT VALID INPUT VOH VOL tCEW tHZ VIH WAIT High-Z VIL High-Z DON'T CARE Table 31: Asynchronous WRITE Timing Parameters--WE#-Controlled -70x SYMBOL MIN -856 MAX MIN -70x MAX UNITS SYMBOL MIN -856 MAX MAX 0 ns AW 70 85 ns t OW 5 5 ns tBW 70 85 ns tWC 70 85 ns ns tWHZ tCEW 1 7.5 1 7.5 10 UNITS 0 t 10 MIN tLZ tAS 8 ns 8 ns 70 85 ns t WP 46 55 ns tDH 0 0 ns tWPH 10 10 ns tDW 23 23 ns tWR 0 0 ns t CW tHZ 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 8 8 ns 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 35: Asynchronous WRITE Using ADV# A[21:0] VIH VALID ADDRESS VIL tAVH tAVS tVS tVPH ADV# tVP tAS VIH VIL tAS tAW tCW VIH CE# VIL tBW VIH LB#/UB# OE# VIL VIH VIL tWPH tWP WE# VIH VIL tDW DQ[15:0] VIH IN VIL DQ[15:0] VOH OUT VOL High-Z VALID INPUT tWHZ tLZ tOW tCEW WAIT tDH tHZ VIH High-Z VIL High-Z DON'T CARE Table 32: Asynchronous WRITE Timing Parameters Using ADV# -70x SYMBOL t AS tAVH MIN -856 MAX MIN -70x MAX UNITS SYMBOL 0 0 ns t 5 5 ns tLZ MIN -856 MAX MIN 8 HZ 10 MAX UNITS 8 ns 10 ns AVS 10 10 ns t 5 5 ns tAW 70 85 ns tVP 10 10 ns tBW 70 85 ns tVPH 10 10 ns ns tVS 70 85 ns t tCEW 1 7.5 1 7.5 OW 70 85 ns tWHZ DH 0 0 ns t WP 46 55 ns tDW 23 23 ns tWPH 10 10 ns tCW t 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 42 8 8 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 36: Burst WRITE Operation1 tCLK CLK tKP tKP tKHKL VIH VIL tSP A[21:0] VALID ADDRESS VIL ADV# tHD VIH tSP VIH tHD VIL LB#/UB# tSP tHD VIH VIL tHD tCSP CE# tCBPH tCEM VIH VIL OE# VIH VIL tSP WE# tHD VIH VIL tKHTL tCEW VOH WAIT tHZ High-Z VOL High-Z tHD tSP VIH DQ[15:0] D[0] VIL D[1] D[2] D[3] WRITE Burst Identified (WE# = LOW) DON'T CARE NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 33: Burst WRITE Timing Parameters -701 -708 -706, -856 -701 SYMBOL MIN MAX MIN MAX MIN MAX UNITS t CBPH 5 8 tCEM tCEW 5 5 8 -708 -706, -856 SYMBOL MIN MAX MIN MAX MIN MAX UNITS ns t 8 8 8 ns 8 s tKHKL 1.6 1.6 1.6 ns 7 9 11 ns HZ 1 7.5 1 7.5 1 7.5 ns tKHTL CLK 9.62 20 12.5 20 15 20 ns t KP 3 4 5 ns tCSP 4 20 4.5 20 5 20 ns tSP 3 3 3 ns tHD 2 t 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 2 2 ns 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 37: Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition1 CLK VIH VIL tCLK A[21:0] VIH VIL ADV# VIH VIL LB#/UB# VIH VIL CE# VIH NOTE 4 VIL VIH WE# VIL VIH OE# VIL tKHTL tKHTL WAIT VOH NOTE 3 VOL tSP VIH DQ[15:0] tHD VALID INPUT D[n] VIL VALID INPUT D[n+1] VALID INPUT D[n+2] VALID INPUT D[n+3] END OF ROW DON'T CARE NOTE: 1. 2. 3. 4. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. WAIT will be asserted (2 x LC) + 1 cycles (BCR[8] = 0; WAIT asserted during delay). LC = Latency Code (BCR[13:11]). CE# must not remain LOW longer than tCEM. Table 34: Burst WRITE Timing Parameters--BCR[8] = 0 -701 -708 -706, -856 -701 SYMBOL MIN MAX MIN MAX MIN MAX UNITS tCLK 9.62 tHD 2 20 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 12.5 2 20 15 2 20 -708 -706, -856 SYMBOL MIN MAX MIN MAX MIN MAX UNITS ns tKHTL ns tSP 44 7 3 9 3 11 3 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 38: Burst WRITE Followed by Burst READ1 tCLK CLK VIH VIL A[21:0] VIH VIL ADV# VIH VIL tSP tSP tHD LB#/UB# VALID ADDRESS tSP tHD tSP tHD tSP tHD VIH VIL tCSP CE# OE# WE# WAIT tHD VALID ADDRESS tHD VIH VIL tCBPH2 tABA tCSP VIH VIL tOHZ tSP tHD VIH VIL tSP tHD VOH VOL tBOE High-Z tSP tHD DQ[15:0] VIH IN/OUT VIL VOH High-Z D[1] D[0] D[2] D[3] VOL High-Z tKOH tACLK VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. 3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 35: WRITE Timing Parameters--Burst WRITE Followed by Burst READ -701 -708 -706, -856 -701 SYMBOL MIN MAX MIN MAX MIN MAX UNITS tCBPH tCLK t CSP 5 5 5 -708 -706, -856 SYMBOL MIN MAX MIN MAX MIN MAX UNITS ns tHD 2 2 2 ns tSP 3 3 3 ns 9.62 20 12.5 20 15 20 ns 4 20 4.5 20 5 20 ns Table 36: READ Timing Parameters--Burst WRITE Followed by Burst READ -701 -708 -706, -856 -701 SYMBOL MIN MAX MIN MAX MIN MAX UNITS SYMBOL -708 -706, -856 MIN MAX MIN MAX MIN MAX UNITS tABA 35 46.5 56 ns tHD 2 2 2 ns tACLK 7 9 11 ns tKOH 2 2 2 ns 20 20 20 ns tOHZ t tBOE CLK 9.62 20 12.5 20 15 20 ns tCSP 4 20 4.5 20 5 20 ns t 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN SP 45 8 3 8 3 8 3 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 39: Asynchronous WRITE Followed by Burst READ1 tCLK VIH CLK VIL VALID ADDRESS tAVS tCKA tWC tWC VIH A[21:0] VIL tAW tWR tSP tVPH VIH ADV# VIL tVP tCVS VIH LB#/UB# VIL tVS tBW tHD tSP tHD tCBPH2 tCW VIH CE# VIL tHD VALID ADDRESS VALID ADDRESS tAVH tSP tABA tCSP tAS tOHZ VIH OE# VIL tWC tAS VIH tWP tSP tHD tWPH WE# VIL WAIT tCEW VOH VOL tBOE tWHZ DQ[15:0] VIH IN/OUT VIL High-Z VOH DATA DATA tDH VOL tDW High-Z tKOH tACLK VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT DON'T CARE UNDEFINED NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. 3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 37: WRITE Timing Parameters--Async WRITE Followed by Burst READ -70x SYMBOL MIN -856 MAX MIN -70x MAX UNITS SYMBOL MIN -856 MAX MIN MAX UNITS tAS 0 0 ns tDW 20 23 ns tAVH 5 5 ns tVP 10 10 ns tAVS 10 10 ns tVPH 10 10 ns tAW 70 85 ns tVS 70 85 ns tBW 70 85 ns tWC 70 85 tCKA 70 85 ns tWHZ tCVS 10 10 ns tWP 46 55 ns tCW 70 85 ns tWPH 10 10 ns tDH 0 0 ns tWR 0 0 ns ns 8 8 ns Table 38: READ Timing Parameters--Async WRITE Followed by Burst READ -701 SYMBOL MIN -708 MAX MIN -706, -856 MAX MIN -701 MAX UNITS SYMBOL -708 -706, -856 MIN MAX MIN MAX MIN MAX UNITS 20 4.5 20 5 20 ns tABA 35 46.5 56 ns tCSP 4 tACLK 7 9 11 ns tHD 2 2 2 ns 20 20 20 ns tKOH 2 2 2 ns ns tOHZ tSP tBOE tCBPH 5 tCEW 5 1 7.5 1 7.5 1 7.5 ns tCLK 9.62 20 12.5 20 15 20 ns 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 5 46 8 3 8 3 8 3 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 40: Asynchronous WRITE Followed By Burst READ--ADV# LOW1 CLK VIH VIL A[21:0] VIH VIL ADV# VIH VIL LB#/UB# CE# tCLK tWC tWC VALID ADDRESS VALID ADDRESS tWR tAW tCKA VALID ADDRESS tSP tBW VIH tHD tSP tHD tSP tHD VIL tCBPH2 tCW VIH tCSP tABA VIL tOHZ OE# WE# WAIT VIH tWC VIL tWP VIH VIL VOH tCEW tBOE tWHZ High-Z VIL DATA VOH DATA tDH VOL tDW High-Z tKOH VOL VIH DQ[15:0] IN/OUT tSP tHD tWPH tACLK VALID OUTPUT High-Z VALID OUTPUT VALID OUTPUT VALID OUTPUT UNDEFINED DON'T CARE NOTE: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. 3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. Table 39: Asynchronous WRITE Timing Parameters--ADV# LOW -70x SYMBOL MIN -856 MAX MIN -70x MAX UNITS SYMBOL tAW 70 85 ns tWC t BW 70 85 ns t t CKA 70 85 ns t t CW 70 85 ns t tWR tDH t DW 0 0 ns 23 23 ns MIN -856 MAX MIN 70 MAX 85 ns 8 WHZ UNITS 8 ns WP 46 55 ns WPH 10 10 ns 0 0 ns Table 40: Burst READ Timing Parameters -701 SYMBOL t MIN -708 MAX MIN 35 ABA tACLK tBOE -706, -856 MAX MIN 46.5 -701 -706, -856 MAX UNITS MIN MAX MIN MAX MIN MAX UNITS 56 ns t CSP 4 20 4.5 20 5 20 ns 7 9 11 ns tHD 2 2 2 ns 20 20 20 ns tKOH 2 2 2 ns ns t t 5 5 5 t CBPH t CEW 1 7.5 1 7.5 1 7.5 ns CLK 9.62 20 12.5 20 15 20 ns t SYMBOL -708 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 8 OHZ SP 47 3 8 3 8 3 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 41: Burst READ Followed by Asynchronous WRITE (WE#-Controlled) tCLK VIH CLK A[21:0] VIL tSP VIH tSP VIH CE# VALID ADDRESS VALID ADDRESS VIL ADV# tWC tHD tWR tAW tHD VIL tHD tCSP VIH tHZ tABA tCW tCBPH1 VIL tBOE tOHZ VIH OE# VIL tAS tSP WE# tHD tOLZ tWP tWPH VIH VIL tHD tSP tBW VIH LB#/UB# VIL tCEW tKHTL tCEW tHZ VOH WAIT High-Z High-Z VOL DQ[15:0] tKOH tACLK VOH VALID INPUT VALID OUTPUT High-Z VOL tDH tDW READ Burst Identified (WE# = HIGH) DON'T CARE UNDEFINED NOTE: 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Table 41: Burst READ Timing Parameters -701 SYMBOL MIN -708 MAX MIN -706, -856 MAX MIN -701 MAX UNITS SYMBOL tABA 35 46.5 56 ns tHD tACLK 7 9 11 ns tHZ 20 ns tKHTL ns t 20 tBOE 20 t 5 t 1 7.5 1 7.5 1 7.5 ns t t 9.62 20 12.5 20 15 20 ns t t 4 20 4.5 20 5 20 ns CBPH CEW CLK CSP 5 5 MIN -708 MAX MIN 2 7 9 UNITS 8 ns ns 11 2 2 8 OHZ MAX 2 8 2 8 3 ns ns 8 3 SP MIN 2 8 KOH -706, -856 MAX 3 ns ns Table 42: Asynchronous WRITE Timing Parameters--WE# Controlled -70x SYMBOL tAS MIN -856 MAX MIN 0 -70x MAX UNITS SYMBOL 0 ns tHZ MIN -856 MAX MIN 8 MAX 8 UNITS ns t 70 85 ns t 70 85 t 70 85 ns t 46 55 ns t 70 85 ns t 10 10 ns t 0 0 ns t 0 0 ns t 23 23 ns AW BW CW DH DW 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN WC WP WPH WR 48 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 42: Burst READ Followed by Asynchronous WRITE Using ADV# CLK A[21:0] tCLK VIH VIL VIH tSP VIH CE# VALID ADDRESS VALID ADDRESS VIL ADV# tHD tSP tVPH tHD WE# tAVH tVS tVP VIL tCSP VIH tAW tHD tABA tAS tHZ tCW tCBPH1 VIL tOHZ tBOE VIH OE# tAVS VIL tSP VIH tHD tAS tOLZ tWP tWPH VIL tHD tSP VIH tBW LB#/UB# VIL tCEW tKHTL tCEW tHZ VOH WAIT High-Z VOL High-Z tACLK DQ[15:0] VOH tDH tDW VALID INPUT VALID OUTPUT High-Z VOL tKOH READ Burst Identified (WE# = HIGH) DON'T CARE UNDEFINED NOTE: 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Table 43: Burst READ Timing Parameters -701 SYMBOL MIN -708 MAX MIN -706, -856 MAX MIN -701 MAX UNITS SYMBOL MIN -708 MAX MIN MIN 35 46.5 56 ns tACLK 7 9 11 ns tHZ 8 8 8 ns 20 20 20 ns tKHTL 7 9 11 ns 5 ns tKOH tCEW 1 7.5 1 5 7.5 1 5 7.5 ns tOHZ tCLK 9.62 20 12.5 20 15 20 ns tSP tCSP 4 20 4.5 20 5 20 ns 2 2 UNITS tHD tCBPH 2 MAX tABA tBOE 2 -706, -856 MAX 2 8 ns 2 ns 8 3 8 3 3 ns ns Table 44: Asynchronous WRITE Timing Parameters Using ADV# -70x SYMBOL MIN -856 MAX MIN -70x MAX UNITS SYMBOL MIN -856 MAX MAX UNITS 8 ns 0 0 ns tDW tAVH 5 5 ns tHZ tAVS 10 10 ns tVP 10 tAW 70 85 ns tVPH 10 10 ns tBW 70 85 ns tVS 70 85 ns 1 7.5 8 10 ns ns ns tWP 46 55 ns 70 85 ns tWPH 10 10 ns tDH 0 0 ns 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 7.5 23 tCW tCEW 1 23 MIN tAS 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 43: Asynchronous WRITE Followed by Asynchronous READ--ADV# LOW A[21:0] VIH VALID ADDRESS VIL VALID ADDRESS ADV# LB#/UB# CE# VALID ADDRESS tAA tWR tAW VIH VIL tBHZ tBLZ tBW VIH VIL tCW VIH tCPH1 tCO tHZ VIL tOHZ tLZ OE# WE# WAIT tOE VIH VIL tWC tWPH tWP VIH VIL tHZ tHZ VOH VOL tWHZ DQ[15:0] VIH IN/OUT VIL tOLZ High-Z DATA VOH High-Z DATA tDW tDH VALID OUTPUT VOL UNDEFINED DON'T CARE NOTE: 1. When transitioning between asynchronous cycles, CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate internal refresh operation. BCR[15] can be 1 or 0. Table 45: WRITE Timing Parameters--ADV# LOW -856 -70x SYMBOL MIN MAX MIN -856 -70x MAX UNITS SYMBOL MIN MAX MAX 70 85 ns t BW 70 85 ns t WHZ t CW 70 85 ns t WP 46 55 ns t DH 0 0 ns t WPH 10 10 ns DW 23 23 ns t WR 0 0 ns 8 tHZ 8 85 UNITS tWC t 70 MIN tAW ns 8 8 ns ns Table 46: READ Timing Parameters--ADV# LOW -856 -70x SYMBOL MIN MAX MIN -856 -70x MAX UNITS SYMBOL MIN MAX MIN AA 70 85 ns 8 8 ns tLZ ns t OE 20 20 ns ns tOHZ 8 8 ns ns t BLZ 10 70 tCO t CPH 10 5 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 85 5 50 HZ OLZ 10 5 8 UNITS tBHZ t 8 MAX t t 10 8 5 ns ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 44: Asynchronous WRITE Followed by Asynchronous READ VIH A[21:0] VALID ADDRESS VIL tAVS tVPH VIH ADV# VALID ADDRESS tAVH VALID ADDRESS tAA tWR tAW tAVS tVS tVP tVP VIL LB#/UB# VIL tCW VIH CE# VIL tAS VIH WE# tOHZ tWC tWPH tWP tHZ tCO tLZ tAS VIH OE# tCVS tCPH1 VIL tBHZ tAADV tBLZ tBW tCVS VIH tAVH tOLZ VIL VOH WAIT VOL tOE tWHZ DQ[15:0] VIH IN/OUT VIL High-Z DATA VOH DATA VOL tDW tDH VALID OUTPUT High-Z DON'T CARE UNDEFINED NOTE: 1. When transitioning between asynchronous cycles, CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate internal refresh operation. BCR[15] can be 1 or 0. Table 47: WRITE Timing Parameters--Async WRITE Followed by Async READ -70x SYMBOL tAS MIN 0 -856 MAX MIN 0 -70x MAX UNITS ns SYMBOL tVP MIN 10 -856 MAX MIN 10 MAX UNITS ns tAVH 5 5 ns tVPH 10 10 ns tAVS 10 10 ns tVS 70 85 ns tAW 70 85 ns tWC 70 tBW 70 85 ns tWHZ t CVS 10 10 ns t WP 46 55 CW WPH 10 10 ns 0 0 ns 70 85 ns t tDH 0 0 ns tWR tDW 23 23 ns t 85 ns 8 8 ns ns Table 48: READ Timing Parameters--Async WRITE Followed by Async READ -70x SYMBOL MIN tAA AVH tAVS t CBPH t CO MIN 70 MAX 85 UNITS ns 85 SYMBOL tCVS ns tHZ 5 ns t 10 10 ns tOE ns tOHZ 8 tBHZ tBLZ MAX 70 -70x 5 tAADV t -856 8 LZ 10 10 ns tOLZ 5 5 ns t 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 70 85 VP MIN 10 -856 MAX MIN 10 8 10 MAX UNITS ns 8 ns 10 ns 20 20 ns 8 8 ns 5 5 ns 10 10 ns ns 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Figure 45: 54-Ball VFBGA 0.700 0.075 SEATING PLANE C 0.10 C SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or 62% Sn, 36% Pb, 2% Ag SOLDER BALL PAD: O 0.27mm BALL A6 54X O 0.35 TYP SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS O 0.33 SUBSTRATE: PLASTIC LAMINATE ENCAPSULATION MATERIAL: EPOXY NOVOLAC BALL A1 ID 0.75 TYP BALL A1 0.75 TYP 8.00 0.10 BALL A1 ID 6.00 3.00 0.05 4.00 1.875 0.050 3.00 0.05 1.00 MAX 6.00 0.10 NOTE: 1. All dimensions in millimeters; MAX/MIN, or typical, as noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. Data Sheet Designation: PRELIMINARY This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, and the Micron and M Logos are trademarks and/or service marks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc., inside the U.S. and a trademark of Infineon Technologies outside the U.S. All other trademarks are the property of their respective owners. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved. PRELIMINARY 4 MEG x 16, 2 MEG x 16 ASYNC/PAGE/BURST CellularRAM MEMORY Revision History Rev. C, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/04 * Added tCEM to Asynchronous WRITE, Page Mode * Added software access. * CR WRITE diagram titles updated to reflect WRITEs READ Operation, and Burst Mode Operation followed by READ ARRAY operation. descriptions and timing diagrams. * Deleted Appendix A (extended timings and all * Added 80 MHz burst clock (-708). references). * Changed PAR options to full, one-half, one-quarter, * Added -708 timing specifications. one-eight, or none. * Added CIN and CIO MIN values. * Corrected Table 4 typo. * Added Note 3 to Fig. 31 and 37. * Clarified burst latency at row-boundary crossings. * Added tCO to Fig. 43 and Table 46. * Replaced Abbreviated Component Marks with Part Numbering chart. * Clarified READ/WRITE operating currents. * Added measurement time clarification to ISB and * Added clarifying notes for required refresh opportunity for BCR[15], depending on BCR setting. IPAR notes * Changed tCEM MAX to 8. * Changed tCBPH to tCPH for async-async * Updated ICC values and symbols. transitions. * Corrected package nomenclature to VFBGA. * Added ADV# timing parameters and tCO to Fig. 44 * Clarified address A[4] and higher in page mode. and Table 48. * Clarified CRE in Figure 14. * Clarified CE# LOW time limited by refresh--must * Updated tKP to 4ns for the -708, and 5ns for -706 not stay LOW longer than tCEM. and -856 parts. * Aligned tACLK, tKHTL, tABA, and tCSP with consortium values. Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/03 * Changed BCR[6] = 0 to "not supported," and deleted * Added "and ADV# LOW" to tAS in Async WRITE all references to falling clock edges. Timing Req. table; added tAS as appropriate in * Clarified mixed-mode operation. Figures 34, 38, 41, 43, and corollary Tables 38, 44, 48. * 104MHz part now "contact factory." * Added Note 6 to Tables 2 and 3 for Standby Mode, * Changed tHD MIN in all speed grades to 2. and clarified standby description under Low-Power Operation. * Prohibited DPD via software access sequence. * -701 latency code 2 (3 clocks) changed to 66 MHz * Changed tCSP (MIN) to 5ns for -706 and -856 in all (15.2ns) burst timing tables (18, 20, 25, 26, 27, 28, 34, 36, 37, 39, 41.) Rev. A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/03 * L, V and -60 now "contact factory." * Added lead-free option. * Added V & L options. Modified WAIT in bus * Differentiated standard and low-power standby and operations. Indicated wrap factors. related annotation in/for figures and tables. * Added -706 part information where applicable. * CLK in Tables 2 & 3 changed; can be either HIGH or * Removed tSP and tHD from CE# in Burst diagrams. LOW. Data and figures added to cover software access to the configuration registers. 09005aef80be1fbd Burst CellularRAM.fm - Rev. D 5/19/04 EN 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All Rights Reserved.