INTEGRATED CIRCUITS DATA Sil 74ABT543A = = | Octal latched transceiver with dual enable (3-State) Product specification Supersedes data of 1995 Apr 19 IC23 Data Handbook Philips Semiconductors Di 1998 Sep 24 PHILIPSPhilips Semiconductors Product specification Octal latched transceiver with dual enable (3-State) 74ABT543A FEATURES Combines 74ABT245 and 74ABT373 type functions in one device 8-bit octal transceiver with D-type latch Back-to-back registers for storage Separate controls for data flow in each direction Output capability: +64mA/-32mA Live insertion/extraction permitted Power-up 3-State Power-up reset Latch-up protection exceeds 500mA per Jedec Std 17 ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model DESCRIPTION The 74ABT543A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. QUICK REFERENCE DATA The 74ABT543A Octal Registered Transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of data transfer in either direction. The outputs are guaranteed to sink 64mA. FUNCTIONAL DESCRIPTION The 74ABT543A contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A to B as an example, when the A-to-B Enable (EAB) input and the A-to-B Latch Enable (CEAB) input are Low the A-to-B path is transparent. A subsequent Low-to-High transition of the LEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and OEAB both Low, the 3-State B output buffers are active and display the data present at the outputs of the A latches. Control of data flow from B to A is similar, but using the EBA, LEBA and OEBA inputs. CONDITIONS SYMBOL PARAMETER Tamb = 25C; GND = 0V TYPICAL UNIT tpLH Propagation delay = . = 2.9 tpHL An to Bn or Bn to An CL = 50PF: Voc = 5V 3.6 ns CIN Input capacitance V, = OV or Voc 4 pF : Outputs disabled; Cio I/O capacitance Vo = 0V or Voc 7 pF locz Total supply current Outputs disabled; Vocg =5.5V 110 HA ORDERING INFORMATION 1998 Sep 24 PACKAGES TEMPERATURE RANGE | OUTSIDE NORTH AMERICA | NORTH AMERICA DWG NUMBER 24-Pin Plastic DIP 40C to +85C 74ABT543A N 74ABT543A N SOT222-1 24-Pin plastic SO 40C to +85C 74ABT543A D 74ABT543A D SOT137-1 24-Pin Plastic SSOP Type II 40C to +85C 74ABT543A DB 74ABT543A DB SOT340-1 24-Pin Plastic TSSOP Type | 40C to +85C 74ABT543A PW 7ABT543APW DH SOT355-1 PIN CONFIGURATION PIN DESCRIPTION NS PIN NUMBER SYMBOL FUNCTION TEBA [7] 24] Voc a TERR Tena | Ato B/BtoA Latch Enable OEBA [2| [23] EBA 14,1 LEAB/LEBA input (active-Low) ao [3] 22] 80 aan cur | Ato B/Bto A Enable input 11, 23 EAB /EB : at [4] 27] Bt (active-Low) A2 5] (20) B2 13, 2 OEAB / OEBA Ato B/ B to A Output Enable input (active-Low) as [8 3] 8s 3,4,5,6 a4 [7] ra] Ba 78 , 9 4 , AO -A7 Port A, 3-State outputs 8 17 as [2 #7] 8s ae ae BO-B7 _| Port B, 3-State outputs AG [9] 16] B6 , , , a7 FO} 5] 87 12 GND Ground (OV) Eas [7 M4] CEAB 24 Voc Positive supply voltage GND [73] [13] OEAB SA00168 853-1794 20080Philips Semiconductors Product specification Octal latched transceiver with dual enable (3-State) 74ABT543A LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 2 4EN3 (BA) 23 Gt 7 13 105 3B 2EN4 (AB) 3 4 5 6 7 8 9 10 G2 24 eee es -" AO A1 A2 A3 A4 A5 AG A7 3 20 11 q EAB 4 a1 23 EBA OEAB - 13 14 q LEAB OEBA 2 5 20 1 d LEBA 6 19 BO B1 B2 B3 B4 B5 B6 B7 7 18 tieeeeae : 17 22 21 20 19 18 17 16 15 9 16 10 15 SA00169 SA00170 LOGIC DIAGRAM AO A4 DETAIL A X7 mM Ow PI DETAIL A BO Bi B2 B3 B4 BS B6 B7 11 14 __ LEAB SA00171 1998 Sep 24 3Philips Semiconductors Product specification Octal latched transceiver with dual enable (3-State) FUNCTION TABLE INPUTS OUTPUTS STATUS OEXX EXX LEXX An or Bn Bn or An H x x x Z Disabled x H x x Z Disabled L tT L h Z : L t L | Zz Disabled + Latch L L tT h H : L L t | L Latch + Display L L L H H Transparent L L L L L P L L H Xx NC Hold H = High voltage level h = High voltage level one set-up time prior to the Low-to-High transition of LEXX or EXX (XX = AB or BA) L = Low voltage level | = Low voltage level one set-up time prior to the Low-to-High transition of LEXX or EXX (XX = AB or BA) X = Dontcare T = Low-to-High transition of LEXX or EXX (XX = AB or BA) NC= Nochange Z = High impedance or off state ABSOLUTE MAXIMUM RATINGS! 2 SYMBOL PARAMETER CONDITIONS RATING UNIT Voc DC supply voltage 0.5 to +7.0 Vv lik DC input diode current Vv, <0 -18 mA VI DC input voltage -1.2 to +7.0 V lok DC output diode current Vo <0 -50 mA VouT DC output voltage? output in Off or High state 0.5 to +5.5 Vv lout DC output current output in Low state 128 mA Tstg Storage temperature range -65 to 150 C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT Min Max Voc DC supply voltage 4.5 5.5 Vv V| Input voltage 0 Voc Vv Vin High-level input voltage 2.0 Vv VIL Low-level input voltage 0.8 Vv lou High-level output current -32 mA lot Low-level output current 64 mA At/Av Input transition rise or fall rate 0 10 ns/V Tamb Operating free-air temperature range 40 +85 C 1998 Sep 24Philips Semiconductors Product specification Octal latched transceiver with dual enable (3-State) 74ABT543A DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C Tamb oe | UNIT Min Typ Max Min Max Vik Input clamp voltage Voc = 4.5V3 Ik =-18mA 0.9 | -1.2 -1.2 Vv Voc = 4.5V; low = -38mA; V) = Vi_ or Vin 2.5 3.2 2.5 Vv Vou High-level output voltage Voc = 5.0V; loy =-3mA; V) = Vi_ or Vin 3.0 3.7 3.0 Vv Voc = 4.5V; lo = -32mA; V, = Vi_ or Vin 2.0 2.3 2.0 Vv VoL Low-level output voltage Voc = 4.5V; lo_ = 64mA; V) = Vi_ or Vin 0.3 0.55 0.55 Vv Vast voteges output low Voc = 5.5V; Io = 1mA; VI = GND or Voc 0.13 | 55 55 | v l| Input leakage | Control pins | Voc = 5.5V; V; = GND or 5.5V +0.01 | +1.0 +1.0 pA current Data pins Voc = 5.5V; V; = GND or 5.5V +5 +100 +100 pA lorF Power-off leakage current Voc = 0.0V; Vo or V; $ 4.5V +5.0 | +100 +100 pA ioura [Power upldown State | Voos 21; os 08V;Vi= GND or Veo 150 | 80 150 | us li4tlozyH | 3-State output High current Voc = 5.5V; Vo = 2.7V; Vi = Vi_ or Vin 5.0 50 50 pA li_+loz_ | 3-State output Low current Voc = 5.5V; Vo = 0.5V; Vi = Vi_ or Vin 5.0 -50 -50 pA IceEx Output high leakage current | Voc = 5.5V; Vo = 5.5V; V; = GND or Voc 5.0 50 50 pA lo Output current! Voc = 5.5V; Vo = 2.5V 40 65 -180 40 | -180 mA locu Voc = 5.5V; Outputs High, V) = GND or Voc 110 250 250 HA lect Quiescent supply current Voc = 5.5V; Outputs Low, V; = GND or Voc 20 30 30 mA looz ye nD vous 3-State; 110 | 250 250 | pA soo [Adena svpycarentrer [oo = SV: on nest ata ey os | 18 15 | ma NOTES: Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input at 3.4V. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. This parameter is valid for any Voc between OV and 2.1V, with a transition time of up to 10msec. From Voc = 2.1V to Voc = 5V + 10%, a transition time of up to 100usec is permitted. PONS 1998 Sep 24 5Philips Semiconductors Product specification Octal latched transceiver with dual enable (3-State) AC CHARACTERISTICS GND = OV, ta = tp = 2.5ns, CL = 50pF, R; = 500 LIMITS Tory = 425C Tamb = -40 to SYMBOL PARAMETER WAVEFORM yee > a5 ov +85C UNIT cc = +9. Voc = +5.0V +0.5V Min Typ Max Min Max tpLy Propagation delay 2 1.0 2.9 45 1.0 5.2 ns tPHL An to Bn, Bn to An 1.9 3.6 5.2 1.9 5.7 tpLy Propagation delay 1 1.0 3.4 5.1 1.0 6.2 ns tpHL LEBA to An, LEAB to Bn 2 2.1 4.3 6.0 2.1 6.7 tpzH Output enable time 4 1.0 3.2 51 1.0 6.2 ns tezL OEBA to An, OEAB to Bn 5 2.0 4.3 5.9 2.0 6.6 tpHz Output disable time 4 2.0 4.0 5.7 2.0 6.2 ns teLz OEBA to An, OEAB to Bn 5 1.0 3.0 46 1.0 5.0 tpzH Output enable time 4 1.0 3.4 51 1.0 6.2 ns tezL EBA to An, EAB to Bn 5 2.0 4.4 6.1 2.0 6.8 tpHz Output disable time 4 2.0 3.6 5.4 2.0 5.9 ns teLz EBA to An, EAB to Bn 5 1.0 3.0 46 1.0 5.0 AC SETUP REQUIREMENTS GND = OV, tp = tr = 2.5ns, CL = 50pF, R, = 500Q LIMITS Tamb = +25C Tamb = -40 to +85C SYMBOL PARAMETER WAVEFORM Voc = +5.0V Voc = +5.0V 40.5V UNIT Min Typ Min ts(H) Setup time 3 2.5 1.0 2.5 ns t.(L) An to LEAB, Bn to LEBA 3.0 1.4 3.0 ty (H) Hold time 3 0.5 0.8 0.5 ns ty(L) An to LEAB, Bn to LEBA 0.5 0.6 0.5 ts(H) Setup time 3 3.5 1.3 3.5 ns t.(L) An to EAB, Bn to EB 3.0 1.4 3.0 ty (H) Hold time 3 0.5 0.8 0.5 ns ty(L) An to EAB, Bn to EBA 0.5 0.6 0.5 ty(L) Latch enable pulse width, Low 3 3.5 1.0 3.5 ns AC WAVEFORMS Vu = 1.5V, Vin = GND to 3.0V Vin Vw Vw Vin Vn Vn tPHL tPLH tPLH tPHL Vout Vu Vu Vout Vu Vu SA00172 SA00173 Waveform 1. Propagation Delay For Inverting Output Waveform 2. Propagation Delay For Non-Inverting Output 1998 Sep 24 6Philips Semiconductors Product specification Octal latched transceiver with dual enable (3-State) 74ABT543A WN 0 Gf. Wh WY NOTE: For all waveforms, Vjy = 1.5V, the shaded areas indicate when the input is permitted to change for predictable output performance. An, Bn Voi +0.3V ov SA00176 SA00174 Waveform 3. Data Setup and Hold Times And Latch Enable Pulse Width OEAB, OEBA, EAB, EBA Vm Vu tpzH tpHZ Vou An, Bn Vu Von -0.3V ov SA00175 Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level TEST CIRCUIT AND WAVEFORM 7V 500 o From Output s! Open Under Test GND C= 50 pF T 500 22 ~ Load Circuit ~ TEST si tod open teiz/tpzL 7v tpyz/tpzH open DEFINITIONS CL= Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. SA00012 1998 Sep 24 Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low LevelPhilips Semiconductors Product specification Octal latched transceiver with dual enable (3-State) 74ABT543A DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1 2 + D ~ } Me } iE ee 44 ea {fey L Ay t +] ~~! i lz [e] . 7 AAR AAR AAW AR wx pin 1 index Yee ee ee ee 0 5 10mm Lois torr i it scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) A Ay Aa (1) (1) z UNIT | ax | min. | max. b by c D E e ey L Me Muy w max. mm 4.70 0.38 3,94 1.63 0.56 0.36 31.9 6.73 3.51 8.13 10.03 114 | 043 | 025 | 315 | eas | 794 | 78 | 305 | 762 | 762 | OFF | 205 : 0.064 | 0.022 | 0.014 | 1.256 | 0.265 0.138 0.32 0.395 inches | 0.185 | 0.015 | 0.155 0.045 | 0.017 | oo10 | 1.240 | 0255 0.100 | 0,300 0.120 0.30 0.300 0.01 0.081 Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION ISSUE DATE IEC JEDEC EIAJ PROJECTION SOT222-1 MS-001AF f--} 09-11 1998 Sep 24 8Philips Semiconductors Octal latched transceiver with dual enable (3-State) $024: plastic small outline package; 24 leads; body width 7.5 mm Product specification 74ABT543A SOT137-1 D +: _+>_{| = paths, A ee ee o$Oom) OO hr CLE Cr t 7 | i \ | - Co Co = = Co CI = = Co Co CI cu Fr NL? abl He +. POA 7 24 13 I 1 | | \ Q I _| _ _ _ _ _ _ _ A2 j A D> Ay VW (As) | +, | pin 1 index 8 # Se oad Lp <_ 1 a ra el [eo] , Pp 0 5 10 mm Louw i 4 boa 4 \ scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT | ax.| Ar | Az | As | bp e | D|] EM] e He L Lp Q v w y | 2M] 6 0.30 | 2.45 0.49 | 0.32 15.6 7.6 10.65 1.1 11 0.9 mm 2.65 0.10 | 2.25 0.25 0.36 | 0.23 15.2 7A 1.27 10.00 14 0.4 1.0 0.25 | 0.25 0.1 0.4 g 0 : 0.012 | 0.096 0.019] 0.013 | 0.61 | 0.30 0.419 0.043 | 0.043 0.035 0.10 inches 0.004 | 0.089/ ! | oo14| o.009} a.60 | 0.29 | %95} 0.304 | 9: | o.c16 | o.o3a} %O1 | O01 | 9-004 | 9 1g Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES VERSION PROJECTION | SSUEDATE IEC JEDEC EIAJ SOT137-1 07505 MS-013AD --} oon oe 1998 Sep 24Philips Semiconductors Product specification Octal latched transceiver with dual enable (3-State) 74ABT543A SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 << > } | > > 2 <_ > pin 1 index Saat Lp 7 < | | a + 0 2.5 5mm scale DIMENSIONS (mm are the original dimensions) A UNIT | ay | Ar | A2 | As bp c pM | EM | e HE L Lp Q v w y z] 6 0.21 | 1.80 0.38 | 0.20] 84 | 54 7.9 1.03 | 0.9 0.8 8 mm | 29 | 905 | 1.65 | 75 | 0.251 0.09] 80 | 52 | 8 | 76 | 1] oes] 07 | OF? | 2] OT | Od | oe Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ -93-99-08- SOT340-1 MO-150AG es on-0D-04 1998 Sep 24 10Philips Semiconductors Octal latched transceiver with dual enable Product specification (3-State) 74ABT543A TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 D > + E>_{A] = | | oS eo ! : ey oy | He Son MMH AHH AHH { | | ee | + ~ | Aa H\ FAs) od pin 1 index ; | Lg Lp 1 12 detail X + _ w 5 . 0 2.5 5mm scale DIMENSIONS (mm are the original dimensions) A UNIT | ax | Ar | A2 | As | bp c pM | EA |] e HE L Lp Q v w y z | 6 0.15 | 0.95 0.30 0.2 7.9 4.5 6.6 0.75 0.4 0.5 8 mm | 1-19 | 905 | 080} %?8 | o19] 01 | 7.7 | 43 | F] 62 | 1 | o50} 03 | % | 218] OT | Oo | oe Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ 93-06-16 SOT355-1 MO-153AD --} 95-02-04 1998 Sep 24 11Philips Semiconductors Product specification Octal latched transceiver with dual enable (3-State) 74ABT543A Data sheet status Data sheet Product Definition [1] status status Objective Development This data sheet contains the design target or goal specifications for product development. specification Specification may change in any manner without notice. Preliminary Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. specification Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make specification changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors Copyright Philips Electronics North America Corporation 1998 811 East Arques Avenue All rights reserved. Printed in U.S.A. P.O. Box 3409 Sunnyvale, California 94088-3409 print code Date of release: 05-96 Telephone 800-234-7381 Document order number: 9397-750-04611 Lett make things betew Semiconductors E> PH I LI PS