UC5601DWPR - Texas Instruments High-Performance Analog

•Complies with SCSI, SCSI- 2

Standards

•10pF Channel Capacitance During

Disconnect

•Active Termination for 18 Lines

•Logic Command Disconnects all

Term ination Lines

•Low Supply Current in Disconnect

Mode

•Trimmed Regulator for Accurate

Termination Current

•Current Limit and Thermal

Shutdown Protection

•110 Ohm Termination

•Meets SCSI Hot Plugging

The UC5601 p rovid es preci sion resistive pull-up to a 2.9V reference for al l

18 lines in a Small Computer Systems Interface (SCSI) bus cable. The

SCSI-2 standard recommends active termination at both ends of every ca-

ble segment utilizing single ended drivers and receivers.

Internal circuit trimming is utilized, first to reduce resistor tolerances to ±3%

and then to adjust the regulator’s output voltage to insure termination cur-

rent accuracy of ±3%.

The UC 5601 provi des a disco nnect feature which, upon a l ogic command,

disconnects all terminating resistors, and turns off the regulator; greatly re-

ducing standby power.

Other features include negative clamping on all signal lines, 20mA of active

negation sink current capability, regulator current limiting, and therm a l shut-

down protection.

This device is offered in low thermal resistance versions of the industry

standard 28 pin wide body SOI C and PLCC, as well as a 24 pin DIL plastic

package.

UC5601

SCSI Active Termi nator

FEATURES DESCRIPTION

BLOCK DIAGRAM

Circuit Design Patented

10/94

UDG-94060

ABSOLUTE MAXIMUM RATINGS

Term pwr Volt age . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V

Signal Line Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +7V

Regulato r Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A

Storage Temperature . . . . . . . . . . . . . . . . . . . −−65°C to +150 °C

Oper ating Tem pe ratur e . . . . . . . . . . . . . . . . . −−55°C to +150° C

Lead Tem per atur e (Solde ring, 10 Sec .). . . . . . . . . . . . . +300° C

RECOMMENDED OPERATING CONDITIONS

Term pwr Volt age . . . . . . . . . . . . . . . . . . . . . . . . . 4.0V to 5.25 V

Signal Line Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +3V

Disconnect Input Volt age . . . . . . . . . . . . . . . . . . 0V to Te rmpwr

CONNECTION DIAGRAMS

UC5601

Note: Drawings are not to scale.

Unless otherwise specif ied all volta ges are with resp ect to

Gro und. Currents are positive into, neg at iv e out of the speci-

fied terminal.

Consult Pac kaging Sect ion of Unitr ode Int egr ated Circ uits dat-

abook for ther mal limitations and consider at ions of pack ages.

* QP package pins 12 - 18 serve as both hea tsin k and signa l

ground.

* DWP packag e pin 28 serves as signal ground; pins 7, 8, 9,

20, 21, 22 serve as heatsink/ground.

SOIC-28 (Top View)

DWP Package DIL-24 ( To p View)

N or J Package

PLCC-28 (Top View)

QP Packag e

PARAMETER TEST CONDI TIONS MIN TYP MAX UNITS

Su ppl y Curren t Secti on

T ermpwr Supply Current All termination lines = Open 17 25 mA

All termina tion lines = 0.5V 400 430 mA

Power Down Mod e DISCNCT = Open 100 150 µA

Ou tpu t Secti on (T ermi nat ion Li nes )

T erminat ion Im pedance ∆ILINE = -5mA to -15mA 107 110 113 Ω

Output High Voltage VTRMPWR = 4V (Note 1) 2.65 2.9 V

Max Output Current VLINE = 0.5V -21.1 -21.7 -22.4 mA

VLINE = 0.5V, TRMPW R = 4V (No te 1) -19. 8 -21. 7 -22. 4 mA

Output Clamp Le vel ILINE = -30m A -0 .2 -0.05 0.1 V

Output Leakage

DISCNCT = 4V

TRMPWR = 0V to 5.25V

REG = 0 V VLINE = 0 to 4V 10 400 nA

VLINE = 5.25V 100 µA

TRMPWR = 0V to 5.25V, REG = Open

VLINE = 0V to 5.25V 10 400 nA

Ou tput Capacit anc e DISCNCT = O pen (Not e 2) 10 12 p F

Re g ul at or S ecti on

Regulator Output Voltage 2.8 2.9 3.0 V

Lin e Regulation TRMPW R = 4V to 6V 10 20 mV

L oad Reg ulat io n IREG = 0 to -4 00mA 2 0 5 0 mV

Drop O ut Volt age All Term inat ion Lines = 0.5 V 1.0 1.2 V

Sh ort Circuit Current VREG = 0V -450 -650 -850 mA

Cu rrent S ink Capability VREG = 3.5V 8 2 0 2 5 m A

T hermal Shutd ow n 170 °C

Disc onnect Section

Disconnect Threshold 1.3 1.5 1.7 V

T hre shold Hys teres is 100 160 250 mV

Input Current DISCNCT = 0V 10 15 µA

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = 0°C to 70°C.

TRMPWR = 4.75V, DISCNCT = 0V. T A = TJ.

UC5601

Note 1: Measur ing eac h terminat ion l ine while other 17 are low (0.5V).

Note 2: G uaranteed by design. Not 100% tested in produ ction.

QP package: (see packaging sect ion of UICC data book for more deta ils on therm al performanc e)

Thermal Resistance Junction to Leads, θjL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15°C/ W

Thermal Resistance Junction to Ambient, θja. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30°-40°C/ W

DWP package:

Thermal Resistance Junction to Leads, θjL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18°C/ W

Thermal Resistance Junction to Ambient, θja. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33°-43°C/ W

J package:

Thermal Resistance Junction to Leads, θjL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/ W

Thermal Resistance Junction to Ambient, θja. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75°-85°C/ W

N package:

Thermal Resistance Junction to Leads, θjL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50°C/ W

Thermal Resistance Junction to Ambient, θja. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95°-105°C/ W

THERMAL DATA

Not e: The ab ove n u mb ers for

jL are maximum s for the limiting t her mal resist anc e of the packa ge in a standa rd mounting conf igu-

ration . The

ja number s are mea nt to be guidelines f or the th erm al per form ance of the device/ pc -bo ard syst em. All of the abov e

numbe rs assume no ambien t airflow.

Typical SCSI Bus Configu ration Usi ng t he UC5601

UC5601

A Look at the Resp onse o f a SCSI-2 Cabl e

Figu re 1 shows a single line of a SCSI cable. The driver

is an open colletor type which when asserted pulls low,

and when negated the termination resistance serves as

the pull-up.

Figure 2 shows a worst case scenario of mid cable de-

assertion with a close proximity receiver. The voltage

VSTEP is defined as:

VSTEP = V OL +IO Z0

VOL = Driver Output Low Voltage

IO= Current from Receiving Terminator

Z0= Cable Characterist ic Impedance

IO = VREG − VOL

110

In the pursuit of higher data rates, sampling culd occur

during this step portion, ther efore it is important to ensure

that the step is as high as possible to get the most noise

margin. For this reason the UC5601 is trimmed so that

the output current (IO) is as close as possible to the SCSI

max current spec of 22.4mA. The Termination impedance

is initially trimmed on the IC to 110 ohms typical, then the

regulator voltage is trimmed for the highest output cur-

rent to within 22.4mA.

Figur e 1. A Singl e L ine of a SCSI Cabl e

F igure 2. A Typical Response o f a SCSI Cable

UDG-94062

UDG-94063

UDG-94061

UNITRODE INTEGRATED CIRCUITS

7 CONTINENTAL BLVD. •• MERRIMACK, NH 03054

TEL. (603) 424-2410 • FAX (603) 424 3460

PACKAGE OPTION ADDENDUM

www.ti.com 7-Oct-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

UC5601DWP LIFEBUY SOIC DW 28 20 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC5601DWP

UC5601DWPG4 LIFEBUY SOIC DW 28 20 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC5601DWP

UC5601DWPTR LIFEBUY SOIC DW 28 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC5601DWP

UC5601DWPTRG4 LIFEBUY SOIC DW 28 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC5601DWP

UC5601QP LIFEBUY PLCC FN 28 37 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 UC5601QP

UC5601QPTR OBSOLETE PLCC FN 28 TBD Call TI Call TI 0 to 70 UC5601QP

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

PACKAGE OPTION ADDENDUM

www.ti.com 7-Oct-2013

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

UC5601DWPTR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

UC5601DWPTR SOIC DW 28 1000 367.0 367.0 55.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

MECHANICAL DATA

MPLC004A – OCTOBER 1994

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

4040005/B 03/95

20 PIN SHOWN

0.026 (0,66)

0.032 (0,81)

D2/E2

0.020 (0,51) MIN

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

D2/E2

0.013 (0,33)

0.021 (0,53)

Seating Plane

MAX

D2/E2

0.219 (5,56)

0.169 (4,29)

0.319 (8,10)

0.469 (11,91)

0.569 (14,45)

0.369 (9,37)

MAX

0.356 (9,04)

0.456 (11,58)

0.656 (16,66)

0.008 (0,20) NOM

1.158 (29,41)

0.958 (24,33)

0.756 (19,20)

0.191 (4,85)

0.141 (3,58)

MIN

0.441 (11,20)

0.541 (13,74)

0.291 (7,39)

0.341 (8,66)

E1E

MINMAXMIN

PINS

0.385 (9,78)

0.485 (12,32)

0.685 (17,40)

84 1.185 (30,10)

0.985 (25,02)

0.785 (19,94)

D/E

0.395 (10,03)

0.495 (12,57)

1.195 (30,35)

0.995 (25,27)

0.695 (17,65)

0.795 (20,19)

NO. OF D1/E1

0.350 (8,89)

0.450 (11,43)

1.150 (29,21)

0.950 (24,13)

0.650 (16,51)

0.750 (19,05)

0.004 (0,10)

0.007 (0,18)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

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