Am608 1 Microprocessor System Compatible 8-Bit High Speed Multiplying D/A Converter DISTINCTIVE CHARACTERISTICS 8-Bit D/A with 8-Bit input data latch Compatible with most popular microprocessors including the Am8086 and the Am2900 Families Write, Chip Select and Data Enable logic on chip @ DAC appears as memory location to microprocessor MSB inversion under logic control Ditferential current outputs Output current mode multiplexer with logic selection 2-Bit status latch for output select and code select Choice of 8 coding formats . Fast settling current output 200ns Nonlinearity to +0.1% max over temperature range Full scale current pre-matched to +1 LSB High output impedance and voltage compliance Low full scale current drift +5ppm/C Wide range multiplying capability 2.0MHz bandwidth Direct interface to TTL, CMOS, NMOS Output range selection with on chip multiplexer High speed data latch 80ns min write time eee soe ees GENERAL DESCRIPTION The Am6081 is a monolithic B-bit multiplying Digital-to-Analog converter with an 8-bit data latch, a 2-bit status latch, chip select and other contro! signal lines which allow direct inter- face with microprocessor buses. The converter allows a choice of 8 different coding formats. The most significant bit (Dz) can be inverted or non-inverted under the control of the code select input. The code control also provides a zero differential current output for 2s com- plement coding. A pair of high voltage compliance, dual com- plementary current output channels is provided and is selected by the output status command. The output multi- plexer also allows analog bus connection of several convert- ers, range or output load selection, and time-shared operation between D/A and A/D functions. The data and status latches are high speed which makes the Am6081 capable of interfac- ing with high speed microprocessors. The DE and SE control signals allow the data and status latches to be updated individually or simultaneously. Monotonic multiplying performance is maintained over a more than 40 to 1 reference current range. Matching within +1 LSB between reference and full scale current eliminates the need for full scale trimming in most applications. The Am6081 guarantees full 8-bit monotonicity. Nonlinearities as tight as 0.1% over the entire operating temperature range are available. Device performance is essentially unchanged over the full power supply voltage and temperature range. Applications for the Am6081 include microprocessor compati- ble data acquisition systems and data distribution systems, 8-bit A/D converters, servo-motor and pen drivers, waveform generators, programmable attenuators, analog meter drivers, programmabie power supplies, CRT display drivers and high speed modems. EQUIVALENT CIRCUIT CONNECTION DIAGRAM isp usp CODE Top View Dg D,D2030,Ds50, Dz SEL V+ D-24-1, P-24-1 e NAF sane Cope seLecr 1[_ | CODE SEL v+ [__] 24 POSITIVE POWER SUPPLY Ww DATA LATCH STATUS DE sarcr > (M88) Dy INPUT 2 [7] 0, our se [7] 23 OUTPUT SELECT SE ' | DgwPuT 3[ | Dg |) 22 oureur2 VaEF BIT SWITCHES AND LADDER VREFI-) ps inpur 4(_] bs 102 [_] 21 outpur 2 D, input [_] Dy 0, [] 20 OUTPOTT Dy mpuT 6[_] dy A vo, [_] 19 ourpur1 196081 B,iwput 7 [7] Oy v- [7] 18 NeGatve Power supPLy GND v- OUTPUT SEL LiG-001 Dp, weur 8 [_] 0, comp [7] 17 COMPENSATION ORDERING INFORMATION* ese) po meur 9[} Dy Vacri-) [1] 18 NEGATIVE REFERENCE Pac T rature . cep secect 10 [| cs YRer(+) [_] 18 POSITIVE REFERENCE Type Nonlinearity Numb WRITE 11 Ww se [_] 14 STATUS LATCH ENABLE Hermetic | _,,., .1% | AM6081ADM @rounp 12 (] enn oE oaTA MABLE DIP SEC to +425C | 9% | AMG0B1DM F118 ora waren a Hermetic .1% AM6081ADC DIP +.19% AM6081DC OC to +70C Molded *+.1% AM6081APC bie .19% AM6081PC *Also available with burn-in processing. To order add suffix 8 to part number. Note: Pin 1 is marked for orientation. Ltc-o02 2-9 03951B-ANAAm6081 Am6081 FUNCTIONAL PIN DESCRIPTION CODE Code Select input to the CODE SEL latch. The SEL latch is transparent when CS, SE and W are ac- Symbol Function tive and is latched when any of the above signals cs Chip Select This active low input signal enables go inactive. When CODE SEL latch = 0, the MSB the Am6081. Writing into the data or status latches (D7) is inverted and 1 LSB balance current is occurs only when the device is selected. added to the Ip output. ; ; OUT Output Select Input to the OUT SEL latch. The DE Data Latch Enable This active low input is used SEL _latch is transparent when CS, SE and W are ac- to enable the data latch. The CS, DE, and W must tive and is latched when any of the above signals be active in order to write into the data latch. go inactive. When the OUT SEL latch is fow, the . . an . channel 1 output pair (ig1, ip) is selected. When SE Status Latch Enable This active high input is the OUT SEL latch is high, the channel 2 output used to enable the status latches. The CS, SE, pair (loo, Iga) is selected and W must be active in order to write into the 102) 02 , status latches. Vrer(+) Positive and negative reference voltage to the ref- _ Vrerc} erence bias amplifier. These differential inputs allow w Write This active low control signal enables the the use of positive, negative and bipolar references. data and status latches when the CS, DE, and SE COMP Compensation Frequency compensating terminat inputs are active. for the reference amplifier. Dy-Dy Dp-D7 are the input bits 1-8 to the input data latch. lor toy These high impedance current output pairs are Data _is transferred to the data latch when CS, DE, loz: log selected by the output select latch. Io; and log are and W are active and is latched when any of the true outputs and Ig; and Ig are complementary enable signals go inactive. outputs. FUNCTION TABLES CODE SELECT AND DATA LATCH CONTROL STATUS LATCH CONTROL .- OUTPUT SELECT __ _ _ CODE SEL and CODE OUT cS W ODE Data Latch CS W SE _ OUT SEL Latch SEL SEL Function 0 0 0 Transparent 0 0 1 Transparent 9 - MSB Inverted (Note 1) x x 1 Latched x x 0 Latched 1 - MSB Non-inverted x fa] x Latched x [4 x | Latched = 0 | Output Channet 1 1 x x Latched 1 x x Latched ~ 1 Output Channel 2 X = Don't Care Note 1. 1 (SB balance current is added to the to output. MAXIMUM RATINGS Operating Temperature Power Supply Voltage +18V Am6081ADM, Am6081DM 5C to +125C | Logic Inputs ~5V to +18V Am6081ADC, Am6081DC Analog Current Outputs 12V to +18V Am6081APC, Am6081PC OC to +70C | poterence inputs (Vis, Vie) VtoVi Storage Temperature 65C to +150C | Reference Input Differential Voltage (V15 to Vig) +18V Lead Temperature (Soldering, 60 sec) 300C | Reference Input Current (I,5) 1.25mA GUARANTEED FUNCTIONAL SPECIFICATIONS Resolution 8 bits Manotonicity 8 bitsELECTRICAL CHARACTERISTICS These specifications apply tor V; = +5V, V_ = 15V, Irer = 0.5mA, over the operating temperature range unless otherwise specified. Output characteristics refer to all outputs. Am6081 Am6081A Am6081 Parameter Description Conditions Min. Typ. Max. Min. Typ. Max. Unit Resolution Straight coding/Sign Magnitude 8/9 8/9 8/9 8/9 alg a/9 bits Monotonicity Straight coding/ Sign Magnitude 8/9 8/9 8/9 8/9 8/9 8/9 bits Differential D.NL. Noniinearity - ~ +0.19 - - +0.39 | %FS NL. Nonlinearity - - +0.1 - - +0.19 RFS Vrer = 10.000V les Fult Scale Current Fas = Rig = 20.000k0 1.984 {| 1.992 | 2.000 | 1.976 | 1.992 | 2.008 mA Ta = 25C Tcl Full Scale T. - +5 +20 - +10 +40 | ppm/C Ul empco FS | +.0005] =.002 +.001 | +.004 [%FS/C Output Voitage - - - - Ht Voc Compliance 10 +18 10 +18 Volts Full Scale mc less Symmetry les1 ~ lFs1 OF les2 IFs2 - 20.1 | -21.0 - +0.2 | +20 HA Output Switch loss Symmetry lest ~ lps2 Or ipsa Ieee - +01 | +10 | - | #02 | 20 | pA lzg Zero Scale Current - 0.01 1.0 - 0.01 2.0 BA lois Output Disable Output of mpx Off Channels - 0.01 | 0.05 - 001 | 005 | uA ; Refere',e Current V- = -5V 0 05 0.55 0.5 0.55 mA RR Range V- = ~15V o 05 1 0.5 14 Vv Logic ic "0" - - 08 - - 08 a input [Oe 0" Volts Vin Levels Logic 1 20 - - 2.0 Oy tn Logic Input Current Vin = 5V to +18V - - 40 ~ - | 4 BA Vis Logic Input Swing V- = -15V - - +18 - - +18 Volts Reference Bias _ _ _ _ _ _ he Current 0.5 2.0 05 2.0 pA Reference Input Ris(eq) = 8002 _ _ dl/dt Slew Rate CO. OpF 4.0 8.0 40 8.0 mA/us PSSles4 | Power Supply V+ = +4.5V to +5.5V, V- = -15V - +0.0005| +0.01 - +0.0005; 10.01 uES PSSipg | Sensitivity V = ~13.5 to 16.5V, V+ = +5V = }=0.0008)=0.01 [ |=0.0005/ 0.01 V+ Power Supply 45 - 18 45 - 18 Iner = 0.5MA, Voyt = OV Volts v- Range REF out -18 = -45 | -18 = | -45 I+ ~ 9.8 14.7 - 9.8 14.7 V+ = +5V, V- = -5V I~ - -74 | -99 - -7.4 | -99 I+ Power Suppl - 9.8 14.7 - 9.8 14.7 y V+ = +5V, V- = -15V mA i- Current ~ ~74 -9.9 - -7.4 ~9.9 I+ 9.8 147 ~ 9.8 14.7 V+ = +15V, V~- = -15V I~ - -74 | -99 - -74 | -99 V+ = +8V, V- = -5V - a6 123 - 86 123 Power Pp Dissipation V+ = +5V, V = -15V - 160 222 - 160 222 mw V+ = +15V, V- = ~15V - 258 369 - 258 369 2-11Am6081 AC CHARACTERISTICS Vi = +5V, VL = 15V, IRpep = 0.5mA, AR, < 5000, C_ < 15pF over the operating temperature range unless otherwise specified Commercial Military Temp. Grades Temp. Grades Parameter Description Conditions Min. Typ. Max. | Min. Typ. Max. Unit en . : Ty = 25C ts Settling Time, All Bits Switched Settling to + aLSB 200 200 ns 'PLH Propagation | Each bit Ta = 25C 90 180 90 180 ns tPHL Delay All bits switched | 50% to 50% 90 180 90 180 / a Ta = 25C tos Output Switch Settling Time to + 1/2LSB of les 250 250 ns Output Switch Propagation Ta = 26C, top Delay 50% to 50% 180 300 150 300 ns tou Data Hoid Time See timing diagram 10 ~30 10 -30 ns tos Data Set Up Time See timing diagram 80 35 100 35 ns tow Data Write Time See timing diagram 80 35 100 a5 ns tsH Status Hold Time See timing diagram 10 -70 10 -70 ns tss Status Set Up Time See timing diagram 200 100 230 100 ns tsw Status Write Time See timing diagram 200 106 230 100 | ns Notes: 1. tpw is the overlap of W low, CS low, and DE low. All three signals must be fow to enable the latch. Any signal going inactive latches the data. 2. ts is measured with the latches open from the time the data becomes stable on the inputs to the time when the outputs are settled to within w > +1/2 LSB. All bits switched on or off. the data. . The internal time delays trom CS, W, SE and DE inputs to the enabling of the fatches are all equal. . tgw is the overlap of W low, CS low and SE high, all three signals must be active to enable the latch and any signal going inactive will latch TIMING DIAGRAM tow e| (NOTES 1, 4) b tos -| ton os }~_______- tg, _-__-_+] output 'o XK T (NOTE 2} lo (NOTES. a0 } f bs |a 55 a CODE SEL OR M56 SEL XXKKK KH IN STABLE XXX KKK KKK ts output 'o (NOTE 2) 55 LiC-003Am6081 APPLICATION HINTS wee - +100 1. Reference current and reference resistor There is a 1 to 4 scale up between the reference current (Iper) = Irs and the full scale output current (Ips)- ff Vaer = + 10V and les Pas = 2mA, the value of the Ris is: Wer ee Am081 4x 10 Volt VReF{) Res - AX Wee =e = | FS 15 2mA = 20K = , ' Fig = Fis LiC-004 2. Reference amplifier compensation For AC reference applications, a minimum value compensa- tion capacitor (Cc) is normally used. The value of this capacitor depends on Rj5. The minimum values to maximize bandwidth without oscillation are as follows: Reference Amplifier Output Voltage Frequency Response Compliance Table 2 ALL BITS ON 6 + 32 Compensation Capacitor qT] Rar cea) = 2x0 (lpg = 2mA, Ipeg = 0.5mA) sf LO cg = 10pF <7 2 ate HLH ie Rrer (kQ) Cc (PF) FO & 20 LARGE SIGNAL =50% 4 1.6 20 100 & _,| MODULATION OF 2ma *_| tI 3 10 50 w FULL SCALE CURRENT __ | 5 12 5 25 E watt} ft 0.8 z SMALL SIGNAL =1% 1 2 2 10 & _ | MODULATION OF 2mA o4 1 5 FULL SCALE CURRENT __| 5 0 | ~a te Ltt ii 5 ~14@-10-6 -2 2 6 10 14 18 - , " . OUTPUT VOLTAGE - VOLTS FREQUENCY MHz LIC-005 Lic-008 A0.014uF capacitor is recommended for the fixed reference operation. Reference Ampilfier Biasing 10, w Oz 74 LIC-007 Reference Configuration Ras Ris Rin Co lper Positive Reference Vat ov NC O1pF Vr+/ Pig Negative Reference ov VR NC OtuF ~Vp_/Ris Lo Impedance Bipolar (Vr+/ Rig) + (Vin/ Rin) Reference Vr+ ov VIN (Note 1) (Note 2) Hi Impedance Bipolar Vas Vind/Ras Reference Vat Vin NG (Note 1) (Note 3) Pulsed Reference (Note 4) Vat ov Vin Can Waa! Ras) + (Ving/ Fyn) Notes: 1. The compensation capacitor is a function of the impedance seen atthe + Vref input and must be atleast C = SpF x Ryseq) (in kf). For Rys < 8002 no capacitor is necessary. 2. For negative values of Vin, Va+/A15 must be greater than Vin Max/Rjy So that the amplifier is not turned off. 3. For positive values of Vin, Va+ Must be greater than Vi Max so the amplifier is not turned oft. 4. For pulsed operation, Va, provides a OC offset and may be set to zero in some cases. The impedance at pin 15 should be 8002 or less and an additional resistor may be connected fram pin 15 to ground to lower the impedance. 2-13Am6081 CODE SEL bt xo.) ~ a fy 20K tov A Vaerix) 6; 6 . REF Fis Your Am08t OP AMP Vaeri-) e ' Pais d = 9 Ry { 5K Ip OPTIONAL (NOTE 1} I MB LsB ~ = Note: Connect all unused outputs to ground. LIG-008 CODE} OUT! con. OUT MSB tsb] 1, | bb CODE FORMAT set | set |Nections! OUTPUTSCALE [cei 7 06 ps D4 D3 D211 D0 | (mA}| (map| VOUT ae Positive full scale x 4 1 + 1 | 1.9921 0 9.960 ce 0 bg Positive fullscale-4SB | X 1 #1 1 1 4 1 4 | 1.984] 0 9.920 Straight binary: one Zero scale X 0 000000 0 | 0} 0 000 polarity with true input 1 code, true zero output. ce 1 og UNIPOLAR ag Positive full scale xX 0 0 0 6 0 O oO |1992}) | 9.960 Complementary binary: 0 bs Positive fullscale -LSB | X 0 0 0 0 0 0 1 |1.984/ 0 | 9.920 one polarity with Zero scale x 1 144 7 1421 1 000 | 0 000 complementary input code, true Zero output. 1 cg d-e Positive full scale 1 1 114 4 71 45 1 | 1.992; .000] 9.960 Signed magnitude binary: Positive full scale - LSB 1 1 1 t 1 t tt G | 1.984, .000|] 9.920 8 bits + sign reflected i ae (+) Zero scale 1 0 06000UwMUmCMUdUCUCOMUClCUO -000] .000 000 code, overlapping cf (-} Zera scala 0 0 0609000 0 .000 | .000 000 true Zero output. Negative full scale - LSB] 0 1 +1 F1 171 0G -000 | 1.984) -9.920 tive full scal 1 14 +44 4] 1.982] -9: SIGNED Negative full scaie 0 1 000 982] 9.960 MAGNITUDE Complementary signed Positive full scale 1 0 6 @ 0 0 0 0 |1.992] .000] 9.960 ms ne le: ary sig Positive fullscale -LSB | 1 0 0 0 0 0 0 0 14 | 1.984] 000] 9.920 jagnitude: be __| (+) Zero scale + 1 1 4 4 4 9 4 4 { 000] 000] 000 5 bits + sign complementary | -) Zeto scale o 4 1 4 1 4 14 4 1 | 000} .000] 000 reflected code, overlapping dt (-) Zero scal : : : true zero 0 , Negative full scale - LSB] 0 090 60 090 4 .000 | 1.984] -9.920 ero output. Negative full scale 0 0 0 0 0 0 0 0 0 | 000] 1.992] -9.960 aa Positive full scate x 1 1 4 4 4 4 1 1 | 1.992] .000] 9.960 Straight offset binary: o bf Positive fullscale LSB | X 1 1 1 1 1 1 1 GO | 1.964] 008] 9.680 offset haif scale, 1 (+) Zero scale x 1 00000 0 O | 1.000] .992 040 symmetrical about zero, (-) Zero scale x oO 1 4 4 11~21 i -982 11.000] .040 no true zero output. 1 ce Negative full scale - LSB | X o 000000 41 .008 | 1.984] -9.880 ot Negative full scale x 0 @ 6 GOO 0 Oo | .000] 1.992] -9.960 SYMMETRICAL OFFSET 1's complement: ae Positive full scale xX oO 4 41 1 1 1 1 1 | 1,992] .000] 9.960 offset hall scale, 9 bet Positive fulscale~LSB | X Oo 1 4 1 1 1 1 | 1.984] .008] 9.980 symmetrical about zero, 1 (+) Zero scale xX 0 0 0686 0 0 0 0 O }1.000} .ss2 049 no true Zero output {Note 1) (~) Zero scale x 1 11 4 14 1441 1 992 71.000] -.040 MSB complemented. 1 ce Negative full scale - LSB] X 1 000000 1 .008 | 1.984] 9.880 (need inverter at D>) at Negative full scale x 1 0 0 0 6 G O @ |] .000} 1.992] -9.960 : Positive full scale x 4 1179 4 4 4 1 [1.992] .0o8| 9.920 Onset biter Ya 0 48 | Positive fullscale LSB} X 1 1 7 1 9 1 4 | 4.988) O16! 9.840 offset nal Scale, 0 bf + LSB x 1 0 0 606 0 0 1 |1.008] 992] 080 ee oe anes roy oe coco o)rmelsom! mo ainder add to I. ce . , . OFFSET | (noed inverter at DO 1 ot Negative full scale + LSB} X 0 0 0 0 0 0 O 1 | 008/1.892| ~9.620 with {need inverter at D7) Negative full scale xX 0 G 0 0 0 0 0 0 | .000|2.000]-10.000 TRUE Positive full scale x oOo 1 * 17 17 1 4 + +F |1.992] 008] 9920 ZERO . . ae Positive fullscale -LSB | X O 14 1 1 4 1 4 OF | 1.984] 016) 9.840 ee tee b+ +1 LSB X 0 000 00 0 +t | 1,008] 992] 080 0 Zero scale x 08 0 0 0 0 O 0 oO }1,000}1.000] .000 true zero output - MSB com ted ce -1 LSB x 4 4 4 4 4 4 4 14 | 992] 1.008) -.080 plementod. 1 a+ | Negative fullscale + LSB] X 1 0 0 G O O 1 | .008] 1.982] -9.920 Negative full scale x t+ 0 0006 00 0 -000 | 2.000 | 10.000 Note 1: An extemal inverter is necessary since the code select inverts the MSB and adds a 1 LSB balance current to Tg. Only one of the two features is desired for these codes. ADDITIONAL CODE MODIFICATIONS 1. Any of the offset binary codes may be complemented by reversing the output terminal pair. 2. The sign on any of the sign-magnitude codes may be changed by reversing the output terminal pair. 3. The polarity of the unipolar codes may be changed by driving the opposite side of the balanced load. 2-14Am6081 SYSTEM APPLICATIONS AmS080A DATA SYSTEM: SEPARATE UPDATE OF DATA AND STATUS SELECT OUTPUT PORT 1 : ones MVIA,2 _: SET STATUS TO 0 (SELECT OUTPUT 1) Aois out 1 : SEND STATUS MOV A,M : GET DATA FROM MEMORY OUT 0 : SEND DATA SELECT OUTPUT PORT 2 Pods MVIA,3_; SET STATUS TO 1 (SELECT OUTPUT 2) OUT 1 : SEND STATUS amona0a MOV A.M : GET DATA FROM MEMORY SYSTEM OUT 0 : SEND DATA ow SELECT OUTPUT PORT 2 AND 2's COMPLEMENT CODE MVIA, 1; SET STATUS TO 3 (OUTPUT 2, MSB COMP) OUT 1 : SEND STATUS MOV A.M; GET DATA FROM MEMORY OUT oO : SEND DATA Lic-008 Am8080A DATA SYSTEM: SIMULTANEOUS UPDATE OF DATA AND STATUS AorAas ADORESS BUS > Ay Ao Og; K DATA BUS \ AMBOBDA SYSTEM a MOV A.M: GET DATA IN ACCUMULATOR OUT O : OUTPUT DATA TO PORT 1, 2S COMPLEMENT OUT 1 : QUTPUT DATA TO PORT 2, 2S COMPLEMENT OUT 2 : OUTPUT DATA TO PORT 1, STRAIGHT BINARY OUT 3 : QUTPUT DATA TO PORT 2, STRAIGHT BINARY Lic-o10 Am9080A DATA SYSTEM: 8-BIT PLUS SIGN CONVERSION Aobas ADDRESS BUS DoD; DATA BUS Amo0aGA SYSTEM MOV A,M : LOAD MAGNITUDE (8-BITS) OUT 0 : SEND POSITIVE OUTPUT OUT 1 : SEND NEGATIVE OUTPUT Lic-or 2-15: SYSTEM APPLICATIONS (Cont.) Am2900 DATA SYSTEM: MULTIPLE ANALOG OUTPUTS K DATA BUS > . a COMMAND REGISTER a Am25LS374 8 DACK ts tack - EOP PROGRAM xINSTRUCTION 18 mux RDY (2) Am2a11 Am26811A am258151 Ta Te Ln tL 23 e CONTROL STORAGE (8) Amz7814 256 x 24 PROM DoD, + 24 INSTRUCTION PIPELINE OUTPUT 1 REGISTER Tix) z OUTPUT 2 FIs) 3) gg " a al | | i818 : . . . . OTHER . . CONTROL . . (DMARQ, Dy, . ADY . L = * 3 e 3:8 oO DECODER JO OUTPUT 15 jO OUTPUT 16 LK-012 2-16Am6081 SYSTEM APPLICATIONS (Cont.) D/A CONVERSION WITH 12-BIT DYNAMIC RANGE DIGITAL INPUT B11 Bip By Bg B87 Bg Bs 84 Bz Bz B; Bp WHEN THE UPPER 4 BITS, Dg-D,,, OF THE 12-B}T CODE ARE ZERO, THE iL LOWER 8 BITS AND THE 1X SCALE | | ARE SELECTED. 1A 2A 3A 4A 168 2B 35 4B 1A 2A 3A 4A 18 2B 3B 4B 8 Am2SLS157 1 Ss Am25LS157 we eM 1 2 3c ac Dr De Ds Dg D3 Dz 01 Dp OUT SEL ameost WV a RANGE INDICATOR ~L- LiC-013 A/D CONVERSION WITH AUTO RANGING AND DIFFERENTIAL INPUT Vin> Yin- RS k, 3 > > 102 1sR = 216A wh q OUT Am6081 2 Amit SEL 10; ww, J comp 07 De Ds O, D3 De Dy D9 / RANGE BIT 07 Dg Ds Os pIGFrAL D3 OUTPUT O2 s o, ob a ___ OF 4 cP R A Q. Qs @, Qa a G cLocK ce 7 Gg Gs Gq G3 G2 G, Qo stant am2502 o COMMAND WHEN THE FIRST FOUR BITS CONVERSION START RESULTS ARE ZERO, THE 1X SCALE 1S SELECTED AND THE CONVERSION IS RESTARTED. THE START COMMAND RESETS THE CONVERSION TO 16X SCALE Lic-014 2-17Am6081 SYSTEM APPLICATIONS (Cont.) ANALOG/DIGITAL TRANSCEIVER WITH HARDWARE CONTROLLED SUCCESSIVE APPROXIMATION A/D CONVERSION AorAt5 AmB080A Dg, READY ANALOG Ww Am6081 OD, ns ADDRESS BUS x x | sm ADDRESS L gf DECODE | = Loaic CL cope ouT SE 9,\ | oles SEL SEL 0; Am311 = u K DATA BUS ae READ = CONTROL Locic it TRI-STATE BUFFER Sc START Am2502 > F398 v4 I " ANALOG OUTPUT (NEGATIVE) LIC-015 ANALOG/DIGITAL TRANSCEIVER WITH SOFTWARE CONTROLLED A/D CONVERSION ANALOG AoAis ADDRESS BUS x > Am@080A ADORESS DECODE +5v Loaic | iow -QO_};_o READ OR JO] conTROL Loaic OD K DATA BUS LIC-016 2-18Am6081 Am9080A SOFTWARE FOR A/D AND D/A CONVERSION USING Am6081 SEQ SOURCE STATEMENT SEQ SOURCE STATEMENT 0 PORTI EQU 00H 18 CMA 1 PORTS EQU 02H 19 CRAA iSET SIGN FLAG 2 PORT2 EQU 01H 20 JM NEXT 3IF SMALLER GO TO NEXT BIT 3 ORG 3E50H a1 MOV D,E ;SAVE RESULT 4 START: LXI SP,STAKS16 = {INITIAL STAKS POINTER 22 NEXT: MOV A,B GET NEXT TRIAL BIT 5 SAMPLE: CALL ADCON sCALL A/D CONVERSATION 23 RAR SSHIFT RIGHT ONCE 6 CMA 24 RC ;RETURN ON CARRY 7 CALL DACON CALL D/A CONVERSION 25. MOV B.A STORE TEST BIT 8 JMP SAMPLE NEXT SAMPLE 26 ADD D ;ACCUMULATE RESULT 9 ADCON: XRAA CLEAR ACC 27 JMP LOOP TRY NEXT BIT 10 MOV D,A ;CLEAR D REG 28 DACON: QUT PORT 2 ;QUTPUT TO D/A 11 STC ;SET CARRY 29 MVi C,05H ;LOAD C REG WITH TIME 12 RAR SET BIT 7 T0 1 30 OCR C TIME DELAY 13 MOV B.A STORE TEST BIT AT B REGISTER =. 31 RZ ;RETURN 14 LOOP: MOV E,A STORE TEST WORD 32 FILT: RET 15 CMA 33 STAKS: OS 16 16 QUT PORTI /QUTPUT TO AD 34 END START 17 IN PORT3 sINPUT FROM COMP ADVANCED MICRO DEVICES DATA CONVERSION PRODUCTS Digital to Analog Converters AmDAC-08 -- 8-Bit High Speed Multiplying D/A Converter Am1508/1408 8-Bit Multiplying O/A Converter Am6070 8-Bit Companding D/A Converter for Control Systems (4-law) Am6072 8-Bit Companding D/A Converter for Telecommunications (p-law) Am6080 8-Bit High Speed Multiplying D/A Converter System/Microprocessor Compatible Am6081 - 8-Bit High Speed Multiplying DAA Converter System/Microprocessor Compatible *Am6689 8-Bit, Ultra High Speed DA Converter (ECL) *Am6012 12-Bit High Speed Muttiptying D/A Converter Analog to Digital Converters *Am6688 4-Bit Quantizer (Ultra High Speed A/D Converter) Successive Approximation Registers Am2502 8-Bit Successive Approximation Registers Am2503 8-Bit Successive Approximation Registers Am2504 ~ 12-Bit Successive Approximation Registers Sample and Hold Amplifiers LF198/398 Monolithic Sample and Hold Amplifier *Am6098 Precision Sample and Hold Amplifier Comparators LM111/311 ~ Precision Voltage Comparator LM119/319 Dual Comparator Am686 ~ High Speed Voltage Comparator High Speed Operational Amplifiers Am118/318 ~ High Speed Operational Amplifier LF155/156/157 JFET Input Operationa! Amplifiers LF355/356/357 JFET Input Operational Amplifiers To be announced. 2-19Am6081 instrumentation and Control Data Acquisition Data Distribution Data Transceiver Function Generation Servo Controls Programmable Power Supplies Digital Zero Scale Calibration Digital Full Scate Calibration Digitally Controlled Offset Null Audio Music Distribution Digitally Controlled Gain Potentiometer Replacement APPLICATIONS Signal Processing CRT Displays Floating Point Analog Processors IF Gain Control Four Quadrant Multiplexer 8 x 8 Digital Multiplication Line Driver A/D Converters Ratiometric ADC Differential Input ADC Multiple Input Range ADC Two Channe! ADC Microprocessor Controlled ADC D/A Converters Single Quadrant Multiplying DAC Two Quadrant Multiplying DAC Four Quadrant Multiplying DAC Digital Recording Two Channet DAC Speech Digitizing Multiple Output Range DAC Metallization and Pad Layout Dp Of D2 D3 Dg Dg 9 B 7 6 4 3 o 0 2 Or Wn + CODE SEL GND 12 { 24 V+ 23 OUT SEL BE 13 Se 14 22 Dy VREF(+) 15 s ew 1 199 20 21 VREF(-) COMP V Oy Dy We DIE SIZE: 0.083 X 0.121 2-20