. HY638100 HY U NDAI 428Kx8bit CMOS FAST SRAM DESCRIPTION The HY638100 is a high-speed 131,072 x 8-bits CMOS static RAM fabricated using Hyundai's high performance CMOS process technology. This high reliability process coupled with high-speed circuit design techniques, yields maximum access time of 15ns. The HY638100 has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0 voit. It is suitable for use in high-density high- speed system applications. FEATURES BLOCK DIAGRM Single 5V+ 10% Power Supply e High speed - 15/20/25ns(max.) not 8 vo Low power consumption(Max.) i % 3 fi . Mode | Conditions { Current | Units (a) |8 Bs] 3 Operating | 15ns 150 mA "12 LIB LU] wemorvarray | PH fe] * 20/25ns 140 mA 12/12 S12K2048 eye]: Standby [TTL 40 mA l2hl2 glye} - CMOS 2 mA as o7 WE? 2 O vO8 L {500 uA Ksot = Battery backup(L-part) wrod ES - 2.0V(min.) data retention g g * Fully static operation and Tri-state outputs awe O7 - No clock or refresh required TTL compatible inputs and outputs Standard pin configuration - 32pin 400mil SOJ - 32pin 400mil TSOP-II PIN CONNECTION PIN DESCRIPTION Pin Name Pin Function 1 ics Chip Select g ANE Write Enable 4 /OE Output Enable AQ~A16 Adderss Input 8 /01~VO8 | Data Input/Output Vec Power(+5.0V) Vss Ground SOJ/TSOP-II ORDERING INFORMATION Part No. Speed Power | Package HY638100J 15/20/25 SOJ HY638100LJ 15/20/25 |L-part | SOJ HY638100T2 | 15/20/25 TSOP-Ii HY638100LT2 | 15/20/25 | L-part | TSOP-II This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.02 { Dec.97 Hyundai Semiconductor atHYUNDAI HY638100 Series ABSOLUTE MAXIMUM RATING (1) Parameter VouT -0.5 to 7.0 TA 0 to 70 STG to 1 IOUT mA T Lead Time 26010 Note 4. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. RECOMMENDED DC OPERATING CONDITIONS Ta=0TC to 70T Min. Vcc 4. 0 VIH 2.2 Vit Low -0.5(4 Note 1. ViL = -3.0V for puise width less than 10ns TRUTH TABLE ICS | WE | /0E H L L L Note: 1. H=Vin, L=VIL, X=Don't care Rev.02 / Dec.97 212HYUNDAI DC ELECTRICAL CHARACTERISTICS Veco = .0V+ 10%, T, = OT to 70T, unless otherwise specified. HY638100 Series _Symbol Parameter Test Conditions Min | Typ | Max | Unit HL Input Leakage Current Vss = VIN Vcc -2 - 2 uA Lo Output Leakage Current | Vss = VouT Vcc, -2 - 2 uA CS = Vinior /OE = Vinior /WE = VIL lect Average Operating ICS = Vit, Ivo = OmA, 15ns - - 150 mA Current Min. Duty Cycle = 100% | 20/25ns - - 140 mA ISB TTL Standby Current ICS = Vit, ViNeViH or Vit Min. Cycle - ~ 40 mA (TTL Inputs) \sBi CMOS Standby Current | /CS >= Vec-0.2V, Vin= : - 2 mA (CMOS Inputs) Vcc-0.2V or VIN = 0.2V L - 650 | 500 uA VOL Output Low Voltage io. = 8.0mMA - - 04 Vv VoH Output High Voltage lon = ~4.0mA 24] - - v Note : Typical values are at Voc = 5.0V, TA=25T AC CHARACTERISTICS Veco = 5.0V+10%, TA= OT to 70T, unless otherwise specified. . 15 -20 -25 . # | Symbol Parameter Min [ Max | Min | Max | Min | Max Unit READ CYCLE 1 jtRC Read Cycle Time 15 - 20 - 256 - ns 2 | tAA Address Access Time 15 - 20 - 25 ns 3 | tACS Chip Select Access Time - 16 - 20 - 25 ns 4 |tOE Output Enable to Output Valid : 7 - 9 - 10 ns | tCiz Chip Select to Output in Low Z 3 - 3 - 3 - ns 6 | t01z Output Enable to Output in Low Z 3 - 3 - 3 - ns 7_|tCHZ | Chip Deselecting to Output in High Z 0 8 0 9 0 10 ns 8 | tOHZ | Gut Disable to Output in High Z 0 8 Q 9 0 10 ns 9 | tOH Qutput Hold from Address Change 3 - 3 - 3 - ns WRITE CYCLE 10 | wwe Write Cycle Time 45 - 20 - 25 - ns 414 | tCW Chip Select to End of Write 12 - 15 - 17 - ns 42 | (AW Address Valid to End of Write 12 : 15 : 17 - ns 43 | tAS Address Set-up Time 0 - 0 : 0 ~ ns 14 | twP Write Pulse Width 12 - 15 - 17 - ns 15 | WR Write Recovery Time 2 - 2 - 2 - ns 16 | tWHZ_ | Write to Output in High Z 0 0 9 0 10 ns 17_ | toW Data to Write Time Overlap 8 3 - 10 - ns 18 | tDH Data Hold from Write Time 0 - 0 : 6 - ns 19 | tOW Output Active from End of Write 3 : 3 - 3 - ns Rev.02 / Dec.97 213HYUNDAI HY638100. Series AC TEST CONDITIONS Vee =5.0V11 Ta= 0 to 70T, unless Value Level OV to 3.0V and 3ns Reference 1.5V below AC TEST LOADS Output Load (A) Output Load (B) {for tCHZ, tCLZ, tOHZ, tOLZ, t(WHZ & tOW) +5V +5V 480 Ohm 480 Ohm Bow r : Dour f 255 Ohm sk CL=30pFo 255 Ohm sk CL=5pF T7 ITT Note : Including jig and scope capacitance CAPACITANCE Temp = 25C, f= 1.0MHz Symbol Parameter Condition | Max. Unit CiN Input Capacitance VIN= OV 6 pF Co Input/Output Capacitance Vuo = OV 8 pF Note : This parameter is sampled and not 100% tested Rev.02 / Dec.97 214HYUNDAI HY638100. Series TIMING DIAGRAM READ CYCLE 1 ARE ADDR cs Data Out Note (Read Cycie) 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device and from device to device. 3. WE is high for read cycle. READ CYCLE 2 {RC ADOR [OH _10H oa Previous Data Data Valid y Note (Read Cycle} 1. WE is high for read cycle. 2. Device is continuously selected /CS=VIL. 3. /OE=VIL. agi ant Rev.02 | Dec.97 215HYUNDA I HY638100 Series WRITE CYCLE 1(/OE Clocked) ADDR X AWE ~ oe TLR \ A WW Ww [eee renner eee AW / _... ACW WIM _ WE Data in We fap a re en nr 1AW = ce on AW cs \AN \ AK LTELETTL. _ iDw tDH Data in ! Dath Valid | -__ tWHZ, LHW 4 (7) @) oe (IMM Rev.02 / Dec.07 216HYUNDAI HY638100 Series Notes(Write Cycle) 4. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition among /CS going low, and (WE going low : A write ends at the earliest transition among /CS going high and AWE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of /CS going law to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. (WR is measured from the end of write to the address change. tWR applied in case a write ends as {CS or WE going high. 5. lf (OE and /WE are in the read made during this period, the !/O pins are in the output low-Z state, inputs of opposite phase of the output must not be applied because bus contention can occur. 6. If /CS goes low simultaneously with AWE going low or after AWE going low, the outputs remain in high impedance state. 7. DouT is the same phase of latest written data in the write cycle. 8. Dourt is the read data of the new address. DATA RETENTION ELECTRIC CHARACTERISTIC( L-Version } Ta=OT to 70T Symbol Parameter Test Conditions | Power | Min [ Typ | Max | Unit VoR Vcc for Data Retention | /CS 2Vec -0.2V 2.0 - - Vv Vss = VIN S Voc IccpR Data Retention Current | Voce = 3V, /CS= Vcc-0.2V L - 10 50 uA Vss S VIN = Voc tCDR Chip Deselect to Data | See Data Retention Timing 0 - - ns Retention Time Diagram itR Operating Recovery tRC2 - - ns Time ) Notes 1. Typical values are at the condition of Ta=25 T 2. tRC is read cycle time DATA RETENTION WAVEFORM vec p--DATA RETENTION MODE --4 4.5V 2.2V VDR cs vss > - oo _ - _ RELIABILITY SPEC. TEST MODE TEST SPEC. ESD HBM 2 2000V MM = 250V LATCH - UP = -100mA =4100mA Rev.02 / Dec.97 217HYUNDAI PACKAGE INFORMATION 32pin 400mil Small Outline J-Form Package (J) HY638100 Series 8. 092(0.8128) -| | 2.9400 a6 :: 0.026(0.6604) ' | 0.030(0.762) n coe ores a ae i Cyr | i | |0.408(10.287) 0,990(9.6520) | 0.444(11.2776) 0 395(10 033) 0. 368(9 3472) | 0.496(1 1.0744) | t NY ah | : pee a. | A 80.2489) . 0,829(21.0568) ae oom 248) 0.821(20.8534) : iH ~'0.148(3.759) MAX. PUT ca 0388, 605) UNIT: INCHimm) gay | |, @.0501.27) | "Lo o20(9.508) PBSC ""0.016(0.406) 32pin 400mil Thin Smait Outline Package (T2) _ _ | 0.404(10.2620) | j 0 0.396(10 0580) | a + | UNIT INCH{meny MAX: i 0.470(11; 3380) MIN. {oO oe 0482(11.7350) HeUEEERUER quaeEE ss . o. .B29(21. OS70) ee i 0.822(20.8780) . GAGE PLANE __. wae - BASE PLANE rengoreneeryenO f 1.2700 BSC ,0.017(0.4500) fF ft. SEATING PLANE 4 Gn > kt ~ 0.6160(0.4060) | (0.050) a, 012(0.3050} | 0.0059(0.1500) 0 0036(0.2100 | aes 0038(0.2109) | 0.047(1.1940) 0.0020(0.0500) 0 039(0 9910) 0.0047(0.1200) Rev.02 | Dec.97 218