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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT PD754144, 754244 4-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The PD754244 is a 4-bit single-chip microcontroller which incorporates the EEPROMTM for key-less entry application. It incorporates a 16 x 8-bit EEPROM, a 4-Kbyte mask ROM to store software, a 128 x 4-bit RAM to store the processing data, a processing CPU, and a carrier generator which easily outputs waveforms for infrared remote controller. The details of functions are described in the following user's manual. Be sure to read it before designing. PD754144, 754244 User's Manual: U10676E FEATURES * * * * * * * On-chip EEPROM: 16 x 8 bits (mapped to the data memory) On-chip key return reset function for key-less entry System clock oscillation circuit * PD754144: RC oscillator (external resistor and capacitor) * PD754244: Crystal/ceramic oscillator Low-voltage operation: VDD = 1.8 to 6.0 V Timer function (4 channels) * Basic interval timer/watchdog timer: 1 channel * 8-bit timer counter : 3 channels On-chip memory * Program memory (ROM) 4096 x 8 bits * Data memory (static RAM) 128 x 4 bits Instruction execution time variable function suited for power saving. * PD754144: 4, 8, 16, 64 s (at fcc = 1.0-MHz operation) * PD754244: 0.95, 1.91, 3.81, 15.3 s (at fx = 4.19-MHz operation) 0.67, 1.33, 2.67, 10.7 s (at fx = 6.0-MHz operation) APPLICATIONS Automotive appliances such as key-less entry, compact data carrier, etc. Unless contextually excluded, references in this data sheet to the PD754244 (crystal/ceramic oscillation: fX) mean the PD754144. The PD754144 and PD754244 differ in the notation of their RC oscillation: whenever fX (RC oscillation notation for PD754244) is described, fCC should be substituted for the PD754144. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. U10040EJ2V1DS00 (2nd edition) Date Published August 2005 N CP(K) Printed in Japan The mark shows major revised points. 1995 PD754144, 754244 ORDERING INFORMATION Part Number Package PD754144GS-xxx-BA5 20-pin plastic SOP (300 mil, 1.27-mm pitch) PD754144GS-xxx-BA5-A 20-pin plastic SOP (300 mil, 1.27-mm pitch) PD754144GS-xxx-GJG 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) PD754144GS-xxx-GJG-A 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) PD754244GS-xxx-BA5 20-pin plastic SOP (300 mil, 1.27-mm pitch) PD754244GS-xxx-BA5-A 20-pin plastic SOP (300 mil, 1.27-mm pitch) PD754244GS-xxx-GJG 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) PD754244GS-xxx-GJG-A 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Remarks 1. Products with "-A" at the end of the part number are lead-free products. 2. xxx indicates ROM code suffix. 2 Data Sheet U10040EJ2V1DS PD754144, 754244 Functional Outline PD754144 Parameter Instruction execution time * 4, 8, 16, 64 s (at fcc = 1.0-MHz operation) On-chip Mask ROM 4096 x 8 bits (0000H-0FFFH) memory RAM 128 x 4 bits (000H-07FH) EEPROM 16 x 8 bits (400H-41FH) PD754244 * 0.95, (at fx * 0.67, (at fx 1.91, 3.81, 15.3 s = 4.19-MHz operation) 1.33, 2.67, 10.7 s = 6.0-MHz operation) System clock oscillator RC oscillator (External resistor and capacitor) Crystal/ceramic oscillator General-purpose register * 4-bit operation: 8 x 4 banks * 8-bit operation: 4 x 4 banks Input/output CMOS input 4 On-chip pull-up resistor can be specified by mask option. port CMOS input/output 9 On-chip pull-up resistor connection can be specified by means of software. Total 13 17 15 Start-up time after reset 56/fcc 2 /fx, 2 /fx (selected by mask option) Stand-by mode release time 29/fcc 220/fx, 217/fx, 215/fx, 213/fx Timer 4 channels * 8-bit timer counter (can be used as 16-bit timer counter) : 3 channels * Basic interval/watchdog timer : 1 channel (selected by the setting of BTM) Bit sequential buffer 16 bits Vectored interrupt External: 1, Internal: 5 Test input External: 1 (key return reset function available) Standby function STOP/HALT mode Operating ambient temperature TA = -40 to +85 C Operating supply voltage V DD = 1.8 to 6.0 V Package * 20-pin plastic SOP (300 mil, 1.27-mm pitch) * 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Data Sheet U10040EJ2V1DS 3 PD754144, 754244 CONTENTS 1. PIN CONFIGURATION (TOP VIEW) .................................................................................................... 6 2. BLOCK DIAGRAM ................................................................................................................................8 3. PIN FUNCTION ..................................................................................................................................... 9 3.1 Port Pins ......................................................................................................................................9 3.2 Non-port Pins ............................................................................................................................ 10 3.3 Pin Input/Output Circuits ......................................................................................................... 11 3.4 Recommended Connection of Unused Pins .......................................................................... 12 4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE ............................................... 13 4.1 Difference between Mk I and Mk II Modes .............................................................................. 13 4.2 Setting Method of Stack Bank Select Register (SBS) ........................................................... 14 5. MEMORY CONFIGURATION ............................................................................................................. 15 6. EEPROM ............................................................................................................................................. 18 7. PERIPHERAL HARDWARE FUNCTIONS ......................................................................................... 19 7.1 Digital Input/Output Ports ........................................................................................................ 19 7.2 Clock Generator ........................................................................................................................ 19 7.3 Basic Interval Timer/Watchdog Timer ..................................................................................... 22 7.4 Timer Counter ........................................................................................................................... 23 7.5 Programmable Threshold Port (Analog Input Port) ............................................................... 27 7.6 Bit Sequential Buffer ....... 16 Bits ............................................................................................ 28 8. INTERRUPT FUNCTION AND TEST FUNCTION .............................................................................. 29 9. STANDBY FUNCTION ........................................................................................................................ 31 10. RESET FUNCTION ............................................................................................................................. 32 10.1 Configuration and Operation Status of RESET Function ..................................................... 32 10.2 Watchdog Flag (WDF), Key Return Flag (KRF) ...................................................................... 36 11. MASK OPTION ................................................................................................................................... 38 12. INSTRUCTION SETS .......................................................................................................................... 39 13. ELECTRICAL SPECIFICATIONS ...................................................................................................... 48 13.1 PD754144 ................................................................................................................................. 48 13.2 PD754244 ................................................................................................................................. 56 14. CHARACTERISTICS CURVES (REFERENCE VALUES) ................................................................. 67 14.1 PD754144 ................................................................................................................................. 67 14.2 PD754244 ................................................................................................................................. 69 4 Data Sheet U10040EJ2V1DS PD754144, 754244 15. RC OSCILLATION FREQUENCY CHARACTERISTICS EXAMPLES (REFERENCE VALUES) ..... 72 16. PACKAGE DRAWINGS ...................................................................................................................... 76 17. RECOMMENDED SOLDERING CONDITIONS .................................................................................. 78 APPENDIX A. COMPARISON OF FUNCTIONS AMONG PD754144, 754244, AND 75F4264 ........... 81 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................. 82 APPENDIX C. RELATED DOCUMENTS ................................................................................................ 85 Data Sheet U10040EJ2V1DS 5 PD754144, 754244 1. PIN CONFIGURATION (TOP VIEW) * PD754144 * 20-pin Plastic SOP (300 mil, 1.27-mm pitch) PD754144GS-xxx-BA5 PD754144GS-xxx-BA5-A * 20-pin Plastic Shrink SOP (300 mil, 0.65-mm pitch) PD754144GS-xxx-GJG PD754144GS-xxx-GJG-A RESET 1 20 KRREN CL1 2 19 P80 CL2 3 18 P30/PTO0 VSS 4 17 P31/PTO1 IC 5 16 P32/PTO2 VDD 6 15 P33 P60/AVREF 7 14 P70/KR4 P61/INT0 8 13 P71/KR5 P62/PTH00 9 12 P72/KR6 P63/PTH01 10 11 P73/KR7 IC: Internally Connected (Connect to VDD directly) 6 Data Sheet U10040EJ2V1DS PD754144, 754244 * PD754244 * 20-pin Plastic SOP (300 mil, 1.27-mm pitch) PD754244GS-xxx-BA5 PD754244GS-xxx-BA5-A * 20-pin Plastic Shrink SOP (300 mil, 0.65-mm pitch) PD754244GS-xxx-GJG PD754244GS-xxx-GJG-A RESET 1 20 KRREN X1 2 19 P80 X2 3 18 P30/PTO0 VSS 4 17 P31/PTO1 IC 5 16 P32/PTO2 VDD 6 15 P33 P60/AVREF 7 14 P70/KR4 P61/INT0 8 13 P71/KR5 P62/PTH00 9 12 P72/KR6 P63/PTH01 10 11 P73/KR7 IC: Internally Connected (Connect to VDD directly) Pin Identification AVREF : Analog reference P70 to P73 : Port 7 CL1 and CL2 : System clock (RC) P80 : Port 8 IC : Internally connected PTH00 and PTH01 : Programmable threshold port analog inputs 0 and 1 INT0 : External vectored interrupt 0 PTO0 to PTO2 : Programmable timer outputs 0 to 2 KR4 to KR7 : Key returns 4 to 7 RESET : Reset KRREN : Key return reset enable V DD : Positive power supply P30 to P33 : Port 3 VSS : Ground P60 to P63 : Port 6 X1 and X2 : System clock (crystal/ceramic) Data Sheet U10040EJ2V1DS 7 PD754144, 754244 2. BLOCK DIAGRAM BASIC INTERVAL TIMER/WATCHDOG TIMER PORT3 4 P30 to P33 PORT6 4 P60 to P63 PORT7 4 P70 to P73 SP (8) INTBT RESET ALU PTO0/P30 CY 8-BIT TIMER COUNTER#0 INTT0 TOUT SBS PROGRAM COUNTER INTT1 PTO1/P31 PTO2/P32 BANK 8-BIT TIMER COUNTER#1 CASCADED 8-BIT TIMER COUNTER#2 16-BIT TIMER COUNTER GENERAL REG. PROGRAM MEMORY (ROM) 4096x8 BITS DATA MEMORY (RAM) 128x4 BITS INTT2 PORT8 P80 EEPROM 16x8 BITS INT0/P61 KRREN INTERRUPT CONTROL BIT SEQ. BUFFER (16) DECODE AND CONTROL KR4/P70 to 4 KR7/P73 fX/2N AVREF/P60 PTH00/P62 PTH01/P63 8 PROGRAMMABLE THRESHOLD PORT CPU CLOCK CLOCK SYSTEM CLOCK STAND BY DIVIDER GENERATOR CONTROL CL1 CL2 X1 X2 Apply to the Apply to the PD754144 PD754244 Data Sheet U10040EJ2V1DS IC VDD VSS RESET PD754144, 754244 3. PIN FUNCTION 3.1 Port Pins Pin Name P30 Input/Output Alternate Function Input/Output PTO0 P31 PTO1 P32 PTO2 P33 - P60 Input/Output AVREF 8-bit I/O After Reset I/O Circuit TYPE Note 1 Programmable 4-bit input/output port (PORT3). This port can be specified input/output bitwise. On-chip pull-up resistor connection can be specified by software in 4-bit units. - Input E-B Programmable 4-bit input/output port (PORT6). This port can be specified input/output bitwise. On-chip pull-up resistor can be specified by software in 4-bit unitsNote2. - Input F -A Function P61 INT0 P62 PTH00 P63 PTH01 Noise eliminator can be selected with P61/INT0. KR4 4-bit input port (PORT7). On-chip pull-up resistor can be specified by software bit-wise. - Input B -A 1-bit input/output port (PORT8). On-chip pull-up resistor connection can be specified by software. - Input F -A P70 Input P71 KR5 P72 KR6 P73 KR7 P80 Input/Output Notes 1. 2. - Circled characters indicate the Schmitt-trigger input. Do not specify an on-chip pull-up resistor connection when using the programmable threshold port. Data Sheet U10040EJ2V1DS 9 PD754144, 754244 3.2 Non-port Pins Pin Name PTO0 Input/Output Output Alternate P30 PTO1 P31 PTO2 P32 INT0 Input P61 KR4 to KR7 Input P70 to P73 PTH00 Input P62 PTH01 Input - AV REF Input P60 - - CL2 - X1 Input X2 RESET I/O Circuit TYPENote Input E-B Input F -A Falling edge detection testable input pins Input B -A Threshold voltage-variable 2-bit analog input pins Input F -A Key return reset enable pin The reset signal is generated at the falling edge of KRn while KRREN is high in STOP mode. Input B Reference voltage input pin Input F -A - - - - - B -A - - Timer counter output pins Edge detection vectored interrupt input pin (detected edge can be selected) Noise elimination circuit can be selected. Noise elimination circuit can be selected. Asynchronous input P63 KRREN CL1 After Reset Function Function RC (for system clock oscillation) connection pin External clock cannot be input. - Incorporated in the PD754244 only Crystal/ceramic resonator (for system clock oscillation) connection pin When inputting the external clock, input the external clock to pin X1 and input the inverted phase of the external clock to pin X2. - Input Incorporated in the PD754144 only - System reset input pin (low-level active) Pull-up resistor can be incorporated (mask option). IC - - Internally Connected V DD - - Positive supply pin - - V SS - - Ground potential - - Note 10 Connect directly to V DD. Circled characters indicate the Schmitt-trigger input. Data Sheet U10040EJ2V1DS PD754144, 754244 3.3 Pin Input/Output Circuits The PD754244 pin input/output circuits are shown schematically. TYPE A TYPE D VDD VDD data P-ch OUT P-ch IN N-ch output disable N-ch Push-pull output that can be placed in output high-impedance (both P-ch, N-ch off). CMOS specification input buffer. TYPE E-B TYPE B VDD P.U.R. P.U.R. enable IN P-ch data Type D IN/OUT output disable Type A Schmitt-trigger input having hysteresis characteristic. P.U.R. : Pull-Up Resistor TYPE F-A TYPE B-A VDD VDD P.U.R. P.U.R. enable P.U.R. (Mask Option) P-ch data IN output disable P.U.R. : Pull-Up Resistor IN/OUT Type D Type B P.U.R. : Pull-Up Resistor Data Sheet U10040EJ2V1DS 11 PD754144, 754244 3.4 Recommended Connection of Unused Pins Table 3-1. List of Recommended Connection of Unused Pins Pin Recommended Connecting Method P30/PTO0 Input state : Independently connect to VSS or VDD via a resistor. P31/PTO1 Output state: Leave open. P32/PTO2 P33 P60/AVREF P61/INT0 P62/PTH00 P63/PTH01 P70/KR4 Connect to V DD. P71/KR5 P72/KR6 P73/KR7 P80 Input state : Independently connect to VSS or VDD via a resistor. Output state: Leave open. 12 KRREN When this pin is connected to VDD, internal reset signal is generated at the falling edge of the KRn pin in the STOP mode. When this pin is connected to VSS, internal reset signal is not generated even if the falling edge of KRn pin is detected in the STOP mode. IC Connect directly to VDD. Data Sheet U10040EJ2V1DS PD754144, 754244 4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE 4.1 Difference between Mk I and Mk II Modes The PD754244 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by the bit 3 of the Stack Bank Select register (SBS). * Mk I mode: Instructions are compatible with the 75X series. Can be used in the 75XL CPU with a ROM * Mk II mode: Incompatible with 75X series. Can be used in all the 75XL CPU's including those products capacity of up to 16 Kbytes. whose ROM capacity is more than 16 Kbytes. Table 4-1. Differences between Mk I Mode and Mk II Mode Mk I Mode Mk II Mode Number of stack bytes for subroutine instructions 2 bytes 3 bytes BRA !addr1 instruction CALLA !addr1 instruction Not available Available CALL !addr instruction 3 machine cycles 4 machine cycles CALLF !faddr instruction 2 machine cycles 3 machine cycles Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series. Therefore, this mode is effective for enhancing software compatibility with products that have a program area of more than 16 Kbytes. With regard to the number of stack bytes during execution of subroutine call instructions, the usable area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected. However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and processing performance than on software compatibility, the Mk I mode should be used. Data Sheet U10040EJ2V1DS 13 PD754144, 754244 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program. When using the Mk II mode, it must be initialized to 0000B. Figure 4-1. Stack Bank Select Register Format Address 3 F84H SBS3 2 1 SBS2 SBS1 0 Symbol SBS0 SBS Stack area specification 0 0 Memory bank 0 Other than above setting prohibited 0 0 must be set in the bit 2 position Mode switching specification 0 Mk II mode 1 Mk I mode Caution Because SBS. 3 is set to "1" after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to "0" to select the Mk II mode. 14 Data Sheet U10040EJ2V1DS PD754144, 754244 5. MEMORY CONFIGURATION * Program memory (ROM) * *** 4096 x 8 bits Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset and start are possible at an arbitrary address. * Addresses 0002H to 000FH Vector table wherein the program start address and values set for the RBE and MBE by the vectored interrupts are written. Interrupt service can be started at an arbitrary address. * Addresses 0020H to 007FH Table area referenced by the GETI instructionNote. Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the program steps. * Data memory * * Data area Static RAM *** 128 words x 4 bits (000H to 07FH) EEPROM *** 16 words x 8 bits (400H to 41FH) Peripheral hardware area *** 128 words x 4 bits (F80H to FFFH) Data Sheet U10040EJ2V1DS 15 PD754144, 754244 Figure 5-1. Program Memory Map Address 0000H 7 6 5 4 MBE RBE 0 0 0001H 0002H MBE RBE 0 0 0003H 0004H MBE RBE 0 0 0005H 0 Internal reset start address (high-order 4 bits) Internal reset start address (low-order 8 bits) INTBT start address (high-order 4 bits) INTBT start address (low-order 8 bits) INT0 start address (high-order 4 bits) INT0 start address (low-order 8 bits) CALLF !faddr instruction entry address 0006H 0007H 0008H 0009H 000AH MBE RBE 0 0 000BH 000CH MBE RBE 0 0 000DH 000EH 000FH MBE RBE 0 0 INTT0 start address (high-order 4 bits) INTT0 start address (low-order 8 bits) INTT1/INTT2 start address (high-order 4 bits) INTT1/INTT2 start address (low-order 8 bits) INTEE start address (high-order 4 bits) INTEE start address (low-order 8 bits) Branch address of BR !addr BRCB !caddr BR BCDE BR BCXA BRA !addrNote CALL !addr CALLA !addrNote instructions GETI Branch/call Addresses BR $addr instruction relative branch address (-15 to -1, +2 to +16) 0020H GET instruction reference table 007FH 0080H 07FFH 0800H 0FFFH Note Can be used in the MkII mode only. Remark In addition to the above, a branch can be made to an address with the low-order 8-bits only of the PC changed by means of a BR PCDE or BR PCXA instruction. 16 Data Sheet U10040EJ2V1DS PD754144, 754244 Figure 5-2. Data Memory Map Data memory 000H General-purpose register area 01FH 020H Data area static RAM (128 x 4) Memory bank (32 x 4) Stack area 128 x 4 (96 x 4) 0 07FH 080H 0FFH Not incorporated 400H Data area EEPROM (16 x 8) 16 x 8 4 41FH 420H 4FFH Not incorporated F80H 128 x 4 Peripheral hardware area 15 FFFH Data Sheet U10040EJ2V1DS 17 PD754144, 754244 6. EEPROM The PD754244 incorporates 16 words x 8 bit EEPROM (Electrically Erasable PROM) as well as static RAM (128 words x 4 bit) as a data memory. The EEPROM incorporated into the PD754244 has the following features. (1) Written data is retained if power is turned off. (2) 8-bit data manipulation (auto-erase/auto-write) is available by memory manipulation instruction as well as for static RAM. However available instructions are restricted. (3) It can reduce loads of software because the auto-erase and/or auto-write operation is performed by hardware. (4) Write operation control using the interrupt request The interrupt request is generated under following conditions. * Terminates write operation * Write status flag It is possible to check whether enables or disables write operation by bit manipulation instructions. 18 Data Sheet U10040EJ2V1DS PD754144, 754244 7. PERIPHERAL HARDWARE FUNCTIONS 7.1 Digital Input/Output Ports The following two types of I/O ports are provided. * CMOS input (Port 7) : 4 * CMOS I/O (Ports 3, 6, 8) : 9 Total : 13 Table 7-1. Types and Features of Digital Ports Port Name PORT3 Function 4-bit I/O Operation and Features Can be set to input or output mode bit-wise. PORT6 Remarks Also used as PTO0 to PTO2 pins. Also used as AVREF, INT0, PTH00, and PTH01 pins. PORT7 4-bit input 4-bit input only port Also used as KR4 to KR7 pins. On-chip pull-up resistor connection can be specified by mask option bit-wise. PORT8 1-bit I/O Can be set to input or output mode bit wise. _ 7.2 Clock Generator The clock generator provides the clock signals to the CPU and peripheral hardware. Its configuration is shown in Figures 7-1 and 7-2. The operation of the clock generator is set with the processor clock control register (PCC). The instruction execution time can be changed. * PD754144 * 4, 8, 16, 64 s (when the system clock fCC operates at 1.0 MHz) * PD754244 * 0.95, 1.91, 3.81, 15.3 s (when the system clock fX operates at 4.19 MHz) * 0.67, 1.33, 2.67, 10.7 s (when the system clock fX operates at 6.0 MHz) Data Sheet U10040EJ2V1DS 19 PD754144, 754244 Figure 7-1. PD754144 (RC Oscillation) Clock Generator Block Diagram * Basic interval timer (BT) * Timer counter * INT0 noise eliminator CL1 CL2 System clock oscillator 1/1~1/4096 fcc Divider Selector 1/2 1/4 1/16 Oscillation stops Divider Internal bus 1/4 * CPU * INT0 noise eliminator PCC PCC0 PCC1 HALT F/F 4 PCC2 S HALTNote PCC3 R STOPNote PCC2, PCC3 clear STOP F/F Q Wait release signal from BT S Reset signal Standby release signal from interrupt control circuit R Note Instruction execution Remarks 1. 20 Q fcc: System clock frequency 2. = CPU clock 3. PCC: Processor Clock Control Register 4. One clock cycle (t CY) of the CPU clock is equal to one machine cycle of the instruction. Data Sheet U10040EJ2V1DS PD754144, 754244 Figure 7-2. PD754244 (Crystal/Ceramic Oscillation) Clock Generator Block Diagram * Basic interval timer (BT) * Timer counter * INT0 noise eliminator X1 X2 System clock oscillator 1/1~1/4096 fX Divider Selector 1/2 1/4 1/16 Oscillation stops Divider Internal bus 1/4 * CPU * INT0 noise eliminator PCC PCC0 PCC1 HALT F/F 4 PCC2 S HALTNote PCC3 R STOPNote PCC2, PCC3 clear STOP F/F Q Wait release signal from BT S Reset signal Standby release signal from interrupt control circuit R Note Q Instruction execution Remarks 1. fX: System clock frequency 2. = CPU clock 3. PCC: Processor Clock Control Register 4. One clock cycle (t CY) of the CPU clock is equal to one machine cycle of the instruction. Data Sheet U10040EJ2V1DS 21 PD754144, 754244 7.3 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. (a) Interval timer operation to generate a reference time interrupt (b) Watchdog timer operation to detect a runaway of program and reset the CPU (c) Selects and counts the wait time when the standby mode is released (PD754244 only)Note 1 (d) Reads the contents of counting Figure 7-3. Basic Interval Timer/Watchdog Timer Block Diagram From clock generator Clear Clear fX/25 fX/27 MPX Basic interval timer (8-bit frequency divider) Set fX/29 BT fX/212 3 Wait release signal when standby is releasedNote 1. BTM3 BTM2 BTM1 BTM0 BTM 4 SET1Note 2 BT interrupt request flag Vectored interrupt IRQBT request signal Internal reset signal WDTM SET1Note 2 8 1 Internal bus Notes 1. In the PD754144 (RC oscillation), the wait time cannot be specified when the standby mode is released. The oscillation stabilization wait time is negligible in the PD754144 and this device returns to the normal operation mode after counting 29/fCC (512 s: @ fCC = 1.0-MHz operation). In the PD754244 (crystal/ceramic oscillation), on the other hand, the wait time can be specified when the standby mode is released. 2. 22 Instruction execution. Data Sheet U10040EJ2V1DS PD754144, 754244 7.4 Timer Counter The PD754244 incorporates three channels of timer counters. Its configuration is shown in Figures 7-4 to 7-6. The timer counter has the following functions. (a) Programmable interval timer operation (b) Square wave output of any frequency to PTO0-PTO2 pins (c) Count value read function The timer counter can operate in the following four modes as set by the mode register. Table 7-2. Mode List Channel Mode Channel 0 Channel 1 Channel 2 8-bit timer counter mode TM10 TM21 TM20 0 0 0 0 0 0 0 1 PWM pulse generator mode x 16-bit timer counter mode x 1 0 1 0 Carrier generator mode x 0 0 1 1 Remark : x : x TM11 Available Not available Data Sheet U10040EJ2V1DS 23 24 Figure 7-4. Timer Counter (Channel 0) Block Diagram Internal bus 8 SET1Note 8 8 - TM06 TM05 TM04 TM03 TM02 0 TOE0 TMOD0 TM0 T0 enable flag Modulo register (8) 0 PORT3.0 P30 Output latch PMGA bit 0 Port 3 input/output mode 8 Match Comparator (8) TOUT F/F P30/PTO0 Output buffer 8 Reset T0 Data Sheet U10040EJ2V1DS fx/24 From clock fx/26 generator fx/28 MPX CP Count register (8) Clear fx/210 Timer operation start INTT0 IRQT0 set signal RESET IRQT0 clear signal Note Instruction execution PD754144, 754244 Caution When setting data to TM0, be sure to set bits 0 and 1 to 0. Figure 7-5. Timer Counter (Channel 1) Block Diagram Internal bus 8 SET Note TOE1 TM1 - 8 T1 enable flag TM16 TM15 TM14 TM13 TM12 TM11 TM10 TMOD1 Decoder PORT3.1 P31 Output latch PMGA bit 1 Port 3 input/output mode Modulo register (8) 8 Match Comparator (8) Timer counter (channel 2) output Data Sheet U10040EJ2V1DS From clock generator fx/25 fx/26 fx/28 TOUT F/F 8 P31/PTO1 Output buffer Reset T1 MPX CP Count register (8) Clear fx/210 fx/212 RESET Timer operation start 16 bit timer counter mode IRQT1 clear signal Selector Timer counter (channel 2) reload signal Timer counter (channel 2) comparator (When 16-bit timer counter mode) Note Instruction execution 25 PD754144, 754244 Timer counter (channel 2) match signal (When 16-bit timer counter mode) INTT1 IRQT1 set signal 26 Figure 7-6. Timer Counter (Channel 2) Block Diagram Internal bus 8 TM2 8 TMODH High-level period setting modulo register (8) TM26 TM25 TM24 TM23 TM22 TM21 TM20 Modulo register (8) 8 - - - PORT3.2 TC2 Output latch TOE2 REMC NRZB NRZ PMGA bit 2 Port 3 input/output mode Reload MPX (8) 8 Match TOUT F/F Comparator (8) From clock generator 0 8 Decoder Data Sheet U10040EJ2V1DS fx fx/2 fx/24 fx/26 fx/28 fx/210 8 TMOD2 8 Reset T2 MPX CP Overflow Count register (8) P32/PTO2 Output buffer Selector - SET Selector 8 Note Timer counter (channel 1) clock input Carrier generator mode Clear INTT2 IRQT2 set signal 16-bit timer counter mode IRQT2 clear signal Timer operation start RESET Timer counter (channel 1) clear signal (When 16-bit timer mode) Timer counter (channel 1) match signal (When 16-bit timer counter mode) Timer counter (channel 1) match signal (When Carrier generator mode) Note Instruction execution Caution When setting data to TC2, be sure to set bit 7 to 0. PD754144, 754244 PD754144, 754244 7.5 Programmable Threshold Port (Analog Input Port) The PD754244 provides analog input pins (PTH00, PTH01) whose threshold voltage (reference voltage) is selectable within sixteen steps. The following operations can be performed with these analog input pins. (1) Comparator operation (2) 4-bit resolution A/D converter operation (controlled by software) Caution Do not specify an on-chip pull-up resistor connection for Port 6 when using the programmable threshold port. Figure 7-7. Programmable Threshold Port Block Diagram PTH0 PTH00 Input buffer + - Programmable threshold port input latch (2) PTH01 Input buffer + Operate/stop Standby mode signal AVREF Internal bus - PTHM7 1 R 2 PTHM6 PTHM5 R PTHM4 R 8 MPX PTHM3 VREF PTHM2 PTHM1 1 R 2 PTHM0 PTHM Data Sheet U10040EJ2V1DS 27 PD754144, 754244 7.6 Bit Sequential Buffer ....... 16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing large data bit-wise. Figure 7-8. Bit Sequential Buffer Format Address Bit FC3H 3 Symbol L register 2 1 FC2H 0 3 2 BSB3 L = FH 1 FC1H 0 3 BSB2 L = CH L = BH 2 1 FC0H 0 3 BSB1 L = 8H L = 7H 2 1 0 BSB0 L = 4H L = 3H L = 0H DECS L INCS L Remarks 1. 2. 28 In the pmem.@L addressing, the specified bit moves corresponding to the L register. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MSB specification. Data Sheet U10040EJ2V1DS PD754144, 754244 8. INTERRUPT FUNCTION AND TEST FUNCTION Figure 8-1 shows the interrupt control circuit. Each hardware device is mapped in the data memory space. The interrupt control circuit of the PD754244 has the following functions. (1) Interrupt function * Vectored interrupt function for hardware control, enabling/disabling the interrupt acknowledgement by the interrupt enable flag (IExxx) and interrupt master enable flag (IME). * Can set any interrupt start address. * Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). * Test function of interrupt request flag (IRQxxx). An interrupt generated can be checked by software. * Release the standby mode. A release interrupt can be selected by the interrupt enable flag. (2) Test function * Test request flag (IRQ2) generation can be checked by software. * Release the standby mode. The test source to be released can be selected by the test enable flag. Data Sheet U10040EJ2V1DS 29 30 Figure 8-1. Interrupt Control Circuit Block Diagram Internal bus 2 4 Interrupt enable flag (IExxx) IM2 IME IPS IST1 IST0 IM0 Decoder VRQn Data Sheet U10040EJ2V1DS INT0/P61 Note1 KR4/P70 Selector INTBT Edge detector IRQBT IRQ0 INTT0 IRQT0 INTT1 IRQT1 INTT2 IRQT2 INTEE IRQEE Falling edge detectorNote2 Vector table address generator Priority control ciricuit IRQ2 KR7/P73 Key return reset circuit Notes 1. 2. Noise eliminator (Standby release is disable when noise eliminator is selected.) The INT2 pin is not provided. Interrupt request flag (IRQ2) is set at the KRn pin falling edge when IM20 = 1 and IM21 = 0. PD754144, 754244 IM2 Standby release signal PD754144, 754244 9. STANDBY FUNCTION In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the PD754244. Table 9-1. Operation Status in Standby Mode Mode Item STOP Mode HALT Mode Set instruction STOP instruction HALT instruction Operation status Clock generator Operation stops. Only the CPU clock halts (oscillation continues). Basic interval timer/ watchdog timer Operation stops. Operable BT mode: The IRQBT is set in the basic time interval. WT mode: Reset is generated by the BT overflow. Timer Operation stops. Operable. External interrupt INT0 is not operable.Note INT2 is operable during KRn falling period only. CPU Release signal Note The operation stops. * Reset signal * Interrupt request signal sent from interrupt enabled peripheral hardware * System reset signal (key return reset) generated by KRn falling edge when the KRREN pin = 1 * Reset signal * Interrupt request signal sent from interrupt enabled peripheral hardware Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register (IM0). Data Sheet U10040EJ2V1DS 31 PD754144, 754244 10. RESET FUNCTION 10.1 Configuration and Operation Status of RESET Function There are three kinds of reset input: the external reset signal (RESET), the reset signal sent from the basic interval/watchdog timer, and the reset signal generated by a falling edge signal from KRn in the STOP mode. When any of these reset signals is input, an internal reset signal is generated. The configuration is shown in Figure 10-1. Figure 10-1. Configuration of Reset Function VDD Mask option RESET Internal reset signal Output buffer Watchdog timer overflow S R Q WDF Q KRF Instruction KRREN S R Q R S Instruction STOP mode VDD One-shot pulse generator Interrupt Falling edge detector Mask option Internal bus P70/KR4 P71/KR5 P72/KR6 P73/KR7 32 Data Sheet U10040EJ2V1DS PD754144, 754244 Each hardware is initialized by the RESET signal generation as listed in Table 10-1. Figure 10-2 shows the timing chart of the reset operation. Figure 10-2. Reset Operation by RESET Signal Generation WaitNote RESET signal generated Operation mode or standby mode HALT mode Operation mode Internal reset operation Note In the PD754144, the wait time is fixed to 56/fcc (56s: @ 1.0-MHz operation). In the PD754244, the wait time can be selected from the following two time settings by means of the mask option. 2 17/fx (21.8 ms : @ 6.0-MHz operation, 31.3 ms: @ 4.19-MHz operation) 2 15/fx (5.46 ms : @ 6.0-MHz operation, 7.81 ms: @ 4.19-MHz operation) Data Sheet U10040EJ2V1DS 33 PD754144, 754244 Table 10-1. Hardware Status After Reset (1/3) RESET signal generation in the standby mode RESET signal generation in operation Sets the low-order 4 bits of program memory's address 0000H to the PC11-PC8 and the contents of address 0001H to the PC7-PC0. Sets the low-order 4 bits of program memory's address 0000H to the PC11-PC8 and the contents of address 0001H to the PC7-PC0. Held Undefined Skip flag (SK0 to SK2) 0 0 Interrupt status flag (IST0, IST1) 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined Undefined 1000B 1000B Held Undefined Hardware Program counter (PC) PSW Carry flag (CY) Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank select register (SBS) Data memory (RAM) Data memory (EEPROM) Held EEPROM write control register (EWC) Note 1 HeldNote 2 0 0 General-purpose register (X, A, H, L, D, E, B, C) Held Undefined Bank select register (MBS, RBS) 0, 0 0, 0 Undefined Undefined Basic interval Counter (BT) timer/watchdog Mode register (BTM) 0 0 timer Watchdog timer enable flag (WDTM) 0 0 Timer counter Counter (T0) 0 0 (channel 0) Modulo register (TMOD0) FFH FFH 0 0 0, 0 0, 0 0 0 FFH FFH 0 0 0, 0 0, 0 0 0 Mode register (TM0) TOE0, TOUT F/F Timer counter Counter (T1) (channel 1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Timer counter Counter (T2) (channel 2) Modulo register (TMOD2) FFH FFH High-level period setting modulo register (TMOD2H) FFH FFH 0 0 0, 0 0, 0 0, 0, 0 0, 0, 0 Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB Notes 1. Undefined if STOP mode is entered during an EEPROM write operation. Also undefined if HALT mode is entered during a write operation and a RESET signal is input during a write operation. 2. 34 If a RESET signal is input during an EEPROM write operation, the data at that address is undefined. Data Sheet U10040EJ2V1DS PD754144, 754244 Table 10-1. Hardware Status After Reset (2/3) Hardware RESET signal generation in the standby mode RESET signal generation in operation 00H 00H 0 0 Reset (0) Reset (0) Programmable threshold port mode register (PTHM) Clock generator Processor clock control register (PCC) Interrupt Interrupt request flag (IRQxxx) function Interrupt enable flag (IExxx) 0 0 Interrupt priority selection register (IPS) 0 0 INT0, 2 mode registers (IM0, IM2) 0, 0 0, 0 Output buffer Off Off Output latch Cleared (0) Cleared (0) I/O mode registers (PMGA, C) 0 0 Pull-up resistor setting register (POGA, B) 0 0 Held Undefined Digital port Bit sequential buffer (BSB0-BSB3) Table 10-1. Hardware Status After Reset (3/3) RESET signal generation by key return reset RESET signal generation in the standby mode RESET signal generation by WDT during operation RESET signal generation during operation Watchdog flag (WDF) Hold the previous status 0 1 0 Key return flag (KRF) 1 0 Hold the previous status 0 Hardware Data Sheet U10040EJ2V1DS 35 PD754144, 754244 10.2 Watchdog Flag (WDF), Key Return Flag (KRF) The WDF is cleared by a watchdog timer overflow signal, and the KRF is set by a reset signal generated by the KRn pins. As a result, by checking the contents of WDF and KRF, it is possible to know what kind of reset signal is generated. As the WDF and KRF are cleared only by external signal or instruction execution, if once these flags are set, they are not cleared until an external signal is generated or a clear instruction is executed. Check and clear the contents of WDF and KRF after reset start operation by executing SKTCLR instruction and so on. Table 10-2 lists the contents of WDF and KRF corresponding to each signal. Figure 10-3 shows the WDF operation in generating each signal, and Figure 10-4 shows the KRF operation in generating each signal. Table 10-2. WDF and KRF Contents Correspond to Each Signal Hardware External RESET signal generation Reset signal Reset signal generation by watch- generation by the dog timer overflow KRn input WDF clear instruction execution KRF clear instruction execution Watchdog flag (WDF) 0 1 Hold 0 Hold Key return flag (KRF) 0 Hold 1 Hold 0 Figure 10-3. WDF Operation in Generating Each Signal Reset signal generation by watchdog timer overflow External RESET signal generation Reset signal generation by watchdog timer overflow WDF clear instruction execution WDF External RESET Operation mode HALT mode Operation mode HALT mode Operation mode HALT mode Operation mode Operation mode Internal reset operation 36 Internal reset operation Data Sheet U10040EJ2V1DS Internal reset operation PD754144, 754244 Figure 10-4. KRF Operation in Generating Each Signal Reset signal generation by the KRn input Reset signal generation by the KRn input STOP instruction execution External RESET signal generation STOP instruction execution KRF clear instruction execution KRF External RESET Operation mode STOP mode HALT mode Operation mode HALT mode Operation mode STOP mode HALT mode Operation mode Operation mode Internal reset operation Internal reset operation Data Sheet U10040EJ2V1DS Internal reset operation 37 PD754144, 754244 11. MASK OPTION The PD754244 has the following mask options: * Mask option of P70/KR4 to P73/KR7 On-chip pull-up resistor connection can be specified for these pins. (1) Do not connect an on-chip pull-up resistor (2) Connect the 100-k (typ.) pull-up resistor bit-wise * Mask option of RESET pin On-chip pull-up resistor connection can be specified for this pin. (1) Do not connect an on-chip pull-up resistor (2) Connect the 100-k (typ.) pull-up resistor * Standby function mask option (PD754244 only) Note The wait time when the RESET signal is input can be selected. (1) 2 17/fX (21.8 ms: @ fX = 6.0-MHz operation, 31.3 ms: @ fX = 4.19-MHz operation) (2) 2 15/fX (5.46 ms: @ fX = 6.0-MHz operation, 7.81 ms: @ fX = 4.19-MHz operation) Note This mask option is not provided for the PD754144, and its wait time is fixed to 56/fCC (56 s: @ fCC = 1.0-MHz operation). 38 Data Sheet U10040EJ2V1DS PD754144, 754244 12. INSTRUCTION SETS (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to "RA75X ASSEMBLER PACKAGE USERS' MANUAL -- LANGUAGE (EEU-1367)". If there are several elements, one of them is selected. Capital letters and the + and - symbols are key words and are described as they are. For immediate data, appropriate numbers and labels are described. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be described. However, there are restrictions in the labels that can be described for fmem and pmem. For details, refer to "PD754144, 754244 user's manual (U10676E)". Expression format Description method reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 rp' rp'1 XA, BC, BC, XA, BC, rpa rpa1 HL, HL+, HL-, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or labelNote 2-bit immediate data or label fmem pmem FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label addr addr1 caddr faddr 000H-FFFH immediate data or label 000H-FFFH immediate data or label 12-bit immediate data or label 11-bit immediate data or label taddr 20H-7FH immediate data (where bit 0 = 0) or label PORTn IExxx RBn MBn PORT3, 6, 7, 8 IEBT, IET0-IET2, IE0, IE2, IEEE RB0-RB3 MB0, MB4, MB15 BC, DE, DE BC, DE, DE, HL HL DE, HL, XA', BC', DE', HL' HL, XA', BC', DE', HL' Note mem can be only used for even address in 8-bit data processing. Data Sheet U10040EJ2V1DS 39 PD754144, 754244 (2) Legend in explanation of operation 40 A : A register, 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register X : X register XA : XA register pair; 8-bit accumulator BC : BC register pair DE : DE register pair HL : HL register pair XA' : XA' extended register pair BC' : BC' extended register pair DE' : DE' extended register pair HL' : HL' extended register pair PC : Program counter SP : Stack pointer CY : Carry flag, bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 3, 6, 7, 8) IME : Interrupt master enable flag IPS : Interrupt priority selection register IExxx : Interrupt enable flag RBS : Register bank selection register MBS : Memory bank selection register PCC : Processor clock control register . : Separation between address and bit (xx) : The contents addressed by xx xxH : Hexadecimal data Data Sheet U10040EJ2V1DS PD754144, 754244 (3) Explanation of symbols under addressing area column *1 MB = MBE*MBS (MBS = 0, 4, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1 : MB = MBS (MBS = 0, 4, 15) *4 MB = 15, fmem = FB0H to FBFH, FF0H to FFFH *5 MB = 15, pmem = FC0H to FFFH *6 addr = 000H to FFFH *7 addr = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 addr1 = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 *8 caddr = 000H to FFFH *9 faddr = 0000H to 07FFH *10 taddr = 0020H to 007FH *11 addr1 = 000H to FFFH Remarks 1. Data memory addressing Program memory addressing MB indicates memory bank that can be accessed. 2. In *2, MB = 0 independently of how MBE and MBS are set. 3. In *4 and *5, MB = 15 independently of how MBE and MBS are set. 4. *6 to *11 indicate the areas that can be addressed. (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. * When no skip is made: S = 0 * When the skipped instruction is a 1- or 2-byte instruction: S = 1 * When the skipped instruction is a 3-byte instructionNote: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr, or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by setting PCC. Data Sheet U10040EJ2V1DS 41 PD754144, 754244 Instruction group Transfer instruction Mnemonic MOV XCH Table reference instructions Note 42 MOVT Number of bytes Number of machine cycles A, #n4 1 1 A n4 reg1, #n4 2 2 reg1 n4 XA, #n8 2 2 XA n8 String effect A HL, #n8 2 2 HL n8 String effect B rp2, #n8 2 2 rp2 n8 A, @HL 1 1 A (HL) *1 A, @HL+ 1 2+S A (HL), then L L+1 *1 L=0 A, @HL- 1 2+S A (HL), then L L-1 *1 L = FH A, @rpa1 1 1 A (rpa1) *2 XA, @HL 2 2 XA (HL) *1 @HL, A 1 1 (HL) A *1 @HL, XA 2 2 (HL) XA *1 A, mem 2 2 A (mem) *3 XA, mem 2 2 XA (mem) *3 mem, A 2 2 (mem) A *3 mem, XA 2 2 (mem) XA *3 A, reg 2 2 A reg XA, rp' 2 2 XA rp' reg1, A 2 2 reg1 A rp'1, XA 2 2 rp'1 XA A, @HL 1 1 A (HL) *1 A, @HL+ 1 2+S A (HL), then L L+1 *1 L=0 A, @HL- 1 2+S A (HL), then L L-1 *1 L = FH A, @rpa1 1 1 A (rpa1) *2 XA, @HL 2 2 XA (HL) *1 A, mem 2 2 A (mem) *3 XA, mem 2 2 XA (mem) *3 A, reg1 1 1 A reg1 XA, rp' 2 2 XA rp' XA, @PCDE 1 3 XA (PC11-8+DE)ROM XA, @PCXA 1 3 XA (PC11-8+XA)ROM XA, @BCDE 1 3 XA (BCDE)ROMNote *6 XA, @BCXA 1 3 XA (BCXA)ROMNote *6 Operand Operation Set "0" in register B. Data Sheet U10040EJ2V1DS Addressing area Skip condition String effect A PD754144, 754244 Instruction group Bit transfer instructions Operation instructions Number of bytes Number of machine cycles CY, fmem.bit 2 2 CY (fmem.bit) *4 CY, pmem.@L 2 2 CY (pmem7-2+L3-2.bit(L1-0)) *5 CY, @H+mem.bit 2 2 CY (H+mem3-0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) CY *4 pmem.@L, CY 2 2 (pmem7-2+L3-2.bit(L1-0)) CY *5 @H+mem.bit, CY 2 2 (H+mem3-0.bit) CY *1 A, #n4 1 1+S A A+n4 carry XA, #n8 2 2+S XA XA+n8 carry A, @HL 1 1+S A A+(HL) XA, rp' 2 2+S XA XA+rp' carry rp'1, XA 2 2+S rp'1 rp'1+XA carry A, @HL 1 1 A, CY A+(HL)+CY XA, rp' 2 2 XA, CY XA+rp'+CY rp'1, XA 2 2 rp'1, CY rp'1+XA+CY A, @HL 1 1+S A A-(HL) XA, rp' 2 2+S XA XA-rp' borrow rp'1, XA 2 2+S rp'1 rp'1-XA borrow A, @HL 1 1 A, CY A-(HL)-CY XA, rp' 2 2 XA, CY XA-rp'-CY rp'1, XA 2 2 rp'1, CY rp'1-XA-CY A, #n4 2 2 A A n4 A, @HL 1 1 A A (HL) XA, rp' 2 2 XA XA rp' rp'1, XA 2 2 rp'1 rp'1 XA A, #n4 2 2 A A n4 A, @HL 1 1 A A (HL) XA, rp' 2 2 XA XA rp' rp'1, XA 2 2 rp'1 rp'1 XA A, #n4 2 2 A A v n4 A, @HL 1 1 A A v (HL) XA, rp' 2 2 XA XA v rp' rp'1, XA 2 2 rp'1 rp'1 v XA RORC A 1 1 CY A0, A3 CY, An-1 An NOT A 2 2 AA Mnemonic MOV1 ADDS ADDC SUBS SUBC AND OR XOR Accumulator manipulation instructions Operand Operation Data Sheet U10040EJ2V1DS Addressing area *1 Skip condition carry *1 *1 borrow *1 *1 *1 *1 43 PD754144, 754244 Instruction group Increment and Decrement instructions Number of bytes Number of machine cycles reg 1 1+S reg reg+1 reg=0 rp1 1 1+S rp1 rp1+1 rp1=00H @HL 2 2+S (HL) (HL)+1 *1 (HL)=0 mem 2 2+S (mem) (mem)+1 *3 (mem)=0 reg 1 1+S reg reg-1 reg=FH rp' 2 2+S rp' rp'-1 rp'=FFH reg, #n4 2 2+S Skip if reg = n4 reg=n4 @HL, #n4 1 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 2 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A=reg XA, rp' 2 2+S Skip if XA = rp' XA=rp' SET1 CY 1 1 CY 1 CLR1 CY 1 1 CY 0 SKT CY 1 1+S NOT1 CY 1 1 CY CY SET1 mem.bit 2 2 (mem.bit) 1 *3 fmem.bit 2 2 (fmem.bit) 1 *4 pmem.@L 2 2 (pmem7-2+L3-2.bit(L1-0)) 1 *5 @H+mem.bit 2 2 (H+mem3-0.bit) 1 *1 mem.bit 2 2 (mem.bit) 0 *3 fmem.bit 2 2 (fmem.bit) 0 *4 pmem.@L 2 2 (pmem7-2+L3-2.bit(L1-0)) 0 *5 @H+mem.bit 2 2 (H+mem3-0.bit) 0 *1 mem.bit 2 2+S Skip if (mem.bit)=1 *3 (mem.bit)=1 fmem.bit 2 2+S Skip if (fmem.bit)=1 *4 (fmem.bit)=1 pmem.@L 2 2+S Skip if (pmem7-2+L3-2.bit(L1-0))=1 *5 (pmem.@L)=1 @H+mem.bit 2 2+S Skip if (H+mem3-0.bit)=1 *1 (@H+mem.bit)=1 mem.bit 2 2+S Skip if (mem.bit)=0 *3 (mem.bit)=0 fmem.bit 2 2+S Skip if (fmem.bit)=0 *4 (fmem.bit)=0 pmem.@L 2 2+S Skip if (pmem7-2+L3-2.bit(L1-0))=0 *5 (pmem.@L)=0 @H+mem.bit 2 2+S Skip if (H+mem3-0.bit)=0 *1 (@H+mem.bit)=0 Mnemonic INCS DECS Comparison instruction Carry flag manipulation instruction Memory bit manipulation instructions SKE CLR1 SKT SKF 44 Operand Operation Addressing area Skip if CY = 1 Data Sheet U10040EJ2V1DS Skip condition CY=1 PD754144, 754244 Instruction group Memory bit manipulation instructions SKTCLR AND1 OR1 XOR1 Branch instructions Notes 1. 2. Number of bytes Number of machine cycles fmem.bit 2 2+S Skip if (fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@L 2 2+S Skip if (pmem7-2+L3-2.bit(L1-0))=1 and clear *5 (pmem.@L)=1 @H+mem.bit 2 2+S Skip if (H+mem3-0.bit)=1 and clear *1 (@H+mem.bit)=1 CY, fmem.bit 2 2 CY CY (fmem.bit) *4 CY, pmem.@L 2 2 CY CY (pmem7-2+L3-2.bit(L1-0)) *5 CY, @H+mem.bit 2 2 CY CY (H+mem3-0.bit) *1 CY, fmem.bit 2 2 CY CY (fmem.bit) *4 CY, pmem.@L 2 2 CY CY (pmem7-2+L3-2.bit(L1-0)) *5 CY, @H+mem.bit 2 2 CY CY (H+mem3-0.bit) *1 CY, fmem.bit 2 2 CY CY v (fmem.bit) *4 CY, pmem.@L 2 2 CY CY v (pmem7-2+L3-2.bit(L1-0)) *5 CY, @H+mem.bit 2 2 CY CY v (H+mem3-0.bit) *1 addr - - PC11-0 addr Select appropriate instruction among BR !addr BRCB !caddr, and BR $addr according to the assembler being used. *6 addr1 - - PC11-0 addr Select appropriate instruction among BR !addr BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. *11 ! addr 3 3 PC11-0 addr *6 $addr 1 2 PC11-0 addr *7 $addr1 1 2 PC11-0 addr1 PCDE 2 3 PC11-0 PC11-8+DE PCXA 2 3 PC11-0 PC11-8+XA BCDE 2 3 PC11-0 BCDENote 2 *6 Mnemonic BRNote 1 Operand Operation Addressing area BCXA 2 3 PC11-0 BCXA *6 BRANote 1 !addr1 3 3 PC11-0 addr1 *11 BRCB !caddr 2 2 PC11-0 caddr11-0 *8 Note 2 Skip condition The above operations in the double boxes can be performed only in the Mk II mode. "0" must be set to B register. Data Sheet U10040EJ2V1DS 45 PD754144, 754244 Instruction group Subroutine stack control instructions Mnemonic Operand Number of bytes Number of machine cycles Operation Addressing area CALLANote !addr1 3 3 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 PC11-0 addr1, SP SP-6 *11 CALLNote !addr 3 3 (SP-3) MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) PC11-0 PC11-0 addr, SP SP-4 *6 4 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 PC11-0 addr, SP SP-6 2 (SP-3) MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) PC11-0 PC11-0 0+faddr, SP SP-4 3 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 PC11-0 0+faddr, SP SP-6 3 PC11-0 (SP) (SP+3) (SP+2) MBE, RBE, 0, 0 (SP+1), SP SP+4 CALLFNote !faddr RETNote 2 1 Skip condition *9 x, x, MBE, RBE (SP+4) 0, 0, 0, 0, (SP+1) PC11-0 (SP) (SP+3) (SP+2), SP SP+6 RETSNote 1 3+S MBE, RBE, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) SP SP+4 then skip unconditionally Unconditional 0, 0, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) x, x, MBE, RBE (SP+4) SP SP+6 then skip unconditionally RETINote 1 3 MBE, RBE, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 0, 0, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 PUSH POP Note rp 1 1 (SP-1) (SP-2) rp, SP SP-2 BS 2 2 (SP-1) MBS, (SP-2) RBS, SP SP-2 rp 1 1 rp (SP+1) (SP), SP SP+2 BS 2 2 MBS (SP+1), RBS (SP), SP SP+2 The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 46 Data Sheet U10040EJ2V1DS PD754144, 754244 Instruction group Interrupt control instructions Number of bytes Number of machine cycles 2 2 IME (IPS.3) 1 2 2 IExxx 1 2 2 IME (IPS.3) 0 IExxx 2 2 IExxx 0 A, PORTn 2 2 A PORTn (n = 3, 6, 7, 8) PORTn, A 2 2 PORTn A (n = 3, 6, 8) HALT 2 2 Set HALT Mode (PCC.2 1) STOP 2 2 Set STOP Mode (PCC.3 1) NOP 1 1 No Operation RBn 2 2 RBS n (n = 0-3) MBn 2 2 MBS n (n = 0, 4, 15) GETINotes 2, 3 taddr 1 3 * When TBR instruction PC11-0 (taddr) 3-0 + (taddr+1) Mnemonic Operand EI IExxx DI Input/output instructions INNote 1 Note 1 OUT CPU control instructions Special instructions SEL Addressing area Operation Skip condition *10 ---------------------------------- ------------- * When TCALL instruction (SP-4) (SP-1) (SP-2) PC11-0 (SP-3) MBE, RBE, 0, 0 PC11-0 (taddr) 3-0 + (taddr+1) SP SP-4 ---------------------------------- ------------- * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3 * When TBR instruction PC11-0 (taddr) 3-0 + (taddr+1) ------------------------------------- --- 4 Notes 1. *10 ------------- * When TCALL instruction (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 (SP-2) x, x, MBE, RBE PC11-0 (taddr) 3-0 + (taddr+1) SP SP-6 ------------------------------------- --- 3 Depending on the reference instruction * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. ------------- Depending on the reference instruction While the IN instruction and OUT instruction are being executed, MBE must be set to 0, or MBE must be set to 1 and MBS must be set to 15. 2. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. 3. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Data Sheet U10040EJ2V1DS 47 PD754144, 754244 13. ELECTRICAL SPECIFICATIONS 13.1 PD754144 Absolute Maximum Ratings (TA = 25C) Parameter Symbol Test Conditions Ratings Unit -0.3 to +7.0 V Power supply voltage V DD Input voltage VI -0.3 to VDD + 0.3 V Output voltage VO -0.3 to VDD + 0.3 V Output current, high IOH P30, P31, P33, P60 to P63, P80 -10 mA P32 -20 mA For all pins -30 mA Per pin 20 mA For all pins 90 mA TA -40 to +85 C Tstg -65 to +150 C Output current, low Operating ambient IOL Per pin temperature Storage temperature Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the products. Be sure to use the products within the ratings. Capacitance (TA = 25C, VDD = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz 15 pF Output capacitance COUT Unmeasured pins returned to 0 V 15 pF I/O capacitance CIO 15 pF 48 Data Sheet U10040EJ2V1DS PD754144, 754244 * PD754144 System Clock Oscillator Characteristics (TA = -40 to +85 C, VDD = 1.8 to 6.0 V) Resonator Recommended Constant RC Parameter Testing Conditions Oscillation oscillator CL1 CL2 frequency (fcc) MIN. TYP. 0.4 MAX. Unit 2.0 MHz Note * Note Only the oscillator characteristics are shown. For the instruction execution time and oscillation frequency characteristics, refer to AC Characteristics. Caution When using the oscillation circuit of the system clock, wire the portion enclosed in dotted lines in the figures as follows to avoid adverse influences on the wiring capacitance: * Keep the wire length as short as possible. * Do not cross other signal lines. * Do not route the wiring in the vicinity of lines though which a high fluctuating current flows. * Always keep the ground point of the capacitor of the oscillation circuit as the same potential as VSS. * Do not connect the power source pattern through which a high current flows. * Do not extract signals from the oscillation circuit. Data Sheet U10040EJ2V1DS 49 PD754144, 754244 * PD754144 DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 6.0 V) Parameter High-level output Symbol IOH Conditions Per pin MIN. TYP. P30, P31, P33, MAX. Unit -5 mA -15 mA Total of all pins -20 mA Per pin 15 mA Total of all pins 45 mA current P60 to P63, P80 P32, VDD = 3.0 V, -7 VOH = VDD - 2.0 V Low-level output IOL current High-level input VIH1 2.7 V VDD 6.0 V 0.7VDD VDD V 1.8 V VDD < 2.7 V 0.9VDD VDD V Ports 6 to 8, 2.7 V VDD 6.0 V 0.8VDD VDD V KRREN, RESET 1.8 V VDD < 2.7 V 0.9VDD VDD V Port 3 2.7 V VDD 6.0 V 0 0.3VDD V 1.8 V VDD < 2.7 V 0 0.1VDD V Ports 6 to 8, 2.7 V VDD 6.0 V 0 0.2VDD V KRREN, RESET 1.8 V VDD < 2.7 V 0 0.1VDD V Port 3 voltage VIH2 Low-level input VIL1 voltage VIL2 High-level VOH output voltage Low-level VOL VDD = 4.5 to 6.0 V, IOH = -1.0 mA VDD - 1.0 V VDD = 1.8 to 6.0 V, IOH = -100 A VDD - 0.5 V VDD = 4.5 to 6.0 V 2.0 V 0.4 V VDD = 1.8 to 6.0 V, IOH = 400 A 0.5 V ILIH VIN = VDD 3.0 A ILIL VIN = 0 V -3.0 A ILOH VOUT = VDD 3.0 A ILOL VOUT = 0 V -3.0 A On-chip pull-up RL1 VIN = 0 V resistance RL2 output voltage Port 3, IOL = 15 mA 0.6 Ports 6, 8, IOL = 1.6 mA High-level input leakage current Low-level input leakage current High-level output leakage current Low-level output leakage current Ports 3, 6, 8 50 100 200 k Port 7, RESET 50 100 200 k (mask option) 50 Data Sheet U10040EJ2V1DS PD754144, 754244 * PD754144 DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 6.0 V) Parameter Power supply current Symbol IDD1 Note 1 IDD2 IDD1 IDD2 IDD3 Conditions TYP. MAX. VDD = 5.0 V 10% Note 2 0.7 2.1 mA RC oscillation VDD = 3.0 V 10% Note 3 0.3 1.0 mA R = 22 k HALT VDD = 5.0 V 10% 0.5 1.8 mA C = 22 pF mode VDD = 3.0 V 10% 1.0-MHz MIN. 0.25 0.9 mA VDD = 5.0 V 10% Note 2 1.15 3.5 mA RC oscillation VDD = 3.0 V 10% Note 3 0.55 1.6 mA R = 5.1 k HALT VDD = 5.0 V 10% 0.95 2.8 mA C = 120 pF mode VDD = 3.0 V 10% 0.5 1.5 mA STOP VDD = 1.8 to 6.0 V 5 A 1 A 0.1 3 A 0.1 1 A 1.0-MHz mode TA = 25C VDD = 3.0 V 10% TA = -40 to +40C Notes 1. Unit The current flowing through the on-chip pull-up resistor, the current during EEPROM writing time, and the current when the program threshold port (PTH) is operating are not included. 2. When the device is operated in the high-speed mode by setting the processor clock control register (PCC) to 0011H. 3. When the device is operated in the low-speed mode by setting PCC to 0000H. Data Sheet U10040EJ2V1DS 51 PD754144, 754244 * PD754144 AC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 6.0 V) Parameter CPU clock cycle time Symbol Note1 Test Conditions tCY MIN. TYP. MAX. Unit 2.0 4.0 128 s (Minimum instruction execution time = 1 machine cycle) RC oscillation frequency Interrupt input high- and fCC tINTH, tINTL R = 22 k, VDD = 3.6 to 6.0 V 0.9 1.0 Note 2 1.2 MHz C = 22 pF VDD = 2.2 to 3.6 V 0.75 1.0 Note 2 1.15 MHz VDD = 1.8 to 3.6 V 0.5 1.0 Note 2 1.15 MHz VDD = 1.8 to 6.0 V 0.5 1.0 Note 2 1.2 MHz R = 5.1 k, VDD = 3.6 to 6.0 V 0.91 1.0 Note 2 1.1 MHz C = 120 pF VDD = 2.2 to 3.6 V 0.76 1.0 Note 2 1.05 MHz VDD = 1.8 to 3.6 V 0.51 1.0 Note 2 1.05 MHz VDD = 1.8 to 6.0 V 0.51 1.0 Note 2 1.1 MHz INT0 low-level width IM02 = 0 Note 3 s IM02 = 1 10 s 10 s 10 s KR4 to KR7 RESET low-level width Notes 1. tRSL The CPU clock () cycle time (minimum instruction execution time) is determined by the time constants of the connected tCY vs. VDD resistor (R) and capacitor (d) and the pro- (During system clock operation) cessor clock control register (PCC). The figure on the right shows the cycle time tCY 128 characteristics against the supply voltage VDD when the system clock is used. 2. This is the typical value when VDD = 3.6 V. 6 3. 2tCY or 128/fCC depending on the setting of 5 the interrupt mode register (IM0). 4 Cycle time tCY ( s) Operation guranteed range 3 2 1 0.5 52 0 1 Data Sheet U10040EJ2V1DS 1.8 2 3 4 5 Supply voltage VDD (V) 6 PD754144, 754244 * PD754144 EEPROM Characteristics (TA = -40 to +85 C, VDD = 1.8 to 6.0 V) Parameter EEPROM Symbol IEEW write current EEPROM Conditions 1.0 MHz, RC oscillation MIN. TYP. MAX. Unit VDD = 5.0 V 10% 4.0 12 mA VDD = 3.0 V 10% 2.0 6 mA 4.6 10.0 ms Note tEEW 1.0 MHz, RC oscillation 3.8 EEWT TA = -40 to +70C 100000 times/byte TA = -40 to +85C 80000 times/byte write time EEPROM write times Note Set EWTC 4 to 6 so as to be 18 x 28/fCC (4.6 ms: @ fCC = 1.0-MHz operation), considering the variation of the RC oscillation. Comparator Characteristics (TA = -40 to +85 C, VDD = 1.8 to 6.0 V) Parameter Symbol Comparison accuracy VACOMP Threshold voltage VTH PTH input voltage VIPTH AVREF input voltage VIAVREF Comparator circuit IDD5 Conditions MIN. MAX. Unit 100 mV Note Note V 0 VDD V 1.8 VDD V When bit 7 of PTHM is set to 1 TYP. 1 mA current consumption Note The threshold voltage becomes as follows by settings bits 0 to 3 of PTHM. VTH = VIAVREF x (n + 0.5)/16 (n = 0 to 15) Data Sheet U10040EJ2V1DS 53 PD754144, 754244 * PD754144 AC Timing Test Points VIH (MIN.) VIH (MIN.) VIL (MAX.) VIL (MAX.) VOH (MIN.) VOH (MIN.) VOL (MAX.) VOL (MAX.) Interrupt Input Timing tINTH tINTL INT0, KR4 to KR7 RESET Input Timing tRSL RESET Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Test Conditions Release signal set time tSREL Oscillation stabilization wait time 54 tWAIT MIN. TYP. MAX. Unit s 0 Release by RESET 56/fCC s Release by interrupt request 512/f CC s Data Sheet U10040EJ2V1DS PD754144, 754244 * PD754144 Data Retention Timing (on releasing STOP mode by RESET) Internal reset operation HALT mode Operation mode STOP mode Data retention mode VDD tSREL Execution of STOP instruction RESET tWAIT Data Retention Timing (Standby release signal: on releasing STOP mode by interrupt signal) HALT mode STOP mode Operation mode Data retention mode VDD tSREL Execution of STOP instruction Standby release signal (interrupt request) tWAIT Data Sheet U10040EJ2V1DS 55 PD754144, 754244 13.2 PD754244 Absolute Maximum Ratings (TA = 25C) Parameter Symbol Test Conditions Ratings Unit -0.3 to +7.0 V Power supply voltage V DD Input voltage VI -0.3 to VDD + 0.3 V Output voltage VO -0.3 to VDD + 0.3 V Output current, high IOH P30, P31, P33, P60 to P63, P80 -10 mA P32 -20 mA For all pins -30 mA Per pin 20 mA For all pins 90 mA Output current, low IOL Per pin Note Operating ambient temperature TA -40 to +85 C Storage temperature Tstg -65 to +150 C Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the products. Be sure to use the products within the ratings. Capacitance (TA = 25C, VDD = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz 15 pF Output capacitance COUT Unmeasured pins returned to 0 V 15 pF I/O capacitance CIO 15 pF 56 Data Sheet U10040EJ2V1DS PD754144, 754244 * PD754244 System Clock Oscillator Characteristics (TA = -40 to +85 C, VDD = 1.8 to 6.0 V) Resonator Recommended Constant Ceramic Parameter Testing Conditions Oscillation resonator X1 frequency (fX) X2 C1 C2 Crystal 1.0 After VDD reaches MIN. stabilization value of oscillation Note 5 frequency(f X) X1 X2 6.0 Notes2, 3, 4 MHz VDD = 4.5 to 6.0 V C2 X1 X2 frequency (fX) ms 10 ms 30 ms Note3 X1 input clock 6.0Notes2, 3, 4 MHz 4 1.0 Oscillation External Unit Note1 stabilization time C1 MAX. voltage range Oscillation resonator TYP. Note1 Oscillation time MIN. 1.0 6.0 Notes2, 3, 4 MHz Note1 X1 input high- and 83.3 500 ns low-level widths (tXH, t XL) Notes 1. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Characteristics. 2. If the oscillation frequency is 2.1 MHz < fX 4.19 MHz at 1.8 V VDD < 2.0 V, set the processor control register (PCC) to a value other than 0011. If the PCC is set to 0011, the rated machine cycle time of 1.9 s is not satisfied. 3. If the oscillation frequency is 4.19 MHz < fX 6.0 MHz at 1.8 V V DD < 2.0 V, set the processor control register (PCC) to a value other than 0011 or 0010. If the PCC is set to 0011 or 0010, the rated machine cycle time of 1.9 s is not satisfied. 4. If the oscillation frequency is 4.19 MHz < fX 6.0 MHz at 2.0 V V DD < 2.7 V, set the processor control register (PCC) to a value other than 0011. If the PCC is set to 0011, the rated machine cycle time of 0.95 s is not satisfied. 5. Oscillation stabilization time is a time required for oscillation to stabilize after application of VDD, or after the STOP mode has been released. Caution When using the oscillation circuit of the system clock, wire the portion enclosed in dotted lines in the figures as follows to avoid adverse influences on the wiring capacitance: * Keep the wire length as short as possible. * Do not cross other signal lines. * Do not route the wiring in the vicinity of lines though which a high fluctuating current flows. * Always keep the ground point of the capacitor of the oscillation circuit as the same potential as VSS. * Do not connect the power source pattern through which a high current flows. * Do not extract signals from the oscillation circuit. Data Sheet U10040EJ2V1DS 57 PD754144, 754244 * PD754244 Recommended Oscillator Constants Ceramic resonator (TA = -20 to +80C) Manufacturer Kyocera Part Number Frequency Recommended Circuit Oscillation Voltage Constant (pF) Range (VDD) Remark (MHz) C1 C2 MN. (V) MAX. (V) KBR-1000F/Y 1.0 100 100 1.8 6.0 KBR-2.0MS 2.0 47 47 KBR-4.19MSB 4.19 33 33 KBR-4.19MKC -- -- Model with capacitor PBRC4.19A 33 33 -- PBRC4.19B -- -- Model with capacitor 33 33 -- KBR-6.0MKC -- -- Model with capacitor PBRC6.00A 33 33 -- PBRC6.00B -- -- Model with capacitor KBR-6.0MSB 6.0 -- Ceramic resonator (TA = -40 to +80C) Manufacturer Part Number Note Murata Mfg. CSB1000J Co., Ltd. CSA2.00MG040 Frequency Oscillation Voltage Constant (pF) Range (VDD) (MHz) C1 C2 MIN. (V) MAX. (V) 1.0 100 100 2.0 6.0 2.0 CST2.00MG040 -- 30 30 CST4.19MGW -- -- CSA4.19MGU 30 30 CST4.19MGWU -- -- 30 30 CST6.00MGW -- -- CSA6.00MGU 30 30 CST6.00MGWU -- -- CSA6.00MG 4.19 6.0 CCR1000K2 1.0 100 100 CCR4.19MC3 4.19 -- -- FCR4.19MC5 CCR6.0MC3 6.0 FCR6.0MC5 58 Remark Rd = 2.2 k -- -- CSA4.19MG TDK Recommended Circuit Data Sheet U10040EJ2V1DS Model with capacitor 1.9 -- Model with capacitor 1.8 -- Model with capacitor 2.5 -- Model with capacitor 1.8 -- Model with capacitor 2.0 -- Model with capacitor PD754144, 754244 Note When using the CSB1000J (1.0 MHz) made by Murata Mfg. Co., Ltd. as a ceramic resonator, a limiting resistor (Rd = 2.2 k) is necessary (refer to the figure below). This resistor is not necessary when using the other recommended resonators. X1 X2 CSB1000J Rd * * C2 C1 * Caution The oscillator constants and oscillation voltage range indicate conditions for stable oscillation, but do not guarantee oscillation frequency accuracy. If oscillation frequency accuracy is required for actual circuits, it is necessary to adjust the oscillation frequency of the oscillator in the actual circuit. Please contact directly the manufacturer of the resonator to be used. Data Sheet U10040EJ2V1DS 59 PD754144, 754244 * PD754244 DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 6.0 V) Parameter High-level output Symbol IOH Conditions Per pin MIN. TYP. P30, P31, P33, MAX. Unit -5 mA -15 mA Total of all pins -20 mA Per pin 15 mA Total of all pins 45 mA current P60 to P63, P80 P32, VDD = 3.0 V, -7 VOH = VDD - 2.0 V Low-level output IOL current High-level input VIH1 2.7 V VDD 6.0 V 0.7VDD VDD V 1.8 V VDD < 2.7 V 0.9VDD VDD V Ports 6 to 8, 2.7 V VDD 6.0 V 0.8VDD VDD V KRREN, RESET 1.8 V VDD < 2.7 V 0.9VDD VDD V VDD - 0.1 VDD V 2.7 V VDD 6.0 V 0 0.3VDD V 1.8 V VDD < 2.7 V 0 0.1VDD V Ports 6 to 8, 2.7 V VDD 6.0 V 0 0.2VDD V KRREN, RESET 1.8 V VDD < 2.7 V 0 0.1VDD V 0 0.1 V Port 3 voltage VIH2 Low-level input VIH3 X1 VIL1 Port 3 voltage VIL2 High-level VIH3 X1 VOH VDD = 4.5 to 6.0 V, IOH = -1.0 mA VDD - 1.0 V VDD = 1.8 to 6.0 V, IOH = -100 A VDD - 0.5 V output voltage Low-level VOL VDD = 4.5 to 6.0 V 2.0 V 0.4 V VDD = 1.8 to 6.0 V, IOH = 400 A 0.5 V VIN = VDD Pins other than X1 3.0 A X1 20 A Pins other than X1 -3.0 A X1 -20 A output voltage Port 3, IOL = 15 mA 0.6 Ports 6, 8, IOL = 1.6 mA High-level input ILIH1 leakage current ILIH2 Low-level input ILIL1 leakage current ILIH2 High-level output ILOH VOUT = VDD 3.0 A ILOL VOUT = 0 V -3.0 A On-chip pull-up RL1 VIN = 0 V resistance RL2 VIN = 0 V leakage current Low-level output leakage current Port 3, 6, 8 50 100 200 k Port 7, RESET 50 100 200 k (mask option) 60 Data Sheet U10040EJ2V1DS PD754144, 754244 * PD754244 DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 6.0 V) Parameter Power supply current Symbol IDD1 Note 1 IDD2 IDD3 Conditions TYP. MAX. VDD = 5.0 V 10% Note 2 1.5 5.0 mA crystal VDD = 3.0 V 10% Note 3 0.23 1.0 mA oscillation HALT VDD = 5.0 V 10% 0.64 3.0 mA C1 = C2 = 22 pF mode VDD = 3.0 V 10% 0.20 0.9 mA 5 A 1 A 0.1 3 A 0.1 1 A 4.19-MHz X1 = 0 V MIN. VDD = 1.8 to 6.0 V STOP mode TA = 25C VDD = 3.0 V 10% TA = -40 to +40C Notes 1. Unit The current flowing through the on-chip pull-up resistor, the current during EEPROM writing time, and the current during the program threshold port (PTH) operation are not included. 2. When the device is operated in the high-speed mode by setting the processor clock control register (PCC) to 0011H 3. When the device is operated in the low-speed mode by setting PCC to 0000H Data Sheet U10040EJ2V1DS 61 PD754144, 754244 * PD754244 AC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 6.0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit V DD = 1.8 to 2.0 V 1.9 64.0 s (Minimum instruction execution VDD = 2.0 to 2.7 V 0.95 64.0 s time = 1 machine cycle) V DD = 2.7 to 6.0 V 0.67 64.0 s CPU clock cycle time Note 1 Interrupt input high- and tCY tINTH, tINTL INT0 low-level width IM02 = 0 Note 2 s IM02 = 1 10 s 10 s 10 s KR4 to KR7 RESET low-level width Notes 1. tRSL The CPU clock () cycle time (minimum instruction execution time) is determined by the oscillation frequency of the contCY vs. VDD nected resonator (or external clock) and (During system clock operation) the processor clock control register (PCC). The figure on the right shows the cycle 64 60 time tCY characteristics against the supply voltage VDD when the system clock is used. 2. 6 2tCY or 128/f X depending on the setting of 5 the interrupt mode register (IM0). Cycle time tCY ( s) Operation guranteed range 4 3 2 1.9 1 0.95 0.67 0.5 62 0 1 Data Sheet U10040EJ2V1DS 1.8 2 2.7 3 4 5 Supply voltage VDD (V) 6 PD754144, 754244 * PD754244 EEPROM Characteristics (TA = -40 to +85 C, VDD = 1.8 to 6.0 V) Parameter EEPROM Symbol IEEW write current EEPROM Conditions MIN. TYP. MAX. Unit 4.19 MHz, VDD = 5.0 V 10% 4.5 15 mA crystal oscillation VDD = 3.0 V 10% 2.0 6 mA 10.0 ms 3.8 tEEW write time EEPROM EEWT write times TA = -40 to +70C 100000 times/byte TA = -40 to +85C 80000 times/byte Comparator Characteristics (TA = -40 to +85 C, VDD = 1.8 to 6.0 V) Parameter Symbol Comparison accuracy VACOMP Threshold voltage VTH PTH input voltage VIPTH AVREF input voltage VIAVREF Comparator circuit IDD5 Conditions MIN. MAX. Unit 100 mV Note Note V 0 VDD V 1.8 VDD V When bit 7 of PTHM is set to 1 TYP. 1 mA current consumption Note The threshold voltage becomes as follows by settings bits 0 to 3 of PTHM. VTH = VIAVREF x (n + 0.5)/16 (n = 0 to 15) Data Sheet U10040EJ2V1DS 63 PD754144, 754244 * PD754244 AC Timing Test Points (Excluding X1 Input) VIH (MIN.) VIH (MIN.) VIL (MAX.) VIL (MAX.) VOH (MIN.) VOH (MIN.) VOL (MAX.) VOL (MAX.) Clock Timing 1/fX tXL tXH VDD - 0.1 V X1 input 0.1 V 64 Data Sheet U10040EJ2V1DS PD754144, 754244 * PD754244 Interrupt Input Timing tINTL tINTH INT0, KR4 to KR7 RESET Input Timing tRSL RESET Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (TA = -40 to +85 C) Parameter Symbol Test Conditions Release signal set time tSREL Oscillation stabilization wait time Notes 1. Note 1 tWAIT MIN. TYP. MAX. Unit s 0 Release by RESET Note 2 ms Release by interrupt request Note 3 ms The oscillation stabilization wait time is the time during which the CPU operation is stopped to avoid unstable operation at oscillation start. 2. 2 17/fx and 2 15/fx can be selected with mask option. 3. Depends on setting of basic interval timer mode register (BTM) (see table below). BTM3 BTM2 BTM1 BTM0 Wait Time When fX = 4.19 MHz - - - - 0 0 1 1 0 1 0 1 0 220/fX 1 217/fX 1 215/fX 1 213/fX When fX = 6.0 MHz (Approx. 250 ms) 220/fX (Approx. 175 ms) (Approx. 31.3 ms) 217/fX (Approx. 21.8 ms) (Approx. 7.81 ms) 215/fX (Approx. 5.46 ms) (Approx. 1.95 ms) 213/fX (Approx. 1.37 ms) Data Sheet U10040EJ2V1DS 65 PD754144, 754244 Data Retention Timing (on releasing STOP mode by RESET) Internal reset operation HALT mode Operation mode STOP mode Data retention mode VDD tSREL Execution of STOP instruction RESET tWAIT Data Retention Timing (Standby release signal: on releasing STOP mode by interrupt signal) HALT mode STOP mode Operation mode Data retention mode VDD tSREL Execution of STOP instruction Standby release signal (interrupt request) tWAIT 66 Data Sheet U10040EJ2V1DS PD754144, 754244 14. CHARACTERISTICS CURVES (REFERENCE VALUES) 14.1 PD754144 IDD vs. VDD (RC Oscillation, R = 22 k, C = 22 pF) (TA = 25C) 10 5.0 1.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 0.5 Power Supply Current IDD (mA) System clock HALT mode 0.1 0.05 0.01 0.005 CL1 CL2 22 k 22 pF 0.001 0 1 2 3 4 5 6 7 8 Power Supply Voltage V DD (V) Data Sheet U10040EJ2V1DS 67 PD754144, 754244 * PD754144 IDD vs. VDD (RC Oscillation, R = 5.1 k, C = 120 pF) (TA = 25C) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 and 1.0 System clock HALT mode Power Supply Current IDD (mA) 0.5 0.1 0.05 0.01 0.005 CL1 CL2 5.1 k 120 pF 0.001 0 1 2 3 4 5 Power Supply Voltage V DD (V) 68 Data Sheet U10040EJ2V1DS 6 7 8 PD754144, 754244 14.2 PD754244 IDD vs. VDD (System Clock: 6.0-MHz Crystal Resonator) (TA = 25C) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 1.0 System clock HALT mode Power Supply Current IDD (mA) 0.5 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 6.0 MHz 22 pF 0.001 0 1 2 3 4 5 22 pF 6 7 8 Power Supply Voltage V DD (V) Data Sheet U10040EJ2V1DS 69 PD754144, 754244 * PD754244 IDD vs. VDD (System Clock: 4.19-MHz Crystal Resonator) (TA = 25C) 10 5.0 PCC = 0011 PCC = 0010 1.0 PCC = 0001 PCC = 0000 System clock HALT mode Power Supply Current IDD (mA) 0.5 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 4.19 MHz 22 pF 0.001 0 1 2 3 4 5 Power Supply Voltage V DD (V) 70 Data Sheet U10040EJ2V1DS 22 pF 6 7 8 PD754144, 754244 * PD754244 IDD vs. VDD (System Clock: 2.0-MHz Crystal Resonator) (TA = 25C) 10 5.0 PCC = 0011 1.0 PCC = 0010 PCC = 0001 PCC = 0000 System clock HALT mode Power Supply Current IDD (mA) 0.5 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 2.0 MHz 47 pF 0.001 0 1 2 3 4 5 47 pF 6 7 8 Power Supply Voltage V DD (V) Data Sheet U10040EJ2V1DS 71 PD754144, 754244 15. RC OSCILLATION FREQUENCY CHARACTERISTICS EXAMPLES (REFERENCE VALUES) fCC vs. VDD (RC Oscillation, R = 22 k, C = 22 pF) (TA = -40C) System Clock Frequency fCC (MHz) 2.0 CL1 CL2 22 k 22 pF 1.0 Sample C Sample B 0.5 Sample A 0 1 2 3 4 5 6 7 8 Power Supply Voltage V DD (V) (TA = 25C) System Clock Frequency fCC (MHz) 2.0 CL1 CL2 22 k 22 pF 1.0 Sample C Sample B Sample A 0.5 0 1 2 3 4 5 6 7 8 Power Supply Voltage V DD (V) (TA = 85C) System Clock Frequency fCC (MHz) 2.0 CL1 CL2 22 k 22 pF 1.0 Sample C Sample B Sample A 0.5 0 1 2 3 4 5 Power Supply Voltage V DD (V) 72 Data Sheet U10040EJ2V1DS 6 7 8 PD754144, 754244 fCC vs. TA (RC Oscillation, R = 22 k, C = 22 pF) (Sample A) System Clock Frequency fCC (MHz) 2.0 CL1 CL2 22 k 22 pF VDD = 5.0 V VDD = 6.0 V VDD = 3.0 V 1.0 VDD = 2.2 V VDD = 1.8 V 0.5 -60 -40 -20 0 +20 +40 +60 +80 +100 Operating Ambient Temperature TA (C) (Sample B) System Clock Frequency fCC (MHz) 2.0 CL1 CL2 22 k 22 pF VDD = 5.0 V VDD = 6.0 V VDD = 3.0 V VDD = 2.2 V 1.0 VDD = 1.8 V 0.5 -60 -40 -20 0 +20 +40 +60 +80 +100 Operating Ambient Temperature TA ( C) (Sample C) System Clock Frequency fCC (MHz) 2.0 CL1 CL2 22 k 22 pF VDD = 5.0 V VDD = 6.0 V VDD = 3.0 V VDD = 2.2 V VDD = 1.8 V 1.0 0.5 -60 -40 -20 0 +20 +40 +60 +80 +100 Operating Ambient Temperature TA (C) Data Sheet U10040EJ2V1DS 73 PD754144, 754244 fCC vs. VDD (RC Oscillation, R = 5.1 k , C = 120 pF) (TA = -40C) System Clock Frequency fCC (MHz) 2.0 CL1 CL2 5.1 k 120 pF 1.0 Sample C Sample B 0.5 Sample A 0 1 2 3 4 5 6 7 8 Power Supply Voltage V DD (V) (TA = 25C) System Clock Frequency fCC (MHz) 2.0 CL1 CL2 5.1 k 120 pF 1.0 Sample C Sample B Sample A 0.5 0 1 2 3 4 5 6 7 8 Power Supply Voltage V DD (V) (TA = 85C) System Clock Frequency fCC (MHz) 2.0 CL1 CL2 5.1 k 120 pF 1.0 Sample C Sample B Sample A 0.5 0 1 2 3 4 5 Power Supply Voltage V DD (V) 74 Data Sheet U10040EJ2V1DS 6 7 8 PD754144, 754244 fCC vs. TA (RC Oscillation, R = 5.1 k, C = 120 pF) (Sample A) System Clock Frequency fCC (MHz) 2.0 CL1 CL2 5.1 k 120 pF VDD = 5.0 V VDD = 6.0 V VDD = 3.0 V 1.0 VDD = 2.2 V VDD = 1.8 V 0.5 -60 -40 -20 0 +20 +40 +60 +80 +100 Operating Ambient Temperature TA (C) (Sample B) System Clock Frequency fCC (MHz) 2.0 CL1 CL2 5.1 k 120 pF VDD = 5.0 V and VDD = 6.0 V VDD = 3.0 V VDD = 2.2 V VDD = 1.8 V 1.0 0.5 -60 -40 -20 0 +20 +40 +60 +80 +100 Operating Ambient Temperature TA (C) (Sample C) System Clock Frequency fCC (MHz) 2.0 CL1 CL2 5.1 k 120 pF VDD = 5.0 V VDD = 6.0 V VDD = 3.0 V VDD = 2.2 V VDD = 1.8 V 1.0 0.5 -60 -40 -20 0 +20 +40 +60 +80 +100 Operating Ambient Temperature TA (C) Data Sheet U10040EJ2V1DS 75 PD754144, 754244 16. PACKAGE DRAWINGS 20-pin Plastic SOP (300 mils) 20 11 detail of lead end P 1 10 A H I G J L C D M M B K N E F NOTE ITEM Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. MILLIMETERS INCHES A 12.70.3 0.5000.012 B 0.78 MAX. 0.031 MAX. C 1.27 (T.P.) 0.050 (T.P.) D 0.42 +0.08 -0.07 0.017 +0.003 -0.004 E 0.10.1 0.0040.004 F 1.8 MAX. 0.071 MAX. G 1.550.05 0.0610.002 H 7.70.3 0.3030.012 I 5.60.2 0.220 +0.009 -0.008 J 1.1 0.043 K 0.22 +0.08 -0.07 0.009 +0.003 -0.004 L 0.60.2 0.024 +0.008 -0.009 M 0.12 0.005 N 0.10 0.004 P 3 +7 -3 3 +7 -3 P20GM-50-300B, C-5 76 Data Sheet U10040EJ2V1DS PD754144, 754244 20-pin Plastic shrink SOP (300 mils) 20 11 detail of lead end P 1 10 A H F J I G S L E N S K C D M M B NOTE ITEM 1. Controlling dimension millimeter. 2. Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. MILLIMETERS INCHES A 6.70.3 0.264 +0.012 -0.013 B 0.575 MAX. 0.023 MAX. C 0.65 (T.P.) 0.026 (T.P.) D 0.32 +0.08 -0.07 0.013 +0.003 -0.004 E 0.125 0.075 0.005 0.003 F 2.0 MAX. 0.079 MAX. G 1.70.1 0.067 +0.004 -0.005 H I 8.1 0.3 6.1 0.2 0.240 0.008 J 1.0 0.2 0.039 +0.009 -0.008 K 0.15 +0.10 -0.05 0.006 +0.004 -0.002 L 0.5 0.2 0.020 +0.008 -0.009 M 0.12 0.005 N 0.10 0.004 P 3 +7 -3 3 +7 -3 0.319 0.012 P20GM-65-300B-3 Data Sheet U10040EJ2V1DS 77 PD754144, 754244 17. RECOMMENDED SOLDERING CONDITIONS The PD754144 and PD754244 should be soldered and mounted under the following recommended conditions. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 17-1. Surface Mounting Type Soldering Conditions (1/3) (1) PD754244GS-xxx-GJG: 20-pin plastic shrink SOP (300 mil, 0.65 mm pitch) Soldering Method Infrared reflow VPS Wave soldering Partial heating Caution Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once Preheating temperature: 120C max. (package surface temperature) Recommended Condition Symbol IR35-00-2 VP15-00-2 WS60-00-1 Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Do not use different soldering methods together (except for partial heating). Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative. (2) PD754144GS-xxx-GJG: 20-pin plastic shrink SOP (300 mil, 0.65 mm pitch) Soldering Method Infrared reflow VPS Wave soldering Partial heating Caution Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Three times or less Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once Preheating temperature: 120C max. (package surface temperature) Recommended Condition Symbol IR35-00-3 VP15-00-3 WS60-00-1 Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Do not use different soldering methods together (except for partial heating). Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative. 78 Data Sheet U10040EJ2V1DS PD754144, 754244 Table 17-1. Surface Mounting Type Soldering Conditions (2/3) (3) PD754144GS-xxx-BA5: 20-pin plastic SOP (300 mil, 1.27 mm pitch) PD754244GS-xxx-BA5: 20-pin plastic SOP (300 mil, 1.27 mm pitch) Soldering Method Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 to 72 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 to 72 hours) Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once Preheating temperature: 120C max. (package surface temperature) Exposure limit: 7 daysNote (after that, prebake at 125C for 10 to 72 hours) VPS Wave soldering Partial heating Note Soldering Conditions Recommended Condition Symbol IR35-107-2 VP15-107-2 WS60-107-1 Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative. (4) PD754244GS-xxx-BA5-A: 20-pin plastic SOP (300 mil, 1.27 mm pitch) Soldering Method Infrared reflow Soldering Conditions Wave soldering Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Count: Three times or less, Exposure limit: 3 daysNote (after that, prebake at 125C for 10 to 72 hours) For details, contact an NEC Electronics sales representative. Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) Note Recommended Condition Symbol IR60-103-3 - - After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remarks 1. Products with "-A" at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative. Data Sheet U10040EJ2V1DS 79 PD754144, 754244 Table 17-1. Surface Mounting Type Soldering Conditions (3/3) (5) PD754144GS-xxx-BA5-A: 20-pin plastic SOP (300 mil, 1.27 mm pitch) PD754144GS-xxx-GJG-A: 20-pin plastic shrink SOP (300 mil, 0.65 mm pitch) PD754144GS-xxx-GJG-A: 20-pin plastic shrink SOP (300 mil, 0.65 mm pitch) Undefined Remark 80 Products with -A at the end of the part number are lead-free products. Data Sheet U10040EJ2V1DS PD754144, 754244 APPENDIX A. COMPARISON OF FUNCTIONS AMONG PD754144, 754244, AND 75F4264 PD754144 Item Program memory Data Static RAM memory PD754244 PD75F4264 Mask ROM Flash memory 0000H to 0FFFH 0000H to 0FFFH (4096 x 8 bits) (4096 x 8 bits) Note 000H to 07FH (128 x 4 bits) EEPROM 400H to 41FH 400H to 43FH (16 x 8 bits) (32 x 8 bits) CPU 75XL CPU General-purpose register (4 bits x 8 or 8 bits x 4) x 4 banks Instruction execution time * 4, 8, 16, 64 s * 0.67, 1.33, 2.67, 10.7 s (@ fCC = 1.0-MHz (@ fX = 6.0-MHz operation) operation) * 0.95, 1.91, 3.81, 15.3 s (@ fX = 4.19-MHz operation) I/O port CMOS input 4 (on-chip pull-up resistor can be connected by mask option) CMOS I/O 9 (on-chip pull-up resistor connection can be specified by means of software) Total 13 System clock oscillator RC oscillator Ceramic/crystal oscillator (resistor and capacitor are connected externally) Start-up time after reset 17 56/fCC 15 15 2 /fX, 2 /fX (can be 2 /fX selected by mask option) 9 Standby mode release time 2 /fCC Timer 4 channels 20 17 15 13 2 /fX, 2 /fX, 2 /fX, 2 /fX (can be selected by the setting of BTM) * 8-bit timer counter: 3 channels (can be used as 16-bit timer counter) * Basic interval timer/watchdog timer: 1 channel A/D converter None * 8-bit resolution x 2 channels (successive approximation, hardware control) * Can be operated from VDD = 1.8 V Programmable threshold port 2 channels Vectored interrupt External: 1, internal: 5 Test input External: 1 (key return reset function available) Power supply voltage VDD = 1.8 to 6.0 V Operating ambient temperature TA = -40 to +85C Package * 20-pin plastic SOP (300 mil, 1.27-mm pitch) * 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Note * 20-pin plastic SOP (300 mil, 1.27-mm pitch) Under development Data Sheet U10040EJ2V1DS 81 PD754144, 754244 APPENDIX B DEVELOPMENT TOOLS The following development tools are provided for system development using the PD754244. In the 75XL series, the relocatable assembler which is common to the series is used in combination with the device file of each product. Language processor RA75X relocatable assembler Part number (product name) Host machine OS PC-9800 series Distribution media MS-DOSTM 3.5-inch 2HD S5A13RA75X Ver. 3.30 to 5-inch 2HD S5A10RA75X 3.5-inch 2HC S7B13RA75X 5-inch 2HC S7B10RA75X Ver. 6.2Note IBM PC/ATTM and compatible machines Device file Refer to "OS for IBM PC" Part number (product name) Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Distribution media 3.5-inch 2HD S5A13DF754244 5-inch 2HD S5A10DF754244 3.5-inch 2HC S7B13DF754244 5-inch 2HC S7B10DF754244 Ver. 6,2Note IBM PC/AT and compatible machines Note Refer to "OS for IBM PC" Ver.5.00 or later have the task swap function, but it cannot be used for this software. Remark Operation of the assembler and device file are guaranteed only on the above host machine and OSs. 82 Data Sheet U10040EJ2V1DS PD754144, 754244 Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the PD754244. The system configurations are described as follows. Hardware IE-75000-R Note 1 IE-75001-R In-circuit emulator for debugging the hardware and software when developing application systems that use the 75X series and 75XL series. When developing the PD754244, the emulation board IE-75300-R-EM and emulation probe EP-754144GS-R which are sold separately must be used with the IE-75001-R. By connecting the host machine, efficient debugging can be made. IE-75300-R-EM Emulation board for evaluating the application systems that use the PD754244. It must be used with the IE-75000-R or IE-75001-R. EP-754144GS-R Emulation probe for the PD754244GS. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the flexible boards EV-9500GS-20 (supporting 20-pin plastic shrink SOPs) and EV-9501GS-20 (supporting 20-pin plastic SOPs) which facillitate connection to a target system. EV-9500GS-20 EV-950IGS-20 Software In-circuit emulator for debugging the hardware and software when developing application systems that use the 75X series and 75XL series. When developing the PD754244, the emulation board IE-75300-R-EM and emulation probe EP-754144GS-R that are sold separately must be used with the IE-75000-R. By connecting with the host machine, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. IE control program Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix I/F and controls the above hardware on a host machine. Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Distribution media Part No. (product name) 3.5-inch 2HD S5A13IE75X 5-inch 2HD S5A10IE75X 3.5-inch 2HC S7B13IE75X 5-inch 2HC S7B10IE75X Ver. 6.2Note 2 IBM PC/AT and its compatible machine Notes 1. 2. Refer to "OS for IBM PC" Maintenance parts Ver.5.00 or later have the task swap function, but it cannot be used for this software. Remark Operation of the IE control program is guaranteed only on the above host machines and OSs. Data Sheet U10040EJ2V1DS 83 PD754144, 754244 OS for IBM PC The following IBM PC OS's are supported. OS Version PC DOSTM Ver. 5.02 to Ver. 6.3 J6.1/VNote to J6.3/VNote MS-DOS Ver. 5.0 to Ver. 6.22 Note Note 5.0/V to J6.2/V IBM DOSTM J5.02/VNote Note Supported only English mode. Caution Ver. 5.0 and later have the task swap function, but it cannot be used for operating systems above. 84 Data Sheet U10040EJ2V1DS PD754144, 754244 APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device related documents Document Number Document Name Japanese English PD754144, 754244 Data Sheet U10040J This document PD754144, 754244 User's Manual U10676J U10676E 75XL Series Selection Guide U10453J U10453E Development tool related documents Document Number Document Name Japanese Hardware Software English IE-75000-R/IE-75001-R User's Manual EEU-846 EEU-1416 IE-75300-R-EM User's Manual U11354J U11354E EP-754144GS-R User's Manual U10695J U10695E Operation EEU-731 EEU-1346 Language EEU-730 EEU-1363 RA75X Assembler Package User's Manual Other related documents Document Number Document Name Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Static Electricity Discharge (ESD) Test MEM-539 Guide to Quality Assurance for Semiconductor Devices C11893J Microcomputer Related Product Guide - Other Manufacturers U11416J - MEI-1202 - Caution These documents are subject to change without notice. Be sure to read the latest documents. Data Sheet U10040EJ2V1DS 85 PD754144, 754244 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. 86 Data Sheet U10040EJ2V1DS PD754144, 754244 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) NEC Electronics (Europe) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Duesseldorf, Germany Tel: 0211-65030 Hong Kong Tel: 2886-9318 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-265 40 10 * Tyskland Filial NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai Ltd. Shanghai, P.R. China Tel: 021-5888-5400 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Taeby, Sweden Tel: 08-63 87 200 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J05.6 Data Sheet U10040EJ2V1DS 87 PD754144, 754244 EEPROM is a trademark of NEC Electronics Corporation. MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of August, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1