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are trademarks of their respective owners. http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA
bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restric-
tion except One Year license where time of
use is limited to 12 months.
● Single Design license for
○ VHDL, Verilog source code called HDL
Source
○ Encrypted, or plain text EDIF called Netlist
● One Year license for
○ Encrypted N et lis t only
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
○ HDL Source to Netlist
○ Single Design to Unlimited Designs
SYMBOL
datai(31:0) datao(31:0)
en
rst
clk
ofo
ufo
ifo
PINS DESCRIPTION
PIN TYPE DESCRIPTION
clk Input Global system clock
rst Input Global system reset
en Input Enable computing
datai[31:0] Input Data bus input
datao[31:0] Output Data bus output
ofo Output Overflow flag
ufo Output Underflow flag
ifo Output Invalid flag
BLOCK DIAGRAM
datai(31:0) datao(31:0)
en
rst
clk
ofo
ufo
ifo
rgument
Checker Main FP
Pipelined Unit
Result
Composer
Arguments Checker - performs input data
analyze against IEEE-754 number standard
compliance. The appropriate numbers and
information about the input data classes are
given as the results to Main FP Pipelined
Unit.
Main FP Pipelined Unit - performs floating
point square root function. Gives the complex
information about the results to Result Com-
poser module.
Result Composer - performs result rounding
function, data alignment to IEEE-754 stan-
dard, and the final flags setting.
PERFORMANCE
The following table gives a survey about the
Core area and performance in the LATTICE®
devices after Place & Route (all key features
have been included):
Device Speed
grade LUTs/PFUs Fmax
ORCA 4 -3 792/143 37 MHz
ispXPGA -4 838/280 46 MHz
Core performance in LATTICE® devices