1
Semiconductor
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
CD4051B, CD4052B, CD4053B
CMOS Analog Multiplex ers/Dem ultiple x ers
with Logic Level Conversion
The CD4051B, CD4052B , and CD4053B analog multiple xers
are digitally-controlled analog switches having low ON
impedance and very low OFF leakage current. Control of
analog signals up to 20VP-P can be achieved by digital
signal amplitudes of 4.5V to 20V (if VDD-VSS = 3V, a
VDD-VEE of up to 13V can be controlled; for VDD-VDD
level differences above 13V, a VDD-VDD of at least 4.5V is
required). For example, if VDD = +4.5V, VDD = 0V, and
VDD = -13.5V, analog signals from -13.5V to +4.5V can be
controlled by digital inputs of 0V to 5V. These multiplexer
circuits dissipate extremely low quiescent power over the
full VDD-VDD and VDD-VDD supply-voltage ranges,
independent of the logic state of the control signals. When
a logic “1” is present at the inhibit input terminal, all
channels are off.
The CD4051B is a single 8-Channel multiplexer having three
binary control inputs, A, B, and C, and an inhibit input. The
three binary signals select 1 of 8 channels to be turned on,
and connect one of the 8 inputs to the output.
The CD4052B is a differential 4-Channel multiplexer having
two binary control inputs, A and B, and an inhibit input. The
two binary input signals select 1 of 4 pairs of channels to be
turned on and connect the analog inputs to the outputs.
The CD4053B is a triple 2-Channel multiplexer having three
separate digital control inputs, A, B, and C, and an inhibit
input. Each control input selects one of a pair of channels
which are connected in a single-pole, double-throw
configuration.
When these devices are used as demultiplexers, the
“CHANNEL IN/OUT” terminals are the outputs and the
“COMMON OUT/IN” terminals are the inputs.
Features
• Wide Range of Digital and Analog Signal Levels
- Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V
- Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20VP-P
• Low ON Resistance, 125Ω(Typ) Over 15VP-P Signal Input
Range for VDD-VEE = 18V
• High OFF Resistance, Channel Leakage of ±100pA (Typ)
at VDD-VEE = 18V
• Logic-Level Conversion for Digital Addressing Signals of
3V to 20V (VDD-VSS = 3V to 20V) to Switch Analog
Signals to 20VP-P (VDD-VEE = 20V)
• Matched Switch Characteristics, rON = 5Ω (Typ) for
VDD-VEE = 15V
• Very Low Quiescent Power Dissipation Under All Digital-
Control Input and Supply Conditions, 0.2µW (Typ) at
VDD-VSS = VDD-VEE = 10V
• Binary Address Decoding on Chip
• 5V, 10V and 15V Parametric Ratings
• 10% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package
Temperature Range, 100nA at 18V and 25oC
• Break-Before-Make Switching Eliminates Channel
Overlap
Applications
• Analog and Digital Multiplexing and Demultiplexing
• A/D and D/A Conversion
• Signal Gating
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
CD4051BF, CD4052BF,
CD4053BF -55 to 125 16 Ld CERDIP F16.3
CD4051BE, CD4052BE,
CD4053BE -55 to 125 16 Ld PDIP E16.3
CD4051BM, CD4052BM,
CD4053BM -55 to 125 16 Ld SOIC M16.15
August 1998 File Number 902.2
2
Pinouts
CD4051B (PDIP, CERDIP, SOIC)
TOP VIEW CD4052B (PDIP, CERDIP)
TOP VIEW
CD4053B (PDIP, CERDIP)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
4
6
COM OUT/IN
7
5
INH
VSS
VEE
VDD
1
0
3
A
B
C
2
CHANNELS IN/OUT
CHANNELS
IN/OUT
CHANNELS
IN/OUT
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
0
2
COMMON “Y” OUT/IN
3
1
INH
VSS
VEE
VDD
1
COMMON “X” OUT/IN
0
3
A
B
2
Y CHANNELS
IN/OUT
Y CHANNELS
IN/OUT
X CHANNELS
IN/OUT
X CHANNELS
IN/OUT
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
by
bx
cy
OUT/IN CX OR CY
IN/OUT CX
INH
VSS
VEE
VDD
OUT/IN ax OR ay
ay
ax
A
B
C
OUT/IN bx OR by
IN/OUT
IN/OUT
Functional Block Diagrams
CD4051B
11
10
9
6
A †
B †
C †
INH †
134 2 5 1 12 15 14
TG
TG
TG
TG
TG
TG
TG
TG
3
COMMON
OUT/IN
01234567
BINARY
TO
1 OF 8
DECODER
WITH
INHIBIT
LOGIC
LEVEL
CONVERSION
8 7
VSS VEE
16 VDD
CHANNEL IN/OUT
CD4051B, CD4052B, CD4053B
3
CD4052B
CD4053B
Functional Block Diagrams
(Continued)
1211 15 14
0123
3210
X CHANNELS IN/OUT
Y CHANNELS IN/OUT
BINARY
TO
1 OF 4
DECODER
WITH
INHIBIT
13
3
COMMON Y
OUT/IN
COMMON X
OUT/IN
78
16
6
9
10
A †
B †
INH †
VSS VEE
VDD
TG
TG
TG
TG
TG
TG
TG
TG
4251
LOGIC
LEVEL
CONVERSION
11
10
9
6
A †
B †
C †
INH †
135 1 12 15 14
TG
TG
TG
TG
TG
TG
4
COMMON
OUT/IN
axaybxbycxcy
87
VSS VEE
16 VDD
IN/OUT
15
14
BINARY TO
1 OF 2
DECODERS
WITH
INHIBIT
LOGIC
LEVEL
CONVERSION
VDD
†All inputs protected by standard CMOS protection network
COMMON
OUT/IN
COMMON
OUT/IN
ax OR ay
bx OR by
cx OR cy
CD4051B, CD4052B, CD4053B
4
TRUTH TABLES
INPUT STATES
“ON” CHANNEL(S)INHIBIT C B A
CD4051B
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1 X X X None
CD4052B
INHIBIT B A
0 0 0 0x, 0y
0 0 1 1x, 1y
0 1 0 2x, 2y
0 1 1 3x, 3y
1 X X None
CD4053B
INHIBIT A OR B OR C
0 0 ax or bx or cx
0 1 ay or by or cy
1 X None
X = Don’t Care
CD4051B, CD4052B, CD4053B
5
Absolute Maximum Ratings Thermal Information
Supply Voltage (V+ to V-)
Voltages Referenced to VSS Terminal . . . . . . . . . . . -0.5V to 20V
DC Input Voltage Range . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A
CERDIP Package. . . . . . . . . . . . . . . . . 115 45
SOIC Package . . . . . . . . . . . . . . . . . . . 115 N/A
Maximum Junction Temperature (Ceramic Package) . . . . . . . . .175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = ±5V, AV = +1,
RL = 100Ω, Unless Otherwise Specified (Note 3)
PARAMETER
CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC)
UNITSVIS (V) VEE (V) VSS (V) VDD (V) -55 -40 85 125
25
MIN TYP MAX
SIGNAL INPUTS (VIS) AND OUTPUTS (VOS)
Quiescent Device
Current, IDD Max - - - 5 5 5 150 150 - 0.04 5 µA
- - - 10 10 10 300 300 - 0.04 10 µA
- - - 15 20 20 600 600 - 0.04 20 µA
- - - 20 100 100 3000 3000 - 0.08 100 µA
Drain to Source ON
Resistance rON Max
0≤ VIS ≤ VDD
- 0 0 5 800 850 1200 1300 - 470 1050 Ω
- 0 0 10 310 330 520 550 - 180 400 Ω
- 0 0 15 200 210 300 320 - 125 240 Ω
Change in ON
Resistance (Between
Any Two Channels),
∆rON
- 0 0 5 -----15 - Ω
- 0 0 10 - - - - - 10 - Ω
-0015-----5-Ω
OFF Channel Leakage
Current: Any Channel
OFF (Max) or ALL
ChannelsOFF(Common
OUT/IN) (Max)
-0018±100 (Note 2) ±1000 (Note 2) - ±0.01 ±100
(Note 2) µA
Capacitance: - -5 5- 5
Input, CIS -----5 - pF
Output, COS
CD4051 - - - - - 30 - pF
CD4052 - - - - - 18 - pF
CD4053 - - - - - 9 - pF
Feedthrough
CIOS -----0.2 - pF
Propagation Delay Time
(Signal Input to Output VDD RL = 200kΩ,
CL = 50pF,
tr, tf = 20ns
5 - - - - - 30 60 ns
10-----1530ns
15-----1020ns
CD4051B, CD4052B, CD4053B
6
CONTROL (ADDRESS OR INHIBIT), VC
Input Low Voltage, VIL,
Max VIL = VDD
through
1kΩ;
VIH = VDD
through
1kΩ
VEE = VSS,
RL = 1kΩ to VSS,
IIS < 2µA on All
OFF Channels
5 1.5 1.5 1.5 1.5 - - 1.5 V
103333 - - 3 V
154444 - - 4 V
Input High Voltage, VIH,
Min 5 3.5 3.5 3.5 3.5 3.5 - - V
1077777 - - V
15 11 11 11 11 11 - - V
Input Current, IIN (Max) VIN = 0, 18 18 ±0.1 ±0.1 ±1±1-±10-5 ±0.1 µA
Propagation Delay Time:
Address-to-Signal
OUT(ChannelsON or
OFF) See Figures 10,
11, 14
tr, tf = 20ns,
CL = 50pF,
RL = 10kΩ
0 0 5 - - - - - 450 720 ns
0 0 10 - - - - - 160 320 ns
0 0 15 - - - - - 120 240 ns
-5 0 5 - - - - - 225 450 ns
Propagation Delay Time:
Inhibit-to-Signal OUT
(Channel Turning ON)
See Figure 11
tr, tf = 20ns,
CL = 50pF,
RL = 1kΩ
0 0 5 - - - - - 400 720 ns
0 0 10 - - - - - 160 320 ns
0 0 15 - - - - - 120 240 ns
-10 0 5 - - - - - 200 400 ns
Propagation Delay Time:
Inhibit-to-Signal OUT
(Channel Turning
OFF) See Figure 15
tr, tf = 20ns,
CL = 50pF,
RL = 10kΩ
0 0 5 - - - - - 200 450 ns
0 0 10 - - - - - 90 210 ns
0 0 15 - - - - - 70 160 ns
-10 0 5 - - - - - 130 300 ns
Input Capacitance, CIN
(Any Address or Inhibit
Input)
- - - - - 5 7.5 pF
NOTE:
2. Determined by minimum feasible leakage measurement for automatic testing.
Electrical Specifications
PARAMETER
TEST CONDITIONS LIMITS
UNITSVIS (V) VDD (V) RL (kΩ) TYP
Cutoff (-3dB) Frequency Chan-
nel ON (Sine Wave Input) 5 (Note 3) 10 1 VOS at Common OUT/IN CD4053 30 MHz
VEE = VSS, CD4052 25 MHz
CD4051 20 MHz
VOS at Any Channel 60 MHz
Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = ±5V, AV = +1,
RL = 100Ω, Unless Otherwise Specified (Continued) (Note 3)
PARAMETER
CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC)
UNITSVIS (V) VEE (V) VSS (V) VDD (V) -55 -40 85 125
25
MIN TYP MAX
20LogVOS
VIS
------------3dB–=
CD4051B, CD4052B, CD4053B
7
Total HarmonicDistortion, THD 2 (Note 3) 5 10 0.3 %
3 (Note 3) 10 0.2 %
5 (Note 3) 15 0.12 %
VEE = VSS, fIS = 1kHz Sine Wa v e %
-40dB Feedthrough Frequency
(All Channels OFF) 5 (Note 3) 10 1 VOS at Common OUT/IN CD4053 8 MHz
VEE = VSS, CD4052 10 MHz
CD4051 12 MHz
VOS at Any Channel 8 MHz
-40dB Signal Crosstalk
Frequency 5 (Note 3) 10 1 Between Any 2 Channels 3 MHz
VEE = VSS, Between Sections,
CD4052 Only Measured on Common 6 MHz
Measured on Any Chan-
nel 10 MHz
Between Any Two
Sections, CD4053
Only
In Pin 2, Out Pin 14 2.5 MHz
In Pin 15, Out Pin 14 6 MHz
Address-or-Inhibit-to-Signal
Crosstalk -1010
(Note 4) 65 mVPEAK
VEE =0,VSS =0,tr,tf= 20ns,VCC
= VDD - VSS (Square Wave) 65 mVPEAK
NOTES:
3. Peak-to-Peak voltage symmetrical about
4. Both ends of channel.
Typical Performance Curves
FIGURE 1. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES) FIGURE 2. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
Electrical Specifications
PARAMETER
TEST CONDITIONS LIMITS
UNITSVIS (V) VDD (V) RL (kΩ) TYP
20LogVOS
VIS
------------40dB–=
20LogVOS
VIS
------------40dB–=
VDD VEE
–
2
-----------------------------
-4 -3 -2 -1 0 1 2 3 4
0
100
200
300
400
500
600
VIS, INPUT SIGNAL VOLTAGE (V)
rON, CHANNEL ON RESISTANCE (Ω)
TA = 125oC
TA = -55oC
TA = 25oC
VDD - VEE = 5V
5-10 -7.5 -5 -2.5 0 2.5 5 7.5 10
0
50
100
150
200
250
300
VIS, INPUT SIGNAL VOLTAGE (V)
rON, CHANNEL ON RESISTANCE (Ω)
TA = 125oC
TA = 25oC
TA = -55oC
VDD - VEE = 10V
CD4051B, CD4052B, CD4053B
8
FIGURE 3. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES) FIGURE 4. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
FIGURE 5. ON CHARACTERISTICS FOR 1 OF 8 CHANNELS
(CD4051B) FIGURE 6. DYNAMIC POWER DISSIPATION vs SWITCHING
FREQUENCY (CD4051B)
FIGURE 7. DYNAMIC POWER DISSIPATION vs SWITCHING
FREQUENCY (CD4052B) FIGURE 8. DYNAMIC POWER DISSIPATION vs SWITCHING
FREQUENCY (CD4053B)
Typical Performance Curves
(Continued)
-10 -7.5 -5 -2.5 0 2.5 5 7.5 10
0
100
200
300
400
600
500
VIS, INPUT SIGNAL VOLTAGE (V)
rON, CHANNEL ON RESISTANCE (Ω)
TA = 25oC
15V
10V
VDD - VEE = 5V
-10 -7.5 -5 -2.5 0 2.5 5 7.5 10
0
50
100
150
200
250
VIS, INPUT SIGNAL VOLTAGE (V)
rON, CHANNEL ON RESISTANCE (Ω)
VDD - VEE = 15V
TA = 125oC
TA = 25oC
TA = -55oC
-6 -4 -2 0 2 4 6
VIS, INPUT SIGNAL VOLTAGE (V)
VOS, OUTPUT SIGNAL VOLTAGE (V)
-6
-4
-2
0
2
4
6VDD = 5V
VSS = 0V
VEE = -5V
TA = 25oC
RL = 100kΩ, RL = 10kΩ
100Ω
500Ω
1kΩTA = 25oC
ALTERNATING “O”
CL = 50pF
AND “I” PATTERN
105
104
103
10
VDD = 15V
VDD = 5V
CL = 15pF
102
102
10
103
104
105
SWITCHING FREQUENCY (kHz)
PD, POWER DISSIPATION PACKAGE (µW)
1
TEST CIRCUIT
VDD
3
5
1011
6
7
8
14
15
1
2
13
12
4CL
CD4051
f
100Ω
100Ω
B/D
CD4029
VDD
ABC
9
Ι
VDD = 10V
105
104
103
10 102
102
10
103
104
105
SWITCHING FREQUENCY (kHz)
PD, POWER DISSIPATION PACKAGE (µW)
1
VDD = 15V
VDD = 5V
TA = 25oC
ALTERNATING “O”
CL = 50pF
AND “I” PATTERN
VDD
3
5
10
11
6
78
14
15
1
213
12
4
CL
CD4052
f
100Ω
100Ω
B/D
CD4029
VDD
AB
9
Ι
TEST CIRCUIT
VDD = 10V
CL = 15pF
105
104
103
10
VDD = 15V
VDD = 10V
VDD = 5V
TA = 25oC
ALTERNATING “O”
CL = 50pF
AND “I” PATTERN
CL = 15pF
102
102
10
103
104
105
SWITCHING FREQUENCY (kHz)
PD, POWER DISSIPATION PACKAGE (µW)
Ι
TEST CIRCUIT
VDD 9
3
5
10
11
6
78
14
15
1
2
13
12
4CL
CD4053
f
100Ω
100Ω
1
CD4051B, CD4052B, CD4053B
9
Test Circuits and Waveforms
FIGURE 9. TYPICAL BIAS VOLTAGES
FIGURE 10. WAVEFORMS, CHANNEL BEING TURNED ON
(RL = 1kΩ)FIGURE 11. WAVEFORMS, CHANNEL BEING TURNED OFF
(RL = 1kΩ)
FIGURE 12. OFF CHANNEL LEAKAGE CURRENT - ANY CHANNEL OFF
VDD = 5V
VSS = 0V
VEE = -7.5V 7
8
(B) (C) (D)
(A)
VDD = 7.5V
7.5V 1616 1616
7
87
8
VDD = 5V
VDD = 15V
VSS = 0V
VEE = 0V 7
8
5V
VEE = -10V
VSS = 0V VSS = 0V
5V
VEE = -5V
NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels
are: “0” = VSS and “1” = VDD. The analog signal (through the TG) may
swing from VEE to VDD.
tf = 20ns
10%
10%
90%
50%
10%
50%
90%
10%
50%
90%
tr = 20ns
TURN-OFF TIME
TURN-ON TIME
tf = 20ns
10%
90%
50% 10%
50%
90%
10%
90%
tr = 20ns
TURN-OFF TIME TURN-ON
tPHZ TIME
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IDD IDD IDD
VDD VDD
CD4053
CD4052
CD4051
CD4051B, CD4052B, CD4053B
10
FIGURE 13. OFF CHANNEL LEAKAGE CURRENT - ALL CHANNELS OFF
FIGURE 14. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT
FIGURE 15. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT
FIGURE 16. INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY)
Test Circuits and Waveforms
(Continued)
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4052
IDD
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4051
IDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4053
IDD
VDD
VDD
CD4051
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VEE
VEE
VEE VEE VEE
VEE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS CD4052 CD4053
CLOCK
IN
CLOCK
IN
CLOCK
IN
RL
RLRLCL
CL
CL
OUTPUT OUTPUT OUTPUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
VEE
tPHL AND tPLH
VSS CLOCK
IN
RL
OUTPUT
CD4051
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4052
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4053
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
VDD
VDD VDD
VDD
VDD VDD
VDD
OUTPUT OUTPUT
tPHL AND tPLH
tPHL AND tPLH
RLRL
VSS
CLOCK
IN
CLOCK
IN
VSS
VSS
VEE
VEE
50pF 50pF
VEE
VSS VSS
VSS VSS
VSS
VEE
VEE
50pF
CD4051B
VIL
VIH
VDD
VIH
VIL
1K
1K
µA
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 6)
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16 µA
VIL VIL
VIH VIH
1K 1K
VDD
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL by)
CD4053B
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
VIH
VIH
VIL
1K
1K
VDD
µA
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 2x)
VIL
CD4052B
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
CD4051B, CD4052B, CD4053B
11
FIGURE 17. QUIESCENT DEVICE CURRENT FIGURE 18. CHANNEL ON RESISTANCE MEASUREMENT
CIRCUIT
FIGURE 19. INPUT CURRENT
FIGURE 20. FEEDTHROUGH (ALL TYPES) FIGURE 21. CROSSTALK BETWEEN ANY TWO CHANNELS
(ALL TYPES)
FIGURE 22. CROSSTALK BETWEEN DUALS OR TRIPLETS (CD4052B, CD4053B)
Test Circuits and Waveforms
(Continued)
CD4051
CD4053
Ι
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
CD4052
Ι
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
VDD
VDD
X-Y
PLOTTER
X
Y
1kΩ
RANGE
TG
“ON”
KEITHLEY
160 DIGITAL
MULTIMETER
H.P.
MOSELEY
7030A
VSS
VDD
10kΩ
VDD
Ι
VDD
VSS CD4051
CD4053
VSS
NOTE: Measureinputssequentially,
to both VDD and VSS connect all
unused inputs to either VDD or VSS.
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
VDD
Ι
VDD
VSS CD4052 VSS
NOTE: Measureinputssequentially,
to both VDD and VSS connect all
unused inputs to either VDD or VSS.
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
RF
VM
VDD
OFF
CHANNEL
6
7
8
1K
5VP-P
OFF
CHANNEL
RL
COMMON
ON
CHANNEL
RL
RF
VM ON
CHANNEL RL
5VP-P
OFF
CHANNEL
RL
RF
VM
5VP-P RF
VM
ON OR OFF
CHANNEL IN Y
RL
RL
ON OR OFF
CHANNEL IN X
CD4051B, CD4052B, CD4053B
12
Special Considerations
In applications where separate power sources are used to
drive VDD and the signal inputs, the VDD current capability
should exceed VDD/RL(RL= effective external load). This
provision avoids permanent current flow or clamp action on
the VDD supply when power is applied or removed from the
CD4051B, CD4052B or CD4053B.
FIGURE 23. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052B
Test Circuits and Waveforms
(Continued)
COMMUNICATIONS
LINK
DIFF.
AMPLIFIER/
LINE DRIVER
DIFF.
RECEIVER
DEMULTIPLEXING
DIFF.
MULTIPLEXING
DIFFERENTIAL
SIGNALS CD4052 CD4052
FIGURE 24. 24-TO-1 MUX ADDRESSING
A
B
E
1/2
CD4556
A
B
CCD4051B
INH
A
B
CCD4051B
INH
A
B
CCD4051B
INH
A
B
C
D
E
Q0
Q1
Q2
COMMON
OUTPUT
CD4051B, CD4052B, CD4053B
13
CD4051B, CD4052B, CD4053B
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. ControllingDimensions:INCH.In caseofconflictbetweenEnglish and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eBand eCare measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 1 2 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AM BS
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N16 169
Rev. 0 12/93
14
CD4051B, CD4052B, CD4053B
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
1. Indexarea:Anotchorapinoneidentificationmarkshallbelocat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
SS
ccc C A - B
MD
SSaaa C A - B
MD
S S
eA
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.200 - 5.08 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 0.840 - 21.34 5
E 0.220 0.310 5.59 7.87 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 - 7
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2, 3
N16 168
Rev. 0 4/94
15
CD4051B, CD4052B, CD4053B
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E” doesnotincludeinterleadflash orprotrusions.Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Theleadwidth“B”,asmeasured0.36mm(0.014inch)orgreaterabove
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controllingdimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AM BS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H0.25(0.010) BM M
α
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.3859 0.3937 9.80 10.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N16 167
α0o8o0o8o-
Rev. 0 12/93
