THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 D D D D D D D D VCM AVDD 48 47 46 45 44 43 42 41 40 39 38 37 AVSS AVDD VIN+ VIN- AVDD 1 36 2 35 3 34 4 33 5 32 VREFOUT- VREFIN- VREFIN+ VREFOUT+ VBG AVSS AVDD 6 31 7 30 8 29 9 28 10 27 11 26 12 25 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 13 14 15 16 17 18 19 20 21 22 23 24 DV SS CLK+ CLK- DV DD DV SS DV SS DV DD DV SS DV DD DRVSS DRVDD D D 40-MSPS Sample Rate 12-Bit Resolution No Missing Codes On-Chip Sample and Hold 80 dB Spurious Free Dynamic Range at fIN = 15.5 MHz 5-V Analog and Digital Supply 3-V and 5-V CMOS Compatible Digital Output 10.3 Bit ENOB at fIN = 31 MHz 64 dB SNR at fIN = 15.5 MHz 120-MHz Bandwidth Internal or External Reference Buffered Differential Analog Input 2s Complement Digital Outputs Typical 380 mW Power Consumption Single-Ended or Differential Low-Level Clock Input AV SS D D D D D AVSS AVDD AVSS AVDD AVSS AVSS DRVSS DRVSS DRVDD DRVDD 48 PHP PACKAGE (TOP VIEW) features applications D D D D D Wireless Local Loop Wireless Internet Access Cable Modem Receivers Medical Ultrasound Magnetic Resonant Imaging description The THS1240 is a high-speed low noise 12-bit CMOS pipelined analog-to-digital converter. A differential sample and hold minimizes even order harmonics and allows for a high degree of common mode rejection at the analog input. A buffered analog input enables operation with a constant analog input impedance, and prevents transient voltage spikes from feeding backward to the analog input source. Full temperature DNL performance allows for industrial application with the assurance of no missing codes. The THS1240 can operate with either internal or external references. Internal reference usage selection is accomplished simply by externally connecting reference output terminals to reference input terminals. AVAILABLE OPTIONS PACKAGE TA 48-TQFP (PHP) - 40C to 85C THS1240I 0C to 70C THS1240C Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 functional block diagram AVDD DVDD DRVDD VIN+ Stage 1 Buffer 1 k S/H A/D D/A A/D D/A A/D 1 1 2 3.0 V Reference AVDD/2 2.0 V VREFOUT- VREFIN- Stage 11 VIN- VREFIN+ VREFOUT+ Stage 10 Stages 2 - 9 Digital Error Correction VCM CLK+ Timing CLK- AVSS DVSS DRVSS D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AVDD 2, 5, 12, 43, 45, 47 I Analog power supply AVSS 1, 11, 13, 41, 42, 44, 46 I Analog ground return for internal analog circuitry CLK+ 15 I Clock input CLK- 16 I Complementary clock input D11-D0 25-36 O Digital data output bits; LSB= D0, MSB = D11 (2s complement output format) DRVDD DRVSS 24, 37, 38 I Digital output driver supply 23, 39, 40 I Digital output driver ground return DVDD 17, 20, 22 I Positive digital supply DVSS 18, 19, 21 I Digital ground return VBG VCM 10 O Band gap reference. Bypass to ground with a 1 F and a 0.01 F chip capacitor. 48 O Common mode voltage output. Bypass to ground with a 0.1 F and a 0.01 F chip capacitor. VIN+ VIN- 3 I Analog signal input 4 I Complementary analog signal input VREFIN - VREFIN+ 7 I External reference input low 8 I External reference input high VREFOUT+ VREFOUT - 9 O Internal reference output. Compensate with a 1 F and a 0.01 F chip capacitor. 6 O Internal reference output. Compensate with a 1 F and a 0.01 F chip capacitor. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 functional description The THS1240 uses a differential pipeline architecture and assures no missing codes over the full operating temperature range. The device uses a 1 bit per stage architecture in order to achieve the highest possible bandwidth. The differential analog inputs are terminated with a 1 k resistor. The inputs are then fed to a unity gain buffer followed by the S/H (sample and hold) stage. This S/H stage is a switched capacitor operational amplifier-based circuit, see Figure 3. The pipeline is a typical 1 bit per stage pipeline as shown in the functional block diagram. The digital output of the 12 stages is sent to a digital correction logic block which then outputs the final 12 bits. absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range: AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V DRVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage between AVSS and DVSS and DRVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 0.5 V Voltage between DRVDD and DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 5 V Voltage between AVDD and DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 5 V Digital data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to DVDD + 0.3 V CLK peak input current, Ip(CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Peak total input current (all inputs), Ip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30 mA Operating free-air temperature range, TA: THS1240C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C THS1240I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN Sample rate NOM MAX UNIT 40 MSPS 1 Analog supply voltage, AVDD 4.75 5 5.25 V Digital supply voltage, DVDD 4.75 5 5.25 V Digital output driver supply voltage, DRVDD CLK + high level input voltage, VIH 3 3.3 5.25 V 3.5 5 5.25 V CLK + low-level input voltage, VIL CLK pulse-width high, tp(H) 10 12.5 ns CLK pulse-width low, tp(L) 10 12.5 ns Operating free-air free air temperature range, range TA 0 THS1240C THS1240I 1.5 0 70 - 40 85 V C CLK- Input tied to ground with 0.01 F capacitor for single-ended clock source. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 electrical characteristics over recommended operating free-air temperature range, AVDD = DVDD = 5 V, DRVDD = 3.3 V, internal references, CLK = 40 MHz, single-ended clock source at 40 MHz with 50% duty cycle (unless otherwise noted) dc accuracy PARAMETER DNL TEST CONDITIONS Differential nonlinearity fIN = 15.5 MHz MIN TYP MAX UNIT -1 0.6 1.25 LSB No missing codes INL Assured Integral nonlinearity 2 fIN = 15.5 MHz V(VIN+) = V(VIN_) = VCM EO Offset error EG Gain error All typical values are at TA = 25C. LSB 14 70 -7 - 10 %FSR mV TYP MAX UNIT V(VIN) = (VCM) V(VIN) = (VCM) V(VIN) = (VCM) 73 110 mA 2 4 mA 2 7 V(VIN) = (VCM) 380 power supply PARAMETER I(AVDD) I(DVDD) TEST CONDITIONS Analog supply current Digital supply current Output driver supply current I(DRVDD) PD Power dissipation All typical values are at TA = 25C. 15 pF load on digital outputs MIN mA mW reference PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VREFOUT - VREFOUT+ Negative reference output voltage 1.9 2 2.1 V Positive reference output voltage 2.9 3 3.1 V VREFIN - VREFIN+ External reference supplied 2 V External reference supplied 3 V V(VCM) Common mode output voltage AVDD/2 I(VCM) Common mode output current All typical values are at TA = 25C. V A 80 analog input PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RI Differential input resistance 1 k CI Differential input capacitance 4 pF VI VID Analog input common mode range VCM 0.05 2 Differential input voltage range BW Analog input bandwidth (large signal) All typical values are at TA = 25C. -3 dB 120 V Vp-p MHz digital outputs PARAMETER VOH VOL TEST CONDITIONS IOH = - 50 A IOL = 50 A High-level output voltage Low-level output voltage CL Output load capacitance All typical values are at TA = 25C. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MIN TYP MAX 0.8DRVDD UNIT V 0.2DRVDD VDD 15 pF THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 ac specifications over recommended operating free-air temperature range, AVDD = DVDD = 5 V, DRVDD = 3.3 V, internal references, CLK = 40 MHz, analog input at -2 dBFS, single-ended clock source at 40 MHz with 50% duty cycle (unless otherwise noted) PARAMETER SNR Signal to noise ratio Signal-to-noise SINAD Signal to noise and distortion Signal-to-noise ENOB Effective number of bits THD Total harmonic distortion SFDR d Harmonic 2nd d Harmonic 3rd Spurious free dynamic range Spurious-free Distortion Distortion TEST CONDITIONS fIN = 2.2 MHz fIN = 15.5 MHz MIN 62 fIN = 2.2 MHz fIN = 15.5 MHz UNIT dB 64 63.3 60 64 dB 63.2 55.7 9.7 10.3 -72 bits -69 dBc 72.7 70 80.4 fIN = 31 MHz fIN = 70 MHz 59.6 fIN = 2.2 MHz fIN = 15.5 MHz -87 dBc 77 82 fIN = 31 MHz fIN = 70 MHz -60.5 fIN = 2.2 MHz fIN = 15.5 MHz -80.4 -70 -77 dBc -73 fIN = 31 MHz fIN = 70 MHz -70 -77 dBc -60 F1 = 14.9 MHz, F2 = 15.6 MHz, Analog inputs at - 8 dBFS each Two tone SFDR 64.5 64 fIN = 31 MHz fIN = 70 MHz fIN = 15.5 MHz fIN = 15.5 MHz MAX 64.6 fIN = 31 MHz fIN = 70 MHz fIN = 2.2 MHz fIN = 15.5 MHz TYP 72 dBc All typical values are at TA = 25C. operating characteristics over recommended operating conditions, AVDD = DVDD = 5 V, DRVDD = 3.3 V switching specifications PARAMETER TEST CONDITIONS Aperture delay, td(A) TYP MAX 120 Aperture jitter Output delay td(O), after falling edge of CLK+ MIN ps 1 Digital outputs driving a 15 pF load each Pipeline delay td(PIPE) ps RMS 13 6.5 UNIT ns CLK Cycle All typical values are at TA = 25C. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 definitions of specifications analog bandwidth The analog input frequency at which the spectral power of the fundamental frequency of a large input signal is reduced by 3 dB. aperture delay The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. aperture uncertainity (jitter) The sample-to-sample variation in aperture delay differential nonlinearity The deviation of any output code from the ideal width of 1 LSB. integral nonlinearity The deviation of the transfer function from an end-point adjusted reference line measured in fractions of 1 LSB. Also the integral of the DNL curve. clock pulse width/duty cycle Pulse width high is the minimum amount of time that the clock pulse should be left in logic 1 state to achieve rated performance; pulse width low is the minimum time clock pulse should be left in low state. At a given clock rate, these specs define acceptable clock duty cycles. offset error The difference between the analog input voltage at which the ADC output changes from mid-scale to 1 LSB above mid-scale, and the ideal voltage at which this transition should occur. gain error The difference between the analog input voltage at which the ADC output changes from full-scale to 1 LSB below full scale, and the ideal voltage at which this transition should occur, minus the offset error Gain Error + 100%x 2 * V2 )V* V IN IN_ @Code 4096 total harmonic distortion The ratio of the power of the fundamental to a given harmonic component reported in dBc. output delay The delay between the 50% point of the falling edge of the clock and the time when all output data bits are within valid logic levels (not including pipeline delay). signal-to-noise-and distortion (SINAD) When tested with a single tone, the ratio of the signal power to the sum of the power of all other spectral components, excluding dc, referenced to full scale. signal-to-noise ratio (SNR) When tested with a single tone, the ratio of the signal power to the sum of the power of all other power spectral components, excluding dc and the first 9 harmonics, referenced to full scale. effective number of bits (ENOB) For a sine wave, SINAD can be expressed in terms of the effective number of bits, using the following formula, ENOB + (SINAD6.02* 1.76) spurious-free dynamic range (SFDR) The ratio of the signal power to the power of the worst spur, excluding dc. The worst spurious component may or may not be a harmonic. The ratio is reported in dBc (that is, degrades as signal levels are lowered). 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 Sample N V(VIN) td(A) td(Pipe) tp(H) tP(L) CLK+ tc Digital Output (D0 - D11) td(O) Data N-7 Data N-6 Data N-5 Data N-4 Data N-3 Data N-2 Data N-1 Data N Data N+1 Data N+2 Figure 1. Timing Diagram equivalent circuits R2 BAND GAP 2 R1 VREFOUT+ VCM VREFOUT- R1 R2 1 VIN+ AVDD 1 1 k 1 VIN- 600 1 VCM VCM 600 2 AVSS Figure 2. References Figure 3. Analog Input Stage VDD DVDD To Timing Circuits R1 5 k DRVDD R1 5 k DVDD CLK+ 10 CLK- DVSS R2 5 k R2 5 k D0-D11 DVSS DRVSS Figure 5. Digital Outputs GND Figure 4. Clock Inputs POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 APPLICATION INFORMATION using the THS1240 references The option of internal or external reference is provided by allowing for an external connection of the internal reference to the reference inputs. This type of reference selection offers the lowest noise possible by not relying on any active switch to make the selection. Compensating each reference output with a 1-F and 0.01-F chip capacitor is required as shown in Figure 6. The differential analog input range is equal to 2 (VREFOUT+ - VREFOUT-). When using external references, it is best to decouple the reference inputs with a 0.1-F and 0.01-F chip capacitor as shown in Figure 7. VREFIN+ VREFOUT+ 0.01 F VREFIN+ External Reference + 0.01 F 1 F 0.1 F VREFIN- VREFOUT- 0.01 F VREFIN- External Reference - 0.01 F 1 F Figure 6. Internal Reference Usage 0.1 F Figure 7. External Reference Usage using the THS1240 clock input The THS1240 clock input can be driven with either a differential clock signal or a single ended clock input with little or no difference in performance between the single-ended and differential-input configurations. The common mode of the clock inputs is set internally to VDD/2 using 5-k resistors (Figure 4). The THS1240 clock input requires a common mode voltage or dc component of VDD/2. It is possible for the common mode voltage of the clock source to differ from VDD/2 by as much as 10% with little or no performance degradation. The clock input should be either a sinewave or a square wave having a 50% duty cycle. When driven with a single-ended CMOS clock input, it is best to connect the CLK- input to ground with a 0.01 F capacitor (see Figure 8). CLK+ Square Wave or Sine Wave 2 V p-p to 5 V p-p Common Mode Voltage = VDD/2 THS1240 CLK- 0.01 F Figure 8. Driving the Clock From a Single-Ended Clock Source 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 APPLICATION INFORMATION using the THS1240 clock input (continued) If the dc component of the input clock differs from VDD/2 by more than 10%, it is best to connect the CLK+ input to the clock source through a 0.01 F capacitor. In this mode, the converter can operate with a clock having a peak-to-peak voltage of as little as 2 V with little or no performance degradation (see Figure 9). Square Wave or Sine Wave 2 V p-p to 5 V p-p CLK+ 0.01 F THS1240 CLK- 0.01 F Figure 9. AC-Coupled Single-Ended Clock Input The THS1240 clock input can also be driven differentially. If the common mode of the clock input is VDD/2, then the clock inputs can be driven directly (see Figure 10) CLK+ Differential Square Wave or Sine Wave 2 V p-p to 5 V p-p Common Mode Voltage = VDD/2 THS1240 CLK- Figure 10. Differential Clock Input If the clock input is driven differentially with a clock signal having a common mode voltage that is different from VDD/2, then it is best to connect both clock inputs to the differential input clock signal with 0.01 F capacitors (see Figure 11). The differential input swing can vary between 2 V and 5 V with little or no performance degradation. Differential Square Wave or Sine Wave 2 V p-p to 5 V p-p CLK+ 0.01 F THS1240 CLK- 0.01 F Figure 11. AC-Coupled Differential Clock Input POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 APPLICATION INFORMATION using the analog input The THS1240 obtains optimum performance when the analog signal inputs are driven differentially. The circuit below shows the optimum configuration, see Figure 12. The signal is fed to the primary of an RF transformer. Since the input signal must be biased around the common mode voltage of the internal circuitry, the common mode (VCM) reference from the THS1240 is connected to the center-tap of the secondary. To ensure a steady low noise VCM reference, the best performance is obtained when the VCM output is connected to ground with a 0.1-F and 0.01-F low inductance capacitor. R0 Z0 = 50 1:1 VIN+ 50 R 50 AC Signal Source THS1240 VIN- T1-1T VCM 0.01 F 0.1 F Figure 12. Driving the THS1240 Analog Input With Impedance Matched Transmission Line When it is necessary to buffer or apply a gain to the incoming analog signal, it is also possible to combine a single-ended amplifier with an RF transformer as shown in Figure 13. For this application, a wide-band current mode feedback amplifier such as the THS3001 is best. The noninverting input to the operational amplifier is terminated with a resistor having an impedance equal to the characteristic impedance of the trace that sources the IF input signal. The single-ended output allows the use of standard passive filters between the amplifier output and the primary. In this case, the SFDR of the operational amplifier is not as critical as that of the A/D converter. While harmonics generated from within the A/D converter fold back into the first Nyquist zone, harmonics generated externally in the operational amplifier can be filtered out with passive filters. 1 k 1 k Impedance Ratio = 1:n 10 _ RT VIN+ BPF + IF Input THS3001 THS1240 VIN- VCM 0.1 F 0.01 F Figure 13. IF Input Buffered With THS3001 Operational Amplifier 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 APPLICATION INFORMATION digital outputs The digital outputs are in 2s complement format and can drive either TTL, 3-V CMOS, or 5-V CMOS logic. The digital output high voltage level is equal to DRVDD. Table 1 shows the value of the digital output bits for full scale analog input voltage, midrange analog input voltage, and negative full scale input voltage. To reduce capacitive loading, each digital output of the THS1240 should drive only one digital input. The CMOS output drivers are capable of handling up to a 15 pF load. For better SNR performance, use 3.3 V for DRVDD. Resistors of 200 in series with the digital output can be used for optimizing SNR performance. Table 1. Digital Outputs ANALOG INPUT VIN+ Vref+ VIN- Vref- VCM Vref- VCM Vref+ D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 power supplies Best performance is obtained when AVDD is kept separate from DVDD. Regulated or linear supplies, as opposed to switched power supplies, must be used to minimize supply noise. It is also recommended to partition the analog and digital components on the board in such a way that the analog supply plane does not overlap with the digital supply plane in order to limit dielectric coupling between the different supplies. package The THS1240 is packaged in a small 48-pin quad flat-pack PowerPAD package. The die of the THS1240 is bonded directly to copper alloy plate which is exposed on the bottom of the package. Although, the PowerPAD provides superior heat dissipation when soldered to a ground land, it is not necessary to solder the bottom of the PowerPAD to anything in order to achieve minimum performance levels indicated in this specification over the full recommended operating temperature range. Only if the device is to be used at ambient temperatures above the recommended operating temperatures, use of the PowerPAD is suggested. The copper alloy plate or PowerPAD is exposed on the bottom of the device package for a direct solder attachment to a PCB land or conductive pad. The land dimensions should have minimum dimensions equal to the package dimensions minus 2 mm, see Figure 14. For a multilayer circuit board, a second land having dimensions equal to or greater than the land to which the device is soldered should be placed on the back of the circuit board (see Figure 15). A total of 9 thermal vias or plated through-holes should be used to connect the two lands to a ground plane (buried or otherwise) having a minimum total area of 3 inches square in 1 oz. copper. For the THS1240 package, the thermal via centers should be spaced at a minimum of 1 mm. The ground plane need not be directly under or centered around the device footprint if a wide ground plane thermal run having a width on the order of the device is used to channel the heat from the vias to the larger portion of the ground plane. The THS1240 package has a standoff of 0.19 mm or 7.5 mils. In order to apply the proper amount of solder paste to the land, a solder paste stencil with a 6 mils thickness is recommended for this device. Too thin a stencil may lead to an inadequate connection to the land. Too thick a stencil may lead to beading of solder in the vicinity of the pins which may lead to shorts. For more information, refer to Texas Instruments literature number SLMA002 PowerPAD Thermally Enhanced Package. PowerPAD is a trademark of Texas Instruments. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 APPLICATION INFORMATION package (continued) 1,25 mm 2 x 1,25 mm 1,25 mm 5 mm 2 x 1,25 mm 0,33 mm Diameter Plated Through Hole 5 mm Figure 14. Thermal Land (top view) PHP (S-PQFP-G48) Thermal Land IIII IIIII II IIII II II IIIIII II IIIII IIIII II II IIIIII IIIII IIII IIIIII IIIII II II IIIIII IIIII II II IIIIII II IIII II IIIII II II IIIIII Plated Through Hole PWB Figure 15. Top and Bottom Thermal Lands With Plated Through Holes (side view) 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 TYPICAL CHARACTERISTICS Power - dBFS OUTPUT POWER SPECTRUM 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 FS = 40 MSPS fIN = 2.2 MHz VIN = -2 dBFS 8K Point Discrete Fourier Transform 0 5 10 15 20 15 20 15 20 f - Frequency - MHz Figure 16 Power - dBFS OUTPUT POWER SPECTRUM 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 FS = 40 MSPS fIN = 15.5 MHz VIN = -2 dBFS 8K Point Discrete Fourier Transform 0 5 10 f - Frequency - MHz Figure 17 Power - dBFS OUTPUT POWER SPECTRUM 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 FS = 40 MSPS fIN = 31 MHz VIN = -2 dBFS 8K Point Discrete Fourier Transform 0 5 10 f - Frequency - MHz Figure 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 TYPICAL CHARACTERISTICS Power - dBFS OUTPUT POWER SPECTRUM 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 FS = 40 MSPS fIN = 69 MHz VIN = -2 dBFS 8K Point Discrete Fourier Transform 0 5 10 15 20 f - Frequency - MHz Figure 19 Power - dBFS TWO-TONE OUTPUT POWER SPECTRUM 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 FS = 40 MSPS fIN = 14.9 MHz and 15.6 MHz VIN = -8 dBFS Each 8K Point Discrete Fourier Transform 0 5 10 15 20 f - Frequency - MHz Figure 20 Dynamic Power Performance - dB DYNAMIC POWER PERFORMANCE vs ANALOG INPUT POWER D 100 90 FS = 40 MSPS fIN = 15.5 MHz 80 SNR (dB) 3rd Harmonic (dBc) 70 60 SFDR (dBc) 50 SINAD (dB) 40 30 -60 2nd Harmonic (dBc) -50 -40 -30 -20 Analog Input Power - dBFS Figure 21 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 -10 0 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 Dynamic Power Performance - dB TYPICAL CHARACTERISTICS DYNAMIC POWER PERFORMANCE vs SAMPLING RATE 3rd Harmonic (dBc) 100 2nd Harmonic (dBc) SNR (dB) 90 3rd Harmonic (dBc) 80 70 60 SFDR (dBc) SINAD (dB) 50 fIN = 15.5 MHz VIN = -2 dBFS 40 30 0 10 20 30 40 50 60 Sampling Rate - MSPS Dynamic Power Performance - dB, dBc Figure 22 DYNAMIC POWER PERFORMANCE vs DUTY CYCLE 100 fIN = 15.5 MHz VIN_ -2 dBFS 90 SFDR (dBc) SNR (dB) 80 70 60 50 SINAD (dB) 40 30 40 50 60 70 Duty Cycle - % Figure 23 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 Dynamic Power Performance - dB, dBc TYPICAL CHARACTERISTICS DYNAMIC POWER PERFORMANCE vs ANALOG INPUT FREQUENCY 100 2nd Harmonic (dBc) 3rd Harmonic (dBc) 90 SNR (dB) 80 70 60 FS = 40 MSPS VIN = -2 dBFS 50 SFDR (dBc) SINAD (dB) 40 0 10 20 30 40 50 60 70 80 3072 3584 4096 Analog Input Frequency - MHz Figure 24 Differential Nonlinearity - LSB DIFFERENTIAL NONLINEARITY vs OUTPUT CODE 1 fIN = 15.5 MHz 0 -1 0 512 1024 1536 2048 2560 Output Code Figure 25 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY vs OUTPUT CODE Integral Nonlinearity - LSB 2 fIN = 15.5 MHz 1 0 -1 -2 0 512 1024 1536 2048 2560 3072 3584 4096 Output Code Figure 26 ANALOG INPUT POWER BANDWIDTH 0 Power - dBFS -5 -10 -15 -20 -25 FS = 40 MSPS VIN = -2 dBFS -30 0 20 40 60 80 100 120 140 160 180 200 f - Frequency - MHz Figure 27 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 THS1240 12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER SLAS279B - JUNE 2000 - REVISED SEPTEMBER 2000 MECHANICAL DATA PHP (S-PQFP-G48) PowerPAD PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 Thermal Pad (see Note D) 48 13 0,13 NOM 1 12 5,50 TYP Gage Plane 7,20 SQ 6,80 9,20 SQ 8,80 0,25 0,15 0,05 1,05 0,95 0- 7 0,75 0,45 Seating Plane 0,08 1,20 MAX 4146927/A 01/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153 PowerPAD is a trademark of Texas Instruments. 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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