FH101-G
High Dynamic Range FET
Datasheet: Rev A 05-15-13
- 1 of 7 -
Disclaimer: Subject to change without notice
© 2013 TriQuint
www.triquint.com
Applications
• Mobile Infrastructure
• CATV / DBS
• W-LAN / ISM
• Defense / Homeland Security
SOT-89 Package
Product Features
• 50 – 4000 MHz
• Low Noise Figure
• 18 dB Gain
• +36 dBm OIP3
• +18 dBm P1dB
• Single or Dual Supply Operation
• Lead-free/Green/RoHS-compliant SOT-89 Package
• MTTF > 100 years
Ordering Information
Part No.
Description
FH101-G High Dynamic Range FET
Standard T/R size = 1000 pieces on a 7” reel
Product Features
Gate Drain
Source
21 3
4
Source
General Description
The FH101-G is a high dynamic range FET- packaged in
a low
-cost surface-mount package. The co
mbination of
low noise figure and high output IP3 at the same bias
point makes it ideal for receiver and transmitter
applications. The device combines dependable
performance with superb quality to maintain MTTF
values exceeding 100 years at mounting temperatures of
+85
°C. The FH101-G is available the environmentally
-
friendly lead
-free/green/RoHS-compliant SOT−
89
package.
The device utilizes a high reliability GaAs MESFET
technology and is targeted for applications where high
linearity is required. It
is well suited for various current
and next generation wireless technologies such as
GPRS, GSM, CDMA, and W
-
CDMA. In addition, the
FH101
-G
will work for other applications within the 50 to
4000 MHz frequency range such as fixed wireless.
Pin Configuration
Label
1 Gate
2, 4 Source
3 Drain
FH101-G
High Dynamic Range FET
Datasheet: Rev A 05-15-13
- 2 of 7 -
Disclaimer: Subject to change without notice
© 2013 TriQuint
www.triquint.com
Recommended Operating Conditions
Parameter
Min
Typ
Max
Units
TCASE
-40
+85
°C
Tj for >106 hours MTTF
+160
°C
Electrical specifications are measured at specified test
conditions. Specifications are not guaranteed over all
recommended operating conditions.
Absolute Maximum Ratings
Parameter
Rating
Storage Temperature
-55 to 150°C
Drain to Source Voltage
+7 V
Gate to Source Voltage -6 V
Gate Current
4.5 mA
RF Input Power,
CW, 50Ω, T=25
°
C
Input P1dB + 4dB
Operation of this device outside the parameter ranges
given above may cause permanent damage.
Electrical Specifications
Test conditions unless otherwise noted:
VDS
=+5 V,
VGS
=0 V, Temp= +25°C, 50Ω System
Parameter
Conditions
Min
Typ
Max
Units
Operational Frequency Range
50
4000
MHz
Test Frequency
800
MHz
Saturated Drain Current, IDSS
VGS=0 V
140
170
mA
Transconductance, Gm
120
mS
Pinch-off Voltage, VP
IDS=0.6 mA
-3
-1.5
V
Small-signal Gain, GSS
17
18
dB
Max Stable Gain, GMSG
23
dB
Output P1dB
+18
dBm
Output IP3 Pout = +5 dBm/tone, ∆f =10 MHz +32 +36 dBm
Noise Figure
ΓS = ΓL= ΓOPT
0.77
dB
Thermal Resistance, θjc
Module (junction to case)
59
°C/W
Typical Performance (1)
Test conditions unless otherwise noted: V
DS
=+5V, I
DS
=140 mA, Temp= +25°C
Parameter
Conditions
Typical Value
Units
Frequency
900
1960
2140
MHz
Gain
19
16.5
16.5
dB
Input Return Loss
11
20
22
dB
Output Return Loss
10
9
9
dB
Output P1dB
+18.8
+18.1
+19.1
dBm
OIP3
Pout = +5 dBm/tone, ∆f =10 MHz
+36
+36
+36
dBm
Noise figure 2.7 3.1 3.0 dB
Notes:
1. The device requires appropriate matching to become unconditionally stable. Parameters reflect performance in an
appropriate application circuit.
FH101-G
High Dynamic Range FET
Datasheet: Rev A 05-15-13
- 3 of 7 -
Disclaimer: Subject to change without notice
© 2013 TriQuint
www.triquint.com
Device Characterization Data
The gain for the unmatched device in
50 ohm system is shown as the trace
in black color, [gain (S(2
1)].
The
maximum stable gain is shown as the
blue trace [Gmax].
For a tuned circuit for a particular
frequency, it is expected that actual
gain will be higher, up to the
maximum stable gain.
The impedance plots are
shown from
0.05
– 6 GHz.
0 1 2 3
Frequency (GHz)
Gain and Max. Stable Gain
12
14
16
18
20
22
24
S21 and MSG (dB)
DB(|S(2,1)|)
DB(GMax())
0
1.0 1.0-1.0
10.0
10.0
-10.0
5.0
5.0
-5.0
2.0
2.0
-2.0
3.0
3.0
-3.0
4.0
4.0
-4.0
0.2
0.2
-0.2
0.4
0.4
-0.4
0.6
0.6
-0.6
0.8
0.8
-0.8
S11
Swp Max
6GHz
Swp Min
0.01GHz
0
1.0 1.0-1.0
10.0
10.0
-10.0
5.0
5.0
-5.0
2.0
2.0
-2.0
3.0
3.0
-3.0
4.0
4.0
-4.0
0.2
0.2
-0.2
0.4
0.4
-0.4
0.6
0.6
-0.6
0.8
0.8
-0.8
S22
Swp Max
6GHz
Swp Min
0.01GHz
Output IP3 vs. Temperature
25
30
35
40
45
-40 -15 10 35 60 85
Temperature (°C)
OIP3 (dBm)
5V 100% Idss
Output IP3 vs. Output Power
25
30
35
40
45
0246810 12
Output Power per tone (dBm)
OIP3 (dBm)
5V 100% Idss
Noise Figure vs. Frequency
0
0.5
1
1.5
2
2.5
0.5 11.5 2
Frequency (GHz)
Noise Figure (dB)
NF (unmatched device)
Minimum NF
S-Parameters
Test Conditions: VD=+5 V, ID=140 mA, T=+25°C, 50 ohm system, calibrated to device leads
Freq (MHz)
S11 (dB)
S11 (ang)
S21 (dB)
S21 (ang)
S12 (dB)
S12 (ang)
S22 (dB)
S22 (ang)
50
0.00
-4.08
19.36
176.06
-51.05
87.96
-4.38
-3.34
250
-0.13
-19.64
19.19
164.65
-37.15
78.37
-4.52
-11.51
500
-0.34
-39.41
18.85
150.19
-31.34
66.75
-4.77
-22.43
750
-0.55
-58.33
18.47
136.21
-28.24
55.74
-5.19
-33.05
1000
-0.83
-75.93
17.95
123.24
-26.22
45.25
-5.77
-43.46
1250
-1.16
-93.29
17.47
110.92
-24.88
35.22
-6.44
-53.09
1500
-1.50
-110.36
16.82
99.18
-23.95
26.69
-7.14
-61.08
1750
-1.80
-125.64
16.21
88.19
-23.27
18.17
-7.94
-69.92
2000
-2.03
-140.92
15.65
77.53
-22.81
9.87
-8.84
-78.43
2250
-2.25
-155.64
15.05
67.15
-22.39
2.11
-9.57
-86.41
2500
-2.37
-169.80
14.42
57.62
-22.25
-4.68
-10.43
-93.92
2750
-2.55
177.26
13.74
48.11
-22.08
-11.35
-11.43
-101.88
3000
-2.62
165.93
13.18
39.86
-22.01
-17.16
-12.30
-108.95
Noise Parameters
Test Conditions: VD=+5 V, ID=140 mA, T=+25°C, 50 ohm system, calibrated to device leads
Freq (GHz)
NF
min
(dB)
MagOpt (mag)
AngOpt (deg)
Rn (Ω)
700
0.51
0.574
32.8
0.403
800
0.77
0.535
37.4
0.409
900
0.66
0.508
44.1
0.379
1000
0.74
0.488
50.4
0.365
1100
0.85
0.463
56.4
0.357
1200
0.85
0.458
62.0
0.345
1300
0.95
0.446
67.3
0.335
1400
1.07
0.450
73.3
0.323
FH101-G
High Dynamic Range FET
Datasheet: Rev A 05-15-13
- 4 of 7 -
Disclaimer: Subject to change without notice
© 2013 TriQuint
www.triquint.com
Reference Design − 800-2200 MHz, 15 dB Gain
Test Conditions: VDS=+5 V, IDS=140 mA, T=+25°C
Parameter
Typical Value
Units
C=2 pF
ID=C3
C=100 pF
ID=C5
L=6.8 nH
ID=L1
L=18 nH
ID=R1
L=2.7 nH
ID=C1
R=2.2 Ohm
TLINP
ID=TL1
Z0=50 Ohm
L=80 mil
Eeff=3.4
Loss=0
F0=0 GHz
ID=C2
C=100 pF
ID=C4
C=100 pF
ID=R6
R=240 Ohm
ID=R7
R=240 Ohm
ID=C6
C=100 pF
1
2
NET="FH1"
+5V
L1
C1
U1
R1 C2
C3
R4
J3
J4
R2
C4
C
C5
R6
R7
C6
Frequency
900
1900
2140
MHz
Gain
14.9
16.3
16.4
dB
Input Return Loss
22
10
18
dB
Output Return Loss
14
9.7
9.6
dB
Output P1dB
+19.1
+19.4
+19.1
dBm
OIP3
+35.7
+37.0
+36.0
dBm
Noise figure
2.4
2.6
2.8
dB
0.75 11.25 1.5 1.75 22.25
Frequency (GHz)
Gain / Return Loss
8
10
12
14
16
18
Gain (dB)
-30
-20
-10
0
10
20
Return Loss (dB)
DB(|S(1,1)|) (R) DB(|S(2,1)|) (L) DB(|S(2,2)|) (R)
Notes:
1. Gain for the circuit can be adjusted slightly with the modification of the feedback resistance.
2. A DC blocking capacitor needs to be placed to the left of C1 if DC is present at the input of the circuit.
0Ω jumper
FH101-G
High Dynamic Range FET
Datasheet: Rev A 05-15-13
- 5 of 7 -
Disclaimer: Subject to change without notice
© 2013 TriQuint
www.triquint.com
Pin Configuration and Description
Gate Drain
Source
21 3
4
Source
Pin No.
Description
1
Gate
RF Input. Requires DC blocking capacitor.
3 Drain
RF Output/Bias. Supply DC bias via an inductor of appropriate
value for frequency of operation.
2, 4 Source
RF/DC ground. Use recommended via pattern for optimum
source inductance and thermal resistance. See PCB Mounting
Pattern for suggested footprint.
Evaluation Board PCB Information
TriQuint PCB 1069136 Material and Stack-up
50 Ohm Line Width: 28 mils
FH101-G
High Dynamic Range FET
Datasheet: Rev A 05-15-13
- 6 of 7 -
Disclaimer: Subject to change without notice
© 2013 TriQuint
www.triquint.com
Package Marking and Dimensions
Marking: Part number – FH101G
Lot code – AaXXXX
Notes:
1. All dimensions are in millimeters. Angles are in degrees.
2. Dimension and tolerance formats conform to ASME Y14.4M-1994.
3. The terminal #1 identifier and terminal numbering conform to JESD 95-1 SPP-012.
4. Contact plating: NiPdAu
PCB Mounting Pattern
3.86 [0.152]
0.64 [0.025] 2X 0.86 [0.034]
0.76 [0.030]
0.38 [0.015]
Ø.254 (.010) PLATED THRU VIA HOLES
0.76 [0.030]
2X 1.27 [0.050]
0.86 [0.034]
2X 0.58 [0.023]
4.50 [0.177]
2.65 [0.104]
PACKAGE OUTLINE
3.86 [0.152]
3
1.42 [0.056]
0.76 [0.030]
3.03 [0.119]
Notes:
1. All dimensions are in millimeters. Angles are in degrees.
2. Use 1 oz. copper minimum for top and bottom layer metal.
3. Use via pattern as shown for proper RF/DC grounding and thermal dissipation
4. We recommend a 0.35mm (#80/.0135"
) diameter bit for drilling via holes and a final plated thru diameter of 0.25 mm (0.10”).
5. Ensure good package backside paddle solder attach for reliable operation and best electrical performance.
FH101G
XXXX
FH101-G
High Dynamic Range FET
Datasheet: Rev A 05-15-13
- 7 of 7 -
Disclaimer: Subject to change without notice
© 2013 TriQuint
www.triquint.com
Product Compliance Information
ESD Sensitivity Ratings
Caution! ESD-Sensitive Device
ESD Rating:
Class 1B
Value:
Passes ≥ 500 V to < 1000 V
Test:
Human Body Model (HBM)
Standard:
JEDEC Standard JESD22-A114
ESD Rating:
Class IV
Value:
Passes ≥ 1000 V to < 2000 V
Test:
Charged Device Model (CDM)
Standard:
JEDEC Standard JESD22-C101
Solderability
Compatible with both le
ad-
free (260°C maximum reflow
temperature) and tin/lead (245°C maximum reflow
temperature) soldering processes.
Contact plating:
NiPdAu
RoHs Compliance
This part
is
compliant with EU 2002/95/EC RoHS
directive (Restrictions on the Use of Certain Hazardous
Substances in Electrical and Electronic Equipment).
This product also has the following attributes:
• Lead Free
• Halogen Free (Chlorine, Bromine)
• Antimony Free
• TBBP-A (C15H12Br402) Free
• PFOS Free
• SVHC Free
MSL Rating
MSL Rating:
Level 1
Test:
260°C convection reflow
Standard:
JEDEC Standard IPC/JEDEC J-STD-020
Contact Information
For the latest specifications, additional product information, worldwide sales and distribution locations, and information
about TriQuint:
Web: www.triquint.com Tel: +1.503.615.9000
Email: info-sales@triquint.com Fax: +1.503.615.8902
For technical questions and application information:
Email: sjcapplications.engineering@triquint.com
Important Notice
The information contained herein is believed to be reliable. TriQuint makes no warranties regarding the information
contained herein.
TriQuint assumes no responsibility or liability whatsoever for any of the information contained
herein. TriQuint assumes no responsibility or liability whatsoever for the use of the information contained herein. The
information contained herein is provided "AS IS, WHERE IS" and with all faults, and the entire risk associated with
such information is entirely with the user. All information contained herein is subject to change without notice.
Customers should obtain and verify the latest relevant information before placing orders for TriQuint products. The
information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any
patent rights, licenses, or any other intellectual property rights, whether with
regard to such information itself or
anything described by such information.
TriQuint products are not warranted or authorized for use as critical components in medical, life
-saving, or life
-
sustaining applications, or other applications where a failure
would reasonably be expected to cause severe personal
injury or death.