100G Interlaken MegaCore Function User Guide Subscribe Send Feedback Last updated for Quartus Prime Design Suite: 16.0 UG-01128 2016.05.02 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 About This MegaCore Function Contents About This IP Core..............................................................................................1-1 Features......................................................................................................................................................... 1-2 IP Core Supported Combinations of Number of Lanes and Data Rate................................... 1-2 IP Core Theoretical Raw Aggregate Bandwidth..........................................................................1-2 Device Family Support................................................................................................................................ 1-3 IP Core Verification.....................................................................................................................................1-3 Performance and Resource Utilization.....................................................................................................1-4 Device Speed Grade Support......................................................................................................................1-5 Release Information.....................................................................................................................................1-5 Getting Started With the 100G Interlaken IP Core............................................2-1 Licensing IP Cores....................................................................................................................................... 2-2 OpenCore Plus IP Evaluation........................................................................................................ 2-2 Specifying the 100G Interlaken IP Core Parameters and Options .......................................................2-3 Files Generated for Arria V GZ and Stratix V Variations......................................................................2-4 Files Generated for Arria 10 Variations....................................................................................................2-5 Simulating the 100G Interlaken IP Core.................................................................................................. 2-6 Integrating Your IP Core in Your Design................................................................................................ 2-6 Pin Assignments...............................................................................................................................2-6 Transceiver Logical Channel Numbering.....................................................................................2-7 Adding the Reconfiguration Controller..................................................................................... 2-11 Adding the External PLL.............................................................................................................. 2-13 Compiling the Full Design and Programming the FPGA....................................................................2-15 Creating a SignalTap II Debug File to Match Your Design Hierarchy ............................................. 2-15 100G Interlaken IP Core Parameter Settings..................................................... 3-1 Number of Lanes..........................................................................................................................................3-1 Meta Frame Length in Words.................................................................................................................... 3-2 Data Rate....................................................................................................................................................... 3-2 Transceiver Reference Clock Frequency...................................................................................................3-2 Include Advanced Error Reporting and Handling..................................................................................3-3 Enable M20K ECC Support........................................................................................................................3-4 Include Diagnostic Features....................................................................................................................... 3-4 Enable Native XCVR PHY ADME............................................................................................................3-5 Include In-Band Flow Control Block........................................................................................................3-5 Number of Calendar Pages......................................................................................................................... 3-6 TX Scrambler Seed.......................................................................................................................................3-6 Transfer Mode Selection............................................................................................................................. 3-6 Data Format..................................................................................................................................................3-7 Altera Corporation About This MegaCore Function TOC-3 Functional Description....................................................................................... 4-1 Interfaces Overview..................................................................................................................................... 4-1 Application Interface.......................................................................................................................4-1 Interlaken Interface..........................................................................................................................4-1 Out-of-Band Flow Control Interface.............................................................................................4-2 Management Interface.................................................................................................................... 4-2 Transceiver Control Interfaces.......................................................................................................4-2 High Level Block Diagram..........................................................................................................................4-4 Clocking and Reset Structure for IP Core................................................................................................ 4-4 100G Interlaken IP Core Clock Signals.........................................................................................4-5 IP Core Reset.................................................................................................................................... 4-5 IP Core Reset Sequence with the Reconfiguration Controller.................................................. 4-7 Interleaved and Packet Modes................................................................................................................... 4-7 Dual Segment Mode.................................................................................................................................... 4-8 M20K ECC Support...................................................................................................................................4-10 100G Interlaken IP Core Transmit Path.................................................................................................4-10 100G Interlaken IP Core Transmit User Data Interface Examples........................................ 4-10 100G Interlaken IP Core In-Band Calendar Bits on Transmit Side....................................... 4-17 100G Interlaken IP Core Transmit Path Blocks........................................................................ 4-18 100G Interlaken IP Core Receive Path....................................................................................................4-19 100G Interlaken IP Core Receive User Data Interface Examples........................................... 4-20 100G Interlaken IP Core RX Errored Packet Handling........................................................... 4-24 In-Band Calendar Bits on the 100G Interlaken IP Core Receiver User Data Interface....... 4-26 100G Interlaken IP Core Receive Path Blocks........................................................................... 4-27 100G Interlaken MegaCore Function Signals.....................................................5-1 100G Interlaken IP Core Clock Interface Signals....................................................................................5-1 100G Interlaken IP Core Reset Interface Signals.....................................................................................5-3 100G Interlaken IP Core User Data Transfer Interface Signals............................................................ 5-4 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals................................. 5-9 100G Interlaken IP Core Management Interface.................................................................................. 5-13 Device Dependent Signals........................................................................................................................ 5-14 Transceiver Reconfiguration Controller Interface Signals.......................................................5-15 Arria 10 External PLL Interface Signals......................................................................................5-15 Arria 10 Transceiver Reconfiguration Interface Signals.......................................................... 5-16 100G Interlaken IP Core Register Map...............................................................6-1 100G Interlaken IP Core Test Features.............................................................. 7-1 Internal Serial Loopback Mode..................................................................................................................7-1 External Loopback Mode............................................................................................................................7-2 PRBS Generation and Validation.............................................................................................................. 7-2 Setting up PRBS Mode in Arria V and Stratix V Devices.......................................................... 7-2 Setting up PRBS Mode in Arria 10 Devices..................................................................................7-4 Altera Corporation TOC-4 About This MegaCore Function CRC32 Error Injection ............................................................................................................................... 7-7 CRC24 Error Injection................................................................................................................................ 7-8 Advanced Parameter Settings............................................................................. 8-1 Hidden Parameters...................................................................................................................................... 8-1 Include Temp Sense.........................................................................................................................8-1 RXFIFO Address Width..................................................................................................................8-2 SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping).......................... 8-2 Modifying Hidden Parameter Values....................................................................................................... 8-3 Out-of-Band Flow Control in the 100G Interlaken MegaCore Function..........9-1 Out-of-Band Flow Control Block Clocks................................................................................................. 9-2 TX Out-of-Band Flow Control Signals..................................................................................................... 9-2 RX Out-of-Band Flow Control Signals..................................................................................................... 9-4 Performance and Fmax Requirements for 100G Ethernet Traffic....................A-1 Additional Information......................................................................................B-1 100G Interlaken MegaCore Function User Guide Archives................................................................. B-1 Document Revision History...................................................................................................................... B-1 How to Contact Altera................................................................................................................................B-5 Typographic Conventions..........................................................................................................................B-6 Altera Corporation 1 About This IP Core 2016.05.02 UG-01128 Send Feedback Subscribe Interlaken is a high-speed serial communication protocol for chip-to-chip packet transfers. The Altera (R) 100G Interlaken MegaCore function implements the Interlaken Protocol Specification, Revision 1.2 . It supports specific combinations of number of lanes (12 or 24) and lane rates from 6.25 gigabits per second (Gbps) to 12.5 Gbps, on Stratix(R) V, Arria(R) V GZ, and Arria 10 devices, providing raw bandwidth of 123.75 Gbps to 150 Gbps. (R) Interlaken provides low I/O count compared to earlier protocols, supporting scalability in both number of lanes and lane speed. Other key features include flow control, low overhead framing, and extensive integrity checking. The 100G Interlaken MegaCore function incorporates a physical coding sublayer (PCS), a physical media attachment (PMA), and a media access control (MAC) block. Figure 1-1: Typical Interlaken Application Traffic Management Packet Processing Ethernet MAC/Framer Interlaken FPGA/ ASIC Interlaken Up to 150 Gbps Interlaken FPGA/ ASIC Interlaken Switch Fabric Interlaken Up to 150 Gbps FPGA/ ASIC To Line Interface Related Information * 100G Interlaken MegaCore Function User Guide Archives on page 11-1 * Introduction to Altera IP Cores Provides general information about all Altera IP cores, including parameterizing, generating, upgrading, and simulating IP. * Creating Version-Independent IP and Qsys Simulation Scripts Create simulation scripts that do not require manual updates for software or IP version upgrades. * Project Management Best Practices Guidelines for efficient management and portability of your project and IP files. * Interlaken Protocol Specification, Revision 1.2 (c) 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 1-2 UG-01128 2016.05.02 Features * 100G Interlaken Example Design User Guide A demonstration hardware example design is available for Arria 10 IP core variations after you click Generate Example Design. Features The 100G Interlaken MegaCore function has the following features: * Compliant with the Interlaken Protocol Specification, Revision 1.2. * Supports 12 and 24 serial lanes in configurations that provide up to 150 Gbps raw bandwidth. * Supports per-lane data rates of 6.25, 10.3125, and 12.5 Gbps using Altera on-chip high-speed transceivers. * Supports dynamically configurable BurstMax and BurstMin values. * Supports Packet mode and Interleaved (Segmented) mode for user data transfer. * Supports dual segment mode for efficient user data transfer. * Supports up to 256 logical channels in out-of-the-box configuration. * Supports optional user-controlled in-band flow control with 1, 2, 4, 8, or 16 16-bit calendar pages. * Supports optional out-of-band flow control blocks. * Supports memory block ECC in Stratix V and Arria 10 devices. Related Information Interlaken Protocol Specification, Revision 1.2 IP Core Supported Combinations of Number of Lanes and Data Rate Table 1-1: 100G Interlaken IP Core Supported Combinations of Number of Lanes and Data Rate Yes indicates a supported combination. Lane Rate (Gbps) Number of Lanes 6.25 10.3125 12.5 12 -- Yes Yes 24 Yes -- -- IP Core Theoretical Raw Aggregate Bandwidth Table 1-2: 100G Interlaken IP Core Theoretical Raw Aggregate Bandwidth in Gbps Lane Rate (Gbps) Number of Lanes 12 Altera Corporation 6.25 10.3125 12.5 -- 123.75 150.00 About This IP Core Send Feedback UG-01128 2016.05.02 Device Family Support 1-3 Lane Rate (Gbps) Number of Lanes 24 6.25 10.3125 12.5 150.00 -- -- Device Family Support The following table lists the device support level definitions for Altera IP cores. Table 1-3: Altera IP Core Device Support Levels FPGA Device Families Preliminary support -- The core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution. Final support -- The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs. The following table shows the level of support offered by the 100G Interlaken MegaCore function for each Altera device family. Table 1-4: Device Family Support Device Family Support Stratix V (GS, GT, and GX) Final Arria V (GZ) Final Arria 10 Preliminary Other device families No support IP Core Verification Before releasing a version of the 100G Interlaken IP core, Altera runs comprehensive regression tests in the current version of the Quartus(R) Prime software. These tests use standalone methods. These files are tested in simulation and hardware to confirm functionality. Altera tests and verifies the 100G Interlaken IP core in hardware for different platforms and environments. Constrained random techniques generate appropriate stimulus for the functional verification of the IP core. Functional coverage metrics measure the quality of the random stimulus, and ensure that all important features are verified. About This IP Core Send Feedback Altera Corporation 1-4 UG-01128 2016.05.02 Performance and Resource Utilization Performance and Resource Utilization Table 1-5: 100G Interlaken MegaCore Function FPGA Resource Utilization Lists the resources and expected performance for selected variations of the 100G Interlaken IP core using the Quartus II software v13.1 and v13.1 Arria 10 edition releases for the following devices: * * * * Arria 10 device 10AX115S2F45I2SGES Arria V GZ device 5AGZE1H2F35I3 Stratix V GX device 5SGXMA7N2F45I3 Stratix V GT device 5SGTMC7K3F40I2 The results in this table do not include the out-of-band flow control block. The numbers of ALMs and logic registers are rounded up to the nearest 100. The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus II Fitter Report. Parameters Device Arria 10 Arria V GZ Stratix V GX Stratix V GT Numb er of Lanes PerLane Data Rate (Gbps) Resource Utilization ALMs Needed Logic Registers Primary M20K Blocks Secondary 12 10.3125 17500 34100 1800 38 12 12.500 17600 34100 1900 38 24 6.25 26100 48500 3200 38 12 10.3125 17300 34100 2500 38 12 10.3125 17200 34200 2300 38 24 6.250 25100 47600 3200 38 12 10.3125 17200 34200 2400 38 12 12.500 17300 34100 2600 38 24 6.250 2500 47600 3100 38 Related Information * Fitter Resources Reports in the Quartus Prime Help Information about Quartus Prime resource utilization reporting for 28-nm devices, including ALMs needed. * Quartus Prime Handbook, Volume 1: Design and Synthesis Includes information about how to apply the Speed setting. Altera Corporation About This IP Core Send Feedback UG-01128 2016.05.02 Device Speed Grade Support 1-5 Device Speed Grade Support Table 1-6: Minimum Recommended FPGA Fabric Speed Grades For each device family the 100G Interlaken IP core supports, Altera recommends that you configure the 100G Interlaken IP core only in the FPGA fabric speed grades listed in the table, and any faster (lower numbered) FPGA fabric speed grades that are available. Altera does not support configuration of this IP core in slower speed grades. IP Core Variation 12 Lanes Device Family 24 Lanes 10.3125 Gbps 12.5 Gbps 6.25 Gbps Arria 10 I2, E2 I2, E2 I2, E2 Arria V GZ I3, C3 -- I3, C3 Stratix V GX I3, C3 I2, C2 I3, C3 Stratix V GT I3, C3 I2, C2 I3, C3 Stratix V GS I3, C3 I2, C2 I3, C3 Related Information * Arria 10 Device Datasheet Provides information about Arria 10 transceiver speed grades for specific operating conditions. * Stratix V Device Datasheet Provides information about Stratix V transceiver speed grades for specific operating conditions. * Arria V Device Datasheet Provides information about Arria V GZ transceiver speed grades for specific operating conditions. Release Information Table 1-7: 100G Interlaken MegaCore Function Release Information Item Value Version 16.0 Release Date May 2016 Ordering Code IP-ILKN/100G Vendor ID 6AF7 About This IP Core Send Feedback Altera Corporation 1-6 UG-01128 2016.05.02 Release Information Item Product ID Value 00D6 Altera verifies that the current version of the Quartus Prime software compiles the previous version of each MegaCore function, if this MegaCore function was included in the previous release. Altera reports any exceptions to this verification in the Altera IP Release Notes or clarifies them in the Quartus Prime IP Update tool. Altera does not verify compilation with IP core versions older than the previous release. A 100G Interlaken IP core with optimized feature set or low resource utilization is available by request. Related Information Altera IP Release Notes Altera Corporation About This IP Core Send Feedback 2 Getting Started With the 100G Interlaken IP Core 2016.05.02 UG-01128 Subscribe Send Feedback The following sections explain how to install, parameterize, simulate, and initialize the 100G Interlaken IP core. Licensing IP Cores on page 2-2 The Altera(R) IP Library provides many useful IP core functions for your production use without purchasing an additional license. Specifying the 100G Interlaken IP Core Parameters and Options on page 2-3 The 100G Interlaken parameter editor allows you to quickly configure your custom IP variation. You specify IP core options and parameters in the Quartus Prime software. Files Generated for Arria V GZ and Stratix V Variations on page 2-4 Files Generated for Arria 10 Variations on page 2-5 Simulating the 100G Interlaken IP Core on page 2-6 Integrating Your IP Core in Your Design on page 2-6 Compiling the Full Design and Programming the FPGA on page 2-15 Creating a SignalTap II Debug File to Match Your Design Hierarchy on page 2-15 For Arria 10 devices, the Quartus Prime Standard Edition software generates two files, build_stp.tcl and <ip_core_name>.xml. You can use these files to generate a SignalTap(R) II file with probe points matching your design hierarchy. Related Information * Introduction to Altera IP Cores Provides general information about all Altera IP cores, including parameterizing, generating, upgrading, and simulating IP. * Creating Version-Independent IP and Qsys Simulation Scripts Create simulation scripts that do not require manual updates for software or IP version upgrades. * Project Management Best Practices Guidelines for efficient management and portability of your project and IP files. * 100G Interlaken Example Design User Guide A demonstration hardware example design is available for Arria 10 IP core variations after you click Generate Example Design. (c) 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 2-2 UG-01128 2016.05.02 Licensing IP Cores Licensing IP Cores The Altera(R) IP Library provides many useful IP core functions for your production use without purchasing an additional license. Some Altera MegaCore(R) IP functions require that you purchase a separate license for production use. However, the OpenCore(R) feature allows evaluation of any Altera IP core in simulation and compilation in the Quartus Prime software. After you are satisfied with functionality and performance, visit the Self Service Licensing Center to obtain a license number for any Altera product. Figure 2-1: IP Core Installation Path acds quartus - Contains the Quartus Prime software ip - Contains the Altera IP Library and third-party IP cores altera - Contains the Altera IP Library source code <IP core name> - Contains the IP core source files Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux the IP installation directory is <home directory>/altera/ <version number>. OpenCore Plus IP Evaluation Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and hardware before purchase. You only need to purchase a license for MegaCore IP cores if you decide to take your design to production. OpenCore Plus supports the following evaluations: * * * * Simulate the behavior of a licensed IP core in your system. Verify the functionality, size, and speed of the IP core quickly and easily. Generate time-limited device programming files for designs that include IP cores. Program a device with your IP core and verify your design in hardware. OpenCore Plus evaluation supports the following two operation modes: * Untethered--run the design containing the licensed IP for a limited time. * Tethered--run the design containing the licensed IP for a longer time or indefinitely. This requires a connection between your board and the host computer. Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times out. Related Information * Altera Licensing Site * Altera Software Installation and Licensing Manual Altera Corporation Getting Started With the 100G Interlaken IP Core Send Feedback UG-01128 2016.05.02 Specifying the 100G Interlaken IP Core Parameters and Options 2-3 Specifying the 100G Interlaken IP Core Parameters and Options The 100G Interlaken parameter editor allows you to quickly configure your custom IP variation. You specify IP core options and parameters in the Quartus Prime software. The 100G Interlaken IP core is not supported in Qsys. You must use the IP Catalog accessible from the Quartus Prime Tools menu. The 100G Interlaken IP core does not support VHDL simulation models. Altera recommends that you specify the Verilog HDL for both synthesis and simulation models. 1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears. 2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.qsys. Click OK. Note: For Arria V GZ and Stratix V variations, you are prompted to specify an IP variation file type. To generate the demonstration testbench and example design, you must select the Verilog HDL and specify the Verilog file extension (.v). 3. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to 100G Interlaken IP Core Parameter Settings for information about specific IP core parameters. * Specify parameters defining the IP core functionality, port configurations, and device-specific features. * Specify options for processing the IP core files in other EDA tools. 4. For Arria 10 variations, follow these steps: a. Click Generate HDL. The Generation dialog box appears. b. Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications. Note: To generate the demonstration testbench and example design, you must specify Verilog HDL for both synthesis and simulation models. c. Optionally, click the Generate Example Design button in the parameter editor to generate a testbench and a hardware example design that targets the Arria 10 Transceiver Signal Integrity Development Kit. d. Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in Project to add the file. 5. For Arria V GZ and Stratix V variations, follow these steps: a. Click Finish. The Generation dialog box appears. b. If you want to generate a demonstration testbench and example design for your IP core variation, turn on Generate example design. c. Click Generate. d. Click Exit. The parameter editor adds the top-level .qsys file to the current project automatically. If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in Project to add the file. 6. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports. Getting Started With the 100G Interlaken IP Core Send Feedback Altera Corporation 2-4 UG-01128 2016.05.02 Files Generated for Arria V GZ and Stratix V Variations Related Information * 100G Interlaken IP Core Parameter Settings on page 3-1 Details about the parameters available in the 100G Interlaken parameter editor. * Arria 10 GX Transceiver Signal Integrity Development Kit product page Files Generated for Arria V GZ and Stratix V Variations The Quartus Prime software generates multiple files during generation of your 100G Interlaken IP core Arria V GZ or Stratix V variation. Figure 2-2: IP Core Generated Files <Project Directory> <your_ip>.qip - Quartus Prime IP integration file <your_ip>.v - Top-level IP synthesis file <your_ip> - IP core synthesis files ilk_core.sv - HDL synthesis file ilk_core.sdc - Timing constraints file <your_ip>.bsf - Block symbol schematic file <your_ip>.cmp - VHDL component declaration file <your_ip>.sip - Lists files for simulation <your_ip>.spd - Combines individual simulation scripts <your_ip>_sim.f - Refers to simulation models and scripts <your_ip>_sim ilk_core ilk_core.sv - IPFS model <simulator_vendor> <simulator setup scripts> <your_ip>_testbench1 ilk_core ilk_100g testbench vlog.do Notes: 1. If example design is generated For 100G Interlaken IP cores that target a non-Arria 10 device, if you select the Verilog HDL for synthesis and simulation models and turn on Generate example design, the demonstration testbench and example design files are located in <your_ip>_testbench/ilk_core/testbench. Altera Corporation Getting Started With the 100G Interlaken IP Core Send Feedback UG-01128 2016.05.02 Files Generated for Arria 10 Variations 2-5 Files Generated for Arria 10 Variations The Quartus Prime software generates multiple files during generation of your 100G Interlaken IP core Arria 10 variation. Figure 2-3: IP Core Generated Files <project directory> <your_ip >.qsys - System or IP integration file <your_ip >.sopcinfo - Software tool-chain integration file <your_ip> <your_ip> n IP variation files IP variation files <your_ip >.cmp - VHDL component declaration file <your_ip >_bb.v - Verilog HDL black box EDA synthesis file <your_ip >_inst.v or .vhd - Sample instantiation template <your_ip >.ppf - XML I/O pin information file <your_ip >.qip - Lists IP synthesis files <your_ip >.sip - Lists files for simulation <your_ip >_generation.rpt <your_ip >.debuginfo - IP generation report - Contains post-generation information <your_ip >.html - Connection and memory map data <your_ip >.bsf - Block symbol schematic <your_ip >.spd - Combines individual simulation scripts sim ilk_core_<version> Subcore libraries synth IP synthesis files Simulation files <your_ip >.v Top-level simulation file <your_ip >.v Top-level IP synthesis file synth Subcore synthesis files <EDA tool name> Simulator scripts sim Subcore Simulation files <HDL files > <simulator_setup_scripts > <HDL files > In the Quartus Prime software v15.1 release, generating a 100G Interlaken IP core that targets an Arria 10 device does not generate a demonstration testbench. To generate the Verilog HDL testbench and example design files in this release, you must click the Generate Example Design button in the 100G Interlaken parameter editor. When you do so, you are prompted to specify the location of the Verilog HDL demonstration testbench and example design files. Getting Started With the 100G Interlaken IP Core Send Feedback Altera Corporation 2-6 Simulating the 100G Interlaken IP Core UG-01128 2016.05.02 Simulating the 100G Interlaken IP Core You can simulate your 100G Interlaken MegaCore function variation using any of the vendor-specific IEEE encrypted functional simulation models which are generated in the new <instance name>_sim or <instance name>/sim subdirectory of your project directory. The 100G Interlaken MegaCore function supports the Synopsys VCS, Cadence NC Sim, and Mentor Graphics Modelsim-SE simulators. The 100G Interlaken IP core generates only a Verilog HDL simulation model and testbench. The IP core parameter editor appears to offer you the option of generating a VHDL simulation model, but this IP core does not support a VHDL simulation model or testbench. For more information about functional simulation models for Altera IP cores, refer to the Simulating Altera Designs chapter in volume 3 of the Quartus Prime Handbook. For non-Arria 10 variations with Verilog HDL models, if you turn on Generate example design when you generate the IP core, the Quartus Prime software generates a testbench. This testbench demonstrates the resetting, clocking, and toggling of the 100G Interlaken IP core user interfaces in simulation. For Arria 10 variations, you can generate both this testbench and a hardware example design by clicking Generate Example Design in the 100G Interlaken parameter editor. Related Information * 100G Interlaken Example Design User Guide A demonstration hardware example design is available for Arria 10 IP core variations after you click Generate Example Design. * Simulating Altera Designs Integrating Your IP Core in Your Design After you generate your 100G Interlaken IP core variation, you can instantiate it in the RTL for your design. When you integrate your IP core instance in your design, you must pay attention to the following items. Pin Assignments When you integrate your 100G Interlaken MegaCore function instance in your design, you must make appropriate pin assignments. You do not need to specify pin assignments for simulation. However, you should make the pin assignments before you compile, to provide direction to the Quartus Prime Fitter and to specify the signals that should be assigned to device pins. You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready to map the design to hardware. Do not create virtual pins for clock or Interlaken link data signals. For the Arria 10 device family, you must configure a PLL external to the 100G Interlaken IP core. The required number of PLLs depends on the distribution of your Interlaken lane data pins in the different A10 transceiver blocks. Altera Corporation Getting Started With the 100G Interlaken IP Core Send Feedback UG-01128 2016.05.02 Transceiver Logical Channel Numbering 2-7 Related Information * Adding the External PLL on page 2-13 * Quartus Prime Help For information about the Quartus Prime software, including virtual pins. Transceiver Logical Channel Numbering In Arria V and Stratix V devices, logical channel numbering starts from zero. The logical channel numbering starts at the bottom of the die with logical channel 0 and continues in physical pin order through the four ordered transceiver blocks on the same side of the device. Each data channel and TX PLL has its own dedicated reconfiguration interface with an assigned logical channel. In Arria 10 devices, you control the mapping of Interlaken lanes directly in the Arria 10 Native PHY IP core that is included in the 100G Interlaken IP core. In Arria V and Stratix V devices, you can control the logical channel assignments in the IP core. You typically assign lanes to match the logical channel numbering. However, you can map the twelve Interlaken lanes in a 12-lane variation to any two adjacent transceiver blocks on the same side of the device. You can use the information in the following table to map the lanes to their default logical channel numbering. The logical channel numbering always starts at the bottom of a transceiver block. Table 2-1: Transceiver Logical Channel Numbering The default expected mapping of logical channels to Interlaken lanes in Arria V and Stratix V devices. Transceiver Block Number Logical Channel Number in Device 27 Getting Started With the 100G Interlaken IP Core Send Feedback Direction Interlaken Lane Number in IP Core TX PLL 3 Altera Corporation 2-8 UG-01128 2016.05.02 Transceiver Logical Channel Numbering Transceiver Block Number Logical Channel Number in Device 26 25 24 3 23 22 21 20 Altera Corporation Direction TX RX TX RX TX RX TX RX TX RX TX RX Interlaken Lane Number in IP Core 23 22 21 20 19 18 TX PLL 2 Getting Started With the 100G Interlaken IP Core Send Feedback UG-01128 2016.05.02 Transceiver Logical Channel Numbering Transceiver Block Number Logical Channel Number in Device 19 18 17 2 16 15 14 13 Getting Started With the 100G Interlaken IP Core Send Feedback Direction TX RX TX RX TX RX TX RX TX RX TX RX 2-9 Interlaken Lane Number in IP Core 17 16 15 14 13 12 TX PLL 1 Altera Corporation 2-10 UG-01128 2016.05.02 Transceiver Logical Channel Numbering Transceiver Block Number Logical Channel Number in Device 12 11 10 1 9 8 7 6 Altera Corporation Direction TX RX TX RX TX RX TX RX TX RX TX RX Interlaken Lane Number in IP Core 11 10 9 8 7 6 TX PLL 0 Getting Started With the 100G Interlaken IP Core Send Feedback UG-01128 2016.05.02 Adding the Reconfiguration Controller Transceiver Block Number Logical Channel Number in Device 5 4 3 0 2 1 0 Direction TX RX TX RX TX RX TX RX TX RX TX RX 2-11 Interlaken Lane Number in IP Core 5 4 3 2 1 0 For example, in an Arria V or Stratix V device, to change the VOD setting for lane 9, you write logical channel 10 to the Reconfiguration Controller. Related Information Altera Transceiver PHY IP User Guide Background information to better understand logical channel numbering. Adding the Reconfiguration Controller 100G Interlaken IP core variations that target an Arria V or a Stratix V device require an external reconfi guration controller to function correctly in hardware. 100G Interlaken IP core variations that target an Arria 10 device include a reconfiguration controller block and do not require an external reconfiguration controller. Keeping the Reconfiguration Controller external to the IP core in Arria V and Stratix V devices provides the flexibility to share the Reconfiguration Controller among multiple IP cores and to accommodate FPGA transceiver layouts based on the usage model of your application. In Arria 10 devices, you can configure individual transceiver channels flexibly through an Avalon-MM Arria 10 transceiver reconfigu ration interface. Getting Started With the 100G Interlaken IP Core Send Feedback Altera Corporation 2-12 UG-01128 2016.05.02 Generating the Reconfiguration Controller The following simple instructions show you how to instantiate an Altera Transceiver Reconfiguration Controller and how to connect the design blocks: Generating the Reconfiguration Controller You can use the IP Catalog to generate an Altera Transceiver Reconfiguration Controller. In the Transceiver Reconfiguration Controller parameter editor, you select the features of the transceiver that can be dynamically reconfigured. However, you must ensure that the following two features are turned on: 1. Enable PLL calibration 2. Enable Analog controls You must also set the value of the Number of reconfiguration interfaces parameter. Each TX PLL requires its own reconfiguration interface, whether or not you intend to reconfigure it. The following formula determines the correct number of reconfiguration interfaces: NUMBER_OF_RECONFIGURATION_INTERFACES = NUMBER_OF_LANES + NUMBER_OF_TX_PLLs where * NUMBER_OF_LANES is the total number of physical lanes used in your implemented design. * NUMBER_OF_TX_PLLs is the total number of transceiver blocks (number of TX PLLs) used in your design. For example, for a design that includes a 12-lane Interlaken variation that is configured in two transceiver blocks, you must set Number of reconfiguration interfaces to the value of 14. Connecting the Reconfiguration Controller to the IP Core The Reconfiguration Controller communicates with the 100G Interlaken IP core on two busses: * reconfig_to_xcvr (output) * reconfig_from_xcvr (input) Each of these busses connects to the bus of the same name in the 100G Interlaken IP core. You must also connect the following signals: * mgmt_clk_clk: Reconfiguration Controller clock (input) * mgmt_rst_reset: Reconfiguration Controller reset (input) * reconfig_busy: Reconfiguration Controller busy indication (output) Altera Corporation Getting Started With the 100G Interlaken IP Core Send Feedback UG-01128 2016.05.02 Adding the External PLL 2-13 Figure 2-4: Typical Connection of Reconfiguration Controller to 100G Interlaken IP Core mgmt_clk_clk mgmt_rst_reset reconfig_to_xcvr Reconfiguration Controller Avalon-MM IF reconfig_from_xcvr 100G Interlaken MegaCore Function reconfig_busy reset_n Altera recommends that you set the Reconfiguration Controller input clock frequency in the range of 100 MHz to 125 MHz. Refer to the Altera Transceiver PHY IP Core User Guide for frequency range require ments specific to the device family. The Reconfiguration Controller reset input should be asserted high during power up and remain asserted until its clock input becomes stable. Upon power up, the Reconfiguration Controller asserts reconfig_busy output high. The reconfig_busy signal remains asserted until the Reconfiguration Controller completes the configuration of all transceivers. Related Information Altera Transceiver PHY IP Core User Guide Adding the External PLL 100G Interlaken IP core variations that target an Arria 10 device require an external transceiver PLL to function correctly in hardware. 100G Interlaken IP core variations that target an Arria V or Stratix V device include the transceiver PLLs and do not require that you configure any additional PLLs. You can use the IP Catalog to generate an external PLL IP core that configures a TX PLL on the device. * Select Arria 10 Transceiver ATX PLL, Arria 10 Transceiver CMU PLL, or Arria 10 FPLL. * In the parameter editor, set the following parameter values: * PLL output frequency to one half the per-lane data rate of the IP core variation. The transceiver performs dual edge clocking, using both the rising and falling edges of the input clock from the PLL. Therefore, this PLL output frequency setting drives the transceiver with the correct clock for the Interlaken lanes. * PLL reference clock frequency to a frequency at which you can drive the TX PLL input reference clock. You must drive the external PLL reference clock input signal at the frequency you specify for this parameter. The number of external PLLs you must define depends on the distribution of your Interlaken TX serial lines across physical transceiver channels. You specify the clock network to which each PLL output connects by setting the clock network in the PLL parameter editor. Getting Started With the 100G Interlaken IP Core Send Feedback Altera Corporation 2-14 UG-01128 2016.05.02 Adding the External PLL You must connect the external PLL signals and the Arria 10 100G Interlaken IP core transceiver Tx PLL interface signals according to the following rules: * Connect the tx_serial_clk input pin for each Interlaken lane to the output port of the same name in the corresponding external PLL. * Connect the tx_pll_locked input pin of the 100G Interlaken IP core to the logical AND of the pll_locked output signals of the external PLLs for all of the Interlaken lanes and the inverse of each of the pll_cal_busy signals from the external PLLs. * Connect the tx_pll_powerdown output pin of the 100G Interlaken IP core to the pll_powerdown reset pin of the external PLLs for all of the Interlaken lanes. User logic must provide the AND function and connections. The following figure provides an example of one correct method, among many, to implement connection logic. You can also refer to the example design for example working user logic including one correct method to instantiate and connect an external PLL. Figure 2-5: Example Connection of ATX PLL with 100G Interlaken IP Core Using Arria 10 xN Clock Network 100G Interlaken IP Core (12 Lanes) tx_pll_powerdown tx_pll_locked ATX PLL tx_serial_clk pll_cal_busy pll_locked pll_powerdown tx_serial_clk[11] (Channel 5) (Lane 11) tx_serial_clk[10] (Channel 4) (Lane 10) tx_serial_clk[9] (Channel 3) (Lane 9) tx_serial_clk[8] (Channel 2) (Lane 8) tx_serial_clk[7] (Channel 1) (Lane 7) tx_serial_clk[6] (Channel 0) (Lane 6) Txvr Block N+1 tx_serial_clk[5] (Channel 5) (Lane 5) tx_serial_clk[4] (Channel 4) (Lane 4) tx_serial_clk[3] (Channel 3) (Lane 3) tx_serial_clk[2] (Channel 2) (Lane 2) tx_serial_clk[1] (Channel 1) (Lane 1) tx_serial_clk[0] (Channel 0) (Lane 0) Txvr Block N Related Information * Arria 10 External PLL Interface on page 4-3 * Pin Assignments on page 2-6 Altera Corporation Getting Started With the 100G Interlaken IP Core Send Feedback UG-01128 2016.05.02 Compiling the Full Design and Programming the FPGA 2-15 * Arria 10 External PLL Interface Signals on page 5-15 * Arria 10 Transceiver PHY User Guide Information about the correspondence between PLLs and transceiver channels, and information about how to configure an external PLL for your own design. You specify the clock network to which the PLL output connects by setting the clock network in the PLL parameter editor. Compiling the Full Design and Programming the FPGA You can use the Start Compilation command on the Processing menu in the Quartus Prime software to compile your design. After successfully compiling your design, program the targeted Altera device with the Programmer and verify the design in hardware. Related Information * Incremental Compilation for Hierarchical and Team-Based Design * Programming Altera Devices Creating a SignalTap II Debug File to Match Your Design Hierarchy For Arria 10 devices, the Quartus Prime Standard Edition software generates two files, build_stp.tcl and <ip_core_name>.xml. You can use these files to generate a SignalTap(R) II file with probe points matching your design hierarchy. The Quartus Prime software stores these files in the IP core Diretory/synth/debug/stp/ directory. Before you begin Synthesize your design using the Quartus Prime software. 1. To open the Tcl console, click View > Utility Windows > Tcl Console. 2. Type the following command in the Tcl console: source <IP core Directory>/synth/debug/stp/build_stp.tcl 3. To generate the STP file, type the following command: main -stp_file <output stp file name>.stp -xml_file <input xml_file name>.xml -mode build 4. To add this SignalTap II file (.stp) to your project, select Project > Add/Remove Files in Project. Then, compile your design. 5. To program the FPGA, click Tools > Programmer. 6. To start the SignalTap II Logic Analyzer, click Quartus Prime > Tools > SignalTap II Logic Analyzer. The software generation script may not assign the SignalTap II acquisition clock in <output stp file name>.stp. Consequently, the Quartus Prime software automatically creates a clock pin called auto_stp_external_clock. You may need to manually substitute the appropriate clock signal as the SignalTap II sampling clock for each STP instance. 7. Recompile your design. 8. To observe the state of your IP core, click Run Analysis. You may see signals or SignalTap II instances that are red, indicating they are not available in your design. In most cases, you can safely ignore these signals and instances.They are present because software generates wider buses and some instances that your design does not include. Getting Started With the 100G Interlaken IP Core Send Feedback Altera Corporation 3 100G Interlaken IP Core Parameter Settings 2016.05.02 UG-01128 Subscribe Send Feedback You customize the 100G Interlaken IP core by specifying parameters in the 100G Interlaken parameter editor, which you access from the Quartus Prime IP Catalog. This chapter describes the parameters and how they affect the behavior of the IP core. To customize your 100G Interlaken IP core, you can modify parameters to specify the following properties: Number of Lanes on page 3-1 Meta Frame Length in Words on page 3-2 Data Rate on page 3-2 Transceiver Reference Clock Frequency on page 3-2 Include Advanced Error Reporting and Handling on page 3-3 Enable M20K ECC Support on page 3-4 Include Diagnostic Features on page 3-4 Enable Native XCVR PHY ADME on page 3-5 Include In-Band Flow Control Block on page 3-5 Number of Calendar Pages on page 3-6 TX Scrambler Seed on page 3-6 Transfer Mode Selection on page 3-6 Data Format on page 3-7 Number of Lanes The Number of lanes parameter specifies the number of lanes available for Interlaken communication. The supported values are 12 and 24. The default value of the Number of lanes parameter is 12. The 100G Interlaken MegaCore function supports various combinations of number of lanes and lane rates. Ensure that your parameter settings specify a supported combination. (c) 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 3-2 UG-01128 2016.05.02 Meta Frame Length in Words Table 3-1: 100G Interlaken IP Core Supported Combinations of Number of Lanes and Data Rate Yes indicates a supported combination. Lane Rate (Gbps) Number of Lanes 6.25 10.3125 12.5 12 -- Yes Yes 24 Yes -- -- Meta Frame Length in Words The Meta frame length in words parameter specifies the length of the meta frame, in 64-bit (8-byte) words. In the Interlaken specification, this parameter is called the MetaFrameLength parameter. Smaller values for this parameter shorten the time to achieve lock. Larger values reduce overhead while transferring data, after lock is achieved. For simulation, you can set the Meta frame length in words parameter to the value of 128 for fast lane locking. For hardware testing, Altera recommends that you set the Meta frame length in words parameter to the value of 2048. The default value of the Meta frame length in words parameter is 2048. Data Rate The Data Rate parameter specifies the data rate on each lane. All lanes have the same data rate (lane rate). The default value of the Data Rate parameter is 10312.5 Mbps (10.3125 Gbps). The 100G Interlaken MegaCore function supports various combinations of number of lanes and lane rates. Ensure that your parameter settings specify a supported combination. Table 3-2: 100G Interlaken IP Core Supported Combinations of Number of Lanes and Data Rate Yes indicates a supported combination. Lane Rate (Gbps) Number of Lanes 6.25 10.3125 12.5 12 -- Yes Yes 24 Yes -- -- Transceiver Reference Clock Frequency The Transceiver reference clock frequency parameter specifies the expected frequency of the pll_ref_clk input clock. Altera Corporation 100G Interlaken IP Core Parameter Settings Send Feedback UG-01128 2016.05.02 Include Advanced Error Reporting and Handling 3-3 If the actual frequency of the pll_ref_clk input clock does not match the value you specify for this parameter, the design fails in both simulation and hardware. Table 3-3: 100G Interlaken IP Core Supported pll_ref_clk Frequencies The sets of valid frequencies vary with the per-lane data rate of the transceivers. Per-Lane Data Rate Valid pll_ref_clk Frequencies (MHz) 10.3125 206.25, 257.8125, 322.265625, 412.5, 515.625, 644.53125 12.5, 6.25 156.25, 195.3125, 250, 312.5, 390.625, 500, 625 The default value of the Transceiver reference clock frequency parameter is 412.5 MHz. Related Information * 100G Interlaken IP Core Clock Signals on page 4-5 * 100G Interlaken IP Core Clock Interface Signals on page 5-1 Include Advanced Error Reporting and Handling The Include advanced error reporting and handling parameter specifies whether your 100G Interlaken MegaCore function checks the integrity of incoming packets on the Interlaken link and reports the packet corruption errors it detects. If you turn on Include advanced error reporting and handling, the irx_err signal reflects CRC24 errors that are associated with data and control words in a burst. Some CRC24 errors might be an indication of one of the following conditions: * * * * Loss of lane alignment Illegal control word Illegal framing pattern Missing SOP or EOP indicator If you turn off Include advanced error reporting and handling, the value on the irx_err signal is not valid. If you turn it on, the irx_err signal is valid in clock cycles when irx_eob is asserted. Your IP core calculates and inserts CRC24 bits in outgoing Interlaken communication, and checks incoming Interlaken communication for CRC24 errors in the control, data, and Idle words, whether or not you turn on this parameter. The IP core reports these errors in real time on the crc24_err output signal. However, the IP core reports all CRC24 errors it encounters on this signal, whether or not it is able to associate them with a specific burst. The irx_err signal, if enabled, provides a better indication of the location of actual errors in incoming communication on the Interlaken link. If you turn this parameter on, your IP core reports certain incoming packet corruption errors, increasing system robustness. If you turn the parameter off your IP core has lower latency and requires fewer resources on the device. A checkmark in the check box to the left of the parameter turns this parameter on, specifying that the IP core include this feature. A check box with no checkmark indicates that the option is turned off, and the IP core does not include the feature. By default, the Include advanced error reporting and handling parameter is turned off. 100G Interlaken IP Core Parameter Settings Send Feedback Altera Corporation 3-4 UG-01128 2016.05.02 Enable M20K ECC Support Related Information 100G Interlaken IP Core RX Errored Packet Handling on page 4-24 Enable M20K ECC Support The Enable M20K ECC support parameter specifies whether your 100G Interlaken MegaCore function variation supports the ECC feature in the Stratix V and Arria 10 M20K memory blocks that are configured as part of the IP core. This parameter is relevant only for IP core variations that target a Stratix V device or an Arria 10 device. You can turn this parameter on to enable single-error correct, double-adjacent-error correct, and tripleadjacent-error detect ECC functionality in the M20K memory blocks configured in your IP core. You can turn this parameter off to decrease IP core latency and save resources on the device. If you turn on this feature, you enhance data reliability but increase latency and resource utilization. Without the ECC feature, a single M20K memory block can support a data path width of 40 bits. With the ECC feature, eight of those bits are dedicated to the ECC, and an M20K memory block can support a maximum data path width of 32 bits. Therefore, to support the same data bus width, the Quartus Prime Fitter must configure additional M20K blocks. The ECC check adds latency to the path through the memory block, and increases the amount of device memory used by your IP core. A checkmark in the check box to the left of the parameter turns this parameter on, specifying that the IP core supports this feature. A check box with no checkmark indicates that the option is turned off, and the IP core does not support this feature. By default, the Enable M20K ECC support parameter is turned off. Related Information * Embedded Memory Blocks in Stratix V Devices Information about the built-in ECC feature in Stratix V devices. * Embedded Memory Blocks in Arria 10 Devices Information about the built-in ECC feature in Arria 10 devices. Include Diagnostic Features The Include diagnostic features parameter enables the following diagnostic modes for initial board bring-up and for system testing in the factory and in the field: * * * * CRC error counters CRC32 error injection on the Interlaken link PRBS generation and checking Factory test features You can turn this parameter on to enable this IP core functionality, or turn it off to save resources on the device. If you turn this parameter on, you control the diagnostic modes by accessing 100G Interlaken IP core registers. A checkmark in the check box to the left of the parameter turns this parameter on, specifying that the IP core has this additional functionality. A check box with no checkmark indicates that the option is turned off, and the IP core does not have this functionality. By default, the Include diagnostic features parameter is turned off. Altera Corporation 100G Interlaken IP Core Parameter Settings Send Feedback UG-01128 2016.05.02 Enable Native XCVR PHY ADME 3-5 Related Information * PRBS Generation and Validation on page 7-2 * CRC32 Error Injection on page 7-7 * CRC24 Error Injection on page 7-8 Enable Native XCVR PHY ADME The Enable Native XCVR PHY ADME parameter specifies whether your Arria 10 100G Interlaken IP core variation supports the ADME feature. This parameter exposes debugging features of the Arria 10 Native PHY IP core that specifies the transceiver settings in the 100G Interlaken IP core. You can turn this parameter on to enable the following Arria 10 Native PHY IP core features: * * * * Enable Altera Debug Master Endpoint (ADME) Enable capability registers Enable prbs soft accumulators Enable odi acceleration logic A checkmark in the check box to the left of the parameter turns this parameter on. When the parameter is turned on, the IP core include these transceiver reconfiguration capabilities. A check box with no checkmark indicates that the option is turned off, and the IP core does not support these features. By default, the Enable native XCVR PHY ADME parameter is turned off. This parameter is available only for 100G Interlaken IP core variations that target an Arria 10 device. Related Information Arria 10 Transceiver PHY User Guide The Implementing Protocols in Arria 10 Transceivers chapter explains these Arria 10 Native PHY IP core parameters. Include In-Band Flow Control Block The Include in-band flow control functionality parameter specifies whether your 100G Interlaken MegaCore function includes an in-band flow control block. You can turn this parameter on to include in-band flow control functionality in your IP core, or turn it off to save resources on the device. If you turn on the parameter, you can specify the number of calendar pages the IP core supports. A checkmark in the check box to the left of the parameter turns this parameter on, specifying that the IP core include the in-band flow control block. A check box with no checkmark indicates that the option is turned off, and the IP core does not include an in-band flow control block. By default, the Include in-band flow control functionality parameter is turned off. Related Information * 100G Interlaken IP Core In-Band Calendar Bits on Transmit Side on page 4-17 * In-Band Calendar Bits on the 100G Interlaken IP Core Receiver User Data Interface on page 4-26 100G Interlaken IP Core Parameter Settings Send Feedback Altera Corporation 3-6 UG-01128 2016.05.02 Number of Calendar Pages Number of Calendar Pages When Include in-band flow control functionality is turned on, the Number of calendar pages parameter specifies the number of 16-bit pages of in-band flow control data that your 100G Interlaken MegaCore function supports. The supported values are 1, 2, 4, 8, and 16. Each 16-bit calendar page includes 16 in-band flow control bits. The application determines the interpre tation of the in-band flow control bits. The IP core supports a maximum of 256 channels with in-band flow control. If your design requires a different number of pages, select the lowest supported number of pages which is larger than the number required, and ignore any unused pages. For example, if your configuration requires three in-band flow control calendar pages, you can set Number of Calendar pages to 4 and use pages 3, 2, and 1 while ignoring page 0. The default value of the Number of calendar pages parameter is 1. TX Scrambler Seed The TX scrambler seed parameter specifies the initial scrambler state. If a single 100G Interlaken IP Core is configured on your device, you can use the default value of this parameter. If multiple 100G Interlaken IP Cores are configured on your device, you must use a different initial scrambler state for each IP core to reduce crosstalk. Try to select random values for each 100G Interlaken IP core, such that they have an approximately even mix of ones and zeros and differ from the other scramblers in multiple spread out bit positions. The default value of this parameter is 58'hdeadbeef123. Transfer Mode Selection The Transfer mode selection parameter specifies whether the 100G Interlaken transmitter expects incoming traffic to the TX user data transfer interface to be interleaved or packet based. The supported values are Interleaved and Packet. Interleaved mode is also called Segmented mode. The value of this parameter cannot be modified dynamically; it is determined when you generate the IP core. If the value of this parameter is Packet, the 100G Interlaken transmitter expects incoming traffic to the TX user data transfer interface to be packet based. This setting enables the internal enhanced scheduler and causes the IP core to send data on the Interlaken link based on the programmed BurstMax and BurstMin parameter settings. If the value of this parameter is Interleaved, the 100G Interlaken transmitter expects you to provide Start of Burst (SOB) and End of Burst (EOB) indications with the data on the TX user data transfer interface. In Interleaved mode, you can send either packet-based traffic or interleaved traffic, but you must provide the correct SOB and EOB signals even when sending non-interleaved packets. In this mode, the IP core does not implement the enhanced scheduler. The IP core ignores the BurstMax and BurstMin values. BurstShort is still in effect. To avoid overflowing the transmit FIFO, you should not send a burst that is longer than 1024 bytes. If packets are always sent contiguously in your application, Altera recommends that you set this parameter to the value of Packet. This setting enables simpler transfers on the user data transfer interface, and enables the 100G Interlaken IP core to perform enhanced scheduling based on the BurstMax and Altera Corporation 100G Interlaken IP Core Parameter Settings Send Feedback UG-01128 2016.05.02 Data Format 3-7 BurstMin settings. If the data bursts that arrive on the TX application interface might be interleaved between channels, then you must set Transfer mode selection to the value of Interleaved. The default value of the Transfer mode selection parameter is Interleaved. Related Information Interleaved and Packet Modes on page 4-7 Data Format The Data format parameter specifies whether the 100G Interlaken IP core opportunistically generates dual segment mode output to the RX user data transfer interface and handles dual segment mode input to the TX user data transfer interface. The supported parameter values are Single segment and Dual segment. This parameter affects both the RX user data transfer interface and the TX user data transfer interface. The 100G Interlaken IP core can accept dual segment input from the application on the TX user data transfer interface only if you specify the value of Dual segment for the Data format parameter. The default value of the Data format parameter is Single segment (single segment mode). Enabling the 100G Interlaken IP core to send dual segment mode output to the RX user data transfer interface improves bandwidth by decreasing idle bytes in outgoing communication. Likewise, enabling the IP core to receive dual segment mode input on the TX user data transfer interface improves system bandwidth by decreasing idle bytes in incoming communication. However, if you turn on this feature, you must ensure your application can process data sent in dual segment format. In addition, enabling dual segment mode configures more complex logic in the IP core, impacting resource utilization. Related Information Dual Segment Mode on page 4-8 100G Interlaken IP Core Parameter Settings Send Feedback Altera Corporation 4 Functional Description 2016.05.02 UG-01128 Subscribe Send Feedback The 100G Interlaken MegaCore function provides the functionality described in the Interlaken Protocol Specification, Revision 1.2. Related Information Interlaken Protocol Specification, Revision 1.2 Interfaces Overview The Altera 100G Interlaken MegaCore function supports the following interfaces: Application Interface on page 4-1 Interlaken Interface on page 4-1 Out-of-Band Flow Control Interface on page 4-2 Management Interface on page 4-2 Transceiver Control Interfaces on page 4-2 Application Interface The application interface, also called the user data transfer interface, provides up to 256 channels of communication to and from the Interlaken link. Related Information * High Level Block Diagram on page 4-4 The figure lists the major application interface signals. * 100G Interlaken IP Core User Data Transfer Interface Signals on page 5-4 Comprehensive list of application interface signals and information about required signal behavior. Interlaken Interface The Interlaken interface complies with the Interlaken Protocol Specification, Revision 1.2. It provides a high-speed transceiver interface to an Interlaken link. 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. (c) www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 4-2 UG-01128 2016.05.02 OutofBand Flow Control Interface The 100G Interlaken MegaCore function value for the Interlaken BurstMax parameter is determined by the value you specify on the burst_max_in input signal. The 100G Interlaken MegaCore function supports three values for BurstMax, 128 bytes, 256, and 512 bytes. Note: You should only modify the value of the burst_max_in signal when no traffic is present. You can configure your 100G Interlaken MegaCore function to use 1, 2, 4, 8, or 16 pages of 16 calendar bits. The application determines the use of the in-band flow control bits that the MegaCore function receives on the incoming Interlaken link, and the application is responsible for specifying the values of the in-band flow control bits the MegaCore function transmits on the outgoing Interlaken link. Related Information * 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals on page 5-9 Information about setting the BurstMax and BurstShort values, including the encoding of your desired value on the burst_max_in or burst_short_in input signal. * 100G Interlaken IP Core User Data Transfer Interface Signals on page 5-4 Information about the in-band flow control signals that you control and view on the application interface. * Interlaken Protocol Specification, Revision 1.2 Available from the Interlaken Alliance web site at www.interlakenalliance.com. OutofBand Flow Control Interface The optional out-of-band flow control interface conforms to the out-of-band requirements in Section 5.3.4.2, Out-of-Band Flow Control, of the Interlaken Protocol Specification, Revision 1.2. Related Information * Out-of-Band Flow Control in the 100G Interlaken MegaCore Function on page 9-1 * Interlaken Protocol Specification, Revision 1.2 Available from the Interlaken Alliance web site at www.interlakenalliance.com. Management Interface The management interface provides access to the 100G Interlaken IP core internal status and control registers. This interface does not provide access to the hard PCS registers on the device. The management interface complies with the Avalon Memory-Mapped (Avalon-MM) specification defined in the Avalon Interface Specifications. Related Information Avalon Interface Specifications Transceiver Control Interfaces The 100G Interlaken IP core provides several interfaces to control the transceiver. The transceiver control interfaces in your 100G Interlaken IP core variation depend on the device family the variation targets. The 100G Interlaken IP core supports the following transceiver control interfaces: Transceiver Reconfiguration Controller Interface on page 4-3 Arria 10 External PLL Interface on page 4-3 Altera Corporation Functional Description Send Feedback UG-01128 2016.05.02 Transceiver Reconfiguration Controller Interface 4-3 Arria 10 Transceiver Reconfiguration Interface on page 4-3 Transceiver Reconfiguration Controller Interface 100G Interlaken IP core variations that target an Arria V or a Stratix V device require an external reconfi guration controller to function correctly in hardware. 100G Interlaken IP core variations that target an Arria 10 device include a reconfiguration controller block and do not require an external reconfiguration controller. Related Information Altera Transceiver PHY IP Core User Guide Describes the Altera Transceiver Reconfiguration Controller and the signals that connect to the 100G Interlaken IP core transceiver reconfiguration controller interface. Arria 10 External PLL Interface 100G Interlaken IP core variations that target an Arria 10 device require an external transceiver PLL to function correctly in hardware. 100G Interlaken IP core variations that target an Arria V or Stratix V device include the transceiver PLLs and do not require that you configure any additional PLLs. Related Information * Adding the External PLL on page 2-13 Describes how to generate an external TX PLL, including parameter requirements. * Arria 10 External PLL Interface Signals on page 5-15 * Arria 10 Transceiver PHY User Guide Information about the Arria 10 transceiver PLLs and clock network. Arria 10 Transceiver Reconfiguration Interface The Arria 10 transceiver reconfiguration interface provides access to the registers in the embedded Arria 10 Native PHY IP core. This interface provides direct access to the hard PCS registers on the device. This interface is available only in variations that target an Arria 10 device. In variations that target an Arria V device or a Stratix V device, user logic reconfigures the transceivers through the transceiver reconfiguration controller, an external block that you must instantiate in your design outside the 100G Interlaken IP core. The Arria 10 transceiver reconfiguration interface complies with the Avalon Memory-Mapped (AvalonMM) specification defined in the Avalon Interface Specifications. Related Information * Avalon Interface Specifications Defines the Avalon Memory-Mapped (Avalon-MM) specification. * Arria 10 Transceiver PHY User Guide Information about the Arria 10 transceiver reconfiguration interface. * Arria 10 Transceiver Registers Information about the Arria 10 transceiver registers. Functional Description Send Feedback Altera Corporation 4-4 UG-01128 2016.05.02 High Level Block Diagram High Level Block Diagram Figure 4-1: 100G Interlaken Block Diagram tx_usr_clk itx_chan[7:0] itx_num_valid[7:0] itx_sob[1:0] itx_eob itx_sop[1:0] itx_eopbits[3:0] itx_din_words[511:0] itx_calendar[16 x n - 1:0] tx_mac_clk TX Transmit Buffer TX MAC clk_tx_common TX PCS TX PMA tx_pin[m - 1:0] itx_ready irx_chan[7:0] irx_num_valid[7:0] irx_sob[1:0] irx_eob irx_sop[1:0] irx_eopbits[3:0] irx_dout_words[511:0] irx_calendar[16 x n - 1:0] irx_err Transceiver Blocks RX Regroup rx_usr_clk RX MAC rx_mac_clk RX PCS RX PMA rx_pin[m - 1:0] clk_rx_common The 100G Interlaken MegaCore function consists of two paths: an Interlaken TX path and an Interlaken RX path. Each path includes MAC, PCS, and PMA blocks. The PCS blocks are implemented in hard IP. Related Information * 100G Interlaken IP Core Transmit Path Blocks on page 4-18 For more information about the Interlaken TX path. * 100G Interlaken IP Core Receive Path Blocks on page 4-27 For more information about the Interlaken RX path. Clocking and Reset Structure for IP Core The following topics describe the clocking and reset structure of the 100G Interlaken IP core: 100G Interlaken IP Core Clock Signals on page 4-5 IP Core Reset on page 4-5 IP Core Reset Sequence with the Reconfiguration Controller on page 4-7 Altera Corporation Functional Description Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core Clock Signals 4-5 100G Interlaken IP Core Clock Signals Table 4-1: 100G Interlaken IP Core Clocks Clock Name Description pll_ref_clk Reference clock for the RX CDR PLL in IP core variations that target an Arria 10 device. Reference clock for the RX CDR PLL and the TX transceiver PLL in all other variations. tx_serial_clk[NUM_LANES-1:0] Clocks for the individual transceiver channels in 100G Interlaken IP core variations that target an Arria 10 device. rx_usr_clk Clock for the receive application interface. tx_usr_clk Clock for the transmit application interface. mm_clk Management clock for 100G Interlaken IP core register access. reconfig_clk Management clock for Arria 10 hard PCS register access, including access for Arria 10 transceiver reconfiguration and testing features. If you choose to instantiate the optional out-of-band flow control blocks, your 100G Interlaken MegaCore function has additional clock domains. Related Information * Out-of-Band Flow Control Block Clocks on page 9-2 Comprehensive list of out-of-band flow control block clocks and information about their expected frequencies. * 100G Interlaken IP Core Clock Interface Signals on page 5-1 Lists the recommended and required frequencies of the 100G Interlaken IP core clocks. IP Core Reset The 100G Interlaken IP core variations have a single asynchronous reset, the reset_n signal. The 100G Interlaken IP core manages the initialization sequence internally. After you de-assert reset_n (raise it after asserting it low), the IP core automatically goes through the entire reset sequence. Note: Altera recommends that you hold the reset_n signal low for at least the duration of two mm_clk cycles, to ensure the reset sequence proceeds correctly. Functional Description Send Feedback Altera Corporation 4-6 IP Core Reset UG-01128 2016.05.02 Figure 4-2: 100G Interlaken IP Core Transceiver Initialization Sequence The internal initialization sequence implemented by the reset controller included in the 100G Interlaken IP core. In Arria 10 devices, the pll_locked signal originates in the external PLL. In other devices, it originates in the 100G Interlaken IP core itself. reset_n pll_pdn pll_locked tx_digital_rst rx_analog_rst rx_is_lockedtodata rx_digital_rst tx_usr_srst rx_usr_srst Following completion of the reset sequence internally, the 100G Interlaken IP core begins link initializa tion. If your 100G Interlaken IP core and its Interlaken link partner initialize the link successfully, you can observe the assertion of the lane and link status signals according to the Interlaken specification. For example, you can monitor the tx_lanes_aligned, sync_locked, word_locked, and rx_lanes_aligned output status signals. In Arria V GZ and Stratix V devices, after you de-assert the reset_n signal, you must wait a certain number of mm_clk cycles before you can successfully access the 100G Interlaken IP core registers using the IP core management interface. * In hardware, you must wait 220 mm_clk cycles. * In simulation, you must wait 26 mm_clk cycles. In Arria 10 devices, the required wait time from de-asserting the reset_n signal to safely accessing the IP core registers is a function of the internal reset controller. The IP core instantiates an Altera Transceiver PHY Reset Controller in Arria 10 variations. Altera Corporation Functional Description Send Feedback UG-01128 2016.05.02 IP Core Reset Sequence with the Reconfiguration Controller 4-7 Related Information * IP Core Reset Sequence with the Reconfiguration Controller on page 4-7 You must wait until the required Altera Transceiver Reconfiguration Controller completes configura tion of the transceivers before you assert the reset_n signal. * Arria 10 Transceiver PHY User Guide For more information about the Altera Transceiver PHY Reset Controller that is included in Arria 10 variations of the 100G Interlaken IP core, refer to the Transceiver Reset Control in Arria 10 Devices chapter. IP Core Reset Sequence with the Reconfiguration Controller If your 100G Interlaken IP core targets an Arria V device or a Stratix V device, you must connect the 100G Interlaken IP core to an Altera Reconfiguration Controller. At power up, the Reconfiguration Controller configures the transceivers. After power up, upon completion of the transceiver configuration process, the Reconfiguration Controller returns control of the reset to your application. You must wait until the Reconfiguration Controller completes configuration of the transceivers before you assert the reset_n signal. The Reconfiguration Controller indicates the end of the configuration cycle by deasserting the reconfig_busy signal. After reconfig_busy is deasserted, you can assert reset_n. Altera recommends that you hold the reset_n signal low for at least the duration of two mm_clk cycles, to ensure the reset sequence proceeds correctly. Figure 4-3: Reset Sequence With the Reconfiguration Controller Indicates when you can safely assert the reset_n signal of the 100G Interlaken MegaCore IP core. mgmt_clk_locked (*) mgmt_rst_reset reconfig_busy reset_n You must wait at least 223 mm_clk cycles (or 29 mm_clk cycles in simulation) after the mgmt_clk locks before you deassert the mgmt_rst_reset input signal to the reconfiguration controller. Related Information Altera Transceiver PHY IP Core User Guide For more information about the Altera Reconfiguration Controller. Interleaved and Packet Modes You can configure the 100G Interlaken IP core to accept interleaved data transfers from the application on the TX user data transfer interface, or to not accept interleaved data transfers on this interface. If the IP core can accept interleaved data transfers, it is in Interleaved mode, sometimes also called Segmented mode. If the IP core does not accept interleaved data transfers, it is in Packet mode. The value you specify Functional Description Send Feedback Altera Corporation 4-8 Dual Segment Mode UG-01128 2016.05.02 for the Transfer mode selection parameter in the 100G Interlaken parameter editor determines the IP core transmit mode. In Packet mode, the 100G Interlaken IP Core performs Optional Scheduling Enhancement based on Section 5.3.2.1.1 of the Interlaken Protocol Specification, Revision 1.2. The IP core ignores the itx_sob and itx_eob signals. Instead, the IP core performs optional enhanced scheduling based on the settings of BurstMax, BurstMin, and BurstShort. In Interleaved mode, the 100G Interlaken IP Core inserts burst control words on the Interlaken link based on the itx_sob and itx_eob inputs. The internal optional enhanced scheduling is disabled and the BurstMax and BurstMin values are ignored. BurstShort is still in effect. To avoid overflowing the transmit FIFO, you should not send a burst that is longer than 1024 bytes. In Interleaved mode or in Packet mode, the 100G Interlaken IP core is capable of accepting noninterleaved data on the TX user data transfer interface (itx_din_words). However, if the IP core is in Interleaved mode, the application must drive the itx_sob and itx_eob inputs correctly. In Interleaved mode or in Packet mode, the 100G Interlaken IP core can generate interleaved data transfers on the RX user data transfer interface (irx_dout_words). The application must be able to accept interleaved data transfers if the Interlaken link partner transmits them on the Interlaken link. In this case, the Interlaken link partner must send traffic in Interleaved mode that conforms with the 100G Interlaken IP core BurstShort value. Note: Altera recommends that the transmitter (link partner) only send packets with a minimum packet size of 64 bytes. Related Information * Transfer Mode Selection on page 3-6 * 100G Interlaken IP Core User Data Transfer Interface Signals on page 5-4 * Interlaken Protocol Specification, Revision 1.2 Dual Segment Mode In dual segment mode, the 100G Interlaken IP core can minimize wasted bandwidth on the user data transfer interface by starting a packet transfer at Byte 31 (Word 3) of the data bus (irx_dout_words[511:0]), if the previous packet ended with four or fewer 64-bit words transferred in the current rx_usr_clk cycle. In dual segment mode, the IP core is capable of accepting dual segment input on the TX user data transfer interface (itx_din_words[511:0]). However, the application can control IP core input signals to specify that the current incoming data transfer does not use dual segment mode. In addition, if you tie the relevant input signals (itx_sob[0], itx_sop[0], and itx_num_valid[3:0]) permanently low in your design, the Quartus Prime Fitter compiles away the IP core logic that generates dual segment output from the IP core. Altera Corporation Functional Description Send Feedback UG-01128 2016.05.02 Dual Segment Mode 4-9 You must enforce the following additional constraints in sending dual segment traffic to the TX user data transfer interface: * The application can start a packet or burst transfer in a single cycle on only one of the most significant byte (Byte 63) or the middle position (Byte 31) in the 512-bit data symbol. Therefore, the application can assert only one of itx_sop[1] and itx_sop[0], and only one of itx_sob[1] and itx_sob[0], in a given cycle. This constraint ensures that the minimum number of idle and data bytes between consecutive starts of packet or burst is at least 64. * The application can end a packet or burst transfer only once in a single cycle. Therefore, the minimum number of idle and data bytes between consecutive ends of packet or burst must be at least 64. The same constraints apply to dual segment traffic on the RX user data transfer interface: the minimum number of idle and data bytes between consecutive starts of packet or burst must be at least 64, and the minimum number of idle and data bytes between consecutive ends of packet or burst must be at least 64. The 100G Interlaken IP core enforces these constraints on the RX user data transfer interface. Figure 4-4: Dual Segment Data Transfer In a dual segment data transfer, the end of one data burst and the start of another can appear in the same clock cycle. In this example, each column represents a single 512-bit data symbol, divided into 64-bit words, and each color represents a separate data burst. The second and third data bursts are dual segment transfers. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Eight-word data symbol:: Word 7 (bits [511:448]) dw0 Word 6 (bits [447:384]) dw8 dw4 dw12 dw20 dw4 dw1 dw5 dw13 dw21 dw5 Word 5 (bits [383:320]) Word 4 (bits [319:256]) dw2 dw6 dw14 dw22 dw6 dw3 dw7 dw15 dw23 dw7 Word 3 (bits [255:192]) dw4 dw0 dw8 dw16 dw0 dw8 Word 2 (bits [191:128]) Word 1 (bits [127:64]) dw5 dw1 dw9 dw17 dw1 dw6 dw2 dw10 dw18 dw2 Word 0 (bits [63:0]) dw7 dw3 dw11 dw19 dw3 Related Information * Data Format on page 3-7 * 100G Interlaken IP Core User Data Transfer Interface Signals on page 5-4 * 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Transmit Example on page 415 Example of dual segment data transfers on the TX user data transfer interface. * 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Receive Example on page 4-22 Example of dual segment data transfers on the RX user data transfer interface. Functional Description Send Feedback Altera Corporation 4-10 UG-01128 2016.05.02 M20K ECC Support M20K ECC Support If you turn on Enable M20K ECC support in your Stratix V or Arria 10 100G Interlaken IP core variation, the IP core takes advantage of the built-in device support for ECC checking in all M20K blocks configured in the IP core on the device. The feature performs single-error correct, double-adjacent-error correct, and triple-adjacent-error detect ECC functionality in the M20K memory blocks configured in your IP core. The IP core reports ECC error statistics in the registers CNT_ERR_TX, CNT_UNCOR_TX, CNT_ERR_RX, and CNT_UNCOR_RX at offsets 0x122 through 0x125. This feature enhances data reliability but increases latency and resource utilization. Without the ECC feature, a single M20K memory block can support a data path width of 40 bits. With the ECC feature, eight of those bits are dedicated to the ECC, and an M20K memory block can support a maximum data path width of 32 bits. Therefore, when M20K ECC support is turned on the IP core configures additional M20K memory blocks. The ECC check adds latency to the path through the memory block, and increases the amount of device memory used by your IP core. Related Information * Enable M20K ECC Support on page 3-4 * 100G Interlaken IP Core Register Map on page 6-1 Describes the CNT_ERR_TX, CNT_UNCOR_TX, CNT_ERR_RX, and CNT_UNCOR_RX 100G Interlaken IP core M20K ECC status registers. * Embedded Memory Blocks in Stratix V Devices Information about the built-in ECC feature in Stratix V devices. * Embedded Memory Blocks in Arria 10 Devices Information about the built-in ECC feature in Arria 10 devices. 100G Interlaken IP Core Transmit Path The 100G Interlaken MegaCore function accepts application data from up to 256 channels and combines it into a single data stream in which data is labeled with its source channel. The 100G Interlaken TX MAC and PCS blocks format the data into protocol-compliant bursts and insert Idle words where required. 100G Interlaken IP Core Transmit User Data Interface Examples The following examples illustrate how to use the Altera 100G Interlaken IP core TX user data interface: 100G Interlaken IP Core Interleaved Mode (Segmented Mode) Example on page 4-10 100G Interlaken IP Core Packet Mode Operation Example on page 4-12 100G Interlaken IP Core Back-Pressured Packet Transfer Example on page 4-13 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Transmit Example on page 4-15 100G Interlaken IP Core Interleaved Mode (Segmented Mode) Example In Interleaved Mode, you are responsible for scheduling the burst. You need to drive an extra pair of signals, Start of Burst (SOB) and End of Burst (EOB), to indicate the burst boundary. You can send the traffic in packet order or interleaved order, as long as you set the SOB and EOB flags correctly to establish the data boundaries. Altera Corporation Functional Description Send Feedback UG-01128 2016.05.02 4-11 100G Interlaken IP Core Interleaved Mode (Segmented Mode) Example Figure 4-5: Packet Transfer on Transmit Interface in Interleaved Single Segment Mode This example illustrates the expected behavior of the 100G Interlaken IP core application interface transmit signals during data transfers from the application to the IP core on the TX user data transfer interface in interleaved, single segment mode. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 tx_usr_clk itx_sop[1] itx_chan 8'h2 8'h4 8'h2 8'h3 8'h4 d4 d5 d6 d7 itx_sob[1] itx_eob d1 d2 d3 itx_num_valid[7:4] 4'b1000 4'b1000 4'b0011 4'b0000 4'b1000 4'b1000 4'b1000 4'b0010 itx_eopbits 4'b0000 4'b1011 4'b0000 4'b0000 4'b0000 4'b0000 4'b1011 itx_din_words The figure shows the timing diagram for an interleaved data transfer in Interleaved mode. In cycle 1, the application asserts itx_sop[1] and itx_sob[1], indicating that this cycle is both the start of the burst and the start of the packet. The value the application drives on itx_chan indicates the data originates from channel 2. In cycle 2, the application asserts itx_eob, indicating the data the application transfers to the IP core in this clock cycle is the end of the burst. (itx_chan only needs to be valid when itx_sob[1] or itx_sop[1] is asserted). itx_num_valid[7:4] indicates all eight words are valid. However, the data in this cycle is not end of packet data. The application is expected to transfer at least one additional data burst in this packet, possibly interleaved with one or more bursts in packets from different data channels. Cycle 3 is a short burst with both itx_sob[1] and itx_eob asserted. The application drives the value of three on itx_num_valid[7:4] to indicate that three words of the eight-word itx_din_words data bus are valid. The data is packed in the most significant words of itx_din_words.The application drives the value of 4'b1011 on itx_eopbits to indicate that the data the application transfers to the IP core in this cycle are the final words of the packet, and that in the final word of the packet, only three bytes are valid data. The value the application drives on itx_chan indicates this burst originates from channel 4. In cycle 4, the itx_num_valid[7:4] signal has the value of zero, which means this cycle is an idle cycle. In cycle 5, the application sends another single-cycle data burst from channel 2, by asserting itx_sob[1] and itx_eob to indicate this data is both the start and end of the burst. The application does not assert itx_sop[1], because this burst is not start of packet data. itx_eopbits has the value of 4'b0000, indicating this burst is also not end of packet data. This data follows the data burst transfered in cycles 1 and 2, within the same packet from channel 2. In cycle 6, the application sends a start of packet, single-cycle data burst from channel 3. In cycles 7 and 8, the application sends a two-cycle data packet in one two-cycle burst. In cycle 8, the second data cycle, the application drives the value of two on itx_num_valid[7:4] and the value of 4'b1011 on itx_eopbits, to tell the IP core that in this clock cycle, the two most significant words of the Functional Description Send Feedback Altera Corporation 4-12 UG-01128 2016.05.02 100G Interlaken IP Core Packet Mode Operation Example data symbol contain valid data and the remaining words do not contain valid data, and that in the second of these two words, only the three most significant bytes contain valid data. In Interleaved Mode, you can transfer a packet without interleaving as long as the channel number does not toggle during the same packet transfer. However, you must still assert the itx_sob and itx_eob signals correctly to maintain the proper burst boundaries. If you do not drive the itx_sob and itx_eob signals, the 100G Interlaken IP Core does not operate properly and the transmit FIFO may overflow, since in this mode the internal logic is looking for itx_sob and itx_eob assertion for insertion of proper burst control words. 100G Interlaken IP Core Packet Mode Operation Example Figure 4-6: Packet Transfer on Transmit Interface in Packet Mode This example illustrates the expected behavior of the 100G Interlaken IP core application interface transmit signals during a packet transfer in single segment packet mode. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 tx_usr_clk itx_sop[1] itx_chan 8'h2 itx_sob[1] itx_eob d1 d2 d3 itx_num_valid[7:4] 4'b1000 4'b1000 4'b0111 itx_eopbits 4'b0000 itx_din_words 4'b1011 itx_ready itx_calendar 64'hffff_ffff_ffff_ffff 64'h1111_2222_3333_4444 The figure illustrates a packet mode data transfer of 179 bytes on the transmit interface into the IP core. In this mode, the 100G Interlaken IP core ignores the itx_sob and itx_eob input signals. To start a transfer, you assert itx_sop[1] when you have data ready on itx_din_words. At the following rising edge of the clock, the IP core detects that itx_sop[1] is asserted, indicating that the value on itx_din_words in the current cycle is the start of an incoming data packet. When you assert itx_sop[1], you must also assert the correct value on itx_chan to tell the IP core the data channel source of the data. In this example, the value 2 on itx_chan tells the IP core that the data originates from channel number 2. Altera Corporation Functional Description Send Feedback UG-01128 2016.05.02 4-13 100G Interlaken IP Core Back-Pressured Packet Transfer Example During the SOP cycle (labeled with data value d1) and the cycle that follows the SOP cycle (labeled with data value d2), you must hold the value of itx_num_valid[7:4] at 4'b1000. In the following clock cycle, labeled with data value d3, you must hold the following values on critical input signals to the IP core: * itx_num_valid[7:4] at the value of 4'b0111 to indicate the current data symbol contains seven 64-bit words of valid data. * itx_eopbits[3] high to indicate the current cycle is an EOP cycle. * itx_eopbits[2:0] at the value of 3'b011 to indicate that only three bytes of the final valid data word are valid data bytes. This signal behavior correctly transfers a data packet with the total packet length of 179 bytes to the IP core, as follows: * In the SOP cycle, the IP core receives 64 bytes of valid data (d1). * In the following clock cycle, the IP core receives another 64 bytes of valid data (d2). * In the third clock cycle, the EOP cycle, the IP core receives six full words (6 x 8 = 48 bytes) and three bytes of valid data, for a total of 51 valid bytes. The total packet length is 64 + 64 + 51 = 179 bytes. 100G Interlaken IP Core Back-Pressured Packet Transfer Example Figure 4-7: Packet Transfer on Transmit Interface with Back Pressure This example illustrates the expected behavior of the 100G Interlaken application interface transmit signals during a packet transfer with back pressure. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 tx_usr_clk itx_sop[1] itx_chan 8'h2 itx_sob[1] itx_eob d1 d2 d3 itx_num_valid[7:4] 4'b1000 4'b1000 4'b1000 itx_eopbits 4'b0000 itx_din_words d4 4'b0000 4'b1000 itx_ready itx_calendar 64'hffff_ffff_ffff_ffff 64'h1111_2222_3333_4444 In this example, the 100G Interlaken IP Core accepts the first four data symbols (256 bytes) of a data packet. The clock cycles in which the application transfers the data values d2 and d3 to the 100G Interlaken IP Core are grace-period cycles following the 100G Interlaken IP Core's de-assertion of itx_ready. The 100G Interlaken IP Core supports up to 4 cycles of grace period, enabling you to register the input data and control signals, as well as the itx_ready signal, without changing functionality. The grace period Functional Description Send Feedback Altera Corporation 4-14 100G Interlaken IP Core Back-Pressured Packet Transfer Example UG-01128 2016.05.02 supports your design in achieving timing closure more easily. In any case you must ensure that you hold itx_num_valid at the value of 0 when you are not driving data. You can think of this interface as a FIFO write interface. When itx_num_valid[7:4] is nonzero, both data and control information (including itx_num_valid[7:4] itself) are written to the transmit side data interface. The itx_ready signal is the inverse of a hypothetical FIFO-almost-full flag. When itx_ready is high, the 100G Interlaken IP Core is ready to accept data. When itx_ready is low, you can continue to send data for another 6 to 8 clock cycles of tx_usr_clk. Related Information 100G Interlaken IP Core In-Band Calendar Bits on Transmit Side on page 4-17 Description of in-band calendar bits on the TX user data transfer interface. Altera Corporation Functional Description Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Transmit... 4-15 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Transmit Example Figure 4-8: Dual Segment Data Transfer on Transmit Interface in Interleaved Mode This example illustrates the expected behavior of the 100G Interlaken IP core application interface transmit signals during dual segment transfers of three data bursts in interleaved mode. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 8'h2 8'h3 d1 d2 d3 d4 d5 d6 itx_num_valid[7:4] 4'b1000 4'b0001 4'b1000 4'b1000 4'b0100 4'b0101 itx_num_valid[3:0] 4'b0000 4'b0100 4'b0000 4'b0100 4'b0000 itx_eopbits 4'b0000 4'b0000 4'b0000 4'b1000 4'b1000 itx_din_words: Word 7 dw0 dw8 dw4 dw12 dw20 dw4 Word 6 dw1 dw5 dw13 dw21 dw5 Word 5 Word 4 dw2 dw6 dw14 dw22 dw6 dw3 dw7 dw15 dw23 dw7 Word 3 dw4 dw0 dw8 dw16 dw0 dw8 Word 2 Word 1 dw5 dw1 dw9 dw17 dw1 dw6 dw2 dw10 dw18 dw2 Word 0 dw7 dw3 dw11 dw19 dw3 Cycle 7 tx_usr_clk itx_sop[1] itx_sop[0] itx_chan 8'h2 itx_sob[1] itx_sob[0] itx_eob itx_din_words The figure shows three data bursts in dual segment mode on the TX user data transfer interface. In cycle 1, the application asserts itx_sop[1] and itx_sob[1], indicating that this cycle is both the start of the burst and the start of the packet, and that data starts from the most significant byte of the data symbol. The application drives the value of 2 on itx_chan to indicate the data originates from channel 2. Functional Description Send Feedback Altera Corporation 4-16 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Transmit... UG-01128 2016.05.02 In cycle 2, the following two events occur: * The first data burst completes. The application asserts itx_eob, indicating the data the application transfers to the IP core in this clock cycle is the end of the burst. The value the application drives on itx_num_valid[7:4] indicates that one word in this data symbol is valid data associated with this burst. In addition, the application drives itx_eopbits to the value of 4'b0000 to indicate that the data the application transfers to the IP core in this clock cycle is not the end of the packet. Therefore, all bytes in this data word are valid. * A second data burst starts at Word 3. This transfer is a dual segment transfer, as is allowed whether or not the IP core is configured in dual segment mode on the RX side. The application asserts itx_sop[0] and itx_sob[0], indicating that this cycle is both the start of the burst and the start of the packet, and that data in this burst and packet starts from Byte 31 of the data symbol. The application drives the value of 3 on itx_chan to indicate the data originates from channel 3. The value of itx_num_valid[3:0] is 4'b0100, indicating this data transfer is a dual segment data transfer--that it begins at Word 3. The value of itx_num_valid[7:4] has no relevance for the data words in this burst that appear in this data symbol, except to indicate the previous burst includes no data in these words of the data symbol (Words 3 through 0), and therefore, that they are available for the second data burst. As is required, the dual segment data transfer places valid data in all four words in the least significant half of the data symbol. In cycles 3 and 4, the second data burst continues with no EOB or EOP indication. The IP core does not sample the value of itx_chan in these clock cycles, and its value is therefore a Don't Care. The value on itx_num_valid[7:4] indicates that all eight words in each of these data symbols are valid data associated with this burst. In cycle 5, the following two events occur: * The second data burst completes. The application asserts itx_eob, indicating the data transfered in this clock cycle is the end of the burst. The value the application drives on itx_num_valid[7:4] indicates that four words in this data symbol are valid data associated with this burst. In addition, the value the application drives on itx_eopbits indicates the data is the end of the packet, and that all eight bytes of the final data word are valid data bytes. * A third data burst starts at Word 3. This transfer is a dual segment transfer, as is allowed whether or not the IP core is configured in dual segment mode on the RX side. The application asserts itx_sob[0], indicating that this cycle is the start of the burst and that data in this burst starts from Byte 31 of the data symbol. However, the application does not assert itx_sop[0], indicating this burst is not the first burst in the packet. The value the application drives on itx_chan indicates the data originates from channel 2. Therefore, we can conclude this data burst is the second burst in a packet from channel 2. The value the application drives on itx_num_valid[3:0] is 4'b0100, indicating this data transfer is a dual segment data transfer--that it begins at Word 3. The value of itx_num_valid[7:4] has no relevance for the data words in this burst that appear in this data symbol, except to indicate the previous burst includes no data in these words of the data symbol (Words 3 through 0), and therefore, that they are available for the second data burst. As is required, the dual segment data transfer places valid data in all four words in the least significant half of the data symbol. In cycle 6, the third data burst completes. The application asserts itx_eob, indicating the data transfered in this clock cycle is the end of the burst. The value on itx_num_valid[7:4] indicates that five words in this data symbol are valid data associated with this burst. In addition, the value the application drives on itx_eopbits indicates the data is the end of the packet, and that all eight bytes of the final data word are valid data bytes. Because the data from this burst occupies words 7 through 3 of the data symbol, another burst cannot start in the current data symbol. Altera Corporation Functional Description Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core In-Band Calendar Bits on Transmit Side 4-17 In dual segment mode as in single segment mode, if the IP core is in Interleaved mode, you can transfer a packet without interleaving--if you do not toggle the channel number during the packet transfer, the packet is not interleaved with another packet. However, you must still assert the itx_sob and itx_eob signals correctly to maintain the proper burst boundaries. If you do not drive the itx_sob and itx_eob signals, the 100G Interlaken IP Core does not operate properly and the transmit FIFO may overflow, since in this mode the internal logic is looking for itx_sob and itx_eob assertion for insertion of proper burst control words. Related Information Dual Segment Mode on page 4-8 100G Interlaken IP Core In-Band Calendar Bits on Transmit Side If you turn on Include in-band flow control functionality, the itx_calendar input signal supports inband flow control. It is synchronous with tx_usr_clk, but does not align with the packets on the user data interface. The 100G Interlaken IP Core reads the itx_calendar bits and encodes them in control words (Burst control words and Idle control words) opportunistically. If you hold all the calendar bits at one, you indicate an XON setting for each channel. You should set the calendar bits to 1 to indicate that the Interlaken link partner does not need to throttle the data it transfers to this 100G Interlaken IP Core. Set this value by default if you choose not to use the in-band flow control feature of the 100G Interlaken IP Core. If you decide to turn off any channel, you must drive the corresponding bits of itx_calendar with zero (the XOFF setting) for that channel. If you turn on Include in-band flow control functionality, the 100G Interlaken IP Core transmits each page of the itx_calendar bits on the Interlaken link in a separate control word, starting with the most significant page and working through the pages, in order, to the least significant page. If you turn off Include in-band flow control functionality, the IP core fills each flow control bit in each control word with the value of 1. Consider an example where the number of calendar pages is four and itx_calendar bits are set to the value 64'h1111_2222_3333_4444. In this example, the Number of calendar pages parameter is set to four, and therefore the width of the itx_calendar signal is 4 x 16 = 64 bits. Each of these bits is a calendar bit. The transmission begins with the page with the value of 16'h1111 and works through the pages in order until the least significant page with the value of 16'h4444. In this example, four control words are required to send the full set of 64 calendar bits from the itx_calendar signal. The 100G Interlaken IP Core automatically sets the Reset Calendar bit[56] of the next available control word to the value of one, to indicate the start of transmission of a new set of calendar pages, and copies the most significant page (16'h1111 in this example) to the In-Band Flow Control bits[55:40] of the control word. It maps the most significant bit of the page to the control word bit[55] and the least significant bit of the page to the control word bit[40]. The table shows the value of the Reset Calendar bit and the In-Band Flow Control bits in the four Interlaken link control words that transmit the 64'h1111_2222_3333_4444 value of itx_calendar: Table 4-2: Value of Reset Calendar Bit and In-band Flow Control Bits in the Example Control Word First Functional Description Send Feedback Reset Calendar Bit (bit [56]) 1 In-Band Flow Control Bits (bits [55:40]) 16'b0001000100010001 (16'h1111) Altera Corporation 4-18 UG-01128 2016.05.02 100G Interlaken IP Core Transmit Path Blocks Control Word Reset Calendar Bit (bit [56]) In-Band Flow Control Bits (bits [55:40]) Second 0 16'b0010001000100010 (16'h2222) Third 0 16'b0011001100110011 (16'h3333) Fourth 0 16'b0100010001000100 (16'h4444) For details of the control word format, refer to the Interlaken Protocol Specification, Revision 1.2. The 100G Interlaken IP Core supports itx_calendar widths of 1, 2, 4, 8, and 16 16-bit calendar pages. You configure the width in the 100G Interlaken IP Core parameter editor. By convention, in a standard case, each calendar bit corresponds to a single data channel. However, the 100G Interlaken IP Core assumes no default usage. You must map the calendar bits to channels or link status according to your specific application needs. For example, if your design has 64 physical channels, but only 16 priority groups, you can use a single calendar page and map each calendar bit to four physical channels. As another example, for a different application, you can use additional calendar bits to pass quality-of-service related information to the Interlaken link partner. If your application flow-controls a channel, you are responsible for dropping the relevant packet. Altera supports the transfer of the itx_calendar values you provide without examining the data that is affected by in-band flow control of the Interlaken link. Related Information * 100G Interlaken IP Core Back-Pressured Packet Transfer Example on page 4-13 Example of in-band calendar bits usage on the TX user data transfer interface. * Interlaken Protocol Specification, Revision 1.2 100G Interlaken IP Core Transmit Path Blocks Figure 4-9: 100G Interlaken IP Core Transmit Path tx_usr_clk itx_chan[7:0] itx_num_valid[7:0] itx_sob[1:0] itx_eob itx_sop[1:0] itx_eopbits[3:0] itx_din_words[511:0] itx_calendar[16 x n - 1:0] itx_ready tx_mac_clk TX Transmit Buffer clk_tx_common TX MAC TX PCS TX PMA tx_pin[m - 1:0] Transceiver Blocks The 100G Interlaken IP core transmit data path has the following four main functional blocks: 100G Interlaken IP Core TX Transmit Buffer on page 4-19 Altera Corporation Functional Description Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core TX Transmit Buffer 4-19 100G Interlaken IP Core TX MAC on page 4-19 100G Interlaken IP Core TX PCS on page 4-19 100G Interlaken IP Core TX PMA on page 4-19 100G Interlaken IP Core TX Transmit Buffer The 100G Interlaken MegaCore function TX transmit buffer performs the following functions: * Aligns the incoming user application data, itx_data, in the IP core internal format. * Implements domain crossing from the tx_usr_clk clock domain to the tx_mac_clk clock domain. 100G Interlaken IP Core TX MAC The 100G Interlaken MegaCore function TX MAC performs the following functions: * Inserts burst and idle control words in the incoming data stream. Burst delineation allows packet segmentation in the Interlaken protocol. * Performs flow adaption of the data stream, repacking the data to ensure the maximum number of words is available on each valid clock cycle. * Calculates and inserts CRC24 bits in all burst and idle words. * Inserts calendar data in all burst and idle words, if you configure in-band flow control. * Stripes the data across the PCS lanes. Configurable order, default is MSB of the data goes to lane 0. * Buffers data between the application and the TX PCS block in the TX FIFO buffer. The TX PCS block uses the FIFO buffer to recover bandwidth when the number of words delivered to the transmitter is less than the full width. 100G Interlaken IP Core TX PCS TX PCS logic is an embedded hard macro and does not consume FPGA soft logic elements. The 100G Interlaken MegaCore function TX PCS block performs the following functions for each lane: * * * * Inserts the meta frame words in the incoming data stream. Calculates and inserts the CRC32 bits in the meta frame diagnostic words. Scrambles the data according to the scrambler seed and the protocol-specified polynomial. Performs 64B/67B encoding. 100G Interlaken IP Core TX PMA The 100G Interlaken MegaCore function TX PMA serializes the data and sends it out on the Interlaken link. 100G Interlaken IP Core Receive Path The 100G Interlaken MegaCore function receives data on the Interlaken link, monitors and removes Interlaken overhead, and provides user data and calendar information to the application. Calendar information is available only if you turn on Include in-band flow control block in the 100G Interlaken parameter editor. Functional Description Send Feedback Altera Corporation 4-20 UG-01128 2016.05.02 100G Interlaken IP Core Receive User Data Interface Examples 100G Interlaken IP Core Receive User Data Interface Examples The following examples illustrate how to use the Altera 100G Interlaken IP core RX user data interface: 100G Interlaken IP Core Receiver Side Example on page 4-20 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Receive Example on page 4-22 100G Interlaken IP Core Receiver Side Example The 100G Interlaken IP Core can generate interleaved data transfers on the RX user data transfer interface. The IP core always toggles the irx_sob and irx_eob signals to indicate the beginning of the burst and end of the burst. In single segment mode, only irx_sob[1] toggles. In dual segment mode, irx_sob[0] toggles if the current burst starts at word 4 of the data symbol. Figure 4-10: 100G Interlaken IP Core Receiver Side Single Segment Example This example illustrates the expected behavior of the 100G Interlaken IP core application interface receive signals during data transfers from the IP core to the application on the RX user data transfer interface in interleaved, single segment mode. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 8'h4 8'h2 8'h3 8'h4 d3 d4 d5 d6 4'b0000 4'b1000 4'b1000 4'b1000 4'b0000 4'b0000 4'b0000 4'b0000 Cycle 8 Cycle 9 rx_usr_clk irx_sop[1] irx_chan 8'h2 irx_sob[1] irx_eob irx_dout_words d1 irx_num_valid[7:4] 4'b1000 irx_eopbits 4'b0000 d2 4'b1000 4'b0011 4'b1011 d7 4'b0010 4'b1011 The figure shows the timing diagram for an interleaved data transfer in Interleaved mode. In cycle 1, the IP core asserts irx_sop[1] and irx_sob[1], indicating that this cycle is both the start of the burst and the start of the packet. The first word is MSB aligned at the top. The value the IP core drives on irx_chan indicates the data targets channel 2. You must sample irx_chan during cycles in which irx_sob[1] is asserted. The irx_chan output signal is not guaranteed to remain valid for the duration of the burst. In cycle 2, the IP core asserts irx_eob, indicating the data the IP core transfers to the application in this clock cycle is the end of the burst. irx_num_valid[7:4] indicates all eight words are valid. However, the data in this cycle is not end of packet data. The IP core will transfer at least one additional data burst in this packet, possibly interleaved with one or more bursts in packets that target different data channels. Cycle 3 is a short burst with both irx_sob[1] and irx_eob asserted. The IP core drives the value of three on irx_num_valid[7:4] to indicate that three words of the eight-word irx_dout_words data bus are valid. The data is packed in the most significant words of irx_dout_words.The IP core drives the value of Altera Corporation Functional Description Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core Receiver Side Example 4-21 4'b1011 on irx_eopbits to indicate that the data the IP core transfers to the application in this cycle are the final words of the packet, and that in the final word of the packet, only three bytes are valid data. The value the IP core drives on irx_chan indicates this burst targets channel 4. In cycle 4, the irx_num_valid[7:4] signal has the value of zero, which means this cycle is an idle cycle. In cycle 5, the IP core sends another single-cycle data burst to channel 2, by asserting irx_sob[1] and irx_eob to indicate this data is both the start and end of the burst. The IP core does not assert irx_sop[1], because this burst is not start of packet data. irx_eopbits has the value of 4'b0000, indicating this burst is also not end of packet data. This data follows the data burst transfered in cycles 1 and 2, within the same packet the IP core is sending to channel 2. In cycle 6, the IP core sends a start of packet, single-cycle data burst to channel 3. In cycles 7 and 8, the IP core sends a two-cycle data packet in one two-cycle burst. In cycle 8, the second data cycle, the IP core drives the value of two on irx_num_valid[7:4] and the value of 4'b1011 on irx_eopbits, to tell the application that in this clock cycle, the two most significant words of the data symbol contain valid data and the remaining words do not contain valid data, and that in the second of these two words, only the three most significant bytes contain valid data. Functional Description Send Feedback Altera Corporation 4-22 UG-01128 2016.05.02 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Receive... 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Receive Example Figure 4-11: Dual Segment Data Transfer on Receive Interface in Interleaved Mode This example illustrates the expected behavior of the 100G Interlaken IP core application interface receive signals during dual segment transfers of three data bursts in interleaved mode. The 100G Interlaken IP core can generate dual segment data transfers only if you configure the IP core in dual segment mode. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 8'h2 8'h3 d1 d2 d3 d4 d5 d6 irx_num_valid[7:4] 4'b1000 4'b0001 4'b1000 4'b1000 4'b0100 4'b0101 irx_num_valid[3:0] 4'b0000 4'b0100 4'b0000 4'b0100 4'b0000 irx_eopbits 4'b0000 4'b0000 4'b0000 4'b1000 4'b1000 irx_dout_words: Word 7 dw0 dw8 dw4 dw12 dw20 dw4 Word 6 dw1 dw5 dw13 dw21 dw5 Word 5 Word 4 dw2 dw6 dw14 dw22 dw6 dw3 dw7 dw15 dw23 dw7 Word 3 dw4 dw0 dw8 dw16 dw0 dw8 Word 2 Word 1 dw5 dw1 dw9 dw17 dw1 dw6 dw2 dw10 dw18 dw2 Word 0 dw7 dw3 dw11 dw19 dw3 Cycle 7 rx_usr_clk irx_sop[1] irx_sop[0] irx_chan 8'h2 irx_sob[1] irx_sob[0] irx_eob irx_dout_words The figure shows three data bursts in dual segment mode on the RX user data transfer interface. In cycle 1, the IP core asserts irx_sop[1] and irx_sob[1], indicating that this cycle is both the start of the burst and the start of the packet, and that data starts from the most significant byte of the data symbol. The IP core drives the value of 2 on irx_chan to indicate the data targets channel 2. Altera Corporation Functional Description Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Receive... 4-23 In cycle 2, the following two events occur: * The first data burst completes. The IP core asserts irx_eob, indicating the data the IP core transfers to the application in this clock cycle is the end of the burst. The value the IP core drives on irx_num_valid[7:4] indicates that one word in this data symbol is valid data associated with this burst. In addition, the IP core drives irx_eopbits to the value of 4'b0000 to indicate that the data the IP core transfers to the application in this clock cycle is not the end of the packet. * A second data burst starts at Word 3, as is allowed in dual segment mode. The IP core asserts irx_sop[0] and irx_sob[0], indicating that this cycle is both the start of the burst and the start of the packet, and that data in this burst and packet starts from Byte 31 of the data symbol. The IP core drives the value of 3 on irx_chan to indicate the data targets channel 3. The value of irx_num_valid[3:0] is 4'b0100, indicating this data transfer is a dual segment data transfer--that it begins at Word 3. The value of irx_num_valid[7:4] has no relevance for the data words in this burst that appear in this data symbol, except to indicate the previous burst includes no data in these words of the data symbol (Words 3 through 0), and therefore, that they are available for the second data burst. As is required, the dual segment data transfer places valid data in all four words in the least significant half of the data symbol. In cycles 3 and 4, the second data burst continues with no EOB or EOP indication. The application should not sample the value of irx_chan in these clock cycles. The value on irx_num_valid[7:4] indicates that all eight words in each of these data symbols are valid data associated with this burst. In cycle 5, the following two events occur: * The second data burst completes. The IP core asserts irx_eob, indicating the data transfered in this clock cycle is the end of the burst. The value the IP core drives on irx_num_valid[7:4] indicates that four words in this data symbol are valid data associated with this burst. In addition, the value the IP core drives on irx_eopbits indicates the data is the end of the packet, and that all eight bytes of the final data word are valid data bytes. * A third data burst starts at Word 3, as is allowed in dual segment mode. The IP core asserts irx_sob[0], indicating that this cycle is the start of the burst and that data in this burst starts from Byte 31 of the data symbol. However, the IP core does not assert irx_sop[0], indicating this burst is not the first burst in the packet. The value the IP core drives on irx_chan indicates the data targets channel 2. Therefore, we can conclude this data burst is the second burst in a packet that targets channel 2. The value the IP core drives on irx_num_valid[3:0] is 4'b0100, indicating this data transfer is a dual segment data transfer--that it begins at Word 3. The value of irx_num_valid[7:4] has no relevance for the data words in this burst that appear in this data symbol, except to indicate the previous burst includes no data in these words of the data symbol (Words 3 through 0), and therefore, that they are available for the second data burst. As is required, the dual segment data transfer places valid data in all four words in the least significant half of the data symbol. In cycle 6, the third data burst completes. The IP core asserts irx_eob, indicating the data transfered in this clock cycle is the end of the burst. The value on irx_num_valid[7:4] indicates that five words in this data symbol are valid data associated with this burst. In addition, the value the IP core drives on irx_eopbits indicates the data is the end of the packet, and that all eight bytes of the final data word are valid data bytes. Because the data from this burst occupies words 7 through 3 of the data symbol, another burst cannot start in the current data symbol. By default, the RX user data transfer interface can generate interleaved data. However, the IP core can also transfer a packet without interleaving--if the IP core does not toggle the channel number during the Functional Description Send Feedback Altera Corporation 4-24 100G Interlaken IP Core RX Errored Packet Handling UG-01128 2016.05.02 packet transfer, the packet is not interleaved with another packet. In this case, the IP core still asserts the irx_sob and irx_eob signals correctly to maintain the proper burst boundaries. Related Information Dual Segment Mode on page 4-8 100G Interlaken IP Core RX Errored Packet Handling The 100G Interlaken IP Core provides information about errored packets on the RX user data transfer interface through the following output signals: * irx_eopbits[3:0]--If this signal has the value of 4'b0001, an error indication arrived with the packet on the incoming Interlaken link: the EOP_Format field of the control word following the final burst of the packet on the Interlaken link has this value, which indicates an error and EOP. * irx_err--If you turn on Include advanced error reporting and handling, the 100G Interlaken IP Core checks the integrity of incoming packets on the Interlaken link, and reports some packet corruption errors it detects on the RX user data transfer interface in the irx_err output signal. The IP core asserts the irx_err output signal synchronously with the irx_eob signal. The IP core asserts this signal only if it can determine the burst in which the error occurred. If the IP core cannot determine the burst in which the error occurred, it does not assert the irx_err in response. In both cases, the application is responsible for discarding the relevant packet. If you turn on Include advanced error reporting and handling, the irx_err signal reflects CRC24 errors that are associated with a data or control burst. Some CRC24 errors might be an indication of one of the following conditions: * * * * Loss of lane alignment Illegal control word Illegal framing pattern Missing SOP or EOP indicator If you turn on Include advanced error reporting and handling, the irx_err output signal is aligned with irx_eob. If you do not turn on this parameter, the value on the irx_err output signal is invalid and should be ignored. The irx_err signal indicates where an error occurs. The IP core asserts this signal only if an error occurs in an identifiable burst. Corruption can occur at the SOP of the current packet, in some later cycle in the payload of the current packet, in a packet that is interleaved with the current packet, or in the current EOP cycle. However, the IP core asserts the irx_err signal only in a subset of these cases, If the current EOP cycle data is corrupted so badly that the EOP indication is missing, or if an error occurs during an IDLE cycle, the IP core does not assert the irx_err signal. For CRC24 errors, you should use the crc24_err status signal, rather than relying on the irx_err signal, in the following situations: * If you monitor the link when only Idle control words are being received (no data is flowing), you should monitor the real time status signal crc24_err. * If you maintain a count of CRC24 errors, you should monitor the number of times that the real time status signal crc24_err is asserted. * If you turn off Include advanced error reporting and handling, crc24_err is your only indicator of CRC24 errors. Altera Corporation Functional Description Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core Receiver Side Example With Errors and In-Band... 4-25 Related Information Include Advanced Error Reporting and Handling on page 3-3 100G Interlaken IP Core Receiver Side Example With Errors and In-Band Calendar Bits Figure 4-12: 100G Interlaken IP Core Receiver Side Single Segment Example With irx_err Errors This example illustrates the expected behavior of the 100G Interlaken IP core application interface receive signals during a packet transfer in single segment mode with CRC or other errors. In the example, the errored packet transfer is followed by two idle cycles and a non-errored packet transfer. rx_usr_clk Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 d5 d6 Cycle 9 irx_sop[1] irx_chan 8'h2 8'h3 irx_sob[1] irx_eob irx_dout_words irx_num_valid[7:4] d1 d2 d3 4'b1000 4'b1000 4'b0111 4'b0000 irx_eopbits 4'b0000 irx_calendar 64'hffff_ffff_ffff_ffff d4 4'b1000 4'b1000 4'b0010 4'b1011 4'b0000 4'b1011 ///////////64'h1111_2222_3333_4444 irx_err This figure illustrates the attempted transfer of a 179-byte packet on the RX user data transfer interface to channel 2, after the 100G Interlaken IP Core receives the packet on the Interlaken link and detects corruption. Following the errored packet, the IP core transfers an uncorrupted packet to channel 3. In cycle 1, the 100G Interlaken IP Core asserts irx_sop[1] when data is ready on irx_dout_words. When the 100G Interlaken IP Core asserts irx_sop[1], it also asserts the correct value on irx_chan to tell the application the data channel destination of the data. In this example, the value 2 on irx_chan tells the application that the data should be sent to channel number 2. During the SOP cycle (labeled with data value d1) and the cycle that follows the SOP cycle (labeled with data value d2), the 100G Interlaken IP Core holds the value of irx_num_valid[7:4] at 4'b1000. In the following clock cycle, labeled with data value d3, the 100G Interlaken IP Core holds the following values on critical output signals: * irx_num_valid[7:4] at the value of 4'b0111 to indicate the current data symbol contains seven 64-bit words of valid data. * irx_eopbits[3] high to indicate the current cycle is an EOP cycle. * irx_eopbits[2:0] at the value of 3'b011 to indicate that only three bytes of the final valid data word are valid data bytes. This signal behavior, in the absence of the irx_err flag, would correctly transfer a data packet with the total packet length of 179 bytes from the 100G Interlaken IP Core. However, the 100G Interlaken IP Core marks the burst as errored by asserting the irx_err signal, even though the irx_eopbits signal would appear to indicate the packet is valid. Functional Description Send Feedback Altera Corporation 4-26 UG-01128 2016.05.02 In-Band Calendar Bits on the 100G Interlaken IP Core Receiver User Data... The application is responsible for discarding the errored packet when it detects that the IP core has asserted the irx_err signal. Following the corrupted packet, the IP core waits two idle cycles and then transfers a valid 139-byte packet. Related Information * 100G Interlaken IP Core Packet Mode Operation Example on page 4-12 The first data transfer in the current example is the receiver interface equivalent of the transmitter interface transfer example described at this link. * In-Band Calendar Bits on the 100G Interlaken IP Core Receiver User Data Interface on page 4-26 Description of in-band calendar bits on the RX user data transfer interface. In-Band Calendar Bits on the 100G Interlaken IP Core Receiver User Data Interface The 100G Interlaken IP core receiver logic decodes incoming control words (both Burst control words and Idle control words) on the incoming Interlaken link. If you turn on Include in-band flow control functionality, the receiver logic extracts the calendar pages from the In-Band Flow Control bits and assembles them into the irx_calendar output signal. If you turn off Include in-band flow control functionality, the IP core sets all the bits of irx_calendar to the value of 1, indicating that the IP core is not flow controlling the incoming data on the Interlaken link. The 100G Interlaken IP core receives the most significant calendar page in a control word with the Reset Calendar bit set, indicating the beginning of the calendar page sequence. The mapping of bits from the control words to the irx_calendar output signal is consistent with the mapping of bits from the itx_calendar input signal to the control words. On the RX side, your application is responsible for mapping the calendar pages to the corresponding channels, according to any interpretation agreed upon with the Interlaken link partner application in sideband communication. On the TX side, your application is responsible for throttling the data it transfers to the TX user data transfer interface, in response to the agreed upon interpretation of the irx_calendar bits. Related Information * 100G Interlaken IP Core In-Band Calendar Bits on Transmit Side on page 4-17 * 100G Interlaken IP Core Receiver Side Example With Errors and In-Band Calendar Bits on page 425 Example of in-band calendar bits usage on the RX user data transfer interface. Altera Corporation Functional Description Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core Receive Path Blocks 4-27 100G Interlaken IP Core Receive Path Blocks Figure 4-13: 100G Interlaken IP Core Receive Path irx_chan[7:0] irx_num_valid[7:0] irx_sob[1:0] irx_eob irx_sop[1:0] irx_eopbits[3:0] irx_dout_words[511:0] irx_calendar[16 x n - 1:0] irx_err Transceiver Blocks RX Regroup rx_usr_clk RX MAC rx_mac_clk RX PCS RX PMA rx_pin[m - 1:0] clk_rx_common The 100G Interlaken IP core receive data path has the following four main functional blocks: 100G Interlaken IP Core RX PMA on page 4-27 100G Interlaken IP Core RX PCS on page 4-27 100G Interlaken IP Core RX MAC on page 4-27 100G Interlaken IP Core RX Regroup Block on page 4-28 100G Interlaken IP Core RX PMA The 100G Interlaken MegaCore function RX PMA deserializes data that the IP core receives on the serial lines of the Interlaken link. 100G Interlaken IP Core RX PCS RX PCS logic is an embedded hard macro and does not consume FPGA soft logic elements. The 100G Interlaken MegaCore function RX PCS block performs the following functions to retrieve the data: * * * * * * * Detects word lock and word synchronization. Checks running disparity. Reverses gearboxing and 64/67B encoding. Descrambles the data. Delineates meta frame boundaries. Performs CRC32 checking. Sends lane status information to the calendar and status blocks, if Include in-band flow control functionality is turned on. 100G Interlaken IP Core RX MAC To recover a packet or burst, the RX MAC takes data from each of the PCS lanes and reassembles the packet or burst. Functional Description Send Feedback Altera Corporation 4-28 UG-01128 2016.05.02 100G Interlaken IP Core RX Regroup Block The 100G Interlaken MegaCore function RX MAC performs the following functions: * Data de-striping, including lane alignment and burst assembly from the PCS lanes. * CRC24 validation * Calendar recovery, if Include in-band flow control functionality is turned on 100G Interlaken IP Core RX Regroup Block The 100G Interlaken MegaCore function RX regroup block performs the following functions: * Translates the IP core internal data format to the outgoing user application data irx_data format. * Implements domain crossing from the rx_mac_clk clock domain to the rx_usr_clk clock domain. Altera Corporation Functional Description Send Feedback 5 100G Interlaken MegaCore Function Signals 2016.05.02 UG-01128 Send Feedback Subscribe The 100G Interlaken MegaCore function communicates with the surrounding design through multiple external signals. 100G Interlaken IP Core Clock Interface Signals Table 5-1: 100G Interlaken IP Core Clock Interface Signal Name Direction Width (Bits) Description Clock Ports pll_ref_clk Input 1 Transceiver reference clock for the RX CDR PLL in IP core variations that target an Arria 10 device. Transceiver reference clock for the RX CDR PLL and the TX transceiver PLL in all other variations. Table 5-2: 100G Interlaken IP Core Supported pll_ref_clk Frequencies The sets of valid frequencies vary with the per-lane data rate of the transceivers. Per-Lane Data Rate Valid pll_ref_clk Frequencies (MHz) 10.3125 206.25, 257.8125, 322.265625, 412.5, 515.625, 644.53125 12.5, 6.25 156.25, 195.3125, 250, 312.5, 390.625, 500, 625 The pll_ref_clk input clock frequency must match the value you specify for the Transceiver reference clock frequency parameter. (c) 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 5-2 UG-01128 2016.05.02 100G Interlaken IP Core Clock Interface Signals Signal Name Direction Width (Bits) Description tx_serial_clk Input NUM_ LANES- Clocks for the individual transceiver channels in 100G Interlaken IP core variations that target an Arria 10 device. clk_tx_common Output 1 PCS common lane clock driven by the SERDES transmit PLL. The clock rate is the lane rate divided by 40 bits. The clk_tx_common frequency is 156.25 MHz for 6.25 Gbps, 257.8 MHz for 10.3125 Gbps, and 312.5 MHz for 12.5 Gbps per lane. clk_rx_common Output 1 Master recovered lane clock. The Interlaken specification requires all incoming lanes to run at the same frequency. tx_usr_clk Input 1 Transmit side user data interface clock. To achieve 100 Gbps Ethernet traffic throughput, you must run this clock at one of the following minimum frequencies: * 225 MHz in dual segment mode, 12-lane variations * 300 MHz in single segment mode and in 24-lane variations rx_usr_clk Input 1 Receive side user data interface clock. To achieve 100 Gbps Ethernet traffic throughput, you must run this clock at one of the following minimum frequencies: * 225 MHz in dual segment mode, 12-lane variations * 300 MHz in single segment mode and in 24-lane variations mm_clk Input 1 Management clock. Clocks the register accesses. It is also used for clock rate monitoring and some analog calibration procedures. You must run this clock at a frequency in the range of 100 MHz-125 MHz. reconfig_clk Input 1 Clocks the Arria 10 transceiver reconfiguration interface. This clock is available only in IP core variations that target an Arria 10 device. You should run this clock at a frequency of 100 MHz. Note: If you change the port name or period of a clock, then you must modify .sdc file to match the corresponding changes. Related Information Performance and Fmax Requirements for 100G Ethernet Traffic on page 10-1 Explains the tx_usr_clk and rx_usr_clk frequency requirements. Altera Corporation 100G Interlaken MegaCore Function Signals Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core Reset Interface Signals 5-3 100G Interlaken IP Core Reset Interface Signals Table 5-3: 100G Interlaken IP Core Reset Interface Signal Name Direction Width (Bits) Description 100G Interlaken IP Core Reset Signals reset_n Input 1 Active-low reset signal for the 100G Interlaken IP core. Altera recommends that you hold this signal low for at least the duration of two mm_clk cycles, to ensure the reset sequence proceeds correctly. reconfig_reset Input 1 Reset signal for the Arria 10 transceiver reconfiguration interface. This signal is available only in IP core variations that target an Arria 10 device. srst_tx_common Output 1 Synchronous reset signal that the IP core asserts high while the transmitter is initializing. This signal is synchro nous with clk_tx_common. This signal goes low to indicate that the transceiver PLL has locked to the reference clock. The TX PCS and the TX MAC are held in reset while the srst_tx_common reset signal is asserted. You can use this signal for diagnostic purposes. srst_rx_common Output 1 Synchronous reset that is active at startup. This signal is synchronous with clk_rx_common. This signal goes low to indicate that the transceiver PLL has achieved lock and the recovered clock has locked to data in normal operation, this signal is deasserted after the transceiver completes its reset sequence. The RX PCS and the RX MAC are held in reset while the srst_rx_common reset signal is asserted. This signal is also active in the event of a serious clock data recovery failure on any of the RX lanes. tx_usr_srst Output 1 Transmit side reset output signal. Indicates the transmit side user data interface is resetting. This signal is synchro nous with tx_usr_clk. Your application can use this signal to reset any status counters you may maintain in the tx_usr_clk domain. rx_usr_srst Output 1 Receive side reset output signal. Indicates the receive side user data interface is resetting. This signal is synchronous with rx_usr_clk. Your application can use this signal to reset any status counters you may maintain in the rx_ usr_clk domain. 100G Interlaken MegaCore Function Signals Send Feedback Altera Corporation 5-4 UG-01128 2016.05.02 100G Interlaken IP Core User Data Transfer Interface Signals 100G Interlaken IP Core User Data Transfer Interface Signals Table 5-4: 100G Interlaken IP Core User Data Transfer Interface Signal Name Direction Width (Bits) Description 100G Interlaken IP Core Transmit User Interface itx_chan itx_num_ valid Input 8 Transmit logic channel number. The IP core supports up to 256 channels. The 100G Interlaken IP core samples this value only when a bit of itx_sop or itx_sob is high and itx_num_valid has a non-zero value. Input 8 itx_num_valid[7:4] specifies the number of valid 64-bit words in the current packet in the current data symbol. The maximum value of itx_num_valid[7:4] is eight, because a data symbol on the 512 bit wide data path has eight words (8 x 64 bits = 512 bits). In non-valid cycles, you must set the value of itx_num_valid[7:4] to zero. In valid cycles, you must set the value of itx_num_valid[7:4] as follows: * 4'b1000: if all eight words contain valid data from the current packet. * 4'b0xxx: where xxx indicates the number of valid words that are part of the current packet, if the number is less than eight. Data is always MSB aligned (left aligned). For example, the value of 4'b0111 indicates that word 0 (bit [63:0]) is not valid. In dual segment mode, if the value of itx_num_valid[7:4] is four or less (but not zero), the application can hold itx_num_valid[2] high to indicate the current data symbol also includes the first four 64-bit words of a new packet. The only valid values for itx_num_valid[3:0] are 4'b0100 and 4'b0000. When itx_num_valid[3:0] has the value of 4'b0100, you must also hold itx_sop[0] high. You must set the value of itx_num_valid to zero in all non-valid cycles, even when itx_ready is not asserted. itx_sop Input 2 Indicates the current data symbol on itx_din_words contains the start of a packet (SOP). This signal has the following valid values: * 2'b00--The current data symbol does not contain the start of a packet. * 2'b10-- If itx_sop[1] has the value of 1, the start-of-packet aligns with the most significant byte (byte 63) of the data. * 2'b01-- If itx_sop[0] has the value of 1, the start-of-packet aligns with byte 31 of the data. Altera Corporation 100G Interlaken MegaCore Function Signals Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core User Data Transfer Interface Signals Signal Name itx_ eopbits Direction Input Width (Bits) 4 5-5 Description Indicates whether the current data symbol contains the end of a packet (EOP) with or without an error, and specifies the number of valid bytes in the current end-of-packet, non-error 8-byte data word, if relevant. You must set the value of itx_eopbits as follows: * 4b'0000: no end of packet, no error. * 4b'0001: Error and end of packet. * 4b'1xxx: End of packet. xxx indicates the number of valid bytes in the final valid 8-byte word of the packet, as follows: * * * * 3b'000: all 8 bytes are valid. 3b'001: 1 byte is valid. ... 3b'111: 7 bytes are valid. All other values (4'b01xx, 4'b001x) are undefined. The valid bytes always start in bit positions [63:56] of the final valid data word of the packet. itx_sob Input 2 Indicates the current data symbol contains the start of a burst (SOB). If the 100G Interlaken IP core is in Interleaved mode, you are responsible for providing this start of the burst signal. If the100G Interlaken IP core is in Packet mode, the IP core ignores this signal. The 100G Interlaken IP core samples the itx_chan signal during this cycle. This signal has the following valid values: * 2'b00--The current data symbol does not contain the start of a burst. * 2'b10-- If itx_sob[1] has the value of 1, the start-of-burst aligns with the most significant byte (byte 63) of the data. * 2'b01-- If itx_sob[0] has the value of 1, the start-of-burst aligns with byte 31 of the data. Typically, you use this mode for sending interleaved packets. However, you can still send non-interleaved packets as long as you provide the itx_sob and itx_eob signal values. You are responsible to comply with the BurstMax and BurstMin parameters. If the burst you send is too large, it can overflow the 100G Interlaken transmit buffer. itx_eob itx_din_ words Input 1 End of the burst. If the 100G Interlaken IP core is in Interleaved mode, you are responsible for providing this end of the burst signal. If the 100G Interlaken IP core is in Packet mode, the IP core ignores this signal. You are responsible to comply with the BurstMax and BurstMin parameters. Input 512 The eight 64-bit words of input data (one data symbol). When itx_ num_valid has the value of zero, the IP core ignores itx_din_words. 100G Interlaken MegaCore Function Signals Send Feedback Altera Corporation 5-6 UG-01128 2016.05.02 100G Interlaken IP Core User Data Transfer Interface Signals Signal Name itx_ calendar itx_ready Direction Width (Bits) Description Input 16 N Multiple pages (16 bits per page) of calendar input bits. The 100G Interlaken IP Core copies these bits to the in-band flow control bits in N control words that it sends on the Interlaken link. N is the value of the Number of calendar pages parameter, which can be any of 1, 2, 4, 8. or 16. This signal is synchronous with tx_usr_clk, although it is not part of the user data transfer protocol. Output 1 Flow control signal to back pressure transmit traffic. When this signal is high, you can send traffic to the IP core. When this signal is low, you should stop sending traffic to the IP core within one to four cycles. You can consider the inverse of itx_ready to be a FIFO-almost-full indicator. In full duplex mode, itx_ready is low when rx_lanes_ aligned is low. itx_ifc_ err Output 1 Indicates the transmit side user data transfer interface received traffic that the 100G Interlaken IP Core does not support. The IP core asserts the itx_ifc_err signal in the following cases: * In Interleaved mode, the IP core receives a burst that exceeds the size of MaxBurst. * itx_sop or itx_sob has the invalid value of 2'b11 in a valid data cycle. * Two instances of non-zero itx_sop (a start of packet), or two instances of non-zero itx_sob (a start of burst), are separated by fewer than 64 bytes. The IP core asserts the itx_ifc_err signal for a single clock cycle. The signal pulses within the current burst, with a delay of one or two cycles after the error on the transmit side user data transfer interface. 100G Interlaken IP Core Receive User Interface irx_chan Altera Corporation Output 8 Receive logic channel number. The IP core supports up to 256 channels. You should sample this value when a bit of irx_sop or irx_ sob is high and irx_num_valid has a non-zero value. 100G Interlaken MegaCore Function Signals Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core User Data Transfer Interface Signals Signal Name irx_num_ valid Direction Output Width (Bits) 8 5-7 Description irx_num_valid[7:4] specifies the number of valid 64-bit words in the current packet in the current data symbol. The maximum value of irx_num_valid[7:4] is eight, because a data symbol on the 512 bit wide data path has eight words (8 x 64 bits = 512 bits). In valid cycles, the IP core sets the value of irx_num_valid[7:4] as follows: * 4'b1000: if all eight words contain valid data from the current packet. * 4'b0xxx: where xxx indicates the number of valid words that are part of the current packet, if the number is less than eight. Data is always MSB aligned (left aligned). For example, the value of 4'b0111 indicates that word 0 (bit [63:0]) is not valid. In dual segment mode, if the value of irx_num_valid[7:4] is four or less (but not zero), the IP core can hold irx_num_valid[2] high to indicate the current data symbol also includes the first four 64-bit words of a new packet. The only valid values for irx_num_valid[3:0] are 4'b0100 and 4'b0000. When irx_num_valid[3:0] has the value of 4'b0100, the IP core also holds irx_sop[0] high. The IP core sets the value of irx_num_valid to zero in all non-valid cycles. irx_sop Output 2 Indicates the current data symbol on irx_dout_words contains the start of a packet (SOP). This signal has the following valid values: * 2'b00--The current data symbol does not contain the start of a packet. * 2'b10-- If irx_sop[1] has the value of 1, the start-of-packet aligns with the most significant byte (byte 63) of the data. * 2'b01-- If irx_sop[0] has the value of 1, the start-of-packet aligns with byte 31 of the data. This value is valid only in variations configured in dual segment mode. 100G Interlaken MegaCore Function Signals Send Feedback Altera Corporation 5-8 UG-01128 2016.05.02 100G Interlaken IP Core User Data Transfer Interface Signals Signal Name irx_ eopbits Direction Output Width (Bits) 4 Description Indicates whether the current data symbol contains the end of a packet (EOP) with or without an error, and specifies the number of valid bytes in the current end-of-packet, non-error 8-byte data word, if relevant. The IP core sets the value of irx_eopbits as follows: * 4b'0000: no end of packet, no error. * 4b'0001: Error and end of packet. * 4b'1xxx: End of packet. xxx indicates the number of valid bytes in the final valid 8-byte word of the packet, as follows: * * * * 3b'000: all 8 bytes are valid. 3b'001: 1 byte is valid. ... 3b'111: 7 bytes are valid. All other values (4'b01xx, 4'b001x) are undefined and are not generated by the IP core. The valid bytes always start in bit positions [63:56] of the final valid data word of the packet. irx_sob Output 2 Start of the burst. The 100G Interlaken IP core indicates the start of the burst. The signal irx_channel is only valid when irx_sob is high. This signal toggles in Packet Mode and in Interleaved Mode. This signal has the following valid values: * 2'b00--The current data symbol does not contain the start of a burst. * 2'b10-- If irx_sob[1] has the value of 1, the start-of-burst aligns with the most significant byte (byte 63) of the data. * 2'b01-- If irx_sob[0] has the value of 1, the start-of-burst aligns with byte 31 of the data. irx_eob irx_dout_ words irx_ calendar Altera Corporation Output 1 End of the burst. The 100G Interlaken IP core indicates the end of the burst. This signal toggles in Packet Mode and in Interleaved Mode. Output 512 The eight 64-bit words of output data (one data symbol). When irx_ num_valid has the value of zero, you should ignore irx_dout_words. Output 16 x N Multiple pages (16 bits per page) of calendar output bits. The value is the in-band flow control bits from N control words on the incoming Interlaken link. N is the value of the Number of calendar pages parameter, which can be any of 1, 2, 4, 8, or 16. This signal is synchro nous with rx_usr_clk, although it is not part of the user data transfer protocol. 100G Interlaken MegaCore Function Signals Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface... Signal Name irx_err Direction Output Width (Bits) 1 5-9 Description Indicates an errored packet. This signal is valid only when irx_eob is asserted. This signal is only valid in irx_eob cycles if you turn on the Include advanced error reporting and handling parameter. Related Information * Data Format on page 3-7 Describes the parameter to select single segment or dual segment mode. * Dual Segment Mode on page 4-8 Describes the dual segment mode. * 100G Interlaken IP Core RX Errored Packet Handling on page 4-24 Describes the behavior of the irx_err signal. * Transfer Mode Selection on page 3-6 Describes the parameter to select Packet or Interleaved mode. * Interleaved and Packet Modes on page 4-7 Describes the Packet and Interleaved modes. 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals Table 5-5: 100G Interlaken IP Core SERDES Signals, Burst Parameter Signals, and Real Time Status Signals Signal Name Direction Width (Bits) Description SERDES Pins rx_pin Input Number of lanes Each bit represents the differential pair on an RX Interlaken lane. tx_pin Output Number of lanes Each bit represents the differential pair on a TX Interlaken lane. TX Burst Control Settings 100G Interlaken MegaCore Function Signals Send Feedback Altera Corporation 5-10 UG-01128 2016.05.02 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface... Signal Name burst_max_in Direction Input Width (Bits) 4 Description Encodes the BurstMax parameter for the IP core. The actual value of the BurstMax parameter must be a multiple of 64 bytes. While traffic is present, this input signal should remain static. However, when no traffic is present, you can modify the value of the burst_ max_in signal to modify the BurstMax value of the IP core. The 100G InterlakenIP core supports the following valid values for this signal: 2: 128 bytes 4: 256 bytes 8: 512 bytes burst_short_in Input 4 Encodes the BurstShort parameter for the IP core. The 100G Interlaken IP core supports the following valid value for this parameter: 2: 64 bytes In general, the presence of the BurstMin parameter makes the BurstShort parameter obsolete. burst_min_in Input 4 Encodes the BurstMin parameter for the IP core. The IP core supports the following valid values for this signal: 0: Disable optional enhanced scheduling. Altera recommends you do not drive this value in variations in dual segment mode. If you disable enhanced scheduling, performance is nonoptimal. 2: 64 bytes 4: 128 bytes The BurstMin parameter should have a value that is less than or equal to half of the value of the BurstMax parameter. Altera recommends that you modify the value of this input signal only when no traffic is present on the TX user data interface. You do not need to reset the IP core. Real-Time Transmit Status Signals (Synchronous with tx_usr_clk) Altera Corporation 100G Interlaken MegaCore Function Signals Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface... Signal Name tx_lanes_ aligned itx_hungry Direction Width (Bits) 5-11 Description Output 1 All of the transmitter lanes are aligned and are ready to send traffic. Output 1 A dynamic status flag indicating that a downstream buffer which supplies data to the PCS is running empty. The IP core handles this situation by inserting IDLE symbols (IDLE control words) in the packet stream. Therefore, this signal does not indicate an error. This signal is asserted for the duration of the condition it indicates. The PCS runs continuously with the provided data or inserted IDLE symbols. This signal is usually asserted immediately after the IP core comes out of reset. However, the signal can also be asserted during normal operation, and is not a cause for concern. itx_overflow Output 1 An error flag indicating that the PCS buffer is currently overflowing. This signal is asserted for the duration of the overflow condition: it is asserted in the first clock cycle in which the overflow occurs, and remains asserted until the PCS buffer pointers indicate that no overflow condition exists. itx_underflow Output 1 An error flag indicating that the PCS buffer is currently underflowed. In normal operation, this signal may be asserted temporarily immediately after the 100G Interlaken IP core comes out of reset. It is asserted as a single cycle wide pulse. Real-Time Receiver Status Signals (Synchronous with rx_usr_clk ) sync_locked Output Number of lanes Receive lane has locked on the remote transmitter Meta Frame. These signals are level signals: all bits are expected to stay high unless a problem occurs on the serial line. word_locked Output Number of lanes Receive lane has identified the 67-bit word boundaries in the serial stream. These signals are level signals: all bits are expected to stay high unless a problem occurs on the serial line. Output 1 All of the receiver lanes are aligned and are ready to receive traffic. This signal is a level signal. rx_lanes_ aligned 100G Interlaken MegaCore Function Signals Send Feedback Altera Corporation 5-12 UG-01128 2016.05.02 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface... Signal Name crc24_err Direction Output Width (Bits) 1 Description A CRC24 error flag covering both control word and data word. This signal does not associate the CRC24 error with a particular packet. Instead, its value indicates the overall SERDES status. You can use this signal to count the number of CRC24 errors. This signal is asserted as a single cycle wide pulse. If the IP core detects back-to-back CRC24 errors, this signal toggles. crc32_err Output Number of lanes An error flag indicating diagnostic CRC32 failures per lane. This signal is asserted as a single cycle wide pulse. If back-to-back CRC32 errors are detected, this signal toggles. irx_overflow Output 1 An error flag indicating the presence of excessive jitter at the receiver side. This signal is included in the current IP core opportunisti cally for diagnostic purposes. rdc_overflow Output 1 An error flag indicating that the RX domaincrossing FIFO is currently overflowed. The RX domain-crossing FIFO transfers data from the PCS clock domain to the MAC clock domain. rg_overflow Output 1 An error flag indicating that the Reassembly FIFO is currently overflowed. The Reassembly FIFO is the receiver FIFO that feeds directly to the user data interface. Output RXFIFO_ADDR_ WIDTH The fill level of the Reassembly FIFO, in units of 64-bit words. The width of this signal is the value of the RXFIFO_ADDR_WIDTH parameter, which is 12 by default. You can use this signal to monitor when the RX Reassembly FIFO is empty. sop_cntr_inc Output 1 A pulse indicating that the 100G Interlaken IP core receiver user data interface received a startof-packet. You can use this signal to increment a count of SOPs the application observes on the receive interface. eop_cntr_inc Output 1 A pulse indicating that the 100G Interlaken IP core receiver user data interface received an end-of-packet. You can use this signal to increment a count of EOPs the application observes on the receive interface. rxfifo_fill_ level Altera Corporation 100G Interlaken MegaCore Function Signals Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core Management Interface 5-13 Related Information RXFIFO Address Width on page 8-2 Information about programming the depth of the Reassembly FIFO with the RXFIFO_ADDR_WIDTH parameter. 100G Interlaken IP Core Management Interface The 100G Interlaken IP core management interface allows you to communicate with IP core internal status and control registers. This interface manages the PMA (resets and serial loopback controls) and PCS control and status registers. This interface does not provide access to the hard PCS registers on the device. The management interface is a typical 32-bit memory-mapped register port. It complies with the Avalon Memory-Mapped (Avalon-MM) specification defined in the Avalon Interface Specifications. Table 5-6: 100G Interlaken IP Core Management Interface Signals Signal Name Direction Width (Bits) Description 100G Interlaken IP Core Management Interface Signals mm_clk Input 1 Management clock. Clocks the register accesses. It is also used for clock rate monitoring and some analog calibration procedures. You must run this clock at a frequency in the range of 100 MHz-125 MHz. mm_read Input 1 Read access to the register ports. mm_write Input 1 Write access to the register ports. mm_addr Input 16 Address to access the register ports. mm_rdata Output 32 When mm_rdata_valid is high, mm_rdata holds valid read data. mm_rdata_valid Output 1 Valid signal for mm_rdata. mm_wdata Input 32 When mm_write is high, mm_wdata holds valid write data. If you do not use the management interface, drive the management inputs as follows: * mm_clk must connect to a stable clock. However, the clock signal need not be of unusually high quality. * mm_read and mm_write must be tied to zero. 100G Interlaken MegaCore Function Signals Send Feedback Altera Corporation 5-14 UG-01128 2016.05.02 Device Dependent Signals If you use the management interface, drive the control lines as shown in the examples and observing the following constraints: * During a write operation, you must maintain the the mm_write signal asserted for at least two clock cycles. Back-to-back writes must be separated by at least one clock cycle. * During a read operation, you must maintain the mm_read signal asserted for at least two clock cycles. Back-to-back reads must be separated by at least one clock cycle. Figure 5-1: 100G Interlaken IP Core Management Interface Write Operation Shows the timing requirements for a write operation on the 100G Interlaken IP core management interface. mm_clk mm_write mm_addr[15:0] Don't Care 0x0012 0x0013 Don't Care mm_wdata[31:0] Don't Care wdata0 wdata1 Don't Care Figure 5-2: 100G Interlaken IP Core Management Interface Read Operation Shows the timing requirements for a read operation on the 100G Interlaken IP core management interface. The IP core asserts the mm_rdata_valid signal two cycles after the mm_read signal is asserted. mm_clk mm_read mm_addr[15:0] Don't Care 0x0000 0x0001 Don't Care mm_rdata_valid mm_rdata[31:0] Previous Value rdata0 rdata1 Related Information Avalon Interface Specifications Device Dependent Signals Some of the 100G Interlaken MegaCore function signals depend on the device that your variation targets. Variations that target an Arria V device or a Stratix V device have an interface to connect to an Altera Transceiver Reconfiguration Controller that you must instantiate outside the 100G Interlaken IP core for successful functioning in hardware. Variations that target an Arria 10 device have Arria 10-specific Altera Corporation 100G Interlaken MegaCore Function Signals Send Feedback UG-01128 2016.05.02 Transceiver Reconfiguration Controller Interface Signals 5-15 requirements to support the Arria 10 transceivers. The following 100G Interlaken IP core interfaces are device specific: Transceiver Reconfiguration Controller Interface Signals on page 5-15 Arria 10 External PLL Interface Signals on page 5-15 Arria 10 Transceiver Reconfiguration Interface Signals on page 5-16 Transceiver Reconfiguration Controller Interface Signals 100G Interlaken IP core variations that target an Arria V or a Stratix V device require an external reconfi guration controller to function correctly in hardware. 100G Interlaken IP core variations that target an Arria 10 device include a reconfiguration controller block and do not require an external reconfiguration controller. Table 5-7: 100G Interlaken IP Core Arria V and Stratix V Transceiver Reconfiguration Controller Interface Signals Signal Name Direction Width (Bits) Description reconfig_to_xcvr Input 70 bits per reconfi guration interface. Bus from the external transceiver reconfiguration controller to the 100G Interlaken IP core. The bus includes signals from multiple transceiver reconfigu ration interfaces. The reconfiguration controller has one interface to control each transceiver channel (one per Interlaken lane) plus one interface to control each TX PLL configured in the IP core. The width of each reconfiguration controller output reconfiguration interface is 70 bits. reconfig_from_xcvr Output 46 bits per reconfi guration interface Bus to the external transceiver reconfiguration controller from the 100G Interlaken IP core. The bus includes signals for multiple reconfiguration interfaces of the transceiver reconfiguration controller. The reconfiguration controller has one interface for each transceiver channel (one per Interlaken lane) plus one interface for each TX PLL configured in the IP core. The width of each reconfi guration controller input reconfiguration interface is 46 bits. Arria 10 External PLL Interface Signals 100G Interlaken IP core variations that target an Arria 10 device require an external transceiver PLL to function correctly in hardware. 100G Interlaken IP core variations that target an Arria V or Stratix V device include the transceiver PLLs and do not require that you configure any additional PLLs. 100G Interlaken MegaCore Function Signals Send Feedback Altera Corporation 5-16 UG-01128 2016.05.02 Arria 10 Transceiver Reconfiguration Interface Signals Table 5-8: 100G Interlaken IP Core Arria 10 External PLL Interface Signals Signal Name Direction Width (Bits) Description tx_serial_clk Input NUM_LANES High-speed clock for Arria 10 transceiver channel, provided from external TX PLL. tx_pll_locked Input 1 PLL-locked indication from external TX PLL. tx_pll_powerdown Output 1 Output signal from the IP core internal reset controller. The IP core asserts this signal to tell the external PLLs to power down. Related Information Adding the External PLL on page 2-13 Arria 10 Transceiver Reconfiguration Interface Signals The 100G Interlaken IP core Arria 10 transceiver reconfiguration interface allows you to communicate with Arria 10 hard PCS registers. This interface is available only in variations that target an Arria 10 device. You use this interface to reconfigure the transceiver and to take advantage of built-in transceiver features that the 100G Interlaken IP Core supports for IP core testing. The interface allows you to address a single register in a single transceiver channel at one time. The Arria 10 transceiver reconfiguration interface is a typical 32-bit memory-mapped register port. It complies with the Avalon Memory-Mapped (Avalon-MM) specification defined in the Avalon Interface Specifications. Table 5-9: 100G Interlaken IP Core Arria 10 Transceiver Reconfiguration Interface Signals Signal Name Direction Width (Bits) Description reconfig_clk Input 1 Arria 10 transceiver reconfiguration interface clock. reconfig_reset Input 1 Assert this signal to reset the Arria 10 transceiver reconfiguration interface. reconfig_read Input 1 Read access to the Arria 10 hard PCS registers. reconfig_write Input 1 Write access to the Arria 10 hard PCS registers. Altera Corporation 100G Interlaken MegaCore Function Signals Send Feedback UG-01128 2016.05.02 Arria 10 Transceiver Reconfiguration Interface Signals Signal Name reconfig_address Direction Input Width (Bits) 14 or 15 5-17 Description Address to access the hard PCS registers. This signal holds both the hard PCS register offset and the transceiver channel being addressed, in the following fields: * [8:0]: register offset in the hard PCS * [N:9]: Interlaken lane number * In 12-lane variations, N is 13 * In 24-lane variations, N is 14 reconfig_readdata Output 32 After user logic asserts the reconfig_read signal, when the IP core deasserts the reconfig_ waitrequest signal, reconfig_readdata holds valid read data. reconfig_waitrequest Output 1 Busy signal for reconfig_readdata. reconfig_writedata Input 32 When reconfig_write is high, reconfig_writedata holds valid write data. Related Information Avalon Interface Specifications Defines the Avalon-MM interface specification, including the behavior of the output signals and the expected behavior of the input signals. 100G Interlaken MegaCore Function Signals Send Feedback Altera Corporation 6 100G Interlaken IP Core Register Map 2016.05.02 UG-01128 Subscribe Send Feedback The 100G Interlaken IP core control registers are 32 bits wide and are accessible to you using the management interface, an Avalon-MM interface which conforms to the Avalon Interface Specifications. This table lists the registers available in the IP core. All unlisted locations are reserved. Table 6-1: 100G Interlaken IP Core Register Map Offset 9'h0 Name PCS_BASE R/W RO Description [31:8] - Constant "HSi" ASCII [7:0] - version number Despite its name, this register does not encode the hard PCS base address. 9'h1 LANE_COUNT RO Number of lanes 9'h2 TEMP_SENSE RO Device temperature according to the internal temperature sensing diode. [7:0] - the temperature in degrees Fahrenheit [15:8] - the temperature in degrees Celsius For example, when the temperature is 54 degrees Celsius (130 degrees Fahrenheit), the value of the register is 0x3682. To interpret this register value, you read 0x36 (decimal 54) to be the temperature in degrees Celsius, and you read 0x82 (decimal 130) to be the temperature in degrees Fahrenheit. This register is invalid in the following IP core variations: * Variations that target an Arria 10 device * Variations in which you turn off the hidden parameter Include Temp Sense 9'h3 ELAPSED_SEC RO [23:0] - Elapsed seconds since power up. The IP core calculates this value from the management interface clock (mm_clk) for diagnostic purposes. During continuous operation, this value rolls over every 194 days. (c) 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 6-2 UG-01128 2016.05.02 100G Interlaken IP Core Register Map Offset Name R/W Description 9'h4 TX_EMPTY RO [NUM_LANES-1:0] - Transmit FIFO status (empty) 9'h5 TX_FULL RO [NUM_LANES-1:0] - Transmit FIFO status (full) 9'h6 TX_PEMPTY RO [NUM_LANES-1:0] - Transmit FIFO status (partially empty) 9'h7 TX_PFULL RO [NUM_LANES-1:0] - Transmit FIFO status (partially full) 9'h8 RX_EMPTY RO [NUM_LANES-1:0] - Receive FIFO status (empty) 9'h9 RX_FULL RO [NUM_LANES-1:0] - Receive FIFO status (full) 9'hA RX_PEMPTY RO [NUM_LANES-1:0] - Receive FIFO status (partially empty) 9'hB RX_PFULL RO [NUM_LANES-1:0] - Receive FIFO status (partially full) 9'hC REF_KHZ (1) RO PLL reference clock frequency (kHz) If you turn off Include diagnostic features, this register is not available. 9'hD RX_KHZ(1) RO RX recovered clock frequency (kHz) If you turn off Include diagnostic features, this register is not available. 9'hE TX_KHZ (1) RO TX serial clock frequency (kHz) If you turn off Include diagnostic features, this register is not available. 9'hF LANE_PROFILE RO [NUM_LANES-1:0] - Mask delineating the transceivers this IP core uses on the device. For example, if the FPGA has 24 lanes on one side of the device and the IP core uses the bottom twelve transceivers, the mask would be 24'b000000_000000_111111_111111.. This register is not available in IP core variations that target an Arria 10 device. (1) Altera recommends that you use this register only during hardware operation. During simulation, you should not rely on the value in this register, because the amount of simulation time required for the IP core to provide consistent values in the REF_KHZ, RX_KHZ, and TX_KHZ registers is too long. Altera Corporation 100G Interlaken IP Core Register Map Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core Register Map Offset 9'h10 Name PLL_LOCKED R/W RO 6-3 Description In Arria 10 devices: [0] - Transmit PLL lock indication. In other device families: [Number of transceiver blocks-1:0] - Transceiver block transmit PLL n lock indication. One lock indicator per transceiver block. Bits that correspond to unused transceiver block PLLs are forced to 1. 9'h11 FREQ_LOCKED RO [NUM_LANES-1:0] - Clock data recovery is frequency locked on the inbound data stream 9'h12 LOOPBACK RW [NUM_LANES-1:0] - For each lane, write a 1 to activate internal TX to RX serial loopback mode, or write a 0 to disable the loopback for normal operation. 9'h13 RESET RW Bit 9 : 1 = Force lock to data mode Bit 8 : 1 =Force lock to reference mode Bit 7 : 1 = Synchronously clear the TX-side error counters and sticky flags Bit 6 : 1 = Synchronously clear the RX-side error counters and sticky flags Bit 5 : 1 =Program load mode: perform a sequence of DMA reads. Currently the IP core supports only the value of 1'b0, indicating a processor controls the read operations. Bit 4 : 1 = Ignore the RX analog reset Bit 3 : 1 = Reset the soft microcontroller Bit 2 : 1 = Reset the transmitter and the receiver Bit 1 : 1 = Reset the receiver Bit 0 : 1 =Ignore RX digital resets The normal operating state for this register is all zeroes, to allow automatic reset control. These bits are intended primarily for hardware debugging use. Bit 2 is a good general purpose soft reset. Bits 6 and 7 are convenient for monitoring long stretches of error-free operation. 9'h20 ALIGN RO Bit 12 : TX lanes are aligned Bit 0 : RX lanes are aligned. 9'h21 WORD_LOCK RO [NUM_LANES-1:0] - Word (block) boundaries have been identified in the RX stream. 9'h22 SYNC_LOCK RO [NUM_LANES-1:0] - Metaframe synchronization has been achieved. 100G Interlaken IP Core Register Map Send Feedback Altera Corporation 6-4 UG-01128 2016.05.02 100G Interlaken IP Core Register Map Offset 9'h23 Name CRC0 R/W RO Description 4 bit counters indicating CRC errors in lanes 7,6,5,4,3,2,1,0. These will saturate at F, and you clear them by setting bit 6 in the RESET register. If you turn off Include diagnostic features, this register is not available. 9'h24 CRC1 RO 4 bit counters indicating CRC errors in lanes 15,14,13,12,11,10,9,8. These will saturate at F, and you clear them by setting bit 6 in the RESET register. If you turn off Include diagnostic features, this register is not available. 9'h25 CRC2 RO 4 bit counters indicating CRC errors in lanes 23,22,21,20,19,18,17,16. These will saturate at F, and you clear them by setting bit 6 in the RESET register. If you turn off Include diagnostic features, this register is not available. 9'h27 SH_ERR RO [NUM_LANES-1:0] - Sticky flag indicating a sync header (framing bit) error has occurred in the corresponding RX lane since this bit was last cleared through the RESET register. 9'h28 RX_LOA RO Bit [0] - Sticky flag indicating loss of RX side lane-to-lane alignment since this bit was last cleared through the RESET register. Typically, the IP core asserts this bit in case of a catastrophic problem such as one or more lanes going down. 9'h29 TX_LOA RO Bit [0] - Sticky flag indicating loss of TX side lane to lane alignment since this bit was last cleared through the RESET register. Typically, the IP core asserts this bit in case of a TX FIFO underflow / overflow caused by a significant deviation from the expected data flow rate through the TX PCS. 9'h30 PCS_6SEL RO Transceiver block selection for PCS test bus. (Factory use only). If you turn off Include diagnostic features, this register is not available. Altera Corporation 100G Interlaken IP Core Register Map Send Feedback UG-01128 2016.05.02 100G Interlaken IP Core Register Map Offset 9'h31 Name PCS_LNSEL R/W RO 6-5 Description Lane selection within transceiver block for PCS test bus. (Factory use only). If you turn off Include diagnostic features, this register is not available. 9'h32 PCS_TB RO PCS test bus. (Factory use only). If you turn off Include diagnostic features, this register is not available. 9'h33 Reserved 9'h34 RX_PRBS_DONE RO [NUM_LANES-1:0] - Indicates whether enough bits have been received on the corresponding RX lane for one complete pass through the PRBS polynomial. If you turn off Include diagnostic features, this register is not available. 9'h35 RX_PRBS_ERR RO [NUM_LANES-1:0] - Sticky flag that indicates whether a PRBS error has occurred on the corresponding RX lane after RX_PRBS_DONE has attained the value of 1. If you turn off Include diagnostic features, this register is not available. 9'h36 RX_PRBS_COUNT RO [7:0] - This eight-bit counter holds the number of words that had PRBS errors across all lanes. Saturates at the value of 0xFF. If you turn off Include diagnostic features, this register is not available. 9'h37 RX_PRBS_CTRL RW Bit [0] - If you set this bit to the value of 1, the IP core clears the RX_PRBS_DONE, RX_PRBS_ERR, and RX_PRBS_ COUNT registers. Reset this bit to the value of 0 to capture new PRBS status. If you turn off Include diagnostic features, this register is not available. 9'h38 CRC32_ERR_INJECT RW [NUM_LANES-1:0] - When a bit has the value of 1, the IP core injects CRC32 errors on the corresponding TX lane. When it has the value of 0, the IP core does not inject errors on the TX lane. You must maintain each bit at the value of 1 for the duration of a Meta Frame, at least, to ensure that the IP core transmits at least one CRC32 error. If you turn off Include diagnostic features, this register is not available. 100G Interlaken IP Core Register Map Send Feedback Altera Corporation 6-6 UG-01128 2016.05.02 100G Interlaken IP Core Register Map Offset 9'h102 Name ERR_INJECT R/W RW Description Bit [0] - When you write the value of 1 to this register bit, the IP core TX MAC injects a single bit error in outgoing Interlaken communication. This bit error will cause one or possibly more CRC24 errors. Before you can inject a second error, you must write the value of 0 to this register bit. Altera recommends that you write the value of 1 and then write the value of 0 to inject a single bit error. If you turn off Include diagnostic features, this register is not available. 9'h122 CNT_ERR_TX RO Number of correctable errors in M20K memory in the TX MAC logic. If you turn off Enable M20K ECC support, this register is not available. 9'h123 CNT_UNCOR_TX RO Number of uncorrectable errors in M20K memory in the TX MAC logic. If you turn off Enable M20K ECC support, this register is not available. 9'h124 CNT_ERR_RX RO Number of correctable errors in M20K memory in the RX MAC logic. If you turn off Enable M20K ECC support, this register is not available. 9'h125 CNT_UNCOR_RX RO Number of uncorrectable errors in M20K memory in the RX MAC logic. If you turn off Enable M20K ECC support, this register is not available. Related Information Avalon Interface Specifications Altera Corporation 100G Interlaken IP Core Register Map Send Feedback 100G Interlaken IP Core Test Features 7 2016.05.02 UG-01128 Subscribe Send Feedback Depending on the features you turn on in the 100G Interlaken parameter editor, your 100G Interlaken IP core supports the following test features: Internal Serial Loopback Mode on page 7-1 The 100G Interlaken IP core supports an internal TX to RX serial loopback mode. External Loopback Mode on page 7-2 The 100G Interlaken IP core operates correctly in an external loopback configuration. PRBS Generation and Validation on page 7-2 CRC32 Error Injection on page 7-7 CRC24 Error Injection on page 7-8 Internal Serial Loopback Mode The 100G Interlaken IP core supports an internal TX to RX serial loopback mode. To turn on internal serial loopback: * Reset the IP core by asserting and then deasserting the active low reset_n signal. * After reset completes, set the value of bits [NUM_LANES-1:0] of the LOOPBACK register at offset 0x12 to all ones. Note: Refer to "IP Core Reset" for information about the required wait period for register access. * Monitor the RX lanes aligned bit (bit 0) of the ALIGN register at offset 0x20 or the rx_lanes_aligned output signal. After the RX lanes are aligned, the IP core is in internal serial loopback mode. Resetting the IP core turns off internal serial loopback. To turn off internal serial loopback: * Reset the IP core by asserting and then deasserting the active low reset_n signal. Resetting the IP core sets the value of bits [NUM_LANES-1:0] of the LOOPBACK register at offset 0x12 to all zeroes. * Monitor the RX lanes aligned bit (bit 0) of the ALIGN register at offset 0x20 or the rx_lanes_aligned output signal. After the RX lanes are aligned, the IP core is in normal operational mode. Related Information IP Core Reset on page 4-5 Describes the required delay from reset to successful register access attempts. (c) 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 7-2 UG-01128 2016.05.02 External Loopback Mode External Loopback Mode The 100G Interlaken IP core operates correctly in an external loopback configuration. To put the IP core in external loopback mode, connect the TX lanes to the RX lanes of the IP core. This mode does not require any special programming of the IP core. PRBS Generation and Validation The 100G Interlaken IP core supports generation and validation of several predetermined pseudo-random binary sequences (PRBS) for Interlaken link testing. This feature is available if you turn on Include diagnostic features in the 100G Interlaken parameter editor. Table 7-1: PRBS Polynomials Available in the 100G Interlaken IP Core Pattern Name Polynomial Defined in Interlaken Specification Available in 100G Interlaken IP Core Variations with Target Device Family Arria V or Stratix V Arria 10 PRBS7 x7 + x6 + 1 Yes Yes No PRBS9 x9 + x5 +1 No Yes Yes No No Yes +1 Yes Yes Yes PRBS31 x31 + x28 + 1 Yes Yes Yes PRBS15 x15 + x14 +1 PRBS23 x23 + x18 For instructions to activate and use the PRBS test feature in your 100G Interlaken IP core IP core, refer to one of the following two topics: Setting up PRBS Mode in Arria V and Stratix V Devices on page 7-2 Setting up PRBS Mode in Arria 10 Devices on page 7-4 Setting up PRBS Mode in Arria V and Stratix V Devices To enable the IP core to generate PRBS output, you must program the relevant hard PCS registers to enable the PRBS generator clock, to set the test_enable bit, and to select the PRBS polynomial. To enable the IP core to receive PRBS input, you must program the relevant hard PCS registers to enable the PRBS receiver clock, to set the test_enable bit, and to select the expected PRBS polynomial. If you perform your PRBS testing in loopback mode, you must enable the IP core to both generate and receive PRBS sequences. The PRBS feature is available only if you turn on Include diagnostic features in the 100G Interlaken parameter editor. This section describes the register values you must program. For instructions to program the registers that activate the PRBS test feature in your Arria V or Stratix V 100G Interlaken IP core, refer to the hard PCS register programming instructions in the Native PHY IP Core chapter for your target device family and in the Transceiver Reconfiguration Controller chapter of the Altera Transceiver PHY IP Core User Guide. Altera Corporation 100G Interlaken IP Core Test Features Send Feedback UG-01128 2016.05.02 Setting up PRBS Mode in Arria V and Stratix V Devices 7-3 Table 7-2: Programming the Hard PCS Registers in Arria V and Stratix V Devices To turn on the PRBS feature in the hard PCS, you must program the following hard PCS registers in the order shown, for each of the TX and RX sides. These registers are not accessible using the 100G Interlaken IP core Management interface. You must access these registers through the Transceiver Reconfiguration Controller that connects to the IP core. Ensure you set these register bits using a read-modify-write register access sequence (per register), to avoid modifying the other register fields. TX 1 2 3 RX 1 2 3 Register Offset 0x141 0x135 0x137 Register Offset 0x16D 0x15E 0x164 Bits Meaning Action [0] Invert TX channels [10] Enable PRBS7 [8] Enable PRBS23 [6] Enable PRBS9 [4] Enable PRBS31 [3] TX test enable Set this bit to the value of 1 to enable the PRBS pattern generator in the transmitter. [2] Enable TX PRBS clock Set this bit to the value of 1 to enable the TX PRBS clock. Bits Meaning Set this bit to the value of 0 to specify that the outgoing PRBS be inverted, or set this bit to the value of 1 to specify that the outgoing PRBS not be inverted. The default value of this register bit is 0. By default, the outgoing PRBS is inverted. Set one of these bits to the value of 1, and the others to the value of 0, to select the TX polynomial. Action [2] Invert RX channels Set this bit to the value of 0 to specify that the PCS should expect the incoming PRBS to be inverted, or set this bit to the value of 1 to specify that the PCS should not expect the incoming PRBS to be inverted. The default value of this bit is 0. In loopback mode, you should set this bit to match the setting in the PRBS transmitter. [14] Enable PRBS7 [13] Enable PRBS23 [12] Enable PRBS9 [11] Enable PRBS31 [10] RX test enable Set this bit to the value of 1 to enable the PRBS pattern verifier in the receiver. [10] Enable RX PRBS clock Set this bit to the value of 1 to enable the RX PRBS clock. Set one of these bits to the value of 1, and the others to the value of 0, to select the expected polynomial. After you activate an IP core that targets an Arria V or Stratix V device to generate PRBS output, it immediately begins transmitting PRBS output on the Interlaken link. After you enable the IP core to 100G Interlaken IP Core Test Features Send Feedback Altera Corporation 7-4 UG-01128 2016.05.02 Setting up PRBS Mode in Arria 10 Devices receive PRBS input, you can check the receive PRBS status in the 100G Interlaken IP core PRBS status registers (RX_PRBS_DONE, RX_PRBS_ERR, and RX_PRBS_COUNT). After your testing is complete, you must reset these register bits to their default values to enable normal operation. Related Information * 100G Interlaken IP Core Register Map on page 6-1 Describes the PRBS status registers. * PRBS Generation and Validation on page 7-2 Lists the supported PRBS polynomials. * Altera Transceiver PHY IP Core User Guide Setting up PRBS Mode in Arria 10 Devices To enable the IP core to generate PRBS output, for each Interlaken lane, you must program the relevant hard PCS registers to enable the PRBS generator clock, to set the test_enable bit, and to select the PRBS polynomial. To enable the IP core to receive PRBS input, for each Interlaken lane, you must program the relevant hard PCS registers to enable the PRBS receiver clock and to select the expected PRBS polynomial, in addition to some bookkeeping tasks. If you perform your PRBS testing in loopback mode, you must enable the IP core to both generate and receive PRBS sequences. After you set the hard PCS registers for PRBS mode, you must perform a soft reset of the transceiver. The PRBS feature is available only if you turn on Include diagnostic features in the 100G Interlaken parameter editor. This section describes the register values you must program. For instructions to program the registers that activate the PRBS test feature in your Arria 10 100G Interlaken IP core, refer to the hard PCS register information in the Arria 10 Transceiver PHY User Guide. You program the hard PCS registers using the 100G Interlaken IP core Arria 10 transceiver reconfiguration interface. Table 7-3: Programming the Hard PCS Registers in Arria 10 Devices To turn on the PRBS feature in the hard PCS for IP core variations that target an Arria 10 device, you must program the following hard PCS registers in the order shown, for each of the TX and RX sides. These registers are not accessible using the 100G Interlaken IP core management interface. You must access these registers through the Arria 10 transceiver reconfiguration interface of the 100G Interlaken IP core. Ensure you set these register bits using a read-modify-write register access sequence (per register), to avoid modifying the other register fields. TX 1 Register Offset 0x6 Altera Corporation Bits Meaning Action [2:0] TX test enable Set this field to the value of 3'b100 to enable the PRBS pattern generator in the transmitter. [3] PRBS width select Set this bit to the value of 0 to specify that the PRBS width is 64 bits. [7:6] Enable TX PRBS clock Set this field to the value of 2'b01 to enable the TX PRBS clock. 100G Interlaken IP Core Test Features Send Feedback UG-01128 2016.05.02 Setting up PRBS Mode in Arria 10 Devices TX 2 3 RX 1 Register Offset Bits Meaning [2] Invert TX channels [5] Enable PRBS9 [6] Enable PRBS15 [7] Enable PRBS23 [4] Enable PRBS31 0x7 0x8 Register Offset Bits Meaning Action Set this bit to the value of 0 to specify that the outgoing PRBS be inverted, or set this bit to the value of 1 to specify that the outgoing PRBS not be inverted. The default value of this register field is 0. By default, the outgoing PRBS is inverted. Set one of these bits to the value of 1, and the others to the value of 0, to select the TX polynomial. Action [4] Invert RX channels Set this bit to the value of 0 to specify that the PCS should expect the incoming PRBS to be inverted, or set this bit to the value of 1 to specify that the PCS should not expect the incoming PRBS to be inverted. The default value of this bit is 0. In loopback mode, you should set this bit to match the setting in the PRBS transmitter. [7] Enable RX PRBS clock Set this bit to the value of 1 to enable the RX PRBS clock. 0xA 100G Interlaken IP Core Test Features Send Feedback 7-5 Altera Corporation 7-6 UG-01128 2016.05.02 Setting up PRBS Mode in Arria 10 Devices RX 2 3 4 Register Offset Bits Meaning [1] Enable 10G PCS mode Set this bit to the value of 1 to specify the PCS is in 10G PCS mode. [3:2] Verifier counter threshold Set this field to the value your design requires to ensure adequate lead time before the PRBS checker begins counting PRBS errors. The field value specifies the wait time in number of clk_rx_common clock cycles. A counter begins counting clk_rx_ common clock cycles after the soft reset, and triggers the start of PRBS checking when the specified threshold is reached. This field has the following valid values: 0xB 0xC 0x13F Action * 2'b00--Specifies the counter threshold (the wait time) is 127. * 2'b01--Specifies the counter threshold is 255. * 2'b10--Specifies the counter threshold is 511. * 2'b11--Specifies the counter threshold is 1023. [5] Enable PRBS9 [6] Enable PRBS15 [7] Enable PRBS23 [0] Enable PRBS31 [1] Confirm 10G PCS mode Set this bit to the value of 1 to confirm the PCS is in 10G mode. [3] PRBS width select Set this bit to the value of 0 to specify that the PRBS width is 64 bits. [3:0] RX Deserializer width select Set this field to the value of 4'b1110 to specify that the data width after deserializa tion is 64 bits. Set one of these bits to the value of 1, and the others to the value of 0, to select the expected polynomial. After you enable the IP core to generate or receive PRBS output, by setting the relevant register field values for each Interlaken lane, you must perform a soft reset of the transceiver transmitters and receivers. To perform a soft reset of the transceiver transmitters and receivers, on the 100G Interlaken IP core management interface, program bit [2] of the 100G Interlaken IP core RESET register at offset 0x13 with the value of 1. On the following mm_clk cycle, or later, program the bit 0x13[2] with the value of 0 to clear the reset. After you reset the transceivers and subsequently clear the reset bit, the IP core immediately begins transmitting PRBS output on the Interlaken link. You can check the receive PRBS status in the 100G Interlaken IP core PRBS status registers (RX_PRBS_DONE, RX_PRBS_ERR, and RX_PRBS_COUNT). After your testing is complete, you must reset these register bits to their default values and perform the soft reset to enable normal operation. Altera Corporation 100G Interlaken IP Core Test Features Send Feedback UG-01128 2016.05.02 CRC32 Error Injection 7-7 Related Information * 100G Interlaken IP Core Register Map on page 6-1 Describes the PRBS status registers and the soft reset register. * Arria 10 Transceiver Reconfiguration Interface Signals on page 5-16 Describes the interface to program the Arria 10 hard PCS registers, including the information you need to address the registers for each individual lane. * 100G Interlaken IP Core Management Interface on page 5-13 Describes the interface to program the 100G Interlaken IP core registers, including the RESET register. * PRBS Generation and Validation on page 7-2 Lists the supported PRBS polynomials. * Arria 10 Transceiver PHY User Guide Information about the Arria 10 transceiver reconfiguration interface. * Arria 10 Transceiver Registers Information about the Arria 10 transceiver registers. CRC32 Error Injection The 100G Interlaken IP core supports the injection of CRC32 errors on the Interlaken link for validation of the Interlaken link partner's error handling, and for validation of this IP core's error handling in a loopback configuration. Variations that target an Arria V or Stratix V device require that you first enable the feature in the hard PCS; variations that target an Arria 10 device do not require this step. This feature is available if you turn on Include diagnostic features in the 100G Interlaken parameter editor. To enable the CRC32 error injection feature in your 100G Interlaken IP core that targets an Arria V or Stratix V device, set the value of bit [15] of the hard PCS register at offset 0x138 (offset 0xC from the hard PCS base address of 0x12C) to the value of 1. Ensure you set the register bit using a read-modify-write register access sequence, to avoid modifying the other register fields. This step is not necessary in 100G Interlaken IP core devices that target an Arria 10 device, because CRC32 error injection is enabled by default in these variations. For instructions to program the hard PCS registers in Arria V and Stratix V devices, refer to the Native PHY IP Core chapter for your target device family and to the Transceiver Reconfiguration Controller chapter of the Altera Transceiver PHY IP Core User Guide. After you enable the IP core to inject CRC32 errors in the output to the Interlaken link, you can turn on the feature using the 100G Interlaken IP core CRC32_ERR_INJECT register. You must maintain each register bit at the value of 1 for the duration of a Meta Frame, at least, to ensure that the IP core transmits at least one CRC32 error on the corresponding lane. After your testing is complete, in Arria V and Stratix V devices, you must reset the hard PCS register bit to its default value of zero to enable normal operation. The 100G Interlaken IP core CRC32 error injection feature does not keep a count of the errors injected. Related Information * 100G Interlaken IP Core Register Map on page 6-1 Describes the CRC32_ERR_INJECT register. * Altera Transceiver PHY IP Core User Guide 100G Interlaken IP Core Test Features Send Feedback Altera Corporation 7-8 CRC24 Error Injection UG-01128 2016.05.02 CRC24 Error Injection The 100G Interlaken IP core supports the injection of CRC24 errors on the Interlaken link for validation of the Interlaken link partner's error handling, and for validation of this IP core's error handling in a loopback configuration. This feature is available if you turn on Include diagnostic features in the 100G Interlaken parameter editor. To force the IP core to inject a bit error in the output to the Interlaken link, you write the value of 1 to bit [0] of the 100G Interlaken IP core ERR_INJECT register at offset 0x102. This change to the register field value forces the IP core to inject a single bit error, which will cause one or possibly more CRC24 errors. Before you can inject a second bit error, you must write the value of 0 to the register. Altera recommends that you write the value of 1 and then the value of 0 to inject a single bit error, rather than waiting until you want to inject a second error before writing the value of 0 to clear the register. Altera Corporation 100G Interlaken IP Core Test Features Send Feedback 8 Advanced Parameter Settings 2016.05.02 UG-01128 Subscribe Send Feedback Advanced users can further customize the 100G Interlaken IP core by modifying hidden parameters that are not displayed in the 100G Interlaken parameter editor. These parameters can only be modified in the Verilog RTL instantiation in the generated ilk_core.sv file and the instantiation of the 100G Interlaken IP core in the top level design file. The following topics describe the hidden parameters and tell you how to modify their values. Hidden Parameters on page 8-1 Modifying Hidden Parameter Values on page 8-3 Hidden Parameters The advanced parameters affect the behavior of the 100G Interlaken MegaCore function. Note: Altera recommends that you do not modify any RTL parameters that are not listed here. Some undocumented modifications might overwrite settings you specify in the parameter editor. To customize your 100G Interlaken MegaCore function, you can modify parameters to specify the following properties: Include Temp Sense on page 8-1 RXFIFO Address Width on page 8-2 SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping) on page 8-2 Include Temp Sense The Include Temp Sense parameter specifies whether the IP core includes logic to sense the device's case temperature. If the value is set to 1, the IP core is configured with internal temperature sensing. If the value is set to 0, this logic is synthesized away. This parameter is not available in IP core variations that target an Arria 10 device. The default value of this parameter is 1. Related Information Modifying Hidden Parameter Values on page 8-3 (c) 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 8-2 UG-01128 2016.05.02 RXFIFO Address Width RXFIFO Address Width The RXFIFO Address Width parameter specifies the number of bits in the address (offset) of an entry in the RX Reassembly FIFO. The number of bits is log2 of the depth of this FIFO. Each RX Reassembly FIFO entry is a 64-bit word. The default value for the RXFIFO Address Width parameter is 12, specifying this FIFO can hold 212 (==4K) 64-bit words. Adjusting this parameter may affect your ability to close timing for your design. However, you can adjust this parameter subject to the successful closure of the timing. Related Information Modifying Hidden Parameter Values on page 8-3 SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping) The 100G Interlaken IP core supports a lane reversal feature (lane swapping). Lane swapping parameters determine the order in which blocks are distributed and gathered from the lanes. The 100G Interlaken IP core provides the following two options for the lane order: * Straight Lane order. The transmitter sends Interlaken blocks sequentially across the lanes starting with the top lane, ending with Lane 0. The receiver takes in Interlaken blocks starting with the top lane, ending with Lane 0. Figure 8-1: Straight Lane Order Lane N . . . Lane 2 Lane 1 Lane 0 * Swapped Lane order. The transmitter sends Interlaken blocks sequentially across the lanes starting with Lane 0, ending with Lane N. The receiver takes in Interlaken blocks starting with Lane 0, ending with Lane N. Altera Corporation Advanced Parameter Settings Send Feedback UG-01128 2016.05.02 Modifying Hidden Parameter Values 8-3 Figure 8-2: Swapped Lane Order Lane 0 Lane 1 Lane 2 . . . Lane N Two parameters determine lane order: SWAP_TX_LANES SWAP_RX_LANES When a parameter is set to 0, the 100G Interlaken IP core implements the Straight Lane order. When a parameter is set to 1, the 100G Interlaken IP core implements the Swapped Lane order. The TX and RX parameters are independent and can be set separately. To conform with the Interlaken specification, the default value of SWAP_TX_LANES and SWAP_RX_LANES is 1. Note: Running traffic with incompatible lane swapping configuration results in CRC24 errors and incorrect data at the receiver. Related Information Modifying Hidden Parameter Values on page 8-3 Modifying Hidden Parameter Values To modify the value of a hidden parameter, you must edit one or more generated files. Every time you regenerate the 100G Interlaken IP core, the files are overwritten and you must edit them again. Table 8-1: Files to Edit to Modify the Value of a Hidden Parameter In each entry, the first file controls the RTL parameter value for synthesis, and the second file controls the RTL parameter value for simulation. Parameter RXFIFO_ADDR_WIDTH Arria 10 Variations <instance name>/synth/ <instance name>.v <instance name>/sim/ <instance name>.v Advanced Parameter Settings Send Feedback Other Variations <instance name>.v <instance name>_ sim/<instance name>.v Altera Corporation 8-4 UG-01128 2016.05.02 Modifying Hidden Parameter Values Parameter SWAP_TX_LANES SWAP_RX_LANES INCLUDE_TEMP_SENSE Altera Corporation Arria 10 Variations <instance name>/ilk_core_ <version>/synth/ilk_core.sv <instance name>/ilk_core_ <version>/sim/ilk_core.sv Other Variations <instance name>/ilk_core.sv <instance name>_sim/ilk_core.sv -- Advanced Parameter Settings Send Feedback 9 Out-of-Band Flow Control in the 100G Interlaken MegaCore Function 2016.05.02 UG-01128 Subscribe Send Feedback The 100G Interlaken MegaCore function includes logic to provide the out-of-band flow control function ality described in the Interlaken Protocol Specification, Revision 1.2, Section 5.3.4.2. This optional feature is intended for applications that require transmission rate control. Figure 9-1: Out-of-Band Flow Control Block Interface This figure lists the signals on the four interfaces of the out-of-band flow control block. double_fc_clk double_fc_arst ena_status lane_status link_status calendar Out-of-Band Flow Control Application Signals status_update lane_status link_status status_error calendar calendar_update calendar_error sys_clk sys_arst TX Out-of-Band Flow Control tx.fc_clk tx.fc_sync tx.fc_data Out-of-Band Flow Control Interface RX Out-of-Band Flow Control rx.fc_clk rx.fc_sync rx.fc_data The out-of-band flow control block is provided as two separate modules that can be stitched to the 100G Interlaken IP core and user logic. You can optionally instantiate these blocks in your own custom logic. To enable the use of these out-of-band modules, the signals on the far left side of the figure must be connected to user logic, and the signals on the far right side of the figure should be connected to the complementary flow control blocks of the Interlaken link partner. You must connect the out-of-band flow control receive and transmit interface signals to device pins. Out-of-Band Flow Control Block Clocks on page 9-2 TX Out-of-Band Flow Control Signals on page 9-2 RX Out-of-Band Flow Control Signals on page 9-4 (c) 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 9-2 UG-01128 2016.05.02 Out-of-Band Flow Control Block Clocks Related Information Interlaken Protocol Specification, Revision 1.2 Out-of-Band Flow Control Block Clocks Table 9-1: 100G Interlaken MegaCore Function Out-of-Band Flow Control Block Clocks Clock Name Interface Direction Recommende d Frequency (MHz) Description RX fc_clk RX Out-ofband Input 100 Clocks the incoming out-of-band flow control interface signals described in the Interlaken specification. This clock is received from an upstream TX out-of-band flow control block associated with the Interlaken link partner. The recommended frequency for the RX fc_clk clock is 100 MHz, which is the maximum frequency allowed by the Interlaken specification. TX fc_clk TX Out-ofband Output 100 Clocks the outgoing out-of-band flow control interface signals described in the Interlaken specification. This clock is generated by the out-of-band flow control block and sent to a downstream RX out-of-band flow control block associated with the Interlaken link partner. The frequency of this clock must be half the frequency of the double_fc_clk clock. The recommended frequency for the TX fc_clk clock is 100 MHz, which is the maximum frequency allowed by the Interlaken specification. RX Application Input 200 Clocks the outgoing calendar and status informa tion on the application side of the block. The frequency of this clock must be at least double the frequency of the RX input clock fc_clk. Therefore, the recommended frequency for the sys_clk clock is 200 MHz. TX Application Input 200 Clocks the incoming calendar and status informa tion on the application side of the block. The frequency of this clock must be double the frequency of the TX output clock fc_clk. Therefore, the recommended frequency for the double_fc_clk clock is 200 MHz. sys_clk double_ fc_clk TX OutofBand Flow Control Signals The transmit out-of-band flow control interface receives calendar and status information, and transmits flow-control clock, data, and sync signals. The TX Out-of-Band Flow Control Interface Signals table describes the transmit out-of-band flow control interface signals specified in the Interlaken Protocol Altera Corporation Out-of-Band Flow Control in the 100G Interlaken MegaCore Function Send Feedback UG-01128 2016.05.02 TX OutofBand Flow Control Signals 9-3 Specification, Revision 1.2. The TX Out-of-Band Flow Control Block Signals for Application Use table describes the signals on the application side of the TX out-of-band flow control block. Table 9-2: TX Out-of-Band Flow Control Interface Signals Signal Name Direction Width (Bits) Description fc_clk Output 1 Output reference clock to a downstream out-of-band RX block. Clocks the fc_data and fc_sync signals. You must connect this signal to a device pin. fc_data Output 1 Output serial data pin to a downstream out-of-band RX block. You must connect this signal to a device pin. fc_sync Output 1 Output sync control pin to a downstream out-of-band RX block. You must connect this signal to a device pin. Table 9-3: TX Out-of-Band Flow Control Block Signals for Application Use Signal Name Direction Width (Bits) Description Input 1 Input 1 Asynchronous reset for the out-of-band TX block. ena_status Input 1 Enable transmission of the lane status and link status to the downstream out-of-band RX block. If this signal is asserted, the lane and link status information is transmitted on fc_data. If this signal is not asserted, only the calendar information is transmitted on fc_data. lane_status Input Number of Lanes Lane status to be transmitted to a downstream out-of-band RX block if ena_status is asserted. Width is the number of lanes. link_status Input 1 Link status to be transmitted to a downstream out-of-band RX block if ena_status is asserted. calendar Input 16 Calendar status to be transmitted to a downstream out-of-band RX block. double_fc_clk double_fc_ arst Reference clock for generating the flow control output clock fc_clk. The frequency of the double_fc_clk clock must be double the intended frequency of the TX fc_clk output clock. Related Information Interlaken Protocol Specification, Revision 1.2 Out-of-Band Flow Control in the 100G Interlaken MegaCore Function Send Feedback Altera Corporation 9-4 UG-01128 2016.05.02 RX Out-of-Band Flow Control Signals RX Out-of-Band Flow Control Signals The receive out-of-band flow control interface receives input flow-control clock, data, and sync signals and sends out calendar and status information. The RX Out-of-Band Flow Control Interface Signals table describes the receive out-of-band flow control interface signals specified in the Interlaken Protocol Specifi cation, Revision 1.2. The RX Out-of-Band Flow Control Block Signals for Application Use describes the signals on the application side of the RX out-of-band flow control block. Table 9-4: RX Out-of-Band Flow Control Interface Signals Signal Name Direction Width (Bits) Description fc_clk Input 1 Input reference clock from an upstream out-of-band TX block. This signal clocks the fc_data and fc_sync signals. You must connect this signal to a device pin. fc_data Input 1 Input serial data pin from an upstream out-of-band TX block. You must connect this signal to a device pin. fc_sync Input 1 Input sync control pin from an upstream out-of-band TX block. You must connect this signal to a device pin. Table 9-5: RX Out-of-Band Flow Control Block Signals for Application Use Signal Name Direction Width (Bits) Description sys_clk Input 1 Reference clock for capturing RX calendar, lane status, and link status. Frequency must be at least double the frequency of the TX fc_clk input clock. sys_arst Input 1 Asynchronous reset for the out-of-band RX block. status_update Output 1 Indicates a new value without CRC4 errors is present on at least one of lane_status or link_status in the current sys_clk cycle. The value is ready to be read by the application logic. lane_status Output Number of Lane status bits received from an upstream out-of-band Lanes TX block on fc_data. Width is the number of lanes. link_status Output 1 Link status bit received from an upstream out-of-band TX block on fc_data. status_error Output 1 Indicates corrupt lane or link status. A new value is present on at least one of lane_status or link_status in the current sys_clk cycle, but the value has at least one CRC4 error. Altera Corporation Out-of-Band Flow Control in the 100G Interlaken MegaCore Function Send Feedback UG-01128 2016.05.02 RX Out-of-Band Flow Control Signals Signal Name Direction Width (Bits) 9-5 Description calendar Output 16 Calendar bits received from an upstream out-of-band TX block on fc_data. calendar_update Output 1 Indicates a new value without CRC4 errors is present on calendar in the current sys_clk cycle. The value is ready to be read by the application logic. calendar_error Output 1 Indicates corrupt calendar bits. A new value is present calendar in the current sys_clk cycle, but the value has at least one CRC4 error. Related Information Interlaken Protocol Specification, Revision 1.2 Out-of-Band Flow Control in the 100G Interlaken MegaCore Function Send Feedback Altera Corporation A Performance and Fmax Requirements for 100G Ethernet Traffic 2016.05.02 UG-01128 Subscribe Send Feedback To achieve 100G Ethernet line rates through the application interface of your 100G Interlaken IP core, you must run the transmit side and receiver side user interface clocks tx_usr_clk and rx_usr_clk at the following minimum required operating frequency: * 300 MHz in single segment mode and in 24 lane variations(2) * 225 MHz in 12 lane variations in dual segment mode The following discussion describes the packet rate calculation that supports this requirement. Figure A-1: Interlaken Ethernet Packet To transmit a minimum size (64-byte) Ethernet packet, the Interlaken link transmitter must send 672 bits of data. Preamble 8 Bytes Minimum Packet 64 Bytes Interpacket Gap 12 Bytes 672 Bits To support an Ethernet line rate of 100Gb/s, the Interlaken link must process 1000 bits in 10ns. The following calculation derives the required clock frequency. 100 x 1,000,000,000 bits/sec .. 672 = 148.8 million packets/sec 150 million packets/sec This packet rate requires that the user interface handle one packet per cycle if the operating clock runs at 150 MHz, or one packet per two cycles if the operating clock runs at 300 MHz. In dual segment mode, because the final cycle of one packet can overlap with the initial cycle of another packet, the operating clock frequency requirements are derived from the average number of cycles required for a single packet in back-to-back traffic. The calculations that follow show that the minimum operating clock frequency in dual segment mode is 225 MHz. (2) The restriction to a minimum of 300 MHz in dual segment mode in 24 lane variations is an artifact of the clocking scheme in this IP core. (c) 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered A-2 UG-01128 2016.05.02 Performance and Fmax Requirements for 100G Ethernet Traffic The following figures explain the derivation of the minimum frequency requirements. Figure A-2: Packet Processing Requirements in Single Segment Mode 64 Bytes at 300 MHz 512 64 Bytes Idle 65 - 128 Bytes 512 64 Bytes 1 1 - 64 Bytes 129 - 192 Bytes in 10 ns 512 64 Bytes 2 64 Bytes 1 - 64 Bytes 3 A 65-byte packet comprises (65 + 20) x 8 = 680 bits. Therefore, for traffic that consists mainly of 65-byte packets, the most inefficient traffic possible, the user interface must handle: 100 x 1,000,000,000 bits/sec / 680 = 147 Million packets/sec, or one packet every 6.8 ns. Case 2 in the single segment mode figure shows that the user interface requires two cycles to process each 65-byte packet. At 300 MHz, two cycles take 6.66 ns, which is a sufficiently small amount of time. A 129-byte packet comprises (129 + 20) x 8 = 1192 bits. Therefore, for traffic that consists mainly of 129byte packets, the user interface must handle: 100 x 1,000,000,000 bits/sec / 1192 = 83.9 Million packets/sec, or one packet every 11.9 ns. Case 3 in the single segment mode figure shows that the user interface requires three cycles to process each 129-byte packet. At 300 MHz, three cycles take 10 ns, which is a sufficiently small amount of time. The same calculations applied to lower frequencies yield an average time per packet that is not sufficiently short. Therefore, 300 MHz is the recommended frequency for the two user data transfer interface clocks in your single segment mode 100G Interlaken IP core. For logistical clocking reasons, this frequency is also recommended for your 24-lane variation in dual segment mode. Figure A-3: Packet Processing Requirements in Dual Segment Mode 512 Two 65 Byte Packets at 225 MHz 1 Byte 64 33 32 Bytes Bytes Bytes (next pkt) 1 512 64 Bytes Two 129 Byte Packets in 22.23 ns 1 Byte 64 64 32 Bytes Bytes Bytes (next pkt) 33 Bytes 2 In dual segment mode, a 65-byte packet or a 129-byte packet can be followed in the same cycle by the first 32 bytes of the following packet. The table summarizes the numbers illustrated in the figure. Altera Corporation Performance and Fmax Requirements for 100G Ethernet Traffic Send Feedback UG-01128 2016.05.02 Performance and Fmax Requirements for 100G Ethernet Traffic A-3 Table A-1: Packet Processing Time in Dual Segment Mode at 225 MHz The time to process two consecutive packets at 225 MHz is simply the time taken by the relevant number of cycles at 225 MHz. The required maximum time per packet is derived in the discussion of the requirements for single segment mode. Processing Time Packet Size (Bytes) Number of Cycles for Two Consecutive Packets At 225 MHz: Time for Two Consecutive Packets (ns) Average Time per Packet (ns) Required Maximum Time per Packet (ns) (derived earlier) 65 3 13.33 6.66 6.8 129 5 22.23 11.12 11.9 Both of the average times per packet are sufficiently short, based on the packets per second requirements for the different sized packets (6.66 < 6.8 and 11.12 < 11.9). The same calculations applied to lower frequencies yield an average time per packet that is not sufficiently short. Therefore, 225 MHz is the recommended frequency for the two user data transfer interface clocks in your 12-lane, dual segment mode 100G Interlaken IP core. Performance and Fmax Requirements for 100G Ethernet Traffic Send Feedback Altera Corporation Additional Information B 2016.05.02 UG-01128 Subscribe Send Feedback This section provides additional information about the document and Altera. 100G Interlaken MegaCore Function User Guide Archives If an IP core version is not listed, the user guide for the previous IP core version applies. IP Core Version User Guide 15.1 100G Interlaken MegaCore Function User Guide 15.1 15.0 100G Interlaken MegaCore Function User Guide 15.0 14.1 100G Interlaken MegaCore Function User Guide 14.1 Document Revision History Table B-1: 100G Interlaken MegaCore Function User Guide Revision History Date 2016.05.02 ACDS Version 16.0 Changes Made * Added a new topic titled Creating a SignalTap II Debug File to Match Your Design Hierarchy. * Removed callouts to set_global_assignment -name DISABLE_ EMBEDDED_TIMING_CONSTRAINT ON. * Removed the chapter Arria 10 Hardware Example Design and 100G Interlaken IP Core Testbench, instead refer to the 100G Interlaken Example Design User Guide. (c) 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered B-2 UG-01128 2016.05.02 Document Revision History Date ACDS Version Changes Made 2015.11.02 15.1 * Updated for new Quartus Prime software v15.1 release. * Added new Enable Native XCVR PHY ADME parameter for Arria 10 variations. * Updated behavior of irx_err signal. In previous releases, this signal was asserted synchronously with irx_eop. Now it is asserted synchronously with irx_eob, and is only asserted if the IP core can identify the burst with which the error is associated. * Updated with change in process to generate legacy testbench. * Added new Arria 10 hardware example design. * Updated generated directory structure for non-Arria 10 variations and location of testbench files for all variations. * Corrected descriptions of TX out-of-band flow control interface signals fc_clk, fc_data, and fc_sync to indicate they are intended to connect to an upstream RX out-of-band block rather than a downstream block. * Corrected 100G Interlaken IP Core Transceiver Initialization Sequence figure in IP Core Reset on page 4-5. Corrected descriptions of use of reset_n signal to indicate user must assert (low) and deassert (raise) the signal to initiate the reset sequence, in Internal Serial Loopback Mode on page 7-1. 2015.05.04 15.0 * Added new TX scrambler seed parameter in new section TX Scrambler Seed on page 3-6. Previously this parameter was hidden (SCRAM_CONST) and unavailable for Arria 10 devices. In the IP core version 15.0 and later, you must modify the scrambler seed from the parameter editor. * Improved description of itx_ifc_err output signal in 100G Interlaken IP Core User Data Transfer Interface Signals on page 5-4. * Improved description of itx_hungry output signal in 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals on page 5-9. * Updated filenames for hidden parameter editing to include the filenames for Arria 10 variations, in Modifying Hidden Parameter Values on page 8-3. 2014.12.15 14.1 * Updated release-specific information for the software release v14.1, including new resource utilization numbers and new Arria 10 speed grade notation. * Updated for new Quartus II IP Catalog, which replaces the MegaWizard Plug-In Manager starting in the Quartus II software v14.0. Changes are located primarily in Getting Started With the 100G Interlaken IP Core chapter. Reordered the chapter to accommodate the new descriptions. * Fixed speed grade information for Arria 10 devices in Device Speed Grade Support section. * Removed mm_clk_locked signal. Signal is removed in the IP core v14.0 and later. * Corrected management interface read operation waveform and require ments. In the IP core v13.1 and later, the read data is valid two cycles after mm_read is asserted, not one cycle as was previously shown. Altera Corporation Additional Information Send Feedback UG-01128 2016.05.02 Document Revision History Date ACDS Version B-3 Changes Made * Corrected instructions to connect the external TX PLL to include the tx_ cal_busy signal, and added example figure to illustrate the required connections between the IP core and an ATX PLL. Changes are located in Adding the External PLL section. * In relevant parameter description sections, removed note to ignore the compilation warnings if you turn off any of the following parameters. The issue is fixed in the SDC file in the IP core version 14.0 and later. * * * * * * * December 2013 Additional Information Send Feedback * Include advanced error reporting and handling * Enable M20K ECC support * Include diagnostic features * Include in-band flow control functionality Removed CNTR_BITS RTL parameter. Parameter is removed in the IP core v14.0 and later. Added information to IP Core Reset section about the current required wait from reset to successful register access in IP Core Reset section. Corrected width of reconfig_waitrequest signal to one bit. This signal has been a single bit in all versions that support Arria 10 devices, starting with the IP core version 13.1 Arria 10 Edition. Corrected the text that describes the trade-offs between enabling and disabling the Enable M20K ECC support parameter. Added information about turning on and off loopback mode in two new sections, External Loopback Mode and Internal Serial Loopback Mode, in IP Core Test Features chapter. Clarified that the testbench and example design are generated only if you specify the IP core synthesis and simulation models are in Verilog HDL. The IP core does not support VHDL models, despite the fact that in the IP core v14.0 and later, the parameter editor appears to offer that option. Fixed assorted typos and formatting issues. 13.1 Arria 10 * Added preliminary support for Arria 10 devices. Edition * Documented features of new Arria 10 variations: (2013.12. 02) * User logic must configure external PLLs. * IP core includes reconfiguration controller. * IP core includes new Avalon-MM interface to program Arria 10 Native PHY IP core registers. * IP core does not support all of the hidden parameters. * IP core does not support temperature register and other registers related to unsupported parameters. * IP core provides a different process to enable the PRBS and CRC32 error injection testing features in Arria 10 variations. * Corrected recommended simulation value for Meta frame length in words parameter, from 64 (an unsupported value) to 128 (the minimum supported value). Altera Corporation B-4 UG-01128 2016.05.02 Document Revision History Date November 2013 ACDS Version Changes Made 13.1 * Documented change from Received data format to Data format (2013.11.04) parameter. If you select Single segment mode, the IP core can no longer handle incoming dual segment traffic on the TX client data interface. * Added information about the four new parameters: * Include advanced error reporting and handling * Enable M20K ECC support * Include diagnostic features * Include in-band flow control functionality * Documented new ECC feature for Arria 10 and Stratix V device M20K memory blocks, including four new registers: * * * * * * May 2013 13.0 * Documented the new dual segment mode, including: (2013.05.06) * * * * * * Altera Corporation * CNT_ERR_TX * CNT_UNCOR_TX * CNT_ERR_RX * CNT_UNCOR_RX Documented new diagnostic feature: CRC24 error injection, including the new ERR_INJECT register. Added resource utilization information. Updated IP core generation instructions to indicate the MegaWizard Plug-In Manager no longer prompts the user to generate or not generate the example design. Instead, the example design is generated in all cases. Provided additional information about TEMP_SENSE register. Corrected typo in width of itx_hungry signal. Added OpenCore Plus feature support in Installation and Licensing section. * New Received data format parameter in the 100G Interlaken parameter editor. * Changed user data transfer signal widths. * Added new itx_ifc_err signal. * Expanded Fmax requirements discussion to include the dual segment mode case. Documented the new Transfer mode selection parameter in the 100G Interlaken parameter editor. Previously this parameter was hidden (TX_ PKTMOD_ONLY). Documented new error handling features, including changes to and renaming of irx_crc_24_err signal to irx_err. Added PRBS support. Changes include addition of new hard PCS registers. Added support for CRC-32 error injection. Updated device speed grade information. Modified document format. Additional Information Send Feedback UG-01128 2016.05.02 How to Contact Altera Date ACDS Version B-5 Changes Made February 2013 12.1 SP1 * Reformatted figures. * Modified Figure 4-1 on page 4-2, Figure 4-2 on page 4-4, Figure 5-1 on page 5-10, and Figure 5-2 on page 5-10 for readability. * Removed mention of OpenCore evaluation feature from "100G Interlaken IP Core Evaluation Features" on page 1-5 because the feature name caused confusion with the OpenCore Plus evaluation feature. The current and past descriptions of the evaluation features are correct. * Added default parameter values in Chapter 3, Parameter Settings and in Chapter 7, Advanced Parameter Settings. * Renamed Appendix A, Performance and Fmax Requirements for 100G Ethernet Traffic. * Consolidated information about 100G Interlaken MegaCore function license. All variations of this IP core are available if you have a single Altera license for this IP core. * Enhanced description of RX and TX data paths in new sections "Transmit Path Blocks" on page 4-9 and "Receive Path Blocks" on page 4-13. * Corrected location of "Receiver Side Timing Diagrams" on page 4-10 to "Receive Path" on page 4-10. November 2012 12.1 Initial release. How to Contact Altera Table B-2: How to Contact Altera To locate the most up-to-date information about Altera products, refer to this table. You can also contact your local Altera sales office or sales representative. Contact Technical support Contact Method Address Website www.altera.com/support Website www.altera.com/training Email custrain@altera.com Product literature Website www.altera.com/literature Nontechnical support: general Email nacomp@altera.com Nontechnical support: software licensing Email authorization@altera.com Technical training Additional Information Send Feedback Altera Corporation B-6 UG-01128 2016.05.02 Typographic Conventions Related Information * * * * * * www.altera.com/support www.altera.com/training custrain@altera.com www.altera.com/literature nacomp@altera.com authorization@altera.com Typographic Conventions Table B-3: Typographic Conventions Lists the typographic conventions this document uses. Visual Cue Meaning Bold Type with Initial Capital Letters Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitaliza tion matches the GUI. bold type Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \ qdesigns directory, D: drive, and chiptrip.gdf file. Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix V Design Guidelines. italic type Indicates variables. For example, n + 1. Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name> . pof file. Initial Capital Letters Indicate keyboard keys and menu names. For example, the Delete key and the Options menu. "Subheading Title" Quotation marks indicate references to sections in a document and titles of Quartus Prime Help topics. For example, "Typographic Conventions." Altera Corporation Additional Information Send Feedback UG-01128 2016.05.02 Typographic Conventions Visual Cue Courier type B-7 Meaning Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. The suffix n denotes an active-low signal. For example, resetn. Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI). 1., 2., 3., and a., b., c., and so on Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. * Bullets indicate a list of items when the sequence of the items is not important. The Subscribe button links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. The Feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document. Related Information Email Subscription Management Center Additional Information Send Feedback Altera Corporation Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Altera: IP-INTLKN/100G/20L IPR-INTLKN/100G12L IPR-ILKN/100G IP-INTLKN/150G/24L IP-ILKN/50G IPRINTLKN/150G24L IPR-ILKN/50G IP-INTLKN/100G/12L