Waar= in) fanaa MT5C2565 64K x 4 SRAM SRAM 64K x 4 SRAM WITH OUTPUT ENABLE FEATURES High speed: 10, 12, 15, 20 and 25 High-performance, low-power, CMOS double-metal process * Single +5V +10% power supply Easy memory expansion with CE and OE options All inputs and outputs are TTL-compatible OPTIONS MARKING * Timing 10ns access -10 12ns access -12 15ns access -15 20ns access -20 25ns access -25 Packages Plastic DIP (300 mil) None Plastic SOJ (300 mil) DJ * 2V data retention (optional) L * Low power (optional) P Temperature Commercial (0C to +70C) None Industrial _(-40C._ to +85C) IT Automotive (-40C to +125C) AT Extended = (-55C. to +125C) XT Part Number Example: MT5C2565DJ-15 L NOTE: Not all combinations of operating temperature, speed, data retention and low power are necessarily available Please contact the factory for availabil- ity of specific part number combinations GENERAL DESCRIPTION The MT5C2565 is organized as a 65,536 x 4 SRAM using afour-transistor memory cell witha high-speed, low-power CMOS process. Micron SRAMsare fabricated using double- layer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Micron offers chip enable (CE) and output enable (OE) with this organization. These enhancements can place the out- puts in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE) and CE inputs are both LOW. Reading is accomplished when WE remains HIGH and CE and OE go LOW. The device offers a reduced power standby mode PIN ASSIGNMENT (Top View) 28-Pin SOJ 28-Pin DIP (SD-2) (SA-4) ne [1 7 28 |] Voc Ao [| 2 27] A1s At (] 3 26 [] At4 A2()4 25 {] A13 A3()5 24 |] At2 A4 []6 23 [] At4 As [7 22 {] Ato a6 [] 8 21 (] Nc a7 [9 20 {] Nc A8 [] to 19 |] Da4 Ag [} 11 18 |] Das CE [12 17 [] paz OE [] 13 16] Dai Vss [] 14 15] WE when disabled. This allows system designers to meet low standby power requirements. The P version provides a reduction in both operating current (Icc) and TTL standby current (Iss). The latter is achieved through the use of gated inputs on the WE, OEand address lines, which also facilitates the design of battery backed systems. That is, the gated inputs simplify the design effort and circuitry required to protect against inad- vertent battery current drain during power-down, when inputs may be at undefined levels. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL-compatible. MT5C2565, Rev 11/04 MB 6111549 0010256 374 Micron Semiconductor Inc , reserves the nght to change products or specifications without notice: 1994, Micron Semiconductor, Ine WV8S SNONOYHONASV ASINVYS SNONOYHONASVYV AS MT5C2565 64K x 4SRAM FUNCTIONAL BLOCK DIAGRAM Vec GND A Aa A Oo 5 A oO oO Oo 262,144-BIT 5 uw MEMORY ARRAY oO } A = oO Dat 5 Q oc A loe CE A L{ io A | (LSB) WE COLUMN DECODER (LSB) POWER rt tft t t ft t GOS A A A A A A A A TRUTH TABLE MODE tE | CE | WE Da POWER STANDBY x H xX HIGH-Z | STANDBY READ L L H Q ACTIVE NOT SELECTED H L H HIGH-Z ACTIVE WRITE x L L D ACTIVE nrecases 1 -32 Micron Semiconductor, Inc , reserves the nght to change Proce or peciicatone without wine MH 6111549 0010257 200 mmites tate) SEIICONCUCTOR INC MT5C2565 64K x 4 SRAM ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss Storage Temperature (plastic) Short Circuit Output Current... teeters 50mA Voltage on Any Pin Relative to Vss. -1V to Vec +1V Junction Temperature oo... ccecsceeeseesseeseersesssssees +150C *Stresses greater than those listed under Absolute Maxi- mum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See technical note TN-05-14 for more information. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (0C <T, < 70C; Vcc = 5V +10%) DESCRIPTION CONDITIONS SYMBOL | MIN MAX UNITS NOTES Input High (Logic 1) Voltage VIH 2.2 Vec+ Vv 1 Input Low (Logic 0) Voltage Vit -0.5 0.8 Vv 1,2 Input Leakage Current OV < Vin < Voc fli 5 5 pA Output Leakage Current Output(s) disabled ILo 5 5 HA OV < VouT < Vcc Output High Voltage loH = -4.0mMA Vou 2.4 Vv 1 Output Low Voltage lo. = 8.0MA VoL 0.4 Vv 1 Supply Voltage Vec 4.5 5.5 Vv 1 MAX DESCRIPTION CONDITIONS SYMBOL TYP -10t | -12t | -15 | -20 | -25 |UNITS|NOTES Power Supply CE < Vi; Vec = MAX Current: Operating f = MAX = 1/'RC Icc 130 200 | 180 | 165 | 150 | 140 | mA | 3, 13 outputs open [| _P version Icc 100 - | - | 140} 125] 120] ma [3, 13 Power Supply CE 2 Vin; Voc = MAX Current: Standby f = MAX = 1/'RC IsB1 24 55 | 50 | 45 | 40 |} 35 | mA] 13 outputs open | _P-version Isat 1.4 - - | 4 1 4 |] 4 [ mal 43 CE 2 Vcc -0.2V; Vec = MAX Vin < Vss +0.2V or Isp2 0.6 5 5 5 5 7 mA | 13 Vin 2 Vcc -0.2V; f = 0 | _P version Ise2 0.4 - | - | 3 | 3 | 3 | mat 13 TP version not available with this speed. pyseanes 1 -33 Micron Semiconductor, Inc reserves ihe nght lo change Products 07 Specifications wihout notice MM 6111549 90010258 147 me ol < > WVdYS SNONOYHONASMT5C2565 ort al AN ~ CAPACITANCE DESCRIPTION CONDITIONS SYMBOL | MAX UNITS NOTES Input Capacitance T, = 25C; f= 1 MHz Ci 6 pF 4 Output Capacitance Vcc = 5V Co 6 pF 4 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5) (0C < T, < 70C; Veo = 5V +10%) WVHS SNONOYHONASV AS -10 12 15 -20 2 6] | | DESCRIPTION sym | MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX [UNITS|NOTES READ Cycle READ cycle time 'RC 10 12 15 20 25 ns Address access time TAA 10 12 15 20 25 ns Chip Enable access time ACE 10 12 15 20 25 | ns Output hold from address change OH 3 3 3 3 3 ns Chip Enable to output in Low-Z LZCE | 3 3 3 3 3 ns | 7 Chip disable to output in High-Z 'HZCE 5 6 8 9 9 ns | 6,7 Chip Enable to power-up time PU 0 0 0 0 0 ns | 4 Chip disable to power-down time 'PD 10 12 15 20 25 | ns | 4 Output Enable access time AOE 5 6 8 8 8 ns Output Enable to output in Low-Z 'LZOE | 0 0 0 0 0 ns Output disable to out put in High-Z 'HZ0E 5 6 6 7 7 ns 6 WRITE Cycle WRITE cycle time WC 10 12 15 20 25 ns Chip Enable to end of write Cw 7 8 10 12 15 ns Chip Enable to end of write (P and LP version) cw : - 12 12 15 ns Address valid to end of write tAW 7 8 10 12 15 ns Address valid to end of write (P and LP version) | AW : - 12 12 15 ns Address setup time taS 0 0 0 0 0 ns Address hold from end of write tAH 1 1 1 1 1 ns WRITE pulse width WPI 7 8 10 12 15 ns WRITE pulse width twpe2 | 10 12 12 15 15 ns Data setup time ps 6 7 7 10 10 ns Data hold time 'DH 0 0 0 0 0 ns Write disable to output in Low-Z LZWE | 2 2 2 2 2 ns | 7 Write Enable to output in High-Z HZWE 5 6 7 8 10 ns | 6,7 fev 11/98 1-34 Weren Semiconductor, ne resent ng 1 Sh ro, tacron Somoonducor Ine MB 6111549 0010259 043MICRON MT5C2565 com 64K x 4 SRAM INDUSTRIAL TEMPERATURE SPECIFICATIONS (IT) The following specifications are to be used for Industrial Temperature (IT) MT5C2565 SRAMs. (-40C < Ty < 125C - AT) (-55C < T, < 125C - XT) MAX DESCRIPTION CONDITIONS SYMBOL -10 12 | -15 | -20 -25 | UNITS | NOTES Power Supply CE < Vi; Vec = MAX Current: Operating f = MAX = 1/'RC Iec 210 | 190 } 170 | 160 | 150 mA 3 outputs open Power Supply CE > Vin; Voc = MAX Current: Standby f = MAX = 1/'RC IsB1 65 60 50 45 40 mA outputs open CE 2 Voc -0.2V; Voc = MAX Vin < Vss +0.2V or IsB2 6 6 6 6 6 mA Vin 2 Vcc -0.2V; f=0 DATA RETENTION ELECTRICAL CHARACTERISTICS (L and LP versions only) DESCRIPTION CONDITIONS SYMBOL MAX UNITS NOTES Data Retention Current | CE 2 (Vcc -0.2V) Vcc = 2V Iccpr 400 pA L version Vin 2 (Vcc -0.2V) ors0.2V Vcc = 3V Iccpr 600 pA Data Retention Current CE = (Vee -0.2V) Voc = 2V IccpR 400 pA LP version Veo = 3V IccpoR 600 pA ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS Refer to commercial temperature timing parameters for specifications not listed here. (Notes 5, 13) (-40C < T, < 125C - AT; -55C < T, < 125C - XT; Voc = 5V +10%) 12 15 20 25 DESCRIPTION sym | MIN | MAX | MIN | MAX [ MIN | MAX | MIN | MAX | UNITS | NOTES READ Cycle Output hold from address change OH 2 2 2 2 ns Chip Enable to output in Low-Z 'LZCE| 2 2 2 2 ns 7 WRITE Cycle Address hold from end of write [AH | 2 | | 2 ] | 2] | 2 | | ns | ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (40C < Ty $ 125C - AT) (-55C < Ty < 125C - XT) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage VIH 2.3 Vcc +1 Vv 1 MTSC2ERS 1 -35 Micron Semiconductor Inc , reservea the nght to change Pr peticatone wihout notice MB 6131549 0010260 6TS mm WVdS SNONOYHDNASV ASarn MT5C2565 64K x 4 SRAM - AUTOMOTIVE AND EXTENDED TEMPERATURE SPECIFICATIONS (AT AND XT) The following specifications are to be used for Automotive Temperature (AT) and Extended Temperature (XT) MT5C2565 G1 SRAMs. (-40C < Ty < 125C - AT) (55C < Ty S 125C - XT) < MAX > DESCRIPTION CONDITIONS SYMBOL} -12 -15 -20 25 UNITS | NOTES Power Supply CE < Vit; Voc = MAX Current: Operating f= MAX = 1/'RC Icc 195 175 165 155 mA 3 =< outputs open | Power Supply CE > Vin; Vec = MAX QO Current: Standby f = MAX = 1/'RC IsB1 60 50 45 40 mA =r outputs open 0 CE 2 Vec -0.2V; Vec = MAX Vin < Vss +0.2V or IsB2 7 7 7 7 mA oO VIN > Voc -0.2V; f= 0 7) DATA RETENTION ELECTRICAL CHARACTERISTICS (L and LP versions only) ~ DESCRIPTION CONDITIONS SYMBOL MAX UNITS NOTES Vv Data Retention Current | CE => (Vcc -0.2V) Vec = 2V Iccor 500 pA > L version Vin 2 (Vcc -0.2V) ors0.2V Voc = 3V IccDR 800 HA = Data Retention Current | CE 2 (Vcc -0.2V) Voc = 2V IccorR 500 LA LP version Vec = 3V Iecor 800 pA ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS Refer to commercial temperature timing parameters for specifications not listed here. (Notes 5, 13) (-40C < Ty < 125C; -85C < T, < 125C; Veo = 5V 410%) +12 -15 -20 +25 DESCRIPTION sym | MIN | MAX| MIN | MAX {| MIN | MAX | MIN | MAX | UNITS | NOTES READ Cycle Output hold from address change OH 2 2 2 2 ns Chip Enable to output in Low-Z LZCE} 2 2 2 2 ns 7 WRITE Cycle Address hold from end of write | AH | 2 | [ 2 | f 2 | | 2 | [ ns | ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-40C < Ty < 85C) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage Vin 2.3 Voc +1 Vv 1 MTScabse 1 -36 Micron Semiconductor, Inc , reserves the nght to change Products or specricavons nt rote MB 6111549 0010261 73]MICRON MT5C2565 eeentetin 64K x 4 SRAM AC TEST CONDITIONS +5V 45V Input pulse levels ..ccccccceccscccceecsescseseees 480 } 480 Input rise and fall times... 255 30 pF 255 5 pF Input timing reference levels... 1.5V Output reference levels .........c.ccssesseecscrsseseeeeees 1.5V . . Fig. 1 OUTPUT LOAD Fig. 2 OUTPUT LOAD Output TOAD ooo... eeeceeeteeesssensens See Figures 1 and 2 EQUIVALENT EQUIVALENT NOTES 1. All voltages referenced to Vss (GND). 8. WE is HIGH for READ cycle. 2. -3V for pulse width < *RC/2. 9. Device is continuously selected. All chip enables are 3. Icc is dependent on output loading and cycle rates. held in their active state. 4. This parameter is sampled. 10. Address valid prior to, or coincident with, latest 5. Test conditions as specified with the output loading occurring chip enable. as shown in Fig. 1 unless otherwise noted. 11. RC = Read Cycle Time. 6. 'HZCE, 'HZOE and HZWE are specified with C, = 12. Chip enable and write enable can initiate and 5pF as in Fig. 2. Transition is measured +500mV from terminate a WRITE cycle. steady state voltage. 13. Typical values are measured at 5V, 25C and 15ns 7. Atany given temperature and voltage condition, cycle time. HZCE is less than LZCE, and tHZWE is less than 14. Typical currents are measured at 25C. LZWE, DATA RETENTION ELECTRICAL CHARACTERISTICS (L and LP versions only) DESCRIPTION CONDITIONS SYMBOL | MIN TYP MAX UNITS | NOTES Vcc for Retention Data Vor 2 Vv Data Retention Current | CE2 (Vcc -0.2V)| Vcc =2V} Iccor 125 300 pA 14 L version Vin 2 (Vcc -0.2V) ors 0.2V Vec = 3V IccprR 175 500 pA 14 Data Retention Current | CE2 (Vcc -0.2V)| Vcc =2V|_ Iccor 100 300 pA 14 LP version Vcc = 3V Iccor 150 500 LA 14 Chip Deselect to Data CDR 0 ns 4 Retention Time Operation Recovery Time 'R RC ns 4,11 MT5C2Z585 Micron Semiconductor, inc , reserves the right to change products or specifications without nobos Rev 11/94 1 -37 01994, Micron Semiconductor, inc MH 6111549 00102b2 b76 WVYS SNONOYHONASV ASWVYS SNONOYHONASV AS MT5C2565 64K x 4SRAM DATA RETENTION MODE \| 4.5V 45VV Vee K Vor J tepr 'R = <0 Wm. ADDR DQ LOW Vcc DATA RETENTION WAVEFORM READ CYCLE NO. 1&9 tac \ f VALID |! taA tou i | PREVIOUS DATA VALID DATA VALID READ CYCLE NO. 27.8. 10 tac _ a N, j AOE lace {LZCE HIGH-Z DATA VALID tHZCE 'LZ0E tHZOE | =-__ teu | -<___s- | tpo DON'T CARE RX] UNDEFINED MT5C2585 Rev 11/04 MH 6111549 0010263 Sov 1 3 8 Micron Serconductor Inc reserves the nght to changa products or specificalions without nobes 1994 Micron Semiconductor IncMICRON MT5C2565 64K x 4 SRAM WRITE CYCLE NO. 1 2 (Chip Enable Controlled) ADDR t C 2 a, ULL p MM DATA VALID WRITE CYCLE NO. 27.12.15 (Write Enabie Controlled) ADDR x x I tow taH We i I D Mh DATA VALID WMI DON'T CARE B88} UNDEFINED NOTE: Output enable (OE) is inactive (HIGH). fev. 1198 1-39 Meron Semiconedor ne emer nae chan Pr ctor nt etce MB 6111549 0010264 440 WVYS SNONOYHONASY ASMT5C2565 64K x 4 SRAM WRITE CYCLE NO. 37.12.16 (Write Enable Controlled) Ol < we > ADDR < = _ L CE a O We = tos O D DATA VALID Cc ~ Q 2 DON'T CARE = RRS] UNDEFINED NOTE: Output enable (GE) is active (LOW). MTSC2565 1 40 Micron Semiconductor, Inc , reserves the right to change products or specificabons without notice Rev 11/94 1994, Micron Semiconductor, [nc MH 6111549 0010eb5 357