DL135/D Rev. 7, Apr-2001 Power MOSFETs Power MOSFETs DL135/D Rev. 7, Apr-2001 SCILLC, 2001 Previous Edition 1996 "All Rights Reserved" EZFET, MiniMOS & SMARTDISCRETES are trademarks of Semiconductor Components Industries, LLC (SCILLC). ChipFET is a trademark of Vishay Siliconix. FETKY is a trademark of International Rectifier Corporation. Micro8 is a trademark of International Rectifier. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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Ignition IGBT 15 Amps, 410 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 NIB6404-5L . . . . . . . . . . . . . . . . . SMARTDISCRETESt 52 Amps, 40 Volts Self Protected with Temperature Sense N-Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . 23 NIMD6302R2 . . . . . . . . . . . . . . . . SMARTDISCRETESt 5 Amps, 30 Volts Self Protected with Current Sense N-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . . 27 NTD20N03L27 . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 30 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 NTD20N06 . . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 60 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 NTD3055-094 . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 NTD3055L104 . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts, Logic Level N-Channel DPAK . . . . . . . . . . . . . . . . . 37 NTD32N06 . . . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 60 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 NTD32N06L . . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 60 Volts, Logic Level N-Channel DPAK . . . . . . . . . . . . . . . . . 44 NTD4302 . . . . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 30 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 NTGS3433T1 . . . . . . . . . . . . . . . . MOSFET -3.3 Amps, -12 Volts P-Channel TSOP-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 NTGS3441T1 . . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 20 Volts P-Channel TSOP-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 NTGS3443T1 . . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts P-Channel TSOP-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 NTGS3446 . . . . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 20 Volts N-Channel TSOP-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 NTGS3455T1 . . . . . . . . . . . . . . . . MOSFET -3.5 Amps, -30 Volts P-Channel TSOP-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 NTHD5902T1 . . . . . . . . . . . . . . . . Dual N-Channel 30 V (D-S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 NTHD5903T1 . . . . . . . . . . . . . . . . Dual P-Channel 2.5 V (G-S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 NTHD5904T1 . . . . . . . . . . . . . . . . Dual N-Channel 2.5 V (G-S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 NTHD5905T1 . . . . . . . . . . . . . . . . Dual P-Channel 1.8 V (G-S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 NTHS5402T1 . . . . . . . . . . . . . . . . N-Channel 30 V (D-S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 NTHS5404T1 . . . . . . . . . . . . . . . . N-Channel 2.5 V (G-S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 NTHS5441T1 . . . . . . . . . . . . . . . . P-Channel 2.5 V (G-S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 NTHS5443T1 . . . . . . . . . . . . . . . . P-Channel 2.5 V (G-S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 NTHS5445T1 . . . . . . . . . . . . . . . . P-Channel 1.8 V (G-S) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 NTMD3P03R2 . . . . . . . . . . . . . . . Power MOSFET -3.05 Amps, -30 Volts Dual P-Channel SO-8 . . . . . . . . . . . . . . . . . . . 120 NTMD6N02R2 . . . . . . . . . . . . . . . Power MOSFET 6.0 Amps, 20 Volts N-Channel Enhancement Mode Dual SO-8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 NTMD6P02R2 . . . . . . . . . . . . . . . Power MOSFET 6 Amps, 20 Volts P-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 120 NTMD7C02 . . . . . . . . . . . . . . . . . . Power MOSFET 9.5 Amps, 20 Volts (N-Ch) 4 Amps, 20 Volts (P-Ch) Complementary SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 NTMS10P02R2 . . . . . . . . . . . . . . Power MOSFET -10 Amps, -20 Volts P-Channel Enhancement-Mode Single SO-8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 NTMS3P03R2 . . . . . . . . . . . . . . . Power MOSFET -3.05 Amps, -30 Volts P-Channel SO-8 . . . . . . . . . . . . . . . . . . . . . . . . 150 NTMS4N01R2 . . . . . . . . . . . . . . . Power MOSFET 4.2 Amps, 20 Volts N-Channel Enhancement-Mode Single SO-8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 NTMS4P01R2 . . . . . . . . . . . . . . . Power MOSFET -4.5 Amps, -12 Volts P-Channel Enhancement-Mode Single SO-8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 NTMS5P02R2 . . . . . . . . . . . . . . . Power MOSFET -5.4 Amps, -20 Volts P-Channel Enhancement-Mode Single SO-8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 NTMSD2P102LR2 . . . . . . . . . . . . FETKYt Power MOSFET and Schottky Diode Dual SO-8 Package . . . . . . . . . . . . . . . 178 NTMSD3P102R2 . . . . . . . . . . . . . FETKYt P-Channel Enhancement-Mode Power MOSFET and Schottky Diode Dual SO-8 Package . . . . . . . . . . . . . . . . . . . . . . . . 188 NTMSD3P303R2 . . . . . . . . . . . . . FETKYt P-Channel Enhancement-Mode Power MOSFET and Schottky Diode Dual SO-8 Package . . . . . . . . . . . . . . . . . . . . . . . . 198 NTP27N06 . . . . . . . . . . . . . . . . . . Power MOSFET 27 Amps, 60 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . . 208 NTP45N06 . . . . . . . . . . . . . . . . . . Power MOSFET 45 Amps, 60 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . . 210 NTP45N06L . . . . . . . . . . . . . . . . . Power MOSFET 45 Amps, 60 Volts, Logic Level N-Channel TO-220 . . . . . . . . . . . . . . 215 NTP75N03-06 . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 30 Volts N-Channel TO-220 and D2PAK . . . . . . . . . . . . . . 220 NTP75N03L09 . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 30 Volts N-Channel TO-220 and D2PAK . . . . . . . . . . . . . . 225 http://onsemi.com 5 Power MOSFET Numeric Data Sheet Listing (continued) Device Function Page NTQD6866 . . . . . . . . . . . . . . . . . . Power MOSFET 5.8 Amps, 20 Volts N-Channel TSSOP-8 . . . . . . . . . . . . . . . . . . . . . . . 230 NTTD1P02R2 . . . . . . . . . . . . . . . . Power MOSFET -1.45 Amps, -20 Volts P-Channel Enhancement Mode Dual Micro8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 NTTD2P02R2 . . . . . . . . . . . . . . . . Power MOSFET -2.4 Amps, -20 Volts Dual P-Channel Micro8t . . . . . . . . . . . . . . . . . 241 NTTS2P02R2 . . . . . . . . . . . . . . . . Power MOSFET -2.4 Amps, -20 Volts Single P-Channel Micro8t . . . . . . . . . . . . . . . . 248 NTTS2P03R2 . . . . . . . . . . . . . . . . Power MOSFET -2.48 Amps, -30 Volts P-Channel Enhancement Mode Single Micro8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 NTUD01N02 . . . . . . . . . . . . . . . . . Power MOSFET 100 mAmps, 20 Volts Dual N-Channel SC-88 . . . . . . . . . . . . . . . . . . . 262 2N7000 . . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 200 mAmps, 60 Volts N-Channel TO-92 . . . . . . . . . . . . . . . . . . 264 2N7002LT1 . . . . . . . . . . . . . . . . . . Power MOSFET 115 mAmps, 60 Volts N-Channel SOT-23 . . . . . . . . . . . . . . . . . . . . . . 267 BS107 . . . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 250 mAmps, 200 Volts N-Channel TO-92 . . . . . . . . . . . . . . . . . 271 BS108 . . . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 250 mAmps, 200 Volts, Logic Level N-Channel TO-92 . . . . . . 275 BS170 . . . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 500 mAmps, 60 Volts N-Channel TO-92 . . . . . . . . . . . . . . . . . . 277 BSS123LT1 . . . . . . . . . . . . . . . . . Power MOSFET 170 mAmps, 100 Volts N-Channel SOT-23 . . . . . . . . . . . . . . . . . . . . . 280 BSS138LT1 . . . . . . . . . . . . . . . . . Power MOSFET 200 mAmps, 50 Volts N-Channel SOT-23 . . . . . . . . . . . . . . . . . . . . . . 284 BSS84LT1 . . . . . . . . . . . . . . . . . . . Power MOSFET 130 mAmps, 50 Volts P-Channel SOT-23 . . . . . . . . . . . . . . . . . . . . . . 289 MGP15N35CL . . . . . . . . . . . . . . . Ignition IGBT 15 Amps, 350 Volts N-Channel TO-220 and D2PAK . . . . . . . . . . . . . . . . 293 MGP15N40CL . . . . . . . . . . . . . . . Ignition IGBT 15 Amps, 410 Volts N-Channel TO-220 and D2PAK . . . . . . . . . . . . . . . . 301 MGP19N35CL . . . . . . . . . . . . . . . Ignition IGBT 19 Amps, 350 Volts N-Channel TO-220 and D2PAK . . . . . . . . . . . . . . . . 309 MGSF1N02ELT1 . . . . . . . . . . . . . Power MOSFET 750 mAmps, 20 Volts N-Channel SOT-23 . . . . . . . . . . . . . . . . . . . . . . 316 MGSF1N02LT1 . . . . . . . . . . . . . . Power MOSFET 750 mAmps, 20 Volts N-Channel SOT-23 . . . . . . . . . . . . . . . . . . . . . . 320 MGSF1N03LT1 . . . . . . . . . . . . . . Power MOSFET 750 mAmps, 30 Volts N-Channel SOT-23 . . . . . . . . . . . . . . . . . . . . . . 324 MGSF1P02ELT1 . . . . . . . . . . . . . Power MOSFET 750 mAmps, 20 Volts P-Channel SOT-23 . . . . . . . . . . . . . . . . . . . . . . 328 MGSF1P02LT1 . . . . . . . . . . . . . . Power MOSFET 750 mAmps, 20 Volts P-Channel SOT-23 . . . . . . . . . . . . . . . . . . . . . . 332 MGSF2P02HD . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts P-Channel TSOP-6 . . . . . . . . . . . . . . . . . . . . . . . . . . 336 MGSF3442VT1 . . . . . . . . . . . . . . Power MOSFET 4 Amps, 20 Volts N-Channel TSOP-6 . . . . . . . . . . . . . . . . . . . . . . . . . . 344 MGSF3454VT1 . . . . . . . . . . . . . . Power MOSFET 4 Amps, 30 Volts N-Channel TSOP-6 . . . . . . . . . . . . . . . . . . . . . . . . . . 349 MLD1N06CL . . . . . . . . . . . . . . . . . SMARTDISCRETES MOSFET 1 Amp, 62 Volts, Logic Level N-Channel DPAK . . . . . 354 MLP1N06CL . . . . . . . . . . . . . . . . . SMARTDISCRETES MOSFET 1 Amp, 62 Volts, Logic Level N-Channel TO-220 . . . 360 MLP2N06CL . . . . . . . . . . . . . . . . . SMARTDISCRETES MOSFET 2 Amps, 62 Volts, Logic Level N-Channel TO-220 . . 366 MMBF0201NLT1 . . . . . . . . . . . . . Power MOSFET 300 mAmps, 20 Volts N-Channel SOT-23 . . . . . . . . . . . . . . . . . . . . . . 372 MMBF0202PLT1 . . . . . . . . . . . . . Power MOSFET 300 mAmps, 20 Volts P-Channel SOT-23 . . . . . . . . . . . . . . . . . . . . . . 377 MMBF1374T1 . . . . . . . . . . . . . . . Small Signal MOSFET 50 mAmps, 30 Volts N-Channel SC-70/SOT-323 . . . . . . . . . . 382 MMBF170LT1 . . . . . . . . . . . . . . . . Power MOSFET 500 mAmps, 60 Volts N-Channel SOT-23 . . . . . . . . . . . . . . . . . . . . . . 384 MMBF2201NT1 . . . . . . . . . . . . . . Power MOSFET 300 mAmps, 20 Volts N-Channel SC-70/SOT-323 . . . . . . . . . . . . . . 388 MMBF2202PT1 . . . . . . . . . . . . . . Power MOSFET 300 mAmps, 20 Volts P-Channel SC-70/SOT-323 . . . . . . . . . . . . . . . 392 MMDF1300 . . . . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 25 Volts Complementary SO-8, Dual . . . . . . . . . . . . . . . . . . . 396 MMDF1N05E . . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 50 Volts N-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . . 399 MMDF2C01HD . . . . . . . . . . . . . . Power MOSFET 2 Amps, 12 Volts Complementary SO-8, Dual . . . . . . . . . . . . . . . . . . . 404 MMDF2C02E . . . . . . . . . . . . . . . . Power MOSFET 2.5 Amps, 25 Volts Complementary, SO-8, Dual . . . . . . . . . . . . . . . . . 416 MMDF2C02HD . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts Complementary SO-8, Dual . . . . . . . . . . . . . . . . . . . 427 MMDF2C03HD . . . . . . . . . . . . . . Power MOSFET 2 Amps, 30 Volts Complementary SO-8, Dual . . . . . . . . . . . . . . . . . . . 439 MMDF2N02E . . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 25 Volts N-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 451 MMDF2N05ZR2 . . . . . . . . . . . . . . Power MOSFET 2 Amps, 50 Volts N-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 459 MMDF2P01HD . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 12 Volts P-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 468 MMDF2P02E . . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 25 Volts P-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 477 MMDF2P02HD . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts P-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 485 MMDF2P03HD . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 30 Volts P-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 494 MMDF3N02HD . . . . . . . . . . . . . . Power MOSFET 3 Amps, 20 Volts N-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 503 MMDF3N03HD . . . . . . . . . . . . . . Power MOSFET 3 Amps, 30 Volts N-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 512 MMDF3N04HD . . . . . . . . . . . . . . Power MOSFET 3 Amps, 40 Volts N-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 521 MMDF3N06HD . . . . . . . . . . . . . . Power MOSFET 3 Amps, 60 Volts N-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 531 MMDF3N06VL . . . . . . . . . . . . . . . Power MOSFET 3 Amps, 60 Volts N-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 540 MMDF4N01HD . . . . . . . . . . . . . . Power MOSFET 4 Amps, 20 Volts N-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 542 http://onsemi.com 6 Power MOSFET Numeric Data Sheet Listing (continued) Device Function Page MMDF5N02Z . . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 20 Volts N-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 551 MMDF6N03HD . . . . . . . . . . . . . . Power MOSFET 6 Amps, 30 Volts N-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 560 MMDF7N02Z . . . . . . . . . . . . . . . . Power MOSFET 7 Amps, 20 Volts N-Channel SO-8, Dual . . . . . . . . . . . . . . . . . . . . . . . 569 MMDFS2P102 . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts P-Channel SO-8, FETKYt . . . . . . . . . . . . . . . . . . . 579 MMDFS6N303 . . . . . . . . . . . . . . . Power MOSFET 6 Amps, 30 Volts N-Channel SO-8, FETKYt . . . . . . . . . . . . . . . . . . . 589 MMFT2406T1 . . . . . . . . . . . . . . . . Power MOSFET 700 mAmps, 240 Volts N-Channel SOT-223 . . . . . . . . . . . . . . . . . . . . 605 MMFT2955E . . . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 60 Volts P-Channel SOT-223 . . . . . . . . . . . . . . . . . . . . . . . . . . 610 MMFT2N02EL . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts N-Channel SOT-223 . . . . . . . . . . . . . . . . . . . . . . . . . 619 MMFT3055V . . . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 60 Volts N-Channel SOT-223 . . . . . . . . . . . . . . . . . . . . . . . . . . 628 MMFT3055VL . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 60 Volts N-Channel SOT-223 . . . . . . . . . . . . . . . . . . . . . . . . . . 637 MMFT5P03HD . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 30 Volts P-Channel SOT-223 . . . . . . . . . . . . . . . . . . . . . . . . . 646 MMFT960T1 . . . . . . . . . . . . . . . . . Power MOSFET 300 mAmps, 60 Volts N-Channel SOT-223 . . . . . . . . . . . . . . . . . . . . . 656 MMSF10N02Z . . . . . . . . . . . . . . . Power MOSFET 10 Amps, 20 Volts N-Channel SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 MMSF10N03Z . . . . . . . . . . . . . . . Power MOSFET 10 Amps, 30 Volts N-Channel SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 MMSF1308 . . . . . . . . . . . . . . . . . . Power MOSFET 7 Amps, 30 Volts N-Channel SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 MMSF1310 . . . . . . . . . . . . . . . . . . Power MOSFET 10 Amps, 30 Volts N-Channel SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 MMSF2P02E . . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts P-Channel SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 MMSF3300 . . . . . . . . . . . . . . . . . . Power MOSFET 11.5 Amps, 30 Volts N-Channel SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . 705 MMSF3P02HD . . . . . . . . . . . . . . . Power MOSFET 3 Amps, 20 Volts P-Channel SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 MMSF5N02HD . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 20 Volts N-Channel SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 MMSF5N03HD . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 30 Volts N-Channel SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 MMSF7N03HD . . . . . . . . . . . . . . . Power MOSFET 7 Amps, 30 Volts N-Channel SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 MMSF7N03Z . . . . . . . . . . . . . . . . Power MOSFET 7 Amps, 30 Volts N-Channel SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 MPF930 . . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 2 Amps, 35, 60, 90 Volts N-Channel TO-92 . . . . . . . . . . . . . . . 761 MTB1306 . . . . . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 30 Volts, Logic Level N-Channel D2PAK . . . . . . . . . . . . . . . 765 MTB20N20E . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 200 Volts N-Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . 772 MTB23P06V . . . . . . . . . . . . . . . . . Power MOSFET 23 Amps, 60 Volts P-Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 781 MTB29N15E . . . . . . . . . . . . . . . . . Power MOSFET 29 Amps, 150 Volts N-Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . 790 MTB30N06VL . . . . . . . . . . . . . . . . Power MOSFET 30 Amps, 60 Volts, Logic Level N-Channel D2PAK . . . . . . . . . . . . . . . 798 MTB30P06V . . . . . . . . . . . . . . . . . Power MOSFET 30 Amps, 60 Volts P-Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 807 MTB36N06V . . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 60 Volts N-Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 816 MTB40N10E . . . . . . . . . . . . . . . . . Power MOSFET 40 Amps, 100 Volts N-Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . 825 MTB50N06V . . . . . . . . . . . . . . . . . Power MOSFET 42 Amps, 60 Volts N-Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 834 MTB50N06VL . . . . . . . . . . . . . . . . Power MOSFET 42 Amps, 60 Volts, Logic Level N-Channel D2PAK . . . . . . . . . . . . . . . 843 MTB50P03HDL . . . . . . . . . . . . . . Power MOSFET 50 Amps, 30 Volts, Logic Level P-Channel D2PAK . . . . . . . . . . . . . . . 852 MTB52N06V . . . . . . . . . . . . . . . . . Power MOSFET 52 Amps, 60 Volts N-Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 862 MTB52N06VL . . . . . . . . . . . . . . . . Power MOSFET 52 Amps, 60 Volts, Logic Level N-Channel D2PAK . . . . . . . . . . . . . . . 871 MTB55N06Z . . . . . . . . . . . . . . . . . Power MOSFET 55 Amps, 60 Volts N-Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 880 MTB60N05HDL . . . . . . . . . . . . . . Power MOSFET 60 Amps, 50 Volts, Logic Level N-Channel D2PAK . . . . . . . . . . . . . . . 885 MTB60N06HD . . . . . . . . . . . . . . . Power MOSFET 60 Amps, 60 Volts N-Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 895 MTB75N03HDL . . . . . . . . . . . . . . Power MOSFET 75 Amps, 25 Volts, Logic Level N-Channel D2PAK . . . . . . . . . . . . . . . 905 MTB75N05HD . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 50 Volts N-Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 915 MTB75N06HD . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 60 Volts N-Channel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 922 MTD1302 . . . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 30 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . 932 MTD15N06V . . . . . . . . . . . . . . . . . Power MOSFET 15 Amps, 60 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . 942 MTD15N06VL . . . . . . . . . . . . . . . Power MOSFET 15 Amps, 60 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . 951 MTD20N03HDL . . . . . . . . . . . . . . Power MOSFET 20 Amps, 30 Volts, Logic Level N-Channel DPAK . . . . . . . . . . . . . . . . 960 MTD20N06HD . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 60 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . 970 MTD20N06HDL . . . . . . . . . . . . . . Power MOSFET 20 Amps, 60 Volts, Logic Level N-Channel DPAK . . . . . . . . . . . . . . . . 980 MTD20P03HDL . . . . . . . . . . . . . . Power MOSFET 20 Amps, 30 Volts, Logic Level P-Channel DPAK . . . . . . . . . . . . . . . . 990 MTD20P06HDL . . . . . . . . . . . . . . Power MOSFET 20 Amps, 60 Volts, Logic Level P-Channel DPAK . . . . . . . . . . . . . . . 1000 MTD2955V . . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts P-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1010 MTD3055V . . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1019 MTD3055VL . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1028 http://onsemi.com 7 Power MOSFET Numeric Data Sheet Listing (continued) Device Function Page MTD3302 . . . . . . . . . . . . . . . . . . . Power MOSFET 18 Amps, 30 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1037 MTD4N20E . . . . . . . . . . . . . . . . . . Power MOSFET 4 Amps, 200 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1048 MTD5P06V . . . . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 60 Volts P-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057 MTD6N20E . . . . . . . . . . . . . . . . . . Power MOSFET 6 Amps, 200 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1066 MTD6P10E . . . . . . . . . . . . . . . . . . Power MOSFET 6 Amps, 100 Volts P-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1075 MTD9N10E . . . . . . . . . . . . . . . . . . Power MOSFET 9 Amps, 100 Volts N-Channel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1084 MTDF1N02HD . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 20 Volts N-Channel Micro8t, Dual . . . . . . . . . . . . . . . . . . . . . 1093 MTDF1N03HD . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 30 Volts N-Channel Micro8t, Dual . . . . . . . . . . . . . . . . . . . . . 1104 MTDF2N06HD . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 60 Volts N-Channel Micro8t, Dual . . . . . . . . . . . . . . . . . . . . 1115 MTP10N10E . . . . . . . . . . . . . . . . . Power MOSFET 10 Amps, 100 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . 1123 MTP10N10EL . . . . . . . . . . . . . . . . Power MOSFET 10 Amps, 100 Volts, Logic Level N-Channel TO-220 . . . . . . . . . . . . 1130 MTP12P10 . . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 100 Volts P-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . 1136 MTP1302 . . . . . . . . . . . . . . . . . . . Power MOSFET 42 Amps, 30 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1141 MTP1306 . . . . . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 30 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1148 MTP15N06V . . . . . . . . . . . . . . . . . Power MOSFET 15 Amps, 60 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1155 MTP15N06VL . . . . . . . . . . . . . . . . Power MOSFET 15 Amps, 60 Volts, Logic Level N-Channel TO-220 . . . . . . . . . . . . . 1161 MTP20N06V . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 60 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1167 MTP20N15E . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 150 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . 1173 MTP20N20E . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 200 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . 1175 MTP23P06V . . . . . . . . . . . . . . . . . Power MOSFET 23 Amps, 60 Volts P-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1181 MTP27N10E . . . . . . . . . . . . . . . . . Power MOSFET 27 Amps, 100 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . 1187 MTP2955V . . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts P-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1193 MTP29N15E . . . . . . . . . . . . . . . . . Power MOSFET 29 Amps, 150 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . 1199 MTP3055V . . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1213 MTP3055VL . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts, Logic Level N-Channel TO-220 . . . . . . . . . . . . . 1219 MTP30N06VL . . . . . . . . . . . . . . . . Power MOSFET 30 Amps, 60 Volts, Logic Level N-Channel TO-220 . . . . . . . . . . . . . 1225 MTP30P06V . . . . . . . . . . . . . . . . . Power MOSFET 30 Amps, 60 Volts P-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1231 MTP36N06V . . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 60 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1237 MTP40N10E . . . . . . . . . . . . . . . . . Power MOSFET 40 Amps, 100 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . 1243 MTP50N06V . . . . . . . . . . . . . . . . . Power MOSFET 42 Amps, 60 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1249 MTP50N06VL . . . . . . . . . . . . . . . . Power MOSFET 42 Amps, 60 Volts, Logic Level N-Channel TO-220 . . . . . . . . . . . . . 1255 MTP50P03HDL . . . . . . . . . . . . . . Power MOSFET 50 Amps, 30 Volts, Logic Level P-Channel TO-220 . . . . . . . . . . . . . 1261 MTP52N06V . . . . . . . . . . . . . . . . . Power MOSFET 52 Amps, 60 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1268 MTP52N06VL . . . . . . . . . . . . . . . . Power MOSFET 52 Amps, 60 Volts, Logic Level N-Channel TO-220 . . . . . . . . . . . . . 1274 MTP5P06V . . . . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 60 Volts P-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . . 1280 MTP60N06HD . . . . . . . . . . . . . . . Power MOSFET 60 Amps, 60 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1286 MTP6P20E . . . . . . . . . . . . . . . . . . Power MOSFET 6 Amps, 200 Volts P-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1293 MTP75N03HDL . . . . . . . . . . . . . . Power MOSFET 75 Amps, 25 Volts, Logic Level N-Channel TO-220 . . . . . . . . . . . . . 1299 MTP75N05HD . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 50 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1306 MTP75N06HD . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 60 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1313 MTP7N20E . . . . . . . . . . . . . . . . . . Power MOSFET 7 Amps, 200 Volts N-Channel TO-220 . . . . . . . . . . . . . . . . . . . . . . . . 1320 MTSF1P02HD . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 20 Volts P-Channel Micro8t . . . . . . . . . . . . . . . . . . . . . . . . . . 1326 MTSF3N02HD . . . . . . . . . . . . . . . Power MOSFET 3 Amps, 20 Volts N-Channel Micro8t . . . . . . . . . . . . . . . . . . . . . . . . . 1337 MTSF3N03HD . . . . . . . . . . . . . . . Power MOSFET 3 Amps, 30 Volts N-Channel Micro8t . . . . . . . . . . . . . . . . . . . . . . . . . 1348 MTW32N20E . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 200 Volts N-Channel TO-247 . . . . . . . . . . . . . . . . . . . . . . . 1359 MTW32N25E . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 250 Volts N-Channel TO-247 . . . . . . . . . . . . . . . . . . . . . . . 1365 MTW35N15E . . . . . . . . . . . . . . . . Power MOSFET 35 Amps, 150 Volts N-Channel TO-247 . . . . . . . . . . . . . . . . . . . . . . . 1371 MTW45N10E . . . . . . . . . . . . . . . . Power MOSFET 45 Amps, 100 Volts N-Channel TO-247 . . . . . . . . . . . . . . . . . . . . . . . 1377 MTY55N20E . . . . . . . . . . . . . . . . . Power MOSFET 55 Amps, 200 Volts N-Channel TO-264 . . . . . . . . . . . . . . . . . . . . . . . 1383 VN0300L . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 200 mAmps, 60 Volts N-Channel TO-92 . . . . . . . . . . . . . . . . . 1389 VN2222LL . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 150 mAmps, 60 Volts N-Channel TO-92 . . . . . . . . . . . . . . . . . 1391 VN2406L . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 200 mAmps, 240 Volts N-Channel TO-92 . . . . . . . . . . . . . . . . 1394 VN2410L . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 200 mAmps, 240 Volts N-Channel TO-92 . . . . . . . . . . . . . . . . 1396 http://onsemi.com 8 Power MOSFET Selector Guide Table 1. ChipFET - Case 1206A Max RDS(on) @ VGS V(BR)DSS (Volts) Min 10 V () 4.5 V () 2.5 V () 1.8 V () ID (cont) Amps (Note 8.) 30 0.035 0.055 - - 6.7 0.085 0.143 - - 3.9 - 0.03 0.045 - - 0.075 0.0134 - 0.060 (Note 7.) 0.083 - 0.065 - 0.155 - 0.035 0.09 20 8 PD (Notes 1. & 2.) (Watts) Max Configuration Page No. NTHS5402T1 1.3 Single N-Channel 95 NTHD5902T1 1.1 Dual N-Channel 80 7.2 NTHS5404T1 1.3 Single N-Channel 106 - 4.2 NTHD5904T1 1.1 Dual N-Channel 90 - 5.3 NTHS5441T1 1.3 Single P-Channel 109 0.110 - 4.7 NTHS5443T1 1.3 Single P-Channel 112 0.260 - 2.9 NTHD5903T1 1.1 Dual P-Channel 85 0.047 0.062 7.1 NTHS5445T1 1.3 Single P-Channel 114 0.13 0.18 4.1 NTHD5905T1 1.1 Dual P-Channel 95 PD (Notes 1. & 2.) (Watts) Max Configuration (Note 6.) Page No. Device (Note 3.) Table 2. SO-8 (MiniMOS) - Case 751-06 V(BR)DSS (Volts) Min 60 1. 2. 3. 4. 5. 6. 7. 8. Max RDS(on) @ VGS 10 V () 4.5 V () 2.7 V () 2.5 V () ID (cont) Amps Device (Note 4.) - 0.130 (Note 5.) - - 3.3 MMDF3N06VLR2 2.0 Dual N-Channel 540 0.100 0.200 - - 3.3 MMDF3N06HDR2 2.0 Dual N-Channel 531 50 0.300 0.500 - - 1.5 MMDF1N05ER2 2.0 Dual N-Channel 399 40 0.080 0.100 - - 3.4 MMDF3N04HDR2 2.0 Dual N-Channel 521 30 0.030 0.039 - - 7.0 MMSF1308R2 2.5 Single N-Channel 681 0.015 0.019 - - 10.0 MMSF1310R2 2.5 Single N-Channel 689 0.0125 0.020 - - 11.5 MMSF3300R2 2.5 Single N-Channel 705 0.040 0.050 - - 6.5 MMSF5N03HDR2 2.5 Single N-Channel 733 0.028 0.040 - - 8.2 MMSF7N03HDR2 2.5 Single N-Channel 742 0.085 0.115 - - 3.05 NTMS3P03R2 2.5 Single P-Channel 150 0.070 0.075 - - 4.1 MMDF3N03HDR2 2.0 Dual N-Channel 512 0.035 0.050 - - 6.0 MMDF6N03HDR2 2.0 Dual N-Channel 560 0.085 0.125 - - 3.05 NTMD3P03R2 2.0 Dual P-Channel 120 0.070/0.200 0.075/0.300 - - 4.1 MMDF2C03HDR2 2.0 Complementary 439 25 0.100/0.210 0.160/0.375 - - 3.0/2.0 MMDF1300R2 1.8 Complementary 396 20 0.025 0.040 - - 8.2 MMSF5N02HDR2 2.5 Single N-Channel 724 - 0.045 0.055 - 4.0 NTMS4N01R2 2.5 Single N-Channel 157 0.250 0.400 - - 2.5 MMSF2P02ER2 2.5 Single P-Channel 697 0.075 0.095 - - 5.6 MMSF3P02HDR2 2.5 Single P-Channel 715 - 0.033 - 0.048 5.4 NTMS5P02R2 2.5 Single P-Channel 171 - 0.014 - 0.020 10.0 NTMS10P02R2 2.5 Single P-Channel 143 TC = 25C See Data Sheet for Applicable Mounting Configuration. Available in Tape and Reel only. T1 suffix = 3000 per reel. Available in Tape and Reel only. R2 suffix = 2500 per reel. VGS = 5.0 V Data for all Complementary Devices listed as Nch/Pch. VGS = 3.6 V t 5 sec Devices listed in bold, italic are ON Semiconductor preferred devices. http://onsemi.com 9 Power MOSFET Selector Guide (continued) Table 2. SO-8 (MiniMOS) - Case 751-06 (continued) V(BR)DSS (Volts) Min 20 Max RDS(on) @ VGS 10 V () 4.5 V () 0.100 0.200 - - ID (cont) Amps 3.6 PD (Notes 9. & 10.) (Watts) Max 2.0 Configuration (Note 12.) Dual N-Channel Page No. 451 - 0.035 0.048 0.049 6.5 0.090 0.100 - - 3.8 NTMD6N02R2 2.0 Dual N-Channel 127 MMDF3N02HDR2 2.0 Dual N-Channel 0.250 0.400 - - 503 2.5 MMDF2P02ER2 2.0 Dual P-Channel 0.160 0.180 - 477 - 3.3 MMDF2P02HDR2 2.0 Dual P-Channel - 0.033 485 - 0.050 7.8 NTMD6P02R2 2.0 Dual P-Channel 0.100/0.250 120 0.200/0.400 - - 3.6 MMDF2C02ER2 2.0 Complementary 416 0.090/0.160 0.100/0.180 - - 3.8 MMDF2C02HDR2 2.0 Complementary 427 - 0.024/0.074 - - 7.0 NTMD7C02R2 2.0 Complementary 141 - 0.045 0.055 - 5.1 NTMS4P01R2 2.5 Single P-Channel 164 - 0.180 0.220 - 3.4 MMDF2P01HDR2 2.0 Dual P-Channel 468 - 0.045/0.180 - - 5.2 MMDF2C01HDR2 2.0 Complementary 404 Configuration Page No. 12 2.7 V () 2.5 V () Device (Note 11.) MMDF2N02ER2 Table 3. SO-8 FETKY -- Case 751-06 Max RDS(on) @ VGS V(BR)DSS (Volts) Min 10 V () 4.5 V () 2.7 V () 2.5 V () ID (cont) Amps 30 0.035 0.050 - - 6.0 MMDFS6N303R2 2.0 0.085 0.125 - - 3.05 NTMSD3P303R2 2.0 0.160 0.180 - - 3.3 MMDFS2P102R2 2.0 - 0.090 0.130 0.15 2.4 NTMSD2P102LR2 2.0 0.085 0.125 - - 3.0 NTMSD3P102R2 2.0 20 Device (Note 11.) PD (Notes 9. & 10.) (Watts) Max Dual N-Channel/ Schottky Dual P-Channel/ Schottky Dual P-Channel/ Schottky Dual P-Channel/ Schottky Dual P-Channel/ Schottky 589 198 579 178 188 Table 4. EZFET - SO-8 Power MOSFETs with Zener Gate Protection - Case 751-06 V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 4.5 V () 2.7 V () 2.5 V () ID (cont) Amps Device (Note 11.) PD (Notes 9. & 10.) (Watts) Max Configuration Page No. 50 0.3 - - - 2.0 MMDF2N05ZR2 2.0 Dual N-Channel 459 30 0.03 0.04 - - 7.5 MMSF7N03ZR2 2.5 Single N-Channel 751 0.013 0.018 - - 10 MMSF10N03ZR2 1.6 Single N-Channel 671 - 0.015 0.019 - 10 MMSF10N02ZR2 2.5 Single N-Channel 662 - 0.04 0.05 - 5.0 MMDF5N02ZR2 2.0 Dual N-Channel 551 - 0.027 - 0.035 7.0 MMDF7N02ZR2 2.0 Dual N-Channel 569 20 9. TC = 25C 10. See Data Sheet for Applicable Mounting Configuration. 11. Available in Tape and Reel only. R2 suffix = 2500 per reel. 12. Data for all Complementary Devices listed as Nch/Pch. http://onsemi.com 10 Power MOSFET Selector Guide (continued) Table 5. Micro8 - Case 846A-02 Max RDS(on) @ VGS V(BR)DSS (Volts) Min 10 V () 4.5 V () 2.7 V () 2.5 V () ID (cont) Amps Device (Note 15.) PD (Notes 13. & 14.) (Watts) Max 60 0.22 0.26 - - 1.5 MTDF2N06HDR2 1.25 Dual N-Channel 1115 30 0.04 0.06 - - 5.7 MTSF3N03HDR2 1.79 Single N-Channel 1348 0.085 0.135 - - 2.5 NTTS2P03R2 1.79 Single P-Channel 255 0.12 0.16 - - 2.0 MTDF1N03HDR2 1.25 Dual N-Channel 1104 - 0.04 0.05 - 6.1 MTSF3N02HDR2 1.79 Single N-Channel 1337 - 0.16 0.19 - 1.8 MTSF1P02HDR2 1.8 Single P-Channel 1326 - 0.09 0.13 - 2.4 NTTS2P02R2R2 0.78 Single P-Channel 248 - 0.12 0.16 - 2.8 MTDF1N02HDR2 1.25 Dual N-Channel 1093 20 Configuration Page No. - 0.16 0.25 - 1.45 NTTD1P02R2 1.25 Dual P-Channel 234 - 0.090 0.130 - 2.4 NTTD2P02R2 1.25 Dual P-Channel 241 Device (Note 16.) PD (Notes 13. & 14.) (Watts) Max Page No. Table 6. SOT-223 - Case 318E-04 V(BR)DSS (Volts) Min Max RDS(on) @ VGS ID (cont) Amps 10 V () 5.0 V () 2.7 V () 2.5 V () 240 6.0 - - 10 0.7 MMFT2406T1/T3 1.5 605 200 14 - - - 0.25 MMFT107T1/T3 0.8 599 60 0.13 - - - 1.7 MMFT3055VT1/T3 2.0 628 - 0.14 - - 1.5 MMFT3055VLT1/T3 2.0 637 1.7 - - - 0.3 MMFT960T1 0.8 656 - 0.15 - - 1.6 MMFT2N02ELT1 0.8 619 60 0.3 - - - 1.2 MMFT2955ET1/T3 0.8 610 30 0.1 - - - 5.2 MMFT5P03HDT3 3.13 646 PD (Notes 13. & 14.) (Watts) Max Page No. N-Channel 20 P-Channel Table 7. TSOP-6 - Case 318G-02 V(BR)DSS (Volts) Min Max RDS(on) @ VGS 2.5 V () ID (cont) Amps - - 4.2 MGSF3454VT1 2.0 349 - 0.095 4.0 MGSF3442VT1 2.0 344 0.045 - 0.055 5.8 NTGS3446T1 1.6 73 0.100 0.170 - - 3.5 NTGS3455T1 2.0 76 - 0.09 - 0.135 3.3 NTGS3441T1 2.0 61 - 0.065 0.090 0.100 4.4 NTGS3443T1 2.0 67 0.175 0.28 - - 1.3 MGSF2P02HDT1 2.0 336 - .075 .095 - 3.3 NTGS3433T1 2.0 57 10 V () 4.5 V () 2.7 V () 30 0.065 0.095 20 - 0.07 - 30 20 Device (Note 17.) N-Channel P-Channel 12 13. TC = 25C 14. See Data Sheet for Applicable Mounting Configuration. 15. Available in Tape and Reel only. R2 suffix = 4000 per reel. 16. Available in Tape and Reel only. T1 suffix = 1000 per reel, T3 suffix = 4000 per reel. 17. Available in Tape and Reel only. T1 suffix = 3000 per reel. http://onsemi.com 11 Power MOSFET Selector Guide (continued) Table 8. TSSOP-8 - Case 318G-02 V(BR)DSS (Volts) Min 20 Max RDS(on) @ VGS 0.04 ID (cont) Amps 5.8 Device (Note 20.) NTQD6866R2 PD (Notes 18. & 19.) (Watts) Max 1.6 Configuration Dual N-Channel Page No. 230 - 6.2 NTQS6463R2 1.05 Single P-Channel 232 Device (Note 21.) PD (Notes 18. & 19.) (Watts) Max Page No. 10 V () 4.5 V () 2.7 V () 2.5 V () - 0.03 (Note 23.) - - 0.020 0.027 Table 9. SOT-23 - Case 318-08 Max RDS(on) @ VGS V(BR)DSS (Volts) Min 10 V () 4.5 V () 2.5 V () ID (cont) Amps 100 6.0 - - 0.17 BSS123LT1/T3 0.225 280 60 5.0 - - 0.50 MMBF170LT1/T3 0.225 384 7.5 - - 0.115 2N7002LT1/T3 0.225 267 50 - 3.5 @ 5.0 V 7.0 @ 2.75 0.20 BSS138LT1/T3 0.225 284 30 0.1 0.145 - 0.75 MGSF1N03LT1 0.4 324 20 0.09 0.13 - 0.75 MGSF1N02LT1 0.4 320 1.0 1.4 - 0.3 MMBF0201NLT1 0.225 372 - 0.085 0.115 0.75 MGSF1N02ELT1 0.4 316 50 - 10 @ 5.0 V - 0.13 BSS84LT1 0.225 289 20 - 0.26 0.5 0.75 MGSF1P02ELT1 0.4 328 0.35 0.5 - 0.75 MGSF1P02LT1 0.4 332 1.4 3.5 - 0.3 MMBF0202PLT1 0.225 377 PD (Notes 18. & 19.) (Watts) Max VGS (Volts) Min Page No. N-Channel P-Channel Table 10. SC-70 / SOT-323 - Case 419-02 V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 4.5 V () 2.7 V () ID (cont) Amps Device (Note 22.) N-Channel 30 - 50 - 0.10 MMBF1374T1 0.10 1.0 382 20 1.0 1.4 - 0.30 MMBF2201NT1 0.15 1.0 388 2.2 3.5 - 0.30 MMBF2202PT1 0.15 1.0 392 PD (Notes 18. & 19.) (Watts) Max VGS (Volts) Min Page No. 0.15 0.5 262 P-Channel 20 Table 11. SC-88 / SOT-363 - Case 419B-01 V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 4.5 V () 2.7 V () ID (cont) Amps 10 - - 0.1 Device (Note 22.) N-Channel 20 NTUD01N02 18. TC = 25C 19. See Data Sheet for Applicable Mounting Configuration. 20. Available in Tape and Reel only. R2 suffix = 4000 per reel. 21. Available in Tape and Reel only. T1 suffix = 3000 per reel, T3 suffix = 10,000 per reel. 22. Available in Tape and Reel only. T1 suffix = 3000 per reel. 23. VGS = 4.0 V http://onsemi.com 12 Power MOSFET Selector Guide (continued) Table 12. DPAK - Case 369A-13 (TO-252) V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 5.0 V () 2.7 V () ID (cont) Amps - 4.0 6.0 PD (Notes 24. & 25.) (Watts) Max Page No. MTD4N20E 40 1048 MTD6N20E 50 1066 Device (Note 26.) N-Channel 200 1.2 - 0.07 - 100 0.25 - - 9.0 MTD9N10E 40 1084 60 0.094 - - 12 NTD3055-094 36 35 - 0.104 - 12 NTD3055L104 36 37 0.15 - - 12 MTD3055V 48 1019 - 0.18 - 12 MTD3055VL 48 1028 0.12 - - 15 MTD15N06V 55 942 - 0.085 - 15 MTD15N06VL 60 951 0.045 - - 20 MTD20N06HD 40 970 - 0.045 - 20 MTD20N06HDL 40 980 0.046 - - 20 NTD20N06 60 33 0.026 - - 32 NTD32N06 60 39 - 0.028 - 32 NTD32N06L 60 44 - 0.035 - 20 MTD20N03HDL 74 960 0.022 - - 20 MTD1302 74 932 - 0.027 - 20 NTD20N03L27 74 29 0.010 0.013 - 20 NTD4302 62 49 0.010 - - 30 MTD3302 96 1037 100 0.66 - - 6.0 MTD6P10E 50 1075 60 0.45 - - 5.0 MTD5P06V 40 1057 0.20 - - 12 MTD2955V 60 1010 - 0.175 - 15 MTD20P06HDL 72 1000 - 0.099 - 19 MTD20P03HDL 75 990 30 P-Channel 30 24. TC = 25C 25. See Data Sheet for Applicable Mounting Configuration. 26. Also available in Tape and Reel. T4 suffix = 2500 per reel. http://onsemi.com 13 Power MOSFET Selector Guide (continued) Table 13. D2PAK - Case 418B-03 (TO-264) V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 5.0 V () 2.7 V () ID (cont) Amps PD (Notes 27. & 28.) (Watts) Max Page No. 200 0.16 - - 20 150 0.07 - - 29 MTB20N20E 125 772 MTB29N15E 125 100 0.04 - - 790 40 MTB40N10E 169 60 0.04 - 825 - 32 MTB36N06V 90 816 Device (Note 29.) N-Channel - 0.05 - 30 MTB30N06VL 90 798 0.026 - - 45 NTB45N06 120 210 - 0.028 - 45 NTB45N06L 120 215 0.028 - - 42 MTB50N06V 125 834 - 0.032 - 42 MTB50N06VL 125 843 0.022 - - 52 MTB52N06V 165 862 - 0.025 - 52 MTB52N06VL 188 871 0.016 - - 55 MTB55N06Z 136 880 0.014 - - 60 MTB60N06HD 125 895 0.010 - - 75 MTB75N06HD 125 922 50 0.0095 - - 75 MTB75N05HD 125 915 - 0.014 - 60 MTB60N05HDL 150 885 30 0.0065 - - 75 MTB1306 150 765 0.0065 - - 75 NTB75N03-06 150 220 - 0.009 - 75 NTB75N03L09 150 225 - 0.009 - 75 MTB75N03HDL 125 905 0.12 - - 23 MTB23P06V 90 781 0.08 - - 30 MTB30P06V 125 807 - 0.025 - 50 MTB50P03HDL 125 852 25 P-Channel 60 30 27. TC = 25C 28. See Data Sheet for Applicable Mounting Configuration. 29. Also available in Tape and Reel. T4 suffix = 800 per reel. http://onsemi.com 14 Power MOSFET Selector Guide (continued) Table 14. TO-220AB - Case 221A-09 V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 5.0 V () 2.7 V () ID (cont) Amps PD (Note NO TAG) (Watts) Max Page No. 0.70 - - 7.0 0.16 - - 20 MTP7N20E 50 1320 MTP20N20E 125 0.07 - - 1175 29 MTP29N15E 125 0.13 - 1199 - 20 MTP20N15E 112 1173 0.25 0.07 - - 10 MTP10N10E 75 1123 - - 27 MTP27N10E 104 1187 0.04 - - 40 MTP40N10E 169 1243 - 0.22 - 10 MTP10N10EL 40 1130 0.150 - - 12 MTP3055V 48 1213 - 0.18 - 12 MTP3055VL 48 1219 0.12 - - 15 MTP15N06V 55 1155 - 0.085 - 15 MTP15N06VL 60 1161 0.085 - - 20 MTP20N06V 60 1167 0.046 - - 27 NTP27N06 74 208 0.04 - - 32 MTP36N06V 90 1237 - 0.05 - 30 MTP30N06VL 90 1225 0.026 - - 45 NTP45N06 120 210 - 0.028 - 45 NTP45N06L 120 215 0.028 - - 42 MTP50N06V 125 1249 - 0.032 - 42 MTP50N06VL 125 1255 0.022 - - 52 MTP52N06V 165 1268 - 0.025 - 52 MTP52N06VL 165 1274 0.014 - - 60 MTP60N06HD 150 1286 0.01 - - 75 MTP75N06HD 150 1313 Device N-Channel 200 150 100 60 50 0.0095 - - 75 MTP75N05HD 150 1306 30 0.022 0.029 - 42 MTP1302 74 1141 0.0065 0.0085 - 75 MTP1306 150 1148 0.0065 - - 75 NTP75N03-06 150 220 - 0.009 - 75 NTP75N03L09 150 225 - 0.009 - 75 MTP75N03HDL 150 1299 500 6.0 - - 2.0 MTP2P50E 75 1207 200 1.0 - - 6.0 MTP6P20E 75 1293 100 0.30 - - 12 MTP12P10 75 1136 60 0.45 - - 5.0 MTP5P06V 40 1280 0.20 - - 12 MTP2955V 60 1193 0.12 - - 23 MTP23P06V 90 1181 0.08 - - 30 MTP30P06V 125 1231 - 0.025 - 50 MTP50P03HDL 125 1261 25 P-Channel 30 30. TC = 25C http://onsemi.com 15 Power MOSFET Selector Guide (continued) Table 15. TO-247 (Isolated Mounting Hole) - Case 340K-01 V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 4.5 V () 2.7 V () ID (cont) Amps PD (Note 31.) (Watts) Max Page No. 250 0.08 - - 32 200 0.075 - - 32 MTW32N25E 250 1365 MTW32N20E 180 150 0.05 - - 1359 35 MTW35N15E 180 100 0.035 - - 1371 45 MTW45N10E 180 1377 PD (Note 31.) (Watts) Max Page No. 300 1383 PD (Notes 31. & 32.) (Watts) Max Page No. Device N-Channel Table 16. TO-264 - Case 340G-02 V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 4.5 V () 2.7 V () ID (cont) Amps 0.028 - - 55 Device N-Channel 200 MTY55N20E Table 17. SMARTDISCRETES V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 5.0 V () 2.7 V () Function - 0.75 - Current Limit, ESD MLP1N06CL 40 360 - 0.40 - Current Limit, ESD MLP2N06CL 40 366 - 0.75 - Current Limit, ESD MLD1N06CLT4 (Note 33.) 40 354 40 V - 0.02 - Temp Sense, ESD, Overvoltage Protect NIB6404-5L 115 23 30 V 0.05 - - Current Mirror, ESD Protect NIMD6302R2 (Note 34.) 20 27 Device TO-220AB 62 (Clamped) DPAK 62 (Clamped) D2PAK - 5 Lead SO-8 31. TC = 25C 32. See Data Sheet for Applicable Mounting Configuration. 33. Available in Tape and Reel only. T4 suffix = 2500 per reel. 34. Available in Tape and Reel only. R2 suffix = 2500 per reel. http://onsemi.com 16 Power MOSFET Selector Guide (continued) Table 18. TO-92 V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 4.5 V () 2.7 V () ID (cont) Amps Device PD (Note 35.) (Watts) Max Page No. N-Channel 240 200 10 - 10 @ 2.5 V 0.2 VN2410L 0.35 1396 6.0 - 10 @ 2.5 V 0.2 VN2406L 0.35 1394 - 8.0 @ 2.8 V 10 @ 2.5 V 0.25 BS108 0.35 275 14 - 28 @ 2.6 V 0.25 BS107 0.35 271 6.0 - - 0.25 BS107A 0.35 271 90 2.0 - - 2.0 MPF990 1.0 761 60 7.5 - - 0.15 VN2222LL 0.4 1391 5.0 - - 0.5 BS170 0.35 277 5.0 6.0 - 0.2 2N7000 0.35 264 1.7 - - 2.0 MPF960 1.0 761 1.2 3.3 @ 5 V - 0.2 VN0300L 0.35 1389 1.4 - - 2.0 MPF930 1.0 761 1.4 - - 2.0 MPF930A 1.0 761 PD (Notes 35. & 36.) (Watts) Max Page No. 35 Table 19. Ignition IGBTs - Insulated Gate Bipolar Transistors V(BR)CES (Volts) Min Max VCE(on) @ VGE 4.0 V IC = 6.0 A 4.5 V IC = 10 A IC (pulse) Amps IC (cont) Amps 400 V (Clamped) 1.6 1.9 50 15 MGP15N40CL 150 301 350 V (Clamped) 1.6 1.9 50 15 MGP15N35CL 150 293 1.6 1.8 50 19 MGP19N35CL 166 309 400 V (Clamped) 1.6 1.9 50 15 MGB15N40CLT4 (Note 37.) 150 301 350 V (Clamped) 1.6 1.9 50 15 MGB15N35CLT4 (Note 37.) 150 293 1.6 1.8 50 19 MGB19N35CLT4 (Note 37.) 166 309 1.7 2.1 50 15 NGD15N41CLT4 (Note 38.) 96 21 Device TO-220AB D2PAK DPAK 410 V (Clamped) 35. TC = 25C 36. See Data Sheet for Applicable Mounting Configuration. 37. Available in Tape and Reel only. T4 suffix = 800 per reel. 38. Available in Tape and Reel only. T4 suffix = 2500 per reel. http://onsemi.com 17 http://onsemi.com 18 CHAPTER 1 MOSFET Data Sheets http://onsemi.com 19 http://onsemi.com 20 N-Channel DPAK This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Over-Voltage clamped protection for use in inductive coil drivers applications. Primary uses include Ignition, Direct Fuel Injection, or wherever high voltage and high current switching is required. * Ideal for Coil-on-Plug Applications * DPAK Package Offers Smaller Footprint and Increased Board Space * Gate-Emitter ESD Protection * Temperature Compensated Gate-Collector Voltage Clamp Limits Stress Applied to Load * Integrated ESD Diode Protection * New Cell Design Increases Unclamped Inductive Switching (UIS) Energy Per Area * Short-Circuit Withstand Capability * Low Threshold Voltage to Interface Power Loads to Logic or Microprocessor Devices * Low Saturation Voltage * High Pulsed Current Capability * Optional Gate Resistor (RG) and Gate-Emitter Resistor (RGE) http://onsemi.com 15 AMPS 410 VOLTS VCE(on) @ 10 A = 2.1 V MAX C RG G RGE E MARKING DIAGRAM MAXIMUM RATINGS (-55C TJ 175C unless otherwise noted) Symbol Value Unit Collector-Emitter Voltage VCES 440 VDC Collector-Gate Voltage VCER 440 VDC VGE 15 VDC IC 15 ADC TJ, Tstg -55 to 175 C Rating Gate-Emitter Voltage Collector Current-Continuous @ TC = 25C Operating and Storage Temperature Range DPAK CASE 369A STYLE 2 TBD TBD = Specific Device Code ORDERING INFORMATION Device Package Shipping NGD15N41CL DPAK 75 Units/Rail NGD15N41CLT4 DPAK 2500/Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2001 March, 2001 - Rev. 2 21 Publication Order Number: NGD15N41CL/D NGD15N41CL UNCLAMPED COLLECTOR-TO-EMITTER AVALANCHE CHARACTERISTICS (-55C TJ 175C) Characteristic Symbol Single Pulse Collector-to-Emitter Avalanche Energy VCC = 50 V, VGE = 5 V, Pk IL = 16 A, L = 1.8 mH, Starting TJ = 25C VCC = 50 V, VGE = 5 V, Pk IL = 15 A, L = 1.8 mH, Starting TJ = 150C Value Unit EAS mJ 225 200 THERMAL CHARACTERISTICS Thermal Resistance, Junction to Ambient DPAK RJA 100 C/W TL 275 C Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Test Conditions Min Typ Max Unit BVCES IC = 2 mA TJ = -40C to 175C 380 410 440 VDC ICES VCE = 300 V, VGE = 0, TJ = 25C - - 40 ADC VCE = 300 V, VGE = 0, TJ = 150C - - 200 IECS VCE = -24 V - - 1.0 mA BVGES IG = 5 mA 10 - 16 VDC RG - - 70 - RGE - 10 - 26 k VGE(th) IC = 1 mA VGE = VCE 1.0 1.4 2.1 VDC - - - 4.4 - mV/C Collector-to-Emitter On-Voltage VCE(on) IC = 6 A, VGE = 4 V - - 1.8 VDC Collector-to-Emitter On-Voltage VCE(on) IC = 10 A, VGE = 4.5 V, TJ = 150C - - 2.1 VDC Input Capacitance CISS VCC = 15 V - 700 - pF Output Capacitance COSS VGE = 0 V - 60 - Transfer Capacitance CRSS f = 1 MHz - 6.0 - td(off) VCC = 300 V, IC = 10 A - 4.0 - tf RG = 1 k, L = 300 H - 10 - td(on) VCC = 10 V, IC = 6.5 A - 1.0 - tr RG = 1 k, RL = 1 - 4.0 - OFF CHARACTERISTICS Collector-Emitter Clamp Voltage Zero Gate Voltage Collector Current Reverse Collector-Emitter Leakage Current Gate-Emitter Clamp Voltage Gate Resistor (Optional) Gate Emitter Resistor (Optional) ON CHARACTERISTICS* Gate Threshold Voltage Threshold Temperature Coefficient (Negative) DYNAMIC CHARACTERISTICS SWITCHING CHARACTERISTICS* Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time *Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. http://onsemi.com 22 Sec Sec Preferred Device t Self Protected with Temperature Sense N-Channel D2PAK http://onsemi.com SMARTDISCRETES devices are an advanced series of Power MOSFETs which utilize ON Semiconductor's latest MOSFET technology process to achieve the lowest possible on-resistance per silicon area while incorporating additional features such as clamp diodes. They are capable of withstanding high energy in the avalanche and commutation modes. The avalanche energy is specified to eliminate guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. This new SMARTDISCRETES device features integrated Gate-to-Source diodes for ESD protection, and Gate-to-Drain clamp for overvoltage protection. Also, this device integrates a sense diode for temperature monitoring. * Ultra Low RDS(on) Provides Higher Efficiency * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Overvoltage Protection * Temperature Sense Diode * ESD Human Body Model Discharge Sensitivity Class 3 Rating Drain-to-Gate Voltage Gate-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (Note 1.) (VDD = 25 Vdc, VGS = 5.0 Vdc, IL(pk) = 25 A, L = 1.4 mH, RG = 10 k) Drain Current - Continuous @ TA = 25C - Continuous @ TA = 140C - Single Pulse (tpv10 s) Total Power Dissipation (t 10 seconds) Linear Derating Factor Thermal Resistance - Junction-to-Case - Junction-to-Ambient (Note 1.) Symbol Value Unit VDSS VDGR 40 Vdc 40 Vdc VGS TJ, Tstg "10 Vdc -55 to +175 C 450 mJ EAS T2 T1 MARKING DIAGRAM TBD D2PAK CASE 936D PLASTIC MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Drain-to-Source Voltage 52 AMPERES 40 VOLTS RDS(on) = 20 m TBD = Specific Device Code ORDERING INFORMATION Device NIB6404-5L Adc ID ID IDM PD @ TA = 25C 52 25 200 115 0.76 RJC RJA 1.3 80 Package D2PAK Shipping TBD Preferred devices are recommended choices for future use and best overall value. W W/C C/W 1. Measured while surface mounted to an FR4 board using the minimum recommended pad size. Typical value is 64C/W. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2001 February, 2001 - Rev. 1 23 Publication Order Number: NIB6404-5L/D NIB6404-5L ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 40 - 51 7.0 55 - mV/C 10 13 20 Vdc - - - 1.1 0.2 4.0 100 2.0 20 - 0.02 1.0 1.0 - 1.7 4.5 2.0 - mV/C OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 2.) (VGS = 0 Vdc, ID = 250 Adc, -55C < TJ < 175C) Temperature Coefficient (Negative) V(BR)DSS Gate-to-Source Clamp Voltage (Note 2.) (VGS = 0 Vdc, IG = 20 Adc) V(BR)GSS Zero Gate Voltage Drain Current (VDS = 35 Vdc, VGS = 0 Vdc) (VDS = 15 Vdc, VGS = 0 Vdc) (VDS = 35 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 5.0 Vdc, VDS = 0 Vdc) IGSS Vdc Adc Adc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Note 2.) (VDS = VGS, ID = 1.0 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (Note 2.) (VGS = 5.0 Vdc, ID = 20 Adc) RDS(on) - 18 20 m gFS TBD 34 - mhos Ciss - 1720 - pF Coss - 525 - Crss - 120 - td(on) - 16 - tr - 263 - td(off) - 149 - tf - 345 - QT - 29 - Q1 - 6.0 - Q2 - 16 - Q3 - 2.0 - VSD - - 0.876 0.746 1.2 - Vdc trr - 60 - ns ta - 29 - tb - 32 - QRR - 80 - pC (IF(R) = 250 Adc) (Note 2.) (IF(R) = 250 Adc, TJ = 125C) VAC(ACR) 715 - 743 570 775 - mVdc IF(R) = 250 Adc, TJ = 160C VFTC 1.57 1.71 1.85 mV/C IF(R) = 125 Adc to 250 Adc Vhys 25 37 50 mVdc Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) (Note 2.) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 32 Vdc, ID = 25 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 10 ) (Note 2.) Fall Time Gate Charge (VDS = 32 Vdc, ID = 25 Adc, VGS = 5.0 Vdc) (Note 2.) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 2.) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 25 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 2.) Reverse Recovery Stored Charge TEMPERATURE SENSE DIODE CHARACTERISTICS Forward (Reverse) On-Voltage Temperature Coefficient (Negative) Forward Voltage Hysteresis 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 24 NIB6404-5L TYPICAL ELECTRICAL CHARACTERISTICS 40 5.0 V 45 4.0 V 4.5 V 40 I D, DRAIN CURRENT (AMPS) I D, DRAIN CURRENT (AMPS) 50 3.5 V 35 TJ = 25C 30 25 20 3.0 V 15 10 0 25 20 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 25C 10 -55C 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (mW) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 50 45 TJ = 175C 40 35 30 25 25C 20 15 10 -55C 5.0 0 0 10 20 30 40 50 ID, DRAIN CURRENT (AMPS) 3.5 50 45 40 VGS = 3.0 V 35 3.5 V 30 25 4.0 V 20 5.0 V 15 10 V 10 5.0 TJ = 25C 0 0 10 20 30 40 50 ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 2.2 4500 VGS = 5.0 V ID = 20 A 2.0 1.8 1.6 1.4 1.2 1.0 3000 2500 2000 1000 0.6 0 50 100 150 200 Ciss 1500 500 0 TJ = 25C 3500 0.8 -50 VGS = 0 V f = 1.0 MHz 4000 C, CAPACITANCE (pF) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) TJ = 175C 15 0 0 RDS(on), DRAIN-TO-SOURCE RESISTANCE (mW) 30 5.0 VGS = 2.5 V 5.0 35 Coss Crss 0 5.0 10 15 20 25 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (C) Figure 5. On-Resistance Variation with Temperature Figure 6. Capacitance Variation http://onsemi.com 25 30 NIB6404-5L TYPICAL ELECTRICAL CHARACTERISTICS 20 5000 Ciss 18 IS, SOURCE CURRENT (A) C, CAPACITANCE (pF) 4500 4000 3500 3000 Coss 2500 2000 1500 1000 TJ = 25C VDS = 0 V f = 1 MHz 500 14 12 10 8.0 6.0 TJ = 175C 4.0 25C 2.0 0 0 0 2.0 4.0 6.0 8.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 7. Capacitance Variation Figure 8. Diode Forward Voltage versus Current IF(R) = 500 mA 0.8 250 mA 0.7 125 mA 0.6 0.5 50 mA 0.4 25 mA -50 0 50 100 200 150 VFTC, TEMPERATURE COEFFICIENT (mV/C) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 0.9 0.3 -100 0 10 1.0 VF, FORWARD VOLTAGE (V) 16 -1.3 -1.4 -1.5 -1.6 IF(R) = 250 mA -1.7 -1.8 -1.9 -2.0 -2.1 -50 0 50 100 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 9. Sense Diode Forward Voltage Variation with Temperature Figure 10. Sense Diode Temperature Coefficient Variation with Temperature http://onsemi.com 26 1.0 150 ! t ! Self Protected with Current Sense http://onsemi.com N-Channel SO-8, Dual SMARTDISCRETES devices are an advanced series of Power MOSFETs which utilize ON Semiconductor's latest MOSFET technology process to achieve the lowest possible on-resistance per silicon area while incorporating smart features. They are capable of withstanding high energy in the avalanche and commutation modes. The avalanche energy is specified to eliminate guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. This new SMARTDISCRETES device features an integrated Gate-to-Source clamp for ESD protection. Also, this device features a sense FET for current monitoring. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Current Sense FET * ESD Protected, Main FET and SENSEFET 5.0 AMPERES 30 VOLTS RDS(on) = 50 m Drain Gate Sense Main FET Source Sense Source Main ABSOLUTE MAXIMUM RATINGS SOIC-8 CASE 751 STYLE 19 Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in this specification is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. MAIN MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 MW) Gate-to-Source Voltage Single Pulse Drain-to-Source Avalanche Energy (Note 1.) (VDD = 25 Vdc, VGS = 10 Vdc, VDS = 20 Vdc, IL = 15 Apk, L = 10 mH, RG = 25 ) Drain Current - Continuous @ TA = 25C - Continuous @ TA = 100C (Note 1.) - Single Pulse (tpv10 s) Symbol Value Unit VDSS VDGR 30 Vdc 30 Vdc VGS EAS "16 Vdc 250 mJ MARKING DIAGRAM Source 1 Gate 1 Source 2 Gate 2 1 8 2 7 3 TBD 6 5 4 Mirror 1 Drain 1 Mirror 2 Drain 2 (Top View) TBD = Specific Device Code ORDERING INFORMATION ID 6.5 Adc ID 4.4 Adc IDM 33 Apk Maximum Power Dissipation (TA = 25C) PD TBD W 1. Switching characteristics are independent of operating junction temperatures Device NIMD6302R2 Package SOIC-8 Shipping TBD This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2001 February, 2001 - Rev. 1 27 Publication Order Number: NIMD6302R2/D NIMD6302R2 MAIN MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - 35 30 - - Vdc mV/C - - - - 10 100 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Adc Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) IGSS - 22 32 Adc Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) 1.0 - - 5.0 2.0 - Vdc mV/C Static Drain-to-Source On-Resistance (Note 2.) (VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 25C) (VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 125C) RDS(on) - - - - 50 TBD - - 7.4 5.5 - - Ciss - 380 600 Coss - 272 350 Crss - 93 200 td(on) - 8.4 - tr - 24 - td(off) - 18 - ON CHARACTERISTICS Forward Transconductance (Note 2.) (VDS = 6.0 Vdc, ID = 15 Adc) (VDS = 15 Vdc, ID = 15 Adc) m gFS mhos DYNAMIC CHARACTERISTICS (Note 3.) Input Capacitance Output Capacitance (VDS = 6.0 6 0 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 6.0 Vdc, ID = 3.0 Adc, VGS = 10 Vdc, RG = 4.7 ) Fall Time Gate Charge (VDS = 6.0 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) tf - 5.0 - QT - 11.3 - Q1 - 2.8 - Q2 - 1.9 - Q3 - 2.2 - VSD S - 0.76 - - 0.62 - trr - 24.7 - ta - 13 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) Forward On-Voltage (Notes 2., 3.) (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (Note 3.) (IS = 3.0 3 0 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge (Note 3.) MIRROR MOSFET CHARACTERISTICS (TJ = 25C unless otherwise noted) Main/Mirror MOSFET (VDS = 6.0 Vdc, IDmain = 25 mA) Current Ratio (VDS = 6.0 Vdc, IDmain = 25 mA, TA = 125C) Main/Mirror Current Ratio Variation versus Current and Temperature Gate-Body Leakage Current (VDS = 6.0 Vdc, IDmain = 25 mA, TA = 25 to 125C) VDS = 0 Vdc, VGS = 3.0 Vdc 2. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%. 3. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 28 Vdc ns tb - 12 - QRR - 0.018 - mC IRAT 192 192 200 200 208 208 - IDRAT -7.5 3.0 +7.5 % IGSS - - 100 nAdc ! " #$%& '( ! N-Channel DPAK This logic level vertical power MOSFET is a general purpose part that provides the "best of design" available today in a low cost power package. Avalanche energy issues make this part an ideal design in. The drain-to-source diode has a ideal fast but soft recovery. http://onsemi.com 20 AMPERES 30 VOLTS RDS(on) = 27 m Features * * * * * * Ultra-Low RDS(on), single base, advanced technology SPICE parameters available Diode is characterized for use in bridge circuits IDSS and VDS(on) specified at elevated temperatures High Avalanche Energy Specified ESD JEDAC rated HBM Class 1, MM Class A, CDM Class 0 N-Channel D Typical Applications * * * * Power Supplies Inductive Loads PWM Motor Controls Replaces MTD20N03L in many applications G S MARKING DIAGRAM MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous - Non-Repetitive (tpv10 ms) Drain Current - Continuous @ TA = 25_C - Continuous @ TA = 100_C - Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25_C Derate above 25C Total Power Dissipation @ TC = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 30 Vdc, VGS = 5 Vdc, L = 1.0 mH, IL(pk) = 24 A, VDS = 34 Vdc) Thermal Resistance - Junction-to-Case - Junction-to-Ambient - Junction-to-Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol Value Unit VDSS VDGR 30 Vdc 30 Vdc Vdc VGS VGS "20 "24 ID ID IDM PD 20 16 60 Adc 74 0.6 1.75 Watts W/C W TJ, Tstg -55 to 150 C EAS 288 mJ January, 2001 - Rev. 0 CASE 369A DPAK STYLE 2 1 2 3 20N3L Y WW = Device Code = Year = Work Week PIN ASSIGNMENT 4 Drain 1 Gate C/W RJC RJA RJA TL YWW 20N3L Apk 1.67 100 71.4 2 Drain 3 Source ORDERING INFORMATION C 260 1. When surface mounted to an FR4 board using the minimum recommended pad size and repetitive rating; pulse width limited by maximum junction temperature. Semiconductor Components Industries, LLC, 2001 4 29 Device Package Shipping NTD20N03L27 DPAK 75 Units/Rail NTD20N03L27-1 DPAK 75 Units/Rail NTD20N03L27T4 DPAK 2500 Tape & Reel Publication Order Number: NTD20N03L27/D NTD20N03L27 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - 43 - - - - - - 10 100 - - 100 1.0 - 1.6 5.0 2.0 - - - 28 23 31 27 - - 0.48 0.40 0.54 - gFS - 21 - mhos Ciss - 1005 1260 pF Coss - 271 420 Crss - 87 112 td(on) - 17 25 tr - 137 160 td(off) - 38 45 tf - 31 40 QT - 13.8 18.9 Q1 - 2.8 - Q2 - 6.6 - - - 1.0 0.9 1.15 - trr - 23 - ta - 13 - tb - 10 - QRR - 0.017 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 2.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ =150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Note 2.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (Note 2.) (VGS = 4.0 Vdc, ID = 10 Adc) (VGS = 5.0 Vdc, ID = 10 Adc) RDS(on) Static Drain-to-Source On-Resistance (Note 2.) (VGS = 5.0 Vdc, ID = 20 Adc) (VGS = 5.0 Vdc, ID = 10 Adc, TJ = 150C) VDS(on) Forward Transconductance (Note 2.) (VDS = 5.0 Vdc, ID = 10 Adc) Vdc mV/C m Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 20 Vdc, ID = 20 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) (Note 2.) Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 15 Adc, Ad VGS = 10 Vdc) (Note 2.) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage VSD (IS = 20 Adc, VGS = 0 Vdc) (Note 2.) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS =15 15 Adc, Adc VGS = 0 Vdc, Vdc dlS/dt = 100 A/s) (Note 2.) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 30 Vdc ns C NTD20N03L27 40 VGS = 10 V 35 VGS = 4 V VGS = 8 V 30 ID, DRAIN CURRENT (AMPS) -ID, DRAIN CURRENT (AMPS) 40 VGS = 4.5 V VGS = 5 V 25 VGS = 3.5 V 20 VGS = 6 V 15 VGS = 3 V 10 TJ = 25C 5 VGS = 2.5 V 0 0.2 0.4 0.6 1 0.8 1.2 1.4 1.6 1.8 28 24 TJ = 100C 20 16 TJ = 25C TJ = -55C 12 8 4 1 1.5 2 2.5 3 3.5 4 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE () -VGS, GATE-TO-SOURCE VOLTAGE (V) VGS = 5 V TJ = 100C 0.03 TJ = 25C VGS = 5 V 0.025 0.03 TJ = 25C 0.025 0.02 TJ = -55C 0.015 0.01 5 4.5 -VDS, DRAIN-TO-SOURCE VOLTAGE (V) 0.04 0.035 32 0 0.5 2 0.02 VGS = 10 V 0.015 0.005 0 2 5 8 12 15 18 22 25 28 32 35 38 4 8 12 16 20 24 28 32 36 40 ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Drain Current and Temperature Figure 4. On-Resistance vs. Drain Current and Gate Voltage 1000 ID = 10 A VGS = 5 V VGS = 0 V 1.2 1 0.8 0.6 -50 0 ID, DRAIN CURRENT (AMPS) 1.6 1.4 0.01 -IDSS, LEAKAGE (nA) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN-TO-SOURCE RESISTANCE () 0 VDS > = 10 V 36 TJ = 125C 100 TJ = 100C 10 1 -25 0 25 50 75 100 125 150 0 3 6 9 12 15 18 21 24 27 TJ, JUNCTION TEMPERATURE (C) -VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage http://onsemi.com 31 30 NTD20N03L27 VGS, GATE-TO-SOURCE VOLTAGE (V) 2500 C, CAPACITANCE (pF) VGS - VDS 200 1500 Ciss 1000 Coss 500 Crss 0 10 8 6 4 2 0 2 4 6 8 10 12 14 16 18 20 23 25 Q 10 8 VGS 6 Q1 4 Q2 2 0 ID = 20 A TJ = 25C 0 2 4 6 8 10 12 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge 1000 14 IS, SOURCE CURRENT (AMPS) 20 tr 100 tf td(off) 10 td(on) VDS = 20 V ID = 20 A VGS = 5.0 V TJ = 25C 1 1 10 100 VGS = 0 V TJ = 25C 18 16 14 12 10 8 6 4 2 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 RG, GATE RESISTANCE () VSD, SOURCE-TO-DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) t, TIME (ns) 12 350 ID = 24 A 300 250 200 150 100 50 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) Figure 11. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 32 150 1.0 #$%& '( N-Channel DPAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. http://onsemi.com 20 AMPERES 60 VOLTS RDS(on) = 46 m Features * * * * * * * Lower RDS(on) Lower VDS(on) Lower Capacitances Lower Total Gate Charge Lower and Tighter VSD Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge N-Channel D Typical Applications * * * * G Power Supplies Converters Power Motor Controls Bridge Circuits 4 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 10 M) Gate-to-Source Voltage - Continuous - Non-repetitive (tpv10 ms) Drain Current - Continuous @ TA = 25C - Continuous @ TA = 100C - Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, L = 1.0 mH, IL(pk) = 18.4 A, VDS = 60 Vdc) Thermal Resistance - Junction-to-Case - Junction-to-Ambient (Note 1.) - Junction-to-Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol Value Unit VDSS VDGR 60 Vdc 60 Vdc VGS VGS "20 "30 ID ID IDM PD 20 10 60 Apk 60 0.40 1.88 1.36 W W/C W W TJ, Tstg -55 to 175 C EAS 170 mJ Adc C/W RJC RJA RJA 2.5 80 110 TL 260 1 CASE 369A DPAK (Bent Lead) STYLE 2 NTD20N06 Y WW 2 3 CASE 369 DPAK (Straight Lead) STYLE 2 = Device Code = Year = Work Week MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain YWW NTD 20N06 YWW NTD 20N06 1 Gate 2 Drain 3 Source 1 Gate 3 Source 2 Drain C ORDERING INFORMATION Device This document contains information on a new product. Specifications and information herein are subject to change without notice. March, 2001 - Rev. 3 1 2 3 Vdc 1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). Semiconductor Components Industries, LLC, 2001 4 S 33 Package Shipping DPAK 75 Units/Rail NTD20N06-1 DPAK Straight Lead 75 Units/Rail NTD20N06T4 DPAK 2500 Tape & Reel NTD20N06 Publication Order Number: NTD20N06/D NTD20N06 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - 71.7 79.4 - - - - - - 1.0 10 - - 100 2.0 - 2.91 6.9 4.0 - - 37.5 46 - - 0.78 1.57 1.10 - gFS - 13.2 - mhos Ciss - 725 1015 pF Coss - 213 300 Crss - 58 120 td(on) - 9.5 20 tr - 60.5 120 td(off) - 27.1 60 tf - 37.1 80 QT - 21.2 30 Q1 - 5.6 - Q2 - 7.3 - VSD - - 1.0 0.87 1.2 - Vdc trr - 42.9 - ns ta - 33 - tb - 9.9 - QRR - 0.084 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 3.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (Note 3.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (Note 3.) (VGS = 10 Vdc, ID = 10 Adc) RDS(on) Static Drain-to-Source On-Voltage (Note 3.) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 10 Adc, TJ = 150C) VDS(on) Forward Transconductance (Note 3.) (VDS = 7.0 Vdc, ID = 6.0 Adc) Vdc mV/C m Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) Turn-On Delay Time (VDD = 30 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) (Note 3.) Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 20 Adc, Ad VGS = 10 Vdc) (Note 3.) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 3.) (IS = 20 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 20 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 3.) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 34 C !) #$%& '( N-Channel DPAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. http://onsemi.com 12 AMPERES 60 VOLTS RDS(on) = 94 m Features * * * * * Lower RDS(on) Lower VDS(on) Lower and Tighter VSD Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge N-Channel D Typical Applications * * * * Power Supplies Converters Power Motor Controls Bridge Circuits G 4 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 10 M) Gate-to-Source Voltage - Continuous - Non-Repetitive (tpv10 ms) Drain Current - Continuous @ TA = 25C - Continuous @ TA = 100C - Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, L = 1.0 mH IL(pk) = 11 A, VDS = 60 Vdc) Thermal Resistance - Junction-to-Case - Junction-to-Ambient (Note 1.) - Junction-to-Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol Value Unit VDSS VDGR 60 Vdc 60 Vdc VGS VGS "20 "30 ID ID IDM PD 12 10 45 Adc 48 0.32 2.1 1.5 W W/C W W TJ, Tstg -55 to +175 C EAS 61 mJ 1 CASE 369A DPAK (Bent Lead) STYLE 2 NTD3055-094 Y WW RJC RJA RJA 3.13 71.4 100 C/W TL 260 C 35 2 3 CASE 369 DPAK (Straight Lead) STYLE 2 = Device Code = Year = Work Week MARKING DIAGRAMS & PIN ASSIGNMENTS Apk This document contains information on a new product. Specifications and information herein are subject to change without notice. March, 2001 - Rev. 1 1 2 3 Vdc 1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). Semiconductor Components Industries, LLC, 2001 4 S 4 Drain 4 Drain YWW NTD 3055-094 YWW NTD 3055-094 1 Gate 2 Drain 3 Source 1 Gate 3 Source 2 Drain ORDERING INFORMATION Device NTD3055-094 Package Shipping DPAK 75 Units/Rail DPAK NTD3055-094-1 Straight Lead NTD3055-094T4 DPAK 75 Units/Rail 2500 Tape & Reel Publication Order Number: NTD3055-094/D NTD3055-094 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - 68 54.4 - - - - - - 1.0 10 - - 100 2.0 - 2.9 6.3 4.0 - - 84 94 - - 0.85 0.77 1.35 - gFS - 6.7 - mhos Ciss - 323 450 pF Coss - 107 150 Crss - 34 70 td(on) - 7.7 15 tr - 32.3 70 td(off) - 25.2 50 tf - 23.9 50 QT - 10.9 20 Q1 - 3.1 - Q2 - 4.2 - VSD - - 0.94 0.82 1.15 - Vdc trr - 33.1 - ns ta - 24 - tb - 8.9 - QRR - 0.047 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 3.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (Note 3.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (Note 3.) (VGS = 10 Vdc, ID = 6.0 Adc) RDS(on) Static Drain-to-Source On-Voltage (Note 3.) (VGS = 10 Vdc, ID = 12 Adc) (VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150C) VDS(on) Forward Transconductance (Note 3.) (VDS = 7.0 Vdc, ID = 6.0 Adc) Vdc mV/C mOhm Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) Turn-On Delay Time Rise Time (VDD = 48 Vdc, ID = 12 Adc, VGS = 10 Vdc, RG = 9.1 ) (Note 3.) Turn-Off Delay Time Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 12 Adc, Ad VGS = 10 Vdc) (Note 3.) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 12 Adc, VGS = 0 Vdc) (Note 3.) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 12 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 3.) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 36 C ! #$%& '( * %+% N-Channel DPAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. http://onsemi.com 12 AMPERES 60 VOLTS RDS(on) = 104 m Features * * * * * Lower RDS(on) Lower VDS(on) Tighter VSD Specification Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge N-Channel D Typical Applications * * * * Power Supplies Converters Power Motor Controls Bridge Circuits G 4 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 10 M) Gate-to-Source Voltage - Continuous - Non-Repetitive (tpv10 ms) Drain Current - Continuous @ TA = 25C - Continuous @ TA = 100C - Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, L = 1.0 mH IL(pk) = 11 A, VDS = 60 Vdc) Thermal Resistance - Junction-to-Case - Junction-to-Ambient (Note 1.) - Junction-to-Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol Value Unit VDSS VDGR 60 Vdc 60 Vdc VGS VGS "15 "20 ID ID IDM PD 12 10 45 Adc 48 0.32 2.1 1.5 W W/C W W TJ, Tstg -55 to +175 C EAS 61 mJ 1 CASE 369A DPAK (Bent Lead) STYLE 2 NTD3055L104 Y WW RJC RJA RJA 3.13 71.4 100 C/W TL 260 C 37 2 3 CASE 369 DPAK (Straight Lead) STYLE 2 = Device Code = Year = Work Week MARKING DIAGRAMS & PIN ASSIGNMENTS Apk This document contains information on a new product. Specifications and information herein are subject to change without notice. March, 2001 - Rev. 1 1 2 3 Vdc 1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). Semiconductor Components Industries, LLC, 2001 4 S 4 Drain 4 Drain YWW NTD 3055L104 YWW NTD 3055L104 1 Gate 2 Drain 3 Source 1 Gate 3 Source 2 Drain ORDERING INFORMATION Device NTD3055L104 Package Shipping DPAK 75 Units/Rail DPAK NTD3055L104-1 Straight Lead NTD3055L104T4 DPAK 75 Units/Rail 2500 Tape & Reel Publication Order Number: NTD3055L104/D NTD3055L104 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - 70 62.9 - - - - - - 1.0 10 - - 100 1.0 - 1.6 4.2 2.0 - - 89 104 - - 0.98 0.86 1.50 - gFS - 9.1 - mhos Ciss - 316 440 pF Coss - 105 150 Crss - 35 70 td(on) - 9.2 20 tr - 104 210 td(off) - 19 40 tf - 40.5 80 QT - 7.4 20 Q1 - 2.0 - Q2 - 4.0 - VSD - - 0.95 0.82 1.2 - Vdc trr - 35 - ns ta - 21 - tb - 14 - QRR - 0.04 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 3.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (Note 3.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (Note 3.) (VGS = 5.0 Vdc, ID = 6.0 Adc) RDS(on) Static Drain-to-Source On-Voltage (Note 3.) (VGS = 5.0 Vdc, ID = 12 Adc) (VGS = 5.0 Vdc, ID = 6.0 Adc, TJ = 150C) VDS(on) Forward Transconductance (Note 3.) (VDS = 8.0 Vdc, ID = 6.0 Adc) Vdc mV/C mOhm Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) Turn-On Delay Time Rise Time (VDD = 30 Vdc, ID = 12 Adc, VGS = 5.0 Vdc, RG = 9.1 ) (Note 3.) Turn-Off Delay Time Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 12 Adc, Ad VGS = 5.0 Vdc) (Note 3.) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 12 Adc, VGS = 0 Vdc) (Note 3.) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 12 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 3.) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 38 C ! #$%& '( ! N-Channel DPAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. http://onsemi.com Features * * * * * * * 32 AMPERES 60 VOLTS RDS(on) = 26 m Smaller Package than MTB36N06V Lower RDS(on) Lower VDS(on) Lower Total Gate Charge Lower and Tighter VSD Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge N-Channel D Typical Applications * * * * G Power Supplies Converters Power Motor Controls Bridge Circuits 4 4 1 2 3 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 10 M) Gate-to-Source Voltage - Continuous - Non-Repetitive (tpv10 ms) Drain Current - Continuous @ TA = 25C - Continuous @ TA = 100C - Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (Note 3.) (VDD = 50 Vdc, VGS = 10 Vdc, L = 1.0 mH, IL(pk) = 25 A, VDS = 60 Vdc, RG = 25 ) Thermal Resistance - Junction-to-Case - Junction-to-Ambient (Note 1.) - Junction-to-Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol Value Unit VDSS VDGR 60 Vdc 60 Vdc VGS VGS "20 "30 ID ID IDM PD 32 22 90 Adc 93.75 0.625 2.88 1.5 W W/C W W TJ, Tstg -55 to +175 C EAS 313 mJ Vdc C/W RJC RJA RJA 1.6 52 100 TL 260 March, 2001 - Rev. 1 1 CASE 369A DPAK (Bent Lead) STYLE 2 NTD32N06 Y WW T 2 3 CASE 369 DPAK (Straight Lead) STYLE 2 = Device Code = Year = Work Week = MOSFET MARKING DIAGRAMS & PIN ASSIGNMENTS Apk 4 Drain 4 Drain YWW NTD 32N06 YWW NTD 32N06 1 Gate 2 Drain 3 Source 1 Gate 3 Source 2 Drain ORDERING INFORMATION C 1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using minimum recommended pad size, (Cu Area 0.412 in2). 3. Repetitive rating; pulse width limited by maximum junction temperature. Semiconductor Components Industries, LLC, 2001 S 39 Device Package Shipping DPAK 75 Units/Rail NTD32N06-1 DPAK Straight Lead 75 Units/Rail NTD32N06T4 DPAK 2500 Tape & Reel NTD32N06 Publication Order Number: NTD32N06/D NTD32N06 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - 70 41.6 - - - - - - 1.0 10 - - 100 2.0 - 2.8 7.0 4.0 - - 21 26 - - - 0.417 0.680 0.633 0.62 - - gFS - 21.1 - mhos Ciss - 1231 1725 pF Coss - 346 485 Crss - 77 160 td(on) - 10 25 tr - 84 180 td(off) - 31 70 tf - 93 200 QT - 33 60 Q1 - 6.0 - Q2 - 15 - VSD - - - 0.89 0.96 0.75 1.0 - - Vdc trr - 52 - ns ta - 37 - tb - 14.3 - QRR - 0.095 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 4.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (Note 4.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (Note 4.) (VGS = 10 Vdc, ID = 16 Adc) RDS(on) Static Drain-to-Source On-Voltage (Note 4.) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 32 Adc) (VGS = 10 Vdc, ID = 16 Adc, TJ = 150C) VDS(on) Forward Transconductance (Note 4.) (VDS = 6 Vdc, ID = 16 Adc) Vdc mV/C mOhm Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) Turn-On Delay Time (VDD = 30 Vdc, ID = 32 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) (Note 4.) Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 32 Adc, Ad VGS = 10 Vdc) (Note 4.) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 4.) (IS = 32 Adc, VGS = 0 Vdc) (Note 4.) (IS = 20 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 32 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 4.) Reverse Recovery Stored Charge 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 40 C NTD32N06 60 60 VGS = 6 V 50 40 VGS = 6.5 V VGS = 7 V VGS = 5.5 V 30 VGS = 8 V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) VGS = 10 V VGS = 5 V 20 VGS = 4.5 V 10 VDS > = 10 V 50 40 30 20 TJ = 25C 10 TJ = 100C VGS = 4 V TJ = -55C 0 0 1 3 2 3 4 TJ = 100C 0.03 0.026 TJ = 25C 0.022 0.018 TJ = -55C 0.014 0 10 20 30 40 50 60 5 5.4 5.8 6.2 7 6.6 0.024 0.023 0.022 VGS = 10 V 0.021 0.02 VGS = 15 V 0.019 0.018 0 10 20 30 40 50 60 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Gate-to-Source Voltage Figure 4. On-Resistance vs. Drain Current and Gate Voltage 10000 ID = 16 A VGS = 10 V VGS = 0 V IDSS, LEAKAGE (nA) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 4.6 Figure 2. Transfer Characteristics 0.034 1.6 4.2 Figure 1. On-Region Characteristics VGS = 10 V 1.8 3.8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 0.038 0.01 3.4 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN-TO-SOURCE RESISTANCE () RDS(on), DRAIN-TO-SOURCE RESISTANCE () 0 1.4 1.2 1 TJ = 150C 1000 TJ = 125C 100 TJ = 100C 0.8 0.6 -50 -25 10 0 25 50 75 100 125 150 175 0 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage http://onsemi.com 41 60 12 3200 VGS = 0 V VDS = 0 V TJ = 25C 2800 C, CAPACITANCE (pF) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) NTD32N06 2400 2000 Crss Ciss 1600 1200 800 Coss 400 Crss 0 10 5 VGS 0 VDS 5 10 15 25 20 Q2 6 4 2 ID = 32 A TJ = 25C 0 0 4 8 12 16 20 24 28 32 Figure 7. Capacitance Variation Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge 36 32 100 IS, SOURCE CURRENT (AMPS) t, TIME (ns) Q1 Qg, TOTAL GATE CHARGE (nC) VDS = 30 V ID = 32 A VGS = 10 V tr tf td(off) td(on) 1 10 100 20 16 12 8 4 0 0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96 Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current VGS = 20 V SINGLE PULSE TC = 25C RDS(on) Limit Thermal Limit Package Limit dc 10 10 ms 1 ms 100 s 1 Mounted on 3 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating,10 s max 0.1 0.1 24 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 1 10 100 EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 100 VGS = 0 V TJ = 25C 28 RG, GATE RESISTANCE () 1000 ID, DRAIN CURRENT (AMPS) 8 VGS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 10 QT 10 Ciss 350 ID = 32 A 300 250 200 150 100 50 0 25 50 75 100 125 150 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 42 175 NTD32N06 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 10 Normalized to RJC at Steady State 1 0.1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 t, TIME (s) Figure 13. Thermal Response r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) 10 Normalized to RJA at Steady State, 1 square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board 1 0.1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 t, TIME (s) Figure 14. Thermal Response http://onsemi.com 43 10 100 1000 ! #$%& '( ! * %+% N-Channel DPAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. http://onsemi.com Features * * * * * * * 32 AMPERES 60 VOLTS RDS(on) = 28 m Smaller Package than MTB30N06VL Lower RDS(on) Lower VDS(on) Lower Total Gate Charge Lower and Tighter VSD Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge N-Channel D Typical Applications * * * * Power Supplies Converters Power Motor Controls Bridge Circuits G S MARKING DIAGRAM MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 10 M) Gate-to-Source Voltage - Continuous - Non-Repetitive (tpv10 ms) Drain Current - Continuous @ TA = 25C - Continuous @ TA = 100C - Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (Note 3.) (VDD = 50 Vdc, VGS = 5 Vdc, L = 1.0 mH, IL(pk) = 25 A, VDS = 60 Vdc, RG = 25 ) Thermal Resistance - Junction-to-Case - Junction-to-Ambient (Note 1.) - Junction-to-Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol Value Unit VDSS VDGR 60 Vdc 60 Vdc VGS VGS "15 "20 ID ID IDM PD 32 22 90 Adc 93.75 0.625 2.88 1.5 W W/C W W TJ, Tstg -55 to +175 C EAS 313 mJ Vdc Apk 1.6 52 100 TL 260 March, 2001 - Rev. 0 YWW NTD 32N06L CASE 369A DPAK STYLE 2 1 2 3 NTD32N06L Y WW T = Device Code = Year = Work Week = MOSFET PIN ASSIGNMENT 4 Drain 1 Gate C/W RJC RJA RJA 2 Drain 3 Source ORDERING INFORMATION C 1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using minimum recommended pad size, (Cu Area 0.412 in2). 3. Repetitive rating; pulse width limited by maximum junction temperature. Semiconductor Components Industries, LLC, 2001 4 44 Device Package Shipping NTD32N06L DPAK 75 Units/Rail NTD32N06L-1 DPAK 75 Units/Rail NTD32N06LT4 DPAK 2500 Tape & Reel Publication Order Number: NTD32N06L/D NTD32N06L ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - 70 62 - - - - - - 1.0 10 - - 100 1.0 - 1.7 4.8 2.0 - - 23.7 28 - - - 0.48 0.78 0.61 0.67 - - gFS - 27 - mhos Ciss - 1214 1700 pF Coss - 343 480 Crss - 87 180 td(on) - 12.8 30 tr - 221 450 td(off) - 37 80 tf - 128 260 QT - 23 50 Q1 - 4.5 - Q2 - 14 - VSD - - - 0.89 0.95 0.74 1.0 - - Vdc trr - 56 - ns ta - 31 - tb - 25 - QRR - 0.093 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 4.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (Note 4.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (Note 4.) (VGS = 5 Vdc, ID = 16 Adc) RDS(on) Static Drain-to-Source On-Resistance (Note 4.) (VGS = 5 Vdc, ID = 20 Adc) (VGS = 5 Vdc, ID = 32 Adc) (VGS = 5 Vdc, ID = 16 Adc, TJ = 150C) VDS(on) Forward Transconductance (Note 4.) (VDS = 6 Vdc, ID = 16 Adc) Vdc mV/C mOhm Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) Turn-On Delay Time (VDD = 30 Vdc, ID = 32 Adc, VGS = 5 Vdc, Vdc RG = 9.1 ) (Note 4.) Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 32 Adc, Ad VGS = 5 Vdc) (Note 4.) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 4.) (IS = 32 Adc, VGS = 0 Vdc) (Note 4.) (IS = 20 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 32 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 4.) Reverse Recovery Stored Charge 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 45 C NTD32N06L 60 60 ID, DRAIN CURRENT (AMPS) VGS = 5 V VGS = 4 V 40 VGS = 6 V 30 VGS = 3.5 V 20 VGS = 8 V VGS = 3 V 10 0 RDS(on), DRAIN-TO-SOURCE RESISTANCE () VGS = 4.5 V 50 0 1 3 2 4 20 TJ = 25C 10 TJ = 100C 2.2 TJ = -55C 2.6 3 3.4 3.8 4.2 4.6 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 0.038 0.034 TJ = 100C 0.03 TJ = 25C 0.026 0.022 TJ = -55C 0.018 0.014 0 10 20 30 40 50 60 5 0.042 VGS = 10 V 0.038 0.034 0.03 0.026 TJ = 100C 0.022 TJ = 25C 0.018 TJ = -55C 0.014 0.01 0 10 20 30 40 50 60 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Gate-to-Source Voltage Figure 4. On-Resistance vs. Drain Current and Gate Voltage 10000 1.8 VGS = 0 V ID = 16 A VGS = 5 V IDSS, LEAKAGE (nA) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 30 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VGS = 5 V 1.6 40 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.042 0.01 VDS > = 10 V 50 0 1.8 RDS(on), DRAIN-TO-SOURCE RESISTANCE () ID, DRAIN CURRENT (AMPS) VGS = 10 V 1.4 1.2 1 TJ = 150C 1000 TJ = 125C 100 TJ = 100C 0.8 0.6 -50 -25 10 0 25 50 75 100 125 150 175 0 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage http://onsemi.com 46 60 4000 3600 3200 C, CAPACITANCE (pF) VGS = 0 V VDS = 0 V TJ = 25C Ciss 2800 2400 Crss 2000 Ciss 1600 1200 800 Coss 400 Crss 0 10 5 VGS 0 VDS 5 15 10 25 20 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) NTD32N06L 4 3 2 1 ID = 32 A TJ = 25C 0 0 4 8 12 16 20 Figure 7. Capacitance Variation Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge 24 32 IS, SOURCE CURRENT (AMPS) t, TIME (ns) VGS Q2 Q1 Qg, TOTAL GATE CHARGE (nC) VDS = 30 V ID = 32 A VGS = 5 V tr tf 100 td(off) td(on) 1 10 20 16 12 8 4 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96 Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current RDS(on) Limit Thermal Limit Package Limit dc 10 ms 1 ms 100 s 1 Mounted on 3 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating,10 s max 1 10 100 EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 10 0.1 0.1 24 RG, GATE RESISTANCE () VGS = 20 V SINGLE PULSE TC = 25C 100 VGS = 0 V TJ = 25C 28 0 0.6 100 1000 ID, DRAIN CURRENT (AMPS) QT 5 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 10 6 350 ID = 32 A 300 250 200 150 100 50 0 25 50 75 100 125 150 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 47 175 NTD32N06L r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 10 Normalized to RJC at Steady State 1 0.1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 t, TIME (s) Figure 13. Thermal Response r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) 10 Normalized to RJA at Steady State, 1 square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board 1 0.1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 t, TIME (s) Figure 14. Thermal Response http://onsemi.com 48 10 100 1000 ! #$%& '( ,- ! N-Channel DPAK Features * * * * * * * Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified IDSS Specified at Elevated Temperature SO-8 Mounting Information Provided http://onsemi.com 18.5 AMPERES 30 VOLTS 10 m @ VGS = 10 V N-Channel D Applications * DC-DC Converters * Low Voltage Motor Control * Power Management in Portable and Battery Powered Products: i.e., Computers, Printers, Cellular and Cordless Telephones, and PCMCIA Cards G 4 S 4 1 2 3 12 CASE 369A DPAK (Bend Lead) STYLE 2 3 CASE 369 DPAK (Straight Lead) STYLE 2 MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain YWW T 4302 YWW T 4302 1 Gate 2 Drain 4302 Y WW T 3 Source 1 Gate = Device Code = Year = Work Week = MOSFET 3 Source 2 Drain ORDERING INFORMATION Device Package Shipping DPAK 75 Units/Rail NTD4302-1 DPAK Straight Lead 75 Units/Rail NTD4302T4 DPAK 2500 Tape & Reel NTD4302 Semiconductor Components Industries, LLC, 2001 March, 2001 - Rev. 1 49 Publication Order Number: NTD4302/D NTD4302 MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit VDSS 30 Vdc Gate-to-Source Voltage - Continuous VGS 20 Vdc Thermal Resistance - Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Pulsed Drain Current (Note 5.) RJA PD ID IDM 1.3 96 30 90 C/W Watts Amps Amps Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 100C Pulsed Drain Current (Note 5.) RJA PD ID ID IDM 25 5.0 18.5 11.5 60 C/W Watts Amps Amps Amps Thermal Resistance - Junction-to-Ambient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 100C Pulsed Drain Current (Note 5.) RJA PD ID ID IDM 67 1.87 11.3 7.1 36 C/W Watts Amps Amps Amps RJA PD ID ID IDM TJ, Tstg 120 1.04 8.4 5.3 28 C/W Watts Amps Amps Amps -55 to 150 C EAS 722 mJ 260 C Rating Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient (Note 4.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 100C Pulsed Drain Current (Note 5.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 30 Vdc, VGS = 10 Vdc, Peak IL = 17 Apk, L = 5.0 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 1. 2. 3. 4. 5. TL Mounted on Heat Sink, Steady State. Mounted on 2 square FR-4 Board (1 sq. 2 oz. Cu 0.06 thick single sided), Time 10 seconds. Mounted on 2 square FR-4 Board (1 sq. 2 oz. Cu 0.06 thick single sided), Steady State. Minimum FR-4 or G-10 PCB, Steady State. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%. http://onsemi.com 50 NTD4302 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - 25 - - - - - - 1.0 10 - - 100 1.0 - 1.9 -3.8 3.0 - - - - 0.0078 0.0078 0.010 0.010 0.010 0.013 gFS - 20 - Mhos Ciss - 2050 2400 pF Coss - 640 800 Crss - 225 310 td(on) tr - 11 20 - 15 25 td(off) tf - 85 130 - 55 90 td(on) tr - 11 20 - 13 20 td(off) tf - 55 90 - 40 75 td(on) tr - 15 - - 25 - td(off) tf - 40 - - 58 - QT - 55 80 Qgs (Q1) Qgd (Q2) - 5.5 - - 15 - - - - 0.75 0.88 0.65 1.0 - - trr ta - 39 65 - 20 - tb Qrr - 19 - - 0.043 - OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 A) Positive Temperature Coefficient V(BR)DSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 30 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = 30 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) Vdc Adc IDSS IGSS mV/C nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Negative Temperature Coefficient VGS(th) Static Drain-Source On-State Resistance (VGS = 10 Vdc, ID = 18.5 Adc) (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) RDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 1 0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 7.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 10 Vdc, Vdc RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 10 Vdc, Vdc RG = 2.5 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 24 Vdc, ID = 18.5 Adc, VGS = 10 Vdc, Vdc RG = 2.5 ) Fall Time Gate Charge g (VDS = 24 Vd Vdc, ID = 2.0 2 0 Ad Adc, VGS = 10 Vdc) ns ns ns nC BODY-DRAIN DIODE RATINGS (Note 6.) Diode Forward On-Voltage (IS = 2.3 Adc, VGS = 0 Vdc) (IS = 18.5 Adc, VGS = 0 Vdc) (IS = 2.3 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery y Time (IS = 2.3 2 3 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 6. Indicates Pulse Test: Pulse Width = 300 sec max, Duty Cycle 2%. 7. Switching characteristics are independent of operating junction temperature. http://onsemi.com 51 VSD Vdc ns C NTD4302 40 60 TJ = 25C VGS = 4 V VDS > = 10 V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 50 VGS = 3.8 V VGS = 4.4 V VGS = 4.6 V 30 VGS = 5 V 20 VGS = 7 V VGS = 3.4 V VGS = 10 V VGS = 3.2 V 10 VGS = 3.0 V VGS = 2.8 V 0 1 0.5 1.5 2 2.5 40 30 TJ = 25C 20 TJ = 100C TJ = -55C 10 0 3 2 4 3 5 6 VDS, DRAIN-TO-SOURCE VOLTAGE (V) VGS, GATE-TO-SOURCE VOLTAGE (V) Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 0.1 RDS(on), DRAIN-TO-SOURCE RESISTANCE () RDS(on), DRAIN-TO-SOURCE RESISTANCE () 0 50 0.015 ID = 10 A TJ = 25C 0.075 0.05 TJ = 25C VGS = 4.5 V 0.01 VGS = 10 V 0.005 0.025 0 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 0 2 4 6 8 10 1.00E+01 2.00E+01 3.00E+01 4.00E+01 5.00E+01 6.00E+01 VGS, GATE-TO-SOURCE VOLTAGE (V) ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Gate-To-Source Voltage Figure 4. On-Resistance vs. Drain Current and Gate Voltage 1.6 10000 ID = 18.5 A VGS = 10 V VGS = 0 V TJ = 150C 1.4 IDSS, LEAKAGE (nA) 1000 1.2 1 0.8 0.6 -50 0 0.00E+00 100 TJ = 100C 10 1 -25 0 25 50 75 100 125 150 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current vs. Voltage http://onsemi.com 52 30 60 VGS = 0 V TJ = 25C C, CAPACITANCE (pF) 50 Ciss 40 30 30 12.5 VDS = 0 V Crss Ciss 20 10 Coss Crss 0 10 VGS 0 VDS 10 20 QT 10 20 7.5 VGS 5 15 Q2 Q1 10 2.5 30 0 ID = 2 A TJ = 25C 0 20 10 30 40 50 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge 1000 25 IS, SOURCE CURRENT (AMPS) VDD = 24 V ID = 18.5 A VGS = 10 V t, TIME (ns) 25 VD 100 tf td(off) tr td(on) 10 1 10 VGS = 0 V TJ = 25C 20 15 10 5 0 0.5 100 0 60 0.6 0.7 0.8 0.9 RG, GATE RESISTANCE () VSD, SOURCE-TO-DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current http://onsemi.com 53 VDS, DRAIN-TO-SOURCE- VOLTAGE (V) VGS, GATE-TO-SOURCE- VOLTAGE (V) NTD4302 1 NTD4302 m! %&' ! " " #$ '(( ') ! '+ #$ '* Figure 12. Diode Reverse Recovery Waveform Figure 11. Maximum Rated Forward Biased Safe Operating Area '23)'.. . - - " $ # $ # *0 ' '# - - " '&'# $ 6 4 # ' !1! 5 Figure 13. Thermal Response - Various Duty Cycles http://onsemi.com 54 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5# 54 NTD4302 INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection 9$ 67 interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. #$6 8 4 94 9 7 68#9 #64 9:# inches mm SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 14 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CC CCC CCCCCC CCC CC CC CCC CCC CCC CCC CCC Figure 14. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 55 NTD4302 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 15. Typical Solder Heating Profile http://onsemi.com 56 !!! '( !-! P-Channel TSOP-6 Features http://onsemi.com * Ultra Low RDS(on) * Higher Efficiency Extending Battery Life * Miniature TSOP-6 Surface Mount Package -3.3 AMPERES -12 VOLTS 75 m @ VGS = -4.5 V Applications * Power Management in Portable and Battery-Powered Products, i.e.: Cellular and Cordless Telephones, and PCMCIA Cards P-Channel MAXIMUM RATINGS (TJ = 25C unless otherwise noted.) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Thermal Resistance Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (Tp t 10 S) Maximum Operating Power Dissipation Maximum Operating Drain Current Thermal Resistance Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (Tp t 10 S) Maximum Operating Power Dissipation Maximum Operating Drain Current Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes for 10 Seconds 1 2 5 6 Symbol Value Unit VDSS VGS -12 Volts "8.0 Volts 62.5 2.0 -3.3 C/W Watts Amps ID IDM Pd ID -20 1.0 -2.35 Amps Watts Amps RJA Pd 128 1.0 C/W Watts ID IDM Pd ID TJ, Tstg -2.35 -14 0.5 -1.65 Amps Amps Watts Amps -55 to 150 C 260 C RJA Pd TL DRAIN 3 GATE 4 SOURCE MARKING DIAGRAM 3 4 5 2 1 433 x TSOP-6 CASE 318G STYLE 1 6 433 x = Device Code = Date Code PIN ASSIGNMENT 1. Mounted onto a 2 square FR-4 board (1 sq. 2 oz. cu. 0.06 thick single sided), t t 5.0 seconds. 2. Mounted onto a 2 square FR-4 board (1 sq. 2 oz. cu. 0.06 thick single sided), operating to steady state. Drain Drain ;(1 6 5 4 1 2 3 Drain Drain Gate ORDERING INFORMATION Device NTGS3433T1 Package Shipping TSOP-6 3000 Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 0 57 Publication Order Number: NTGS3433T1/D NTGS3433T1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Notes 3. & 4.) Characteristic Symbol Min Typ Max -12 - - - - - - -1.0 -5.0 - - -100 - - 100 -0.50 -0.70 -1.50 - - 0.055 0.075 0.075 0.095 - 7.0 - Qtot - 7.0 15 Qgs - 2.0 - Qgd - 3.5 - Ciss - 550 - Coss - 450 - Crss - 200 - td(on) - 20 30 Unit OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = -10 A) V(BR)DSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = -8 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = -8 Vdc, TJ = 70C) IDSS Gate-Body Leakage Current (VGS = -8.0 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +8.0 Vdc, VDS = 0 Vdc) IGSS Vdc Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) VGS(th) Static Drain-Source On-State Resistance (VGS = -4.5 Vdc, ID = -3.3 Adc) (VGS = -2.5 Vdc, ID = -2.9 Adc) RDS(on) Forward Transconductance (VDS = -10 Vdc, ID = -3.3 Adc) Vdc W gFS mhos DYNAMIC CHARACTERISTICS Total Gate Charge Gate-Source Charge (VDS = -10 10 Vdc, Vd VGS = -4.5 4 5 Vdc, Vd ID = -3.3 Adc) Gate-Drain Charge Input Capacitance Output Capacitance (VDS = -5.0 5 0 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Reverse Transfer Capacitance nC pF SWITCHING CHARACTERISTICS Turn-On Delay Time Rise Time ns (VDD = -10 10 Vdc, ID = -1.0 1.0 Adc, VGS = -4.5 Vdc, Rg = 6.0 W) tr - 20 30 td(off) - 110 120 tf - 100 115 (IS = -1.7 Adc, dlS/dt = 100 A/s) trr - 30 - ns (IS = -1.7 Adc, VGS = 0 Vdc) VSD - -0.80 -1.5 Vdc Diode Forward On-Voltage (IS = -3.3 Adc, VGS = 0 Vdc) VSD - 3. Indicates Pulse Test: P.W. = 300 sec max, Duty Cycle = 2%. 4. Class 1 ESD rated - Handling precautions to protect against electrostatic discharge is mandatory. -0.90 - Vdc Turn-Off Delay Time Fall Time Reverse Recovery Time BODY-DRAIN DIODE RATINGS Diode Forward On-Voltage http://onsemi.com 58 NTGS3433T1 20 VGS = -2.5 V VGS = -5 V 10 -ID, DRAIN CURRENT (AMPS) -ID, DRAIN CURRENT (AMPS) 12 VGS = -3 V VGS = -3.5 V VGS = -4 V VGS = -4.5 V 8 6 VGS = -2 V 4 TJ = 25C 2 VGS = -1.5 V 0 0 0.25 0.5 0.75 1.25 1 1.5 VDS -10 V 18 TJ = -55C 16 14 TJ = 25C 12 10 TJ = 125C 8 6 4 2 0 0.5 1.75 1 RDS(on), DRAIN-TO-SOURCE RESISTANCE () 0.4 ID = -3.3 A TJ = 25C 0.3 0.25 0.2 0.15 0.1 0.05 0 2 4 6 8 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 4 3.5 TJ = 25C 0.25 0.2 VGS = -2.5 V 0.15 0.1 VGS = -4.5 V 0.05 0 0 2 4 6 8 10 12 14 16 18 20 -ID, DRAIN CURRENT (AMPS) Figure 4. On-Resistance vs. Drain Current and Gate Voltage 1200 1.6 ID = -3.3 A VGS = -4.5 V 1 0.8 800 600 Ciss 400 Coss 200 Crss 0 -25 0 VGS = 0 V TJ = 25C 1000 1.2 0.6 -50 3 0.3 Figure 3. On-Resistance vs. Gate-to-Source Voltage 1.4 2.5 Figure 2. Transfer Characteristics C, CAPACITANCE (pF) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN-TO-SOURCE RESISTANCE () Figure 1. On-Region Characteristics 0 2 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.35 1.5 25 50 75 100 125 150 0 2.5 5 7.5 10 12.5 15 17.5 TJ, JUNCTION TEMPERATURE (C) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Capacitance Variation http://onsemi.com 59 20 6 10 5 -IS, SOURCE CURRENT (AMPS) -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) NTGS3433T1 QT 4 3 Qgs Qgd 2 TJ = 25C ID = -3.3 A 1 0 0 2 4 8 6 8 7 TJ = 150C 6 5 4 TJ = 25C 3 2 1 0 10 VGS = 0 V 9 0 Figure 7. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge 0.4 0.6 0.8 1 1.2 Figure 8. Diode Forward Voltage vs. Current 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.1 1E-04 Single Pulse 1E-03 1E-02 1E-01 1E+00 1E+01 SQUARE WAVE PULSE DURATION (sec) Figure 9. Normalized Thermal Transient Impedance, Junction-to-Ambient 20 16 POWER (W) NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE 0.2 -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Qg, TOTAL GATE CHARGE (nC) 12 8 4 0 0.01 0.10 1.00 10.00 TIME (sec) Figure 10. Single Pulse Power http://onsemi.com 60 100.00 1E+02 1E+03 ! #$%& '( P-Channel TSOP-6 Features * Ultra Low RDS(on) * Higher Efficiency Extending Battery Life * Miniature TSOP-6 Surface Mount Package http://onsemi.com 1 AMPERE 20 VOLTS RDS(on) = 90 m Applications * Power Management in Portable and Battery-Powered Products, i.e.: Cellular and Cordless Telephones, and PCMCIA Cards MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Thermal Resistance Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (Tp t 10 S) Thermal Resistance Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (Tp t 10 S) Thermal Resistance Junction-to-Ambient (Note 3.) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (Tp t 10 S) Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes for 10 Seconds P-Channel Symbol Value Unit VDSS VGS -20 Volts "8.0 Volts RJA Pd ID IDM 244 0.5 -1.65 -10 C/W Watts Amps Amps RJA Pd ID IDM 128 1.0 -2.35 -14 C/W Watts Amps Amps RJA Pd ID IDM TJ, Tstg 62.5 2.0 -3.3 -20 C/W Watts Amps Amps -55 to 150 C 260 C TL 1. Minimum FR-4 or G-10PCB, operating to steady state. 2. Mounted onto a 2 square FR-4 board (1 sq. 2 oz. cu. 0.06 thick single sided), operating to steady state. 3. Mounted onto a 2 square FR-4 board (1 sq. 2 oz. cu. 0.06 thick single sided), t t 5.0 seconds. # $ 9 4 6 MARKING DIAGRAM 3 4 5 2 1 441 W TSOP-6 CASE 318G STYLE 1 6 441 W = Device Code = Work Week PIN ASSIGNMENT ()% ()% ;(1 6 5 4 1 2 3 ()% ()% )'1 ORDERING INFORMATION Device NTGS3441T1 Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 61 Package Shipping TSOP-6 3000 Tape & Reel Publication Order Number: NTGS3441T1/D NTGS3441T1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Notes 4. & 5.) Characteristic Symbol Min Typ Max -20 - - - - - - -1.0 -5.0 - - -100 - - 100 -0.45 -1.05 -1.50 - - 0.069 0.117 0.090 0.135 - 6.8 - Unit OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = -10 A) V(BR)DSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = -20 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = -20 Vdc, TJ = 70C) IDSS Gate-Body Leakage Current (VGS = -8.0 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +8.0 Vdc, VDS = 0 Vdc) IGSS Vdc Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) VGS(th) Static Drain-Source On-State Resistance (VGS = -4.5 Vdc, ID = -3.3 Adc) (VGS = -2.5 Vdc, ID = -2.9 Adc) RDS(on) Forward Transconductance (VDS = -10 Vdc, ID = -3.3 Adc) Vdc W gFS mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = -5.0 5 0 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Reverse Transfer Capacitance Ciss - 480 - pF Coss - 265 - pF Crss - 100 - pF td(on) - 13 25 ns tr - 23.5 45 ns td(off) - 27 50 ns tf - 24 45 ns Qtot - 6.2 14 nC Qgs - 1.3 - nC Qgd - 2.5 - nC SWITCHING CHARACTERISTICS Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = -20 20 Vdc, ID = -1.6 1.6 Adc, VGS = -4.5 Vdc, Rg = 6.0 W) Fall Time Total Gate Charge Gate-Source Charge (VDS = -10 10 Vdc, Vd VGS = -4.5 4 5 Vdc, Vd ID = -3.3 Adc) Gate-Drain Charge BODY-DRAIN DIODE RATINGS Diode Forward On-Voltage (IS = -1.6 Adc, VGS = 0 Vdc) VSD - -0.88 -1.2 Vdc Diode Forward On-Voltage (IS = -3.3 Adc, VGS = 0 Vdc) VSD - -0.98 - Vdc trr - 30 60 ns Reverse Recovery Time (IS = -1.6 Adc, dIS/dt = 100 A/s) 4. Indicates Pulse Test: P.W. = 300 sec max, Duty Cycle = 2%. 5. Handling precautions to protect against electrostatic discharge is mandatory. http://onsemi.com 62 NTGS3441T1 TYPICAL ELECTRICAL CHARACTERISTICS TJ = 25C 20 VGS = -2.7 V 8 -ID, DRAIN CURRENT (AMPS) -ID, DRAIN CURRENT (AMPS) 10 VGS = -2.5 V 6 VGS = -3 V VGS = -3.5 V VGS = -4 V VGS = -4.5 V VGS = -6 V VGS = -2 V 4 2 VGS = -10 V VGS = -1.5 V 0.8 0.4 1.2 1.6 2 TJ = -55C 12 TJ = 100C 8 4 2 2.4 2.8 3.2 3.6 0.2 0.1 2 4 3 5 7 6 8 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 3. On-Resistance vs. Gate-to-Source Voltage RDS(on), DRAIN-TO-SOURCE RESISTANCE () Figure 2. Transfer Characteristics 0 4 0.28 TJ = 25C 0.24 VGS = -2.5 V 0.2 0.16 0.12 VGS = -4.5 V 0.08 0.04 0 0 4 8 12 16 20 -ID, DRAIN CURRENT (AMPS) Figure 4. On-Resistance vs. Drain Current and Gate Voltage 100 VGS = 0 V ID = -3.3 A VGS = -4.5 V TJ = 125C -IDSS, LEAKAGE (nA) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.6 Figure 1. On-Region Characteristics 0.3 1.2 1 0.8 0.6 -50 1.2 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) ID = -3.3 A TJ = 25C 1.4 0.8 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.4 RDS(on), DRAIN-TO-SOURCE RESISTANCE () TJ = 25C 16 0 0.4 0 0 VDS> = -10 V 10 TJ = 100C 1 TJ = 25C 0.1 -25 0 25 50 75 100 125 150 0 4 8 12 16 TJ, JUNCTION TEMPERATURE (C) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage http://onsemi.com 63 20 NTGS3441T1 TYPICAL ELECTRICAL CHARACTERISTICS VDS = 0 V VGS = 0 V TJ = 25C -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 1200 C, CAPACITANCE (pF) Ciss 900 Crss 600 Ciss 300 Coss Crss 0 8 4 -VGS 0 4 8 12 16 20 8 6 QT 4 Qgs VDD = -20 V ID = -3.3 A TJ = 25C 2 0 0 4 6 8 Qg, TOTAL GATE CHARGE (nC) Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge Figure 7. Capacitance Variation 10 1.3 -IS, SOURCE CURRENT (AMPS) VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED) 2 -VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) ID = -250 A 1.2 1.1 1 0.9 0.8 0.7 0.6 -50 Qgd -25 0 25 50 75 100 125 150 VGS = 0 V TJ = 25C 8 6 4 2 0 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 TJ, JUNCTION TEMPERATURE (C) -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 9. Gate Threshold Voltage Variation with Temperature Figure 10. Diode Forward Voltage vs. Current http://onsemi.com 64 1.4 NTGS3441T1 TYPICAL ELECTRICAL CHARACTERISTICS 20 POWER (W) 16 12 8 4 0 0.01 0.10 1.00 10.00 100.00 TIME (sec) NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE Figure 11. Single Pulse Power 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 1E-04 Single Pulse 1E-03 1E-02 1E-01 1E+00 1E+01 1E+02 SQUARE WAVE PULSE DURATION (sec) Figure 12. Normalized Thermal Transient Impedance, Junction-to-Ambient http://onsemi.com 65 1E+03 NTGS3441T1 INFORMATION FOR USING THE TSOP-6 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 76 #6 4: 7$ :6 7 4: 7$ #8 : 47 %21! SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 66 !! #$%& '( P-Channel TSOP-6 Features * Ultra Low RDS(on) * Higher Efficiency Extending Battery Life * Miniature TSOP6 Surface Mount Package http://onsemi.com 2 AMPERES 20 VOLTS RDS(on) = 65 m Applications * Power Management in Portable and Battery-Powered Products, i.e.: Cellular and Cordless Telephones, and PCMCIA Cards MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Thermal Resistance Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (Tp t 10 S) Thermal Resistance Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (Tp t 10 S) Thermal Resistance Junction-to-Ambient (Note 3.) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (Tp t 10 S) Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes for 10 Seconds P-Channel Symbol Value Unit VDSS VGS -20 Volts "12 Volts RJA Pd ID IDM 244 0.5 -2.2 -10 C/W Watts Amps Amps RJA Pd ID IDM 128 1.0 -3.1 -14 C/W Watts Amps Amps RJA Pd ID IDM TJ, Tstg 62.5 2.0 -4.4 -20 C/W Watts Amps Amps -55 to 150 C 260 C TL # $ 9 4 6 MARKING DIAGRAM 3 4 5 2 1 443 W TSOP-6 CASE 318G STYLE 1 6 443 W 1. Minimum FR-4 or G-10PCB, operating to steady state. 2. Mounted onto a 2 square FR-4 board (1 sq. 2 oz. cu. 0.06 thick single sided), operating to steady state. 3. Mounted onto a 2 square FR-4 board (1 sq. 2 oz. cu. 0.06 thick single sided), t t 5.0 seconds. = Device Code = Work Week PIN ASSIGNMENT ()% ()% ;(1 6 5 4 1 2 3 ()% ()% )'1 ORDERING INFORMATION Device NTGS3443T1 Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 67 Package Shipping TSOP-6 3000 Tape & Reel Publication Order Number: NTGS3443T1/D NTGS3443T1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Notes 4. & 5.) Characteristic Symbol Min Typ Max Unit -20 - - - - - - -1.0 -5.0 - - -100 - - 100 -0.60 -0.95 -1.50 - - - 0.058 0.082 0.092 0.065 0.090 0.100 - 8.8 - Ciss - 565 - pF Coss - 320 - pF Crss - 120 - pF td(on) - 10 25 ns tr - 18 45 ns td(off) - 30 50 ns OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = -10 A) V(BR)DSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = -20 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = -20 Vdc, TJ = 70C) IDSS Gate-Body Leakage Current (VGS = -12 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +12 Vdc, VDS = 0 Vdc) IGSS Vdc Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) VGS(th) Static Drain-Source On-State Resistance (VGS = -4.5 Vdc, ID = -4.4 Adc) (VGS = -2.7 Vdc, ID = -3.7 Adc) (VGS = -2.5 Vdc, ID = -3.5 Adc) RDS(on) Forward Transconductance (VDS = -10 Vdc, ID = -4.4 Adc) Vdc W gFS mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = -5.0 5 0 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = -20 20 Vdc, ID = -1.0 1.0 Adc, VGS = -4.5 Vdc, Rg = 6.0 W) Fall Time Total Gate Charge Gate-Source Charge (VDS = -10 10 Vdc, Vd VGS = -4.5 4 5 Vdc, Vd ID = -4.4 Adc) Gate-Drain Charge tf - 31 50 ns Qtot - 7.5 15 nC Qgs - 1.4 - nC Qgd - 2.9 - nC VSD - -0.83 -1.2 Vdc trr - 30 - ns BODY-DRAIN DIODE RATINGS Diode Forward On-Voltage (IS = -1.7 Adc, VGS = 0 Vdc) Reverse Recovery Time (IS = -1.7 Adc, dIS/dt = 100 A/s) 4. Indicates Pulse Test: P.W. = 300 sec max, Duty Cycle = 2%. 5. Handling precautions to protect against electrostatic discharge is mandatory. http://onsemi.com 68 NTGS3443T1 TYPICAL ELECTRICAL CHARACTERISTICS 8 8 VGS = -2.5 V -ID, DRAIN CURRENT (AMPS) -ID, DRAIN CURRENT (AMPS) VGS = -5 V TJ = 25C VGS = -3 V VGS = -4.5 V VGS = -4 V VGS = -3.5 V VGS = -2 V 6 4 2 VGS = -1.5 V 0 0.4 0 0.8 1.2 1.6 VDS = -10 V 6 4 TJ = 25C 2 TJ = 125C 0 0.6 2 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1 RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.3 0.25 0.2 0.15 0.1 0.05 2.5 3 3.5 4 4.5 5 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 0.14 VGS = -2.5 V 0.12 VGS = -2.7 V 0.1 0.08 VGS = -4.5 V 0.06 0.04 0 1 2 3 4 5 6 7 8 -ID, DRAIN CURRENT (AMPS) Figure 4. On-Resistance vs. Drain Current and Gate Voltage 100 1.5 TJ = 125C ID = -4.4 A VGS = -4.5 V 1.3 1.2 1.1 1 0.9 TJ = 100C 10 1 TJ = 25C 0.1 0.8 0.7 -50 3 TJ = 25C Figure 3. On-Resistance vs. Gate-to-Source Voltage 1.4 2.6 0.16 -IDSS, LEAKAGE (nA) RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) ID = -4.4 A TJ = 25C 2 2.2 Figure 2. Transfer Characteristics 0.4 0 1.5 1.8 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 1. On-Region Characteristics 0.35 1.4 TJ = -55C VGS = 0 V 0.01 -25 0 25 50 75 100 125 150 0 4 8 12 16 TJ, JUNCTION TEMPERATURE (C) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage http://onsemi.com 69 20 NTGS3443T1 TYPICAL ELECTRICAL CHARACTERISTICS 5 1200 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 1000 C, CAPACITANCE (pF) QT TJ = 25C VGS = 0 V 800 600 Ciss 400 Coss 200 VGS 4 3 Q1 Q2 2 1 TJ = 25C ID = -4.4 A Crss 2 0 4 6 8 10 12 14 16 18 0 20 0 1 2 3 4 5 6 7 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge 1.3 ID = -250 A 1.2 1.1 1 0.9 0.8 0.7 0.6 -50 8 4 -IS, SOURCE CURRENT (AMPS) VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED) 0 -25 0 25 50 75 100 125 150 VGS = 0 V 3 TJ = 150C 2 TJ = 25C 1 0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 TJ, JUNCTION TEMPERATURE (C) -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 9. Gate Threshold Voltage Variation with Temperature Figure 10. Diode Forward Voltage vs. Current http://onsemi.com 70 1 NTGS3443T1 TYPICAL ELECTRICAL CHARACTERISTICS 20 POWER (W) 16 12 8 4 0 0.01 0.10 1.00 10.00 100.00 TIME (sec) NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE Figure 11. Single Pulse Power 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 1E-04 Single Pulse 1E-03 1E-02 1E-01 1E+00 1E+01 1E+02 SQUARE WAVE PULSE DURATION (sec) Figure 12. Normalized Thermal Transient Impedance, Junction-to-Ambient http://onsemi.com 71 1E+03 NTGS3443T1 INFORMATION FOR USING THE TSOP-6 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 76 #6 4: 7$ :6 7 4: 7$ #8 : 47 %21! SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 72 ! #$%& '( -! N-Channel TSOP-6 Features * * * * * * Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified IDSS Specified at Elevated Temperature http://onsemi.com 5.3 AMPERES 20 VOLTS RDS(on) = 45 m Applications * Power Management in portable and battery-powered products, i.e. * * N-Channel computers, printers, PCMCIA cards, cellular and cordless Lithium Ion Battery Applications Notebook PC Drain 1 2 5 6 MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-Source Voltage - Continuous Thermal Resistance Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (tp t 10 s) Thermal Resistance Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (tp t 10 s) Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes for 10 seconds Symbol Value Unit VDSS VGS 20 Vdc 12 Vdc RJA Pd 62.5 2.0 C/W Watts ID IDM 5.3 25 Amps Amps RJA Pd 128 1.0 C/W Watts ID IDM TJ, Tstg 3.7 20 Amps Amps -55 to 150 C 260 C TL Gate 3 Source 4 MARKING DIAGRAM 3 4 5 2 1 446 W TSOP-6 CASE 318G STYLE 1 6 446 W = Device Code = Work Week PIN ASSIGNMENT Drain Drain Source 6 5 4 1. Mounted onto a 2 square FR-4 board (1 sq. 2 oz. cu. 0.06 thick single sided), t t 5.0 seconds. 2. Mounted onto a 2 square FR-4 board (1 sq. 2 oz. cu. 0.06 thick single sided), operating to steady state. 1 2 3 Drain Drain Gate ORDERING INFORMATION Device NTGS3446T1 Semiconductor Components Industries, LLC, 2001 March, 2001 - Rev. 2 73 Package TSOP-6 Shipping 3000 Tape & Reel Publication Order Number: NTGS3446/D NTGS3446T1 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 20 - - 22 - - - - - - 1.0 25 - - - - 100 -100 0.6 - 0.85 -2.5 1.2 - - - 36 44 45 55 gFS - 12 - mhos Ciss - 510 750 pF Coss - 200 350 Crss - 60 100 td(on) - 9.0 16 tr - 12 20 td(off) - 35 60 tf - 20 35 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Collector Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 85C) Vdc Adc IDSS Gate-Body Leakage Current (VGS = 12 Vdc, VDS = 0) IGSS(f) IGSS(r) mV/C nAdc ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage ID = 0.25 mA, VDS = VGS Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 5.3 Adc) (VGS = 2.5 Vdc, ID = 4.4 Adc) RDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 5.3 Adc) Vdc mV/C mW DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 1.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) Fall Time Gate Charge (VDS = 10 Vd Vdc, ID = 5.3 5 3 Ad Adc, VGS = 4.5 Vdc) QT - 8.0 15 Qgs - 2.0 - Qgd - 2.0 - - - 0.74 0.66 1.1 - trr - 20 - ta - 11 - tb - 9.0 - QRR - 0.01 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 3.) VSD (IS = 1.7 Adc, VGS = 0 Vdc) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 85C) Reverse Recovery Time (IS = 1.7 1 7 Adc, Adc VGS = 0 Vdc, Vdc diS/dt = 100 A/s) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperature. http://onsemi.com 74 Vdc ns C 1.8 1.6 100 ID = 5.3 A VGS = 4.5 V tf td(off) 1.4 t, TIME (ns) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) NTGS3446T1 1.2 1 tr 10 td(on) 0.8 VDD = 10 V ID = 1.0 A VGS = 4.5 V 0.6 0.4 -50 -25 0 25 50 75 100 125 150 1 1 10 TJ, JUNCTION TEMPERATURE (C) RG, GATE RESISTANCE () Figure 1. On-Resistance Variation with Temperature Figure 2. Resistive Switching Time Variation vs. Gate Resistance http://onsemi.com 75 100 ! '( !- ! P-Channel TSOP-6 Features http://onsemi.com * Ultra Low RDS(on) * Higher Efficiency Extending Battery Life * Miniature TSOP-6 Surface Mount Package -3.5 AMPERES -30 VOLTS 100 m @ VGS = -10 V Applications * Power Management in Portable and Battery-Powered Products, i.e.: Cellular and Cordless Telephones, and PCMCIA Cards P-Channel MAXIMUM RATINGS (TJ = 25C unless otherwise noted.) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Thermal Resistance Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (Tp t 10 S) Maximum Operating Power Dissipation Maximum Operating Drain Current Thermal Resistance Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (Tp t 10 S) Maximum Operating Power Dissipation Maximum Operating Drain Current Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes for 10 Seconds 1 2 5 6 Symbol Value Unit VDSS VGS -30 Volts "20.0 Volts 62.5 2.0 -3.5 C/W Watts Amps ID IDM Pd ID -20 1.0 -2.5 Amps Watts Amps RJA Pd 128 1.0 C/W Watts ID IDM Pd ID TJ, Tstg -2.5 -14 0.5 -1.75 Amps Amps Watts Amps -55 to 150 C 260 C RJA Pd TL DRAIN 3 GATE 4 SOURCE MARKING DIAGRAM 3 4 5 2 1 TSOP-6 CASE 318G STYLE 1 455 x 6 455 x = Device Code = Date Code PIN ASSIGNMENT 1. Mounted onto a 2 square FR-4 board (1 sq. 2 oz. cu. 0.06 thick single sided), t t 5.0 seconds. 2. Mounted onto a 2 square FR-4 board (1 sq. 2 oz. cu. 0.06 thick single sided), operating to steady state. Drain Drain ;(1 6 5 4 1 2 3 Drain Drain Gate ORDERING INFORMATION Device NTGS3455T1 Package Shipping TSOP-6 3000 Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 0 76 Publication Order Number: NTGS3455T1/D NTGS3455T1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Notes 3. & 4.) Characteristic Symbol Min Typ Max -30 - - - - - - -1.0 -5.0 - - -100 - - 100 -1.0 -1.87 -3.0 - - 0.094 0.144 0.100 0.170 - 6.0 - Qtot - 9.0 13 Qgs - 2.5 - Qgd - 2.0 - Ciss - 480 - Coss - 220 - Crss - 60 - td(on) - 10 20 Unit OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = -10 A) V(BR)DSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = -30 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = -30 Vdc, TJ = 70C) IDSS Gate-Body Leakage Current (VGS = -20.0 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +20.0 Vdc, VDS = 0 Vdc) IGSS Vdc Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) VGS(th) Static Drain-Source On-State Resistance (VGS = -10 Vdc, ID = -3.5 Adc) (VGS = -4.5 Vdc, ID = -2.7 Adc) RDS(on) Forward Transconductance (VDS = -15 Vdc, ID = -3.5 Adc) Vdc W gFS mhos DYNAMIC CHARACTERISTICS Total Gate Charge Gate-Source Charge (VDS = -15 15 Vdc, Vd VGS = -10 10 Vdc, Vd ID = -3.5 Adc) Gate-Drain Charge Input Capacitance Output Capacitance (VDS = -5.0 5 0 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Reverse Transfer Capacitance nC pF SWITCHING CHARACTERISTICS Turn-On Delay Time Rise Time ns (VDD = -20 20 Vdc, ID = -1.0 1.0 Adc, VGS = -10 Vdc, Rg = 6.0 W) tr - 15 30 td(off) - 20 35 tf - 10 20 (IS = -1.7 Adc, dlS/dt = 100 A/s) trr - 30 - ns (IS = -1.7 Adc, VGS = 0 Vdc) VSD - -0.90 -1.2 Vdc Diode Forward On-Voltage (IS = -3.5 Adc, VGS = 0 Vdc) VSD - 3. Indicates Pulse Test: P.W. = 300 sec max, Duty Cycle = 2%. 4. Class 1 ESD rated - Handling precautions to protect against electrostatic discharge is mandatory. -1.0 - Vdc Turn-Off Delay Time Fall Time Reverse Recovery Time BODY-DRAIN DIODE RATINGS Diode Forward On-Voltage http://onsemi.com 77 NTGS3455T1 20 VGS = -10 V VGS = -9 V 16 -ID, DRAIN CURRENT (AMPS) -ID, DRAIN CURRENT (AMPS) 20 VGS = -6 V VGS = -8 V VGS = -7 V 12 VGS = -5 V 8 VGS = -4 V 4 TJ = 25C VGS = -3 V 0 0 0.5 1 1.5 2 2.5 3 3.5 18 16 14 TJ = 25C 12 TJ = 125C 10 8 6 4 2 0 4 TJ = -55C 0 1 RDS(on), DRAIN-TO-SOURCE RESISTANCE () 0.3 ID = -3.5 A TJ = 25C 0.2 0.15 0.1 0.05 2 3 4 5 6 7 8 9 10 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 7 6 TJ = 25C 0.25 0.2 VGS = -4.5 V 0.15 VGS = -10 V 0.1 0.05 0 0 2 4 6 8 10 12 16 14 18 20 -ID, DRAIN CURRENT (AMPS) Figure 4. On-Resistance vs. Drain Current and Gate Voltage 700 1.6 ID = -3.5 A VGS = -10 V VGS = 0 V TJ = 25C 1.2 1 0.8 0.6 -50 5 0.3 Figure 3. On-Resistance vs. Gate-to-Source Voltage 1.4 4 Figure 2. Transfer Characteristics C, CAPACITANCE (pF) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN-TO-SOURCE RESISTANCE () Figure 1. On-Region Characteristics 0 3 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.25 2 500 Ciss 300 Coss 100 Crss -100 -25 0 25 50 75 100 125 150 0 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (C) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Capacitance Variation http://onsemi.com 78 30 NTGS3455T1 10 11 -IS, SOURCE CURRENT (AMPS) -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 9 8 7 6 Qgs 5 4 Qgd 3 TJ = 25C ID = -3.5 A 2 1 0 0 2 4 8 6 10 VGS = 0 V 8 4 TJ = 25C 2 0 12 TJ = 150C 6 0 Figure 7. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge 0.4 0.6 0.8 1 1.4 1.2 Figure 8. Diode Forward Voltage vs. Current 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.1 1E-04 Single Pulse 1E-03 1E-02 1E-01 1E+00 1E+01 SQUARE WAVE PULSE DURATION (sec) Figure 9. Normalized Thermal Transient Impedance, Junction-to-Ambient 20 16 POWER (W) NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE 0.2 -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Qg, TOTAL GATE CHARGE (nC) 12 8 4 0 0.01 0.10 1.00 10.00 TIME (sec) Figure 10. Single Pulse Power http://onsemi.com 79 100.00 1E+02 1E+03 .) /0 10% ! 23 '( http://onsemi.com D1 D2 G1 G2 PRODUCT SUMMARY S1 VDS (V) 30 rDS(on) () ID (A) 0.085 @ VGS = 10 V "3.9 0.143 @ VGS = 4.5 V "3.0 S2 N-Channel MOSFET N-Channel MOSFET MAXIMUM RATINGS (TA = 25C unless otherwise noted) Rating Symbol Steady State 5 secs Unit Drain-Source Voltage VDS 30 V Gate-Source Voltage VGS "20 V Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current ID PIN CONNECTIONS Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C PD 1.8 A 0.9 A W 2.1 1.1 TJ, Tstg "2.9 "2.1 "10 IDM IS Operating Junction and Storage Temperature Range A "3.9 "2.8 Continuous Source Current (Diode Conduction) (Note 1.) ChipFET CASE 1206A STYLE 2 D1 8 1 S1 D1 7 2 G1 D2 6 3 S2 D2 5 4 G2 1.1 0.6 MARKING DIAGRAM C -55 to +150 1. Surface Mounted on 1 x 1 FR4 Board. A6 A6 = Specific Device Code ORDERING INFORMATION This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 0 80 Device Package Shipping NTHD5902T1 ChipFET 3000/Tape & Reel Publication Order Number: NTHD5902T1/D NTHD5902T1 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction-to-Ambient (Note 2.) t v 5 sec Steady State RthJA Maximum Junction-to-Foot Steady State RthJF Typ Max 50 90 60 110 30 40 Unit C/W C/W ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit VGS(th) VDS = VGS, ID = 250 A 1.0 - - V Gate-Body Leakage IGSS VDS = 0 V, VGS = "20 V - - "100 nA Zero Gate Voltage Drain Current IDSS SS VDS = 24 V, VGS = 0 V - - 1.0 A VDS = 24 V, VGS = 0 V, TJ = 85C - - 5.0 ID(on) VDS w 5.0 V, VGS = 10 V 10 - - A rDS(on) S( ) VGS = 10 V, ID = 2.9 A - 0.072 0.085 VGS = 4.5 V, ID = 2.2 A - 0.120 0.143 gfs VDS = 15 V, ID = 2.9 A - 20 - S VSD IS = 0.9 A, VGS = 0 V - 0.8 1.2 V - 5.0 7.5 nC - 0.8 - - 1.0 - - 7.0 11 - 12 18 - 12 18 - 7.0 11 - 40 80 Static Gate Threshold Voltage On-State Drain Current (Note 3.) Drain-Source On-State Resistance (Note 3.) Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge Qg VDS = 15 V V, VGS = 10 V V, ID = 2.9 A Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = 15 V, RL = 15 ID ^ 1.0 1 0 A, A VGEN = 10 V, V RG = 6 tf Source-Drain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. IF = 0.9 A, di/dt = 100 A/s http://onsemi.com 81 ns NTHD5902T1 TYPICAL ELECTRICAL CHARACTERISTICS 10 10 VGS = 10 thru 5 V 8 6 ID,Drain Current (A) ID,Drain Current (A) 8 4V 4 2 0 0.5 4 125C 2 3V 0 6 25C TC = -55C 1.0 1.5 2.0 2.5 VDS, Drain-to-Source Voltage (V) 0 3.0 0 Figure 1. Output Characteristics C, Capacitance (pF) 0.15 VGS = 4.5 V 0.10 VGS = 10 V 0.05 Ciss 200 Coss 100 0 Crss 0 0 2 4 6 ID, Drain Current (A) 8 10 0 4 8 12 16 VDS, Drain-to-Source Voltage (V) Figure 3. On-Resistance vs. Drain Current 20 Figure 4. Capacitance 1.8 r DS(on),On-Resistance ( ) (Normalized) 10 VGS,Gate-to-Source Voltage (V) 5 400 300 VDS = 15 V ID = 2.9 A 8 6 4 2 0 4 Figure 2. Transfer Characteristics 0.20 r DS(on),On-Resistance ( ) 1 2 3 VGS, Gate-to-Source Voltage (V) 0 1 2 3 Qg, Total Gate Charge (nC) 4 5 1.6 VGS = 10 V ID = 2.9 A 1.4 1.2 1.0 0.8 0.6 -50 Figure 5. Gate Charge -25 0 25 50 75 100 TJ, Junction Temperature (C) Figure 6. On-Resistance vs. Junction Temperature http://onsemi.com 82 125 150 NTHD5902T1 TYPICAL ELECTRICAL CHARACTERISTICS 0.20 rDS(on),On-Resistance ( ) I S,Source Current (A) 10 TJ = 150C TJ = 25C 1 0.15 ID = 2.9 A 0.10 0.05 0 0 0.2 0.4 0.6 0.8 1.0 VDS, Drain-to-Source Voltage (V) 1.2 Figure 7. Source-Drain Diode Forward Voltage 2 4 6 8 VGS, Gate-to-Source Voltage (V) 10 Figure 8. On-Resistance vs. Gate-to-Source Voltage 0.4 50 0.2 40 ID = 250 A -0.0 Power (W) V GS (th),Varience (V) 0 -0.2 30 20 -0.4 10 -0.6 -0.8 -50 -25 0 25 50 75 TJ, Temperature (C) 100 125 150 0 10-4 Figure 9. Threshold Voltage 10-3 10-2 10 -1 1 Time (sec) 10 Figure 10. Single Pulse Power http://onsemi.com 83 100 600 NTHD5902T1 TYPICAL ELECTRICAL CHARACTERISTICS Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 Notes: PDM 0.2 t1 0.1 t2 0.1 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 90C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10 -1 1 Square Wave Pulse Duration (sec) 10 100 600 Figure 11. Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10 -1 Square Wave Pulse Duration (sec) 1 Figure 12. Normalized Thermal Transient Impedance, Junction-to-Foot http://onsemi.com 84 10 .)! /0 #10% '( - 23 http://onsemi.com S1 S2 G2 G1 PRODUCT SUMMARY VDS (V) -20 D2 D1 rDS(on) () ID (A) 0.155 @ VGS = -4.5 V "2.9 0.180 @ VGS = -3.6 V "2.7 0.260 @ VGS = -2.5 V "2.2 P-Channel MOSFET MAXIMUM RATINGS (TA = 25C unless otherwise noted) Rating Symbol 5 secs Steady State VDS -20 V Gate-Source Voltage VGS "12 V Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current ID Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C PD Operating Junction and Storage Temperature Range -1.8 A -0.9 A D1 8 1 S1 D1 7 2 G1 D2 6 3 S2 D2 5 4 G2 W 2.1 1.1 TJ, Tstg "2.1 "1.5 "10 IDM IS PIN CONNECTIONS A "2.9 "2.1 Continuous Source Current (Diode Conduction) (Note 1.) ChipFET CASE 1206A STYLE 2 Unit Drain-Source Voltage P-Channel MOSFET 1.1 0.6 MARKING DIAGRAM C -55 to +150 A7 1. Surface Mounted on 1 x 1 FR4 Board. A7 = Specific Device Code ORDERING INFORMATION This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 0 85 Device Package Shipping NTHD5903T1 ChipFET 3000/Tape & Reel Publication Order Number: NTHD5903T1/D NTHD5903T1 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction-to-Ambient (Note 2.) t v 5 sec Steady State RthJA Maximum Junction-to-Foot (Drain) Steady State RthJF Typ Max 50 90 60 110 30 40 Unit C/W C/W ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit VGS(th) VDS = VGS, ID = -250 A -0.6 - - V Gate-Body Leakage IGSS VDS = 0 V, VGS = "12 V - - "100 nA Zero Gate Voltage Drain Current IDSS SS VDS = -16 V, VGS = 0 V - - -1.0 A VDS = -16 V, VGS = 0 V, TJ = 85C - - -5.0 ID(on) VDS v -5.0 V, VGS = -4.5 V -10 - - A rDS(on) S( ) VGS = -4.5 V, ID = -2.1 A - 0.130 0.155 VGS = -3.6 V, ID = -2.0 A - 0.150 0.180 VGS = -2.5 V, ID = -1.7 A - 0.215 0.260 gfs VDS = -10 V, ID = -2.1 A - 5.0 - S VSD IS = -0.9 A, VGS = 0 V - -0.8 -1.2 V - 3.0 6.0 nC - 0.9 - Static Gate Threshold Voltage On-State Drain Current (Note 3.) Drain-Source On-State Resistance (Note 3.) Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge Gate-Source Charge Qg 10 V 45V VDS = -10 V, VGS = -4.5 V, ID = -2.1 A Qgs Gate-Drain Charge Qgd - 0.6 - Turn-On Delay Time td(on) - 13 20 - 35 55 - 25 40 - 25 40 - 40 80 Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = -10 V, RL = 10 ID ^ -1.0 -1 0 A A, VGEN = -4 -4.5 5V V, RG = 6 tf Source-Drain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. IF = -0.9 A, di/dt = 100 A/s http://onsemi.com 86 ns NTHD5903T1 TYPICAL ELECTRICAL CHARACTERISTICS 10 10 3.5 V TC = -55C VGS = 5 thru 4 V 8 8 I D,Drain Current (A) ID,Drain Current (A) 3V 6 2.5 V 4 2V 2 25C 125C 6 4 2 1.5 V 0 0 0.5 1.0 1.5 2.0 2.5 VDS, Drain-to-Source Voltage (V) 0 3.0 0 0.5 Figure 1. Output Characteristics 4.0 Figure 2. Transfer Characteristics 0.4 600 500 VGS = 2.5 V 0.3 C, Capacitance (pF) r DS(on),On-Resistance ( ) 3.5 1.0 1.5 2.0 2.5 3.0 VGS, Gate-to-Source Voltage (V) VGS = 3.6 V 0.2 VGS = 4.5 V 0.1 Ciss 400 300 200 Coss 100 0 Crss 0 0 2 4 6 ID, Drain Current (A) 8 10 0 4 8 12 16 VDS, Drain-to-Source Voltage (V) Figure 3. On-Resistance vs. Drain Current Figure 4. Capacitance 1.6 r DS(on),On-Resistance ( ) (Normalized) VGS,Gate-to-Source Voltage (V) 5 VDS = 10 V ID = 2.1 A 4 3 2 1 0 20 0 0.5 1.0 1.5 2.0 2.5 3.0 1.4 VGS = 4.5 V ID = 2.1 A 1.2 1.0 0.8 0.6 -50 Qg, Total Gate Charge (nC) Figure 5. Gate Charge -25 0 25 50 75 100 TJ, Junction Temperature (C) Figure 6. On-Resistance vs. Junction Temperature http://onsemi.com 87 125 150 NTHD5903T1 TYPICAL ELECTRICAL CHARACTERISTICS 0.40 rDS(on),On-Resistance ( ) I S,Source Current (A) 10 TJ = 150C TJ = 25C 0.35 ID = 2.1 A 0.30 0.25 0.20 0.15 0.10 0.05 1 0 0 0.2 0.4 0.6 0.8 1.0 1.2 VDS, Drain-to-Source Voltage (V) 1.4 0 Figure 7. Source-Drain Diode Forward Voltage 2 3 4 VGS, Gate-to-Source Voltage (V) 5 Figure 8. On-Resistance vs. Gate-to-Source Voltage 0.4 50 0.3 40 ID = 250 A 0.2 Power (W) V GS (th),Varience (V) 1 0.1 30 20 0.0 10 -0.1 -0.2 -50 -25 0 25 50 75 TJ, Temperature (C) 100 125 150 0 10-4 Figure 9. Threshold Voltage 10-3 10-2 10 -1 1 Time (sec) 10 Figure 10. Single Pulse Power http://onsemi.com 88 100 600 NTHD5903T1 TYPICAL ELECTRICAL CHARACTERISTICS Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 Notes: PDM 0.2 t1 0.1 t2 0.1 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 90C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10 -1 1 Square Wave Pulse Duration (sec) 10 100 600 Figure 11. Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10 -1 Square Wave Pulse Duration (sec) 1 Figure 12. Normalized Thermal Transient Impedance, Junction-to-Foot http://onsemi.com 89 10 .) /0 10% '( - 23 http://onsemi.com D2 D1 G2 G1 VDS (V) 20 S2 S1 PRODUCT SUMMARY rDS(on) () ID (A) 0.075 @ VGS = 4.5 V "4.2 0.134 @ VGS = 2.5 V "3.1 N-Channel MOSFET N-Channel MOSFET MAXIMUM RATINGS (TA = 25C unless otherwise noted) Rating Symbol Steady State 5 secs Drain-Source Voltage VDS 20 V Gate-Source Voltage VGS "12 V Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current ID Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C PD Operating Junction and Storage Temperature Range 1.8 2.1 1.1 TJ, Tstg "3.1 "2.2 "10 IDM IS PIN CONNECTIONS A "4.2 "3.0 Continuous Source Current (Diode Conduction) (Note 1.) ChipFET CASE 1206A STYLE 2 Unit 0.9 D1 8 1 S1 A D1 7 2 G1 A D2 6 3 S2 W D2 5 4 G2 1.1 0.6 MARKING DIAGRAM C -55 to +150 A2 1. Surface Mounted on 1 x 1 FR4 Board. A2 = Specific Device Code ORDERING INFORMATION This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 0 90 Device Package Shipping NTHD5904T1 ChipFET 3000/Tape & Reel Publication Order Number: NTHD5904T1/D NTHD5904T1 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction-to-Ambient (Note 2.) t v 5 sec Steady State RthJA Maximum Junction-to-Foot (Drain) Steady State RthJF Typ Max 50 90 60 110 30 40 Unit C/W C/W ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit VGS(th) VDS = VGS, ID = 250 A 0.6 - - V Gate-Body Leakage IGSS VDS = 0 V, VGS = "12 V - - "100 nA Zero Gate Voltage Drain Current IDSS SS VDS = 16 V, VGS = 0 V - - 1.0 A VDS = 16 V, VGS = 0 V, TJ = 85C - - 5.0 ID(on) VDS w 5.0 V, VGS = 4.5 V 10 - - A rDS(on) S( ) VGS = 4.5 V, ID = 3.1 A - 0.065 0.075 VGS = 2.5 V, ID = 2.3 A - 0.115 0.143 gfs VDS = 10 V, ID = 3.1 A - 8.0 - S VSD IS = 0.9 A, VGS = 0 V - 0.8 1.2 V - 4.0 6.0 nC - 0.6 - - 1.3 - - 12 18 - 35 55 - 19 30 - 9.0 15 - 40 80 Static Gate Threshold Voltage On-State Drain Current (Note 3.) Drain-Source On-State Resistance (Note 3.) Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge Qg VDS = 10 V V, VGS = 4.5 4 5 V, V ID = 3.1 A Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = 10 V, RL = 10 ID ^ 1.0 1 0 A, A VGEN = 4.5 4 5 V, V RG = 6 tf Source-Drain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. IF = 0.9 A, di/dt = 100 A/s http://onsemi.com 91 ns NTHD5904T1 TYPICAL ELECTRICAL CHARACTERISTICS 10 10 TC = -55C VGS = 5 thru 3 V D,Drain Current (A) 2.5 V 6 4 125C 6 4 I ID,Drain Current (A) 25C 8 8 2V 2 2 1.5 V 0 0 0.5 1.0 1.5 2.0 2.5 VDS, Drain-to-Source Voltage (V) 0 3.0 0 0.5 0.30 600 0.25 500 0.20 0.15 VGS = 2.5 V 0.10 VGS = 4.5 V 0.05 Ciss 400 300 200 Coss 100 Crss 0 0 0 2 4 6 8 0 10 4 ID, Drain Current (A) 8 12 16 VDS, Drain-to-Source Voltage (V) Figure 3. On-Resistance vs. Drain Current 1.6 r DS(on),On-Resistance ( ) (Normalized) VGS,Gate-to-Source Voltage (V) 20 Figure 4. Capacitance 5 VDS = 10 V ID = 3.1 A 4 3 2 1 0 3.5 Figure 2. Transfer Characteristics C, Capacitance (pF) r DS(on),On-Resistance ( ) Figure 1. Output Characteristics 1.0 1.5 2.0 2.5 3.0 VGS, Gate-to-Source Voltage (V) 0 2 3 1 Qg, Total Gate Charge (nC) 1.4 1.2 1.0 0.8 0.6 -50 4 VGS = 4.5 V ID = 3.1 A Figure 5. Gate Charge -25 0 25 50 75 100 TJ, Junction Temperature (C) Figure 6. On-Resistance vs. Junction Temperature http://onsemi.com 92 125 150 NTHD5904T1 TYPICAL ELECTRICAL CHARACTERISTICS 0.20 rDS(on),On-Resistance ( ) I S,Source Current (A) 10 TJ = 150C TJ = 25C 1 0.15 ID = 3.1 A 0.10 0.05 0 0 0.2 0.4 0.6 0.8 1.0 VDS, Drain-to-Source Voltage (V) 1.2 0 Figure 7. Source-Drain Diode Forward Voltage 1 2 3 4 VGS, Gate-to-Source Voltage (V) 5 Figure 8. On-Resistance vs. Gate-to-Source Voltage 0.4 50 0.2 V GS (th),Varience (V) 40 ID = 250 A Power (W) -0.0 -0.2 30 20 -0.4 10 -0.6 -0.8 -50 -25 0 25 50 75 100 TJ, Temperature (C) 125 0 10-4 150 Figure 9. Threshold Voltage 10-3 10-2 10 -1 1 Time (sec) 10 Figure 10. Single Pulse Power http://onsemi.com 93 100 600 NTHD5904T1 TYPICAL ELECTRICAL CHARACTERISTICS Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 Notes: PDM 0.2 t1 0.1 t2 0.1 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 90C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10 -1 1 Square Wave Pulse Duration (sec) 10 100 600 Figure 11. Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10 -1 Square Wave Pulse Duration (sec) 1 Figure 12. Normalized Thermal Transient Impedance, Junction-to-Foot http://onsemi.com 94 10 .) /0 #10% -, 23 '( http://onsemi.com S2 S1 G2 G1 VDS (V) -8.0 D2 D1 PRODUCT SUMMARY rDS(on) () ID (A) 0.090 @ VGS = -4.5 V "4.1 0.130 @ VGS = -2.5 V "3.4 0.180 @ VGS = -1.8 V "2.9 MAXIMUM RATINGS (TA = 25C unless otherwise noted) Rating Symbol 5 secs Steady State VDS -8.0 V Gate-Source Voltage VGS "8.0 V Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current ID Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C PD Operating Junction and Storage Temperature Range -1.8 A -0.9 A D1 8 1 S1 D1 7 2 G1 D2 6 3 S2 D2 5 4 G2 W 2.1 1.1 TJ, Tstg "3.0 "2.2 "10 IDM IS PIN CONNECTIONS A "4.1 "2.9 Continuous Source Current (Diode Conduction) (Note 1.) ChipFET CASE 1206A STYLE 2 Unit Drain-Source Voltage P-Channel MOSFET P-Channel MOSFET 1.1 0.6 MARKING DIAGRAM C -55 to +150 A9 1. Surface Mounted on 1 x 1 FR4 Board. A9 = Specific Device Code ORDERING INFORMATION This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 0 95 Device Package Shipping NTHD5905T1 ChipFET 3000/Tape & Reel Publication Order Number: NTHD5905T1/D NTHD5905T1 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction-to-Ambient (Note 2.) t v 5 sec Steady State RthJA Maximum Junction-to-Foot (Drain) Steady State RthJF Typ Max 50 90 60 110 30 40 Unit C/W C/W ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit VGS(th) VDS = VGS, ID = -250 A -0.45 - - V Gate-Body Leakage IGSS VDS = 0 V, VGS = "8.0 V - - "100 nA Zero Gate Voltage Drain Current IDSS SS VDS = -6.4 V, VGS = 0 V - - -1.0 A VDS = -6.4 V, VGS = 0 V, TJ = 85C - - -5.0 ID(on) VDS v -5.0 V, VGS = -4.5 V -10 - - A rDS(on) S( ) VGS = -4.5 V, ID = -3.0 A - 0.075 0.090 VGS = -2.5 V, ID = -2.5 A - 0.110 0.130 VGS = -1.8 V, ID = -1.0 A - 0.150 0.180 gfs VDS = -5.0 V, ID = -3.0 A - 7.0 - S VSD IS = -0.9 A, VGS = 0 V - -0.8 -1.2 V - 5.5 9.0 nC - 0.5 - Static Gate Threshold Voltage On-State Drain Current (Note 3.) Drain-Source On-State Resistance (Note 3.) Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge Gate-Source Charge Qg 40V 45V VDS = -4.0 V, VGS = -4.5 V, ID = -3.0 A Qgs Gate-Drain Charge Qgd - 1.5 - Turn-On Delay Time td(on) - 10 15 - 45 70 - 30 45 - 10 15 - 30 60 Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = -4.0 V, RL = 4 ID ^ -1.0 -1 0 A A, VGEN = -4 -4.5 5V V, RG = 6 tf Source-Drain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. IF = -0.9 A, di/dt = 100 A/s http://onsemi.com 96 ns NTHD5905T1 TYPICAL ELECTRICAL CHARACTERISTICS 10 10 TC = -55C 2.5 V VGS = 5 thru 3 V 25C 8 D,Drain Current (A) ID,Drain Current (A) 8 2V 6 4 1.5 V 2 125C 6 4 2 1V 0 0 0.5 1.0 1.5 2.0 2.5 VDS, Drain-to-Source Voltage (V) 0 3.0 0 0.5 Figure 1. Output Characteristics 800 VGS = 1.8 V C, Capacitance (pF) r DS(on),On-Resistance ( ) 1000 0.25 0.20 VGS = 2.5 V 0.15 VGS = 4.5 V 0.10 Ciss 600 400 Coss 200 0.05 Crss 0 0 0 2 4 6 ID, Drain Current (A) 8 10 0 4 8 12 16 VDS, Drain-to-Source Voltage (V) Figure 3. On-Resistance vs. Drain Current 20 Figure 4. Capacitance 5 1.6 r DS(on),On-Resistance ( ) (Normalized) VGS,Gate-to-Source Voltage (V) 3.0 Figure 2. Transfer Characteristics 0.30 4 3 2 1 0 1.0 1.5 2.0 2.5 VGS, Gate-to-Source Voltage (V) 0 1 2 3 4 Qg, Total Gate Charge (nC) 5 6 1.4 VGS = 4.5 V ID = 3 A 1.2 1.0 0.8 0.6 -50 Figure 5. Gate Charge -25 0 25 50 75 100 TJ, Junction Temperature (C) Figure 6. On-Resistance vs. Junction Temperature http://onsemi.com 97 125 150 NTHD5905T1 TYPICAL ELECTRICAL CHARACTERISTICS 0.25 rDS(on),On-Resistance ( ) I S,Source Current (A) 10 TJ = 150C TJ = 25C 1 0.20 0.15 0.10 0.05 0 0 0.2 0.4 0.6 0.8 1.0 VDS, Drain-to-Source Voltage (V) 1.2 1.4 Figure 7. Source Diode Forward Voltage 0 1 2 3 4 VGS, Gate-to-Source Voltage (V) 5 Figure 8. On-Resistance vs. Gate-to-Source Voltage 0.4 50 0.3 40 ID = 250 A 0.2 Power (W) V GS (th),Varience (V) ID = 3 A 0.1 30 20 0.0 10 -0.1 -0.2 -50 -25 0 25 50 75 100 TJ, Temperature (C) 125 150 0 10-4 Figure 9. Threshold Voltage 10-3 10-2 10 -1 1 Time (sec) 10 Figure 10. Single Pulse Power http://onsemi.com 98 100 600 NTHD5905T1 TYPICAL ELECTRICAL CHARACTERISTICS Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 Notes: PDM 0.2 t1 0.1 t2 0.1 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 90C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10 -1 1 Square Wave Pulse Duration (sec) 10 100 600 Figure 11. Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10 -1 Square Wave Pulse Duration (sec) 1 Figure 12. Normalized Thermal Transient Impedance, Junction-to-Foot http://onsemi.com 99 10 . 10% ! 23 '( http://onsemi.com D G S PRODUCT SUMMARY VDS (V) 30 rDS(on) () ID (A) 0.035 @ VGS = 10 V "6.7 0.055 @ VGS = 4.5 V "5.3 N-Channel MOSFET MAXIMUM RATINGS (TA = 25C unless otherwise noted) Rating Symbol Steady State 5 secs Unit Drain-Source Voltage VDS 30 V Gate-Source Voltage VGS "20 V Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current ID Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C PD Operating Junction and Storage Temperature Range 2.1 1.1 D 8 1 D A D 7 2 D A D 6 3 D S 5 4 G W 2.5 1.3 TJ, Tstg "4.9 "3.5 "20 IDM IS PIN CONNECTIONS A "6.7 "4.8 Continuous Source Current (Diode Conduction) (Note 1.) ChipFET CASE 1206A STYLE 1 1.3 0.7 MARKING DIAGRAM C -55 to +150 1. Surface Mounted on 1 x 1 FR4 Board. A6 A6 = Specific Device Code ORDERING INFORMATION This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 0 100 Device Package Shipping NTHS5402T1 ChipFET 3000/Tape & Reel Publication Order Number: NTHS5402T1/D NTHS5402T1 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction-to-Ambient (Note 2.) t v 5 sec Steady State RthJA Maximum Junction-to-Foot (Drain) Steady State RthJF Typ Max 40 80 50 95 15 20 Unit C/W C/W ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit VGS(th) VDS = VGS, ID = 250 A 1.0 - - V Gate-Body Leakage IGSS VDS = 0 V, VGS = "20 V - - "100 nA Zero Gate Voltage Drain Current IDSS SS VDS = 24 V, VGS = 0 V - - 1.0 A VDS = 24 V, VGS = 0 V, TJ = 85C - - 5.0 ID(on) VDS w 5.0 V, VGS = 10 V 20 - - A rDS(on) S( ) VGS = 10 V, ID = 4.9 A - 0.030 0.035 VGS = 4.5 V, ID = 3.9 A - 0.045 0.055 gfs VDS = 10 V, ID = 4.9 A - 15 - S VSD IS = 1.1 A, VGS = 0 V - 0.8 1.2 V - 13 20 nC - 1.3 - - 3.1 - - 10 15 - 10 15 - 25 40 - 10 15 - 30 60 Static Gate Threshold Voltage On-State Drain Current (Note 3.) Drain-Source On-State Resistance (Note 3.) Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge Qg VDS = 15 V V, VGS = 10 V V, ID = 4.9 A Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = 15 V, RL = 15 ID ^ 1.0 1 0 A, A VGEN = 10 V, V RG = 6 tf Source-Drain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. IF = 1.1 A, di/dt = 100 A/s http://onsemi.com 101 ns NTHS5402T1 TYPICAL CHARACTERISTICS 20 20 4V 16 ID,Drain Current (A) ID,Drain Current (A) VGS = 10 thru 5 V 16 12 8 3V 12 8 TC125C 4 4 0 0 25C TC = -55C 0 0.5 1.0 1.5 2.0 2.5 VDS, Drain-to-Source Voltage (V) 3.0 0 0.5 Figure 1. Output Characteristics 1.5 2.0 2.5 3.0 3.5 4.0 Figure 2. Transfer Characteristics 1200 0.10 1000 0.08 0.06 C, Capacitance (pF) r DS(on),On-Resistance ( ) 1.0 VGS, Gate-to-Source Voltage (V) VGS = 4.5 V 0.04 VGS = 10 V 0.02 Ciss 800 600 400 Coss 200 Crss 0 0 0 4 8 12 ID, Drain Current (A) 16 20 0 6 12 18 24 VDS, Drain-to-Source Voltage (V) Figure 3. On-Resistance vs. Drain Current Figure 4. Capacitance 1.6 r DS(on),On-Resistance ( ) (Normalized) VGS,Gate-to-Source Voltage (V) 10 VDS = 15 V ID = 4.9 A 8 6 4 2 0 30 0 3 6 9 Qg, Total Gate Charge (nC) 12 15 1.4 VGS = 10 V ID = 4.9 A 1.2 1.0 0.8 0.6 -50 Figure 5. Gate Charge -25 0 25 50 75 100 TJ, Junction Temperature (C) Figure 6. On-Resistance vs. Junction Temperature http://onsemi.com 102 125 150 NTHS5402T1 TYPICAL CHARACTERISTICS 0.10 20 rDS(on),On-Resistance ( ) I S,Source Current (A) TJ = 150C 10 TJ = 25C 1 0.08 ID = 4.9 A 0.06 0.04 0.02 0 0 0.2 0.4 0.6 0.8 1.0 VSD, Source-to-Drain Voltage (V) 1.2 0 Figure 7. Source-Drain Diode Forward Voltage 10 Figure 8. On-Resistance vs. Gate-to-Source Voltage 0.4 50 0.2 40 ID = 250 A -0.0 Power (W) V GS (th),Varience (V) 2 4 6 8 VGS, Gate-to-Source Voltage (V) -0.2 30 20 -0.4 10 -0.6 -0.8 -50 -25 0 25 50 75 100 TJ, Temperature (C) 125 150 0 10-3 Figure 9. Threshold Voltage 10-2 10 -1 1 Time (sec) 10 100 Figure 10. Single Pulse Power http://onsemi.com 103 600 NTHS5402T1 TYPICAL CHARACTERISTICS Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 Notes: 0.2 PDM t1 0.1 t2 0.1 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 80C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10 -1 1 Square Wave Pulse Duration (sec) 10 100 600 Figure 11. Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10 -1 Square Wave Pulse Duration (sec) 1 Figure 12. Normalized Thermal Transient Impedance, Junction-to-Foot http://onsemi.com 104 10 NTHS5402T1 80 mm 80 mm 18 mm 25 mm 68 mm 28 mm 28 mm 26 mm 26 mm Figure 13. Figure 14. BASIC PAD PATTERNS confines of the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. The basic pad layout with dimensions is shown in Figure 13. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 14 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the http://onsemi.com 105 . 10% - 23 '( http://onsemi.com D G S PRODUCT SUMMARY VDS (V) 20 rDS(on) () ID (A) 0.030 @ VGS = 4.5 V "7.2 0.045 @ VGS = 2.5 V "5.9 N-Channel MOSFET MAXIMUM RATINGS (TA = 25C unless otherwise noted) Rating Symbol Steady State 5 secs Unit Drain-Source Voltage VDS 20 V Gate-Source Voltage VGS "12 V Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current ID Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C PD Operating Junction and Storage Temperature Range 2.1 D 8 1 D D 7 2 D D 6 3 D S 5 4 G A 1.1 A W 2.5 1.3 TJ, Tstg "5.2 "3.8 "20 IDM IS PIN CONNECTIONS A "7.2 "5.2 Continuous Source Current (Diode Conduction) (Note 1.) ChipFET CASE 1206A STYLE 1 1.3 0.7 MARKING DIAGRAM C -55 to +150 A2 1. Surface Mounted on 1 x 1 FR4 Board. A2 = Specific Device Code ORDERING INFORMATION This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 0 106 Device Package Shipping NTHS5404T1 ChipFET 3000/Tape & Reel Publication Order Number: NTHS5404T1/D NTHS5404T1 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction-to-Ambient (Note 2.) t v 5 sec Steady State RthJA Maximum Junction-to-Foot (Drain) Steady State RthJF Typ Max 40 80 50 95 15 20 Unit C/W C/W ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit VGS(th) VDS = VGS, ID = 250 A 0.6 - - V Gate-Body Leakage IGSS VDS = 0 V, VGS = "12 V - - "100 nA Zero Gate Voltage Drain Current IDSS SS VDS = 16 V, VGS = 0 V - - 1.0 A VDS = 16 V, VGS = 0 V, TJ = 85C - - 5.0 ID(on) VDS w 5.0 V, VGS = 4.5 V 20 - - A rDS(on) S( ) VGS = 4.5 V, ID = 5.2 A - 0.025 0.030 VGS = 2.5 V, ID = 4.3 A - 0.038 0.045 gfs VDS = 10 V, ID = 5.2 A - 20 - S VSD IS = 1.1 A, VGS = 0 V - 0.8 1.2 V - 12 18 nC - 2.4 - - 3.2 - - 20 30 - 40 60 - 40 60 - 15 23 - 30 60 Static Gate Threshold Voltage On-State Drain Current (Note 3.) Drain-Source On-State Resistance (Note 3.) Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge Qg VDS = 10 V V, VGS = 4.5 4 5 V, V ID = 5.2 A Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = 10 V, RL = 10 ID ^ 1.0 1 0 A, A VGEN = 4.5 4 5 V, V RG = 6 tf Source-Drain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. IF = 1.1 A, di/dt = 100 A/s http://onsemi.com 107 ns NTHS5404T1 80 mm 80 mm 18 mm 25 mm 68 mm 28 mm 28 mm 26 mm 26 mm Figure 1. Figure 2. BASIC PAD PATTERNS the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. The basic pad layout with dimensions is shown in Figure 1. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 2 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the confines of http://onsemi.com 108 . #10% - 23 '( http://onsemi.com S G D PRODUCT SUMMARY VDS (V) -20 rDS(on) () ID (A) 0.055 @ VGS = -4.5 V "5.3 0.06 @ VGS = -3.6 V "5.1 0.083 @ VGS = -2.5 V "4.3 P-Channel MOSFET ChipFET CASE 1206A STYLE 1 MAXIMUM RATINGS (TA = 25C unless otherwise noted) Rating Symbol 5 secs Steady State Unit Drain-Source Voltage VDS -20 V Gate-Source Voltage VGS "12 V Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current ID Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C PD -2.1 A -1.1 D 8 1 D D 7 2 D D 6 3 D S 5 4 G A W 2.5 1.3 TJ, Tstg "3.9 "2.8 "20 IDM IS Operating Junction and Storage Temperature Range A "5.3 "3.8 Continuous Source Current (Note 1.) PIN CONNECTIONS 1.3 0.7 MARKING DIAGRAM C -55 to +150 A3 1. Surface Mounted on 1 x 1 FR4 Board. A3 = Specific Device Code ORDERING INFORMATION This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 0 109 Device Package Shipping NTHS5441T1 ChipFET 3000/Tape & Reel Publication Order Number: NTHS5441T1/D NTHS5441T1 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction-to-Ambient (Note 2.) t v 5 sec Steady State RthJA Maximum Junction-to-Foot (Drain) Steady State RthJF Typ Max 40 80 50 95 15 20 Unit C/W C/W ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit VGS(th) VDS = VGS, ID = -250 A -0.6 - - V Gate-Body Leakage IGSS VDS = 0 V, VGS = "12 V - - "100 nA Zero Gate Voltage Drain Current IDSS SS VDS = -16 V, VGS = 0 V - - -1.0 A VDS = -16 V, VGS = 0 V, TJ = 85C - - -5.0 ID(on) VDS v -5.0 V, VGS = -4.5 V -20 - - A rDS(on) S( ) VGS = -3.6 V, ID = -3.7 A - 0.050 0.06 VGS = -2.5 V, ID = -3.1 A - 0.070 0.083 gfs VDS = -10 V, ID = -3.9 A - 12 - S VSD IS = -1.1 A, VGS = 0 V - -0.8 -1.2 V - 11 22 nC - 3.0 - - 2.5 - - 20 30 - 35 55 - 65 100 - 45 70 - 30 60 Static Gate Threshold Voltage On-State Drain Current (Note 3.) Drain-Source On-State Resistance (Note 3.) Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge Qg VDS = -10 10 V V, VGS = -4.5 45V V, ID = -3.9 A Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = -10 V, RL = 10 ID ^ -1.0 -1 0 A A, VGEN = -4 -4.5 5V V, RG = 6 tf Source-Drain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. IF = -1.1 A, di/dt = 100 A/s http://onsemi.com 110 ns NTHS5441T1 80 mm 80 mm 18 mm 25 mm 68 mm 28 mm 28 mm 26 mm 26 mm Figure 1. Figure 2. BASIC PAD PATTERNS the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. The basic pad layout with dimensions is shown in Figure 1. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 2 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the confines of http://onsemi.com 111 .! #10% - 23 '( http://onsemi.com S G D PRODUCT SUMMARY VDS (V) -20 RDS(on) () ID (A) 0.065 @ VGS = -4.5 V "4.9 0.074 @ VGS = -3.6 V "4.6 0.110 @ VGS = -2.5 V "3.8 P-Channel MOSFET ChipFET CASE 1206A STYLE 1 MAXIMUM RATINGS (TA = 25C unless otherwise noted) Rating Symbol 5 secs Steady State Unit Drain-Source Voltage VDS -20 V Gate-Source Voltage VGS "12 V Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C ID IDM Continuous Source Current (Note 1.) IAS Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C PD Operating Junction and Storage Temperature Range A "4.9 "3.5 Pulsed Drain Current -2.1 D 8 1 D D 7 2 D A D 6 3 D A S 5 4 G "3.6 "2.6 "15 -1.1 W 2.5 1.3 TJ, Tstg PIN CONNECTIONS MARKING DIAGRAM 1.3 0.7 C -55 to +150 A4 1. Surface Mounted on 1 x 1 FR4 Board. A4 = Specific Device Code ORDERING INFORMATION This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2001 January, 2001 - Rev. 1 112 Device Package Shipping NTHS5443T1 ChipFET 3000/Tape & Reel Publication Order Number: NTHS5443T1/D NTHS5443T1 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction-to-Ambient (Note 2.) t v 5 sec Steady State RthJA Maximum Junction-to-Foot (Drain) Steady State RthJF Typ Max 40 80 50 95 15 20 Unit C/W C/W ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit VGS(th) VDS = VGS, ID = -250 A -0.6 - - V Gate-Body Leakage IGSS VDS = 0 V, VGS = "12 V - - "100 nA Zero Gate Voltage Drain Current IDSS SS VDS = -16 V, VGS = 0 V - - -1.0 A VDS = -16 V, VGS = 0 V, TJ = 85C - - -5.0 ID(on) VDS v -5.0 V, VGS = -4.5 V -15 - - A rDS(on) S( ) VGS = -4.5 V, ID = -3.6 A - 0.056 0.065 VGS = -3.6 V, ID = -3.3 A - 0.065 0.074 VGS = -2.5 V, ID = -2.7 A - 0.095 0.110 gfs VDS = -10 V, ID = -3.6 A - 10 - S VSD IS = -1.1 A, VGS = 0 V - -0.8 -1.2 V - 9.0 14 nC - 2.2 - Static Gate Threshold Voltage On-State Drain Current (Note 3.) Drain-Source On-State Resistance (N t 3 (Note 3.)) Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge Gate-Source Charge Qg 10 V 45V VDS = -10 V, VGS = -4.5 V, ID = -3.6 A Qgs Gate-Drain Charge Qgd - 2.2 - Turn-On Delay Time td(on) - 15 25 - 30 45 - 50 75 - 35 50 - 30 60 Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Source-Drain Reverse Recovery Time trr VDD = -10 V, RL = 10 ID ^ -1.0 -1 0 A A, VGEN = -4 -4.5 5V V, RG = 6 IF = -1.1 A, di/dt = 100 A/s 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. http://onsemi.com 113 s ns . #10% -, 23 '( http://onsemi.com S G D PRODUCT SUMMARY VDS (V) -8.0 rDS(on) () ID (A) 0.035 @ VGS = -4.5 V "7.1 0.047 @ VGS = -2.5 V "6.2 0.062 @ VGS = -1.8 V "5.7 P-Channel MOSFET MAXIMUM RATINGS (TA = 25C unless otherwise noted) Rating Symbol 5 secs Steady State Unit Drain-Source Voltage VDS -8.0 V Gate-Source Voltage VGS "8.0 V Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current ID Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C PD Operating Junction and Storage Temperature Range -2.1 A -1.1 A D 8 1 D D 7 2 D D 6 3 D S 5 4 G W 2.5 1.3 TJ, Tstg "5.2 "3.7 "20 IDM IS PIN CONNECTIONS A "7.1 "5.2 Continuous Source Current (Note 1.) ChipFET CASE 1206A STYLE 1 1.3 0.7 MARKING DIAGRAM C -55 to +150 A5 1. Surface Mounted on 1 x 1 FR4 Board. A5 = Specific Device Code ORDERING INFORMATION This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2001 January, 2001 - Rev. 1 114 Device Package Shipping NTHS5445T1 ChipFET 3000/Tape & Reel Publication Order Number: NTHS5445T1/D NTHS5445T1 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction-to-Ambient (Note 2.) t v 5 sec Steady State RthJA Maximum Junction-to-Foot (Drain) Steady State RthJF Typ Max 40 80 50 95 15 20 Unit C/W C/W ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit VGS(th) VDS = VGS, ID = -250 A -0.45 - - V Gate-Body Leakage IGSS VDS = 0 V, VGS = "8.0 V - - "100 nA Zero Gate Voltage Drain Current IDSS SS VDS = -6.4 V, VGS = 0 V - - -1.0 A VDS = -6.4 V, VGS = 0 V, TJ = 85C - - -5.0 ID(on) VDS v -5.0 V, VGS = -4.5 V -20 - - A rDS(on) S( ) VGS = -4.5 V, ID = -5.2 A - 0.030 0.035 VGS = -2.5 V, ID = -4.5 A - 0.040 0.047 VGS = -1.8 V, ID = -2.0 A - 0.052 0.062 gfs VDS = -5.0 V, ID = -5.2 A - 18 - S VSD IS = -1.1 A, VGS = 0 V - -0.8 -1.2 V - 17 26 nC - 2.8 - Static Gate Threshold Voltage On-State Drain Current (Note 3.) Drain-Source On-State Resistance (Note 3.) Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge Gate-Source Charge Qg 40V 45V VDS = -4.0 V, VGS = -4.5 V, ID = -5.2 A Qgs Gate-Drain Charge Qgd - 2.6 - Turn-On Delay Time td(on) - 15 25 - 45 70 - 110 165 - 65 100 - 30 60 Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = -4.0 V, RL = 4 ID ^ -1.0 -1 0 A A, VGEN = -4 -4.5 5V V, RG = 6 tf Source-Drain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. IF = -1.1 A, di/dt = 100 A/s http://onsemi.com 115 ns NTHS5445T1 TYPICAL ELECTRICAL CHARACTERISTICS 20 20 VGS = 5 thru 2.5 V TC = -55C 16 2V ID,Drain Current (A) ID,Drain Current (A) 16 12 8 1.5 V 4 25C 125C 12 8 4 1V 0 0 0.5 1.0 1.5 2.0 2.5 VDS, Drain-to-Source Voltage (V) 0 3.0 0 0.5 1.0 1.5 2.0 VGS, Gate-to-Source Voltage (V) Figure 1. Output Characteristics Figure 2. Transfer Characteristics 3000 0.08 2500 VGS = 1.8 V C, Capacitance (pF) r DS(on),On-Resistance ( ) 0.10 0.06 VGS = 2.5 V 0.04 VGS = 4.5 V 0.02 Ciss 2000 1500 Coss 1000 500 Crss 0 0 0 4 8 12 ID, Drain Current (A) 16 0 20 2 4 6 VDS, Drain-to-Source Voltage (V) Figure 3. On-Resistance vs. Drain Current 1.6 r DS(on),On-Resistance ( ) (Normalized) VGS,Gate-to-Source Voltage (V) 8 Figure 4. Capacitance 5 VDS = 4 V ID = 5.2 A 4 3 2 1 0 2.5 0 4 8 12 Qg, Total Gate Charge (nC) 16 20 1.4 VGS = 4.5 V ID = 5.2 A 1.2 1.0 0.8 0.6 -50 Figure 5. Gate Charge -25 0 25 50 75 100 TJ, Junction Temperature (C) 125 Figure 6. On-Resistance vs. Junction Temperature http://onsemi.com 116 150 NTHS5445T1 TYPICAL ELECTRICAL CHARACTERISTICS 0.10 rDS(on),On-Resistance ( ) 20 TJ = 150C I S,Source Current (A) 10 TJ = 25C 1 0.08 0.04 0.02 0 0 0.2 0.4 0.6 0.8 1.0 VDS, Drain-to-Source Voltage (V) ID = 5.2 A 0.06 1.2 0 Figure 7. Source-Drain Diode Forward Voltage 1 2 3 4 VGS, Gate-to-Source Voltage (V) 5 Figure 8. On-Resistance vs. Gate-to-Source Voltage 50 0.4 0.3 40 V GS (th),Varience (V) ID = 250 A Power (W) 0.2 0.1 30 20 0.0 10 -0.1 -0.2 -50 -25 0 25 50 75 100 TJ, Temperature (C) 125 0 10-3 150 Figure 9. Threshold Voltage 10-2 10 -1 1 Time (sec) 10 100 Figure 10. Single Pulse Power http://onsemi.com 117 600 NTHS5445T1 TYPICAL ELECTRICAL CHARACTERISTICS Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 Notes: 0.2 PDM t1 0.1 t2 0.1 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 80C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10 -1 1 Square Wave Pulse Duration (sec) 10 100 600 Figure 11. Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10 -1 Square Wave Pulse Duration (sec) 1 Figure 12. Normalized Thermal Transient Impedance, Junction-to-Foot http://onsemi.com 118 10 NTHS5445T1 80 mm 80 mm 18 mm 25 mm 68 mm 28 mm 28 mm 26 mm 26 mm Figure 13. Figure 14. BASIC PAD PATTERNS confines of the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. The basic pad layout with dimensions is shown in Figure 13. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 14 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the http://onsemi.com 119 !#! #$%& '( !- ! Dual P-Channel SO-8 Features * * * * * * * http://onsemi.com High Efficiency Components in a Dual SO-8 Package High Density Power MOSFET with Low RDS(on) Miniature SO-8 Surface Mount Package - Saves Board Space Diode Exhibits High Speed with Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for the SO-8 Package is Provided -3.05 AMPERES -30 VOLTS 0.085 W @ VGS = -10 V P-Channel Applications * DC-DC Converters * Low Voltage Motor Control * Power Management in Portable and Battery-Powered Products, i.e.: D Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones G MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit -30 V Gate-to-Source Voltage - Continuous VDSS VGS 20 V Thermal Resistance - Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) RJA PD ID ID IDM 171 0.73 -2.34 -1.87 -8.0 C/W W A A A Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) RJA PD ID ID IDM 100 1.25 -3.05 -2.44 -12 C/W W A A A RJA PD ID ID IDM TJ, Tstg 62.5 2.0 -3.86 -3.1 -15 C/W W A A A -55 to +150 C EAS 140 mJ TL 260 Rating Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = -30 Vdc, VGS = -4.5 Vdc, Peak IL = -7.5 Apk, L = 5 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds January, 2001 - Rev. 0 MARKING DIAGRAM SO-8 CASE 751 STYLE 11 8 ED3P03 LYWW 1 ED3P03 L Y WW = Device Code = Assembly Location = Year = Work Week PIN ASSIGNMENT Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 Top View C ORDERING INFORMATION Device 1. Minimum FR-4 or G-10 PCB, t = Steady State. 2. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t = steady state. 3. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. Semiconductor Components Industries, LLC, 2001 S 120 NTMD3P03R2 Package Shipping SO-8 2500/Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Publication Order Number: NTMD3P03R2/D NTMD3P03R2 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 5.) Characteristic Symbol Min Typ Max Unit -30 - - -30 - - - - - - - - -1.0 -20 -2.0 - - -100 - - 100 -1.0 - -1.7 3.6 -2.5 - - - 0.063 0.090 0.085 0.125 gFS - 5.0 - Mhos Ciss - 520 750 pF Coss - 170 325 Crss - 70 135 td(on) - 12 22 tr - 16 30 td(off) - 45 80 tf - 45 80 td(on) - 16 - tr - 42 - td(off) - 32 - tf - 35 - Qtot - 16 25 Qgs - 2.0 - Qgd - 4.5 - VSD - - -0.96 -0.78 -1.25 - Vdc trr - 34 - ns ta - 18 - tb - 16 - QRR - 0.03 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = -250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = -24 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = -24 Vdc, VGS = 0 Vdc, TJ = 125C) (VDS = -30 Vdc, VGS = 0 Vdc, TJ = 25C) IDSS Gate-Body Leakage Current (VGS = -20 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-State Resistance (VGS = -10 Vdc, ID = -3.05 Adc) (VGS = -4.5 Vdc, ID = -1.5 Adc) RDS(on) Forward Transconductance (VDS = -15 Vdc, ID = -3.05 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = -24 24 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6. and 7.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = -24 Vdc, ID = -3.05 Adc, VGS = -10 10 Vdc Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time (VDD = -24 Vdc, ID = -1.5 Adc, VGS = -4.5 4 5 Vdc, Vdc RG = 6.0 ) Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (VDS = -24 Vdc, VGS = -10 Vdc, ID = -3.05 3 05 Adc) Ad ) Gate-Source Charge Gate-Drain Charge ns ns nC BODY-DRAIN DIODE RATINGS (Note 6.) Diode Forward On-Voltage (IS = -3.05 Adc, VGS = 0 V) (IS = -3.05 Adc, VGS = 0 V, TJ = 125C) Reverse Recovery Time (IS = -3.05 3 05 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. http://onsemi.com 121 C NTMD3P03R2 TYPICAL ELECTRICAL CHARACTERISTICS -ID, DRAIN CURRENT (AMPS) VGS = -4 V VGS = -4.6 V VGS = -6 V 4 VGS = -4.8 V TJ = 25C 3 VGS 2 VGS = -3.6 V VGS = -2.8 V VGS = -3.2 V = -5 V VGS = -2.6 V VGS = -3 V 1 0 0.25 0.5 0.75 1 1.25 1.5 1.75 TJ = 25C 2 TJ = -55C 1 1 2 3 4 5 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics ID = -3.05 A TJ = 25C 0.5 0.4 0.3 0.2 0.1 5 4 6 7 8 0.7 ID = -1.5 A TJ = 25C 0.6 0.5 0.4 0.3 0.2 0.1 0 2 4 3 5 6 7 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 3. On-Resistance vs. Gate-to-Source Voltage Figure 4. On-Resistance vs. Gate-to-Source Voltage 0.25 TJ = 25C 0.2 VGS = -4.5 V 0.15 VGS = -10 V 0.1 0.05 1 TJ = 100C 3 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 0.6 3 4 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.7 0 VDS > = -10 V 5 0 2 2 3 4 5 6 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN-TO-SOURCE RESISTANCE () VGS = -4.4 V VGS = -8 V 5 0 RDS(on), DRAIN-TO-SOURCE RESISTANCE () 6 VGS = -10 V RDS(on), DRAIN-TO-SOURCE RESISTANCE () -ID, DRAIN CURRENT (AMPS) 6 1.6 1.4 ID = -3.05 A VGS = -10 V 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 125 -ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (C) Figure 5. On-Resistance vs. Drain Current and Gate Voltage Figure 6. On Resistance Variation with Temperature http://onsemi.com 122 150 NTMD3P03R2 10000 VDS = 0 V 1200 C, CAPACITANCE (pF) IDSS, LEAKAGE (nA) VGS = 0 V TJ = 150C 1000 TJ = 125C 100 VGS = 0 V Ciss 1000 800 Ciss Crss 600 400 Coss 200 Crss TJ = 25C 10 14 18 22 26 0 10 30 0 5 -VDS 10 15 20 25 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Drain-to-Source Leakage Current vs. Voltage Figure 8. Capacitance Variation 30 30 1000 12 QT 10 VDS = -24 V ID = -3.05 A VGS = -10 V 25 VDS 20 8 100 VGS 15 6 Q1 4 tr td(on) ID = -3.05 A TJ = 25C 0 2 4 6 8 10 12 0 16 14 1 10 1 100 Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE () Figure 9. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge Figure 10. Resistive Switching Time Variation vs. Gate Resistance 3 100 tr tf 1 10 IS, SOURCE CURRENT (AMPS) VDS = -24 V ID = -1.5 A VGS = -4.5 V 10 tf 5 2 0 td(off) 10 10 Q2 1000 t, TIME (ns) 5 -VGS t, TIME (ns) -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 6 td(off) td(on) 100 VGS = 0 V TJ = 25C 2.5 2 1.5 1 0.5 0 0.2 0.4 0.6 0.8 1 RG, GATE RESISTANCE () -VSD, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 11. Resistive Switching Time Variation vs. Gate Resistance Figure 12. Diode Forward Voltage vs. Current http://onsemi.com 123 1.2 NTMD3P03R2 VGS = 12 V SINGLE PULSE TC = 25C 10 1.0 ms di/dt 10 ms IS dc 1.0 ta 0.01 trr tb TIME 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 1.0 0.25 IS tp 10 IS 100 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 13. Maximum Rated Forward Biased Safe Operating Area Figure 14. Diode Reverse Recovery Waveform 1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE -ID, DRAIN CURRENT (AMPS) 100 D = 0.5 0.2 0.1 0.1 Normalized to RJA at Steady State (1 pad) Chip Junction 2.32 18.5 50.9 37.1 56.8 0.05 0.02 0.01 1E-03 0.0014 F 0.01 0.0073 F 0.022 F 0.105 F 0.484 F 3.68 F Ambient Single Pulse 1E-02 24.4 1E-01 1E+00 1E+01 t, TIME (s) Figure 15. FET Thermal Response http://onsemi.com 124 1E+02 1E+03 NTMD3P03R2 INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 125 NTMD3P03R2 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 126 #$%& '( - N-Channel Enhancement Mode Dual SO-8 Package http://onsemi.com Features * * * * * * * Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature Dual SO-8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified SO-8 Mounting Information Provided 6.0 AMPERES 20 VOLTS 35 mW @ VGS = 4.5 V N-Channel Applications D * DC-DC Converters * Low Voltage Motor Control * Power Management in Portable and Battery-Powered Products, i.e.: Computers, Printers, Cellular and Cordless Telephones and PCMCIA Cards G MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Value Unit Drain-to-Source Voltage VDSS 20 V Drain-to-Gate Voltage (RGS = 1.0 MW) VDGR 20 V Gate-to-Source Voltage - Continuous VGS "12 V RJA PD ID ID IDM 62.5 2.0 6.5 5.5 20 C/W W A A A Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) RJA PD ID ID IDM 102 1.22 5.07 4.07 16 C/W W A A A 2. 3. 4. RJA PD ID ID IDM Mounted onto a 2 square FR-4 Board (1 sq. 2 oz. Cu sided), t < 10 seconds. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz. Cu sided), t = steady state. Minimum FR-4 or G-10 PCB, t = steady state. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. November, 2000 - Rev. 0 SO-8 CASE 751 STYLE 11 MARKING DIAGRAM & PIN ASSIGNMENT Source 1 Gate 1 Source 2 Gate 2 172 0.73 3.92 3.14 12 C/W W A A A 0.06 thick single 1 8 2 7 3 E6N02 LYWW 4 6 5 Drain 1 Drain 1 Drain 2 Drain 2 (Top View) E6N02 L Y WW = Device Code = Assembly Location = Year = Work Week 0.06 thick single ORDERING INFORMATION Device This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2000 8 1 Thermal Resistance - Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) Thermal Resistance - Junction-to-Ambient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) 1. S Symbol 127 NTMD6N02R2 Package Shipping SO-8 2500/Tape & Reel Publication Order Number: NTMD6N02R2/D NTMD6N02R2 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (continued) Rating Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 6.0 Apk, L = 20 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes for 10 seconds Symbol Value Unit TJ, Tstg -55 to +150 C EAS 360 mJ TL 260 C ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 5.) Characteristic Symbol Min Typ Max 20 - - 19.2 - - - - - - 1.0 10 Unit OFF CHARACTERISTICS V(BR)DSS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Vdc mV/C Adc Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = +12 Vdc, VDS = 0 Vdc) IGSS - - 100 nAdc Gate-Body Leakage Current (VGS = -12 Vdc, VDS = 0 Vdc) IGSS - - -100 nAdc 0.6 - 0.9 -3.0 1.2 - - - - - 0.028 0.028 0.033 0.035 0.035 0.043 0.048 0.049 gFS - 10 - Mhos Ciss - 785 1100 pF Coss - 260 450 Crss - 75 180 td(on) - 12 20 tr - 50 90 td(off) - 45 75 ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-State Resistance (VGS = 4.5 Vdc, ID = 6.0 Adc) (VGS = 4.5 Vdc, ID = 4.0 Adc) (VGS = 2.7 Vdc, ID = 2.0 Adc) (VGS = 2.5 Vdc, ID = 3.0 Adc) RDS(on) Forward Transconductance (VDS = 12 Vdc, ID = 3.0 Adc) Vdc mV/C DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6. and 7.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 16 Vdc, ID = 6.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 16 Vdc, ID = 4.0 Adc, 5 Vdc VGS = 4 4.5 Vdc, RG = 6.0 ) Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge (VDS = 16 Vdc, VGS = 4.5 Vdc, ID = 6.0 6 0 Ad Adc)) 5. Handling precautions to protect against electrostatic discharge is mandatory 6. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. http://onsemi.com 128 tf - 80 130 td(on) - 11 18 tr - 35 65 td(off) - 45 75 tf - 60 110 Qtot - 12 20 Qgs - 1.5 - Qgd - 4.0 - ns ns nC NTMD6N02R2 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (continued) (Note 8.) Characteristic Symbol Min Typ Max Unit VSD - - - 0.83 0.88 0.75 1.1 1.2 - Vdc trr - 30 - ns ta - 15 - tb - 15 - QRR - 0.02 - BODY-DRAIN DIODE RATINGS (Note 9.) Diode Forward On-Voltage (IS = 4.0 Adc, VGS = 0 Vdc) (IS = 6.0 Adc, VGS = 0 Vdc) (IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 6.0 6 0 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge C 8. Handling precautions to protect against electrostatic discharge is mandatory. 9. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 2.5 V 12 2.0 V 4.5 V 3.2 V ID, DRAIN CURRENT (AMPS) 10 TJ = 25C 8 1.8 V 6 4 VGS = 1.5 V 2 0 R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 10 V 0 0.25 0.5 0.75 1 1.25 1.5 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 1. On-Region Characteristics 0.07 ID = 6.0 A TJ = 25C 0.06 0.05 0.04 0.03 0.02 0.01 0 0 2 4 6 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 VDS 10 V 10 8 6 4 25C 100C TJ = -55C 2 0 1.75 R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) I D, DRAIN CURRENT (AMPS) 12 0.5 1 1.5 2 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 2.5 Figure 2. Transfer Characteristics 0.05 TJ = 25C 0.04 VGS = 2.5 V 0.03 4.5 V 0.02 0.01 1 Figure 3. On-Resistance versus Gate-To-Source Voltage 3 9 5 7 ID, DRAIN CURRENT (AMPS) 11 13 Figure 4. On-Resistance versus Drain Current and Gate Voltage http://onsemi.com 129 1.6 1000 ID = 6.0 A VGS = 4.5 V 1.4 I DSS , LEAKAGE (nA) 1.2 1 VGS = 0 V TJ = 125C 100 100C 10 1 25C 0.1 0.8 0.6 -50 0.01 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 4 VDS = 0 V 2000 VGS = 0 V TJ = 25C Ciss 1500 Crss 1000 Ciss 500 Coss Crss 0 10 5 0 5 10 15 VGS VDS 20 5 20 QT 16 4 VDS VGS 3 12 Q1 2 ID = 6 A VDS = 16 V VGS = 4.5 V TJ = 25C Q2 8 4 1 0 0 0 4 8 12 16 Qg, TOTAL GATE CHARGE (nC) GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 7. Capacitance Variation 1000 VDS = 16 V ID = 6.0 A VGS = 4.5 V t, TIME (ns) C, CAPACITANCE (pF) 2500 100 tf tr td(off) td(on) 10 1 20 Figure 6. Drain-To-Source Leakage Current versus Voltage VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature 8 12 16 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 RG, GATE RESISTANCE (OHMS) Figure 9. Resistive Switching Time Variation versus Gate Resistance http://onsemi.com 130 100 V DS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) NTMD6N02R2 NTMD6N02R2 DRAIN-TO-SOURCE DIODE CHARACTERISTICS 100 VGS = 0 V TJ = 25C 4 I D , DRAIN CURRENT (AMPS) I S, SOURCE CURRENT (AMPS) 5 3 2 1 0 VGS = 12 V SINGLE PULSE TC = 25C 10 10 ms 1 0.1 0 0.2 0.4 0.6 0.8 1.2 1.0 1 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 0.1 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) dc 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current Figure 11. Maximum Rated Forward Biased Safe Operating Area di/dt IS ta trr tb TIME 0.25 IS tp IS Figure 12. Diode Reverse Recovery Waveform TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 0.2 0.1 0.1 0.05 *0 0.02 0.01 0.01 ' '# - - " '&'# SINGLE PULSE ,' " (' , - . / / ' ,*0 " *0 ,' 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 t, TIME (s) Figure 13. Thermal Response http://onsemi.com 131 1.0E+01 1.0E+02 1.0E+03 NTMD6N02R2 INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 132 NTMD6N02R2 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 14. Typical Solder Heating Profile http://onsemi.com 133 # Preferred Device #$%& '( P-Channel SO-8, Dual Features * * * * * * * Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature Dual SO-8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified SO-8 Mounting Information Provided http://onsemi.com 6 AMPERES 20 VOLTS RDS(on) = 33 mW Applications * Power Management in Portable and Battery-Powered Products, i.e.: P-Channel Cellular and Cordless Telephones and PCMCIA Cards D MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Symbol Value Unit VDSS -20 V Gate-to-Source Voltage - Continuous VGS "12 V Thermal Resistance - Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) RJA PD ID ID PD ID IDM 62.5 2.0 -7.8 -5.7 0.5 -3.89 -40 C/W W A A W A A Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) RJA PD ID ID PD ID IDM 98 1.28 -6.2 -4.6 0.3 -3.01 -35 C/W W A A W A A Thermal Resistance - Junction-to-Ambient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) RJA PD ID ID PD ID IDM 166 0.75 -4.8 -3.5 0.2 -2.48 -30 C/W W A A W A A 1. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz. Cu 0.06 thick single sided), t = 10 seconds. 2. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz. Cu 0.06 thick single sided), t = steady state. 3. Minimum FR-4 or G-10 PCB, t = steady state. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. G S MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 11 8 E6P02 LYWW 1 E6P02 L Y WW = Device Code = Location Code = Year = Work Week PIN ASSIGNMENT Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 Top View ORDERING INFORMATION Device NTMD6P02R2 Package SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 134 Publication Order Number: NTMD6P02R2/D NTMD6P02R2 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (continued) Rating Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = -20 Vdc, VGS = -5.0 Vdc, Peak IL = -5.0 Apk, L = 40 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes for 10 seconds Symbol Value Unit TJ, Tstg -55 to +150 C EAS 500 mJ TL 260 C ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 5.) Characteristic Symbol Min Typ Max Unit -20 - - -11.6 - - - - - - -1.0 -5.0 - - -100 - - 100 -0.6 - -0.88 2.6 -1.20 - - - - 0.027 0.038 0.038 0.033 0.050 - gFS - 15 - Mhos pF OFF CHARACTERISTICS V(BR)DSS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = -250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = -20 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = -20 Vdc, VGS = 0 Vdc, TJ = 70C) IDSS Gate-Body Leakage Current (VGS = -12 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +12 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-State Resistance (VGS = -4.5 Vdc, ID = -6.2 Adc) (VGS = -2.5 Vdc, ID = -5.0 Adc) (VGS = -2.5 Vdc, ID = -3.1 Adc) RDS(on) Forward Transconductance (VDS = -10 Vdc, ID = -6.2 Adc) Vdc mV/C DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance 16 Vdc, Vd VGS = 0 Vdc, Vd (VDS = -16 f = 1.0 MHz) Reverse Transfer Capacitance Ciss - 1380 1700 Coss - 515 775 Crss - 250 450 td(on) - 15 25 SWITCHING CHARACTERISTICS (Notes 6. and 7.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = -10 Vdc, ID = -1.0 Adc, 10 Vdc, Vdc VGS = -10 RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = -16 Vdc, ID = -6.2 Adc, VGS = -4.5 4 5 Vdc, Vdc RG = 6.0 ) Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge (VDS = -16 Vdc, VGS = -4.5 Vdc, ID = -6.2 6 2 Ad Adc)) 5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. http://onsemi.com 135 tr - 20 50 td(off) - 85 125 tf - 50 110 td(on) - 17 - tr - 65 - td(off) - 50 - tf - 80 - Qtot - 20 35 Qgs - 4.0 - Qgd - 8.0 - ns ns nC NTMD6P02R2 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (continued) (Note 8.) Characteristic Symbol Min Typ Max Unit BODY-DRAIN DIODE RATINGS (Note 9..) Diode Forward On-Voltage (IS = -1.7 Adc, VGS = 0 Vdc) (IS = -1.7 Adc, VGS = 0 Vdc, TJ = 125C) VSD - - -0.80 -0.65 -1.2 - Vdc Diode Forward On-Voltage (IS = -6.2 Adc, VGS = 0 Vdc) (IS = -6.2 Adc, VGS = 0 Vdc, TJ = 125C) VSD - - -0.95 -0.80 - - Vdc trr - 50 80 ns ta - 20 - tr - 30 - QRR - 0.04 - Reverse Recovery Time (IS = -1.7 1 7 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge C 8. Handling precautions to protect against electrostatic discharge is mandatory. 9. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. -10 V 10 -4.5 V -3.8 V 10 -2.1 V -ID, DRAIN CURRENT (AMPS) -ID, DRAIN CURRENT (AMPS) 12 TJ = 25C 8.0 -3.1 V -2.5 V 6.0 -1.8 V 4.0 2.0 0 -1.5 V VGS = -1.3 V 0 VDS -10 V 8.0 6.0 25C 4.0 100C 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = -55C 2.0 0 1.0 1.5 2.0 2.5 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 2. Transfer Characteristics 0.05 ID = -6.2 A TJ = 25C 0.04 0.03 0.02 0.01 0 0 2.0 4.0 6.0 8.0 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) Figure 1. On-Region Characteristics 0.05 TJ = 25C VGS = -2.5 V 0.04 -2.7 V 0.03 -4.5 V 0.02 0.01 0 Figure 3. On-Resistance versus Gate-To-Source Voltage 2.0 8.0 10 4.0 6.0 -ID, DRAIN CURRENT (AMPS) 12 14 Figure 4. On-Resistance versus Drain Current and Gate Voltage http://onsemi.com 136 1.6 1000 ID = -6.2 A VGS = -4.5 V 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 100C 10 1 25C 0.1 4 5000 C, CAPACITANCE (pF) 4500 4000 VGS = 0 V TJ = 25C Ciss 3500 3000 2500 Crss 2000 Ciss 1500 1000 Coss Crss 500 0 10 5.0 0 5.0 10 15 20 -VGS -VDS 5 20 QT 16 4 VDS 3 Q1 VGS 12 Q2 8 2 ID = -6.2 A VDS = -16 V VGS = -4.5 V TJ = 25C 1 4 0 0 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 1000 5.0 0 10 15 20 25 Qg, TOTAL GATE CHARGE (nC) Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge 1000 VDD = -16 V ID = -1.0 A VGS = -10 V VDD = -16 V ID = -6.2 A VGS = -4.5 V td(off) tf t, TIME (ns) t, TIME (ns) 8 12 16 20 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 6. Drain-To-Source Leakage Current versus Voltage VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature VDS = 0 V TJ = 125C 100 0.01 150 VGS = 0 V V DS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1.4 -I DSS , LEAKAGE (nA) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) NTMD6P02R2 100 tr 100 tf tr td(off) td(on) td(on) 10 10 1 10 100 1 10 100 RG, GATE RESISTANCE (OHMS) RG, GATE RESISTANCE (OHMS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Resistive Switching Time Variation versus Gate Resistance http://onsemi.com 137 NTMD6P02R2 DRAIN-TO-SOURCE DIODE CHARACTERISTICS 100 VGS = 0 V TJ = 25C 4 -ID , DRAIN CURRENT (AMPS) -IS, SOURCE CURRENT (AMPS) 5 3 2 1 0 0.2 0.4 0.6 0.8 10 ms 1 1.2 1.0 1.0 ms 10 0.1 0 VGS = 2.5 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) dc 1 0.1 10 100 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 11. Diode Forward Voltage versus Current Figure 12. Maximum Rated Forward Biased Safe Operating Area di/dt IS ta trr tb TIME 0.25 IS tp IS Figure 13. Diode Reverse Recovery Waveform TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t) , EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 1 0.1 D = 0.5 0.2 0.1 0.05 2%* 0.02 0.01 :$ : #:9 $6 . 8$6 . 4:6 . $::9 :89 0.01 SINGLE PULSE :87 . :$$ . +%1' 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 t, TIME (s) Figure 14. Thermal Response http://onsemi.com 138 1.0E+01 1.0E+02 1.0E+03 NTMD6P02R2 INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 139 NTMD6P02R2 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 15. Typical Solder Heating Profile http://onsemi.com 140 " #$%& '( )- 213 2#13 Complementary SO-8 http://onsemi.com MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol N P Unit Drain-to-Source Voltage VDSS 20 -20 Vdc Gate-to-Source Voltage VGS 20 12 Vdc ID 7.0 4.5 A Rating Drain Current - Continuous (Note 1.) Operating and Storage Temperature Range TJ, Tstg Thermal Resistance (Note 2.) - Junction-to-Ambient C -55 to +150 RJA 50 1. Mounted on 1 square FR-4 board. 2. Mounted on 1 square FR-4 board, t 10 seconds. 9.5 AMPERES, 20 VOLTS RDS(on) = 24 mW (N-Channel) 4 AMPERES, 20 VOLTS RDS(on) = 108 mW (P-Channel) N-Channel P-Channel D D C/W 50 G G S S MARKING DIAGRAM SO-8 CASE 751 STYLE 20 8 NTMDC02 YWW 1 NTMDC02 Y WW = Device Code = Year = Work Week PIN ASSIGNMENT Source (N) 1 8 Drain Gate (N) 2 7 Drain Source (P) 3 6 Drain Gate (P) 4 5 Drain Top View ORDERING INFORMATION Semiconductor Components Industries, LLC, 2001 January, 2001 - Rev. 0 141 Device Package NTMD7C02R2 SO-8 Shipping 2500 Units/Rail Publication Order Number: NTMD7C02/D NTMD7C02 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Polarity Min Typ Max Unit (N) (P) - - - - 1.0 1.0 (N) (P) - - - - 100 100 (N) (P) 1.0 0.6 - - - - (N) (P) (P) - - - 19 63 94 24 74 108 Ciss (N) (P) - - 1470 500 1750 570 Coss (N) (P) - - 660 190 770 220 Crss (N) (P) - - 189 58 260 80 td(on) (N) (P) - - 22 12 30 20 tr (N) (P) - - 38 22 50 30 td(off) (N) (P) - - 38 36 50 50 tf (N) (P) - - 31 24 45 35 QT (N) (P) - - 16 7.0 20 9.0 Qgs (N) (P) - - 4.5 0.6 6.0 1.0 Qgd (N) (P) - - 7.0 1.7 9.0 2.5 VSD (N) (P) - - 730 840 760 870 Vdc trr (N) (P) - - 104 24 160 36 ns ta (N) (P) - - 18 13.5 28 22 tb (N) (P) - - 85 11 140 20 Qrr (N) (P) - - 0.082 0.018 0.12 0.028 OFF CHARACTERISTICS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) (VGS = 12 Vdc, VDS = 0 Vdc) IGSS Adc nAdc ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) (VDS = VGS, ID = 250 Adc) VGS(th) Static Drain-to-Source On-State Resistance (VGS = 4.5 Vdc, ID = 7.0 Adc) (VGS = 4.5 Vdc, ID = 4.5 Adc) (VGS = 2.5 Vdc, ID = 3.5 Adc) RDS(on) Vdc mOhms DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vd Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 1.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) Fall Time Gate Charge (VDS = 10 Vd Vdc, ID = 4.5 Adc, VGS = 4.5 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 3.) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 25_C) Reverse Recovery Time (IF = 1.7 Adc, VGS = 0 Vdc, di/dt = 100 As) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width = 300 s, Duty Cycle= 2%. http://onsemi.com 142 C # #$%& '( P-Channel Enhancement-Mode Single SO-8 Package http://onsemi.com Features * * * * * * * Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature SO-8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified SO-8 Mounting Information Provided -10 AMPERES -20 VOLTS 14 mW @ VGS = -4.5 V P-Channel D Applications * Power Management in Portable and Battery-Powered Products, i.e.: Cellular and Cordless Telephones and PCMCIA Cards MAXIMUM RATINGS (TJ = 25C unless otherwise noted) G Symbol Value Unit VDSS VGS -20 Vdc Gate-to-Source Voltage - Continuous "12 Vdc Thermal Resistance - Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 3.) RJA PD ID ID PD ID IDM 50 2.5 -10 -8.0 0.6 -5.5 -50 C/W W A A W A A RJA PD ID ID PD ID IDM TJ, Tstg 80 1.6 -8.8 -6.4 0.4 -4.5 -44 C/W W A A W A A -55 to +150 C 500 mJ Rating Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 3.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = -20 Vdc, VGS = -4.5 Vdc, Peak IL = 5.0 Apk, L = 40 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds EAS S 8 1 SO-8 CASE 751 STYLE 12 MARKING DIAGRAM & PIN ASSIGNMENT Source Source Source Gate 1 8 2 7 3 E10P02 LYWW 4 6 5 Drain Drain Drain Drain Top View TL C 260 E10P02 L Y WW = Device Code = Assembly Location = Year = Work Week 1. Mounted onto a 2 square FR-4 Board (1 sq. Cu 0.06 thick single sided), t = 10 seconds. 2. Mounted onto a 2 square FR-4 Board (1 sq. Cu 0.06 thick single sided), t = steady state. 3. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2%. Device Package Shipping This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. NTMS10P02R2 SO-8 2500/Tape & Reel Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 2 143 ORDERING INFORMATION Publication Order Number: NTMS10P02R2/D NTMS10P02R2 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 4.) Characteristic Symbol Min Typ Max Unit -20 - - -12.1 - - - - - - -1.0 -5.0 - - -100 - - 100 -0.6 - -0.88 2.8 -1.20 - - - 0.012 0.017 0.014 0.020 gFS - 30 - Mhos Ciss - 3100 3640 pF Coss - 1100 1670 Crss - 475 1010 td(on) - 25 35 tr - 40 65 td(off) - 110 190 tf - 110 190 td(on) - 25 - tr - 100 - td(off) - 100 - tf - 125 - Qtot - 48 70 Qgs - 6.5 - Qgd - 17 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = -250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = -20 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = -20 Vdc, VGS = 0 Vdc, TJ = 70C) IDSS Gate-Body Leakage Current (VGS = -12 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +12 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-State Resistance (VGS = -4.5 Vdc, ID = -10 Adc) (VGS = -2.5 Vdc, ID = -8.8 Adc) RDS(on) Forward Transconductance (VDS = -10 Vdc, ID = -10 Adc) Vdc mV/C DYNAMIC CHARACTERISTICS Input Capacitance (VDS = -16 16 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 5. & 6.) Turn-On Delay Time (VDD = -10 Vdc, ID = -1.0 Adc, VGS = -4.5 4 5 Vdc, Vdc RG = 6.0 ) Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time (VDD = -10 Vdc, ID = -10 Adc, 4 5 Vdc, Vdc VGS = -4.5 RG = 6.0 ) Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (VDS = -10 Vdc, VGS = -4.5 Vdc, ID = -10 10 Ad Adc)) Gate-Source Charge Gate-Drain Charge ns ns nC BODY-DRAIN DIODE RATINGS (Note 5.) Diode Forward On-Voltage (IS = -2.1 Adc, VGS = 0 Vdc) (IS = -2.1 Adc, VGS = 0 Vdc, TJ = 125C) VSD - - -0.72 -0.60 -1.2 - Vdc Diode Forward On-Voltage (IS = -10 Adc, VGS = 0 Vdc) (IS = -10 Adc, VGS = 0 Vdc, TJ = 125C) VSD - - -0.90 -0.75 - - Vdc trr - 65 100 ns ta - 25 - tb - 40 - QRR - 0.075 - Reverse Recovery Time (IS = -2.1 2 1 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 4. Handling precautions to protect against electrostatic discharge is mandatory. 5. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 6. Switching characteristics are independent of operating junction temperature. http://onsemi.com 144 C NTMS10P02R2 -2.3 V 15 10 -2.1 V -10 V -3.1 V VDS -10 V 20 TJ = 25C -1.9 V 10 VGS = -1.7 V 5.0 0 0 8.0 6.0 100C 2.0 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 25C 4.0 0 0.5 1.0 1.5 2.0 2.5 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 0.100 ID = -10 A TJ = 25C 0.075 0.050 0.025 0 2.0 4.0 6.0 8.0 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 Figure 2. Transfer Characteristics 0.020 TJ = 25C VGS = -2.5 V 0.016 VGS = -4.5 V 0.012 0.008 6.0 Figure 3. On-Resistance versus Gate-To-Source Voltage 10 14 -ID, DRAIN CURRENT (AMPS) 18 Figure 4. On-Resistance versus Drain Current and Gate Voltage 1.6 10,000 VGS = 0 V ID = -10 A VGS = -4.5 V 1.4 < Figure 1. On-Region Characteristics 0 TJ = -55C 1.2 1.0 TJ = 125C 1000 TJ = 100C 100 0.8 0.6 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 10 2.0 Figure 5. On-Resistance Variation with Temperature 6.0 10 14 18 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 145 NTMS10P02R2 10,000 C, CAPACITANCE (pF) VGS = 0 V 8000 VDS = 0 V TJ = 25C Ciss 6000 Crss 4000 Ciss 2000 Coss Crss 0 10 5.0 0 5.0 -VGS -VDS 15 10 20 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) 5.0 10 QT 4.0 8.0 VGS VDS 3.0 6.0 Q1 Q2 4.0 2.0 1.0 ID = -10 A TJ = 25C Q3 2.0 0 0 0 10 20 40 30 50 Qg, TOTAL GATE CHARGE (nC) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) -VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge 1000 1000 td(off) tf VDD = -10 V ID = -10 A VGS = -4.5 V tr 100 td(on) t, TIME (ns) t, TIME (ns) VDD = -10 V ID = -1.0 A VGS = -4.5 V 10 td(off) tr tf 100 td(on) 10 1.0 10 100 1.0 10 100 RG, GATE RESISTANCE (OHMS) RG, GATE RESISTANCE (OHMS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Resistive Switching Time Variation versus Gate Resistance http://onsemi.com 146 NTMS10P02R2 DRAIN-TO-SOURCE DIODE CHARACTERISTICS 2.0 VGS = 0 V TJ = 25C -ID , DRAIN CURRENT (AMPS) -IS, SOURCE CURRENT (AMPS) 100 1.6 1.2 0.8 0.4 0 100 ms 0.55 0.60 0.70 0.65 10 ms VGS = 2.5 V SINGLE PULSE TC = 25C 1.0 0.1 0.50 1.0 ms 10 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 0.1 -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) dc 10 100 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 11. Diode Forward Voltage versus Current Figure 12. Maximum Rated Forward Biased Safe Operating Area di/dt IS ta trr tb TIME 0.25 IS tp IS Figure 13. Diode Reverse Recovery Waveform TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t) , EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 1.0 0.1 D = 0.5 0.2 0.1 0.05 2%* 0.02 0.01 94 9$# 788 4: . 998 . $$6 . 96 7$# 0.01 764: . :#69 . SINGLE PULSE +%1' 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 t, TIME (s) Figure 14. Thermal Response http://onsemi.com 147 1.0E+01 1.0E+02 1.0E+03 NTMS10P02R2 INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 148 NTMS10P02R2 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 15. Typical Solder Heating Profile http://onsemi.com 149 !#! #$%& '( !- ! P-Channel SO-8 Features * * * * * * * http://onsemi.com High Efficiency Components in a Single SO-8 Package High Density Power MOSFET with Low RDS(on) Miniature SO-8 Surface Mount Package - Saves Board Space Diode Exhibits High Speed with Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for the SO-8 Package is Provided -3.05 AMPERES -30 VOLTS 0.085 W @ VGS = -10 V P-Channel Applications * DC-DC Converters * Low Voltage Motor Control * Power Management in Portable and Battery-Powered Products, i.e.: D Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones G MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit -30 V Gate-to-Source Voltage - Continuous VDSS VGS 20 V Thermal Resistance - Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) RJA PD ID ID IDM 171 0.73 -2.34 -1.87 -8.0 C/W W A A A Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) RJA PD ID ID IDM 100 1.25 -3.05 -2.44 -12 C/W W A A A RJA PD ID ID IDM TJ, Tstg 62.5 2.0 -3.86 -3.1 -15 C/W W A A A N.C. 1 8 Drain Source 2 7 Drain -55 to +150 C Source 3 6 Drain Gate 4 5 Drain EAS 140 mJ TL 260 C Rating Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = -30 Vdc, VGS = -4.5 Vdc, Peak IL = -7.5 Apk, L = 5 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds January, 2001 - Rev. 0 MARKING DIAGRAM SO-8 CASE 751 STYLE 13 8 E3P03 LYWW 1 E3P03 L Y WW = Device Code = Assembly Location = Year = Work Week PIN ASSIGNMENT Top View ORDERING INFORMATION 1. Minimum FR-4 or G-10 PCB, t = Steady State. 2. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t = steady state. 3. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. Semiconductor Components Industries, LLC, 2001 S 150 Device NTMS3P03R2 Package Shipping SO-8 2500/Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Publication Order Number: NTMS3P03R2/D NTMS3P03R2 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 5.) Characteristic Symbol Min Typ Max Unit -30 - - -30 - - - - - - -1.0 -10 - - -100 - - 100 -1.0 - -1.7 3.6 -2.5 - - - 0.063 0.090 0.085 0.115 gFS - 5.0 - Mhos Ciss - 520 750 pF Coss - 170 325 Crss - 70 135 td(on) - 12 22 tr - 16 30 td(off) - 45 80 tf - 45 80 td(on) - 16 - tr - 42 - td(off) - 32 - tf - 35 - Qtot - 16 25 Qgs - 2.0 - Qgd - 4.5 - VSD - - -0.96 -0.78 -1.25 - Vdc trr - 34 - ns ta - 18 - tb - 16 - QRR - 0.03 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = -250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = -30 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = -30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = -20 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-State Resistance (VGS = -10 Vdc, ID = -3.05 Adc) (VGS = -4.5 Vdc, ID = -1.5 Adc) RDS(on) Forward Transconductance (VDS = -15 Vdc, ID = -3.05 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = -24 24 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6. & 7.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = -24 Vdc, ID = -3.05 Adc, VGS = -10 10 Vdc Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time (VDD = -24 Vdc, ID = -1.5 Adc, 4 5 Vdc, Vdc VGS = -4.5 RG = 6.0 ) Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (VDS = -24 Vdc, VGS = -10 Vdc, ID = -3.05 3 05 Adc) Ad ) Gate-Source Charge Gate-Drain Charge ns ns nC BODY-DRAIN DIODE RATINGS (Note 6.) Diode Forward On-Voltage (IS = -3.05 Adc, VGS = 0 V) (IS = -3.05 Adc, VGS = 0 V, TJ = 125C) Reverse Recovery Time (IS = -3.05 3 05 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. http://onsemi.com 151 C NTMS3P03R2 TYPICAL ELECTRICAL CHARACTERISTICS -ID, DRAIN CURRENT (AMPS) VGS = -4 V VGS = -4.6 V VGS = -6 V 4 VGS = -4.8 V TJ = 25C 3 VGS 2 VGS = -3.6 V VGS = -2.8 V VGS = -3.2 V = -5 V VGS = -2.6 V VGS = -3 V 1 0 0.25 0.5 0.75 1 1.25 1.5 1.75 TJ = 25C 2 TJ = -55C 1 1 2 3 4 5 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics ID = -3.05 A TJ = 25C 0.5 0.4 0.3 0.2 0.1 5 4 6 7 8 0.7 ID = -1.5 A TJ = 25C 0.6 0.5 0.4 0.3 0.2 0.1 0 2 4 3 5 6 7 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 3. On-Resistance vs. Gate-to-Source Voltage Figure 4. On-Resistance vs. Gate-to-Source Voltage 0.25 TJ = 25C 0.2 VGS = -4.5 V 0.15 VGS = -10 V 0.1 0.05 1 TJ = 100C 3 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 0.6 3 4 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.7 0 VDS > = -10 V 5 0 2 2 3 4 5 6 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN-TO-SOURCE RESISTANCE () VGS = -4.4 V VGS = -8 V 5 0 RDS(on), DRAIN-TO-SOURCE RESISTANCE () 6 VGS = -10 V RDS(on), DRAIN-TO-SOURCE RESISTANCE () -ID, DRAIN CURRENT (AMPS) 6 1.6 1.4 ID = -3.05 A VGS = -10 V 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 125 -ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (C) Figure 5. On-Resistance vs. Drain Current and Gate Voltage Figure 6. On Resistance Variation with Temperature http://onsemi.com 152 150 NTMS3P03R2 10000 C, CAPACITANCE (pF) IDSS, LEAKAGE (nA) VGS = 0 V TJ = 150C 1000 TJ = 125C 100 1200 VDS = 0 V 1000 Ciss VGS = 0 V 800 Ciss Crss 600 400 Coss 200 Crss TJ = 25C 0 10 10 14 10 22 18 26 30 0 5 -VDS 10 15 20 25 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Drain-to-Source Leakage Current vs. Voltage Figure 8. Capacitance Variation 30 30 1000 12 QT 10 VDS = -24 V ID = -3.05 A VGS = -10 V 25 VDS 8 20 100 VGS 15 6 Q1 4 tr 5 ID = -3.05 A TJ = 25C 0 2 4 6 8 10 12 0 16 14 1 10 1 100 Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE () Figure 9. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge Figure 10. Resistive Switching Time Variation vs. Gate Resistance 3 100 tr tf 1 10 IS, SOURCE CURRENT (AMPS) VDS = -24 V ID = -1.5 A VGS = -4.5 V 10 tf td(on) 2 0 td(off) 10 10 Q2 1000 t, TIME (ns) 5 -VGS t, TIME (ns) -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 6 td(off) td(on) 100 VGS = 0 V TJ = 25C 2.5 2 1.5 1 0.5 0 0.2 0.4 0.6 0.8 1 RG, GATE RESISTANCE () -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 11. Resistive Switching Time Variation vs. Gate Resistance Figure 12. Diode Forward Voltage vs. Current http://onsemi.com 153 1.2 NTMS3P03R2 VGS = 12 V SINGLE PULSE TA = 25C 10 1.0 ms di/dt 10 ms IS dc 1.0 ta trr tb TIME 0.1 RDS(on) THERMAL LIMIT PACKAGE LIMIT 0.01 0.1 1.0 0.25 IS tp 10 IS 100 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 13. Maximum Rated Forward Biased Safe Operating Area Figure 14. Diode Reverse Recovery Waveform 1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE -ID, DRAIN CURRENT (AMPS) 100 D = 0.5 0.2 0.1 0.1 Normalized to RJA at Steady State (1 pad) Chip Junction 2.32 18.5 50.9 37.1 56.8 0.05 0.02 0.01 1E-03 0.0014 F 0.01 0.0073 F 0.022 F 0.105 F 0.484 F 3.68 F Ambient Single Pulse 1E-02 24.4 1E-01 1E+00 1E+01 t, TIME (s) Figure 15. FET Thermal Response http://onsemi.com 154 1E+02 1E+03 NTMS3P03R2 INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 155 NTMS3P03R2 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 156 #$%& '( - N-Channel Enhancement-Mode Single SO-8 Package Features * High Density Power MOSFET with Ultra Low RDS(on) Providing * * * * Higher Efficiency Miniature SO-8 Surface Mount Package Saving Board Space; Mounting Information for the SO-8 Package is Provided IDSS Specified at Elevated Temperature Drain-to-Source Avalanche Energy Specified Diode Exhibits High Speed, Soft Recovery http://onsemi.com 4.2 AMPERES 20 VOLTS 0.045 W @ VGS = 4.5 V Applications * Power Management in Portable and Battery-Powered Products, i.e.: Single N-Channel Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones D MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Symbol Value Unit 20 V 20 V Gate-to-Source Voltage - Continuous VDSS VDGR VGS 10 V Thermal Resistance - Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) RJA PD ID ID IDM 50 2.5 5.9 4.7 25 C/W W A A A Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) RJA PD ID ID IDM 100 1.25 4.2 3.3 20 C/W W A A A RJA PD ID ID IDM TJ, Tstg 162 0.77 3.3 2.6 15 C/W W A A A -55 to +150 C 169 mJ Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 mW) Thermal Resistance - Junction-to-Ambient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 7.5 Apk, L = 6 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds EAS G S 8 1 SO-8 CASE 751 STYLE 13 MARKING DIAGRAM & PIN ASSIGNMENT N.C. Source Source Gate TL C 260 7 3 E4N01 LYWW 4 E4N01 L Y WW 6 5 Drain Drain Drain Drain 157 = Device Code = Assembly Location = Year = Work Week ORDERING INFORMATION Device NTMS4N01R2 February, 2001 - Rev. 2 8 2 Top View 1. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. 2. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t = steady state. 3. Minimum FR-4 or G-10 PCB, t = Steady State. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. Semiconductor Components Industries, LLC, 2001 1 Package Shipping SO-8 2500/Tape & Reel Publication Order Number: NTMS4N01R2/D NTMS4N01R2 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 5.) Characteristic Symbol Min Typ Max Unit 20 - - 20 - - - - - - - 0.2 1.0 10 - - - 100 - - -100 0.6 - 0.95 -3.0 1.2 - - - - 0.030 0.035 0.037 0.04 0.05 - gFS - 10 - Mhos Ciss - 870 1200 pF Coss - 260 400 Crss - 60 100 td(on) - 13 25 tr - 35 65 td(off) - 45 75 tf - 50 90 Qtot - 11 16 Qgs - 2.0 - Qgd - 3.0 - VSD - - 0.85 0.70 1.1 - Vdc trr - 20 - ns ta - 12 - tb - 8.0 - QRR - 0.01 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 12 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = 12 Vdc, VGS = 0 Vdc, TJ = 125C) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 25C) IDSS Gate-Body Leakage Current (VGS = +10 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = -10 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-State Resistance (VGS = 4.5 Vdc, ID = 4.2 Adc) (VGS = 2.7 Vdc, ID = 2.1 Adc) (VGS = 2.5 Vdc, ID = 2.0 Adc) RDS(on) Forward Transconductance (VDS = 2.5 Vdc, ID = 2.0 Adc) Vdc mV/C DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6. & 7.) Turn-On Delay Time (VDD = 12 Vdc, ID = 4.2 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 2.3 ) Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (VDS = 12 Vdc, VGS = 4.5 Vdc, ID = 4.2 4 2 Ad Adc)) Gate-Source Charge Gate-Drain Charge ns nC BODY-DRAIN DIODE RATINGS (Note 6.) Diode Forward On-Voltage (IS = 4.2 Adc, VGS = 0 Vdc) (IS = 4.2 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 4.2 4 2 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. http://onsemi.com 158 C NTMS4N01R2 8V 2.1 V 6 1.9 V 4.5 V 3.1 V 2.7 V 2.5 V 2.3 V 5 4 3 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 7 TJ = 25C 1.7 V 2 1 0 1.5 V VGS = 1.3 V 0 0.25 0.5 0.75 1 1.25 1.5 1.75 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 6 4 100C 2 25C TJ = -55C 0 2 VDS 10 V 8 0.5 ID = 4.2 A TJ = 25C 0.06 0.05 0.04 0.03 0.02 0 2 4 6 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 8 RDS(on), DRAIN-TO SOURCE-RESISTANCE (W) 0.08 0.07 0.05 TJ = 25C 0.04 VGS = 2.5 V VGS = 2.7 V 0.03 VGS = 4.5 V 0.02 0.01 0 Figure 3. On-Resistance versus Gate-To-Source Voltage 2 8 4 6 ID, DRAIN CURRENT (AMPS) 10 Figure 4. On-Resistance versus Drain Current and Gate Voltage 10,000 1.6 VGS = 0 V ID = 4.2 A VGS = 4.5 V 1.4 1.2 1 TJ = 150C 1000 TJ = 125C 0.8 0.6 -50 2.5 Figure 2. Transfer Characteristics IDSS, LEAKAGE (nA) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN-TO SOURCE-RESISTANCE (W) Figure 1. On-Region Characteristics 1 1.5 2 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 100 2 Figure 5. On-Resistance Variation with Temperature 4 8 14 16 18 6 10 12 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 20 Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 159 NTMS4N01R2 2500 VDS = 0 V VGS = 0 V C, CAPACITANCE (pF) Ciss TJ = 25C 2000 1500 Crss 1000 Ciss 500 Coss Crss 0 8 6 4 0 2 2 VGS VDS 4 6 10 8 12 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) 5 20 QT VGS 4 16 VDS 3 12 Q1 Q2 8 2 ID = 4.2 A TJ = 25C 1 4 0 0 0 2 4 6 8 10 12 Qg, TOTAL GATE CHARGE (nC) V DS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge 1000 1000 VDD = 10 V ID = 2.1 A VGS = 4.5 V td(off) tf tr 100 t, TIME (ns) t, TIME (ns) VDD = 10 V ID = 4.2 A VGS = 4.5 V tf 100 td(off) tr td(on) td(on) 10 10 1 10 100 1 10 100 RG, GATE RESISTANCE (OHMS) RG, GATE RESISTANCE (OHMS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Resistive Switching Time Variation versus Gate Resistance http://onsemi.com 160 NTMS4N01R2 DRAIN-TO-SOURCE DIODE CHARACTERISTICS 100 VGS = 0 V TJ = 25C ID , DRAIN CURRENT (AMPS) IS, SOURCE CURRENT (AMPS) 4 3 2 1 0 10 0.4 0.5 0.6 0.7 0.8 100 ms 1.0 ms 10 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT dc 0.1 Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10s max. 0.01 0.3 VGS = 20 V SINGLE PULSE TC = 25C 0.9 0.1 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 11. Diode Forward Voltage versus Current Figure 12. Maximum Rated Forward Biased Safe Operating Area di/dt IS ta trr tb TIME 0.25 IS tp IS Figure 13. Diode Reverse Recovery Waveform TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 2%* ## # #$8: # . #: . 4$: . :#4 9894 0.01 464 . 866 . SINGLE PULSE +%1' 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 t, TIME (s) Figure 14. Thermal Response http://onsemi.com 161 1.0E+01 1.0E+02 1.0E+03 NTMS4N01R2 INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 162 NTMS4N01R2 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 15. Typical Solder Heating Profile http://onsemi.com 163 # #$%& '( - P-Channel Enhancement-Mode Single SO-8 Package http://onsemi.com Features * High Density Power MOSFET with Ultra Low RDS(on) * * * * * Providing Higher Efficiency Miniature SO-8 Surface Mount Package - Saves Board Space Diode Exhibits High Speed with Soft Recovery IDSS Specified at Elevated Temperature Drain-to-Source Avalanche Energy Specified Mounting Information for the SO-8 Package is Provided -4.5 AMPERES -12 VOLTS 0.045 W @ VGS = -4.5 V Single P-Channel D Applications * Power Management in Portable and Battery-Powered Products, i.e.: Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones G MAXIMUM RATINGS Please See the Table on the Following Page S 8 1 SO-8 CASE 751 STYLE 13 MARKING DIAGRAM & PIN ASSIGNMENT N.C. Source Source Gate 1 8 2 7 3 E4P01 LYWW 4 6 5 Drain Drain Drain Drain Top View E4P01 L Y WW = Device Code = Assembly Location = Year = Work Week ORDERING INFORMATION Device NTMS4P01R2 Package Shipping SO-8 2500/Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2001 February, 2001 - Rev. 0 164 Publication Order Number: NTMS4P01R2/D NTMS4P01R2 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit -12 V Drain-to-Gate Voltage (RGS = 1.0 mW) VDSS VDGR -12 V Gate-to-Source Voltage - Continuous VGS 10 V Thermal Resistance - Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) RJA PD ID ID PD ID IDM 50 2.5 -6.04 -4.82 1.2 -4.18 -20 C/W W A A W A A Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) RJA PD ID ID PD ID IDM 85 1.47 -4.50 -3.65 0.7 -3.20 -15 C/W W A A W A A RJA PD ID ID PD ID IDM TJ, Tstg 159 0.79 -3.40 -2.72 0.38 -2.32 -12 C/W W A A W A A Rating Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C EAS (VDD = -12 Vdc, VGS = -5.0 Vdc, Peak IL = -8.0 Apk, L = 10 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 1. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. 2. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t = steady state. 3. Minimum FR-4 or G-10 PCB, t = Steady State. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. http://onsemi.com 165 -55 to +150 C 320 mJ 260 C NTMS4P01R2 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 5.) Characteristic Symbol Min Typ Max Unit -12 - - -15 - - - - - - -1.0 -10 - - -100 - - 100 -0.65 - -0.9 2.9 -1.15 - - - - 0.030 0.040 0.045 0.045 0.055 - gFS - 10 - Mhos Ciss - 1435 1850 pF Coss - 635 1000 Crss - 210 400 td(on) - 20 35 tr - 60 100 td(off) - 65 100 tf - 75 125 Qtot - 20 35 Qgs - 4.0 - Qgd - 7.0 - VSD - - -0.9 -0.7 -1.25 - Vdc trr - 38 - ns ta - 20 - tb - 18 - QRR - 0.03 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = -250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = -12 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = -12 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = -10 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +10 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-State Resistance (VGS = -4.5 Vdc, ID = -4.5 Adc) (VGS = -2.7 Vdc, ID = -2.25 Adc) (VGS = -2.5 Vdc, ID = -2.25 Adc) RDS(on) Forward Transconductance (VDS = -2.5 Vdc, ID = -2.25 Adc) Vdc mV/C DYNAMIC CHARACTERISTICS Input Capacitance (VDS = -9.6 9 6 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6. & 7.) Turn-On Delay Time (VDD = -12 Vdc, ID = -4.5 Adc, VGS = -4.5 4 5 Vdc, Vdc RG = 6.0 ) Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (VDS = -9.6 Vdc, VGS = -4.5 Vdc, ID = -4.5 4 5 Ad Adc)) Gate-Source Charge Gate-Drain Charge ns nC BODY-DRAIN DIODE RATINGS (Note 6.) Diode Forward On-Voltage (IS = -4.5 Adc, VGS = 0 V) (IS = -4.5 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = -4.5 4 5 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. http://onsemi.com 166 C NTMS4P01R2 -2.3 V 7 -2.1 V -4.5 V -3.7 V -3.1 V -2.7 V 6 5 4 TJ = 25C -ID, DRAIN CURRENT (AMPS) -ID, DRAIN CURRENT (AMPS) 8 -8 V -1.9 V -2.5 V 3 -1.7 V 2 1 0 VGS = -1.3 V 0 0.25 0.5 0.75 1 1.25 1.5 1.75 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 6 4 100C 25C 2 TJ = -55C 0 2 VDS -10 V 8 0.5 0.12 ID = -4.5 A TJ = 25C 0.09 0.06 0.03 0 0 2 4 6 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 8 RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) Figure 2. Transfer Characteristics 0.05 TJ = 25C VGS = -2.5 V 0.04 VGS = -2.7 V 0.03 VGS = -4.5 V 0.02 0.01 2 Figure 3. On-Resistance versus Gate-To-Source Voltage 8 4 6 -ID, DRAIN CURRENT (AMPS) Figure 4. On-Resistance versus Drain Current and Gate Voltage 10,000 1.6 VGS = 0 V 1.4 ID = -4.5 A VGS = -4.5 V -IDSS, LEAKAGE (nA) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) Figure 1. On-Region Characteristics 2.5 1 1.5 2 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 TJ = 150C 1000 TJ = 125C 100 2 Figure 5. On-Resistance Variation with Temperature 4 8 6 10 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 12 Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 167 4000 C, CAPACITANCE (pF) Ciss TJ = 25C 3000 Crss 2000 Ciss 1000 Coss Crss 0 10 8 6 4 2 2 0 -VGS -VDS 4 6 8 12 10 5 10 QT 8 4 -VDS 3 Q1 -VGS 6 Q2 4 2 ID = -4.5 A TJ = 25C 1 2 0 0 4 0 8 12 16 20 24 Qg, TOTAL GATE CHARGE (nC) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDS = 0 V VGS = 0 V -VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) NTMS4P01R2 Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 4 t, TIME (ns) VDD = -12 V ID = -4.5 A VGS = -4.5 V -IS, SOURCE CURRENT (AMPS) 1000 td(off) tf tr 100 td(on) 10 1 10 VGS = 0 V TJ = 25C 3 2 1 0 100 0.2 RG, GATE RESISTANCE (OHMS) 0.3 0.4 0.5 0.7 0.6 0.8 0.9 Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current DRAIN-TO-SOURCE DIODE CHARACTERISTICS ID , DRAIN CURRENT (AMPS) 100 10 VGS = 10 V SINGLE PULSE TC = 25C 1.0 ms 10 ms di/dt 1 IS RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.01 dc ta Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10s max. 0.1 1 1 -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) trr tb TIME 0.25 IS tp 10 100 IS VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Diode Reverse Recovery Waveform http://onsemi.com 168 NTMS4P01R2 TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 1 0.1 D = 0.5 0.2 0.1 0.05 2%* 0.02 0.01 94 9$# 788 4: . 998 . $$6 . 96 7$# 0.01 764: . :#69 . SINGLE PULSE +%1' 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 t, TIME (s) Figure 13. Thermal Response INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 169 NTMS4P01R2 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 14. Typical Solder Heating Profile http://onsemi.com 170 # #$%& '( - P-Channel Enhancement-Mode Single SO-8 Package http://onsemi.com Features * High Density Power MOSFET with Ultra Low RDS(on) * * * * * Providing Higher Efficiency Miniature SO-8 Surface Mount Package - Saves Board Space Diode Exhibits High Speed with Soft Recovery IDSS Specified at Elevated Temperature Drain-to-Source Avalanche Energy Specified Mounting Information for the SO-8 Package is Provided -5.4 AMPERES -20 VOLTS 0.033 W @ VGS = -4.5 V Single P-Channel D Applications * Power Management in Portable and Battery-Powered Products, i.e.: Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones G MAXIMUM RATINGS Please See the Table on the Following Page S 8 1 SO-8 CASE 751 STYLE 13 MARKING DIAGRAM & PIN ASSIGNMENT N.C. Source Source Gate 1 8 2 7 3 E5P02 LYWW 4 6 5 Drain Drain Drain Drain Top View E5P02 L Y WW = Device Code = Assembly Location = Year = Work Week ORDERING INFORMATION Device NTMS5P02R2 Package Shipping SO-8 2500/Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2001 February, 2001 - Rev. 0 171 Publication Order Number: NTMS5P02R2/D NTMS5P02R2 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit -20 V Drain-to-Gate Voltage (RGS = 1.0 mW) VDSS VDGR -20 V Gate-to-Source Voltage - Continuous VGS 10 V Thermal Resistance - Junction-to-Ambient (Note 1) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) RJA PD ID ID PD ID IDM 50 2.5 -7.05 -5.62 1.2 -4.85 -28 C/W W A A W A A Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) RJA PD ID ID PD ID IDM 85 1.47 -5.40 -4.30 0.7 -3.72 -20 C/W W A A W A A RJA PD ID ID PD ID IDM TJ, Tstg 159 0.79 -3.95 -3.15 0.38 -2.75 -12 C/W W A A W A A -55 to +150 C 360 mJ 260 C Rating Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C EAS (VDD = -20 Vdc, VGS = -5.0 Vdc, Peak IL = -8.5 Apk, L = 10 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 1. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. 2. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t = steady state. 3. Minimum FR-4 or G-10 PCB, t = Steady State. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. http://onsemi.com 172 NTMS5P02R2 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 5.) Characteristic Symbol Min Typ Max Unit -20 - - -15 - - - - - - - -0.2 -1.0 -10 - - - -100 - - 100 -0.65 - -0.9 2.9 -1.25 - - - 0.026 0.037 0.033 0.048 gFS - 15 - Mhos Ciss - 1375 1900 pF Coss - 510 900 Crss - 200 380 td(on) - 18 35 tr - 25 50 td(off) - 70 125 tf - 55 100 td(on) - 22 - tr - 70 - td(off) - 65 - tf - 90 - Qtot - 20 35 Qgs - 4.0 - Qgd - 7.0 - VSD - - -0.95 -0.72 -1.25 - Vdc trr - 40 75 ns ta - 20 - tb - 20 - QRR - 0.03 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = -250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = -16 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = -16 Vdc, VGS = 0 Vdc, TJ = 125C) (VDS = -20 Vdc, VGS = 0 Vdc, TJ = 25C) IDSS Gate-Body Leakage Current (VGS = -10 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +10 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-State Resistance (VGS = -4.5 Vdc, ID = -5.4 Adc) (VGS = -2.5 Vdc, ID = -2.7 Adc) RDS(on) Forward Transconductance (VDS = -9.0 Vdc, ID = -5.4 Adc) Vdc mV/C DYNAMIC CHARACTERISTICS Input Capacitance (VDS = -16 16 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6. & 7.) Turn-On Delay Time (VDD = -16 Vdc, ID = -1.0 Adc, VGS = -4.5 4 5 Vdc, Vdc RG = 6.0 ) Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time (VDD = -16 Vdc, ID = -5.4 Adc, VGS = -4.5 4 5 Vdc, Vdc RG = 6.0 ) Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (VDS = -16 Vdc, VGS = -4.5 Vdc, ID = -5.4 5 4 Ad Adc)) Gate-Source Charge Gate-Drain Charge ns ns nC BODY-DRAIN DIODE RATINGS (Note 6.) Diode Forward On-Voltage (IS = -5.4 Adc, VGS = 0 V) (IS = -5.4 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = -5.4 5 4 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. http://onsemi.com 173 C NTMS5P02R2 -8 V -2.3 V -4.5 V -3.7 V -3.1 V 10 12 TJ = 25C -ID, DRAIN CURRENT (AMPS) -ID, DRAIN CURRENT (AMPS) 12 -2.1 V 8 -2.7 V -2.5 V 6 -1.9 V 4 -1.7 V 2 0 VGS = -1.3 V 0 0.25 0.5 0.75 1 1.25 1.5 1.75 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDS -10 V 10 8 6 100C 4 1 ID = -5.4 A TJ = 25C 0.06 0.04 0.02 0 10 RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.08 8 2 4 6 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 2.5 1.5 2 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 3 Figure 2. Transfer Characteristics 0.05 TJ = 25C VGS = -2.5 V 0.04 VGS = -2.7 V 0.03 VGS = -4.5 V 0.02 0.01 2 Figure 3. On-Resistance versus Gate-To-Source Voltage 4 8 10 6 -ID, DRAIN CURRENT (AMPS) 12 Figure 4. On-Resistance versus Drain Current and Gate Voltage 10,000 1.6 VGS = 0 V 1.4 ID = -5.4 A VGS = -4.5 V -IDSS, LEAKAGE (nA) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) Figure 1. On-Region Characteristics 0 TJ = -55C 2 0 2 25C 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 TJ = 150C 1000 TJ = 125C 100 2 Figure 5. On-Resistance Variation with Temperature 4 8 14 16 18 20 6 10 12 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 174 4000 C, CAPACITANCE (pF) Ciss TJ = 25C 3000 Crss 2000 Ciss 1000 Coss Crss 0 10 5 0 5 10 20 15 -VGS -VDS 5 20 QT 4 -VGS -VDS 3 Q1 16 12 Q2 8 2 ID = -5.4 A TJ = 25C 1 4 0 0 4 0 8 12 16 20 24 Qg, TOTAL GATE CHARGE (nC) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDS = 0 V VGS = 0 V -VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) NTMS5P02R2 Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation t, TIME (ns) VDD = -16 V ID = -5.4 A VGS = -4.5 V -IS, SOURCE CURRENT (AMPS) 1000 td(off) tf tr 100 td(on) 10 1 10 5 4 3 2 1 0 100 VGS = 0 V TJ = 25C 0.2 RG, GATE RESISTANCE (OHMS) 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current DRAIN-TO-SOURCE DIODE CHARACTERISTICS ID , DRAIN CURRENT (AMPS) 100 VGS = 20 V SINGLE PULSE TC = 25C 1 ms 10 di/dt IS 10 ms 1 ta RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 trr tb TIME 0.25 IS tp dc 0.1 1 -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 10 100 IS VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Diode Reverse Recovery Waveform http://onsemi.com 175 NTMS5P02R2 TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 1 0.1 D = 0.5 0.2 0.1 0.05 2%* 0.02 0.01 94 9$# 788 4: . 998 . $$6 . 96 7$# 0.01 764: . :#69 . SINGLE PULSE +%1' 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 t, TIME (s) Figure 13. Thermal Response INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 176 NTMS5P02R2 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 14. Typical Solder Heating Profile http://onsemi.com 177 # (45 Power MOSFET and Schottky Diode Dual SO-8 Package Features * High Efficiency Components in a Single SO-8 Package * High Density Power MOSFET with Low RDS(on), http://onsemi.com Schottky Diode with Low VF MOSFET -2.3 AMPERES -20 VOLTS 90 mW @ VGS = -4.5 V * Logic Level Gate Drive * Independent Pin-Outs for MOSFET and Schottky Die Allowing for Flexibility in Application Use * Less Component Placement for Board Space Savings * SO-8 Surface Mount Package, Mounting Information for SO-8 Package Provided Applications * Power Management in Portable and Battery-Powered Products, i.e.: SCHOTTKY DIODE 2.0 AMPERES 20 VOLTS 580 mV @ IF = 2.0 A Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Symbol Value Unit VDSS VGS -20 V Gate-to-Source Voltage - Continuous "10 V Thermal Resistance - Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 100C Pulsed Drain Current (Note 4.) RJA PD ID ID IDM 175 0.71 -2.3 -1.45 -9.0 C/W W A A A Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 100C Pulsed Drain Current (Note 4.) Thermal Resistance - Junction-to-Ambient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 100C Pulsed Drain Current (Note 4.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = -20 Vdc, VGS = -4.5 Vdc, Peak IL = -5.0 Apk, L = 28 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds RJA PD ID ID IDM 105 1.19 -2.97 -1.88 -12 C/W W A A A RJA PD ID ID IDM TJ, Tstg 62.5 2.0 -3.85 -2.43 -15 C/W W A A A -55 to +150 C EAS TL 350 8 1 SO-8 CASE 751 STYLE 18 C 1. Minimum FR-4 or G-10 PCB, Steady State. 2. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. 3. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. 8 # : 9 4 6 $ / MARKING DIAGRAM & PIN ASSIGNMENTS Anode Anode Source Gate 1 8 2 7 3 E2P102 LYWW 4 6 5 Cathode Cathode Drain Drain (Top View) mJ 260 E2P102 L Y WW = Device Code = Assembly Location = Year = Work Week ORDERING INFORMATION Device Package Shipping NTMSD2P102LR2 SO-8 2500/Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 1 178 Publication Order Number: NTMSD2P102LR2/D NTMSD2P102LR2 SCHOTTKY MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit VRRM VR IO 20 V 1.0 A Peak Repetitive Forward Current (Note 5.) (Rated VR, Square Wave, 20 kHz, TA = 105C) IFRM 2.0 A Non-Repetitive Peak Surge Current (Note 5.) (Surge Applied at Rated Load Conditions, Half-Wave, Single Phase, 60 Hz) IFSM 20 A Rating Peak Repetitive Reverse Voltage DC Blocking Voltage Average Forward Current (Note 5.) (Rated VR, TA = 100C) ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 6.) Symbol Characteristic Min Typ Max -20 - - -12.7 - - - - - - -1.0 -25 - - -2.0 - - -100 - - 100 -0.5 - -0.90 2.5 -1.5 - - - - 0.070 0.100 0.110 0.090 0.130 0.150 - 4.2 - Ciss - 550 750 Coss - 200 300 Crss - 100 175 Unit OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = -250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = -16 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = -16 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = -20 Vdc, TJ = 25C) IDSS Gate-Body Leakage Current (VGS = -10 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +10 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-State Resistance (VGS = -4.5 Vdc, ID = -2.4 Adc) (VGS = -2.7 Vdc, ID = -1.2 Adc) (VGS = -2.5 Vdc, ID = -1.2 Adc) RDS(on) Forward Transconductance (VDS = -10 Vdc, ID = -1.2 Adc) Vdc mV/C gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = -16 16 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Reverse Transfer Capacitance 5. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. 6. Handling precautions to protect against electrostatic discharge is mandatory. http://onsemi.com 179 pF NTMSD2P102LR2 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (continued) (Note 7.) Characteristic Symbol Min Typ Max Unit td(on) - 10 20 ns tr - 35 65 td(off) - 33 60 SWITCHING CHARACTERISTICS (Notes 8. & 9.) Turn-On Delay Time (VDD = -10 Vdc, ID = -2.4 Adc, 4 5 Vdc, Vdc VGS = -4.5 RG = 6.0 ) Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time (VDD = -10 Vdc, ID = -1.2 Adc, VGS = -2.7 2 7 Vdc, Vdc RG = 6.0 ) Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (VDS = -16 Vdc, VGS = -4.5 Vdc, ID = -2.4 2 4 Ad Adc)) Gate-Source Charge Gate-Drain Charge tf - 29 55 td(on) - 15 - tr - 40 - td(off) - 35 - tf - 35 - Qtot - 10 18 ns nC Qgs - 1.5 - Qgd - 5.0 - VSD - - -0.88 -0.75 -1.0 - Vdc trr - 37 - ns ta - 16 - tb - 21 - QRR - 0.025 - BODY-DRAIN DIODE RATINGS (Note 8.) Diode Forward On-Voltage (IS = -2.4 Adc, VGS = 0 Vdc) (IS = -2.4 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = -2.4 2 4 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge C SCHOTTKY RECTIFIER ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 8.) VF g Maximum Instantaneous Forward Voltage IF = 1.0 1 0 Ad Adc IF = 2.0 Adc IR Maximum Instantaneous Reverse Current Vd VR = 20 Vdc Maximum Voltage Rate of Change VR = 20 Vdc 7. Handling precautions to protect against electrostatic discharge is mandatory. 8. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 9. Switching characteristics are independent of operating junction temperature. http://onsemi.com 180 dV/dt TJ = 25C TJ = 125C 0.47 0.58 0.39 0.53 TJ = 25C TJ = 125C 0.05 10 10,000 Volts mA V/ms NTMSD2P102LR2 5 4 VGS = -10 V VGS = -4.5 V VGS = -2.5 V 3 TJ = 25C -ID, DRAIN CURRENT (AMPS) -ID, DRAIN CURRENT (AMPS) VGS = -2.1 V VGS = -1.9 V 2 VGS = -1.7 V 1 VGS = -1.5 V 3 2 TJ = 25C 1 TJ = 100C 0 2 4 6 8 1 10 3 2.5 Figure 2. Transfer Characteristics. RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) Figure 1. On-Region Characteristics. 0.15 0.1 0.05 0 2 4 6 8 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 0.12 TJ = 25C 0.1 VGS = -2.7 V 0.08 VGS = -4.5 V 0.06 0.04 1 1.5 2 2.5 3 3.5 4 4.5 -ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Gate-to-Source Voltage. Figure 4. On-Resistance vs. Drain Current and Gate Voltage. 1.6 1000 VGS = 0 V ID = -2.4 A VGS = -4.5 V TJ = 125C -IDSS, LEAKAGE (nA) 100 1.2 1 0.8 0.6 -50 2 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C 1.4 1.5 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.2 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) TJ = 55C 0 0 RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) VDS > = -10 V 4 TJ = 100C 10 TJ = 25C 1 0.1 0.01 -25 0 25 75 50 100 125 TJ, JUNCTION TEMPERATURE (C) 150 0 Figure 5. On-Resistance Variation with Temperature. 4 8 12 16 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 6. Drain-to-Source Leakage Current vs. Voltage. http://onsemi.com 181 20 C, CAPACITANCE (pF) VDS = 0 V 1200 VGS = 0 V Ciss TJ = 25C 900 Crss Ciss 600 300 Coss Crss 0 10 5 0 -VGS -VDS 5 10 15 20 5 20 18 QT 16 4 14 3 12 VGS Q1 10 Q2 8 2 6 1 ID = -2.4 A TJ = 25C VDS 4 2 0 0 2 0 4 6 12 10 8 14 Qg, TOTAL GATE CHARGE (nC) GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1500 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) NTMSD2P102LR2 Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge Figure 7. Capacitance Variation 1000 100 td (off) tr t, TIME (ns) t, TIME (ns) VDD = -10 V ID = -1.2 A VGS = -2.7 V 100 tr VDD = -10 V ID = -2.4 A VGS = -4.5 V td (on) 1.0 10 10 1.0 td (on) 10 tf td (off) tf 100 RG, GATE RESISTANCE (OHMS) 1.0 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Resistive Switching Time Variation versus Gate Resistance -IS, SOURCE CURRENT (AMPS) 2 1.6 VGS = 0 V TJ = 25C di/dt IS 1.2 ta trr tb TIME 0.8 0.25 IS tp IS 0.4 0 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 12. Diode Reverse Recovery Waveform -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 11. Diode Forward Voltage versus Current http://onsemi.com 182 NTMSD2P102LR2 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE 1 D = 0.5 0.2 0.1 Normalized to Rja at Steady State (1 inch pad) 0.1 0.0125 0.0563 0.110 0.273 0.113 0.436 2.93 F 152 F 261 F 0.05 0.02 0.01 0.021 F 0.137 F 1.15 F Single Pulse 0.01 1E-03 1E-02 1E-01 1E+00 1E+03 1E+02 1E+03 t, TIME (s) Figure 13. FET Thermal Response TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS 10 IF, INSTANTANEOUS FORWARD CURRENT (AMPS) IF, INSTANTANEOUS FORWARD CURRENT (AMPS) 10 TJ = 125C 1.0 85C 25C -40C 0.1 TJ = 125C 85C 1.0 25C 0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS) 0.2 0.4 0.6 0.8 1.0 1.2 VF, MAXIMUM INSTANTANEOUS FORWARD VOLTAGE (VOLTS) Figure 14. Typical Forward Voltage Figure 15. Maximum Forward Voltage http://onsemi.com 183 1.4 NTMSD2P102LR2 IR , REVERSE CURRENT (AMPS) 1E-2 TJ = 125C 1E-3 85C 1E-4 1E-5 25C 1E-6 1E-7 0 5.0 15 10 20 IR, MAXIMUM REVERSE CURRENT (AMPS) TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS 1E-1 TJ = 125C 1E-2 1E-3 1E-4 25C 1E-5 1E-6 0 5.0 VR, REVERSE VOLTAGE (VOLTS) 100 10 10 15 20 1.6 dc FREQ = 20 kHz 1.4 1.2 SQUARE WAVE 1.0 Ipk/Io = p 0.8 Ipk/Io = 5.0 0.6 Ipk/Io = 10 0.4 Ipk/Io = 20 0.2 0 0 20 VR, REVERSE VOLTAGE (VOLTS) 40 60 Ipk/Io = p 0.5 dc SQUARE WAVE Ipk/Io = 5.0 0.4 Ipk/Io = 10 Ipk/Io = 20 0.3 0.2 0.1 0 0 0.5 100 120 Figure 19. Current Derating 0.7 0.6 80 TA, AMBIENT TEMPERATURE (C) Figure 18. Typical Capacitance PFO, AVERAGE POWER DISSIPATION (WATTS) C, CAPACITANCE (pF) TYPICAL CAPACITANCE AT 0 V = 170 pF IO, AVERAGE FORWARD CURRENT (AMPS) Figure 17. Maximum Reverse Current 1000 5.0 20 VR, REVERSE VOLTAGE (VOLTS) Figure 16. Typical Reverse Current 0 15 10 1.0 1.5 IO, AVERAGE FORWARD CURRENT (AMPS) Figure 20. Forward Power Dissipation http://onsemi.com 184 2.0 140 160 NTMSD2P102LR2 TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0 D = 0.5 0.2 0.1 0.1 NORMALIZED TO RqJA AT STEADY STATE (1 PAD) 0.05 0.02 4 W , 6 . 0.01 0.01 $6 W $# W 6$:$ W 4:7 W 8# . $# . SINGLE PULSE #:6 . $896 . = 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 Figure 21. Schottky Thermal Response http://onsemi.com 185 1.0E+01 1.0E+02 1.0E+03 NTMSD2P102LR2 INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 inches mm #6 9 $ #: SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 186 NTMSD2P102LR2 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 22 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 22. Typical Solder Heating Profile http://onsemi.com 187 !# (45 P-Channel Enhancement-Mode Power MOSFET and Schottky Diode Dual SO-8 Package http://onsemi.com Features * High Efficiency Components in a Single SO-8 Package * High Density Power MOSFET with Low RDS(on), MOSFET -3.05 AMPERES -20 VOLTS 0.085 W @ VGS = -10 V Schottky Diode with Low VF * Independent Pin-Outs for MOSFET and Schottky Die Allowing for Flexibility in Application Use * Less Component Placement for Board Space Savings * SO-8 Surface Mount Package, Mounting Information for SO-8 Package Provided SCHOTTKY DIODE 1.0 AMPERES 20 VOLTS 470 mV @ IF = 1.0 A Applications * DC-DC Converters * Low Voltage Motor Control * Power Management in Portable and Battery-Powered Products, i.e.: Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Value Unit VDSS VGS -20 V "20 V RJA PD ID ID IDM 171 0.73 -2.34 -1.87 -8.0 C/W W A A A Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) RJA PD ID ID IDM 100 1.25 -3.05 -2.44 -12 C/W W A A A 62.5 2.0 -3.86 -3.10 -15 C/W W A A A -55 to +150 C 140 mJ Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = -20 Vdc, VGS = -4.5 Vdc, Peak IL = -7.5 Apk, L = 5 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 8 1 Thermal Resistance - Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) Thermal Resistance - Junction-to-Ambient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) 1. 2. 3. 4. Symbol RJA PD ID ID IDM TJ, Tstg EAS SO-8 CASE 751 STYLE 18 8 # : 9 4 6 $ / MARKING DIAGRAM & PIN ASSIGNMENTS Anode Anode Source Gate 1 8 2 7 3 E3P102 LYWW 4 6 5 Cathode Cathode Drain Drain (Top View) E3P102 L Y WW = Device Code = Assembly Location = Year = Work Week ORDERING INFORMATION Device TL C 260 NTMSD3P102R2 Package Shipping SO-8 2500/Tape & Reel Minimum FR-4 or G-10 PCB, Steady State. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2001 January, 2001 - Rev. 0 188 Publication Order Number: NTMSD3P102R2/D NTMSD3P102R2 SCHOTTKY MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit 20 V Thermal Resistance - Junction-to-Ambient (Note 5.) VRRM VR RJA 204 C/W Thermal Resistance - Junction-to-Ambient (Note 6.) RJA 122 C/W Thermal Resistance - Junction-to-Ambient (Note 7.) RJA 83 C/W IO 1.0 A Peak Repetitive Forward Current (Note 7.) (Rated VR, Square Wave, 20 kHz, TA = 105C) IFRM 2.0 A Non-Repetitive Peak Surge Current (Note 7.) (Surge Applied at Rated Load Conditions, Half-Wave, Single Phase, 60 Hz) IFSM 20 A Rating Peak Repetitive Reverse Voltage DC Blocking Voltage Average Forward Current (Note 7.) (Rated VR, TA = 100C) ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 8.) Symbol Characteristic Min Typ Max -20 - - -30 - - - - - - -1.0 -25 - - -100 - - 100 -1.0 - -1.7 3.6 -2.5 - - - 0.063 0.090 0.085 0.125 - 5.0 - Ciss - 518 750 Coss - 190 350 Crss - 70 135 Unit OFF CHARACTERISTICS V(BR)DSS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = -250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = -20 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = -20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = -20 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-State Resistance (VGS = -10 Vdc, ID = -3.05 Adc) (VGS = -4.5 Vdc, ID = -1.5 Adc) RDS(on) Forward Transconductance (VDS = -15 Vdc, ID = -3.05 Adc) Vdc gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = -16 16 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Reverse Transfer Capacitance 5. 6. 7. 8. Minimum FR-4 or G-10 PCB, Steady State. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. Handling precautions to protect against electrostatic discharge is mandatory. http://onsemi.com 189 pF NTMSD3P102R2 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 9.) Characteristic Symbol Min Typ Max Unit td(on) - 12 22 ns tr - 16 30 td(off) - 45 80 SWITCHING CHARACTERISTICS (Notes 10. & 11.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = -20 Vdc, ID = -3.05 Adc, 10 Vdc, Vdc VGS = -10 RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = -20 Vdc, ID = -1.5 Adc, VGS = -4.5 4 5 Vdc, Vdc RG = 6.0 ) Fall Time Total Gate Charge (VDS = -20 Vdc, VGS = -10 Vdc, ID = -3.05 3 05 Adc) Ad ) Gate-Source Charge Gate-Drain Charge tf - 45 80 td(on) - 16 - tr - 42 - td(off) - 32 - tf - 35 - Qtot - 16 25 ns nC Qgs - 2.0 - Qgd - 4.5 - VSD - - -0.96 -0.78 -1.25 - Vdc trr - 34 - ns ta - 18 - tb - 16 - QRR - 0.03 - BODY-DRAIN DIODE RATINGS (Note 10.) Diode Forward On-Voltage (IS = -3.05 Adc, VGS = 0 Vdc) (IS = -3.05 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = -3.05 3 05 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge C SCHOTTKY RECTIFIER ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 10.) VF g Maximum Instantaneous Forward Voltage IF = 1.0 1 0 Ad Adc IF = 2.0 Adc IR Maximum Instantaneous Reverse Current Vd VR = 20 Vdc Maximum Voltage Rate of Change VR = 20 Vdc 9. Handling precautions to protect against electrostatic discharge is mandatory. 10. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 11. Switching characteristics are independent of operating junction temperature. http://onsemi.com 190 dV/dt TJ = 25C TJ = 125C 0.47 0.58 0.39 0.53 TJ = 25C TJ = 125C 0.05 10 10,000 Volts mA V/ms NTMSD3P102R2 TYPICAL MOSFET ELECTRICAL CHARACTERISTICS -ID, DRAIN CURRENT (AMPS) VGS = -4 V VGS = -4.6 V VGS = -6 V 4 VGS = -4.8 V TJ = 25C 3 VGS 2 VGS = -3.6 V VGS = -2.8 V VGS = -3.2 V = -5 V VGS = -2.6 V VGS = -3 V 1 0 0.25 0.5 0.75 1 1.25 1.5 1.75 TJ = 25C 2 TJ = -55C 1 1 2 3 4 5 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics ID = -3.05 A TJ = 25C 0.5 0.4 0.3 0.2 0.1 5 4 6 7 8 0.7 ID = -1.5 A TJ = 25C 0.6 0.5 0.4 0.3 0.2 0.1 0 2 4 3 5 6 7 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 3. On-Resistance vs. Gate-to-Source Voltage Figure 4. On-Resistance vs. Gate-to-Source Voltage 0.25 TJ = 25C 0.2 VGS = -4.5 V 0.15 VGS = -10 V 0.1 0.05 1 TJ = 100C 3 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 0.6 3 4 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.7 0 VDS > = -10 V 5 0 2 2 3 4 5 6 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN-TO-SOURCE RESISTANCE () VGS = -4.4 V VGS = -8 V 5 0 RDS(on), DRAIN-TO-SOURCE RESISTANCE () 6 VGS = -10 V RDS(on), DRAIN-TO-SOURCE RESISTANCE () -ID, DRAIN CURRENT (AMPS) 6 1.6 1.4 ID = -3.05 A VGS = -10 V 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 125 -ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (C) Figure 5. On-Resistance vs. Drain Current and Gate Voltage Figure 6. On Resistance Variation with Temperature http://onsemi.com 191 150 NTMSD3P102R2 10000 VDS = 0 V 1200 C, CAPACITANCE (pF) IDSS, LEAKAGE (nA) VGS = 0 V TJ = 150C 1000 TJ = 125C 100 VGS = 0 V Ciss 1000 800 Ciss Crss 600 Coss 400 Crss 200 TJ = 25C 0 10 10 4 8 6 12 10 16 14 18 20 0 5 10 -VDS 15 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Drain-to-Source Leakage Current vs. Voltage Figure 8. Capacitance Variation 20 24 1000 12 QT 10 VDS = -20 V ID = -3.05 A VGS = -10 V 20 VDS 8 16 100 VGS 12 6 Q1 4 tr 4 ID = -3.05 A TJ = 25C 0 2 4 6 8 10 12 0 16 14 1 10 1 100 Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE () Figure 9. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge Figure 10. Resistive Switching Time Variation vs. Gate Resistance 3 100 tr tf 1 10 IS, SOURCE CURRENT (AMPS) VDS = -20 V ID = -1.5 A VGS = -4.5 V 10 tf td(on) 2 0 td(off) 10 8 Q2 1000 t, TIME (ns) 5 -VGS t, TIME (ns) -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 2 td(off) td(on) 100 VGS = 0 V TJ = 25C 2.5 2 1.5 1 0.5 0 0.2 0.4 0.6 0.8 1 RG, GATE RESISTANCE () -VSD, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 11. Resistive Switching Time Variation vs. Gate Resistance Figure 12. Diode Forward Voltage vs. Current http://onsemi.com 192 1.2 NTMSD3P102R2 di/dt IS ta trr tb TIME 0.25 IS tp IS Figure 13. Diode Reverse Recovery Waveform Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE 1.0 D = 0.5 0.2 0.1 0.1 Normalized to RJA at Steady State (1 pad) Chip Junction 2.32 18.5 50.9 37.1 56.8 0.05 0.02 0.01 1E-03 0.0014 F 0.01 0.0073 F 0.022 F 0.105 F 0.484 F 3.68 F Ambient Single Pulse 1E-02 24.4 1E-01 1E+00 1E+01 t, TIME (s) Figure 14. FET Thermal Response http://onsemi.com 193 1E+02 1E+03 NTMSD3P102R2 TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS 10 IF, INSTANTANEOUS FORWARD CURRENT (AMPS) IF, INSTANTANEOUS FORWARD CURRENT (AMPS) 10 TJ = 125C 1.0 85C 25C -40C 0.1 TJ = 125C 85C 1.0 25C 0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.2 VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS) 85C 1E-4 1E-5 25C 1E-6 1E-7 15 20 IR, MAXIMUM REVERSE CURRENT (AMPS) IR , REVERSE CURRENT (AMPS) TJ = 125C 1E-3 10 1E-3 1E-4 25C 1E-5 1E-6 0 5.0 100 10 20 IO, AVERAGE FORWARD CURRENT (AMPS) C, CAPACITANCE (pF) 15 10 20 Figure 18. Maximum Reverse Current TYPICAL CAPACITANCE AT 0 V = 170 pF 15 1.4 VR, REVERSE VOLTAGE (VOLTS) 1000 10 1.2 TJ = 125C 1E-2 Figure 17. Typical Reverse Current 5.0 1.0 1E-1 VR, REVERSE VOLTAGE (VOLTS) 0 0.8 Figure 16. Maximum Forward Voltage 1E-2 5.0 0.6 VF, MAXIMUM INSTANTANEOUS FORWARD VOLTAGE (VOLTS) Figure 15. Typical Forward Voltage 0 0.4 1.6 dc FREQ = 20 kHz 1.4 1.2 SQUARE WAVE 1.0 Ipk/Io = p 0.8 Ipk/Io = 5.0 0.6 Ipk/Io = 10 0.4 Ipk/Io = 20 0.2 0 0 VR, REVERSE VOLTAGE (VOLTS) 20 40 60 80 100 120 TA, AMBIENT TEMPERATURE (C) Figure 19. Typical Capacitance Figure 20. Current Derating http://onsemi.com 194 140 160 NTMSD3P102R2 PFO, AVERAGE POWER DISSIPATION (WATTS) TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS 0.7 0.6 Ipk/Io = p 0.5 dc SQUARE WAVE Ipk/Io = 5.0 0.4 Ipk/Io = 10 Ipk/Io = 20 0.3 0.2 0.1 0 0 0.5 1.0 1.5 2.0 IO, AVERAGE FORWARD CURRENT (AMPS) Figure 21. Forward Power Dissipation Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0 D = 0.5 0.2 0.1 0.1 NORMALIZED TO RqJA AT STEADY STATE (1 PAD) 0.05 0.02 4 W , 6 . 0.01 0.01 $6 W $# W 6$:$ W 4:7 W 8# . $# . SINGLE PULSE #:6 . $896 . = 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 Figure 22. Schottky Thermal Response http://onsemi.com 195 1.0E+01 1.0E+02 1.0E+03 NTMSD3P102R2 INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 196 NTMSD3P102R2 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 23 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 23. Typical Solder Heating Profile http://onsemi.com 197 !#!! (45 P-Channel Enhancement-Mode Power MOSFET and Schottky Diode Dual SO-8 Package http://onsemi.com Features * High Efficiency Components in a Single SO-8 Package * High Density Power MOSFET with Low RDS(on), MOSFET -3.05 AMPERES -30 VOLTS 0.085 W @ VGS = -10 V Schottky Diode with Low VF * Independent Pin-Outs for MOSFET and Schottky Die Allowing for Flexibility in Application Use * Less Component Placement for Board Space Savings * SO-8 Surface Mount Package, Mounting Information for SO-8 Package Provided SCHOTTKY DIODE 3.0 AMPERES 30 VOLTS 420 mV @ IF = 3.0 A Applications * DC-DC Converters * Low Voltage Motor Control * Power Management in Portable and Battery-Powered Products, i.e.: Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Value Unit VDSS VGS -30 V "20 V RJA PD ID ID IDM 171 0.73 -2.34 -1.87 -8.0 C/W W A A A Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) RJA PD ID ID IDM 100 1.25 -3.05 -2.44 -12 C/W W A A A 62.5 2.0 -3.86 -3.10 -15 C/W W A A A -55 to +150 C 140 mJ Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = -30 Vdc, VGS = -4.5 Vdc, Peak IL = -7.5 Apk, L = 5 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 8 1 Thermal Resistance - Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) Thermal Resistance - Junction-to-Ambient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) 1. 2. 3. 4. Symbol RJA PD ID ID IDM TJ, Tstg EAS SO-8 CASE 751 STYLE 18 8 # : 9 4 6 $ / MARKING DIAGRAM & PIN ASSIGNMENTS Anode Anode Source Gate 1 8 2 7 3 E3P303 LYWW 4 6 5 Cathode Cathode Drain Drain (Top View) E3P303 L Y WW = Device Code = Assembly Location = Year = Work Week ORDERING INFORMATION Device TL C 260 NTMSD3P303R2 Package Shipping SO-8 2500/Tape & Reel Minimum FR-4 or G-10 PCB, Steady State. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2001 January, 2001 - Rev. 0 198 Publication Order Number: NTMSD3P303R2/D NTMSD3P303R2 SCHOTTKY MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit 30 V Thermal Resistance - Junction-to-Ambient (Note 5.) VRRM VR RJA 197 C/W Thermal Resistance - Junction-to-Ambient (Note 6.) RJA 97 C/W Thermal Resistance - Junction-to-Ambient (Note 7.) RJA 62.5 C/W IO 3.0 A Peak Repetitive Forward Current (Note 7.) (Rated VR, Square Wave, 20 kHz, TA = 105C) IFRM 6.0 A Non-Repetitive Peak Surge Current (Note 7.) (Surge Applied at Rated Load Conditions, Half-Wave, Single Phase, 60 Hz) IFSM 30 A Unit Rating Peak Repetitive Reverse Voltage DC Blocking Voltage Average Forward Current (Note 7.) (Rated VR, TA = 100C) ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 8.) Symbol Min Typ Max -30 - - -30 - - - - - - -1.0 -25 - - -100 - - 100 -1.0 - -1.7 3.6 -2.5 - - - 0.063 0.090 0.085 0.125 - 5.0 - Ciss - 520 750 Coss - 170 325 Crss - Minimum FR-4 or G-10 PCB, Steady State. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. Handling precautions to protect against electrostatic discharge is mandatory. 70 135 Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = -250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = -30 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = -30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = -20 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-State Resistance (VGS = -10 Vdc, ID = -3.05 Adc) (VGS = -4.5 Vdc, ID = -1.5 Adc) RDS(on) Forward Transconductance (VDS = -15 Vdc, ID = -3.05 Adc) Vdc gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = -24 24 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Reverse Transfer Capacitance 5. 6. 7. 8. http://onsemi.com 199 pF NTMSD3P303R2 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 9.) Characteristic Symbol Min Typ Max Unit td(on) - 12 22 ns tr - 16 30 td(off) - 45 80 SWITCHING CHARACTERISTICS (Notes 10. & 11.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = -24 Vdc, ID = -3.05 Adc, 10 Vdc, Vdc VGS = -10 RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = -24 Vdc, ID = -1.5 Adc, VGS = -4.5 4 5 Vdc, Vdc RG = 6.0 ) Fall Time Total Gate Charge (VDS = -24 Vdc, VGS = -10 Vdc, ID = -3.05 3 05 Adc) Ad ) Gate-Source Charge Gate-Drain Charge tf - 45 80 td(on) - 16 - tr - 42 - td(off) - 32 - tf - 35 - Qtot - 16 25 ns nC Qgs - 2.0 - Qgd - 4.5 - VSD - - -0.96 -0.78 -1.25 - Vdc trr - 34 - ns ta - 18 - tb - 16 - QRR - 0.03 - BODY-DRAIN DIODE RATINGS (Note 10.) Diode Forward On-Voltage (IS = -3.05 Adc, VGS = 0 Vdc) (IS = -3.05 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = -3.05 3 05 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge C SCHOTTKY RECTIFIER ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 10.) VF Maximum Instantaneous Forward Voltage IF = 100 mAdc IF = 3.0 Adc IF = 6.0 Adc IR Maximum Instantaneous Reverse Current VR = 30 Vdc Vd TJ = 25C TJ = 125C 0.28 0.42 0.50 0.13 0.33 0.45 TJ = 25C TJ = 125C 250 25 Maximum Voltage Rate of Change VR = 30 Vdc 9. Handling precautions to protect against electrostatic discharge is mandatory. 10. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 11. Switching characteristics are independent of operating junction temperature. http://onsemi.com 200 dV/dt 10,000 Volts mA mA V/ms NTMSD3P303R2 TYPICAL MOSFET ELECTRICAL CHARACTERISTICS -ID, DRAIN CURRENT (AMPS) VGS = -4 V VGS = -4.6 V VGS = -6 V 4 VGS = -4.8 V TJ = 25C 3 VGS 2 VGS = -3.6 V VGS = -2.8 V VGS = -3.2 V = -5 V VGS = -2.6 V VGS = -3 V 1 0 0.25 0.5 0.75 1 1.25 1.5 1.75 TJ = 25C 2 TJ = -55C 1 1 2 3 4 5 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics ID = -3.05 A TJ = 25C 0.5 0.4 0.3 0.2 0.1 5 4 6 7 8 0.7 ID = -1.5 A TJ = 25C 0.6 0.5 0.4 0.3 0.2 0.1 0 2 4 3 5 6 7 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 3. On-Resistance vs. Gate-to-Source Voltage Figure 4. On-Resistance vs. Gate-to-Source Voltage 0.25 TJ = 25C 0.2 VGS = -4.5 V 0.15 VGS = -10 V 0.1 0.05 1 TJ = 100C 3 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 0.6 3 4 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.7 0 VDS > = -10 V 5 0 2 2 3 4 5 6 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN-TO-SOURCE RESISTANCE () VGS = -4.4 V VGS = -8 V 5 0 RDS(on), DRAIN-TO-SOURCE RESISTANCE () 6 VGS = -10 V RDS(on), DRAIN-TO-SOURCE RESISTANCE () -ID, DRAIN CURRENT (AMPS) 6 1.6 1.4 ID = -3.05 A VGS = -10 V 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 125 -ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (C) Figure 5. On-Resistance vs. Drain Current and Gate Voltage Figure 6. On Resistance Variation with Temperature http://onsemi.com 201 150 NTMSD3P303R2 10000 VDS = 0 V 1200 C, CAPACITANCE (pF) IDSS, LEAKAGE (nA) VGS = 0 V TJ = 150C 1000 TJ = 125C 100 VGS = 0 V Ciss 1000 800 Ciss Crss 600 400 Coss 200 Crss TJ = 25C 10 14 18 22 26 0 10 30 0 5 -VDS 10 15 20 25 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Drain-to-Source Leakage Current vs. Voltage Figure 8. Capacitance Variation 30 30 1000 12 QT 10 VDS = -24 V ID = -3.05 A VGS = -10 V 25 VDS 20 8 100 VGS 15 6 Q1 4 td(off) tf tr 10 10 Q2 td(on) 5 2 0 ID = -3.05 A TJ = 25C 0 2 4 6 8 10 12 0 16 14 1 100 RG, GATE RESISTANCE () Figure 9. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge Figure 10. Resistive Switching Time Variation vs. Gate Resistance 3 100 tr tf 1 10 IS, SOURCE CURRENT (AMPS) VDS = -24 V ID = -1.5 A VGS = -4.5 V 10 10 1 Qg, TOTAL GATE CHARGE (nC) 1000 t, TIME (ns) 5 -VGS t, TIME (ns) -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 6 td(off) td(on) 100 VGS = 0 V TJ = 25C 2.5 2 1.5 1 0.5 0 0.2 0.4 0.6 0.8 1 RG, GATE RESISTANCE () -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 11. Resistive Switching Time Variation vs. Gate Resistance Figure 12. Diode Forward Voltage vs. Current http://onsemi.com 202 1.2 NTMSD3P303R2 VGS = 12 V SINGLE PULSE TA = 25C 10 1.0 ms di/dt 10 ms IS dc 1.0 ta 0.01 trr tb TIME 0.1 RDS(on) THERMAL LIMIT PACKAGE LIMIT 1 1.0 0.25 IS tp 10 IS 100 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 13. Maximum Rated Forward Biased Safe Operating Area Figure 14. Diode Reverse Recovery Waveform 1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE -ID, DRAIN CURRENT (AMPS) 100 D = 0.5 0.2 0.1 0.1 Normalized to RJA at Steady State (1 pad) Chip Junction 2.32 18.5 50.9 37.1 56.8 0.05 0.02 0.01 1E-03 0.0014 F 0.01 0.0073 F 0.022 F 0.105 F 0.484 F 3.68 F Ambient Single Pulse 1E-02 24.4 1E-01 1E+00 t, TIME (s) Figure 15. FET Thermal Response http://onsemi.com 203 1E+01 1E+02 1E+03 NTMSD3P303R2 8$ ?6 , " #$ #$ # 4 6 $ 9 : 8$ , " #$ # 6 $ 9 : Figure 17. Maximum Forward Voltage , " #$ 8$ #$ 8 , " #$ #$ $ $ # #$ 4 $ . / $ $ # # #$ 4 Figure 19. Maximum Reverse Current $ Figure 18. Typical Reverse Current *. 4 Figure 16. Typical Forward Voltage #$ . > . / > . . / . . / . . / TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS #$ 4 $ 6$ . @ " # 0A 6 @ / 4$ 4 pk/Io = p #$ # Ipk/Io = 5.0 $ Ipk/Io = 10 Ipk/Io = 20 $ # 6 9 8 # = Figure 20. Typical Capacitance Figure 21. Current Derating http://onsemi.com 204 6 9 NTMSD3P303R2 . / / TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS :$ $ #$ @ / *0& " p *0& " $ *0& " :$ *0& " # $ #$ # 4 $ 6 . / Figure 22. Forward Power Dissipation '23)'.. " $ # < q, - $ # W , 476## m. #9:6 W #:78: W 4749 W 4974 W 674#9 m. 4 . ##7# . ##9: . $ 6 = 4 # ' ! 5 Figure 23. Schottky Thermal Response http://onsemi.com 205 5 5# 54 NTMSD3P303R2 INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 206 NTMSD3P303R2 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 24 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 24. Typical Solder Heating Profile http://onsemi.com 207 # " #$%& '( " N-Channel TO-220 http://onsemi.com Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. 27 AMPERES 60 VOLTS RDS(on) = 46 m Features * * * * * * * * Higher Current Rating Lower RDS(on) Lower VDS(on) Lower Capacitances Lower Total Gate Charge Tighter VSD Specification Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge N-Channel D G Typical Applications * * * * Power Supplies Converters Power Motor Controls Bridge Circuits S MARKING DIAGRAM & PIN ASSIGNMENT MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 60 Vdc Drain-to-Gate Voltage (RGS = 10 M) VDGR 60 Vdc VGS VGS 20 30 Rating Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) Drain Current - Continuous @ TA = 25C - Continuous @ TA = 100C - Single Pulse (tp 10 s) 1 27 15 80 Adc PD 88.2 0.59 W W/C Operating and Storage Temperature Range TJ, Tstg -55 to 175 C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 50 Vdc, VGS = 10 Vdc, L = 0.3 mH, IL(pk) = 27 A, VDS = 60 Vdc) EAS Thermal Resistance - Junction-to-Case RJC 1.7 C/W TL 260 C Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds TO-220AB CASE 221A STYLE 5 Vdc ID ID IDM Total Power Dissipation @ TA = 25C Derate above 25C 4 Drain 4 2 NTP27N06 LLYWW 1 Gate 3 3 Source 2 Drain Apk NTP27N06 LL Y WW = Device Code = Location Code = Year = Work Week mJ ORDERING INFORMATION 109 Device NTP27N06 Package Shipping TO-220AB 50 Units/Rail This document contains information on a new product. Specifications and information herein are subject to change without notice. Semiconductor Components Industries, LLC, 2001 March, 2001 - Rev. 1 208 Publication Order Number: NTP27N06/D NTP27N06 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - 70 79.4 - - - - - - 1.0 10 - - 100 2.0 - 2.8 6.9 4.0 - - 37.5 46 - - 1.05 2.12 1.5 - gFS - 13.2 - mhos Ciss - 725 1015 pF Coss - 213 300 Crss - 58 120 td(on) - 13.6 30 tr - 62.7 125 td(off) - 26.6 60 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 1.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (Note 1.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (Note 1.) (VGS = 10 Vdc, ID = 13.5 Adc) RDS(on) Static Drain-to-Source On-Resistance (Note 1.) (VGS = 10 Vdc, ID = 27 Adc) (VGS = 10 Vdc, ID = 13.5 Adc, TJ = 150C) VDS(on) Forward Transconductance (Note 1.) (VDS = 7.0 Vdc, ID = 6.0 Adc) Vdc mV/C mW Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 30 Vdc, ID = 27 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) (Note 1.) Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 27 Adc, Ad VGS = 10 Vdc) (Note 1.) tf - 70.4 140 QT - 21.2 30 Q1 - 5.6 - Q2 - 7.3 - - - 1.05 0.93 1.25 - trr - 42 - ta - 26 - tb - 16 - QRR - 0.07 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage VSD (IS = 27 Adc, VGS = 0 Vdc) (Note 1.) (IS = 27 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 27 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 1.) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 209 Vdc ns c # #$%& '( N-Channel TO-220 and D2PAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. http://onsemi.com Features * * * * * * * * 45 AMPERES 60 VOLTS RDS(on) = 26 m Higher Current Rating Lower RDS(on) Lower VDS(on) Lower Capacitances Lower Total Gate Charge Tighter VSD Specification Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge N-Channel D Typical Applications * * * * G Power Supplies Converters Power Motor Controls Bridge Circuits 4 S 4 1 2 3 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 10 M) Gate-to-Source Voltage - Continuous - Non-Repetitive (tpv10 ms) Drain Current - Continuous @ TA = 25C - Continuous @ TA = 100C - Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 50 Vdc, VGS = 10 Vdc, RG = 25 , IL(pk) = 40 A, L = 0.3 mH, VDS = 60 Vdc) Symbol Value Unit VDSS VDGR 60 Vdc 60 Vdc March, 2001 - Rev. 0 2 3 MARKING DIAGRAMS & PIN ASSIGNMENTS Vdc VGS VGS "20 "30 ID ID IDM PD 45 30 150 Adc 125 0.83 3.2 2.4 W W/C W W TJ, Tstg -55 to +175 C EAS 240 mJ 4 Drain 4 Drain Apk 1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). Semiconductor Components Industries, LLC, 2001 1 D2PAK CASE 418B STYLE 2 TO-220AB CASE 221A STYLE 5 210 NTB45N06 LLYWW NTP45N06 LLYWW 1 Gate 3 Source 2 Drain 1 Gate NTx45N06 LL Y WW 2 Drain 3 Source = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device Package Shipping NTP45N06 TO-220AB 50 Units/Rail NTB45N06 D2PAK 50 Units/Rail NTB45N06T4 D2PAK 800/Tape & Reel Publication Order Number: NTP45N06/D NTP45N06, NTB45N06 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Thermal Resistance - Junction-to-Case - Junction-to-Ambient (Note 3.) - Junction-to-Ambient (Note 4.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol Value Unit RJC RJA RJA 1.2 46.8 63.2 C/W TL 260 C ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - 70 57 - - - - - - 1.0 10 - - 100 2.0 - 2.8 7.2 4.0 - - 21 26 - - 0.93 0.93 1.4 - gFS - 16.6 - mhos Ciss - 1224 1725 pF Coss - 345 485 Crss - 76 160 td(on) - 10 25 tr - 101 200 td(off) - 33 70 tf - 106 220 QT - 33 46 Q1 - 6.4 - Q2 - 15 - VSD - - 1.08 0.93 1.2 - Vdc trr - 53.1 - ns ta - 36 - tb - 16.9 - QRR - 0.087 When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). Pulse Test: Pulse Width 300 s, Duty Cycle 2%. Switching characteristics are independent of operating junction temperatures. - OFF CHARACTERISTICS V(BR)DSS Drain-to-Source Breakdown Voltage (Note 5.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 5.) Gate Threshold Voltage (Note 5.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (Note 5.) (VGS = 10 Vdc, ID = 22.5 Adc) RDS(on) Static Drain-to-Source On-Voltage (Note 5.) (VGS = 10 Vdc, ID = 45 Adc) (VGS = 10 Vdc, ID = 22.5 Adc, TJ = 150C) VDS(on) Forward Transconductance (Note 5.) (VDS = 8.0 Vdc, ID = 12 Adc) Vdc mV/C mOhm Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 6.) Turn-On Delay Time Rise Time (VDD = 30 Vdc, ID = 45 Adc, VGS = 10 Vdc, RG = 9.1 ) (Note 5.) Turn-Off Delay Time Fall Time Gate Charge Ad (VDS = 48 Vd Vdc, ID = 45 Adc, VGS = 10 Vdc) (Note 5.) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 45 Adc, VGS = 0 Vdc) (Note 5.) (IS = 45 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 45 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 5.) Reverse Recovery Stored Charge 3. 4. 5. 6. http://onsemi.com 211 C NTP45N06, NTB45N06 90 90 VGS = 10 V VGS = 7 V VGS = 9 V 70 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 80 VGS = 6.5 V 60 VGS = 6 V VGS = 8 V 50 VGS = 7.5 V 40 VGS = 5.5 V 30 VGS = 5 V 20 VGS = 4.5 V 10 VDS > = 10 V 80 70 60 50 40 30 TJ = 25C 20 TJ = 100C 10 TJ = -55C 0 0 0 4 5 1 2 3 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 6 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 2. Transfer Characteristics 0.05 VGS = 10 V 0.042 0.034 TJ = 100C 0.026 TJ = 25C 0.018 0.01 TJ = -55C 0 10 20 30 40 50 60 70 80 90 ID, DRAIN CURRENT (AMPS) RDS(on), DRAIN-TO-SOURCE RESISTANCE () RDS(on), DRAIN-TO-SOURCE RESISTANCE () Figure 1. On-Region Characteristics 0.032 0.03 0.028 0.026 0.024 VGS = 10 V 0.022 0.02 0.018 VGS = 15 V 0 20 30 40 50 60 70 90 80 Figure 4. On-Resistance vs. Drain Current and Gate Voltage 10000 2.2 VGS = 0 V ID = 22.5 A VGS = 10 V IDSS, LEAKAGE (nA) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 10 ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Gate-to-Source Voltage 2 8 1.8 TJ = 150C 1000 1.6 1.4 1.2 TJ = 125C 100 1 TJ = 100C 0.8 0.6 -50 -25 10 0 25 50 75 100 125 150 175 0 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage http://onsemi.com 212 60 3600 3200 TJ = 25C Ciss 2800 C, CAPACITANCE (pF) VGS = 0 V VDS = 0 V Crss 2400 2000 1600 Ciss 1200 800 Coss 400 Crss 0 10 5 VGS 0 VDS 5 10 15 20 25 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) NTP45N06, NTB45N06 12 QT 10 VGS 8 Q1 6 Q2 4 2 ID = 45 TJ = 25C 0 0 4 8 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) IS, SOURCE CURRENT (AMPS) t, TIME (ns) 24 28 32 36 50 VDS = 30 V ID = 45 A VGS = 10 V tf 100 tr td(off) td(on) 10 1 10 100 VGS = 0 V TJ = 25C 40 30 20 10 0 0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96 1 1.04 RG, GATE RESISTANCE () VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 1000 VGS = 20 V SINGLE PULSE TC = 25C dc 10 ms 10 1 ms 1 0.1 0.10 RDS(on) Limit Thermal Limit Package Limit 1 100 s 10 100 Figure 10. Diode Forward Voltage vs. Current EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) Figure 9. Resistive Switching Time Variation vs. Gate Resistance ID, DRAIN CURRENT (AMPS) 20 Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge 1000 100 16 Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation 1 12 280 ID = 45 A 240 200 160 120 80 40 0 25 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 213 175 NTP45N06, NTB45N06 r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) 1 Normalized to RJC at Steady State 0.1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 t, TIME (s) Figure 13. Thermal Response r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 10 Normalized to RJA at Steady State, 1 square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board 1 0.1 0.01 0.001 0.00001 0.0001 0.001 0.01 0.1 1 t, TIME (s) Figure 14. Thermal Response http://onsemi.com 214 10 100 1000 # #$%& '( * %+% N-Channel TO-220 and D2PAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. http://onsemi.com Features * * * * * * * * 45 AMPERES 60 VOLTS RDS(on) = 28 m Higher Current Rating Lower RDS(on) Lower VDS(on) Lower Capacitances Lower Total Gate Charge Tighter VSD Specification Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge N-Channel D Typical Applications * * * * G Power Supplies Converters Power Motor Controls Bridge Circuits 4 S 4 1 2 3 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 10 M) Gate-to-Source Voltage - Continuous - Non-Repetitive (tpv10 ms) Drain Current - Continuous @ TA = 25C - Continuous @ TA = 100C - Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 50 Vdc, VGS = 5.0 Vdc, L = 0.3 mH IL(pk) = 40 A, VDS = 60 Vdc, RG = 25 ) Symbol Value Unit VDSS VDGR 60 Vdc 60 Vdc March, 2001 - Rev. 0 2 3 MARKING DIAGRAMS & PIN ASSIGNMENTS Vdc VGS VGS "15 "20 ID ID IDM PD 45 30 150 Adc 125 0.83 3.2 2.4 W W/C W W TJ, Tstg -55 to +175 C EAS 240 mJ 4 Drain 4 Drain Apk 1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). Semiconductor Components Industries, LLC, 2001 1 D2PAK CASE 418B STYLE 2 TO-220AB CASE 221A STYLE 5 215 NTB45N06L LLYWW NTP45N06L LLYWW 1 Gate 3 Source 2 Drain 1 Gate NTx45N06L LL Y WW 2 Drain 3 Source = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device Package Shipping NTP45N06L TO-220AB 50 Units/Rail NTB45N06L D2PAK 50 Units/Rail NTB45N06LT4 D2PAK 800/Tape & Reel Publication Order Number: NTP45N06L/D NTP45N06L, NTB45N06L MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Thermal Resistance - Junction-to-Case - Junction-to-Ambient (Note 3.) - Junction-to-Ambient (Note 4.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol Value Unit RJC RJA RJA 1.2 46.8 63.2 C/W TL 260 C ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - 67 67.2 - - - - - - 1.0 10 - - 100 1.0 - 1.8 4.7 2.0 - - 23 28 - - 1.03 0.93 1.51 - gFS - 22.8 - mhos Ciss - 1212 1700 pF Coss - 352 480 Crss - 90 180 td(on) - 13 30 tr - 341 680 td(off) - 36 75 OFF CHARACTERISTICS V(BR)DSS Drain-to-Source Breakdown Voltage (Note 4.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 5.) Gate Threshold Voltage (Note 5.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (Note 5.) (VGS = 5.0 Vdc, ID = 22.5 Adc) RDS(on) Static Drain-to-Source On-Voltage (Note 5.) (VGS = 5.0 Vdc, ID = 45 Adc) (VGS = 5.0 Vdc, ID = 22.5 Adc, TJ = 150C) VDS(on) Forward Transconductance (Note 5.) (VDS = 8.0 Vdc, ID = 12 Adc) Vdc mV/C mOhm Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 6.) Turn-On Delay Time Rise Time (VDD = 30 Vdc, ID = 45 Adc, VGS = 5.0 Vdc, RG = 9.1 ) (Note 5.) Turn-Off Delay Time Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 45 Adc, Ad VGS = 5.0 Vdc) (Note 5.) ns tf - 158 320 QT - 23 32 Q1 - 4.6 - Q2 - 14.1 - VSD - - 1.01 0.92 1.15 - Vdc trr - 56 - ns ta - 30 - tb - 26 - QRR - 0.09 - nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 45 Adc, VGS = 0 Vdc) (Note 5.) (IS = 45 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 45 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 5.) Reverse Recovery Stored Charge 3. 4. 5. 6. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). Pulse Test: Pulse Width 300 s, Duty Cycle 2%. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 216 C NTP45N06L, NTB45N06L 80 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 70 80 VGS = 5.5 V VGS = 10 V VGS = 5 V 60 VGS = 6 V 50 VGS = 7 V VGS = 4.5 V 40 VGS = 4 V 30 VGS = 8 V 20 VGS = 3.5 V VGS = 9 V 10 VDS > = 10 V 70 60 50 40 30 TJ = 25C 20 TJ = 100C 10 TJ = -55C 0 1 3 2 4 TJ = 25C 0.03 0.026 0.022 TJ = -55C 0.018 10 20 30 40 50 60 80 70 RDS(on), DRAIN-TO-SOURCE RESISTANCE () TJ = 100C 0.034 5 5.8 0.046 0.042 0.038 0.034 VGS = 5 V 0.03 0.026 VGS = 10 V 0.022 0.018 0 10 20 30 40 50 60 70 80 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Gate-to-Source Voltage Figure 4. On-Resistance vs. Drain Current and Gate Voltage 10000 ID = 22.5 A VGS = 5 V VGS = 0 V IDSS, LEAKAGE (nA) 1.8 4.2 Figure 2. Transfer Characteristics 0.038 2 3.4 Figure 1. On-Region Characteristics 0.042 0 2.6 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VGS = 5 V 0.014 0 1.8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.046 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN-TO-SOURCE RESISTANCE () 0 1.6 1.4 1.2 1 TJ = 150C 1000 TJ = 125C 100 TJ = 100C 0.8 0.6 -50 -25 10 0 25 50 75 100 125 150 175 0 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage http://onsemi.com 217 60 4000 VGS = 0 V VDS = 0 V Ciss 3600 TJ = 25C C, CAPACITANCE (pF) 3200 Crss 2800 2400 2000 Ciss 1600 1200 800 Coss 400 Crss 0 10 5 VGS 0 VDS 5 10 15 25 20 VGS Q2 4 3 2 1 ID = 45 A TJ = 25C 0 0 4 8 12 16 20 Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge tr td(off) td(on) 1 10 100 40 32 24 16 8 0 0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96 1 Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current dc 10 10 ms 1 ms RDS(on) Limit Thermal Limit Package Limit 1 100 s 10 100 EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) VGS = 15 V SINGLE PULSE TC = 25C 0.1 0.10 VGS = 0 V TJ = 25C RG, GATE RESISTANCE () 1000 1 24 48 VDS = 30 V ID = 45 A VGS = 5 V IS, SOURCE CURRENT (AMPS) t, TIME (ns) Q1 Figure 7. Capacitance Variation 100 ID, DRAIN CURRENT (AMPS) QT 5 Qg, TOTAL GATE CHARGE (nC) tf 100 6 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 10 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) NTP45N06L, NTB45N06L 280 ID = 45 A 240 200 160 120 80 40 0 25 50 75 100 125 150 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 218 175 NTP45N06L, NTB45N06L r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) 1 Normalized to RJC at Steady State 0.1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 t, TIME (s) Figure 13. Thermal Response r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 10 Normalized to RJA at Steady State, 1 square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board 1 0.1 0.01 0.001 0.00001 0.0001 0.001 0.01 0.1 1 t, TIME (s) Figure 14. Thermal Response http://onsemi.com 219 10 100 1000 #"! "! #$%& '( " ! N-Channel TO-220 and D2PAK http://onsemi.com This 10 VGS gate drive vertical Power MOSFET is a general purpose part that provides the "best of design" available today in a low cost power package. Avalanche energy issues make this part an ideal design in. The drain-to-source diode has a ideal fast but soft recovery. 75 AMPERES 30 VOLTS RDS(on) = 6.5 m Features * * * * * * Ultra-Low RDS(on), Single Base, Advanced Technology SPICE Parameters Available Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperatures High Avalanche Energy Specified ESD JEDAC Rated HBM Class 1, MM Class B, CDM Class 0 N-Channel Typical Applications * * * * Power Supplies Inductive Loads PWM Motor Controls Replaces MTP1306 and MTB1306 in Many Applications 4 4 1 2 3 1 D2PAK CASE 418B STYLE 2 TO-220AB CASE 221A STYLE 5 2 3 MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain E75 N03-06 YWW E75 N03-06 YWW 1 Gate 3 Source 2 Drain 1 Gate N03-06 Y WW 2 Drain 3 Source = Device Code = Year = Work Week ORDERING INFORMATION Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 0 220 Device Package Shipping NTP75N03-06 TO-220 50 Units/Rail NTB75N03-06 D2PAK 50 Units/Rail NTB75N03-06T4 D2PAK 800 Tape & Reel Publication Order Number: NTP75N03-06/D NTP75N03-06, NTB75N03-06 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 30 Vdc Drain-to-Gate Voltage (RGS = 10 M) VDGB 30 Vdc Gate-to-Source Voltage - Continuous VGS 20 Vdc Non-repetitive (tp 10 ms) VGS 24 Vdc Drain Current - Continuous @ TA = 25_C - Continuous @ TA = 100_C - Single Pulse (tp 10 s) ID ID IDM 75 59 225 Adc PD 150 1.0 2.5 W W/_C W TJ and Tstg -55 to 150 _C EAS 1500 mJ RJC RJA RJA 1.0 62.5 50 _C/W TL 260 _C Rating Total Power Dissipation @ TC = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 38 Vdc, VGS = 10 Vdc, L = 1 mH, IL(pk) = 55 A, VDS = 40 Vdc) Thermal Resistance - Junction-to-Case - Junction-to-Ambient - Junction-to-Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 1. When surface mounted to an FR4 board using the minimum recommended pad size. http://onsemi.com 221 Apk NTP75N03-06, NTB75N03-06 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Symbol Characteristic Min Typ. Max Unit 30 - -57 - - Vdc mVC - - - - 1.0 10 - - 100 nAdc 1.0 - 1.6 -6 2.0 - Vdc mVC - 5.3 6.5 - - 0.53 0.35 0.68 0.50 gFS - 58 - Mhos Ciss - 4398 5635 pF Coss - 1160 1894 Crss - 317 430 td(on) - 31 48 tr - 510 986 td(off) - 99 120 tf - 203 300 QT - 52 122 Q1 - 6.6 28 Q2 - 28 66 VSD - - 1.19 1.09 1.25 - Vdc trr - 37 - ns ta - 20 - tb - 17 - QRR - 0.023 - OFF CHARACTERISTICS Drain-Source Breakdown Voltage (Note 2.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Negative) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 150C) (VGS = 20 Vdc, VDS = 0 Vdc) Gate-Body Leakage Current Adc IDSS IGSS ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Note 2.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (Note 2.) (VGS = 10 Vdc, ID = 37.5 Adc) RDS(on) Static Drain-to-Source On Resistance (Note 2.) (VGS = 10 Vdc, ID = 75 Adc) (VGS = 10 Vdc, ID = 37.5 Adc, TJ = 125C) VDS(on) Forward Transconductance (Notes 2. & 4.) (VDS = 3 Vdc, ID = 20 Adc) m Vdc DYNAMIC CHARACTERISTICS (Note 4.) Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 0, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 3. & 4.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VGS = 5 5.0 0 Vd Vdc, VDD = 20 Vdc, ID = 75 Adc, RG = 4.7 ) (Note 2.) Fall Time Gate Charge (VGS = 5.0 Vdc, ID = 75 Adc, Ad VDS = 24 Vdc) (Note 2.) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage Reverse Recovery Time (N t 4 (Note 4.)) (IS = 75 Adc, VGS = 0 Vdc) (IS = 75 Adc, VGS = 0 Vdc, TJ = 125C) (Note 2.) (IS = 75 Ad Adc, VGS = 0 Vd Vdc dlS/dt = 100 A/s) (Note 2.) Reverse Recovery Stored Ch Charge (Note (N t 4.) 4) 2. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. 3. Switching characteristics are independent of operating junction temperatures. 4. From characterization test data. http://onsemi.com 222 C NTP75N03-06, NTB75N03-06 VGS = 3.5 V VGS = 5 V VGS = 6 V VGS = 8 V VGS = 10 V 60 VGS = 3 V 30 TJ = 25C VGS = 2.5 V 0 120 105 90 75 60 TJ = 25C 45 30 TJ = 100C 15 0 0.5 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 1 1.5 2.5 3 3.5 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics VGS = 5 V TJ = 100C 0.0075 0.007 TJ = 25C 0.0065 0.006 0.0055 TJ = -55C 0.005 0.0045 0.004 10 20 30 40 50 60 70 80 90 100 120 4 0.009 TJ = 25C 0.008 0.007 VGS = 5 V 0.006 VGS = 10 V 0.005 0.004 0 20 ID, DRAIN CURRENT (AMPS) 40 60 80 100 120 ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Drain Current and Temperature Figure 4. On-Resistance vs. Drain Current and Gate Voltage 1000 1.6 VGS = 0 V VGS = 10 V ID = 37.5 A 1.4 IDSS, LEAKAGE (nA) RDS(on), DRAIN-TO SOURCE RESISTANCE (NORMALIZED) 2 TJ = -55C VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.0085 0.008 VDS 10 V 135 ID, DRAIN CURRENT (AMPS) 90 0 0.2 0.4 0.6 0.8 1 RDS(on), DRAIN-TO SOURCE RESISTANCE () 150 VGS = 4 V VGS = 4.5 V RDS(on), DRAIN-TO SOURCE RESISTANCE () ID, DRAIN CURRENT (AMPS) 120 1.2 1 0.8 0.6 -50 TJ = 125C 100 TJ = 100C 10 1 -25 0 25 50 75 100 125 150 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage http://onsemi.com 223 1200 VGS VDS VDS = 0 V VGS = 0 V TJ = 25C C, CAPACITANCE (pF) 1000 800 600 Ciss 400 Coss 200 Crss 0 10 8 6 4 2 0 2 4 6 8 10 12 14 16 18 20 22 25 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) NTP75N03-06, NTB75N03-06 30 12 QT 10 20 8 VGS 6 15 Q1 Q2 4 ID = 75 A TJ = 25C 0 0 4 0 12 16 20 24 28 32 36 40 44 48 52 8 Figure 8. Gate-to-Source Voltage vs. Total Charge IS, SOURCE CURRENT (AMPS) 1000 tf 100 td(off) td(on) 2.2 4.7 6.2 VDD = 15 V VGS = 5 V 9.1 10 20 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 0.0 VGS = 0 V TJ = 25C 0.2 0.4 0.6 0.8 RG, GATE RESISTANCE () VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) t, TIME (ns) tr 1 1600 ID = 75 A 1400 1200 1000 800 600 400 200 0 25 50 5 Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation 10 10 2 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 75 A 25 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) Figure 11. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 224 150 1.0 #"!) "!) #$%& '( " ! N-Channel TO-220 and D2PAK http://onsemi.com This Logic Level Vertical Power MOSFET is a general purpose part that provides the "best of design" available today in a low cost power package. Avalanche energy issues make this part an ideal design in. The drain-to-source diode has a ideal fast but soft recovery. 75 AMPERES 30 VOLTS RDS(on) = 9 m Features * * * * * * Ultra-Low RDS(on), Single Base, Advanced Technology SPICE Parameters Available Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperatures High Avalanche Energy Specified ESD JEDAC Rated HBM Class 1, MM Class B, CDM Class 0 N-Channel Typical Applications * * * * Power Supplies Inductive Loads PWM Motor Controls Replaces MTP75N03HDL and MTB75N03HDL in Many Applications 4 4 1 2 3 1 D2PAK CASE 418B STYLE 2 TO-220AB CASE 221A STYLE 5 2 3 MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain E75 N03L09 YWW E75 N03L09 YWW 1 Gate 3 Source 2 Drain 1 Gate N03L09 Y WW 2 Drain 3 Source = Device Code = Year = Work Week ORDERING INFORMATION Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 0 225 Device Package Shipping NTP75N03L09 TO-220 50 Units/Rail NTB75N03L09 D2PAK 50 Units/Rail NTB75N03L09T4 D2PAK 800 Tape & Reel Publication Order Number: NTP75N03L09/D NTP75N03L09, NTB75N03L09 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 30 Vdc Drain-to-Gate Voltage (RGS = 10 M) VDGB 30 Vdc Gate-to-Source Voltage - Continuous VGS 20 Vdc Non-repetitive (tp 10 ms) VGS 24 Vdc Drain Current - Continuous @ TA = 25_C - Continuous @ TA = 100_C - Single Pulse (tp 10 s) ID ID IDM 75 59 225 Adc PD 150 1.0 2.5 W W/_C W TJ and Tstg -55 to 150 _C EAS 1500 mJ RJC RJA RJA 1.0 62.5 50 _C/W TL 260 _C Rating Total Power Dissipation @ TC = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 38 Vdc, VGS = 10 Vdc, L = 1 mH, IL(pk) = 55 A, VDS = 40 Vdc) Thermal Resistance - Junction-to-Case - Junction-to-Ambient - Junction-to-Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 1. When surface mounted to an FR4 board using the minimum recommended pad size. http://onsemi.com 226 Apk NTP75N03L09, NTB75N03L09 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Symbol Characteristic Min Typ. Max Unit 30 34 -57 - - Vdc mVC - - - - 1.0 10 - - 100 nAdc 1.0 - 1.6 -6 2.0 - Vdc mVC - 7.5 9 - - 0.52 0.35 0.68 0.50 gFS - 58 - m Ciss - 4398 5635 pF Coss - 1160 1894 Crss - 317 430 td(on) - 31 48 tr - 510 986 td(off) - 99 120 tf - 203 300 QT - 52 122 Q1 - 6.6 28 Q2 - 28 66 VSD - - 1.19 1.09 1.25 - Vdc trr - 37 - ns ta - 20 - tb - 17 - QRR - 0.023 - OFF CHARACTERISTICS Drain-Source Breakdown Voltage (Note 2.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Negative) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 150C) (VGS = 20 Vdc, VDS = 0 Vdc) Gate-Body Leakage Current Adc IDSS IGSS ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Note 2.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (Note 2.) (VGS = 5.0 Vdc, ID = 37.5 Adc) RDS(on) Static Drain-to-Source On Resistance (Note 2.) (VGS = 10 Vdc, ID = 75 Adc) (VGS = 10 Vdc, ID = 37.5 Adc, TJ = 125C) VDS(on) Forward Transconductance (Notes 2. & 4.) (VDS = 3 Vdc, ID = 20 Adc) m Vdc DYNAMIC CHARACTERISTICS (Note 4.) Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 0, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 3. & 4.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VGS = 5 5.0 0 Vd Vdc, VDD = 20 Vdc, ID = 75 Adc, RG = 4.7 ) (Note 2.) Fall Time Gate Charge (VGS = 5.0 Vdc, ID = 75 Adc, Ad VDS = 24 Vdc) (Note 2.) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage Reverse Recovery Time (N t 4 (Note 4.)) (IS = 75 Adc, VGS = 0 Vdc) (IS = 75 Adc, VGS = 0 Vdc, TJ = 125C) (Note 2.) (IS = 75 Ad Adc, VGS = 0 Vd Vdc dlS/dt = 100 A/s) (Note 2.) Reverse Recovery Stored Ch Charge (Note (N t 4.) 4) 2. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. 3. Switching characteristics are independent of operating junction temperatures. 4. From characterization test data. http://onsemi.com 227 C NTP75N03L09, NTB75N03L09 VGS = 3.5 V VGS = 5 V VGS = 6 V VGS = 8 V VGS = 10 V 60 VGS = 3 V 30 TJ = 25C VGS = 2.5 V 0 120 105 90 75 60 TJ = 25C 45 30 TJ = 100C 15 0 0.5 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 1 1.5 2.5 3 3.5 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics VGS = 5 V TJ = 100C 0.0075 0.007 TJ = 25C 0.0065 0.006 0.0055 TJ = -55C 0.005 0.0045 0.004 10 20 30 40 50 60 70 80 90 100 120 4 0.009 TJ = 25C 0.008 0.007 VGS = 5 V 0.006 VGS = 10 V 0.005 0.004 0 20 ID, DRAIN CURRENT (AMPS) 40 60 80 100 120 ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Drain Current and Temperature Figure 4. On-Resistance vs. Drain Current and Gate Voltage 1000 1.6 VGS = 0 V VGS = 10 V ID = 37.5 A 1.4 IDSS, LEAKAGE (nA) RDS(on), DRAIN-TO SOURCE RESISTANCE (NORMALIZED) 2 TJ = -55C VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.0085 0.008 VDS 10 V 135 ID, DRAIN CURRENT (AMPS) 90 0 0.2 0.4 0.6 0.8 1 RDS(on), DRAIN-TO SOURCE RESISTANCE () 150 VGS = 4 V VGS = 4.5 V RDS(on), DRAIN-TO SOURCE RESISTANCE () ID, DRAIN CURRENT (AMPS) 120 1.2 1 0.8 0.6 -50 TJ = 125C 100 TJ = 100C 10 1 -25 0 25 50 75 100 125 150 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage http://onsemi.com 228 1200 VGS VDS VDS = 0 V VGS = 0 V TJ = 25C C, CAPACITANCE (pF) 1000 800 600 Ciss 400 Coss 200 Crss 0 10 8 6 4 2 0 2 4 6 8 10 12 14 16 18 20 22 25 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) NTP75N03L09, NTB75N03L09 30 12 QT 10 20 8 VGS 6 15 Q1 Q2 4 ID = 75 A TJ = 25C 0 0 4 0 12 16 20 24 28 32 36 40 44 48 52 8 Figure 8. Gate-to-Source Voltage vs. Total Charge IS, SOURCE CURRENT (AMPS) 1000 tf 100 td(off) td(on) 2.2 4.7 6.2 VDD = 15 V VGS = 5 V 9.1 10 20 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 0.0 VGS = 0 V TJ = 25C 0.2 0.4 0.6 0.8 RG, GATE RESISTANCE () VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) t, TIME (ns) tr 1 1600 ID = 75 A 1400 1200 1000 800 600 400 200 0 25 50 5 Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation 10 10 2 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 75 A 25 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) Figure 11. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 229 150 1.0 6, #$%& '( -, N-Channel TSSOP-8 Features * * * * * * * http://onsemi.com New Low Profile TSSOP-8 Package Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperatures 5.8 AMPERES 20 VOLTS RDS(on) = 30 m N-Channel Applications D * Power Management in Portable and Battery-Powered Products, i.e.: * * Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones Lithium Ion Battery Applications Note Book PC Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Drain Current - Continuous Drain Current - Continuous @ 70C Drain Current - Single Pulse (tp 10 ms) Total Power Dissipation Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 20 Vdc, VGS = 5 Vdc, IL = 10 Apk, L = 10 mH, RG = 25 ) Thermal Resistance - Junction-to-Ambient (Note 1.) Single Channel Steady State Both Channels Junction-to-Ambient (Note 2.) Both Channels Thermal Resistance - Junction-to-Lead Single Channel Both Channels Steady State Symbol Value Unit VDSS VGS 20 Vdc "12 Vdc ID ID IDM PD 5.8 TBD 20 Adc 1.6 W TJ, Tstg -55 to +150 C EAS 580 mJ C/W RqJA D G1 G2 MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating 180 176 N-Channel S1 S2 TSSOP-8 CASE 948S PLASTIC 8 1 MARKING DIAGRAM & PIN ASSIGNMENT 1 S1 G1 S2 2 3 G2 4 DEVICE MARKING TBD 8 7 6 5 D D D D Top View 100 RqJL C/W 27 24 ORDERING INFORMATION 1. Surface Mounted to Min Pad. 2. Surface Mounted to 1 x 1 FR4 Board. Device Package Shipping NTQD6866 TSSOP-8 100 Units/Rail NTQD6866R2 TSSOP-8 3000/Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2001 January, 2001 - Rev. 1 230 Publication Order Number: NTQD6866/D NTQD6866 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 20 - - TBD - - - - - - 1.0 25 - - - - 100 100 0.6 - 0.9 TBD 1.2 - - - - TBD 0.026 0.031 TBD 0.030 0.040 gFS TBD 17 - Mhos Ciss - 930 TBD pF Coss - 370 TBD Crss - 105 TBD td(on) - 8.6 TBD tr - 14 TBD td(off) - 57 TBD tf - 54 TBD QT - 11 15 Q1 - 2.4 - Q2 - 2.4 - VSD - - 0.7 TBD 1.0 - Vdc trr - 30 - ns ta - 14.5 - tb - 15.5 - QRR - 0.01 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Collector Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 85C) Vdc Adc IDSS Gate-Body Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) IGSS(f) IGSS(r) mV/C nAdc ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mA) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-State Resistance (VGS = 4.5 Vdc, ID = 7.0 Adc) (VGS = 4.0 Vdc, ID = 7.0 Adc) (VGS = 2.5 Vdc, ID = 3.5 Adc) RDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 7.0 Adc) Vdc mV/C DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 1.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RL = 10, RG = 6.0 ) Fall Time Gate Charge (VDS = 10 Vdc, VGS = 4.5 Vdc, ID = 5.8 5 8 Ad Adc)) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 3.) (IS = 1.8 Adc, VGS = 0 Vdc) (IS = 1.8 Adc, VGS = 0 Vdc, TJ = 85C) Reverse Recovery Time (IS = 1.5 1 5 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%. 4. Switching characteristics are independent of operating junction temperature. http://onsemi.com 231 C 6! #$%& '( - P-Channel TSSOP-8 Features * * * * * * * http://onsemi.com New Low Profile TSSOP-8 Package Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperatures 6.2 AMPERES 20 VOLTS RDS(on) = 20 m P-Channel Applications * Power Management in Portable and Battery-Powered Products, i.e.: * * D Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones Lithium Ion Battery Applications Note Book PC G S MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current - TJ = 150C (Note 1.) - TA = 25C - TA = 70C Pulsed Drain Current (10 s Pulse Width) Symbol 10 secs VDS VGS ID Steady State -20 Maximum Power Dissipation (Note 1.) - TA = 25C - TA = 70C PD 8 TSSOP-8 CASE 948S PLASTIC Adc "6.2 "4.9 -1.35 463 YWW X 1 "30 IDM IS MARKING DIAGRAM Vdc "12 "7.4 "5.9 Continuous Source Current (Diode Conduction) (Note 1.) Unit Apk -0.95 463 Y WW X Adc = Device Code = Year = Work Week = MOSFET W PIN ASSIGNMENT 1.5 1.0 1.05 0.67 1 Operating Junction and Storage Temperature Range TJ, Tstg -55 to +150 C D S S 2 3 Single Pulse Drain-to-Source Avalanche Energy - Starting TJ= 25C (VDD = 50 V, IL = 16.3 Apk, L = 10 mH) EAS 1.38 J G 4 8 7 6 5 D S S D Top View ORDERING INFORMATION 1. Surface mounted to 1 x 1 FR-4 board. Device Package Shipping NTQS6463 TSSOP-8 100 Units/Rail NTQS6463R2 TSSOP-8 3000/Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2001 January, 2001 - Rev. 0 232 Publication Order Number: NTQS6463/D NTQS6463 THERMAL RESISTANCE RATINGS Rating Symbol Maximum Junction-to-Ambient (Note 2.) t 10 sec Steady State RJA Maximum Junction-to-Foot Steady State RJF Typical Max Unit C/W 65 100 83 120 43 52 C/W ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit -0.45 -0.9 - - - 100 nAdc - - - - -1.0 -10 dc 20 - - - - 0.018 0.025 0.020 0.027 STATIC VGS(th) Gate Threshold Voltage (VDS = VGS, ID = -250 A) Gate-Body Leakage (VGS = 0 Vdc, VGS = 8 Vdc) IGSS Zero Gate Threshold Voltage Drain Current (VDS = -16 Vdc, VGS = 0 Vdc) (VDS = -16 Vdc, VGS = 0 Vdc, TJ = 70_C) IDSS On-State Drain Current (Note 3.) (VDS = -5.0 Vdc, VGS = -4.5 Vdc) ID(on) Drain-Source On-State Resistance (Note 3.) (VGS = -4.5 Vdc, ID = -7.4 Adc) (VGS = -2.5 Vdc, ID = -6.3 Adc) Vdc Adc RDS(on) Forward Transconductance (VDS = -15 Vdc, ID = -7.4 Adc) (Note 3.) gFS - 21 - S Diode Forward Voltage (IS = -1.3 Adc, VGS = 0 Vdc) (Note 3.) VSD - -0.71 -1.1 Vdc Qg - 28 50 nC DYNAMIC (Note 4.) Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time (VDS = -10 Vdc, VGS = -5.0 Vdc, ID = -7.4 7 4 Ad Adc)) (VDD = -10 10 Vdc, Vdc RL = 15 , ID -1.0 1.0 Adc, VGEN = -4.5 Vdc, RG = 6 6.0 0 ) (IF = -1.3 Adc, di/dt = 100 A/s) 2. Surface mounted to 1 x 1 FR-4 board. 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Guaranteed by design, not subject to production testing. http://onsemi.com 233 Qgs - 4.0 - Qgd - 9.0 - td(on) - 19 50 tr - 20 50 td(off) - 95 120 tf - 65 100 trr - 45 80 ns ns # #$%& '( - P-Channel Enhancement Mode Dual Micro8 Package http://onsemi.com Features * * * * * * Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature Dual Micro8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Micro8 Mounting Information Provided -1.45 AMPERES -20 VOLTS 160 mW @ VGS = -4.5 Applications Dual P-Channel * Power Management in Portable and Battery-Powered Products, i.e.: D Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating G Symbol Value Unit VDSS VGS -20 V Gate-to-Source Voltage - Continuous "8.0 V Thermal Resistance - Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 3.) RJA PD ID ID IDM 250 0.50 -1.45 -1.15 -10 C/W W A A A RJA PD ID ID IDM TJ, Tstg 125 1.0 -2.04 -1.64 -16 C/W W A A A -55 to +150 C EAS 35 mJ TL 260 C Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 3.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = -20 Vdc, VGS = -4.5 Vdc, Peak IL = -3.5 Apk, L = 5.6 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes for 10 seconds This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. November, 2000 - Rev. 0 8 1 Micro8 CASE 846A STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENT Source 1 Gate 1 Source 2 Gate 2 1 8 2 YWW 7 3 6 BC 4 5 Drain 1 Drain 1 Drain 2 Drain 2 (Top View) 1. Minimum FR-4 or G-10 PCB, Steady State. 2. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. 3. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. Semiconductor Components Industries, LLC, 2000 S 234 Y = Year WW = Work Week BC = Device Code ORDERING INFORMATION Device Package Shipping NTTD1P02R2 Micro8 4000/Tape & Reel Publication Order Number: NTTD1P02R2/D NTTD1P02R2 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 4.) Characteristic Symbol Min Typ Max Unit -20 - - -12 - - - - - - -1.0 -10 - - -100 - - 100 -0.7 - -0.95 2.3 -1.4 - - - - 0.130 0.175 0.190 0.160 0.250 - gFS - 2.5 - Mhos Ciss - 265 - pF Coss - 100 - Crss - 60 - td(on) - 10 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = -250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = -20 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = -20 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = -8 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +8 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-State Resistance (VGS = -4.5 Vdc, ID = -1.45 Adc) (VGS = -2.7 Vdc, ID = -0.7 Adc) (VGS = -2.5 Vdc, ID = -0.7 Adc) RDS(on) Forward Transconductance (VDS = -10 Vdc, ID = -0.7 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = -16 16 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 5. & 6.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = -16 16 Vdc, ID = -1.45 1.45 Adc, VGS = -4.5 Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = -16 16 Vdc, ID = -0.7 0.7 Adc, VGS = -4.5 Vdc, RG = 6.0 ) Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge (VDS = -16 Vdc, VGS = -4.5 Vdc, ID = -1.45 1 45 Adc) Ad ) tr - 25 - td(off) - 30 - tf - 25 - td(on) - 10 - tr - 20 - td(off) - 30 - ns ns tf - 20 - Qtot - 5.0 10 Qgs - 1.5 - Qgd - 2.0 - VSD - - -0.91 -0.72 -1.1 - Vdc trr - 25 - ns ta - 13 - tb - 12 - QRR - 0.015 - nC BODY-DRAIN DIODE RATINGS (Note 5.) Diode Forward On-Voltage (IS = -1.45 Adc, VGS = 0 Vdc) (IS = -1.45 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = -1.45 1 45 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 4. Handling precautions to protect against electrostatic discharge is mandatory. 5. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 6. Switching characteristics are independent of operating junction temperature. http://onsemi.com 235 C NTTD1P02R2 3 -2.5 V -2.3 V -ID, DRAIN CURRENT (AMPS) -ID, DRAIN CURRENT (AMPS) 3 -2.7 V -2.9 V -3.1 V -3.3 V -3.7 V -4.5 V 2 TJ = 25C -2.1 V -8 V -1.9 V 1 -1.7 V VGS = -1.5 V 0 2 TJ = -55C 1 0.25 0.5 0.75 1 1.25 1.5 TJ = 25C 1 2 2.5 3 Figure 2. Transfer Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) Figure 1. On-Region Characteristics 0.2 0.1 0 2 4 6 8 12 10 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 3.5 0.3 TJ = 25C VGS = -2.5 V 0.2 VGS = -2.7 V VGS = -4.5 V 0.1 0 0 0.5 1 1.5 2 2.5 3 3.5 -ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance versus Gate-to-Source Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage 1.6 100 VGS = 0 V -IDSS, LEAKAGE (nA) ID = -1.45 A VGS = -4.5 V 1.2 1 0.8 0.6 -50 1.5 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) ID = -1.45 A TJ = 25C 1.4 0.5 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.3 0 0 1.75 0.4 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) TJ = 100C 0 0 RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) VDS -10 V TJ = 125C TJ = 100C 10 1 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 4 Figure 5. On-Resistance Variation with Temperature 8 12 16 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 236 20 800 Ciss VDS = 0 V VGS = 0 V C, CAPACITANCE (pF) TJ = 25C 600 Crss 400 Ciss 200 Coss Crss 0 5 10 0 -VGS -VDS 5 10 15 20 5 20 QT 18 16 4 14 -VGS 3 Q1 12 10 Q2 8 2 6 1 ID = -1.45 A TJ = 25C -VDS 4 2 0 0 0 1 2 3 4 5 6 Qg, TOTAL GATE CHARGE (nC) GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) NTTD1P02R2 Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge Figure 7. Capacitance Variation 100 -IS, SOURCE CURRENT (AMPS) t, TIME (ns) VDD = -16 V ID = -1.45 A VGS = -4.5 V tr td (off) tf 10 td (on) 1.2 0.8 0.4 0 1 10 1 100 ID , DRAIN CURRENT (AMPS) VGS = 0 V TJ = 25C 1.6 100 0.4 0.5 0.6 0.7 0.8 1 -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current VGS = 8 V SINGLE PULSE TC = 25C di/dt IS 10 100 ms 1 ms ta 1 trr tb TIME 10 ms 0.25 IS tp 0.1 0.01 0.9 RG, GATE RESISTANCE (OHMS) IS RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 dc 10 100 Figure 12. Diode Reverse Recovery Waveform VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 237 NTTD1P02R2 TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (C/W) 1000 100 10 D = 0.5 0.2 0.1 0.05 *0 0.02 0.01 ' 1 '# - - " '&'# SINGLE PULSE ,' " (' , - . / / ' ,*0 " *0 ,' 0.1 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 t, TIME (s) Figure 13. Thermal Response INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 0.041 1.04 0.208 5.28 0.126 3.20 0.015 0.38 0.0256 0.65 inches mm http://onsemi.com 238 NTTD1P02R2 SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 14. Typical Solder Heating Profile http://onsemi.com 239 NTTD1P02R2 TAPE & REEL INFORMATION Micro8 Dimensions are shown in millimeters (inches) 1.60 (.063) 1.50 (.059) 2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B A 1.85 (.072) 1.65 (.065) 0.35 (.013) 0.25 (.010) 5.55 (.218) 5.45 (.215) 12.30 11.70 (.484) (.461) 3.50 (.137) 3.30 (.130) A FEED DIRECTION 8.10 (.318) 7.90 (.312) 1.60 (.063) 1.50 (.059) TYP. 1.50 (.059) 1.30 (.052) SECTION A-A 5.40 (.212) 5.20 (.205) SECTION B-B NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 18.4 (.724) MAX. NOTE 3 13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN. NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB. http://onsemi.com 240 14.4 (.57) 12.4 (.49) NOTE 4 # #$%& '( - Dual P-Channel Micro8 Features * * * * * * Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature Micro-8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Micro8 Mounting Information Provided http://onsemi.com -2.4 AMPERES -20 VOLTS RDS(on) = 90 m Applications * Power Management in Portable and Battery-Powered Products, i.e.: Cellular and Cordless Telephones and PCMCIA Cards P-Channel MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit VDSS VGS -20 V Gate-to-Source Voltage - Continuous "8.0 V Thermal Resistance - Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 3.) RJA PD ID ID IDM 160 0.78 -2.4 -1.92 -20 C/W W A A A RJA PD ID ID IDM TJ, Tstg 88 1.42 -3.25 -2.6 -30 C/W W A A A -55 to +150 C 350 mJ Rating Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 3.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = -20 Vdc, VGS = -4.5 Vdc, Peak IL = -5.0 Apk, L = 28 mH, RG = 25 ) EAS Maximum Lead Temperature for Soldering Purposes for 10 seconds TL MARKING DIAGRAM 8 1 YWW BE Micro8 CASE 846A STYLE 2 Y WW BE C 260 1. Minimum FR-4 or G-10 PCB, Steady State. 2. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. 3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. = Year = Work Week = Device Code PIN ASSIGNMENT Source 1 Gate 1 Source 2 Gate 2 1 8 7 6 5 2 3 4 Drain 1 Drain 1 Drain 2 Drain 2 Top View ORDERING INFORMATION Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 0 241 Device Package Shipping NTTD2P02R2 Micro8 4000/Tape & Reel Publication Order Number: NTTD2P02R2/D NTTD2P02R2 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 4.) Characteristic Symbol Min Typ Max Unit -20 - - -12.7 - - - - - - -1.0 -25 - - -5.0 - - -100 - - 100 -0.5 - -0.90 2.5 -1.4 - - - - 0.070 0.100 0.110 0.090 0.130 - gFS 2.0 4.2 - Mhos Ciss - 550 - pF Coss - 200 - Crss - 100 - td(on) - 10 - tr - 31 - td(off) - 33 - tf - 29 - td(on) - 15 - tr - 40 - td(off) - 35 - tf - 35 - Qtot - 10 18 Qgs - 1.5 - Qgd - 5.0 - VSD - - -0.88 -0.75 -1.0 - Vdc trr - 37 - ns ta - 16 - tb - 21 - QRR - 0.025 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = -250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = -16 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = -16 Vdc, TJ = 125C) IDSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = -20 Vdc, TJ = 25C) IDSS Gate-Body Leakage Current (VGS = -8 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +8 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-State Resistance (VGS = -4.5 Vdc, ID = -2.4 Adc) (VGS = -2.7 Vdc, ID = -1.2 Adc) (VGS = -2.5 Vdc, ID = -1.2 Adc) RDS(on) Forward Transconductance (VDS = -10 Vdc, ID = -1.2 Adc) Vdc mV/C DYNAMIC CHARACTERISTICS Input Capacitance (VDS = -16 16 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 5. & 6.) Turn-On Delay Time Rise Time (VDD = -10 10 Vdc, ID = -2.4 2.4 Adc, VGS = -4.5 Vdc, RG = 6.0 ) Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time (VDD = -10 10 Vdc, ID = -1.2 1.2 Adc, VGS = -2.7 Vdc, RG = 6.0 ) Turn-Off Delay Time Fall Time Total Gate Charge (VDS = -16 Vdc, VGS = -4.5 Vdc, ID = -2.4 2 4 Ad Adc)) Gate-Source Charge Gate-Drain Charge ns ns nC BODY-DRAIN DIODE RATINGS (Note 5.) Diode Forward On-Voltage (IS = -2.4 Adc, VGS = 0 Vdc) (IS = -2.4 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = -2.4 2 4 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 4. Handling precautions to protect against electrostatic discharge is mandatory. 5. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 6. Switching characteristics are independent of operating junction temperature. http://onsemi.com 242 C NTTD2P02R2 5 4 VGS = -10 V VGS = -4.5 V VGS = -2.5 V 3 TJ = 25C -ID, DRAIN CURRENT (AMPS) -ID, DRAIN CURRENT (AMPS) VGS = -2.1 V VGS = -1.9 V 2 VGS = -1.7 V 1 VGS = -1.5 V 4 3 2 TJ = 25C 1 TJ = 100C 0 2 4 6 8 1 10 3 2.5 Figure 2. Transfer Characteristics. 0.1 0.05 0 2 4 6 8 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) Figure 1. On-Region Characteristics. 0.15 0.12 TJ = 25C 0.1 VGS = -2.7 V 0.08 VGS = -4.5 V 0.06 0.04 1 1.5 2 2.5 3 3.5 4 4.5 -ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Gate-to-Source Voltage. Figure 4. On-Resistance vs. Drain Current and Gate Voltage. 1000 1.6 VGS = 0 V ID = -2.4 A VGS = -4.5 V TJ = 125C -IDSS, LEAKAGE (nA) 100 1.2 1 0.8 0.6 -50 2 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C 1.4 1.5 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.2 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) TJ = 55C 0 0 RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) VDS > = 10 V TJ = 100C 10 TJ = 25C 1 0.1 0.01 -25 0 25 75 50 100 125 TJ, JUNCTION TEMPERATURE (C) 150 0 Figure 5. On-Resistance Variation with Temperature. 4 8 12 16 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 6. Drain-to-Source Leakage Current vs. Voltage. http://onsemi.com 243 20 1500 C, CAPACITANCE (pF) VDS = 0 V 1200 VGS = 0 V Ciss TJ = 25C 900 Crss Ciss 600 300 Coss Crss 0 10 5 0 -VGS -VDS 5 10 15 20 5 20 18 QT 16 4 14 3 12 VGS Q1 10 Q2 8 2 6 1 ID = -2.4 A TJ = 25C VDS 4 2 0 0 0 2 4 6 8 10 14 12 Qg, TOTAL GATE CHARGE (nC) GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) NTTD2P02R2 Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge Figure 7. Capacitance Variation 1000 100 td (off) tr t, TIME (ns) t, TIME (ns) VDD = -10 V ID = -1.2 A VGS = -2.7 V 100 tr VDD = -10 V ID = -2.4 A VGS = -4.5 V td (on) 1.0 10 10 1.0 td (on) 10 tf td (off) tf 100 RG, GATE RESISTANCE (OHMS) 1.0 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Resistive Switching Time Variation versus Gate Resistance -IS, SOURCE CURRENT (AMPS) 2 1.6 VGS = 0 V TJ = 25C di/dt IS 1.2 ta trr tb TIME 0.8 0.25 IS tp IS 0.4 0 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 12. Diode Reverse Recovery Waveform -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 11. Diode Forward Voltage versus Current http://onsemi.com 244 NTTD2P02R2 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE 1 D = 0.5 0.2 0.1 Normalized to Rja at Steady State (1 inch pad) 0.1 0.0125 0.0563 0.110 0.273 0.113 0.436 2.93 F 152 F 261 F 0.05 0.02 0.01 0.021 F 0.137 F 1.15 F Single Pulse 0.01 1E-03 1E-02 1E-01 1E+00 1E+03 1E+02 1E+03 t, TIME (s) Figure 13. FET Thermal Response. INFORMATION FOR USING THE Micro-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 0.041 1.04 0.208 5.28 0.126 3.20 0.015 0.38 0.0256 0.65 inches mm http://onsemi.com 245 NTTD2P02R2 SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 14. Typical Solder Heating Profile http://onsemi.com 246 NTTD2P02R2 TAPE & REEL INFORMATION Micro-8 Dimensions are shown in millimeters (inches) 1.60 (.063) 1.50 (.059) 2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B 1.85 (.072) 1.65 (.065) A 0.35 (.013) 0.25 (.010) 5.55 (.218) 5.45 (.215) 12.30 11.70 (.484) (.461) 3.50 (.137) 3.30 (.130) 1.60 (.063) 1.50 (.059) TYP. A FEED DIRECTION 8.10 (.318) 7.90 (.312) 1.50 (.059) 1.30 (.052) SECTION A-A 5.40 (.212) 5.20 (.205) SECTION B-B NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 18.4 (.724) MAX. NOTE 3 13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN. 14.4 (.57) 12.4 (.49) NOTE 4 NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB. http://onsemi.com 247 # #$%& '( - Single P-Channel Micro8t Features * * * * * * Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature Micro-8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Micro8 Mounting Information Provided http://onsemi.com -2.4 AMPERES -20 VOLTS RDS(on) = 90 m Applications * Power Management in Portable and Battery-Powered Products, i.e.: Cellular and Cordless Telephones and PCMCIA Cards Single P-Channel MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit VDSS VGS -20 V Gate-to-Source Voltage - Continuous 8.0 V Thermal Resistance - Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 3.) RJA PD ID ID IDM 160 0.78 -2.4 -1.92 -20 C/W W A A A RJA PD ID ID IDM TJ, Tstg 88 1.42 -3.25 -2.6 -30 C/W W A A A -55 to +150 C 350 mJ Rating Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 3.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = -20 Vdc, VGS = -4.5 Vdc, Peak IL = -5.0 Apk, L = 28 mH, RG = 25 ) EAS Maximum Lead Temperature for Soldering Purposes for 10 seconds TL MARKING DIAGRAM 8 1 YWW AD Micro8 CASE 846A STYLE 1 Y WW AD C 260 1. Minimum FR-4 or G-10 PCB, Steady State. 2. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. 3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. = Year = Work Week = Device Code PIN ASSIGNMENT Source Source Source Gate 1 8 7 6 5 2 3 4 Drain Drain Drain Drain Top View ORDERING INFORMATION Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 4 248 Device Package Shipping NTTS2P02R2 Micro8 4000/Tape & Reel Publication Order Number: NTTS2P02R2/D NTTS2P02R2 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 4.) Characteristic Symbol Min Typ Max Unit -20 - - -12.7 - - - - - - -1.0 -25 - - -5.0 - - -100 - - 100 -0.5 - -0.90 2.5 -1.4 - - - - 0.070 0.100 0.110 0.090 0.130 - gFS 2.0 4.2 - Mhos Ciss - 550 - pF Coss - 200 - Crss - 100 - td(on) - 10 - tr - 31 - td(off) - 33 - tf - 29 - td(on) - 15 - tr - 40 - td(off) - 35 - tf - 35 - Qtot - 10 18 Qgs - 1.5 - Qgd - 5.0 - VSD - - -0.88 -0.75 -1.0 - Vdc trr - 37 - ns ta - 16 - tb - 21 - QRR - 0.025 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = -250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = -16 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = -16 Vdc, TJ = 125C) IDSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = -20 Vdc, TJ = 25C) IDSS Gate-Body Leakage Current (VGS = -8 Vdc, VDS = 0 Vdc) IGSS Gate-Body Leakage Current (VGS = +8 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc Adc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-State Resistance (VGS = -4.5 Vdc, ID = -2.4 Adc) (VGS = -2.7 Vdc, ID = -1.2 Adc) (VGS = -2.5 Vdc, ID = -1.2 Adc) RDS(on) Forward Transconductance (VDS = -10 Vdc, ID = -1.2 Adc) Vdc mV/C DYNAMIC CHARACTERISTICS Input Capacitance (VDS = -16 16 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 5. & 6.) Turn-On Delay Time Rise Time (VDD = -10 10 Vdc, ID = -2.4 2.4 Adc, VGS = -4.5 Vdc, RG = 6.0 ) Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time (VDD = -10 10 Vdc, ID = -1.2 1.2 Adc, VGS = -2.7 Vdc, RG = 6.0 ) Turn-Off Delay Time Fall Time Total Gate Charge (VDS = -16 Vdc, VGS = -4.5 Vdc, ID = -2.4 2 4 Ad Adc)) Gate-Source Charge Gate-Drain Charge ns ns nC BODY-DRAIN DIODE RATINGS (Note 5.) Diode Forward On-Voltage (IS = -2.4 Adc, VGS = 0 Vdc) (IS = -2.4 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = -2.4 2 4 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 4. Handling precautions to protect against electrostatic discharge is mandatory. 5. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 6. Switching characteristics are independent of operating junction temperature. http://onsemi.com 249 C NTTS2P02R2 5 4 VGS = -10 V VGS = -4.5 V VGS = -2.5 V 3 TJ = 25C -ID, DRAIN CURRENT (AMPS) -ID, DRAIN CURRENT (AMPS) VGS = -2.1 V VGS = -1.9 V 2 VGS = -1.7 V 1 VGS = -1.5 V 4 3 2 TJ = 25C 1 TJ = 100C 0 2 4 6 8 1 10 3 2.5 Figure 2. Transfer Characteristics. 0.1 0.05 0 2 4 6 8 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) Figure 1. On-Region Characteristics. 0.15 0.12 TJ = 25C 0.1 VGS = -2.7 V 0.08 VGS = -4.5 V 0.06 0.04 1 1.5 2 2.5 3 3.5 4 4.5 -ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Gate-to-Source Voltage. Figure 4. On-Resistance vs. Drain Current and Gate Voltage. 1000 1.6 VGS = 0 V ID = -2.4 A VGS = -4.5 V TJ = 125C -IDSS, LEAKAGE (nA) 100 1.2 1 0.8 0.6 -50 2 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C 1.4 1.5 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.2 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) TJ = 55C 0 0 RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) VDS > = 10 V TJ = 100C 10 TJ = 25C 1 0.1 0.01 -25 0 25 75 50 100 125 TJ, JUNCTION TEMPERATURE (C) 150 0 Figure 5. On-Resistance Variation with Temperature. 4 8 12 16 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 6. Drain-to-Source Leakage Current vs. Voltage. http://onsemi.com 250 20 1500 C, CAPACITANCE (pF) VDS = 0 V 1200 VGS = 0 V Ciss TJ = 25C 900 Crss Ciss 600 300 Coss Crss 0 10 5 0 -VGS -VDS 5 10 15 20 5 20 18 QT 16 4 14 3 12 VGS Q1 10 Q2 8 2 6 1 ID = -2.4 A TJ = 25C VDS 4 2 0 0 0 2 4 6 8 10 14 12 Qg, TOTAL GATE CHARGE (nC) GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) NTTS2P02R2 Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge Figure 7. Capacitance Variation 1000 100 td (off) tr t, TIME (ns) t, TIME (ns) VDD = -10 V ID = -1.2 A VGS = -2.7 V 100 tr VDD = -10 V ID = -2.4 A VGS = -4.5 V td (on) 1.0 10 10 1.0 td (on) 10 tf td (off) tf 100 RG, GATE RESISTANCE (OHMS) 1.0 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Resistive Switching Time Variation versus Gate Resistance -IS, SOURCE CURRENT (AMPS) 2 1.6 VGS = 0 V TJ = 25C di/dt IS 1.2 ta trr tb TIME 0.8 0.25 IS tp IS 0.4 0 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 12. Diode Reverse Recovery Waveform -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 11. Diode Forward Voltage versus Current http://onsemi.com 251 NTTS2P02R2 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE 1 D = 0.5 0.2 0.1 Normalized to Rja at Steady State (1 inch pad) 0.1 0.0125 0.0563 0.110 0.273 0.113 0.436 2.93 F 152 F 261 F 0.05 0.02 0.01 0.021 F 0.137 F 1.15 F Single Pulse 0.01 1E-03 1E-02 1E-01 1E+00 1E+03 1E+02 1E+03 t, TIME (s) Figure 13. FET Thermal Response. INFORMATION FOR USING THE Micro-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 0.041 1.04 0.208 5.28 0.126 3.20 0.015 0.38 0.0256 0.65 inches mm http://onsemi.com 252 NTTS2P02R2 SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 14. Typical Solder Heating Profile http://onsemi.com 253 NTTS2P02R2 TAPE & REEL INFORMATION Micro-8 Dimensions are shown in millimeters (inches) 1.60 (.063) 1.50 (.059) 2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B 1.85 (.072) 1.65 (.065) A 0.35 (.013) 0.25 (.010) 5.55 (.218) 5.45 (.215) 12.30 11.70 (.484) (.461) 3.50 (.137) 3.30 (.130) 1.60 (.063) 1.50 (.059) TYP. A FEED DIRECTION 8.10 (.318) 7.90 (.312) 1.50 (.059) 1.30 (.052) SECTION A-A 5.40 (.212) 5.20 (.205) SECTION B-B NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 18.4 (.724) MAX. NOTE 3 13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN. 14.4 (.57) 12.4 (.49) NOTE 4 NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB. http://onsemi.com 254 #! #$%& '( -, ! P-Channel Enhancement Mode Single Micro8t Package http://onsemi.com Features * * * * * Ultra Low RDS(on) Higher Efficiency Extending Battery Life Miniature Micro8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Micro8 Mounting Information Provided -2.48 AMPERES -30 VOLTS 85 mW @ VGS = -10 V Applications Single P-Channel * Power Management in Portable and Battery-Powered Products, i.e.: Cellular and Cordless Telephones and PCMCIA Cards D MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit -30 V Gate-to-Source Voltage - Continuous VDSS VGS "20 V Thermal Resistance - Junction-to-Ambient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C RJA PD ID ID 160 0.78 -2.48 -1.98 C/W W A A Thermal Resistance - Junction-to-Ambient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C RJA PD ID ID 70 1.78 -3.75 -3.0 C/W W A A Thermal Resistance - Junction-to-Ambient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 5.) RJA PD ID ID IDM 210 0.60 -2.10 -1.67 -17 C/W W A A A RJA PD ID ID IDM TJ, Tstg 100 1.25 -3.02 -2.42 -24 C/W W A A A -55 to +150 C Rating Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient (Note 4.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 5.) Operating and Storage Temperature Range 1. Minimum FR-4 or G-10 PCB, Time 10 Seconds. 2. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Time 10 Seconds. 3. Minimum FR-4 or G-10 PCB, Steady State. 4. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. 5. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. G S 8 1 Micro8 CASE 846A STYLE 1 MARKING DIAGRAM & PIN ASSIGNMENT Source Source Source Gate 1 2 YWW 3 AE 4 8 7 6 5 Drain Drain Drain Drain (Top View) Y = Year WW = Work Week AE = Device Code ORDERING INFORMATION Device NTTS2P03R2 Package Shipping Micro8 4000/Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2001 February, 2001 - Rev. 0 255 Publication Order Number: NTTS2P03R2/D NTTS2P03R2 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (continued) Rating Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = -30 Vdc, VGS = -10 Vdc, Peak IL = -3.0 Apk, L = 65 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes for 10 seconds Symbol Value Unit EAS 292.5 mJ TL 260 C ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 6.) Characteristic Symbol Min Typ Max Unit V(BR)DSS -30 - - -30 - - Vdc mV/C - - - - -1.0 -25 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = -250 Adc) Temperature Coefficient (Positive) Adc Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = -30 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = -30 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = -20 Vdc, VDS = 0 Vdc) IGSS - - -100 nAdc Gate-Body Leakage Current (VGS = +20 Vdc, VDS = 0 Vdc) IGSS - - 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) Temperature Coefficient (Negative) VGS(th) -1.0 - -1.7 3.6 -3.0 - Vdc Static Drain-to-Source On-State Resistance (VGS = -10 Vdc, ID = -2.48 Adc) (VGS = -4.5 Vdc, ID = -1.24 Adc) RDS(on) - - 0.063 0.100 0.085 0.135 gFS - 3.1 - Mhos Ciss - 500 - pF Coss - 160 - Crss - 65 - td(on) - 10 - ON CHARACTERISTICS Forward Transconductance (VDS = -15 Vdc, ID = -1.24 Adc) DYNAMIC CHARACTERISTICS Input Capacitance (VDS = -24 24 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 7. & 8.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = -24 24 Vdc, ID = -2.48 2.48 Adc, VGS = -10 Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = -24 24 Vdc, ID = -1.24 1.24 Adc, VGS = -4.5 Vdc, RG = 6.0 ) Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge (VDS = -24 Vdc, VGS = -4.5 Vdc, 2 48 Adc) Ad ) ID = -2.48 tr - 20 - td(off) - 40 - tf - 35 - td(on) - 16 - tr - 40 - td(off) - 30 - ns ns tf - 30 - Qtot - 15 22 Qgs - 3.2 - Qgd - 4.0 - VSD - - -0.92 -0.72 -1.3 - Vdc trr - 38 - ns ta - 20 - tb - 18 - QRR - 0.04 - nC BODY-DRAIN DIODE RATINGS (Note 7.) Diode Forward On-Voltage (IS = -2.48 Adc, VGS = 0 Vdc) (IS = -2.48 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = -1.45 1 45 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 6. Handling precautions to protect against electrostatic discharge is mandatory. 7. Indicates Pulse Test: Pulse Width = 300 sec max, Duty Cycle = 2%. 8. Switching characteristics are independent of operating junction temperature. http://onsemi.com 256 C NTTS2P03R2 5 -10 V -3.5 V -3.3 V TJ = 25C -3.7 V -3.9 V 2 -ID, DRAIN CURRENT (AMPS) -ID, DRAIN CURRENT (AMPS) 3 -3.1 V -4.1 V -4.5 V -4.9 V -6 V -2.9 V 1 -2.7 V -2.5 V VGS = -2.3 V 3 TJ = 25C 2 TJ = 100C 1 TJ = -55C 0 0 0.5 0.25 0.75 1 1.25 1.5 1 1.75 3 4 5 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 0.3 ID = -2.48 A TJ = 25C 0.25 0.2 0.15 0.1 0.05 0 0 2 4 6 10 8 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 0.15 TJ = 25C VGS = -4.5 V 0.1 VGS = -10 V 0.05 0 0.5 1.5 2.5 3.5 4.5 5.5 -ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance versus Gate-to-Source Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage 1.6 10,000 VGS = 0 V 1.4 ID = -2.48 A VGS = -10 V -IDSS, LEAKAGE (nA) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0 RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) VDS -10 V 4 1.2 1 0.8 0.6 -50 TJ = 150C 1000 100 TJ = 100C 10 1 -25 0 25 75 50 100 125 TJ, JUNCTION TEMPERATURE (C) 150 5 Figure 5. On-Resistance Variation with Temperature 10 15 20 25 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 257 30 C, CAPACITANCE (pF) VGS = 0 V TJ = 25C Ciss 1000 800 Crss 600 Ciss 400 Coss 200 Crss 0 -10 -5 0 5 10 15 20 25 30 -VGS -VDS 6 30 25 5 QT 4 Q1 20 VGS Q2 3 15 2 10 ID = -2.48 A TJ = 25C 1 VDS 5 0 0 2 0 4 6 8 10 12 16 14 Qg, TOTAL GATE CHARGE (nC) GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDS = 0 V 1200 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) NTTS2P03R2 Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge Figure 7. Capacitance Variation 3 -IS, SOURCE CURRENT (AMPS) 100 t, TIME (ns) td (off) tf tr 10 td (on) VDD = -24 V ID = -2.48 A VGS = -10 V 1 10 1 100 2.5 VGS = 0 V TJ = 25C 2 1.5 1 0.5 0 0.4 0.5 0.6 0.7 0.8 0.9 1 RG, GATE RESISTANCE (OHMS) -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current ID , DRAIN CURRENT (AMPS) 100 10 VGS = 30 V SINGLE PULSE TC = 25C di/dt IS 1 ms 10 ms ta trr tb 1 TIME 0.25 IS tp 0.1 0.01 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 IS dc 10 100 Figure 12. Diode Reverse Recovery Waveform VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 258 NTTS2P03R2 TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (C/W) 1000 100 10 D = 0.5 0.2 0.1 0.05 *0 0.02 0.01 ' 1 '# - - " '&'# SINGLE PULSE ,' " (' , - . / / ' ,*0 " *0 ,' 0.1 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 t, TIME (s) Figure 13. Thermal Response INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 0.041 1.04 0.208 5.28 0.126 3.20 0.015 0.38 0.0256 0.65 inches mm http://onsemi.com 259 NTTS2P03R2 SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 14. Typical Solder Heating Profile http://onsemi.com 260 NTTS2P03R2 TAPE & REEL INFORMATION Micro-8 Dimensions are shown in millimeters (inches) 1.60 (.063) 1.50 (.059) 2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B 1.85 (.072) 1.65 (.065) A 0.35 (.013) 0.25 (.010) 5.55 (.218) 5.45 (.215) 12.30 11.70 (.484) (.461) 3.50 (.137) 3.30 (.130) 1.60 (.063) 1.50 (.059) TYP. A FEED DIRECTION 8.10 (.318) 7.90 (.312) 1.50 (.059) 1.30 (.052) SECTION A-A 5.40 (.212) 5.20 (.205) SECTION B-B NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 18.4 (.724) MAX. NOTE 3 13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN. 14.4 (.57) 12.4 (.49) NOTE 4 NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB. http://onsemi.com 261 7 #$%& '( Dual N-Channel SC-88 * * * * * * 2.5 V Gate Drive with Low On-Resistance Low Threshold Voltage: Vth = 0.5 to 1.5 V, Ideal for Portable High Speed Enhancement Mode Small Package Easily Designed Drive Circuits http://onsemi.com 100 mAMPS 20 VOLTS RDS(on) = 10 N-Channel MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Symbol Value Unit VDS 20 Vdc VGSS 10 Vdc Drain Current - Continuous @ TA = 25C ID 100 Total Power Dissipation @ TA = 25C PD 150 mW Channel Temperature Tch 150 C Operating and Storage Temperature Range Tstg - 55 to 150 C mAdc MARKING DIAGRAM 6 5 4 1 2 3 SC-88/SOT-363 CASE 419B STYLE 1 N02 D N02 D = Device Code = Date Code PIN ASSIGNMENT Source-1 1 6 Drain-1 Gate-1 2 5 Gate-2 Drain-2 3 4 Source-2 Top View ORDERING INFORMATION Device NTUD01N02 Package SC-88 Shipping 3000 Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2001 January, 2001 - Rev. 0 262 Publication Order Number: NTUD01N02/D NTUD01N02 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 20 - - Vdc - - 1.0 - - 1.0 0.5 - 1.5 - 5.0 10 YFS 20 - - mS pF OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 100 A) Drain Cut-off Current (VDS = 20 Vdc, VGS = 0 Vdc) IDSS Gate-Body Leakage Current (VGS = 10 Vdc, VDS = 0) IGSS Adc Adc ON CHARACTERISTICS Gate Threshold Voltage (VDS = 3.0 Vdc, ID = 0.1 mAdc) Vth Drain-to-Source On-Resistance (VGS = 2.5 Vdc, ID = 10 mAdc) RDS(on) Forward Transfer Admittance (VDS = 3.0 Vdc, ID = 10 mAdc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 3.0 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss - 5.5 - Output Capacitance (VDS = 3.0 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Coss - 25 - Reverse Transfer Capacitance (VDS = 3.0 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Crss - 1.6 - (VDD = 3.0 Vdc, ID = 10 mAdc, VGS = 0 to 2.5 Vdc) ton - 0.14 - toff - 0.14 - SWITCHING CHARACTERISTICS Turn-On Delay Time Turn-Off Delay Time http://onsemi.com 263 s " Preferred Device 0 0 '( N-Channel TO-92 http://onsemi.com MAXIMUM RATINGS Rating Symbol Value Unit Drain Source Voltage VDSS 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Gate-Source Voltage - Continuous - Non-repetitive (tp 50 s) VGS VGSM ?20 ?40 Vdc Vpk Drain Current - Continuous - Pulsed Total Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Range 200 mAMPS 60 VOLTS RDS(on) = 5 N-Channel mAdc ID IDM 200 500 PD 350 2.8 mW mW/C TJ, Tstg -55 to +150 C Symbol Max Unit RJA 357 C/W TL 300 C THERMAL CHARACTERISTICS Characteristic Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/16 from case for 10 seconds TO-92 CASE 29 Style 22 12 3 MARKING DIAGRAM & PIN ASSIGNMENT 2N7000 YWW 1 Source 3 Drain 2 Gate Y WW = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 266 of this data sheet. Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 5 264 Publication Order Number: 2N7000/D 2N7000 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)DSS 60 - Vdc - - 1.0 1.0 Adc mAdc IGSSF - -10 nAdc Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) VGS(th) 0.8 3.0 Vdc Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 0.5 Adc) (VGS = 4.5 Vdc, ID = 75 mAdc) rDS(on) - - 5.0 6.0 Drain-Source On-Voltage (VGS = 10 Vdc, ID = 0.5 Adc) (VGS = 4.5 Vdc, ID = 75 mAdc) VDS(on) - - 2.5 0.45 On-State Drain Current (VGS = 4.5 Vdc, VDS = 10 Vdc) Id(on) 75 - mAdc Forward Transconductance (VDS = 10 Vdc, ID = 200 mAdc) gfs 100 - mhos Ciss - 60 pF Coss - 25 Crss - 5.0 ton - 10 toff - 10 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 10 Adc) Zero Gate Voltage Drain Current (VDS = 48 Vdc, VGS = 0) (VDS = 48 Vdc, VGS = 0, TJ = 125C) IDSS Gate-Body Leakage Current, Forward (VGSF = 15 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Ohm Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance ((VDS = 25 V,, VGS = 0,, f=1 1.0 0 MH MHz)) SWITCHING CHARACTERISTICS (Note 1.) Turn-On Delay Time Turn-Off Delay Time (VDD = 15 V, ID = 500 mA, RG = 25 W, RL = 30 W, Vgen = 10 V) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. http://onsemi.com 265 ns 2N7000 # " " #$ 9 " 6 7 # 8 : 8 9 9 6 $ # 6 4 8 # 4 6 $ 9 : 8 7 8 #$ 9 6 # # 4 6 $ 9 : 8 #6 ## 8 " " # 9 6 # 8 9 6 ?9 ?# 5?# 5?9 5? 5?6 # $ " " 7$ 7 8$ 8 :$ : ?9 Figure 3. Temperature versus Static Drain-Source On-Resistance ?# 5?# 5?9 5? Figure 4. Temperature versus Gate Threshold Voltage ORDERING INFORMATION Device 7 Figure 2. Transfer Characteristics '2 < ( < Figure 1. Ohmic Region # #$ ?$$ Package Shipping 2N7000 TO-92 1000 Unit/Box 2N7000RLRA TO-92 2000 Tape & Reel 2N7000RLRM TO-92 2000 Ammo Pack 2N7000RLRP TO-92 2000 Ammo Pack 2N7000ZL1 TO-92 2000 Ammo Pack http://onsemi.com 266 5?6 " Preferred Device 0 0 '( N-Channel SOT-23 MAXIMUM RATINGS Rating http://onsemi.com Symbol Value Unit Drain-Source Voltage VDSS 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Drain Current - Continuous TC = 25C (Note 1.) - Continuous TC = 100C (Note 1.) - Pulsed (Note 2.) ID ID IDM ?115 ?75 ?800 mAdc VGS VGSM ?20 ?40 Vdc Vpk Symbol Max Unit PD 225 1.8 mW mW/C Gate-Source Voltage - Continuous - Non-repetitive (tp 50 s) 115 mAMPS 60 VOLTS RDS(on) = 7.5 N-Channel 4 THERMAL CHARACTERISTICS Characteristic Total Device Dissipation FR-5 Board (Note 3.) TA = 25C Derate above 25C # Thermal Resistance, Junction to Ambient RJA 556 C/W Total Device Dissipation Alumina Substrate,(Note 4.) TA = 25C Derate above 25C PD 300 mW mW/C Thermal Resistance, Junction to Ambient RJA 417 C/W 2 TJ, Tstg -?55 to +150 C SOT-23 CASE 318 STYLE 21 Junction and Storage Temperature 3 1 2.4 1. The Power Dissipation of the package may result in a lower continuous drain current. 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. 3. FR-5 = 1.0 x 0.75 x 0.062 in. 4. Alumina = 0.4 x 0.3 x 0.025 in 99.5% alumina. MARKING DIAGRAM & PIN ASSIGNMENT ()% 3 702 W 1 2 )'1 ;(1 702 W = Device Code = Work Week ORDERING INFORMATION Device Package Shipping 2N7002LT1 SOT-23 3000 Tape & Reel 2N7002LT3 SOT-23 10,000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 December, 2000 - Rev. 4 267 Publication Order Number: 2N7002LT1/D 2N7002LT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 60 - - Vdc IDSS - - - - 1.0 500 Adc Gate-Body Leakage Current, Forward (VGS = 20 Vdc) IGSSF - - 100 nAdc Gate-Body Leakage Current, Reverse (VGS = -?20 Vdc) IGSSR - - -100 nAdc VGS(th) 1.0 - 2.5 Vdc On-State Drain Current (VDS 2.0 VDS(on), VGS = 10 Vdc) ID(on) 500 - - mA Static Drain-Source On-State Voltage (VGS = 10 Vdc, ID = 500 mAdc) (VGS = 5.0 Vdc, ID = 50 mAdc) VDS(on) - - - - 3.75 0.375 Static Drain-Source On-State Resistance (VGS = 10 V, ID = 500 mAdc) TC = 25C TC = 125C (VGS = 5.0 Vdc, ID = 50 mAdc) TC = 25C TC = 125C rDS(on) - - - - - - - - 7.5 13.5 7.5 13.5 gFS 80 - - mmhos Input Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Ciss - - 50 pF Output Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Coss - - 25 pF Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Crss - - 5.0 pF td(on) - - 20 ns td(off) - - 40 ns VSD - - -1.5 Vdc IS - - -115 mAdc ISM - - -800 mAdc OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 10 Adc) Zero Gate Voltage Drain Current (VGS = 0, VDS = 60 Vdc) TJ = 25C TJ = 125C ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Forward Transconductance (VDS 2.0 VDS(on), ID = 200 mAdc) Vdc Ohms DYNAMIC CHARACTERISTICS SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Turn-Off Delay Time (VDD = 25 Vdc, ID ^ 500 mAdc, RG = 25 , RL = 50 , Vgen = 10 V) BODY-DRAIN DIODE RATINGS Diode Forward On-Voltage (IS = 11.5 mAdc, VGS = 0 V) Source Current Continuous (Body Diode) Source Current Pulsed 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. http://onsemi.com 268 2N7002LT1 TYPICAL ELECTRICAL CHARACTERISTICS # " " #$ 9 " 6 7 # 8 : 8 9 9 6 $ # 6 4 8 # 4 6 $ 9 : 8 7 8 #$ 9 6 # #6 ## 8 " " # 9 6 # 8 9 6 ?9 ?# 5?# 5?9 # 4 6 $ 9 : 8 7 Figure 2. Transfer Characteristics '2 < ( < Figure 1. Ohmic Region # #$ ?$$ 5? 5?6 # $ " " 7$ 7 8$ 8 :$ : ?9 Figure 3. Temperature versus Static Drain-Source On-Resistance ?# 5?# 5?9 5? Figure 4. Temperature versus Gate Threshold Voltage http://onsemi.com 269 5?6 2N7002LT1 INFORMATION FOR USING THE SOT-23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 4: 7$ 4: 7$ :7 # 4$ 7 4 8 %21! SOT-23 POWER DISSIPATION one can calculate the power dissipation of the device which in this case is 225 milliwatts. The power dissipation of the SOT-23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-23 package, PD can be calculated as follows: PD = PD = 150C - 25C 556C/W = 225 milliwatts The 556C/W for the SOT-23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 270 " " Preferred Device 0 0 '( N-Channel TO-92 http://onsemi.com MAXIMUM RATINGS Rating Drain-Source Voltage Gate-Source Voltage - Continuous - Non-repetitive (tp 50 s) Drain Current Continuous (Note 1.) Pulsed (Note 2.) Total Device Dissipation @ TA = 25C Derate above 25C Operating and Storage Junction Temperature Range Symbol Value Unit VDS 200 Vdc VGS VGSM 20 30 Vdc Vpk ID IDM 250 500 PD 350 mW TJ, Tstg -55 to 150 C 250 mAMPS 200 VOLTS RDS(on) = 14 (BS107) RDS(on) = 6.4 (BS107A) mAdc N-Channel 1. The Power Dissipation of the package may result in a lower continuous drain current. 2. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2.0%. TO-92 CASE 29 Style 30 12 3 MARKING DIAGRAM & PIN ASSIGNMENT BS107 YWW 1 Drain 3 Source 2 Gate Y WW = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 274 of this data sheet. Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 271 Publication Order Number: BS107/D BS107, BS107A ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Zero-Gate-Voltage Drain Current (VDS = 130 Vdc, VGS = 0) IDSS - - 30 nAdc Drain-Source Breakdown Voltage (VGS = 0, ID = 100 Adc) V(BR)DSX 200 - - Vdc IGSS - 0.01 10 nAdc Gate Threshold Voltage (ID = 1.0 mAdc, VDS = VGS) VGS(Th) 1.0 - 3.0 Static Drain-Source On Resistance BS107 (VGS = 2.6 Vdc, ID = 20 mAdc) (VGS = 10 Vdc, ID = 200 mAdc) BS107A (VGS = 10 Vdc) (ID = 100 mAdc) (ID = 250 mAdc) rDS(on) Gate Reverse Current (VGS = 15 Vdc, VDS = 0) ON CHARACTERISTICS (Note 3.) Vdc Ohms - - - - 28 14 - - 4.5 4.8 6.0 6.4 SMALL-SIGNAL CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Ciss - 60 - pF Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Crss - 6.0 - pF Output Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Coss - 30 - pF gfs 200 400 - mmhos Turn-On Time ton - 6.0 15 ns Turn-Off Time toff - 12 15 ns Forward Transconductance (VDS = 25 Vdc, ID = 250 mAdc) SWITCHING CHARACTERISTICS 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2.0%. RESISTIVE SWITCHING 5#$ $ ;' #4 $ % # = $ 6 *. $ ' % 7B 7B B ;' 'CC 7B $B B / $B Figure 2. Switching Waveforms Figure 1. Switching Test Circuit http://onsemi.com 272 BS107, BS107A # 8 " 9 $ " # #$ *. $ 6 # %!! 8 9 6 # # $$ 4$ 8$ $ $ 5$ #$ 9$ 6$ , , #$ 6$ 6 # 4 ?? : 9 : " $ 6 4 # $ 9 : 8 # 4 6 ?? 7 $ $ 6 4 6 # 4 Figure 5. Transfer Characteristic # 6 9 8 # 6 9 ?? Figure 6. Output Characteristic : 9 $ $ 6 4 6 # 4 $ Figure 4. Capacitance Variation 8 Figure 3. On Voltage versus Temperature 9 !! (!! # 4 6 ?? Figure 7. Saturation Characteristic http://onsemi.com 273 $ 8 # BS107, BS107A ORDERING INFORMATION Device Package Shipping BS107 TO-92 1000 Unit/Box BS107RLRA TO-92 2000 Tape & Reel BS107RL1 TO-92 2000 Tape & Reel BS107A TO-92 1000 Units/Box BS107ARLRM TO-92 2000 Ammo Pack BS107ARLRP TO-92 2000 Ammo Pack BS107ARL1 TO-92 2000 Tape & Reel http://onsemi.com 274 , Preferred Device 0 0 '( * %+% N-Channel TO-92 http://onsemi.com This MOSFET is designed for high voltage, high speed switching applications such as line drivers, relay drivers, CMOS logic, microprocessor or TTL to high voltage interface and high voltage display drivers. * Low Drive Requirement, VGS = 3.0 V max * Inherent Current Sharing Capability Permits Easy Paralleling of many Devices 250 mAMPS 200 VOLTS RDS(on) = 8 N-Channel MAXIMUM RATINGS Rating Symbol Value Unit Drain-Source Voltage VDSS 200 Vdc Gate-Source Voltage VGS 20 Vdc Drain Current Continuous (Note 1.) Pulsed (Note 2.) ID IDM 250 500 Total Power Dissipation @ TA = 25C Derate above TA = 25C Operating and Storage Temperature Range mAdc PD TJ, Tstg 350 6.4 mW mW/C -55 to +150 C TO-92 CASE 29 Style 30 12 3 MARKING DIAGRAM & PIN ASSIGNMENT 1. The Power Dissipation of the package may result in a lower continuous drain current. 2. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2.0%. BS108 YWW 1 Drain 3 Source 2 Gate BS108 = Device Code Y = Year WW = Work Week ORDERING INFORMATION Device Package Shipping BS108 TO-92 1000 Units/Box BS108ZL1 TO-92 2000 Ammo Pack Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 275 Publication Order Number: BS108/D BS108 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit - - - Vdc 200 - - 30 - - 10 0.5 - 1.5 - - - - 10 8.0 - - 25 - - 150 - - 30 - - 10 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 10 A) V(BR)DS Zero Gate Voltage Drain Current (VDSS = 130 Vdc, VGS = 0) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0) nAdc IGSSF nAdc ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (ID = 1.0 mA, VDS = VGS) VGS(th) Static Drain-to-Source On-Resistance (VGS = 2.0 Vdc, ID = 50 mA) (VGS = 2.8 Vdc, ID = 100 mA) rDS(on) Drain Cutoff Current (VGS = 0.2 V, VDS = 70 V) Vdc Ohms mA IDSX DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) Ciss Output Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) Coss Reverse Transfer Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) Crss pF pF pF SWITCHING CHARACTERISTICS Turn-On Time (See Figure 1) td(on) - - 15 ns Turn-Off Time (See Figure 1) td(off) - - 15 ns 3. Pulse Test: Pulse Width 300 s, Duty Cycle = 2.0%. RESISTIVE SWITCHING 5#$ $ #4 $ % # = $ 6 *. $ ' ;' 'CC 7B 7B ;' B 7B % $B B / $B Figure 2. Switching Waveforms Figure 1. Switching Test Circuit http://onsemi.com 276 " Preferred Device 0 0 '( N-Channel TO-92 http://onsemi.com MAXIMUM RATINGS Rating Symbol Value Unit VDS 60 Vdc VGS VGSM 20 40 Vdc Vpk Drain Current (Note 1.) ID 0.5 Adc Total Device Dissipation @ TA = 25C PD 350 mW TJ, Tstg -55 to +150 C Drain-Source Voltage Gate-Source Voltage - Continuous - Non-repetitive (tp 50 s) Operating and Storage Junction Temperature Range 500 mAMPS 60 VOLTS RDS(on) = 5 N-Channel 1. The Power Dissipation of the package may result in a lower continuous drain current. TO-92 CASE 29 Style 30 12 3 MARKING DIAGRAM & PIN ASSIGNMENT BS170 YWW 1 Drain 3 Source 2 Gate Y WW = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 278 of this data sheet. Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 277 Publication Order Number: BS170/D BS170 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit IGSS - 0.01 10 nAdc V(BR)DSS 60 90 - Vdc Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) VGS(Th) 0.8 2.0 3.0 Vdc Static Drain-Source On Resistance (VGS = 10 Vdc, ID = 200 mAdc) rDS(on) - 1.8 5.0 ID(off) - - 0.5 A gfs - 200 - mmhos Ciss - - 60 pF Turn-On Time (ID = 0.2 Adc) See Figure 1 ton - 4.0 10 ns Turn-Off Time (ID = 0.2 Adc) See Figure 1 toff - 4.0 10 ns OFF CHARACTERISTICS Gate Reverse Current (VGS = 15 Vdc, VDS = 0) Drain-Source Breakdown Voltage (VGS = 0, ID = 100 Adc) ON CHARACTERISTICS (Note 2.) Drain Cutoff Current (VDS = 25 Vdc, VGS = 0 Vdc) Forward Transconductance (VDS = 10 Vdc, ID = 250 mAdc) SMALL-SIGNAL CHARACTERISTICS Input Capacitance (VDS = 10 Vdc, VGS = 0, f = 1.0 MHz) SWITCHING CHARACTERISTICS 2. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2.0%. ORDERING INFORMATION Device Package Shipping BS170 TO-92 1000 Unit/Box BS170RLRA TO-92 2000 Tape & Reel BS170RLRM TO-92 2000 Ammo Pack BS170RLRP TO-92 2000 Ammo Pack BS170RL1 TO-92 2000 Tape & Reel BS170ZL1 TO-92 2000 Ammo Pack http://onsemi.com 278 BS170 RESISTIVE SWITCHING 5#$ % $ $ ;' ;' # = $ 6 *. $ ' #$ 'CC 7B B 7B $B B % (Vin Amplitude 10 Volts) Figure 2. Switching Waveforms Figure 1. Switching Test Circuit # " " '2 # 9 # 8 6 $ $ , , " 9 7 8 # : 9 8 $ 6 6 $ Figure 3. VGS(th) Normalized versus Temperature 7 : 8 9 6 " 8 8 # 9 6 %!! # $ !! 6 # 4 ?? 6 " 9 # 4 ?? Figure 4. On-Region Characteristics *. # / (!! 6 Figure 5. Output Characteristics # 4 6 $ 9 ?? Figure 6. Capacitance versus Drain-To-Source Voltage http://onsemi.com 279 ! Preferred Device #$%& '( " N-Channel SOT-23 MAXIMUM RATINGS Rating Symbol Value Unit Drain-Source Voltage VDSS 100 Vdc Gate-Source Voltage - Continuous - Non-repetitive (tp 50 s) VGS VGSM 20 40 Vdc Vpk ID IDM 0.17 0.68 Symbol Max Unit PD 225 mW 1.8 mW/C 556 C/W Drain Current Continuous (Note 1.) Pulsed (Note 2.) http://onsemi.com 170 mAMPS 100 VOLTS RDS(on) = 6 N-Channel 4 Adc THERMAL CHARACTERISTICS Characteristic Total Device Dissipation FR-5 Board (Note 3.) TA = 25C Derate above 25C Thermal Resistance, Junction to Ambient RqJA TJ, Tstg -55 to +150 C 1. The Power Dissipation of the package may result in a lower continuous drain current. 2. Pulse Width v 300 ms, Duty Cycle v 2.0%. 3. FR-5 = 1.0 0.75 0.062 in. # MARKING DIAGRAM Junction and Storage Temperature 3 SOT-23 CASE 318 STYLE 21 1 SA W 2 SA W = Device Code = Work Week PIN ASSIGNMENT ()% 3 1 2 ;(1 )'1 ORDERING INFORMATION Device Package Shipping BSS123LT1 SOT-23 3000 Tape & Reel BSS123LT3 SOT-23 10,000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2001 February, 2001 - Rev. 3 280 Publication Order Number: BSS123LT1/D BSS123LT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 100 - - Vdc - - - - 15 60 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 250 Adc) Adc Zero Gate Voltage Drain Current (VGS = 0, VDS = 100 Vdc) TJ = 25C TJ = 125C IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS - - 50 nAdc Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) VGS(th) 0.8 - 2.8 Vdc Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 100 mAdc) rDS(on) - 5.0 6.0 gfs 80 - - mmhos Input Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Ciss - 20 - pF Output Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Coss - 9.0 - pF Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Crss - 4.0 - pF td(on) - 20 - ns td(off) - 40 - ns VSD - - 1.3 V ON CHARACTERISTICS (Note 4.) Forward Transconductance (VDS = 25 Vdc, ID = 100 mAdc) DYNAMIC CHARACTERISTICS SWITCHING CHARACTERISTICS(4) Turn-On Delay Time Turn-Off Delay Time (VCC = 30 Vdc, IC = 0.28 Adc, VGS = 10 Vdc, RGS = 50 ) REVERSE DIODE Diode Forward On-Voltage (ID = 0.34 Adc, VGS = 0 Vdc) 4. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%. http://onsemi.com 281 BSS123LT1 TYPICAL ELECTRICAL CHARACTERISTICS # " " #$ 9 " 6 7 # 8 : 8 9 9 6 $ # 6 4 8 # 4 6 $ 9 : 8 7 8 #$ 9 6 # #6 ## 8 " " # 9 6 # 8 9 6 ?9 ?# 5?# 5?9 # 4 6 $ 9 : 8 7 Figure 2. Transfer Characteristics '2 < ( < Figure 1. Ohmic Region # #$ ?$$ 5? 5?6 # $ " " 7$ 7 8$ 8 :$ : ?9 Figure 3. Temperature versus Static Drain-Source On-Resistance ?# 5?# 5?9 5? Figure 4. Temperature versus Gate Threshold Voltage http://onsemi.com 282 5?6 BSS123LT1 INFORMATION FOR USING THE SOT-23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 4: 7$ 4: 7$ :7 # 4$ 7 4 8 %21! SOT-23 one can calculate the power dissipation of the device which in this case is 225 milliwatts. The power dissipation of the SOT-23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-23 package, PD can be calculated as follows: PD = PD = 150C - 25C 556C/W = 225 milliwatts The 556C/W for the SOT-23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 283 !, Preferred Device #$%& '( N-Channel SOT-23 Typical applications are dc-dc converters, power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. * Low Threshold Voltage (VGS(th): 0.5V...1.5V) makes it ideal for low voltage applications * Miniature SOT-23 Surface Mount Package saves board space http://onsemi.com 200 mAMPS 50 VOLTS RDS(on) = 3.5 MAXIMUM RATINGS (TA = 25C unless otherwise noted) Symbol Value Unit VDSS 50 Vdc Gate-to-Source Voltage - Continuous VGS 20 Vdc Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (tp 10 s) ID IDM 200 800 Total Power Dissipation @ TA = 25C PD 225 mW Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C RJA 556 C/W TL 260 C Rating Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, for 10 seconds N-Channel 4 mA # MARKING DIAGRAM 3 SOT-23 CASE 318 STYLE 21 1 J1 W 2 J1 W = Device Code = Work Week PIN ASSIGNMENT 3 ()% 1 2 )'1 ;(1 ORDERING INFORMATION Device Package Shipping BSS138LT1 SOT-23 3000 Tape & Reel BSS138LT3 SOT-23 10,000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 284 Publication Order Number: BSS138LT1/D BSS138LT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 50 - - Vdc - - - - 0.1 0.5 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Adc Zero Gate Voltage Drain Current (VDS = 25 Vdc, VGS = 0 Vdc) (VDS = 50 Vdc, VGS = 0 Vdc) IDSS Gate-Source Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS - - 0.1 Adc Gate-Source Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) VGS(th) 0.5 - 1.5 Vdc Static Drain-to-Source On-Resistance (VGS = 2.75 Vdc, ID < 200 mAdc, TA = -40C to +85C) (VGS = 5.0 Vdc, ID = 200 mAdc) rDS(on) - - 5.6 - 10 3.5 gfs 100 - - mmhos pF ON CHARACTERISTICS (Note 1.) Forward Transconductance (VDS = 25 Vdc, ID = 200 mAdc, f = 1.0 kHz) Ohms DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0, f = 1 MHz) Ciss - 40 50 Output Capacitance (VDS = 25 Vdc, VGS = 0, f = 1 MHz) Coss - 12 25 Transfer Capacitance (VDG = 25 Vdc, VGS = 0, f = 1 MHz) Crss - 3.5 5.0 td(on) - - 20 td(off) - - 20 SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Turn-Off Delay Time (VDD = 30 Vdc Vdc, ID = 0.2 0 2 Adc,) Adc ) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 285 ns BSS138LT1 TYPICAL ELECTRICAL CHARACTERISTICS : 7 " 4$ , " #$ " 4#$ 9 " 4 $ " #:$ 6 " #$ 4 # " 8 8 $$ : $ 9 $ 6 4 # # 4 6 $ 9 : 8 7 $ $ # #$ 4 4$ 6 6$ Figure 2. Transfer Characteristics Figure 1. On-Region Characteristics ## #$ " # D!'2 " " 8 8 9 " 6$ " $ 6 # #$ 8:$ 8 9 ?$$ $ 6$ 7$ :$ ?$$ 6$ 4 $ # 6$ : 7$ # , , , , Figure 3. On-Resistance Variation with Temperature Figure 4. Threshold Voltage Variation with Temperature < #$ " 6 , " #$ 8 9 6 " # # $ $ # @ * Figure 5. Gate Charge http://onsemi.com 286 #$ 4 6$ BSS138LT1 TYPICAL ELECTRICAL CHARACTERISTICS " #$ 7 8 $ : 9 $ #$ 6 $$ 4 # $ $ #$ # 8 $ 6 6$ 6 4$ 4 #$ #$ # $$ $ $ $ # #$ 4 4$ 6 6$ $ $ $ #$ 4 # $$ $ $ # #$ 6$ " 6 $ 4$ 4 #$ #$ # $$ $ $ $ # #$ 4 4$ 6 6$ $ Figure 9. On-Resistance versus Drain Current Figure 8. On-Resistance versus Drain Current Figure 7. On-Resistance versus Drain Current " 6$ $$ $ 9 Figure 6. On-Resistance versus Drain Current 9 " #:$ : # , " $ #$ $$ 8 9 %!! 6 !! # # 6 9 8 # (!! $ $ . / Figure 10. Body Diode Forward Voltage Figure 11. Capacitance http://onsemi.com 287 # #$ BSS138LT1 INFORMATION FOR USING THE SOT-23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 4: 7$ 4: 7$ :7 # 4$ 7 4 8 %21! SOT-23 POWER DISSIPATION one can calculate the power dissipation of the device which in this case is 225 milliwatts. The power dissipation of the SOT-23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-23 package, PD can be calculated as follows: PD = PD = 150C - 25C 556C/W = 225 milliwatts The 556C/W for the SOT-23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 288 , Preferred Device #$%& '( ! P-Channel SOT-23 These miniature surface mount MOSFETs reduce power loss conserve energy, making this device ideal for use in small power management circuitry. Typical applications are dc-dc converters, load switching, power management in portable and battery-powered products such as computers, printers, cellular and cordless telephones. * Energy Efficient * Miniature SOT-23 Surface Mount Package Saves Board Space http://onsemi.com 130 mAMPS 50 VOLTS RDS(on) = 10 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit VDSS 50 Vdc Gate-to-Source Voltage - Continuous VGS 20 Vdc Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (tp 10 s) ID IDM 130 520 Total Power Dissipation @ TA = 25C PD 225 mW Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C RJA 556 C/W TL 260 C Rating Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, for 10 seconds P-Channel 4 mA # MARKING DIAGRAM 3 SOT-23 CASE 318 STYLE 21 1 PD W 2 PD W = Device Code = Work Week PIN ASSIGNMENT 3 ()% 1 2 ;(1 )'1 ORDERING INFORMATION Device BSS84LT1 Package SOT-23 Shipping 3000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 289 Publication Order Number: BSS84LT1/D BSS84LT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 50 - - Vdc - - - - - - 0.1 15 60 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Adc Zero Gate Voltage Drain Current (VDS = 25 Vdc, VGS = 0 Vdc) (VDS = 50 Vdc, VGS = 0 Vdc) (VDS = 50 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS - - 60 Adc Gate-Source Threaded Voltage (VDS = VGS, ID = 1.0 mAdc) VGS(th) 0.8 - 2.0 Vdc Static Drain-to-Source On-Resistance (VGS = 5.0 Vdc, ID = 100 mAdc) rDS(on) - 5.0 10 Ohms |yfs| 50 - - mS pF ON CHARACTERISTICS (Note 1.) Transfer Admittance (VDS = 25 Vdc, ID = 100 mAdc, f = 1.0 kHz) DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 5.0 Vdc) Ciss - 30 - Output Capacitance (VDS = 5.0 Vdc) Coss - 10 - Transfer Capacitance (VDG = 5.0 Vdc) Crss - 5.0 - td(on) - 2.5 - tr - 1.0 - td(off) - 16 - tf - 8.0 - QT - 6000 - pC IS - - 0.130 A Pulsed Current ISM - - 0.520 Forward Voltage (Note 2.) VSD - 2.5 - SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time (VDD = -15 15 Vdc, ID = -2.5 2.5 Adc, RL = 50 ) Turn-Off Delay Time Fall Time Gate Charge ns SOURCE-DRAIN DIODE CHARACTERISTICS Continuous Current V 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. TYPICAL ELECTRICAL CHARACTERISTICS $ #$ " $ $$ $ 6 4#$ 6 4$ 4 4 4 #$ # # #:$ $ " 4$ , " #$ 6$ 9 #$ ##$ $ $ # #$ 4 4$ 6 # 4 6 $ 9 : 8 Figure 1. Transfer Characteristics Figure 2. On-Region Characteristics http://onsemi.com 290 7 BSS84LT1 7 " 6$ 8 $ : 9 #$ $ 6 $$ 4 # # 4 6 $ 9 TYPICAL ELECTRICAL CHARACTERISTICS : $ " 9$ 9 $$ $ 6$ 6 #$ 4$ 4 $$ #$ # # " " $# 6 " 6$ " 4 # 8 9 ?$$ $ 6$ 7$ 8 9 $ 6 # 6$ " $ 4 $ Figure 6. Gate Charge , " $ #$ $$ $ $ @ * Figure 5. On-Resistance Variation with Temperature 9 $ " 6 , " #$ : , , < # 9 6 Figure 4. On-Resistance versus Drain Current Figure 3. On-Resistance versus Drain Current 8 4 $ # #$ . / Figure 7. Body Diode Forward Voltage http://onsemi.com 291 4 # BSS84LT1 INFORMATION FOR USING THE SOT-23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 4: 7$ 4: 7$ :7 # 4$ 7 4 8 %21! SOT-23 POWER DISSIPATION one can calculate the power dissipation of the device which in this case is 225 milliwatts. The power dissipation of the SOT-23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-23 package, PD can be calculated as follows: PD = PD = 150C - 25C 556C/W = 225 milliwatts The 556C/W for the SOT-23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 292 #! ! Preferred Device ! N-Channel TO-220 and D2PAK http://onsemi.com This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Over-Voltage clamped protection for use in inductive coil drivers applications. Primary uses include Ignition, Direct Fuel Injection, or wherever high voltage and high current switching is required. * Ideal for Coil-On-Plug, IGBT-On-Coil, or Distributorless Ignition System Applications * High Pulsed Current Capability up to 50 A * Gate-Emitter ESD Protection * Temperature Compensated Gate-Collector Voltage Clamp Limits Stress Applied to Load * Integrated ESD Diode Protection * Low Threshold Voltage to Interface Power Loads to Logic or Microprocessor Devices * Low Saturation Voltage * Optional Gate Resistor (RG) 15 AMPERES 350 VOLTS (Clamped) VCE(on) @ 10 A = 1.8 V Max N-Channel C RG G RGE 4 E 4 1 MAXIMUM RATINGS (-55C TJ 175C unless otherwise noted) 3 Symbol Value Unit Collector-Emitter Voltage VCES 380 VDC Collector-Gate Voltage VCER 380 VDC VGE 22 VDC IC 15 50 ADC AAC Rating Gate-Emitter Voltage Collector Current-Continuous @ TC = 25C - Pulsed ESD (Human Body Model) R = 1500 , C = 100 pF ESD ESD (Machine Model) R = 0 , C = 200 pF ESD 800 V PD 150 1.0 Watts W/C TJ, Tstg -55 to 175 C Total Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Range Characteristic Symbol Single Pulse Collector-to-Emitter Avalanche Energy VCC = 50 V, VGE = 5.0 V, Pk IL = 17.4 A, L = 2.0 mH, Starting TJ = 25C VCC = 50 V, VGE = 5.0 V, Pk IL = 14.2 A, L = 2.0 mH, Starting TJ = 150C EAS Semiconductor Components Industries, LLC, 2001 March, 2001 - Rev. 4 1 D2PAK CASE 418B STYLE 4 TO-220AB CASE 221A STYLE 9 2 MARKING DIAGRAMS & PIN ASSIGNMENTS 3 4 Collector 4 Collector kV 8.0 UNCLAMPED COLLECTOR-TO-EMITTER AVALANCHE CHARACTERISTICS (-55C TJ 175C) Reverse Avalanche Energy VCC = 100 V, VGE = 20 V, L = 3.0 mH, Pk IL = 25.8 A, Starting TJ = 25C 2 G15N35CL YWW G15N35CL YWW 1 Gate 3 Emitter 2 Collector Value Unit 1 Gate 3 Emitter 2 Collector G15N35CL = Device Code Y = Year WW = Work Week mJ ORDERING INFORMATION 300 200 EAS(R) mJ Device Package Shipping MGP15N35CL TO-220 50 Units/Rail MGB15N35CLT4 D2PAK 800 Tape & Reel 1000 Preferred devices are recommended choices for future use and best overall value. 293 Publication Order Number: MGP15N35CL/D MGP15N35CL, MGB15N35CL THERMAL CHARACTERISTICS Characteristic Symbol Unit C/W RJC 1.0 TO-220 RJA 62.5 D2PAK (Note 1.) RJA 50 TL 275 Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient Value Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds C ELECTRICAL CHARACTERISTICS Characteristic Symbol Test Conditions Temperature Min Typ Max Unit BVCES IC = 2.0 mA TJ = -40C 40 C to 150C 320 350 380 VDC IC = 10 mA TJ = -40C to 150C 330 360 380 TJ = 25C - 1.5 20 TJ = 150C - 10 40* TJ = -40C - 0.7 1.5 TJ = 25C - 0.35 1.0 TJ = 150C - 8.0 15* TJ = -40C - 0.05 0.5 TJ = 25C 25 33 50 TJ = 150C 25 36 50 TJ = -40C 25 30 50 OFF CHARACTERISTICS Collector-Emitter Collector Emitter Clamp Clam Voltage Zero Gate Voltage g Collector Current ICES VCE = 300 V, V VGE = 0 V Reverse Collector-Emitter Leakage g Current IECS VCE = -24 24 V Reverse Collector-Emitter Clamp Voltage g BVCES(R) IC = -75 75 mA A Gate-Emitter Clamp Voltage Gate-Emitter Leakage Current Gate Resistor (Optional) Gate Emitter Resistor ADC mA VDC BVGES IG = 5.0 mA TJ = -40C to 150C 17 20 22 VDC IGES VGE = 10 V TJ = -40C to 150C 384 600 1000 ADC RG - TJ = -40C to 150C - 70 - RGE - TJ = -40C to 150C 10 16 26 k TJ = 25C 1.4 1.7 2.0 VDC TJ = 150C 0.75 1.1 1.4 TJ = -40C 1.6 1.9 2.1* - - 4.4 - ON CHARACTERISTICS (Note 2.) g Gate Threshold Voltage VGE(th) IC = 1.0 1 0 mA, A VGE = VCE Threshold Temperature Coefficient (Negative) - - 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. *Maximum Value of Characteristic across Temperature Range. http://onsemi.com 294 mV/C MGP15N35CL, MGB15N35CL ELECTRICAL CHARACTERISTICS (continued) Characteristic Symbol Test Conditions Temperature Min Typ Max Unit TJ = 25C 1.0 1.3 1.6 VDC TJ = 150C 0.9 1.2 1.5 TJ = -40C 1.1 1.4 1.7* TJ = 25C 1.3 1.6 1.9 TJ = 150C 1.2 1.5 1.8 TJ = -40C 1.3 1.6 1.9* TJ = 25C 1.6 1.95 2.25 TJ = 150C 1.7 2.0 2.3* TJ = -40C 1.6 1.9 2.2 TJ = 25C 1.9 2.2 2.5 TJ = 150C 2.1 2.4 2.7* TJ = -40C 1.85 2.15 2.45 ON CHARACTERISTICS (continued) (Note 3.) g Collector-to-Emitter On-Voltage VCE(on) IC = 6.0 6 0 A, A VGE = 4.0 V IC = 10 A, A VGE = 4.0 V IC = 15 A, A VGE = 4.0 V IC = 20 A, A VGE = 4.0 V IC = 25 A, A VGE = 4.0 V Collector-to-Emitter On-Voltage Forward Transconductance TJ = 25C 2.1 2.5 2.9 TJ = 150C 2.5 2.9 3.3* TJ = -40C 2.0 2.4 2.8 VCE(on) IC = 10 A, VGE = 4.5 V TJ = 150C - 1.5 1.8 VDC gfs VCE = 5.0 V, IC = 6.0 A TJ = -40C to 150C 8.0 15 25 Mhos - 1000 1300 pF VCC = 25 V V, VGE = 0 V f = 1.0 MHz TJ = -40C 40C to 150C - 100 130 - 5.0 8.0 TJ = 25C - 4.0 10 TJ = 150C - 4.5 10 TJ = 25C - 7.0 10 TJ = 150C - 10 15* TJ = 25C - 4.0 10 TJ = 150C - 4.5 10 TJ = 25C - 13 20 TJ = 150C - 16 20 TJ = 25C - 1.0 1.5 TJ = 150C - 1.0 1.5 TJ = 25C - 4.5 6.0 TJ = 150C - 5.0 6.0 DYNAMIC CHARACTERISTICS Input Capacitance CISS Output Capacitance COSS Transfer Capacitance CRSS SWITCHING CHARACTERISTICS (Note 3.) ( ) Turn-Off Delayy Time (Inductive) Fall Time ((Inductive)) Turn-Off Delay y Time ((Resistive)) td(off) VCC = 300 V,, IC = 6.5 A RG = 1 1.0 0 k k, L = 300 H H tf VCC = 300 V,, IC = 6.5 A RG = 1 1.0 0 k k, L = 300 H H td(off) VCC = 300 V,, IC = 6.5 A RG = 1 1.0 0 k k, RL = 46 , Fall Time ((Resistive)) tf VCC = 300 V,, IC = 6.5 A RG = 1 1.0 0 k k, RL = 46 , Turn-On Delay y Time td(on) VCC = 10 V,, IC = 6.5 A RG = 1 1.0 0 k k, RL = 1 1.5 5 Rise Time tr VCC = 10 V,, IC = 6.5 A RG = 1 1.0 0 k k, RL = 1 1.5 5 3. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. *Maximum Value of Characteristic across Temperature Range. http://onsemi.com 295 Sec Sec Sec MGP15N35CL, MGB15N35CL TYPICAL ELECTRICAL CHARACTERISTICS (unless otherwise noted) 60 VGE = 10.0 V IC, COLLECTOR CURRENT (AMPS) IC, COLLECTOR CURRENT (AMPS) 60 VGE = 4.5 V 50 VGE = 5.0 V 40 VGE = 4.0 V 30 TJ = 25C VGE = 3.5 V 20 VGE = 3.0 V 10 VGE = 2.5 V 0 1 3 2 5 4 7 6 VGE = 5.0 V 40 VGE = 4.0 V 30 TJ = 150C VGE = 3.5 V 20 VGE = 3.0 V 10 8 VGE = 2.5 V 0 3 4 5 6 7 8 Figure 1. Output Characteristics Figure 2. Output Characteristics VCE = 10 V 20 15 TJ = 150C 10 TJ = 25C TJ = -40C 5 0 0 2 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) 25 1 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) 30 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VGE, GATE TO EMITTER VOLTAGE (VOLTS) 4.0 3.5 VGE = 5.0 V 3.0 IC = 25 A IC = 20 A 2.5 2.0 1.5 1.0 IC = 15 A 0.5 0.0 -50 IC = 5 A IC = 10 A -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (C) Figure 3. Transfer Characteristics Figure 4. Collector-to-Emitter Saturation Voltage vs. Junction Temperature 10000 2.5 THRESHOLD VOLTAGE (VOLTS) C, CAPACITANCE (pF) VGE = 4.5 V 50 0 0 IC, COLLECTOR CURRENT (AMPS) VGE = 10.0 V Ciss 1000 Coss 100 10 Crss 1 0 20 40 60 80 100 120 140 160 180 200 Mean + 4 IC = 1 mA Mean 2.0 1.5 Mean - 4 1.0 0.5 0.0 -50 -25 0 25 50 75 100 125 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) TEMPERATURE (C) Figure 5. Capacitance Variation Figure 6. Threshold Voltage vs. Temperature http://onsemi.com 296 150 MGP15N35CL, MGB15N35CL 30 VCC = 50 V VGE = 5.0 V RG = 1000 25 IL, LATCH CURRENT (AMPS) IL, LATCH CURRENT (AMPS) 30 20 T = 25C 15 10 T = 150C 5 0 0 2 4 6 8 15 L = 3.0 mH 10 L = 6.0 mH 5 -25 0 25 50 75 100 125 150 INDUCTOR (mH) TEMPERATURE (C) Figure 7. Minimum Open Secondary Latch Current vs. Inductor Figure 8. Minimum Open Secondary Latch Current vs. Temperature 175 30 VCC = 50 V VGE = 5.0 V RG = 1000 T = 25C 25 IL, LATCH CURRENT (AMPS) IL, LATCH CURRENT (AMPS) L = 2.0 mH 20 0 -50 10 30 20 15 T = 150C 10 5 0 0 2 4 6 8 8 20 L = 3.0 mH 15 L = 6.0 mH 10 5 -25 0 25 50 75 100 125 150 TEMPERATURE (C) Figure 9. Typical Open Secondary Latch Current vs. Inductor Figure 10. Typical Open Secondary Latch Current vs. Temperature 175 14 VCC = 300 V VGE = 5.0 V RG = 1000 IC = 10 A L = 300 H tf 12 tf td(off) 6 4 2 0 -50 25 INDUCTOR (mH) SWITCHING TIME (S) 10 VCC = 50 V VGE = 5.0 V RG = 1000 L = 2.0 mH 0 -50 10 12 SWITCHING TIME (S) VCC = 50 V VGE = 5.0 V RG = 1000 25 10 VCC = 300 V VGE = 5.0 V RG = 1000 TJ = 150C L = 300 H 8 6 td(off) 4 2 0 -25 0 25 50 75 100 125 150 0 2 4 6 8 10 12 14 TC, CASE TEMPERATURE (C) IC, COLLECTOR CURRENT (AMPS) Figure 11. Switching Speed vs. Case Temperature Figure 12. Switching Speed vs. Collector Current http://onsemi.com 297 16 MGP15N35CL, MGB15N35CL 14 14 VCC = 300 V VGE = 5.0 V TJ = 25C IC = 10 A L = 300 H 10 8 12 SWITCHING TIME (S) SWITCHING TIME (S) 12 tf 6 td(off) 4 2 tf 10 VCC = 300 V VGE = 5.0 V TJ = 150C IC = 10 A L = 300 H 8 6 td(off) 4 2 0 250 750 500 0 250 1000 500 750 1000 RG, EXTERNAL GATE RESISTANCE () RG, EXTERNAL GATE RESISTANCE () Figure 13. Switching Speed vs. External Gate Resistance Figure 14. Switching Speed vs. External Gate Resistance R(t), TRANSIENT THERMAL RESISTANCE (C/Watt) 10 Duty Cycle = 0.5 1 0.2 0.1 0.05 0.02 0.1 0.01 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT T1 P(pk) t1 Single Pulse t2 DUTY CYCLE, D = t1/t2 0.01 0.00001 0.0001 0.001 0.1 0.01 TJ(pk) - TA = P(pk) RJA(t) RJC R(t) for t 0.2 s 1 t,TIME (S) Figure 15. Transient Thermal Resistance (Non-normalized Junction-to-Ambient mounted on fixture in Figure 16) http://onsemi.com 298 10 100 1000 MGP15N35CL, MGB15N35CL 1.5 4 4 0.125 4 Figure 16. Test Fixture for Transient Thermal Curve (48 square inches of 1/8, thick aluminum) 100 COLLECTOR CURRENT (AMPS) COLLECTOR CURRENT (AMPS) 100 DC 100 s 10 1 ms 10 ms 1 100 ms 0.1 0.01 1 10 100 1000 DC 10 100 s 1 1 ms 10 ms 100 ms 0.1 0.01 1 10 100 1000 COLLECTOR-EMITTER VOLTAGE (VOLTS) COLLECTOR-EMITTER VOLTAGE (VOLTS) Figure 17. Single Pulse Safe Operating Area (Mounted on an Infinite Heatsink at TC = 255C) Figure 18. Single Pulse Safe Operating Area (Mounted on an Infinite Heatsink at TC = 1255C) http://onsemi.com 299 MGP15N35CL, MGB15N35CL 100 t1 = 1 ms, D = 0.05 t1 = 2 ms, D = 0.10 DC 10 t1 = 3 ms, D = 0.30 1 P(pk) 0.1 t1 t2 DUTY CYCLE, D = t1/t2 0.01 1 10 100 1000 COLLECTOR CURRENT (AMPS) COLLECTOR CURRENT (AMPS) 100 t1 = 1 ms, D = 0.05 DC t1 = 2 ms, D = 0.10 10 t1 = 3 ms, D = 0.30 1 P(pk) t1 0.1 t2 DUTY CYCLE, D = t1/t2 0.01 1 10 100 1000 COLLECTOR-EMITTER VOLTAGE (VOLTS) COLLECTOR-EMITTER VOLTAGE (VOLTS) Figure 19. Pulse Train Safe Operating Area (Mounted on an Infinite Heatsink at TC = 255C) Figure 20. Pulse Train Safe Operating Area (Mounted on an Infinite Heatsink at TC = 1255C) http://onsemi.com 300 # Preferred Device N-Channel TO-220 and D2PAK http://onsemi.com This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Over-Voltage clamped protection for use in inductive coil drivers applications. Primary uses include Ignition, Direct Fuel Injection, or wherever high voltage and high current switching is required. * Ideal for Coil-On-Plug, IGBT-On-Coil, or Distributorless Ignition System Applications * High Pulsed Current Capability up to 50 A * Gate-Emitter ESD Protection * Temperature Compensated Gate-Collector Voltage Clamp Limits Stress Applied to Load * Integrated ESD Diode Protection * Low Threshold Voltage to Interface Power Loads to Logic or Microprocessor Devices * Low Saturation Voltage * Optional Gate Resistor (RG) 15 AMPERES 410 VOLTS (Clamped) VCE(on) @ 10 A = 1.8 V Max N-Channel C RG G RGE 4 E 4 1 MAXIMUM RATINGS (-55C TJ 175C unless otherwise noted) 3 Symbol Value Unit Collector-Emitter Voltage VCES 380 VDC Collector-Gate Voltage VCER 380 VDC VGE 22 VDC IC 15 50 ADC AAC Rating Gate-Emitter Voltage Collector Current-Continuous @ TC = 25C - Pulsed ESD (Human Body Model) R = 1500 , C = 100 pF ESD ESD (Machine Model) R = 0 , C = 200 pF ESD 800 V PD 150 1.0 Watts W/C TJ, Tstg -55 to 175 C Total Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Range Characteristic Symbol Single Pulse Collector-to-Emitter Avalanche Energy VCC = 50 V, VGE = 5.0 V, Pk IL = 17.4 A, L = 2.0 mH, Starting TJ = 25C VCC = 50 V, VGE = 5.0 V, Pk IL = 14.2 A, L = 2.0 mH, Starting TJ = 150C EAS Semiconductor Components Industries, LLC, 2001 March, 2001 - Rev. 5 1 D2PAK CASE 418B STYLE 4 TO-220AB CASE 221A STYLE 9 2 3 MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Collector 4 Collector kV 8.0 Value G15N40CL YWW G15N40CL YWW 1 Gate UNCLAMPED COLLECTOR-TO-EMITTER AVALANCHE CHARACTERISTICS (-55C TJ 175C) Reverse Avalanche Energy VCC = 100 V, VGE = 20 V, L = 3.0 mH, Pk IL = 25.8 A, Starting TJ = 25C 2 Unit 3 Emitter 2 Collector 1 Gate 3 Emitter 2 Collector G15N40CL = Device Code Y = Year WW = Work Week mJ ORDERING INFORMATION 300 200 EAS(R) mJ Device Package Shipping MGP15N40CL TO-220 50 Units/Rail MGB15N40CLT4 D2PAK 800 Tape & Reel 1000 Preferred devices are recommended choices for future use and best overall value. 301 Publication Order Number: MGP15N40CL/D MGP15N40CL, MGB15N40CL THERMAL CHARACTERISTICS Characteristic Symbol Unit C/W RJC 1.0 TO-220 RJA 62.5 D2PAK (Note 1.) RJA 50 TL 275 Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient Value Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds C ELECTRICAL CHARACTERISTICS Characteristic Symbol Test Conditions Temperature Min Typ Max Unit BVCES IC = 2.0 mA TJ = -40C 40 C to 150C 320 350 380 VDC IC = 10 mA TJ = -40C to 150C 330 360 380 TJ = 25C - 1.5 20 TJ = 150C - 10 40* TJ = -40C - 0.7 1.5 TJ = 25C - 0.35 1.0 TJ = 150C - 8.0 15* TJ = -40C - 0.05 0.5 TJ = 25C 25 33 50 TJ = 150C 25 36 50 TJ = -40C 25 30 50 OFF CHARACTERISTICS Collector-Emitter Collector Emitter Clamp Clam Voltage Zero Gate Voltage g Collector Current ICES VCE = 300 V, V VGE = 0 V Reverse Collector-Emitter Leakage g Current IECS VCE = -24 24 V Reverse Collector-Emitter Clamp Voltage g BVCES(R) IC = -75 75 mA A Gate-Emitter Clamp Voltage Gate-Emitter Leakage Current Gate Resistor (Optional) Gate Emitter Resistor ADC mA VDC BVGES IG = 5.0 mA TJ = -40C to 150C 17 20 22 VDC IGES VGE = 10 V TJ = -40C to 150C 384 600 1000 ADC RG - TJ = -40C to 150C - 70 - RGE - TJ = -40C to 150C 10 16 26 k TJ = 25C 1.4 1.7 2.0 VDC TJ = 150C 0.75 1.1 1.4 TJ = -40C 1.6 1.9 2.1* - - 4.4 - ON CHARACTERISTICS (Note 2.) g Gate Threshold Voltage VGE(th) IC = 1.0 1 0 mA, A VGE = VCE Threshold Temperature Coefficient (Negative) - - 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. *Maximum Value of Characteristic across Temperature Range. http://onsemi.com 302 mV/C MGP15N40CL, MGB15N40CL ELECTRICAL CHARACTERISTICS (continued) Characteristic Symbol Test Conditions Temperature Min Typ Max Unit TJ = 25C 1.0 1.3 1.6 VDC TJ = 150C 0.9 1.2 1.5 TJ = -40C 1.1 1.4 1.7* TJ = 25C 1.3 1.6 1.9 TJ = 150C 1.2 1.5 1.8 TJ = -40C 1.3 1.6 1.9* TJ = 25C 1.6 1.95 2.25 TJ = 150C 1.7 2.0 2.3* TJ = -40C 1.6 1.9 2.2 TJ = 25C 1.9 2.2 2.5 TJ = 150C 2.1 2.4 2.7* TJ = -40C 1.85 2.15 2.45 ON CHARACTERISTICS (continued) (Note 3.) g Collector-to-Emitter On-Voltage VCE(on) IC = 6.0 6 0 A, A VGE = 4.0 V IC = 10 A, A VGE = 4.0 V IC = 15 A, A VGE = 4.0 V IC = 20 A, A VGE = 4.0 V IC = 25 A, A VGE = 4.0 V Collector-to-Emitter On-Voltage Forward Transconductance TJ = 25C 2.1 2.5 2.9 TJ = 150C 2.5 2.9 3.3* TJ = -40C 2.0 2.4 2.8 VCE(on) IC = 10 A, VGE = 4.5 V TJ = 150C - 1.5 1.8 VDC gfs VCE = 5.0 V, IC = 6.0 A TJ = -40C to 150C 8.0 15 25 Mhos - 1000 1300 pF VCC = 25 V V, VGE = 0 V f = 1.0 MHz TJ = -40C 40C to 150C - 100 130 - 5.0 8.0 TJ = 25C - 4.0 10 TJ = 150C - 4.5 10 TJ = 25C - 7.0 10 TJ = 150C - 10 15* TJ = 25C - 4.0 10 TJ = 150C - 4.5 10 TJ = 25C - 13 20 TJ = 150C - 16 20 TJ = 25C - 1.0 1.5 TJ = 150C - 1.0 1.5 TJ = 25C - 4.5 6.0 TJ = 150C - 5.0 6.0 DYNAMIC CHARACTERISTICS Input Capacitance CISS Output Capacitance COSS Transfer Capacitance CRSS SWITCHING CHARACTERISTICS (Note 3.) ( ) Turn-Off Delayy Time (Inductive) Fall Time ((Inductive)) Turn-Off Delay y Time ((Resistive)) td(off) VCC = 300 V,, IC = 6.5 A RG = 1 1.0 0 k k, L = 300 H H tf VCC = 300 V,, IC = 6.5 A RG = 1 1.0 0 k k, L = 300 H H td(off) VCC = 300 V,, IC = 6.5 A RG = 1 1.0 0 k k, RL = 46 , Fall Time ((Resistive)) tf VCC = 300 V,, IC = 6.5 A RG = 1 1.0 0 k k, RL = 46 , Turn-On Delay y Time td(on) VCC = 10 V,, IC = 6.5 A RG = 1 1.0 0 k k, RL = 1 1.5 5 Rise Time tr VCC = 10 V,, IC = 6.5 A RG = 1 1.0 0 k k, RL = 1 1.5 5 3. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. *Maximum Value of Characteristic across Temperature Range. http://onsemi.com 303 Sec Sec Sec MGP15N40CL, MGB15N40CL TYPICAL ELECTRICAL CHARACTERISTICS (unless otherwise noted) 60 VGE = 10.0 V IC, COLLECTOR CURRENT (AMPS) IC, COLLECTOR CURRENT (AMPS) 60 VGE = 4.5 V 50 VGE = 5.0 V 40 VGE = 4.0 V 30 TJ = 25C VGE = 3.5 V 20 VGE = 3.0 V 10 VGE = 2.5 V 0 1 3 2 5 4 7 6 VGE = 5.0 V 40 VGE = 4.0 V 30 TJ = 150C VGE = 3.5 V 20 VGE = 3.0 V 10 8 VGE = 2.5 V 0 3 4 5 6 7 8 Figure 1. Output Characteristics Figure 2. Output Characteristics VCE = 10 V 20 15 TJ = 150C 10 TJ = 25C TJ = -40C 5 0 0 2 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) 25 1 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) 30 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VGE, GATE TO EMITTER VOLTAGE (VOLTS) 4.0 3.5 VGE = 5.0 V 3.0 IC = 25 A IC = 20 A 2.5 2.0 1.5 1.0 IC = 15 A 0.5 0.0 -50 IC = 5 A IC = 10 A -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (C) Figure 3. Transfer Characteristics Figure 4. Collector-to-Emitter Saturation Voltage vs. Junction Temperature 10000 2.5 THRESHOLD VOLTAGE (VOLTS) C, CAPACITANCE (pF) VGE = 4.5 V 50 0 0 IC, COLLECTOR CURRENT (AMPS) VGE = 10.0 V Ciss 1000 Coss 100 10 Crss 1 0 20 40 60 80 100 120 140 160 180 200 Mean + 4 IC = 1 mA Mean 2.0 1.5 Mean - 4 1.0 0.5 0.0 -50 -25 0 25 50 75 100 125 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) TEMPERATURE (C) Figure 5. Capacitance Variation Figure 6. Threshold Voltage vs. Temperature http://onsemi.com 304 150 MGP15N40CL, MGB15N40CL 30 VCC = 50 V VGE = 5.0 V RG = 1000 25 IL, LATCH CURRENT (AMPS) IL, LATCH CURRENT (AMPS) 30 20 T = 25C 15 10 T = 150C 5 0 0 2 4 6 8 15 L = 3.0 mH 10 L = 6.0 mH 5 -25 0 25 50 75 100 125 150 INDUCTOR (mH) TEMPERATURE (C) Figure 7. Minimum Open Secondary Latch Current vs. Inductor Figure 8. Minimum Open Secondary Latch Current vs. Temperature 175 30 VCC = 50 V VGE = 5.0 V RG = 1000 T = 25C 25 IL, LATCH CURRENT (AMPS) IL, LATCH CURRENT (AMPS) L = 2.0 mH 20 0 -50 10 30 20 15 T = 150C 10 5 0 0 2 4 6 8 8 20 L = 3.0 mH 15 L = 6.0 mH 10 5 -25 0 25 50 75 100 125 150 TEMPERATURE (C) Figure 9. Typical Open Secondary Latch Current vs. Inductor Figure 10. Typical Open Secondary Latch Current vs. Temperature 175 14 VCC = 300 V VGE = 5.0 V RG = 1000 IC = 10 A L = 300 H tf 12 tf td(off) 6 4 2 0 -50 25 INDUCTOR (mH) SWITCHING TIME (S) 10 VCC = 50 V VGE = 5.0 V RG = 1000 L = 2.0 mH 0 -50 10 12 SWITCHING TIME (S) VCC = 50 V VGE = 5.0 V RG = 1000 25 10 VCC = 300 V VGE = 5.0 V RG = 1000 TJ = 150C L = 300 H 8 6 td(off) 4 2 0 -25 0 25 50 75 100 125 150 0 2 4 6 8 10 12 14 TC, CASE TEMPERATURE (C) IC, COLLECTOR CURRENT (AMPS) Figure 11. Switching Speed vs. Case Temperature Figure 12. Switching Speed vs. Collector Current http://onsemi.com 305 16 MGP15N40CL, MGB15N40CL 14 14 VCC = 300 V VGE = 5.0 V TJ = 25C IC = 10 A L = 300 H 10 8 12 SWITCHING TIME (S) SWITCHING TIME (S) 12 tf 6 td(off) 4 2 tf 10 VCC = 300 V VGE = 5.0 V TJ = 150C IC = 10 A L = 300 H 8 6 td(off) 4 2 0 250 750 500 0 250 1000 500 750 1000 RG, EXTERNAL GATE RESISTANCE () RG, EXTERNAL GATE RESISTANCE () Figure 13. Switching Speed vs. External Gate Resistance Figure 14. Switching Speed vs. External Gate Resistance R(t), TRANSIENT THERMAL RESISTANCE (C/Watt) 10 Duty Cycle = 0.5 1 0.2 0.1 0.05 0.02 0.1 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT T1 P(pk) 0.01 t1 Single Pulse t2 DUTY CYCLE, D = t1/t2 0.01 0.00001 0.0001 0.001 0.1 0.01 TJ(pk) - TA = P(pk) RJA(t) RJC R(t) for t 0.2 s 1 t,TIME (S) Figure 15. Transient Thermal Resistance (Non-normalized Junction-to-Ambient mounted on fixture in Figure 16) http://onsemi.com 306 10 100 1000 MGP15N40CL, MGB15N40CL 1.5 4 4 0.125 4 Figure 16. Test Fixture for Transient Thermal Curve (48 square inches of 1/8, thick aluminum) 100 COLLECTOR CURRENT (AMPS) COLLECTOR CURRENT (AMPS) 100 DC 100 s 10 1 ms 10 ms 1 100 ms 0.1 0.01 1 10 100 1000 DC 10 100 s 1 1 ms 10 ms 100 ms 0.1 0.01 1 10 100 1000 COLLECTOR-EMITTER VOLTAGE (VOLTS) COLLECTOR-EMITTER VOLTAGE (VOLTS) Figure 17. Single Pulse Safe Operating Area (Mounted on an Infinite Heatsink at TC = 255C) Figure 18. Single Pulse Safe Operating Area (Mounted on an Infinite Heatsink at TC = 1255C) http://onsemi.com 307 MGP15N40CL, MGB15N40CL 100 t1 = 1 ms, D = 0.05 t1 = 2 ms, D = 0.10 DC 10 t1 = 3 ms, D = 0.30 1 P(pk) 0.1 t1 t2 DUTY CYCLE, D = t1/t2 0.01 1 10 100 1000 COLLECTOR CURRENT (AMPS) COLLECTOR CURRENT (AMPS) 100 t1 = 1 ms, D = 0.05 DC t1 = 2 ms, D = 0.10 10 t1 = 3 ms, D = 0.30 1 P(pk) t1 0.1 t2 DUTY CYCLE, D = t1/t2 0.01 1 10 100 1000 COLLECTOR-EMITTER VOLTAGE (VOLTS) COLLECTOR-EMITTER VOLTAGE (VOLTS) Figure 19. Pulse Train Safe Operating Area (Mounted on an Infinite Heatsink at TC = 255C) Figure 20. Pulse Train Safe Operating Area (Mounted on an Infinite Heatsink at TC = 1255C) http://onsemi.com 308 #)! )! Preferred Device ) ! N-Channel TO-220 and D2PAK http://onsemi.com This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and Over-Voltage clamped protection for use in inductive coil drivers applications. Primary uses include Ignition, Direct Fuel Injection, or wherever high voltage and high current switching is required. * Ideal for IGBT-On-Coil or Distributorless Ignition System Applications * High Pulsed Current Capability up to 50 A * Gate-Emitter ESD Protection * Temperature Compensated Gate-Collector Voltage Clamp Limits Stress Applied to Load * Integrated ESD Diode Protection * Low Threshold Voltage to Interface Power Loads to Logic or Microprocessor Devices * Low Saturation Voltage * Optional Gate Resistor (RG) 19 AMPERES 350 VOLTS (Clamped) VCE(on) @ 10 A = 1.8 V Max N-Channel C G RGE 4 E 4 1 MAXIMUM RATINGS (-55C TJ 175C unless otherwise noted) Rating Symbol Value Unit Collector-Emitter Voltage VCES 380 VDC Collector-Gate Voltage VCER 380 VDC VGE 22 VDC IC 19 50 ADC AAC Gate-Emitter Voltage Collector Current - Continuous @ TC = 25C - Pulsed ESD (Human Body Model) R = 1500 , C = 100 pF ESD ESD (Machine Model) R = 0 , C = 200 pF ESD 800 V PD 165 1.1 Watts W/C TJ, Tstg -55 to 175 C Total Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Range Characteristic Symbol Single Pulse Collector-to-Emitter Avalanche Energy VCC = 50 V, VGE = 5.0 V, Pk IL = 22.4 A, L = 2.0 mH, Starting TJ = 25C VCC = 50 V, VGE = 5.0 V, Pk IL = 17.4 A, L = 2.0 mH, Starting TJ = 150C EAS Semiconductor Components Industries, LLC, 2001 March, 2001 - Rev. 3 3 1 D2PAK CASE 418B STYLE 4 TO-220AB CASE 221A STYLE 9 2 MARKING DIAGRAMS & PIN ASSIGNMENTS 3 4 Collector 4 Collector kV 8.0 Value G19N35CL YWW G19N35CL YWW 1 Gate UNCLAMPED COLLECTOR-TO-EMITTER AVALANCHE CHARACTERISTICS (-55C TJ 175C) Reverse Avalanche Energy VCC = 100 V, VGE = 20 V, L = 3.0 mH, Pk IL = 25.8 A, Starting TJ = 25_C 2 Unit 3 Emitter 2 Collector mJ 1 Gate 3 Emitter 2 Collector G19N35CL = Device Code Y = Year WW = Work Week ORDERING INFORMATION 500 Device Package Shipping MGP19N35CL TO-220 50 Units/Rail MGB19N35CLT4 D2PAK 800 Tape & Reel 300 EAS(R) mJ 1000 Preferred devices are recommended choices for future use and best overall value. 309 Publication Order Number: MGP19N35CL/D MGP19N35CL, MGB19N35CL THERMAL CHARACTERISTICS Characteristic Symbol Unit C/W RJC 0.9 TO-220 RJA 62.5 D2PAK (Note 1.) RJA 50 TL 275 Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient Value Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds C ELECTRICAL CHARACTERISTICS Characteristic Symbol Test Conditions Temperature Min Typ Max Unit BVCES IC = 2.0 mA TJ = -40C to 150C 320 350 380 VDC IC = 10 mA TJ = -40C to 150C 330 360 380 TJ = 25C - 1.5 20 TJ = 150C - 15 40* TJ = -40C - 0.7 1.5 TJ = 25C - 0.35 1.0 TJ = 150C - 10 20* TJ = -40C - 0.05 0.5 TJ = 25C 25 33 50 TJ = 150C 25 36 50 TJ = -40C 25 30 50 OFF CHARACTERISTICS Collector-Emitter Clamp Voltage Zero Gate Voltage g Collector Current ICES VCE = 300 V, V VGE = 0 V Reverse Collector-Emitter Leakage g Current IECS VCE = -24 24 V Reverse Collector-Emitter Clamp Voltage g BVCES(R) IC = -75 75 mA A Gate-Emitter Clamp Voltage Gate-Emitter Leakage Current Gate Resistor (Optional) Gate Emitter Resistor ADC mA VDC BVGES IG = 5.0 mA TJ = -40C to 150C 17 20 22 VDC IGES VGE = 10 V TJ = -40C to 150C 384 500 1000 ADC RG - TJ = -40C to 150C - 70 - RGE - TJ = -40C to 150C 10 20 26 k TJ = 25C 1.4 1.7 2.0 VDC TJ = 150C 0.75 1.1 1.4 TJ = -40C 1.6 1.9 2.1* - - 4.4 - ON CHARACTERISTICS (Note 2.) g Gate Threshold Voltage VGE(th) IC = 1.0 1 0 mA, A VGE = VCE Threshold Temperature Coefficient (Negative) - - 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. *Maximum Value of Characteristic across Temperature Range. http://onsemi.com 310 mV/C MGP19N35CL, MGB19N35CL ELECTRICAL CHARACTERISTICS (continued) Characteristic Symbol Test Conditions Temperature Min Typ Max Unit TJ = 25C 1.0 1.25 1.6 VDC IC = 6.0 6 0 A, A VGE = 4.0 V TJ = 150C 0.8 1.05 1.4 TJ = -40C 1.15 1.4 1.75* TJ = 25C 1.2 1.5 1.8 TJ = 150C 1.0 1.3 1.6 TJ = -40C 1.3 1.6 1.9* ON CHARACTERISTICS (continued) (Note 3.) g Collector-to-Emitter On-Voltage VCE(on) IC = 10 A, A VGE = 4.0 V IC = 15 A, A VGE = 4.0 V IC = 20 A, A VGE = 4.0 V IC = 25 A, A VGE = 4.0 V Collector-to-Emitter On-Voltage Forward Transconductance TJ = 25C 1.5 1.75 2.1 TJ = 150C 1.35 1.65 1.95 TJ = -40C 1.5 1.8 2.1* TJ = 25C 1.7 2.0 2.3 TJ = 150C 1.6 1.9 2.2 TJ = -40C 1.7 2.0 2.3* TJ = 25C 2.0 2.25 2.6 TJ = 150C 2.0 2.3 2.7* TJ = -40C 2.0 2.2 2.6 VCE(on) IC = 10 A, VGE = 4.5 V TJ = 150C - 1.3 1.8 VDC gfs VCE = 5.0 V, IC = 6.0 A TJ = -40C to 150C 8.0 15 25 Mhos - 1500 1800 pF VCC = 25 V V, VGE = 0 V f = 1.0 MHz TJ = -40C 40C to 150C - 130 160 - 6.0 8.0 TJ = 25C - 5.0 10 TJ = 150C - 6.0 10 DYNAMIC CHARACTERISTICS Input Capacitance CISS Output Capacitance COSS Transfer Capacitance CRSS SWITCHING CHARACTERISTICS (Note 3.) ( ) Turn-Off Delayy Time (Inductive) Fall Time ((Inductive)) Turn-Off Delay y Time ((Resistive)) Fall Time ((Resistive)) Turn-On Delay y Time Rise Time td(off) VCC = 300 V,, IC = 10 A RG = 1 1.0 0 k k, L = 300 H H tf VCC = 300 V,, IC = 10 A RG = 1 1.0 0 k k, L = 300 H H td(off) VCC = 300 V,, IC = 6.5 A RG = 1 1.0 0 k k, RL = 46 tf VCC = 300 V,, IC = 6.5 A RG = 1 1.0 0 k k, RL = 46 td(on) VCC = 10 V,, IC = 6.5 A RG = 1 1.0 0 k k, RL = 1 1.5 5 tr VCC = 10 V,, IC = 6.5 A RG = 1 1.0 0 k k, RL = 1 1.5 5 3. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. *Maximum Value of Characteristic across Temperature Range. http://onsemi.com 311 TJ = 25C - 6.0 10 TJ = 150C - 11 15* TJ = 25C - 6.0 10 TJ = 150C - 7.0 10 TJ = 25C - 12 20 TJ = 150C - 18 22* TJ = 25C - 1.5 2.0 TJ = 150C - 1.5 2.0 TJ = 25C - 4.0 6.0 TJ = 150C - 5.0 6.0 Sec Sec Sec MGP19N35CL, MGB19N35CL TYPICAL ELECTRICAL CHARACTERISTICS (unless otherwise noted) 60 IC, COLLECTOR CURRENT (AMPS) IC, COLLECTOR CURRENT (AMPS) 60 VGE = 10.0 V VGE = 4.0 V 50 VGE = 5.0 V 40 VGE = 4.5 V TJ = 25C VGE = 3.5 V 30 20 VGE = 3.0 V 10 VGE = 2.5 V 0 1 3 2 5 4 7 6 VGE = 5.0 V TJ = 150C VGE = 3.5 V 30 VGE = 3.0 V 20 VGE = 2.5 V 10 3 2 4 5 6 7 8 Figure 1. Output Characteristics Figure 2. Output Characteristics VCE = 10 V 50 45 40 35 30 25 TJ = 25C 20 15 10 TJ = 150C 5 TJ = -40C 0 1 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) 0.5 1 1.5 2 2.5 3 3.5 4 4.5 VGE, GATE TO EMITTER VOLTAGE (VOLTS) 5 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) 55 0 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) 0 3.0 VGE = 5.0 V 2.5 IC = 25 A IC = 20 A 2.0 1.5 1.0 IC = 15 A 0.0 -50 IC = 5 A IC = 10 A 0.5 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (C) Figure 3. Transfer Characteristics Figure 4. Collector-to-Emitter Saturation Voltage vs. Junction Temperature 2.5 10000 THRESHOLD VOLTAGE (VOLTS) Ciss 1000 C, CAPACITANCE (pF) VGE = 4.0 V 40 8 60 IC, COLLECTOR CURRENT (AMPS) 50 0 0 Coss 100 Crss 10 1 0 VGE = 4.5 V VGE = 10.0 V 0 20 40 60 80 100 120 2.0 1.5 Mean Mean - 4 1.0 0.5 0.0 -50 140 160 180 IC = 1 mA Mean + 4 -25 0 25 50 75 100 125 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) TEMPERATURE (C) Figure 5. Capacitance Variation Figure 6. Threshold Voltage vs. Temperature http://onsemi.com 312 150 MGP19N35CL, MGB19N35CL 14 14 VCC = 300 V VGE = 5.0 V RG = 1000 IC = 10 A L = 300 H 10 tf 8 6 td(off) 4 0 -50 8 td(off) 6 VCC = 300 V VGE = 5.0 V RG = 1000 TJ = 150C L = 300 H 4 0 -25 0 25 50 75 100 125 0 150 2 4 6 8 10 12 14 TC, CASE TEMPERATURE (C) IC, COLLECTOR CURRENT (AMPS) Figure 7. Switching Speed vs. Case Temperature Figure 8. Switching Speed vs. Collector Current 30 16 30 VCC = 50 V VGE = 5.0 V RG = 1000 25 T = 25C IL, LATCH CURRENT (AMPS) IL, LATCH CURRENT (AMPS) 10 2 2 20 15 T = 150C 10 5 0 0 2 4 6 8 25 L = 2.0 mH 20 15 L = 3.0 mH 10 L = 6.0 mH VCC = 50 V VGE = 5.0 V RG = 1000 5 0 -50 10 -25 0 25 50 75 100 125 150 INDUCTOR (mH) TEMPERATURE (C) Figure 9. Minimum Open Secondary Latch Current vs. Inductor Figure 10. Minimum Open Secondary Latch Current vs. Temperature 30 175 30 25 L = 2.0 mH VCC = 50 V VGE = 5.0 V RG = 1000 T = 25C IL, LATCH CURRENT (AMPS) IL, LATCH CURRENT (AMPS) tf 12 SWITCHING TIME (S) SWITCHING TIME (S) 12 20 15 T = 150C 10 5 0 0 1 2 3 4 5 6 7 8 9 25 L = 3.0 mH 20 L = 6.0 mH 15 10 VCC = 50 V VGE = 5.0 V RG = 1000 5 0 -50 10 -25 0 25 50 75 100 125 150 INDUCTOR (mH) TEMPERATURE (C) Figure 11. Typical Open Secondary Latch vs. Inductor Figure 12. Typical Open Secondary Latch vs. Temperature http://onsemi.com 313 175 MGP19N35CL, MGB19N35CL R(t), TRANSIENT THERMAL RESISTANCE (C/Watt) 10 Duty Cycle = 0.5 1 0.2 0.1 0.05 0.02 0.1 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT T1 P(pk) 0.01 t1 t2 Single Pulse DUTY CYCLE, D = t1/t2 0.01 0.00001 0.0001 0.001 0.1 0.01 TJ(pk) - TA = P(pk) RJA(t) RJC R(t) for t 0.2 s 1 10 t,TIME (S) Figure 13. Transient Thermal Resistance (Non-normalized Junction-to-Ambient mounted on fixture in Figure 14) 1.5 4 4 0.125 4 Figure 14. Test Fixture for Transient Thermal Curve (48 square inches of 1/8, thick aluminum) http://onsemi.com 314 100 1000 MGP19N35CL, MGB19N35CL 100 DC COLLECTOR CURRENT (AMPS) COLLECTOR CURRENT (AMPS) 100 100 s 10 1 ms 1 10 ms 100 ms 0.1 0.01 1 10 100 1000 1 ms 10 ms 100 ms 0.1 10 100 1000 COLLECTOR-EMITTER VOLTAGE (VOLTS) Figure 15. Single Pulse Safe Operating Area (Mounted on an Infinite Heatsink at TC = 255C) Figure 16. Single Pulse Safe Operating Area (Mounted on an Infinite Heatsink at TC = 1255C) 100 t1 = 1 ms D = 0.05 COLLECTOR CURRENT (AMPS) COLLECTOR CURRENT (AMPS) 1 COLLECTOR-EMITTER VOLTAGE (VOLTS) DC t1 = 2 ms D = 0.10 10 t1 = 3 ms D = 0.30 1 P(pk) t1 t2 DUTY CYCLE, D = t1/t2 0.01 1 100 s 10 0.01 1 100 0.1 DC 10 100 1000 DC t1 = 1 ms D = 0.05 10 t1 = 2 ms D = 0.10 t1 = 3 ms D = 0.30 1 P(pk) t1 0.1 t2 DUTY CYCLE, D = t1/t2 0.01 1 10 100 1000 COLLECTOR-EMITTER VOLTAGE (VOLTS) COLLECTOR-EMITTER VOLTAGE (VOLTS) Figure 17. Pulse Train Safe Operating Area (Mounted on an Infinite Heatsink at TC = 255C) Figure 18. Pulse Train Safe Operating Area (Mounted on an Infinite Heatsink at TC = 1255C) http://onsemi.com 315 ( Preferred Device #$%& '( " N-Channel SOT-23 These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in space sensitive power management circuitry. Typical applications are dc-dc converters and power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Miniature SOT-23 Surface Mount Package Saves Board Space http://onsemi.com 750 mAMPS 20 VOLTS RDS(on) = 85 m N-Channel 4 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Symbol Value Unit VDSS 20 Vdc VGS 8.0 Vdc Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (tp 10 s) ID IDM 750 2000 Total Power Dissipation @ TA = 25C PD 400 mW Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C RJA 300 C/W TL 260 C Thermal Resistance - Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds mA # MARKING DIAGRAM 3 SOT-23 CASE 318 STYLE 21 1 NE W 2 NE W = Device Code = Work Week PIN ASSIGNMENT 3 ()% 1 2 )'1 ;(1 ORDERING INFORMATION Device Package Shipping MGSF1N02ELT1 SOT-23 3000 Tape & Reel MGSF1N02ELT3 SOT-23 10,000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 316 Publication Order Number: MGSF1N02ELT1/D MGSF1N02ELT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 20 - - Vdc - - - - 1.0 10 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Adc Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Source Leakage Current (VGS = 8.0 Vdc, VDS = 0 Vdc) IGSS - - 0.1 Adc Gate-Source Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) 0.5 - 1.0 Vdc Static Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 1.0 A) (VGS = 2.5 Vdc, ID = 0.75 A) rDS(on) - - - - 0.085 0.115 ON CHARACTERISTICS (Note 1.) Ohms DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 5.0 Vdc, VGS = 0 V, f = 1.0 Mhz) Ciss - 160 - pF Output Capacitance (VDS = 5.0 Vdc, VGS = 0 V, f = 1.0 Mhz) Coss - 130 - Transfer Capacitance (VDG = 5.0 Vdc, VGS = 0 V, f = 1.0 Mhz) Crss - 60 - td(on) - 6.0 - tr - 26 - td(off) - 117 - tf - 105 - QT - 6500 - pC A SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time (VDD = 5 Vdc, ID = 1.0 Adc, RL = 5 , RG = 6 ) Turn-Off Delay Time Fall Time Total Gate Charge (VDS = 16 Vdc, ID = 1.2 Adc, VGS = 4.0 Vdc) ns SOURCE-DRAIN DIODE CHARACTERISTICS Continuous Current IS - - 0.6 Pulsed Current ISM - - 0.75 Forward Voltage (Note 2.) (VGS = 0 Vdc, IS = 0.6 Adc) VSD - - 1.2 V 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. TYPICAL ELECTRICAL CHARACTERISTICS #$ # #$ # 8 , " $ $ #$ $$ $ ##$ 9 :$ # 6 $ # 8 9 " #$ 6 # $ 8 6 : # $ $ # Figure 1. Transfer Characteristics Figure 2. On-Region Characteristics http://onsemi.com 317 #$ MGSF1N02ELT1 # " #$ 8 , " $ 9 6 # #$ ?$$ 8 9 6 # # 6 9 8 # 6 9 8 # TYPICAL ELECTRICAL CHARACTERISTICS 6 8 #$ 9 ?$$ 6 # < 6 " #$ " 4 # 7 8 : 9 ?$ #$ $ #$ :$ #$ # 9 6 8 # 6 $ # 6 4 # " # $ " 9 , " #$ 6 # 9 8 @ * Figure 6. Gate Charge Figure 5. On-Resistance Variation Over Temperature $ 6$ #$ ?$$ *. , " $ C " A , " #$ 6 4$ 4 #$ # %!! !! $ (!! $ 8 , , 9 Figure 4. On-Resistance versus Drain Current " 6$ " # $ , " $ Figure 3. On-Resistance versus Drain Current 9 " 6$ # # 4 6 $ 9 : 8 7 # 4 6 $ 9 : 8 . / Figure 7. Body Diode Forward Voltage Figure 8. Capacitance Variation http://onsemi.com 318 7 MGSF1N02ELT1 INFORMATION FOR USING THE SOT-23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 4: 7$ 4: 7$ :7 # 4$ 7 4 8 %21! SOT-23 POWER DISSIPATION one can calculate the power dissipation of the device which in this case is 416 milliwatts. The power dissipation of the SOT-23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-23 package, PD can be calculated as follows: PD = PD = 150C - 25C 300C/W = 416 milliwatts The 300C/W for the SOT-23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 416 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 319 ( Preferred Device #$%& '( " N-Channel SOT-23 These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in space sensitive power management circuitry. Typical applications are dc-dc converters and power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Miniature SOT-23 Surface Mount Package Saves Board Space http://onsemi.com 750 mAMPS 20 VOLTS RDS(on) = 90 m N-Channel 4 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit VDSS 20 Vdc VGS 20 Vdc Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (tp 10 s) ID IDM 750 2000 mA Total Power Dissipation @ TA = 25C PD 400 mW Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C RJA 300 C/W TL 260 C Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Thermal Resistance - Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds # MARKING DIAGRAM 3 SOT-23 CASE 318 STYLE 21 1 N2 W 2 N2 W = Device Code = Work Week PIN ASSIGNMENT 3 ()% 1 2 )'1 ;(1 ORDERING INFORMATION Device Package Shipping MGSF1N02LT1 SOT-23 3000 Tape & Reel MGSF1N02LT3 SOT-23 10,000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 320 Publication Order Number: MGSF1N02LT1/D MGSF1N02LT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 20 - - Vdc - - - - 1.0 10 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 10 Adc) Adc Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS - - 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) 1.0 1.7 2.4 Vdc Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 1.2 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) rDS(on) - - 0.075 0.115 0.090 0.130 ON CHARACTERISTICS (Note 1.) Ohms DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 5.0 Vdc) Ciss - 125 - Output Capacitance (VDS = 5.0 Vdc) Coss - 120 - Transfer Capacitance (VDG = 5.0 Vdc) Crss - 45 - td(on) - 2.5 - pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time ns tr - 1.0 - td(off) - 16 - tf - 8.0 - QT - 6000 - pC IS - - 0.6 A Pulsed Current ISM - - 0.75 Forward Voltage (Note 2.) VSD - 0.8 - (VDD = 15 Vdc, ID = 1.0 Adc, RL = 50 ) Turn-Off Delay Time Fall Time Gate Charge (See Figure 6) SOURCE-DRAIN DIODE CHARACTERISTICS Continuous Current V 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. TYPICAL ELECTRICAL CHARACTERISTICS 4 " #$ # $$ $ , " $ $ $ # #$ 4#$ 4$ # " 4 $ #:$ #$ $ #$ 6 #$ ##$ 4 4$ # 4 6 $ 9 : 8 Figure 1. Transfer Characteristics Figure 2. On-Region Characteristics http://onsemi.com 321 7 MGSF1N02LT1 # $ 8 9 " 6$ 6 #$ # $$ 8 9 6 4 # 6 $ 9 : 8 7 TYPICAL ELECTRICAL CHARACTERISTICS 6 4 $ # " 7 #$ 8 : $$ 9 $ 6 # 6 9 < 9 " " # 6 4 " 6$ " # 7 8 : 9 ?$$ $ 6$ 7$ 8 9 6 8 # 9 6 6$ " # # # 4 6 $ 9 @ * Figure 6. Gate Charge Figure 5. On-Resistance Variation with Temperature , " $ #$ $$ *. # " 9 , " #$ , , Figure 4. On-Resistance versus Drain Current Figure 3. On-Resistance versus Drain Current $ 8 # 6 9 %!! !! (!! 8 " C " A , " #$ $ $ E'! . / Figure 7. Body Diode Forward Voltage Figure 8. Capacitance http://onsemi.com 322 # MGSF1N02LT1 INFORMATION FOR USING THE SOT-23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 4: 7$ 4: 7$ :7 # 4$ 7 4 8 %21! SOT-23 POWER DISSIPATION one can calculate the power dissipation of the device which in this case is 416 milliwatts. The power dissipation of the SOT-23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-23 package, PD can be calculated as follows: PD = PD = 150C - 25C 300C/W = 416 milliwatts The 300C/W for the SOT-23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 416 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 323 (! Preferred Device #$%& '( " ! N-Channel SOT-23 These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in space sensitive power management circuitry. Typical applications are dc-dc converters and power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Miniature SOT-23 Surface Mount Package Saves Board Space http://onsemi.com 750 mAMPS 30 VOLTS RDS(on) = 100 m N-Channel 4 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Symbol Value Unit VDSS 30 Vdc VGS 20 Vdc Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (tp 10 s) ID IDM 750 2000 Total Power Dissipation @ TA = 25C PD 400 mW Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C RJA 300 C/W TL 260 C Thermal Resistance - Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds mA # MARKING DIAGRAM 3 SOT-23 CASE 318 STYLE 21 1 N3 W 2 N3 W = Device Code = Work Week PIN ASSIGNMENT 3 ()% 1 2 ;(1 )'1 ORDERING INFORMATION Device Package Shipping MGSF1N03LT1 SOT-23 3000 Tape & Reel MGSF1N03LT3 SOT-23 10,000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 5 324 Publication Order Number: MGSF1N03LT1/D MGSF1N03LT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 30 - - Vdc - - - - 1.0 10 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 10 Adc) Adc Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS - - 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) 1.0 1.7 2.4 Vdc Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 1.2 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) rDS(on) - - 0.08 0.125 0.10 0.145 ON CHARACTERISTICS (Note 1.) Ohms DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 5.0 Vdc) Ciss - 140 - Output Capacitance (VDS = 5.0 Vdc) Coss - 100 - Transfer Capacitance (VDG = 5.0 Vdc) Crss - 40 - td(on) - 2.5 - pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time ns tr - 1.0 - td(off) - 16 - tf - 8.0 - QT - 6000 - pC IS - - 0.6 A Pulsed Current ISM - - 0.75 Forward Voltage (Note 2.) VSD - 0.8 - (VDD = 15 Vdc, ID = 1.0 Adc, RL = 50 ) Turn-Off Delay Time Fall Time Gate Charge (See Figure 6) SOURCE-DRAIN DIODE CHARACTERISTICS Continuous Current V 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. TYPICAL ELECTRICAL CHARACTERISTICS #$ " #$ # $ $$ , " $ $ " 4:$ 4$ # $ 4#$ 4 $ #:$ #$ $ # #$ 4 #$ 4$ # 6 9 8 Figure 1. Transfer Characteristics Figure 2. On-Region Characteristics http://onsemi.com 325 MGSF1N03LT1 #6 $ 7 " 6$ #$ 6 $$ 7 6 4 # 6 $ : 9 8 7 TYPICAL ELECTRICAL CHARACTERISTICS 9 $ 6 " # #$ 8 $$ 9 6 # 6 < " " # # " 6$ " 8 9 6 # ?$$ ?#$ #$ $ :$ #$ # 6 8 # 9 6 $ " # # 4 # 6 $ 9 @ * Figure 6. Gate Charge Figure 5. On-Resistance Variation with Temperature 4$ " C " A , " #$ 4 #$ $$ *. , " $ #$ # $ %!! !! $ 8 9 " #6 , " #$ , , 8 6 8 Figure 4. On-Resistance versus Drain Current Figure 3. On-Resistance versus Drain Current 9 9 # 4 6 $ 9 : 8 7 (!! 6 8 # 9 E'! . / Figure 7. Body Diode Forward Voltage Figure 8. Capacitance http://onsemi.com 326 # MGSF1N03LT1 INFORMATION FOR USING THE SOT-23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 4: 7$ 4: 7$ :7 # 4$ 7 4 8 %21! SOT-23 POWER DISSIPATION one can calculate the power dissipation of the device which in this case is 416 milliwatts. The power dissipation of the SOT-23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-23 package, PD can be calculated as follows: PD = PD = 150C - 25C 300C/W = 416 milliwatts The 300C/W for the SOT-23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 416 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 327 (# Preferred Device #$%& '( " P-Channel SOT-23 These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in space sensitive power management circuitry. Typical applications are dc-dc converters and power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Miniature SOT-23 Surface Mount Package Saves Board Space http://onsemi.com 750 mAMPS 20 VOLTS RDS(on) = 260 m P-Channel 4 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Symbol Value Unit VDSS 20 Vdc VGS 8.0 Vdc Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (tp 10 s) ID IDM 750 2000 Total Power Dissipation @ TA = 25C PD 400 mW Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C RJA 300 C/W TL 260 C Thermal Resistance - Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds mA # MARKING DIAGRAM 3 SOT-23 CASE 318 STYLE 21 1 PE W 2 PE W = Device Code = Work Week PIN ASSIGNMENT 3 ()% 1 2 ;(1 )'1 ORDERING INFORMATION Device Package Shipping MGSF1P02ELT1 SOT-23 3000 Tape & Reel MGSF1P02ELT3 SOT-23 10,000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 328 Publication Order Number: MGSF1P02ELT1/D MGSF1P02ELT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 20 - - Vdc - - - - 1.0 10 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 10 Adc) Adc Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 8.0 Vdc, VDS = 0 Vdc) IGSS - - 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) 0.7 1.0 1.25 Vdc Static Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 0.75 Adc) (VGS = 2.5 Vdc, ID = 0.5 Adc) rDS(on) - - 0.22 0.40 0.26 0.50 ON CHARACTERISTICS (Note 1.) Ohms DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 5.0 Vdc) Ciss - 140 - Output Capacitance (VDS = 5.0 Vdc) Coss - 130 - Transfer Capacitance (VDG = 5.0 Vdc) Crss - 50 - td(on) - 9.5 - pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time (VDD = 5 Vdc, ID = 1.0 Adc, RL = 5 , RG = 6 ) Turn-Off Delay Time tr - 32 - td(off) - 200 - tf - 200 - QT - 5500 - pC IS - - 0.6 A ISM - - 0.75 VSD - - 1.0 Fall Time Total Gate Charge ns (VDS = 16 Vdc, ID = 1.5 Adc, VGS = 4.0 Vdc) SOURCE-DRAIN DIODE CHARACTERISTICS Continuous Current Pulsed Current Forward Voltage (Note 2.) (VGS = 0 Vdc, IS = 0.6 Adc) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. V TYPICAL ELECTRICAL CHARACTERISTICS $ 6 # 8 ##$ :$ 9 , " $ 6 #$ # " #$ #$ 9 # $ :$ #$ $ $$ # 6 9 8 # ## #6 #9 #$ # 4 6 $ 9 : 8 Figure 1. Transfer Characteristics Figure 2. On-Region Characteristics http://onsemi.com 329 7 MGSF1P02ELT1 9 " #$ $$ $ $ 6$ #$ 6 4$ $$ 4 #$ # $ $ # #$ 4 4$ 6 6$ $ TYPICAL ELECTRICAL CHARACTERISTICS 6 #$ < " 6$ " :$ # " #$ " $ 7 8 : 9 ?$ #$ #$ $ :$ #$ #$ # $ $$ $ 6 4 9 $ : 8 8 9 " $ 6 # $ " 9 , " #$ # , , 4 6 $ 9 : 8 7 @ Figure 6. Gate Charge Figure 5. On-Resistance Variation with Temperature 6 4$ , " $ #$ $$ *. # Figure 4. On-Resistance versus Drain Current $ 4 $ 4 Figure 3. On-Resistance versus Drain Current 6 " 6$ 4$ " C " A , " #$ !! 4 #$ # %!! $ (!! $ # 4 6 $ 9 : 8 7 # 4 6 $ 9 . / Figure 7. Body Diode Forward Voltage Figure 8. Capacitance Variation http://onsemi.com 330 : MGSF1P02ELT1 INFORMATION FOR USING THE SOT-23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 4: 7$ 4: 7$ :7 # 4$ 7 4 8 %21! SOT-23 POWER DISSIPATION one can calculate the power dissipation of the device which in this case is 416 milliwatts. The power dissipation of the SOT-23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-23 package, PD can be calculated as follows: PD = PD = 150C - 25C 300C/W = 416 milliwatts The 300C/W for the SOT-23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 416 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 331 (# Preferred Device #$%& '( " P-Channel SOT-23 These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in space sensitive power management circuitry. Typical applications are dc-dc converters and power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Miniature SOT-23 Surface Mount Package Saves Board Space http://onsemi.com 750 mAMPS 20 VOLTS RDS(on) = 350 m P-Channel 4 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Symbol Value Unit VDSS 20 Vdc VGS 20 Vdc Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (tp 10 s) ID IDM 750 2000 Total Power Dissipation @ TA = 25C PD 400 mW Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C RJA 300 C/W TL 260 C Thermal Resistance - Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds mA # MARKING DIAGRAM 3 SOT-23 CASE 318 STYLE 21 1 PC W 2 PC W = Device Code = Work Week PIN ASSIGNMENT 3 ()% 1 2 )'1 ;(1 ORDERING INFORMATION Device Package Shipping MGSF1P02LT1 SOT-23 3000 Tape & Reel MGSF1P02LT3 SOT-23 10,000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 332 Publication Order Number: MGSF1P02LT1/D MGSF1P02LT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 20 - - Vdc - - - - 1.0 10 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 10 Adc) Adc Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS - - 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) 1.0 1.7 2.4 Vdc Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 1.5 Adc) (VGS = 4.5 Vdc, ID = 0.75 Adc) rDS(on) - - 0.235 0.375 0.350 0.500 ON CHARACTERISTICS (Note 1.) Ohms DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 5.0 Vdc) Ciss - 130 - Output Capacitance (VDS = 5.0 Vdc) Coss - 120 - Transfer Capacitance (VDG = 5.0 Vdc) Crss - 60 - td(on) - 2.5 - pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time ns tr - 1.0 - td(off) - 16 - tf - 8.0 - QT - 6000 - pC IS - - 0.6 A Pulsed Current ISM - - 0.75 Forward Voltage (Note 2.) VSD - 1.5 - (VDD = 15 Vdc, ID = 1.0 Adc, RL = 50 ) Turn-Off Delay Time Fall Time Gate Charge (See Figure 6) SOURCE-DRAIN DIODE CHARACTERISTICS Continuous Current V 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. TYPICAL ELECTRICAL CHARACTERISTICS $ " #$ :$ 4#$ 4 :$ $$ $ , " $ #$ #$ " 4$ #$ $ $ # #$ 4 #:$ $ #$ #$ 4$ ##$ # 4 6 $ 9 : 8 Figure 1. Transfer Characteristics Figure 2. On-Region Characteristics http://onsemi.com 333 7 MGSF1P02LT1 $$ $ $ " 6$ 6$ #$ 6 $$ 4$ 4 # $ 6 9 : 8 TYPICAL ELECTRICAL CHARACTERISTICS 6 48 49 4 #8 #6 " 6$ " :$ $ 7$ 7 8$ 8 ?$$ $ 6$ 7$ $$ ## # 6 # 8 # 9 6 9 6 6$ " $ # 6 4 # $ 9 @ * Figure 6. Gate Charge Figure 5. On-Resistance Variation with Temperature , " $ #$ $$ *. 8 " 9 , " #$ , , 9 < " " $ #$ #9 Figure 4. On-Resistance versus Drain Current #$ $ $ 4# Figure 3. On-Resistance versus Drain Current # " 46 # 6 9 8 # 6 9 " C " A , " #$ %!! (!! 8 !! # 6 9 8 E'! . / Figure 7. Body Diode Forward Voltage Figure 8. Capacitance http://onsemi.com 334 MGSF1P02LT1 INFORMATION FOR USING THE SOT-23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 4: 7$ 4: 7$ :7 # 4$ 7 4 8 %21! SOT-23 POWER DISSIPATION one can calculate the power dissipation of the device which in this case is 416 milliwatts. The power dissipation of the SOT-23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-23 package, PD can be calculated as follows: PD = PD = 150C - 25C 300C/W = 416 milliwatts The 300C/W for the SOT-23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 416 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 335 ( # . #$%& '( P-Channel TSOP-6 This device represents a series of Power MOSFETs which are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. These devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Miniature TSOP-6 Surface Mount Package - Saves Board Space * Low Profile for Thin Applications such as PCMCIA Cards * Very Low RDS(on) Provides Higher Efficiency and Expands Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Diode is Characterized for Use in Bridge Circuits * Diode Exhibits High Speed, with Soft Recovery * IDSS Specified at Elevated Temperatures * Avalanche Energy Specified * Package Mounting Information Provided http://onsemi.com 2 AMPERES 20 VOLTS RDS(on) = 175 m P-Channel # $ 9 4 6 MARKING DIAGRAM 3 4 5 2 1 3V W TSOP-6 CASE 318G STYLE 1 6 3V W = Device Code = Work Week PIN ASSIGNMENT ()% ()% ;(1 6 5 4 1 2 3 ()% ()% )'1 ORDERING INFORMATION Device Package Shipping MGSF2P02HDT1 TSOP-6 3000 Tape & Reel MGSF2P02HDT3 TSOP-6 10,000 Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 336 Publication Order Number: MGSF2P02HD/D MGSF2P02HD MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Symbol Value Unit VDSS VDGR 20 V 20 V 9 V Drain Current - Continuous Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Total Power Dissipation @ TC = 85C Thermal Resistance - Junction to Ambient (Note 1.) VGS ID IDM PD PD RqJA 1.3 10 400 210 312 A Drain Current - Continuous Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Total Power Dissipation @ TC = 85C Thermal Resistance - Junction to Ambient (Note 2.) ID IDM PD PD RqJA 2.9 15 2.0 1.0 62.5 TJ, Tstg - 55 to 150 Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain Source Avalanche Energy VDD = 20 V, VGS = 4.5 Vpk, IL = 3.6 Apk, L = 25 mH, RG = 25 W EAS mW mW C/W A W W C/W C mJ 160 THERMAL CHARACTERISTICS Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 5 seconds TL 1. Minimum FR-4 or G-10 PCB, Operating to Steady State. 2. Mounted onto a 2 square FR-4 Board (1 sq. 2 oz. Cu 0.06 thick single sided), Operating time 5 seconds. http://onsemi.com 337 260 C MGSF2P02HD ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 20 - - - - - - 1.0 10 - - 100 0.7 - 0.95 2.2 1.4 - - - 145 220 175 280 1.3 2.0 - Ciss - 225 - Coss - 150 - Crss - 60 - td(on) - 15 - tr - 27 - td(off) - 60 - tf - 72 - td(on) - 20 - tr - 94 - td(off) - 49 - tf - 76 - QT - 5.3 7.5 Q1 - 0.7 - Q2 - 2.6 - Q3 - 1.9 - - - 0.89 0.72 1.1 - trr - 86 - ta - 27 - tb - 59 - QRR - 0.115 - Unit OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-to-Source Leakage Current (VGS = 9.0 Vdc, VDS = 0 Vdc) IGSS Vdc A nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Temperature Coefficient (Negative) VGS(th) Drain-to-Source On-Voltage (VGS = 4.5 Vdc, ID = 1.3 Adc) (VGS = 2.7 Vdc, ID = 0.8 Adc) RDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 0.6 Adc) gFS Vdc mV/C mW mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 15 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS = 10 Vdc, ID = 1.2 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 0.6 Adc, VGS = 2 2.7 7 Vdc Vdc, RG = 6.0 ) Fall Time Gate Charge (VDS = 16 Vdc, ID = 1.2 Adc, VGS = 4.5 Vdc) nsec nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage VSD (IS = 1.2 Adc, VGS = 0 Vdc) Reverse Recovery Time (IS = 1.2 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) NOTE: Pulse Test: Pulse Width 300 s, Duty Cycle 2%. http://onsemi.com 338 Vdc nsec C MGSF2P02HD TYPICAL ELECTRICAL CHARACTERISTICS " 8 4 6$ 4 6 #: 4: #$ 44 # #4 # , " #$ #7 6 4 # 6 8 # 9 # , " $$ # 6 9 8 # 9 , " #$ $ 6 " #: 4 # 6$ 4 6 Figure 3. On-Resistance versus Drain Current Figure 4. On-Resistance versus Drain Current and Gate Voltage # " 6$ " 8 , " #$ $ $ # < " 4 , " #$ 6 4 Figure 2. Transfer Characteristics 6 # Figure 1. On-Region Characteristics 4 #$ 7 : #$ ?$ F#$ #$ $ :$ #$ $ " 6 8 # 9 , , Figure 5. On-Resistance versus Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 339 # MGSF2P02HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 8 *. %!! 9 " " , " #$ (!! 6 %!! !! # (!! Figure 7. Capacitance Variation http://onsemi.com 340 # # @ 6 9 4 # @ @# # 8 " # , " #$ # 4 6 $ " " # " 6$ , " #$ 'C 'CC '( 6 @4 ' ! GG $ GG MGSF2P02HD 9 ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # " , " #$ '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') 9 %&' " 4 &! # 8 6 6 $ 9 : 8 7 ' Figure 11. Reverse Recovery Time (trr) Figure 10. Diode Forward Voltage versus Current http://onsemi.com 341 MGSF2P02HD TYPICAL ELECTRICAL CHARACTERISTICS < $ # *0 $ ' '# # - - " '&'# ' ! Figure 12. Thermal Response %&' '(( ') '+ #$ '* Figure 13. Diode Reverse Recovery Waveform http://onsemi.com 342 - . / / ' ,' " (' , ,*0 " *0 ,' MGSF2P02HD INFORMATION FOR USING THE TSOP-6 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 76 #6 4: 7$ :6 7 4: 7$ #8 : 47 %21! TSOP-6 POWER DISSIPATION one can calculate the power dissipation of the device which in this case is 400 milliwatts. The power dissipation of the TSOP-6 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the TSOP-6 package, PD can be calculated as follows: PD = PD = 150C - 25C 312C/W = 400 milliwatts The 312C/W for the TSOP-6 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 400 milliwatts. There are other alternatives to achieving higher power dissipation from the TSOP-6 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 343 (! Preferred Device #$%& '( N-Channel TSOP-6 These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in small power management circuitry. Typical applications are dc-dc converters, power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Miniature TSOP-6 Surface Mount Package Saves Board Space http://onsemi.com 4 AMPERES 20 VOLTS RDS(on) = 70 m N-Channel MAXIMUM RATINGS (TJ = 25C unless otherwise noted) # $ 9 Symbol Value Unit VDSS 20 Vdc Gate-to-Source Voltage - Continuous VGS 8.0 Vdc Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (tp 10 s) ID IDM 4.0 20 Total Power Dissipation @ TA = 25C Mounted on FR4 t 5 sec PD 2.0 W Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C RJA 62.5 C/W TL 260 C Rating Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, for 10 seconds 4 A 6 MARKING DIAGRAM 3 4 5 2 1 442 W TSOP-6 CASE 318G STYLE 1 6 442 W = Device Code = Work Week PIN ASSIGNMENT ()% ()% ;(1 6 5 4 1 2 3 ()% ()% )'1 ORDERING INFORMATION Device Package MGSF3442VT1 TSOP-6 Shipping 3000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 344 Publication Order Number: MGSF3442VT1/D MGSF3442VT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 20 - - - - - - 1.0 5.0 - - 100 0.6 - - - - 0.058 0.072 0.070 0.095 Unit OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 70C) IDSS Gate-Body Leakage Current (VGS = 8.0 Vdc, VDS = 0) IGSS Vdc Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) Static Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 4.0 A) (VGS = 2.5 Vdc, ID = 3.4 A) rDS(on) Vdc Ohms DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 5.0 V) Ciss - 90 - Output Capacitance (VDS = 5.0 V) Coss - 50 - Transfer Capacitance (VDG = 5.0 V) Crss - 10 - td(on) - 8.0 20 pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time ns tr - 24 40 td(off) - 36 60 tf - 10 20 QT - - - nC IS - - 1.0 A Pulsed Current ISM - - 5.0 A Forward Voltage (Note 2.) VSD - - 1.2 V Turn-Off Delay Time (VDD = 10 Vdc, ID = 1.0 A, VGEN = 10 V, RL = 10 ) Fall Time Gate Charge SOURCE-DRAIN DIODE CHARACTERISTICS Continuous Current 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 345 MGSF3442VT1 TYPICAL ELECTRICAL CHARACTERISTICS 9 # 4 " 6$ 6 4$ " $$ #$ # # # 8 6 9 #$ # #$ 8 6 $ 4 # 6 $ #$ Figure 2. Transfer Characteristics 4 # " #$ 8 *. W # Figure 1. Output Characteristics " 6$ 9 6 8 9 %!! 6 !! # # 6 8 # 9 6 # 8 9 Figure 3. On-Resistance versus Drain Current Figure 4. Capacitance < W 4 # (!! " " 6 6 # $ $ # $ 6 # 6 9 8 # 8 9 " 6$ " 6 6 # 8 9 $ #$ #$ $ :$ #$ @D , , Figure 5. Gate Charge Figure 6. On-Resistance versus Junction Temperature http://onsemi.com 346 $ MGSF3442VT1 TYPICAL ELECTRICAL CHARACTERISTICS # # #$ :$ $ " 6 , " #$ #$ W , " $ # 8 6 $ # 6 9 8 Figure 7. Source-Drain Diode Forward Voltage Figure 8. On-Resistance versus Gate-to-Source Voltage # # 9 " #$ m / / '2 9 # # 8 6 4 6 $ #$ #$ $ :$ #$ $ , !1 Figure 9. Threshold Voltage Figure 10. Single Pulse Power <.. # - - " $ # I - - " '&'# # = " # '2, " 9#$&/ 4 , " <'2,' 6 . $ # ' '# @ / !1 Figure 11. Normalized Thermal Transient Impedance, Junction-to-Ambient http://onsemi.com 347 4 MGSF3442VT1 INFORMATION FOR USING THE TSOP-6 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 76 #6 4: 7$ :6 7 4: 7$ #8 : 47 %21! TSOP-6 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 watts. The power dissipation of the TSOP-6 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the TSOP-6 package, PD can be calculated as follows: PD = PD = 150C - 25C 62.5C/W = 2.0 watts The 62.5C/W for the TSOP-6 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 watts. There are other alternatives to achieving higher power dissipation from the TSOP-6 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 348 (! Preferred Device #$%& '( ! N-Channel TSOP-6 These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in small power management circuitry. Typical applications are dc-dc converters, power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Miniature TSOP-6 Surface Mount Package Saves Board Space http://onsemi.com 4 AMPERES 30 VOLTS RDS(on) = 65 m N-Channel MAXIMUM RATINGS (TJ = 25C unless otherwise noted) # $ 9 Symbol Value Unit VDSS 30 Vdc Gate-to-Source Voltage - Continuous VGS 20 Vdc Drain Current - Continuous @ TA = 25C - Pulsed Drain Current (tp 10 s) ID IDM 4.2 20 Total Power Dissipation @ TA = 25C Mounted on FR4 t 5 sec PD 2.0 W Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C RJA 62.5 C/W TL 260 C Rating Drain-to-Source Voltage Thermal Resistance - Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, for 10 seconds 4 A 6 MARKING DIAGRAM 3 4 5 2 1 3P W TSOP-6 CASE 318G STYLE 1 6 3P W = Device Code = Work Week PIN ASSIGNMENT ()% ()% ;(1 6 5 4 1 2 3 ()% ()% )'1 ORDERING INFORMATION Device Package MGSF3454VT1 TSOP-6 Shipping 3000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 349 Publication Order Number: MGSF3454VT1/D MGSF3454VT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 30 - - - - - - 1.0 25 - - 100 1.0 - - - - 0.05 0.07 0.065 0.095 Unit OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 70C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 4.2 A) (VGS = 4.5 Vdc, ID = 3.4 A) rDS(on) Vdc Ohms DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 5.0 V) Ciss - 90 - Output Capacitance (VDS = 5.0 V) Coss - 50 - Transfer Capacitance (VDG = 5.0 V) Crss - 10 - td(on) - 10 20 pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time ns tr - 15 30 td(off) - 20 35 tf - 10 20 QT - - 15 nC IS - - 1.0 A Pulsed Current ISM - - 5.0 A Forward Voltage (Note 2.) VSD - - 1.2 V Turn-Off Delay Time (VDD = 10 Vdc, ID = 1.0 A, VGEN = 10 V, RL = 10 ) Fall Time Gate Charge SOURCE-DRAIN DIODE CHARACTERISTICS Continuous Current 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 350 MGSF3454VT1 TYPICAL ELECTRICAL CHARACTERISTICS # " 7 8 : 9 9 # $ # 6 8 , " $$C #$C 9 #$C # 8 6 6 4 # 4 6 # 9 $9 68 # " 6$ 8 " 6 %!! 6 4# !! #6 9 (!! 8 6 8 # 9 # 9 # 8 #6 4 Figure 3. On-Resistance vs. Drain Current Figure 4. Capacitance :$ " $ " 6# 8 < $ 6 Figure 2. Transfer Characteristics 9 9 6 # 4 Figure 1. Output Characteristics *. # $ 4 6$ 9 :$ " " 6# $ #$ :$ $ 7 @D #$ #$ $ :$ , , #$ $ Figure 6. On-Resistance vs. Junction Temperature Figure 5. Gate Charge http://onsemi.com 351 MGSF3454VT1 TYPICAL ELECTRICAL CHARACTERISTICS # 6 , " $ , " #$ #$ $ :$ #$ $ 9 # 8 " 6# 6 :$ # 6 9 8 Figure 7. Source-Drain Diode Forward Voltage Figure 8. On-Resistance vs. Gate-to-Source Voltage 6 4 # #6 " #$ / / '2 8 # # 6 9 9 8 $ #$ #$ $ :$ #$ $ , Figure 9. Threshold Voltage !1 Figure 10. Single Pulse Power <.. # ;'H HE1 " $ # *0 $ ' # 6 '# - - " '&'# 4 # ,' " (' , - . / / ' ,*0 " *0 ,' 5 J;)(1 /)K1 ;E!1 ;()'% !1 Figure 11. Normalized Thermal Transient Impedance, Junction-to-Ambient http://onsemi.com 352 5 MGSF3454VT1 INFORMATION FOR USING THE TSOP-6 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 76 #6 4: 7$ :6 7 4: 7$ #8 : 47 %21! TSOP-6 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 watts. The power dissipation of the TSOP-6 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the TSOP-6 package, PD can be calculated as follows: PD = PD = 150C - 25C 62.5C/W = 2.0 watts The 62.5C/W for the TSOP-6 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 watts. There are other alternatives to achieving higher power dissipation from the TSOP-6 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 353 Preferred Device t '( * %+% N-Channel DPAK The MLD1N06CL is designed for applications that require a rugged power switching device with short circuit protection that can be directly interfaced to a microcontrol unit (MCU). Ideal applications include automotive fuel injector driver, incandescent lamp driver or other applications where a high in-rush current or a shorted load condition could occur. This Logic Level Power MOSFET features current limiting for short circuit protection, integrated Gate-Source clamping for ESD protection and integral Gate-Drain clamping for over-voltage protection and Sensefet technology for low on-resistance. No additional gate series resistance is required when interfacing to the output of a MCU, but a 40 k gate pulldown resistor is recommended to avoid a floating gate condition. The internal Gate-Source and Gate-Drain clamps allow the device to be applied without use of external transient suppression components. The Gate-Source clamp protects the MOSFET input from electrostatic voltage stress up to 2.0 kV. The Gate-Drain clamp protects the MOSFET drain from the avalanche stress that occurs with inductive loads. Their unique design provides voltage clamping that is essentially independent of operating temperature. http://onsemi.com 1 AMPERE 62 VOLTS (Clamped) RDS(on) = 750 m N-Channel # MARKING DIAGRAM MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS Clamped Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR Clamped Vdc Rating VGS 10 Vdc Drain Current - Continuous - Single Pulse ID IDM Self-limited 1.8 Adc Apk Operating and Storage Temperature Range Electrostatic Discharge Voltage (Human Model) PD 40 Watts TJ, Tstg -50 to 150 C ESD 2.0 kV RJC RJA RJA 3.12 100 71.4 TL 260 YWW L1N 06C CASE 369A DPAK STYLE 2 1 2 3 Gate-to-Source Voltage - Continuous Total Power Dissipation 4 L1N06C Y WW T = Device Code = Year = Work Week = MOSFET PIN ASSIGNMENT 4 Drain THERMAL CHARACTERISTICS Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 sec. C/W 1 Gate C 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2 Drain 3 Source ORDERING INFORMATION Device Package Shipping MLD1N06CLT4 DPAK 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 354 Publication Order Number: MLD1N06CL/D MLD1N06CL UNCLAMPED DRAIN-TO-SOURCE AVALANCHE CHARACTERISTICS Rating Single Pulse Drain-to-Source Avalanche Energy Starting TJ = 25C Symbol Value Unit EAS 80 mJ ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 59 59 62 62 65 65 - - 0.6 6.0 5.0 20 - - 0.5 1.0 5.0 20 1.0 0.6 1.5 - 2.0 1.6 - - - - 0.63 0.59 1.1 1.0 0.75 0.75 1.9 1.8 - 1.1 1.5 2.0 1.1 2.3 1.3 2.75 1.8 gFS 1.0 1.4 - mhos td(on) - 1.2 2.0 ns tr - 4.0 6.0 td(off) - 4.0 6.0 tf - 3.0 5.0 - 4.5 - - 7.5 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Internally Clamped) (ID = 20 mAdc, VGS = 0 Vdc) (ID = 20 mAdc, VGS = 0 Vdc, TJ = 150C) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 45 Vdc, VGS = 0 Vdc) (VDS = 45 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Source Leakage Current (VG = 5.0 Vdc, VDS = 0 Vdc) (VG = 5.0 Vdc, VDS = 0 Vdc, TJ = 150C) IGSS Vdc Adc Adc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (ID = 250 Adc, VDS = VGS) (ID = 250 Adc, VDS = VGS, TJ = 150C) VGS(th) Static Drain-to-Source On-Resistance (ID = 1.0 Adc, VGS = 4.0 Vdc) (ID = 1.0 Adc, VGS = 5.0 Vdc) (ID = 1.0 Adc, VGS = 4.0 Vdc, TJ = 150C) (ID = 1.0 Adc, VGS = 5.0 Vdc, TJ = 150C) RDS(on) Static Source-to-Drain Diode Voltage (IS = 1.0 Adc, VGS = 0 Vdc) Static Drain Current Limit (VGS = 5.0 Vdc, VDS = 10 Vdc) (VGS = 5.0 Vdc, VDS = 10 Vdc, TJ = 150C) VSD Vdc Ohms ID(lim) Forward Transconductance (ID = 1.0 Adc, VDS = 10 Vdc) Vdc Adc RESISTIVE SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 Vdc, ID = 1.0 Adc, VGS(on) = 5.0 Vdc, RGS = 50 Ohms) Fall Time INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 355 nH nH MLD1N06CL , " #$ 4 9 " 4 8 6 # # 6 9 :$ 6 6 4 #$ # , " $ 8 $ Figure 1. Output Characteristics # 6 9 8 Figure 2. Transfer Function THE SMARTDISCRETES CONCEPT SHORT CIRCUIT PROTECTION AND THE EFFECT OF TEMPERATURE From a standard power MOSFET process, several active and passive elements can be obtained that provide on-chip protection to the basic power device. Such elements require only a small increase in silicon area and/or the addition of one masking layer to the process. The resulting device exhibits significant improvements in ruggedness and reliability as well as system cost reduction. The SMARTDISCRETES device functions can now provide an economical alternative to smart power ICs for power applications requiring low on-resistance, high voltage and high current. These devices are designed for applications that require a rugged power switching device with short circuit protection that can be directly interfaced to a microcontroller unit (MCU). Ideal applications include automotive fuel injector driver, incandescent lamp driver or other applications where a high in-rush current or a shorted load condition could occur. The on-chip circuitry of the MLD1N06CL offers an integrated means of protecting the MOSFET component from high in-rush current or a shorted load. As shown in the schematic diagram, the current limiting feature is provided by an NPN transistor and integral resistors R1 and R2. R2 senses the current through the MOSFET and forward biases the NPN transistor's base as the current increases. As the NPN turns on, it begins to pull gate drive current through R1, dropping the gate drive voltage across it, and thus lowering the voltage across the gate-to-source of the power MOSFET and limiting the current. The current limit is temperature dependent as shown in Figure 3, and decreases from about 2.3 Amps at 25C to about 1.3 Amps at 150C. Since the MLD1N06CL continues to conduct current and dissipate power during a shorted load condition, it is important to provide sufficient heatsinking to limit the device junction temperature to a maximum of 150C. The metal current sense resistor R2 adds about 0.4 ohms to the power MOSFET's on-resistance, but the effect of temperature on the combination is less than on a standard MOSFET due to the lower temperature coefficient of R2. The on-resistance variation with temperature for gate voltages of 4 and 5 Volts is shown in Figure 5. Back-to-back polysilicon diodes between gate and source provide ESD protection to greater than 2 kV, HBM. This on-chip protection feature eliminates the need for an external Zener diode for systems with potentially heavy line transients. OPERATION IN THE CURRENT LIMIT MODE The amount of time that an unprotected device can withstand the current stress resulting from a shorted load before its maximum junction temperature is exceeded is dependent upon a number of factors that include the amount of heatsinking that is provided, the size or rating of the device, its initial junction temperature, and the supply voltage. Without some form of current limiting, a shorted load can raise a device's junction temperature beyond the maximum rated operating temperature in only a few milliseconds. Even with no heatsink, the MLD1N06CL can withstand a shorted load powered by an automotive battery (10 to 14 Volts) for almost a second if its initial operating temperature is under 100C. For longer periods of operation in the current-limited mode, device heatsinking can extend operation from several seconds to indefinitely depending on the amount of heatsinking provided. http://onsemi.com 356 MLD1N06CL 6 F"F$F F"F:$F E% 6 4 # 4 # #$ $ , , $ $ # 6 9 8 Figure 4. RDS(on) Variation With Gate-To-Source Voltage Figure 3. ID(lim) Variation With Temperature #$ ,F"F$ $ " " " 6 :$ F"F$ $ #$ $ $ , , $ = / - , Figure 5. On-Resistance Variation With Temperature 8 9 6 # #$ $ :$ #$ , , $ 96 94 9# 9 9 $ Figure 6. Single Pulse Avalanche Energy versus Junction Temperature $ , , Figure 7. Drain-Source Sustaining Voltage Variation With Temperature http://onsemi.com 357 $ MLD1N06CL FORWARD BIASED SAFE OPERATING AREA (1.8 A at 150C) and not the RDS(on). The maximum voltage can be calculated by the following equation: The FBSOA curves define the maximum drain-to-source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, "Transient Thermal Resistance - General Data and Its Use" provides detailed instructions. Vsupply = (150 - TA) ID(lim) (RJC + RCA) where the value of RCA is determined by the heatsink that is being used in the application. DUTY CYCLE OPERATION When operating in the duty cycle mode, the maximum drain voltage can be increased. The maximum operating temperature is related to the duty cycle (DC) by the following equation: TC = (VDS x ID x DC x RCA) + TA MAXIMUM DC VOLTAGE CONSIDERATIONS The maximum value of VDS applied when operating in a duty cycle mode can be approximated by: The maximum drain-to-source voltage that can be continuously applied across the MLD1N06CL when it is in current limit is a function of the power that must be dissipated. This power is determined by the maximum current limit at maximum rated operating temperature VDS = 150 - TC ID(lim) x DC x RJC " " #$ ! ! ! ! Figure 8. Maximum Rated Forward Bias Safe Operating Area (MLD1N06CL) (' <.. " $ # *0 $ # ' '# - - " '&'# ??$ ??6 ??4 ??# ?? ' ! Figure 9. Thermal Response (MLD1N06CL) http://onsemi.com 358 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MLD1N06CL D1 $ % 'CC ' ' ;' '( 7B ;' A " $ 'CC 'C 7B B 7B $ % Figure 10. Switching Test Circuit $B B $B / Figure 11. Switching Waveforms ACTIVE CLAMPING MLD1N06CL, the integrated gate-to-source voltage elements provide greater than 2.0 kV electrostatic voltage protection. The avalanche voltage of the gate-to-drain voltage clamp is set less than that of the power MOSFET device. As soon as the drain-to-source voltage exceeds this avalanche voltage, the resulting gate-to-drain Zener current builds a gate voltage across the gate-to-source impedance, turning on the power device which then conducts the current. Since virtually all of the current is carried by the power device, the gate-to-drain voltage clamp element may be small in size. This technique of establishing a temperature compensated drain-to-source sustaining voltage (Figure 7) effectively removes the possibility of drain-to-source avalanche in the power device. The gate-to-drain voltage clamp technique is particularly useful for snubbing loads where the inductive energy would otherwise avalanche the power device. An improvement in ruggedness of at least four times has been observed when inductive energy is dissipated in the gate-to-drain clamped conduction mode rather than in the more stressful gate-to-source avalanche mode. SMARTDISCRETES technology can provide on-chip realization of the popular gate-to-source and gate-to-drain Zener diode clamp elements. Until recently, such features have been implemented only with discrete components which consume board space and add system cost. The SMARTDISCRETES technology approach economically melds these features and the power chip with only a slight increase in chip area. In practice, back-to-back diode elements are formed in a polysilicon region monolithicly integrated with, but electrically isolated from, the main device structure. Each back-to-back diode element provides a temperature compensated voltage element of about 7.2 volts. As the polysilicon region is formed on top of silicon dioxide, the diode elements are free from direct interaction with the conduction regions of the power device, thus eliminating parasitic electrical effects while maintaining excellent thermal coupling. To achieve high gate-to-drain clamp voltages, several voltage elements are strung together; the MLD1N06CL uses 8 such elements. Customarily, two voltage elements are used to provide a 14.4 volt gate-to-source voltage clamp. For the TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS = The MLD1N06CL has been designed to allow direct interface to the output of a microcontrol unit to control an isolated load. No additional series gate resistance is required, but a 40 k gate pulldown resistor is recommended to avoid a floating gate condition in the event of an MCU failure. The internal clamps allow the device to be used without any external transistent suppressing components. 9 http://onsemi.com 359 # Preferred Device t '( * %+% N-Channel TO-220 These SMARTDISCRETES devices feature current limiting for short circuit protection, an integral gate-to-source clamp for ESD protection and gate-to-drain clamp for over-voltage protection. No additional gate series resistance is required when interfacing to the output of a MCU, but a 40 k gate pulldown resistor is recommended to avoid a floating gate condition. The internal gate-to-source and gate-to-drain clamps allow the devices to be applied without use of external transient suppression components. The gate-to-source clamp protects the MOSFET input from electrostatic gate voltage stresses up to 2.0 kV. The gate-to-drain clamp protects the MOSFET drain from drain avalanche stresses that occur with inductive loads. This unique design provides voltage clamping that is essentially independent of operating temperature. * Temperature Compensated Gate-to-Drain Clamp Limits Voltage Stress Applied to the Device and Protects the Load From Overvoltage * Integrated ESD Diode Protection * Controlled Switching Minimizes RFI * Low Threshold Voltage Enables Interfacing Power Loads to Microprocessors http://onsemi.com 1 AMPERE 62 VOLTS (Clamped) RDS(on) = 750 m N-Channel # MARKING DIAGRAM & PIN ASSIGNMENT MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Symbol Value Unit Drain-to-Source Voltage VDSS Clamped Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR Clamped Vdc Gate-to-Source Voltage - Continuous VGS 10 Vdc Drain Current - Continuous Drain Current - Single Pulse ID IDM Self-limited 1.8 Adc Total Power Dissipation PD 40 Watts Electrostatic Discharge Voltage (Human Body Model) ESD 2.0 kV Operating and Storage Junction Temperature Range TJ, Tstg -50 to 150 C THERMAL CHARACTERISTICS Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient , , 3.12 62.5 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from case TL 260 C 4 Drain 4 TO-220AB CASE 221A STYLE 5 1 2 L1N06CL LLYWW 1 Gate 3 3 Source 2 Drain L1N06CL LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MLP1N06CL Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 360 Publication Order Number: MLP1N06CL/D MLP1N06CL UNCLAMPED DRAIN-TO-SOURCE AVALANCHE CHARACTERISTICS Rating Single Pulse Drain-to-Source Avalanche Energy (Starting TJ = 25C, ID = 2.0 A, L = 40 mH) (Figure 6) Symbol Value Unit EAS 80 mJ ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 59 59 62 62 65 65 - - 0.6 6.0 5.0 20 - - 0.5 1.0 5.0 20 1.0 0.6 1.5 - 2.0 1.6 - - - - 0.63 0.59 1.1 1.0 0.75 0.75 1.9 1.8 Unit OFF CHARACTERISTICS Drain-to-Source Sustaining Voltage (Internally Clamped) (ID = 20 mA, VGS = 0) (ID = 20 mA, VGS = 0, TJ = 150C) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 45 V, VGS = 0) (VDS = 45 V, VGS = 0, TJ = 150C) IDSS Gate-Body Leakage Current (VG = 5.0 V, VDS = 0) (VG = 5.0 V, VDS = 0, TJ = 150C) IGSS Vdc Adc Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (ID = 250 A, VDS = VGS) (ID = 250 A, VDS = VGS, TJ = 150C) VGS(th) Static Drain-to-Source On-Resistance (ID = 1.0 A, VGS = 4.0 V) (ID = 1.0 A, VGS = 5.0 V) (ID = 1.0 A, VGS = 4.0 V, TJ = 150C) (ID = 1.0 A, VGS = 5.0 V, TJ = 150C) RDS(on) Vdc Ohms Forward Transconductance (ID = 1.0 A, VDS = 10 V) gFS 1.0 1.4 - mhos Static Source-to-Drain Diode Voltage (IS = 1.0 A, VGS = 0) VSD - 1.1 1.5 Vdc 2.0 1.1 2.3 1.3 2.75 1.8 td(on) - 1.2 2.0 tr - 4.0 6.0 td(off) - 4.0 6.0 tf - 3.0 5.0 Static Drain Current Limit (VGS = 5.0 V, VDS = 10 V) (VGS = 5.0 V, VDS = 10 V, TJ = 150C) ID(lim) A RESISTIVE SWITCHING CHARACTERISTICS (Note 1.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 V, ID = 1.0 A, VGS = 5.0 V, RG = 50 Ohms) Fall Time 1. Indicates Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. http://onsemi.com 361 s MLP1N06CL 6 4 9 8 6 # " 4 # 6 9 :$ 6 , " #$ 4 #$ # , " $ 8 $ Figure 1. Output Characteristics # 6 9 8 Figure 2. Transfer Function THE SMARTDISCRETES CONCEPT SHORT CIRCUIT PROTECTION AND THE EFFECT OF TEMPERATURE From a standard power MOSFET process, several active and passive elements can be obtained that provide on-chip protection to the basic power device. Such elements require only a small increase in silicon area and/or the addition of one masking layer to the process. The resulting device exhibits significant improvements in ruggedness and reliability as well as system cost reduction. The SMARTDISCRETES device functions can now provide an economical alternative to smart power ICs for power applications requiring low on-resistance, high voltage and high current. These devices are designed for applications that require a rugged power switching device with short circuit protection that can be directly interfaced to a microcontroller unit (MCU). Ideal applications include automotive fuel injector driver, incandescent lamp driver or other applications where a high in-rush current or a shorted load condition could occur. The on-chip circuitry of the MLP1N06CL offers an integrated means of protecting the MOSFET component from high in-rush current or a shorted load. As shown in the schematic diagram, the current limiting feature is provided by an NPN transistor and integral resistors R1 and R2. R2 senses the current through the MOSFET and forward biases the NPN transistor's base as the current increases. As the NPN turns on, it begins to pull gate drive current through R1, dropping the gate drive voltage across it, and thus lowering the voltage across the gate-to-source of the power MOSFET and limiting the current. The current limit is temperature dependent as shown in Figure 3, and decreases from about 2.3 Amps at 25C to about 1.3 Amps at 150C. Since the MLP1N06CL continues to conduct current and dissipate power during a shorted load condition, it is important to provide sufficient heatsinking to limit the device junction temperature to a maximum of 150C. The metal current sense resistor R2 adds about 0.4 ohms to the power MOSFET's on-resistance, but the effect of temperature on the combination is less than on a standard MOSFET due to the lower temperature coefficient of R2. The on-resistance variation with temperature for gate voltages of 4 and 5 Volts is shown in Figure 5. Back-to-back polysilicon diodes between gate and source provide ESD protection to greater than 2 kV, HBM. This on-chip protection feature eliminates the need for an external Zener diode for systems with potentially heavy line transients. OPERATION IN THE CURRENT LIMIT MODE The amount of time that an unprotected device can withstand the current stress resulting from a shorted load before its maximum junction temperature is exceeded is dependent upon a number of factors that include the amount of heatsinking that is provided, the size or rating of the device, its initial junction temperature, and the supply voltage. Without some form of current limiting, a shorted load can raise a device's junction temperature beyond the maximum rated operating temperature in only a few milliseconds. Even with no heatsink, the MLP1N06CL can withstand a shorted load powered by an automotive battery (10 to 14 Volts) for almost a second if its initial operating temperature is under 100C. For longer periods of operation in the current-limited mode, device heatsinking can extend operation from several seconds to indefinitely depending on the amount of heatsinking provided. http://onsemi.com 362 MLP1N06CL 6 F"F$F F"F:$F E% 6 4 # 4 # #$ $ , , $ $ # 6 9 8 Figure 4. RDS(on) Variation With Gate-To-Source Voltage Figure 3. ID(lim) Variation With Temperature #$ ,F"F$ $ " " " 6 :$ F"F$ $ #$ $ $ , , $ 8 9 6 # #$ $ :$ #$ , , $ = / - , Figure 5. On-Resistance Variation With Temperature 96 94 9# 9 9 $ Figure 6. Single Pulse Avalanche Energy versus Junction Temperature $ , , Figure 7. Drain-Source Sustaining Voltage Variation With Temperature http://onsemi.com 363 $ MLP1N06CL FORWARD BIASED SAFE OPERATING AREA (1.8 A at 150C) and not the RDS(on). The maximum voltage can be calculated by the following equation: The FBSOA curves define the maximum drain-to-source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, "Transient Thermal Resistance - General Data and Its Use" provides detailed instructions. (150 - TA) ID(lim) (RJC + RCA) Vsupply = where the value of RCA is determined by the heatsink that is being used in the application. DUTY CYCLE OPERATION When operating in the duty cycle mode, the maximum drain voltage can be increased. The maximum operating temperature is related to the duty cycle (DC) by the following equation: TC = (VDS x ID x DC x RCA) + TA MAXIMUM DC VOLTAGE CONSIDERATIONS The maximum value of VDS applied when operating in a duty cycle mode can be approximated by: The maximum drain-to-source voltage that can be continuously applied across the MLP1N06CL when it is in current limit is a function of the power that must be dissipated. This power is determined by the maximum current limit at maximum rated operating temperature VDS = 150 - TC ID(lim) x DC x RJC 9 E% FF> 4 # $ ! $F ! E% FF 9 &/ 4 # F ! F"F$F " #$ # 4 9 # 4 9 ('.. < Figure 8. Maximum Rated Forward Bias Safe Operating Area (MLP1N06CL) : $ " $ 4 # # : $ 4 # ,' " (' , ,' " 4#&/ )L ;(K1! **EH C( M1( ;E!1 ()% 2M 1) % 1 )' ' ,*0 " *0 ,' $ # *0 ' '# - - "'&'# # 4 $ # 4 $ # 4 $ # ' ! Figure 9. Thermal Response (MLP1N06CL) http://onsemi.com 364 4 $ # 4 $ MLP1N06CL D1 $ % 'CC ' ' ;' ;' A " $ 'CC '( 7B 'C 7B B 7B $ $B % Figure 10. Switching Test Circuit B $B / Figure 11. Switching Waveforms ACTIVE CLAMPING MLP1N06CL, the integrated gate-to-source voltage elements provide greater than 2.0 kV electrostatic voltage protection. The avalanche voltage of the gate-to-drain voltage clamp is set less than that of the power MOSFET device. As soon as the drain-to-source voltage exceeds this avalanche voltage, the resulting gate-to-drain Zener current builds a gate voltage across the gate-to-source impedance, turning on the power device which then conducts the current. Since virtually all of the current is carried by the power device, the gate-to-drain voltage clamp element may be small in size. This technique of establishing a temperature compensated drain-to-source sustaining voltage (Figure 7) effectively removes the possibility of drain-to-source avalanche in the power device. The gate-to-drain voltage clamp technique is particularly useful for snubbing loads where the inductive energy would otherwise avalanche the power device. An improvement in ruggedness of at least four times has been observed when inductive energy is dissipated in the gate-to-drain clamped conduction mode rather than in the more stressful gate-to-source avalanche mode. SMARTDISCRETES technology can provide on-chip realization of the popular gate-to-source and gate-to-drain Zener diode clamp elements. Until recently, such features have been implemented only with discrete components which consume board space and add system cost. The SMARTDISCRETES technology approach economically melds these features and the power chip with only a slight increase in chip area. In practice, back-to-back diode elements are formed in a polysilicon region monolithicly integrated with, but electrically isolated from, the main device structure. Each back-to-back diode element provides a temperature compensated voltage element of about 7.2 volts. As the polysilicon region is formed on top of silicon dioxide, the diode elements are free from direct interaction with the conduction regions of the power device, thus eliminating parasitic electrical effects while maintaining excellent thermal coupling. To achieve high gate-to-drain clamp voltages, several voltage elements are strung together; the MLP1N06CL uses 8 such elements. Customarily, two voltage elements are used to provide a 14.4 volt gate-to-source voltage clamp. For the TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS = The MLP1N06CL has been designed to allow direct interface to the output of a microcontrol unit to control an isolated load. No additional series gate resistance is required, but a 40 k gate pulldown resistor is recommended to avoid a floating gate condition in the event of an MCU failure. The internal clamps allow the device to be used without any external transistent suppressing components. 9 http://onsemi.com 365 # Preferred Device t '( * %+% N-Channel TO-220 This logic level power MOSFET features current limiting for short circuit protection, integrated Gate-Source clamping for ESD protection and integral Gate-Drain clamping for over-voltage protection and Sensefet technology for low on-resistance. No additional gate series resistance is required when interfacing to the output of a MCU, but a 40 k gate pulldown resistor is recommended to avoid a floating gate condition. The internal Gate-Source and Gate-Drain clamps allow the device to be applied without use of external transient suppression components. The Gate-Source clamp protects the MOSFET input from electrostatic voltage stress up to 2.0 kV. The Gate-Drain clamp protects the MOSFET drain from the avalanche stress that occurs with inductive loads. Their unique design provides voltage clamping that is essentially independent of operating temperature. http://onsemi.com 2 AMPERES 62 VOLTS (Clamped) RDS(on) = 400 m N-Channel MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Symbol Value Unit Drain-to-Source Voltage VDSS Clamped Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR Clamped Vdc VGS 10 Vdc Drain Current - Continuous @ TC = 25C ID Self-limited Adc Total Power Dissipation @ TC = 25C PD 40 Watts ESD 2.0 kV TJ, Tstg -50 to 150 C Gate-to-Source Voltage - Continuous Electrostatic Voltage Operating and Storage Temperature Range # MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 TO-220AB CASE 221A STYLE 5 THERMAL CHARACTERISTICS Maximum Junction Temperature TJ(max) 150 C Thermal Resistance - Junction to Case RJC 3.12 C/W TL 260 C Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 sec. DRAIN-TO-SOURCE AVALANCHE CHARACTERISTICS Single Pulse Drain-to-Source Avalanche Energy (Starting TJ = 25C, ID = 2.0 A, L = 40 mH) EAS 80 mJ 1 2 L2N06CL LLYWW 1 Gate 3 3 Source 2 Drain L2N06CL LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MLP2N06CL Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 366 Publication Order Number: MLP2N06CL/D MLP2N06CL ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Symbol Characteristic Min Typ Max 58 58 62 62 66 66 - - 0.6 6.0 5.0 20 - - 0.5 1.0 5.0 20 1.0 0.6 1.5 1 2.0 1.6 3.8 1.6 4.4 2.4 5.2 2.9 - - 0.3 0.53 0.4 0.7 1.0 1.4 - - 1.1 1.5 td(on) - 1.0 1.5 tr - 3.0 5.0 td(off) - 5.0 8.0 tf - 3.0 5.0 Unit OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (ID = 20 mAdc, VGS = 0 Vdc) (ID = 20 mAdc, VGS = 0 Vdc, TJ = 150C) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 40 Vdc, VGS = 0 Vdc) (VDS = 40 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Source Leakage Current (VG = 5.0 Vdc, VDS = 0 Vdc) (VG = 5.0 Vdc, VDS = 0 Vdc, TJ = 150C) IGSS Vdc Adc Adc ON CHARACTERISTICS (Note 1.) VGS(th) Gate Threshold Voltage (ID = 250 Adc, VDS = VGS) (ID = 250 Adc, VDS = VGS, TJ = 150C) Static Drain Current Limit (VGS = 5.0 Vdc, VDS = 10 Vdc) (VGS = 5.0 Vdc, VDS = 10 Vdc, TJ = 150C) Vdc ID(lim) Static Drain-to-Source On-Resistance (ID = 1.0 Adc, VGS = 5.0 Vdc) (ID = 1.0 Adc, VGS = 5.0 Vdc, TJ = 150C) Adc RDS(on) Forward Transconductance (ID = 1.0 Adc, VDS = 10 Vdc) gFS Static Source-to-Drain Diode Voltage (IS = 1.0 Adc, VGS = 0 Vdc) VSD Ohms mhos Vdc SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 30 Vdc, ID = 1.0 Adc, VGS(on) = 5.0 Vdc, RGS = 25 Ohms) Fall Time 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 367 s MLP2N06CL , " #$C 6 4 4$ 4 # 6 9 $$ $ 6$ 6 $ #$ # 6 $$C #$C , " $C 4 #$ # $ $ # :$ 4$ 9 8 # 4 6 $ 9 : 8 Figure 1. Output Characteristics Figure 2. Transfer Function THE SMARTDISCRETES CONCEPT SHORT CIRCUIT PROTECTION AND THE EFFECT OF TEMPERATURE From a standard power MOSFET process, several active and passive elements can be obtained that provide on-chip protection to the basic power device. Such elements require only a small increase in silicon area and/or the addition of one masking layer to the process. The resulting device exhibits significant improvements in ruggedness and reliability as well as system cost reduction. The SMARTDISCRETES device functions can now provide an economical alternative to smart power ICs for power applications requiring low on-resistance, high voltage and high current. These devices are designed for applications that require a rugged power switching device with short circuit protection that can be directly interfaced to a microcontroller unit (MCU). Ideal applications include automotive fuel injector driver, incandescent lamp driver or other applications where a high in-rush current or a shorted load condition could occur. The on-chip circuitry of the MLP2N06CL offers an integrated means of protecting the MOSFET component from high in-rush current or a shorted load. As shown in the schematic diagram, the current limiting feature is provided by an NPN transistor and integral resistors R1 and R2. R2 senses the current through the MOSFET and forward biases the NPN transistor's base as the current increases. As the NPN turns on, it begins to pull gate drive current through R1, dropping the gate drive voltage across it, and thus lowering the voltage across the gate-to-source of the power MOSFET and limiting the current. The current limit is temperature dependent as shown in Figure 3, and decreases from about 2.3 Amps at 25C to about 1.3 Amps at 150C. Since the MLP2N06CL continues to conduct current and dissipate power during a shorted load condition, it is important to provide sufficient heatsinking to limit the device junction temperature to a maximum of 150C. The metal current sense resistor R2 adds about 0.4 ohms to the power MOSFET's on-resistance, but the effect of temperature on the combination is less than on a standard MOSFET due to the lower temperature coefficient of R2. The on-resistance variation with temperature for gate voltages of 4 and 5 Volts is shown in Figure 5. Back-to-back polysilicon diodes between gate and source provide ESD protection to greater than 2 kV, HBM. This on-chip protection feature eliminates the need for an external Zener diode for systems with potentially heavy line transients. OPERATION IN THE CURRENT LIMIT MODE The amount of time that an unprotected device can withstand the current stress resulting from a shorted load before its maximum junction temperature is exceeded is dependent upon a number of factors that include the amount of heatsinking that is provided, the size or rating of the device, its initial junction temperature, and the supply voltage. Without some form of current limiting, a shorted load can raise a device's junction temperature beyond the maximum rated operating temperature in only a few milliseconds. Even with no heatsink, the MLP2N06CL can withstand a shorted load powered by an automotive battery (10 to 14 Volts) for almost a second if its initial operating temperature is under 100C. For longer periods of operation in the current-limited mode, device heatsinking can extend operation from several seconds to indefinitely depending on the amount of heatsinking provided. http://onsemi.com 368 MLP2N06CL 9 E% $ " $ " 6 4 # ?$ $ " 8 9 #$ # $ 6 , " ?$C : 8 # 4 6 $ 9 , , 7 Figure 4. RDS(on) Variation With Gate-To-Source Voltage Figure 3. ID(lim) Variation With Temperature 9 " $ " 6 6 " $ 4 # ?$ $ , , $ Figure 5. On-Resistance Variation With Temperature = - , " # 8 9 6 # #$ $ :$ #$ , , $ 96 94$ " # 94 9#$ 9# 9$ 9 9$ 9 ?$ Figure 6. Maximum Avalanche Energy versus Starting Junction Temperature $ , " , Figure 7. Drain-Source Sustaining Voltage Variation With Temperature http://onsemi.com 369 $ MLP2N06CL FORWARD BIASED SAFE OPERATING AREA (1.8 A at 150C) and not the RDS(on). The maximum voltage can be calculated by the following equation: The FBSOA curves define the maximum drain-to-source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, "Transient Thermal Resistance - General Data and Its Use" provides detailed instructions. Vsupply = (150 - TA) ID(lim) (RJC + RCA) where the value of RCA is determined by the heatsink that is being used in the application. DUTY CYCLE OPERATION When operating in the duty cycle mode, the maximum drain voltage can be increased. The maximum operating temperature is related to the duty cycle (DC) by the following equation: TC = (VDS x ID x DC x RCA) + TA MAXIMUM DC VOLTAGE CONSIDERATIONS The maximum value of VDS applied when operating in a duty cycle mode can be approximated by: The maximum drain-to-source voltage that can be continuously applied across the MLP2N06CL when it is in current limit is a function of the power that must be dissipated. This power is determined by the maximum current limit at maximum rated operating temperature VDS = 150 - TC ID(lim) x DC x RJC " " #$ ! ! Figure 8. Maximum Rated Forward Bias Safe Operating Area (MLP2N06CL) (' <.. " $ # $ *0 # ' '# - - " '&'# ??$ ??6 ??4 ??# ?? ' ! Figure 9. Thermal Response (MLP2N06CL) http://onsemi.com 370 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MLP2N06CL D1 $ % 'CC ' ' ;' '( 7B ;' A " $ 'CC 'C 7B B 7B $ % Figure 10. Switching Test Circuit $B B $B / Figure 11. Switching Waveforms ACTIVE CLAMPING MLP2N06CL, the integrated gate-to-source voltage elements provide greater than 2.0 kV electrostatic voltage protection. The avalanche voltage of the gate-to-drain voltage clamp is set less than that of the power MOSFET device. As soon as the drain-to-source voltage exceeds this avalanche voltage, the resulting gate-to-drain Zener current builds a gate voltage across the gate-to-source impedance, turning on the power device which then conducts the current. Since virtually all of the current is carried by the power device, the gate-to-drain voltage clamp element may be small in size. This technique of establishing a temperature compensated drain-to-source sustaining voltage (Figure 7) effectively removes the possibility of drain-to-source avalanche in the power device. The gate-to-drain voltage clamp technique is particularly useful for snubbing loads where the inductive energy would otherwise avalanche the power device. An improvement in ruggedness of at least four times has been observed when inductive energy is dissipated in the gate-to-drain clamped conduction mode rather than in the more stressful gate-to-source avalanche mode. SMARTDISCRETES technology can provide on-chip realization of the popular gate-to-source and gate-to-drain Zener diode clamp elements. Until recently, such features have been implemented only with discrete components which consume board space and add system cost. The SMARTDISCRETES technology approach economically melds these features and the power chip with only a slight increase in chip area. In practice, back-to-back diode elements are formed in a polysilicon region monolithicly integrated with, but electrically isolated from, the main device structure. Each back-to-back diode element provides a temperature compensated voltage element of about 7.2 volts. As the polysilicon region is formed on top of silicon dioxide, the diode elements are free from direct interaction with the conduction regions of the power device, thus eliminating parasitic electrical effects while maintaining excellent thermal coupling. To achieve high gate-to-drain clamp voltages, several voltage elements are strung together; the MLP2N06CL uses 8 such elements. Customarily, two voltage elements are used to provide a 14.4 volt gate-to-source voltage clamp. For the TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS = The MLP2N06CL has been designed to allow direct interface to the output of a microcontrol unit to control an isolated load. No additional series gate resistance is required, but a 40 k gate pulldown resistor is recommended to avoid a floating gate condition in the event of an MCU failure. The internal clamps allow the device to be used without any external transistent suppressing components. # 9 http://onsemi.com 371 ( Preferred Device #$%& '( ! N-Channel SOT-23 These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in small power management circuitry. Typical applications are dc-dc converters, power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Miniature SOT-23 Surface Mount Package Saves Board Space http://onsemi.com 300 mAMPS 20 VOLTS RDS(on) = 1 N-Channel 4 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C - Continuous @ TA = 70C - Pulsed Drain Current (tp 10 s) Total Power Dissipation @ TA = 25C(1) Operating and Storage Temperature Range Thermal Resistance - Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol Value Unit VDSS 20 Vdc VGS 20 Vdc mAdc ID ID IDM 300 240 750 PD 225 mW TJ, Tstg - 55 to 150 C RJA 556 C/W TL 260 C # MARKING DIAGRAM 3 SOT-23 CASE 318 STYLE 21 1 N1 W 2 N1 W = Device Code = Work Week PIN ASSIGNMENT 3 ()% 1 2 )'1 ;(1 ORDERING INFORMATION Device Package MMBF0201NLT1 SOT-23 Shipping 3000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 372 Publication Order Number: MMBF0201NLT1/D MMBF0201NLT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 20 - - Vdc - - - - 1.0 10 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Adc Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS - - 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) 1.0 1.7 2.4 Vdc Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 300 mAdc) (VGS = 4.5 Vdc, ID = 100 mAdc) rDS(on) - - 0.75 1.0 1.0 1.4 gFS - 450 - mMhos pF ON CHARACTERISTICS (Note 1.) Forward Transconductance (VDS = 10 Vdc, ID = 200 mAdc) Ohms DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 5.0 V) Ciss - 45 - Output Capacitance (VDS = 5.0 V) Coss - 25 - Transfer Capacitance (VDG = 5.0 V) Crss - 5.0 - td(on) - 2.5 - tr - 2.5 - td(off) - 15 - tf - 0.8 - QT - 1400 - pC IS - - 0.3 A Pulsed Current ISM - - 0.75 Forward Voltage (Note 2.) VSD - 0.85 - SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 300 mAdc, RL = 50 ) Fall Time Gate Charge (See Figure 5) ns SOURCE-DRAIN DIODE CHARACTERISTICS Continuous Current 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 373 V MMBF0201NLT1 TYPICAL ELECTRICAL CHARACTERISTICS 8 9 6 #$ # ?$$ #$ # 4 6 $ " 6 9 " 7 8 : 9 6 # " 4 4 # Figure 2. On-Region Characteristics " 6$ 9 " 4 # 6 9 8 # $ $ $ $ 6 $ " #$ '2 < " 9 " 4 # Figure 4. On-Resistance versus Gate-to-Source Voltage 9 # 6 #6 Figure 3. On-Resistance versus Drain Current 7 Figure 1. Transfer Characteristics 7 8 9 6 7$ 7 8$ 8 :$ : # 9 # 8 $ " $ 9 9$ 9 6$ # 9 #$ 46 #$ $ :$ #$ @D * Figure 5. Gate Charge Figure 6. Threshold Voltage Variance Over Temperature http://onsemi.com 374 $ MMBF0201NLT1 TYPICAL ELECTRICAL CHARACTERISTICS 9 " N 4 *. 8 6 # " 6$ N 9 $ 9 %!! 6 !! # 8 #$ #$ $ :$ #$ $ (!! $ $ , , Figure 7. On-Resistance versus Junction Temperature Figure 8. Capacitance < 8 #$ #$ ?$$ 4 9 7 # . / Figure 9. Source-to-Drain Forward Voltage versus Continuous Current (IS) http://onsemi.com 375 6 # MMBF0201NLT1 INFORMATION FOR USING THE SOT-23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 4: 7$ 4: 7$ :7 # 4$ 7 4 8 %21! SOT-23 POWER DISSIPATION one can calculate the power dissipation of the device which in this case is 225 milliwatts. The power dissipation of the SOT-23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-23 package, PD can be calculated as follows: PD = PD = 150C - 25C 556C/W = 225 milliwatts The 556C/W for the SOT-23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, SOLDERING PRECAUTIONS * The soldering temperature and time should not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 376 ( # Preferred Device #$%& '( ! P-Channel SOT-23 These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in small power management circuitry. Typical applications are dc-dc converters, power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Miniature SOT-23 Surface Mount Package Saves Board Space http://onsemi.com 300 mAMPS 20 VOLTS RDS(on) = 1.4 P-Channel 4 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C - Continuous @ TA = 70C - Pulsed Drain Current (tp 10 s) Symbol Value Unit VDSS 20 Vdc VGS 20 Vdc ID ID IDM 300 240 750 Total Power Dissipation @ TA = 25C (Note 1.) PD 225 Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C RJA 625 C/W TL 260 C Thermal Resistance - Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds mAdc # mW MARKING DIAGRAM 3 SOT-23 CASE 318 STYLE 21 1 P3 W 2 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. P3 W = Device Code = Work Week PIN ASSIGNMENT 3 ()% 1 2 )'1 ;(1 ORDERING INFORMATION Device Package Shipping MMBF0202PLT1 SOT-23 3000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 377 Publication Order Number: MMBF0202PLT1/D MMBF0202PLT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 20 - - Vdc - - - - 1.0 10 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Adc Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS - - 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) 1.0 1.7 2.4 Vdc Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 200 mAdc) (VGS = 4.5 Vdc, ID = 50 mAdc) rDS(on) - - 0.9 2.0 1.4 3.5 gFS - 600 - mMhos pF ON CHARACTERISTICS (Note 2.) Forward Transconductance (VDS = 10 Vdc, ID = 200 mAdc) Ohms DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 5.0 V) Ciss - 50 - Output Capacitance (VDS = 5.0 V) Coss - 45 - Transfer Capacitance (VDG = 5.0 V) Crss - 20 - td(on) - 2.5 - tr - 1.0 - td(off) - 16 - tf - 8.0 - QT - 2700 - pC IS - - 0.3 A Pulsed Current ISM - - 0.75 Forward Voltage (Note 3.) VSD - 1.5 - SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = -15 Vdc, RL = 75 , ID = 200 mAdc, mAdc 10 V, RG = 6.0 ) VGEN = -10 Fall Time Gate Charge (See Figure 5) (VDS = 16 V, VGS = 10 V, ID = 200 mA) ns SOURCE-DRAIN DIODE CHARACTERISTICS Continuous Current 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 378 V MMBF0202PLT1 TYPICAL ELECTRICAL CHARACTERISTICS $ 8 #$ #$ 9 6 # # 6 9 6 4 # " 6$ " # 4 $ 6 $ 6 # 4 # $ $ $ # Figure 4. On-Resistance versus Gate-to-Source Voltage 9 # $ " # '2 < Figure 3. On-Resistance versus Drain Current #9 8 " 9 " 9 $7 6 # 6 Figure 2. On-Region Characteristics # # 4 Figure 1. Transfer Characteristics 4 6 # 6 6 $ " 7 8 : 9 8 8 9 " ?$$ " #$ $ 7$ 7 8$ #4 97 ##: 8 $ 4$ @D * Figure 5. Gate Charge #$ #$ $ :$ #$ Figure 6. Threshold Voltage Variance Over Temperature http://onsemi.com 379 $ MMBF0202PLT1 TYPICAL ELECTRICAL CHARACTERISTICS 4 6 # # $ *. " 6$ N $ $ " N # 7$ 7 8$ 8 $ 8 9 %!! 6 !! # #$ #$ $ :$ #$ $ (!! $ $ , , Figure 7. On-Resistance versus Junction Temperature Figure 8. Capacitance < #$ , " $C ?$$C #$C 4 6 # . / Figure 9. Source-to-Drain Forward Voltage versus Continuous Current (IS) http://onsemi.com 380 6$ # MMBF0202PLT1 INFORMATION FOR USING THE SOT-23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 4: 7$ 4: 7$ :7 # 4$ 7 4 8 %21! SOT-23 POWER DISSIPATION one can calculate the power dissipation of the device which in this case is 225 milliwatts. The power dissipation of the SOT-23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-23 package, PD can be calculated as follows: PD = PD = 150C - 25C 556C/W = 225 milliwatts The 556C/W for the SOT-23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, SOLDERING PRECAUTIONS * The soldering temperature and time should not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 381 (!" Preferred Device 0 0 '( ! N-Channel SC-70/SOT-323 These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in small power management circuitry. Typical applications are dc-dc converters, power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Miniature SC-70/SOT-323 Surface Mount Package Saves Board Space http://onsemi.com 50 mAMPS 30 VOLTS RDS(on) = 50 N-Channel MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDS 20 Vdc Gate-to-Source Voltage - Pulse VGS 20 Vdc Drain Current - Continuous @ TA = 25C ID 50 mAdc Total Power Dissipation @ TA = 25C (Note 1.) Derate above 25C PD 100 mW Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C TL 260 C Rating Maximum Lead Temperature for Soldering Purposes, for 10 seconds 1. Mounted on G10/FR4 glass epoxy board using minimum recommended footprint. MARKING DIAGRAM 3 SC-70/SOT-323 CASE 419 STYLE 8 F1 W 1 2 F1 W = Device Code = Work Week PIN ASSIGNMENT 3 Drain Gate 1 2 Source Top View ORDERING INFORMATION Device MMBF1374T1 Package SC-70/ SOT-323 Shipping 3000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2001 January, 2001 - Rev. 0 382 Publication Order Number: MMBF1374T1/D MMBF1374T1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 30 - - Vdc Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) IDSS - - 1.0 Adc Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS - - 1.0 Adc Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) - 2 2.8 Vdc Static Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 10 mAdc) rDS(on) - 27 50 gFS - 450 - mMhos pF OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) ON CHARACTERISTICS (Note 2.) Forward Transconductance (VDS = 10 Vdc, ID = 50 mAdc) DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 5.0 V) Ciss - 45 - Output Capacitance (VDS = 5.0 V) Coss - 25 - Transfer Capacitance (VDG = 5.0 V) Crss - 5.0 - td(on) - 2.5 - SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 50 mAdc, RL = 50 ) Fall Time 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 383 tr - 2.5 - td(off) - 15 - tf - 0.8 - ns (" #$%& '( N-Channel SOT-23 MAXIMUM RATINGS Rating Symbol Value Unit Drain-Source Voltage VDSS 60 Vdc Drain-Gate Voltage VDGS 60 Vdc Gate-Source Voltage - Continuous - Non-repetitive (tp 50 ms) VGS VGSM 20 40 Vdc Vpk ID IDM 0.5 0.8 Adc Symbol Max Unit 225 1.8 mW mW/C RqJA 556 C/W TJ, Tstg -55 to +150 C Drain Current - Continuous - Pulsed http://onsemi.com 500 mAMPS 60 VOLTS RDS(on) = 5 N-Channel 4 THERMAL CHARACTERISTICS Characteristic Total Device Dissipation FR-5 Board (Note 1.) TA = 25C Derate above 25C Thermal Resistance, Junction to Ambient Junction and Storage Temperature PD # MARKING DIAGRAM 1. FR-5 = 1.0 0.75 0.062 in. 3 SOT-23 CASE 318 STYLE 21 1 6Z W 2 6Z W = Device Code = Work Week PIN ASSIGNMENT 3 Drain Gate 1 2 Source ORDERING INFORMATION Device Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 384 Package Shipping MMBF170LT1 SOT-23 3000 Tape & Reel MMBF170LT3 SOT-23 10,000 Tape & Reel Publication Order Number: MMBF170LT1/D MMBF170LT1 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Symbol Min Max Unit V(BR)DSS 60 - Vdc IGSS - 10 nAdc Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) VGS(th) 0.8 3.0 Vdc Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 200 mA) rDS(on) - 5.0 W ID(off) - 0.5 mA Ciss - 60 pF td(on) - 10 ns td(off) - 10 Characteristic OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 100 mA) Gate-Body Leakage Current, Forward (VGSF = 15 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) On-State Drain Current (VDS = 25 Vdc, VGS = 0) DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 10 Vdc, VGS = 0 V, f = 1.0 MHz) SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Turn-Off Delay Time (VDD = 25 Vdc, ID = 500 mA, Rgen = 50 W) Figure 1 2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%. 5#$ $ W ' ' #$ W % # = $ W 6 *. $ W $ W ;' ;' '( 7B 'CC B % W B 7B $B 7B $B / % Figure 1. Switching Test Circuit Figure 2. Switching Waveform http://onsemi.com 385 'CC 'C MMBF170LT1 TYPICAL ELECTRICAL CHARACTERISTICS # " " #$ 9 " 6 7 # 8 : 8 9 9 6 $ # 6 4 8 # 4 6 $ 9 : 8 7 8 #$ 9 6 # #6 ## 8 " " # 9 6 # 8 9 6 ?9 ?# 5?# 5?9 # 4 6 $ 9 : 8 7 Figure 4. Transfer Characteristics '2 < ( < Figure 3. Ohmic Region # #$ ?$$ 5? 5?6 # $ " " 7$ 7 8$ 8 :$ : ?9 Figure 5. Temperature versus Static Drain-Source On-Resistance ?# 5?# 5?9 5? Figure 6. Temperature versus Gate Threshold Voltage http://onsemi.com 386 5?6 MMBF170LT1 INFORMATION FOR USING THE SOT-23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 4: 7$ 4: 7$ :7 # 4$ 7 4 8 %21! SOT-23 POWER DISSIPATION one can calculate the power dissipation of the device which in this case is 225 milliwatts. The power dissipation of the SOT-23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-23 package, PD can be calculated as follows: PD = PD = 150C - 25C 556C/W = 225 milliwatts The 556C/W for the SOT-23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 387 ( Preferred Device #$%& '( ! N-Channel SC-70/SOT-323 These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in small power management circuitry. Typical applications are dc-dc converters, power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Miniature SC-70/SOT-323 Surface Mount Package Saves Board Space http://onsemi.com 300 mAMPS 20 VOLTS RDS(on) = 1 N-Channel 4 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit VDSS 20 Vdc Gate-to-Source Voltage - Continuous VGS 20 Vdc Drain Current - Continuous @ TA = 25C - Continuous @ TA = 70C - Pulsed Drain Current (tp 10 s) ID ID IDM 300 240 750 Rating Drain-to-Source Voltage mAdc Total Power Dissipation @ TA = 25C (Note 1.) Derate above 25C PD Operating and Storage Temperature Range Thermal Resistance - Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, for 10 seconds # 150 1.2 mW mW/C TJ, Tstg - 55 to 150 C RJA 833 C/W TL 260 C MARKING DIAGRAM 3 SC-70/SOT-323 CASE 419 STYLE 8 N1 W 1 2 N1 W 1. Mounted on G10/FR4 glass epoxy board using minimum recommended footprint. = Device Code = Work Week PIN ASSIGNMENT 3 Drain 2 Source Gate 1 Top View ORDERING INFORMATION Device Package MMBF2201NT1 SC-70/ SOT-323 Shipping 3000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 388 Publication Order Number: MMBF2201NT1/D MMBF2201NT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 20 - - Vdc - - - - 1.0 10 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Adc Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS - - 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) 1.0 1.7 2.4 Vdc Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 300 mAdc) (VGS = 4.5 Vdc, ID = 100 mAdc) rDS(on) - - 0.75 1.0 1.0 1.4 gFS - 450 - mMhos pF ON CHARACTERISTICS (Note 2.) Forward Transconductance (VDS = 10 Vdc, ID = 200 mAdc) Ohms DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 5.0 V) Ciss - 45 - Output Capacitance (VDS = 5.0 V) Coss - 25 - Transfer Capacitance (VDG = 5.0 V) Crss - 5.0 - td(on) - 2.5 - tr - 2.5 - td(off) - 15 - tf - 0.8 - QT - 1400 - pC IS - - 0.3 A Pulsed Current ISM - - 0.75 Forward Voltage (Note 3.) VSD - 0.85 - SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 300 mAdc, RL = 50 ) Fall Time Gate Charge (See Figure 5) ns SOURCE-DRAIN DIODE CHARACTERISTICS Continuous Current V 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. TYPICAL CHARACTERISTICS 9 6 " 6 8 7 : 9 " 4$ $ 6 " 4 4 # " #$ 6 : 8 # 4 $ 9 ?? 7 # 8 " 6$ " " " 4 9 6 # ?9 ?6 Figure 1. Typical Drain Characteristics ?# # 6 9 8 # 6 9 Figure 2. On Resistance versus Temperature http://onsemi.com 389 MMBF2201NT1 TYPICAL CHARACTERISTICS # " 4 8 9 6 # # 9 : 8 4 6 $ ?? 7 8 9 " 6 # " 6$ Figure 3. On Resistance versus Gate-Source Voltage # $ 4 6 9 6$ " . " A *. 6 8 Figure 4. On Resistance versus Drain Current 4$ 4 #$ # %!! $ !! (!! $ # 4 6 $ 9 : 8 7 ?? . / Figure 5. Source-Drain Forward Voltage # 6 8 # 9 9 6 ?? Figure 6. Capacitance Variation 7 : 8 ?$$ : #$ $ 9 $ 6 4 # $ $ # #$ 4 4$ ?? Figure 7. Transfer Characteristics http://onsemi.com 390 6 6$ 8 # MMBF2201NT1 INFORMATION FOR USING THE SC-70/SOT-323 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.025 0.025 0.65 0.65 0.075 1.9 0.035 0.9 0.028 inches 0.7 mm SC-70/SOT-323 POWER DISSIPATION one can calculate the power dissipation of the device which in this case is 150 milliwatts. The power dissipation of the SC-70/SOT-323 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SC-70 package, PD can be calculated as follows: PD = PD = 150C - 25C 833C/W = 150 milliwatts The 833C/W for the SC-70/SOT-323 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 150 milliwatts. There are other alternatives to achieving higher power dissipation from the SC-70/SOT-323 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, SOLDERING PRECAUTIONS * The soldering temperature and time should not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 391 ( # Preferred Device #$%& '( ! P-Channel SC-70/SOT-323 These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in small power management circuitry. Typical applications are dc-dc converters, power management in portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Miniature SC-70/SOT-323 Surface Mount Package Saves Board Space http://onsemi.com 300 mAMPS 20 VOLTS RDS(on) = 2.2 P-Channel 4 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit VDSS 20 Vdc Gate-to-Source Voltage - Continuous VGS 20 Vdc Drain Current - Continuous @ TA = 25C - Continuous @ TA = 70C - Pulsed Drain Current (tp 10 s) ID ID IDM 300 240 750 Rating Drain-to-Source Voltage mAdc Total Power Dissipation @ TA = 25C (Note 1.) Derate above 25C PD Operating and Storage Temperature Range Thermal Resistance - Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, for 10 seconds # 150 1.2 mW mW/C TJ, Tstg - 55 to 150 C RJA 833 C/W TL 260 C MARKING DIAGRAM 3 SC-70/SOT-323 CASE 419 STYLE 8 P3 W 1 2 P3 W 1. Mounted on G10/FR4 glass epoxy board using minimum recommended footprint. = Device Code = Work Week PIN ASSIGNMENT 3 Drain Gate 1 2 Source Top View ORDERING INFORMATION Device Package MMBF2202PT1 SC-70/ SOT-323 Shipping 3000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 392 Publication Order Number: MMBF2202PT1/D MMBF2202PT1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 20 - - Vdc - - - - 1.0 10 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Adc Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS - - 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) 1.0 1.7 2.4 Vdc Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 200 mAdc) (VGS = 4.5 Vdc, ID = 50 mAdc) rDS(on) - - 1.5 2.0 2.2 3.5 gFS - 600 - mMhos pF ON CHARACTERISTICS (Note 2.) Forward Transconductance (VDS = 10 Vdc, ID = 200 mAdc) Ohms DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 5.0 V) Ciss - 50 - Output Capacitance (VDS = 5.0 V) Coss - 45 - Transfer Capacitance (VDG = 5.0 V) Crss - 20 - td(on) - 2.5 - tr - 1.0 - td(off) - 16 - tf - 8.0 - QT - 2700 - pC IS - - 0.3 A Pulsed Current ISM - - 0.75 Forward Voltage (Note 3.) VSD - 1.5 - SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time (VDD = -15 Vdc, RL = 75 , ID = 200 mAdc, mAdc 10 V, RG = 6.0 ) VGEN = -10 Rise Time Turn-Off Delay Time Fall Time Gate Charge (See Figure 5) (VDS = 16 V, VGS = 10 V, ID = 200 mA) ns SOURCE-DRAIN DIODE CHARACTERISTICS Continuous Current V 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. TYPICAL CHARACTERISTICS 6 8 ( ( " # 9 6 # # 4 6 $ 9 : 8 7 4$ 4 #$ # " " # $ $ " 6$ " $ ?6 ?# # 6 9 8 # 6 Figure 1. On Resistance versus Gate-Source Voltage Figure 2. On Resistance versus Temperature http://onsemi.com 393 9 MMBF2202PT1 TYPICAL CHARACTERISTICS 7 $ 6 9 " 6$ 4 " # : ?$$ 9 $ $ #$ 6 4 # # 4 6 $ 9 : 8 $ $ # #$ 4 4$ 6 Figure 3. On Resistance versus Drain Current Figure 4. Transfer Characteristics 8 #$ $ $ $ # 9 4 " 4 # 4 6 $ 9 : 8 Figure 6. On Region Characteristics $ 6$ " C " A 6 4$ 4 #$ # %!! $ !! $ (!! # 6 9 8 # 6 9 Figure 7. Capacitance Variation http://onsemi.com 394 " 4$ # Figure 5. Source-Drain Forward Voltage 7 " 6 6 9 " 6$ $ #$ $$ " $ : . / *. 6$ $ 8 8 # MMBF2202PT1 INFORMATION FOR USING THE SC-70/SOT-323 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.025 0.025 0.65 0.65 0.075 1.9 0.035 0.9 0.028 inches 0.7 mm SC-70/SOT-323 POWER DISSIPATION one can calculate the power dissipation of the device which in this case is 150 milliwatts. The power dissipation of the SC-70/SOT-323 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SC-70/SOT-323 package, PD can be calculated as follows: PD = PD = 150C - 25C 833C/W = 150 milliwatts The 833C/W for the SC-70/SOT-323 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 150 milliwatts. There are other alternatives to achieving higher power dissipation from the SC-70/SOT-323 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, SOLDERING PRECAUTIONS * The soldering temperature and time should not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 395 (! #$%& '( ! Complementary SO-8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Exhibits High Speed, with Soft Recovery http://onsemi.com 3 AMPERES 25 VOLTS RDS(on) = 100 mW (N-Channel) RDS(on) = 210 mW (P-Channel) N-Channel P-Channel D D G G S S MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage Drain Current - Continuous N-Channel P-Channel Drain Current - Pulsed N-Channel P-Channel Operating and Storage Temperature Range Total Power Dissipation @ TA = 25C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 20 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 25 mH, RG = 25 W) Thermal Resistance - Junction-to-Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 sec. Symbol Value Unit VDSS VGS 25 Vdc 20 Vdc ID MARKING DIAGRAM Adc 3.0 2.0 SO-8, Dual CASE 751 STYLE 11 8 IDM Apk 9.0 6.0 TJ, Tstg -65 to +150 C PD EAS 1.8 Watts 1300 LYWW 1 1300 L Y WW = Device Code = Location Code = Year = Work Week mJ PIN ASSIGNMENT 113 RJA TL C/W 66.3 C 260 Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 4 5 Drain-2 Gate-2 Top View 1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max. ORDERING INFORMATION Semiconductor Components Industries, LLC, 2001 March, 2001 - Rev. 1 396 Device Package MMDF1300R2 SO-8 Shipping 2500 Tape & Reel Publication Order Number: MMDF1300/D MMDF1300 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Polarity Min Typ Max - 30 - - Unit OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) V(BR)DSS Vdc Zero Gate Voltage Drain Current (VDS = 25 Vdc, VGS = 0 Vdc) IDSS (N) (P) - - - - 1.0 1.0 Adc Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS - - - 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) (N) (P) 1.0 1.0 1.5 2.0 2.0 3.0 Vdc Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 2.0 Adc) RDS(on) (N) (P) - - 0.09 0.16 0.10 0.21 Ohms Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 1.0 Adc) RDS(on) (N) (P) - - 0.13 0.30 0.16 0.375 Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) gFS (N) (P) 1.0 1.0 - - - - mhos Ciss (N) (P) - - 215 200 301 300 pF Coss (N) (P) - - 111 100 158 160 Crss (N) (P) - - 30 40 60 75 td(on) (N) (P) - - 18 14 36 28 tr (N) (P) - - 98 95 196 180 td(off) (N) (P) - - 16 22 32 45 tf (N) (P) - - 30 40 60 80 QT (N) (P) - - 3.3 7.0 5.0 10 Q1 (N) (P) - - 1.2 1.2 - - Q2 (N) (P) - - 2.0 2.5 - - Q3 (N) (P) - - 1.9 3.5 - - ON CHARACTERISTICS (Notes 2. & 3.) Ohms DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vd Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) Fall Time Total Gate Charge (VDS = 16 Vdc, ID = 2 2.0 0 Adc Adc, VGS = 4.5 Vdc) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Negative signs for P-Channel device omitted for clarity. 4. Switching characteristics are independent of operating junction temperature. http://onsemi.com 397 ns nC MMDF1300 ELECTRICAL CHARACTERISTICS - continued (TA = 25C unless otherwise noted) Characteristic Symbol Polarity Min Typ Max Unit VSD (N) (P) - - 1.0 1.3 1.4 1.7 Vdc trr (N) (P) - - 23 20 - - ns ta (N) (P) - - 18 13 - - tb (N) (P) - - 5.0 7.0 - - QRR (N) (P) - - 0.02 0.02 - - SOURCE-DRAIN DIODE CHARACTERISTICS (Note 5.) Forward On-Voltage (Note 6.) (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc) Reverse Recovery Time (N) (ID = 2.0 Adc, VGS = 0 Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge 5. Negative signs for P-Channel device omitted for clarity. 6. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. http://onsemi.com 398 C ( #$%& '( N-Channel SO-8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed * Avalanche Energy Specified * Mounting Information for SO-8 Package Provided * IDSS Specified at Elevated Temperature http://onsemi.com 1 AMPERE 50 VOLTS RDS(on) = 300 m N-Channel MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 11 8 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) 1 Symbol Value Unit Drain-to-Source Voltage VDS 50 Volts Gate-to-Source Voltage - Continuous VGS 20 Volts Drain Current - Continuous Drain Current - Pulsed ID IDM 2.0 10 Amps Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 V, VGS = 10 V, IL = 2 Apk) EAS 300 mJ TJ, Tstg -55 to 150 C PD 2.0 Watts RJA 62.5 C/W TL 260 10 C Sec Rating Operating and Storage Temperature Range Total Power Dissipation @ TA = 25C Thermal Resistance - Junction to Ambient (Note 1.) Maximum Temperature for Soldering, Time in Solder Bath 1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 6 F1N05 LYWW 399 F1N05 L Y WW = Device Code = Location Code = Year = Work Week PIN ASSIGNMENT Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 Top View ORDERING INFORMATION Device Package MMDF1N05ER2 SO-8 Shipping 2500 Tape & Reel Publication Order Number: MMDF1N05E/D MMDF1N05E ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Symbol Min Typ Max Unit V(BR)DSS 50 - - Vdc Zero Gate Voltage Drain Current (VDS = 50 V, VGS = 0) IDSS - - 250 Adc Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS - - 100 nAdc VGS(th) 1.0 - 3.0 Vdc RDS(on) RDS(on) - - - - 0.30 0.50 gFS - 1.5 - mhos pF Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0, ID = 250 A) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 1.5 Adc) (VGS = 4.5 Vdc, ID = 0.6 Adc) Ohms Forward Transconductance (VDS = 15 V, ID = 1.5 A) DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 V V, VGS = 0 0, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance Ciss - 330 - Coss - 160 - Crss - 50 - td(on) - - 20 SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 V, ID = 1.5 A, RL = 10 , VG = 10 V, RG = 50 ) Fall Time Total Gate Charge Gate-Source Charge (VDS = 10 V V, ID = 1.5 15A A, VGS = 10 V) Gate-Drain Charge ns tr - - 30 td(off) - - 40 tf - - 25 Qg - 12.5 - Qgs - 1.9 - Qgd - 3.0 - VSD - - 1.6 V trr - 45 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS (TC = 25C) Forward Voltage (Note 2.) Reverse Recovery Time (IS = 1.5 A, VGS = 0 V) (dIS/dt = 100 A/s) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 400 MMDF1N05E TYPICAL ELECTRICAL CHARACTERISTICS 9 8 , " #$ $ 8 6$ 9 6 6 " 4$ # ?$$ 8 9 6 #$ # # 6 9 8 < " 4 #$ ?$$ # 6 9 8 $ " $ " 4 # # 4 6 $ 9 : 8 , , 6 $ 9 : 8 #$ $ 7 8 9 6 " " $ # 8 9 6 # ?$ ?#$ #$ :$ $ , , Figure 4. On-Resistance Variation with Temperature '2 < Figure 3. On-Resistance versus Drain Current 6 ?$$ 4 Figure 2. Transfer Characteristics $ # # Figure 1. On-Region Characteristics 6 #$ # " " 7 8 : ?$ Figure 5. On Resistance versus Gate-To-Source Voltage ?#$ #$ $ :$ , , #$ Figure 6. Gate Threshold Voltage Variation with Temperature http://onsemi.com 401 $ MMDF1N05E , " #$ (!! *. %!! 8 " 9 " %!! 6 !! # (!! # # " #$ " # 8 9 6 # # # #$ $ $ $ $ # Figure 7. Capacitance Variation 6 9 8 # @D 6 9 Figure 8. Gate Charge versus Gate-To-Source Voltage SAFE OPERATING AREA INFORMATION Forward Biased Safe Operating Area The FBSOA curves define the maximum drain-to-source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, "Transient Thermal Resistance - General Data and Its Use" provides detailed instructions. " # " #$ ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L ! ! ! Figure 9. Maximum Rated Forward Biased Safe Operating Area '23)'.. " $ # $ # 2%* $ 6 4 # :$ : #:9 $6 . 8$6 . 4:6 . ' ! 5 Figure 10. Thermal Response http://onsemi.com 402 $::9 :87 . 5 :89 :$$ . 5# +%1' 54 MMDF1N05E INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. These can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C 62.5C/W = 2.0 Watts The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 403 ( . Preferred Device #$%& '( Complementary SO-8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Mounting Information for SO-8 Package Provided http://onsemi.com 2 AMPERES 12 VOLTS RDS(on) = 45 m (N-Channel) RDS(on) = 180 m (P-Channel) N-Channel P-Channel D D G G S S MARKING DIAGRAM MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.) Rating Symbol Value Unit Drain-to-Source Voltage N-Channel P-Channel VDSS Gate-to-Source Voltage VGS 8.0 Vdc ID 5.2 3.4 48 17 A TJ and Tstg -55 to 150 C PD 2.0 Watts Drain Current - Continuous - Pulsed Vdc 20 12 N-Channel P-Channel N-Channel P-Channel Operating and Storage Temperature Range Total Power Dissipation @ TA= 25C (Note 2.) IDM Thermal Resistance - Junction to Ambient (Note 2.) RJA Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds. TL 62.5 SO-8, Dual CASE 751 STYLE 14 8 D2C01 LYWW 1 D2C01 L Y WW = Device Code = Location Code = Year = Work Week PIN ASSIGNMENT C/W C 260 N-Source 1 8 N-Drain N-Gate 2 7 N-Drain P-Source 3 6 P-Drain 4 5 P-Drain P-Gate Top View 1. Negative signs for P-Channel device omitted for clarity. 2. Mounted on 2" square FR4 board (1" sq. 2 oz. Cu 0.06" thick single sided) with one die operating, 10 sec. max. ORDERING INFORMATION Device MMDF2C01HDR2 Package SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 6 404 Publication Order Number: MMDF2C01HD/D MMDF2C01HD ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.) Characteristic Symbol Polarity Min Typ Max Unit V(BR)DSS (N) (P) 20 12 - - - - Vdc (N) (P) - - - - 1.0 1.0 - - - 100 (N) (P) 0.7 0.7 0.8 1.0 1.1 1.1 (N) (P) - - 0.035 0.16 0.045 0.18 (N) (P) - - 0.043 0.2 0.055 0.22 (N) (P) 3.0 3.0 6.0 4.75 - - Ciss (N) (P) - - 425 530 595 740 Coss (N) (P) - - 270 410 378 570 Crss (N) (P) - - 115 177 230 250 td(on) (N) (P) - - 13 21 26 45 tr (N) (P) - - 60 156 120 315 td(off) (N) (P) - - 20 38 40 75 tf (N) (P) - - 29 68 58 135 td(on) (N) (P) - - 10 16 20 35 tr (N) (P) - - 42 44 84 90 td(off) (N) (P) - - 24 68 48 135 tf (N) (P) - - 28 54 56 110 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 20 Vdc) (VGS = 0 Vdc, VDS = 12 Vdc) Adc IDSS Gate-Body Leakage Current (VGS = 8.0 Vdc, VDS = 0) IGSS nAdc ON CHARACTERISTICS (Note 4.) VGS(th) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 4.0 Adc) (VGS = 4.5 Vdc, ID = 2.0 Adc) RDS(on) Drain-to-Source On-Resistance (VGS = 2.7 Vdc, ID = 2.0 Adc) (VGS = 2.7 Vdc, ID = 1.0 Adc) RDS(on) Forward Transconductance (VDS = 2.5 Adc, ID = 2.0 Adc) (VDS = 2.5 Adc, ID = 1.0 Adc) gFS Vdc Ohm Ohm mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 10 Vdc, VGS = 0 Vdc, f = 1.0 MHz)) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 5.) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time (VDD = 6.0 Vdc, ID = 4.0 Adc, VGS = 2.7 Vdc, RG = 2.3 ) (VDD = 6.0 Vdc, ID = 2.0 Adc, VGS = 2.7 Vdc, RG = 6.0 ) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time (VDS = 6.0 Vdc, ID = 4.0 Adc, VGS = 4.5 Vdc, RG = 2.3 ) (VDS = 6.0 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) 3. Negative signs for P-Channel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. http://onsemi.com 405 ns MMDF2C01HD ELECTRICAL CHARACTERISTICS - continued (TA = 25C unless otherwise noted) (Note 6.) Characteristic Symbol Polarity Min Typ Max Unit QT (N) (P) - - 9.2 9.3 13 13 nC SWITCHING CHARACTERISTICS - continued (Note 8.) Total Gate Charge Gate-Source Charge (VDS = 10 Vdc, ID = 4.0 Adc, VGS = 4.5 Vdc) Q1 (N) (P) - - 1.3 0.8 - - Gate-Drain Charge (VDS = 6.0 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc) Q2 (N) (P) - - 3.5 4.0 - - Q3 (N) (P) - - 3.0 3.0 - - VSD (N) (P) - - 0.95 1.69 1.1 2.0 Vdc trr (N) (P) - - 38 48 - - ns ta (N) (P) - - 17 23 - - tb (N) (P) - - 22 25 - - QRR (N) (P) - - 0.028 0.05 - - SOURCE-DRAIN DIODE CHARACTERISTICS (TC = 25C) Forward Voltage (Note 7.) (IS = 4.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc) Reverse Recovery Time (IF = IS, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 6. Negative signs for P-Channel device omitted for clarity. 7. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 8. Switching characteristics are independent of operating junction temperature. http://onsemi.com 406 C MMDF2C01HD TYPICAL ELECTRICAL CHARACTERISTICS N-Channel 6 , " #$ # 6 7 : # # 6 9 8 # 6 #$ , " #$ #4 #: # # 7 $ 9 8 # # 6 9 8 # 6 9 8 # #9 #8 Figure 1. On-Region Characteristics Figure 1. On-Region Characteristics 6 6 #$ , " ?$$ # 4 9 " 8 6$ 4 : $ 4 8 #4 #$ " 8 6$ 4 9 #: 8 P-Channel # 6 9 8 # 4 # ## #$ , " ?$$ # 6 9 8 # ## #6 Figure 2. Transfer Characteristics Figure 2. Transfer Characteristics http://onsemi.com 407 MMDF2C01HD TYPICAL ELECTRICAL CHARACTERISTICS P-Channel , " #$ " # 9 $ 6 4 9 # 6 8 N-Channel : 4$ , " #$ " 4 #$ # $ 9 # 6 $ Figure 3. On-Resistance versus Gate-To-Source Voltage , " #$ " #: 6$ 6 6$ 4$ 4 # 9 6 8 Figure 3. On-Resistance versus Gate-To-Source Voltage 4 6$ $ < < " #: # 8 9 #6 6 4# Figure 4. On-Resistance versus Drain Current and Gate Voltage # " 6$ " 6 # $ $ ?$ , " #$ #$ Figure 4. On-Resistance versus Drain Current and Gate Voltage $ 8 " 6$ " # $ ?#$ #$ $ :$ #$ $ ?$ ?#$ #$ $ :$ #$ , , , , Figure 5. On-Resistance Variation with Temperature Figure 5. On-Resistance Variation with Temperature http://onsemi.com 408 $ MMDF2C01HD TYPICAL ELECTRICAL CHARACTERISTICS N-Channel P-Channel " " , " #$ # 6 9 8 , " #$ # Figure 6. Drain-To-Source Leakage Current versus Voltage 6 8 # Figure 6. Drain-To-Source Leakage Current versus Voltage POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) http://onsemi.com 409 MMDF2C01HD N-Channel # " " (!! %!! 6 6 8 # !! 8 6 6 8 (!! Figure 7. Capacitance Variation Figure 7. Capacitance Variation 4 @ 9 @# " 6 , " #$ # 6 # @4 # 6 9 8 $ @ 6 8 4 9 # @ " # , " #$ @# 6 # @4 # 6 9 8 @ @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge " 9 " # " 6$ , " #$ '( 'C 'CC ' ! " 9 " 6 " 6$ , " #$ ' 'CC 'C '( ' Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 9. Resistive Switching Time Variation versus Gate Resistance http://onsemi.com 410 8 # E'! @ %!! 6 6 (!! $ , " #$ %!! 8 (!! 8 " # !! *. # 8 " 9 %!! 6 ' ! # , " #$ *. 9 P-Channel MMDF2C01HD DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by N-Channel P-Channel 4 # " " ,," "#$ #$ 6 # 4 6 $ 9 : 8 7 " , " #$ $ $ 6 9 8 # 6 9 8 Figure 10. Diode Forward Voltage versus Current Figure 10. Diode Forward Voltage versus Current http://onsemi.com 411 MMDF2C01HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the N-Channel " # " #$ ! ! ! ! P-Channel ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L " 8 " #$ ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L ! ! Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 412 MMDF2C01HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # 2%* $ 6 4 # :$ : #:9 $6 . 8$6 . 4:6 . ' ! 5 %&' '(( '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 413 :87 . 5 Figure 13. Thermal Response ') $::9 :89 :$$ . 5# +%1' 54 MMDF2C01HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 414 MMDF2C01HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 15. Typical Solder Heating Profile http://onsemi.com 415 ( #$%& '( - Complementary SO-8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, with Soft Recovery * Avalanche Energy Specified * Mounting Information for SO-8 Package Provided http://onsemi.com 2.5 AMPERES 25 VOLTS RDS(on) = 100 m (N-Channel) RDS(on) = 250 m (P-Channel) N-Channel D D G G Drain-to-Source Voltage Gate-to-Source Voltage Drain Current - Continuous N-Channel P-Channel - Pulsed N-Channel P-Channel Operating and Storage Temperature Range Total Power Dissipation @ TA= 25C (Note 2.) Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 20 V, VGS = 10 V, Peak IL = 9.0 A, L = 6.0 mH, RG = 25 ) N-Channel (VDD = 20 V, VGS = 10 V, Peak IL = 7.0 A, L = 10 mH, RG = 25 ) P-Channel Thermal Resistance - Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering, 0.0625 from case. Time in Solder Bath is 10 seconds. Symbol Value Unit VDSS VGS 25 Vdc 20 Vdc 3.6 2.5 18 13 Adc - 55 to 150 C 2.0 Watts ID IDM TJ and Tstg PD EAS mJ S S MARKING DIAGRAM MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.) Rating P-Channel SO-8, Dual CASE 751 STYLE 14 8 F2C02 LYWW 1 F2C02 L Y WW = Device Code = Location Code = Year = Work Week PIN ASSIGNMENT N-Source 1 8 N-Drain N-Gate 2 7 N-Drain 245 P-Source 3 6 P-Drain 245 P-Gate 4 5 P-Drain RJA 62.5 C/W Top View TL 260 C ORDERING INFORMATION Device 1. Negative signs for P-Channel device omitted for clarity. 2. Mounted on 2" square FR4 board (1" sq. 2 oz. Cu 0.06" thick single sided) with one die operating, 10 sec. max. MMDF2C02ER2 Package SO-8 Shipping 2500 Tape & Reel This document contains information on a new product. Specifications and information herein are subject to change without notice. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 6 416 Publication Order Number: MMDF2C02E/D MMDF2C02E ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.) Characteristic Symbol Polarity Min Typ Max - 25 - - Unit OFF CHARACTERISTICS V(BR)DSS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Vdc Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) IDSS (N) (P) - - - - 1.0 1.0 Adc Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS - - - 100 nAdc - 1.0 2.0 3.0 (N) (P) - - - - 0.100 0.250 (N) (P) - - - - 0.200 0.400 (N) (P) 2.0 2.0 - - - - (N) (P) 1.0 1.0 2.6 2.8 - - Ciss (N) (P) - - 380 340 532 475 Coss (N) (P) - - 235 220 329 300 Crss (N) (P) - - 55 75 110 150 td(on) (N) (P) - - 10 20 30 40 tr (N) (P) - - 35 40 70 80 td(off) (N) (P) - - 19 53 38 106 tf (N) (P) - - 25 41 50 82 td(on) (N) (P) - - 7.0 13 21 26 tr (N) (P) - - 17 29 30 58 td(off) (N) (P) - - 27 30 48 60 tf (N) (P) - - 18 28 30 56 ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 2.2 Adc) (VGS = 10 Vdc, ID = 2.0 Adc) RDS(on) Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 1.0 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) On-State Drain Current (VDS = 5.0 Vdc, VGS = 4.5 Vdc) RDS(on) ID(on) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) (VDS = 3.0 Vdc, ID = 1.0 Adc) Vdc Ohm Ohm gFS Adc mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 5.) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc, RG = 9.1 ) (VDD = 10 Vdc, ID = 1.0 Adc, VGS = 5.0 Vdc, RG = 25 ) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 6.0 ) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 6.0 ) 3. Negative signs for P-Channel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. http://onsemi.com 417 ns MMDF2C02E ELECTRICAL CHARACTERISTICS - continued (TA = 25C unless otherwise noted) (Note 6.) Characteristic Symbol Polarity Min Typ Max Unit QT (N) (P) - - 10.6 10 30 15 nC Q1 (N) (P) - - 1.3 1.0 - - Q2 (N) (P) - - 2.9 3.5 - - Q3 (N) (P) - - 2.7 3.0 - - VSD (N) (P) - - 1.0 1.5 1.4 2.0 Vdc trr (N) (P) - - 34 32 66 64 ns ta (N) (P) - - 17 19 - - tb (N) (P) - - 17 12 - - QRR (N) (P) - - 0.025 0.035 - - SWITCHING CHARACTERISTICS - continued (Note 8.) Total Gate Charge Gate-Source Charge Gate-Drain Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) SOURCE-DRAIN DIODE CHARACTERISTICS (TC = 25C) Forward Voltage (Note 7.) (IS = 2.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc) Reverse Recovery Time see Figure 7 (IF = IS, dIS/dt = 100 A/s) 6. Negative signs for P-Channel device omitted for clarity. 7. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 8. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. http://onsemi.com 418 C MMDF2C02E TYPICAL ELECTRICAL CHARACTERISTICS N-Channel " 6$ 64 6 9 $ 6 4: 4$ 47 : P-Channel 44 6 4 4 #7 # #: #$ , " #$ $ #$ :$ #$ $ :$ , " #$ 64 # 6 47 4: 4$ 44 6 8 # 9 Figure 1. On-Region Characteristics Figure 1. On-Region Characteristics 6 , " #$ 6$ $ 6 4 #$ # $ 6: : 9 $ : 4 # " # 4 # #$ , " $$ , " $$ # #$ 4 4$ #$ 6 4 4$ 6 Figure 2. Transfer Characteristics Figure 2. Transfer Characteristics http://onsemi.com 419 6$ MMDF2C02E TYPICAL ELECTRICAL CHARACTERISTICS P-Channel 9 N-Channel " 4$ , " #$ $ 6 4 # # 4 6 $ 9 : 8 7 9 " , " #$ $ 6 4 # 4 6 , " #$ " 6$ $ # 4 $ 6 9 : 9 $ $ #$ $ :$ #$ $ , , < < " " 4$ ?#$ $ 6 " 6$ 4 # $ $ # Figure 4. On-Resistance versus Drain Current and Gate Voltage ?$ 7 , " #$ # 8 Figure 3. On-Resistance versus Gate-to-Source Voltage $ : 9 Figure 3. On-Resistance versus Gate-to-Source Voltage $ Figure 4. On-Resistance versus Drain Current and Gate Voltage # " " # $ $ ?$ ?#$ #$ $ :$ #$ , , Figure 5. On-Resistance Variation with Temperature Figure 5. On-Resistance Variation with Temperature http://onsemi.com 420 $ MMDF2C02E TYPICAL ELECTRICAL CHARACTERISTICS N-Channel " #$ " , " #$ P-Channel $ $ , " #$ #$ # 6 8 # 9 Figure 6. Drain-to-Source Leakage Current versus Voltage Figure 6. Drain-to-Source Leakage Current versus Voltage POWER MOSFET SWITCHING During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. http://onsemi.com 421 MMDF2C02E DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 7. Reverse Recovery Time (trr) http://onsemi.com 422 MMDF2C02E SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 9). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For N-Channel " # " #$ P-Channel ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L ! ! ! " # " #$ ! Figure 8. Maximum Rated Forward Biased Safe Operating Area #8 #8 *0 " 7 #6 GG - , GG - , ! Figure 8. Maximum Rated Forward Biased Safe Operating Area # 9 # 8 6 ! ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L #$ $ :$ $ #$ *0 " : #6 # 9 # 8 6 #$ $ :$ #$ , , , , Figure 9. Maximum Avalanche Energy versus Starting Junction Temperature Figure 9. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 423 $ MMDF2C02E '23)'.. " $ # $ # 2%* $ 6 4 # :$ : #:9 $6 . 8$6 . 4:6 . ' ! 5 %&' '(( '+ #$ '* Figure 11. Diode Reverse Recovery Waveform http://onsemi.com 424 :87 . 5 Figure 10. Thermal Response ') $::9 :89 :$$ . 5# +%1' 54 MMDF2C02E INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 425 MMDF2C02E TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 12. Typical Solder Heating Profile http://onsemi.com 426 ( . Preferred Device #$%& '( Complementary SO-8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * Avalanche Energy Specified * Mounting Information for SO-8 Package Provided http://onsemi.com 2 AMPERES 20 VOLTS RDS(on) = 90 m (N-Channel) RDS(on) = 160 m (P-Channel) N-Channel D D G G Drain-to-Source Voltage Gate-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 m) Drain Current - Continuous - Pulsed N-Channel P-Channel N-Channel P-Channel Operating and Storage Temperature Range Total Power Dissipation @ TA= 25C (Note 2.) Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 20 V, VGS = 5.0 V, Peak IL = 9.0 A, L = 10 mH, RG = 25 ) N-Channel (VDD = 20 V, VGS = 5.0 V, Peak IL = 6.0 A, L = 18 mH, RG = 25 ) P-Channel Symbol Value Unit VDSS VGS 20 Vdc 20 Vdc VDGR ID 20 Vdc 3.8 3.3 19 20 A TJ, Tstg - 55 to 150 C PD EAS 2.0 Watts IDM mJ MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 14 1 D2C02 L Y WW = Device Code = Location Code = Year = Work Week PIN ASSIGNMENT N-Source 1 8 N-Drain N-Gate 2 7 N-Drain P-Source 3 6 P-Drain 4 5 P-Drain 324 RJA 62.5 C/W Maximum Lead Temperature for Soldering, 0.0625 from case. Time in Solder Bath is 10 seconds. TL 260 C ORDERING INFORMATION Device MMDF2C02HDR2 1. Negative signs for P-Channel device omitted for clarity. 2. Mounted on 2" square FR4 board (1" sq. 2 oz. Cu 0.06" thick single sided) with one die operating, 10 sec. max. November, 2000 - Rev. 6 D2C02 LYWW Top View Thermal Resistance - Junction to Ambient (Note 2.) Semiconductor Components Industries, LLC, 2000 8 P-Gate 405 S S MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.) Rating P-Channel 427 Package SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MMDF2C02HD/D MMDF2C02HD ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.) Characteristic Symbol Polarity Min Typ Max - 20 - - Unit OFF CHARACTERISTICS V(BR)DSS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Vdc Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) IDSS (N) (P) - - - - 1.0 1.0 Adc Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS - - - 100 nAdc - 1.0 1.5 2.0 (N) (P) - - 0.074 0.152 0.100 0.180 (N) (P) - - 0.058 0.118 0.090 0.160 (N) (P) 2.0 2.0 3.88 3.0 - - Ciss (N) (P) - - 455 420 630 588 Coss (N) (P) - - 184 290 250 406 Crss (N) (P) - - 45 116 90 232 td(on) (N) (P) - - 11 19 22 38 tr (N) (P) - - 58 66 116 132 td(off) (N) (P) - - 17 25 35 50 tf (N) (P) - - 20 37 40 74 td(on) (N) (P) - - 7.0 11 21 22 tr (N) (P) - - 32 21 64 42 td(off) (N) (P) - - 27 45 54 90 tf (N) (P) - - 21 36 42 72 ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 1.5 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) RDS(on) Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 3.0 Adc) (VGS = 10 Vdc, ID = 2.0 Adc) RDS(on) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) (VDS = 3.0 Vdc, ID = 1.0 Adc) gFS Vdc Ohm Ohm mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vdc, VGS = 0 Vdc, f = 1.0 MHz)) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 5.) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time (VDD = 10 Vdc, ID = 3.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time (VDD = 10 Vdc, ID = 3.0 Adc, VGS = 10 Vdc, RG = 6.0 ) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 6.0 ) 3. Negative signs for P-Channel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. http://onsemi.com 428 ns MMDF2C02HD ELECTRICAL CHARACTERISTICS - continued (TA = 25C unless otherwise noted) (Note 6.) Characteristic Symbol Polarity Min Typ Max Unit QT (N) (P) - - 12.5 15 18 20 nC SWITCHING CHARACTERISTICS - continued (Note 8.) Total Gate Charge Gate-Source Charge (VDS = 16 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) Q1 (N) (P) - - 1.3 1.2 - - Gate-Drain Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) Q2 (N) (P) - - 2.8 5.0 - - Q3 (N) (P) - - 2.4 4.0 - - VSD (N) (P) - - 0.79 1.5 1.3 2.1 Vdc trr (N) (P) - - 23 38 - - ns (IS = 3.0 Adc, VAS = 0 Vdc, dIS/dt = 100 A/s) ta (N) (P) - - 18 17 - - (IS = 2.0 Adc, VAS = 0 Vdc, dIS/dt = 100 A/s) tb (N) (P) - - 5.0 21 - - QRR (N) (P) - - 0.025 0.034 - - SOURCE-DRAIN DIODE CHARACTERISTICS (TC = 25C) Forward Voltage (Note 7.) (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc) Reverse Recovery Time Reverse Recovery Stored Charge 6. Negative signs for P-Channel device omitted for clarity. 7. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 8. Switching characteristics are independent of operating junction temperature. http://onsemi.com 429 C MMDF2C02HD TYPICAL ELECTRICAL CHARACTERISTICS N-Channel " 6$ $ 47 6 , " #$ 4$ 44 4: 6 9 P-Channel 4 4 #7 # #: 4: # 6 9 8 6 # 44 # 4 #7 #: #$ 9 8 # # 6 9 8 # 6 9 Figure 1. On-Region Characteristics Figure 1. On-Region Characteristics 6 6 , " #$ # $$ , " #$ 4$ 4 47 #$ 9 " 6$ 6 8 ## #9 4 4 # #$ , " $$ $ # #$ 4 Figure 2. Transfer Characteristics Figure 2. Transfer Characteristics http://onsemi.com 430 # 46 8 4$ MMDF2C02HD TYPICAL ELECTRICAL CHARACTERISTICS 9 P-Channel N-Channel " $ , " #$ 6 # # 4 6 $ 9 : 8 7 9 " , " #$ 6 # # " 6$ : 9 $ $ # 4 6 9 # " 6$ 9 # 8 6 < < # 8 #$ $ :$ $ # #$ 4 4$ 6 Figure 4. On-Resistance versus Drain Current and Gate Voltage " " $ ?#$ $ 9 9 ?$ , " #$ Figure 4. On-Resistance versus Drain Current and Gate Voltage 6 8 Figure 3. On-Resistance versus Gate-To-Source Voltage , " #$ 9 Figure 3. On-Resistance versus Gate-To-Source Voltage 8 6 #$ $ 9 6 " " # # 8 9 ?$ , , F#$ #$ $ :$ #$ , , Figure 5. On-Resistance Variation with Temperature Figure 5. On-Resistance Variation with Temperature http://onsemi.com 431 $ MMDF2C02HD TYPICAL ELECTRICAL CHARACTERISTICS N-Channel " , " #$ P-Channel #$ 6 8 # 9 # " , " #$ $ $ # Figure 6. Drain-To-Source Leakage Current versus Voltage Figure 6. Drain-To-Source Leakage Current versus Voltage POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) http://onsemi.com 432 MMDF2C02HD N-Channel " # " # , " #$ *. *. 8 (!! %!! 6 !! # $ $ 8 9 (!! %!! 6 !! # (!! $ (!! # $ # @ # @# 8 6 # @4 # 6 9 8 # 6 8 @ $ 8 # 9 7 6 @ @# 9 " # , " #$ # @4 8 6 # 4 9 @ @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge " " 4 " '( , " #$ ' CC ' ! ' ! 9 " 4 , " #$ GG # K #6 9 # $ Figure 7. Capacitance Variation @ 8 E'! Figure 7. Capacitance Variation # $ E'! 6 , " #$ %!! %!! 9 " " 'C ' " " # " , " #$ 'CC 'C '( ' Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 9. Resistive Switching Time Variation versus Gate Resistance http://onsemi.com 433 GG 6 P-Channel MMDF2C02HD DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by N-Channel P-Channel # 4 " , " #$ 9 #$ " , " #$ # # $ 8 6 $ $ $$ 9 9$ : :$ $ 8 : 7 4 $ Figure 10. Diode Forward Voltage versus Current Figure 10. Diode Forward Voltage versus Current %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) http://onsemi.com 434 MMDF2C02HD SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For N-Channel " # " #$ P-Channel ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L ! ! ! " # " #$ - , - , 4$ " 7 4$ 4 #$ # $ $ #$ $ :$ #$ Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Rated Forward Biased Safe Operating Area 6 6$ ! ! ! ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L $ " 9 4 #$ # $ $ #$ $ :$ #$ $ , , , , Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 435 MMDF2C02HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # 2%* $ 6 4 # :$ : #:9 $6 . 8$6 . 4:6 . ' ! 5 %&' '(( '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 436 :87 . 5 Figure 14. Thermal Response ') $::9 :89 :$$ . 5# +%1' 54 MMDF2C02HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 437 MMDF2C02HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 438 ( !. Preferred Device #$%& '( ! Complementary SO-8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Mounting Information for SO-8 Package Provided http://onsemi.com 2 AMPERES 30 VOLTS RDS(on) = 70 m (N-Channel) RDS(on) = 200 m (P-Channel) Rating Drain-to-Source Voltage Gate-to-Source Voltage Drain Current - Continuous Drain Current - Pulsed N-Channel P-Channel N-Channel P-Channel Operating and Storage Temperature Range Total Power Dissipation @ TA= 25C (Note 2.) Thermal Resistance - Junction to Ambient (Note 2.) Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 30 V, VGS = 5.0 V, Peak IL = 9.0 Apk, L = 8.0 mH, RG = 25 ) N-Channel (VDD = 30 V, VGS = 5.0 V, Peak IL = 6.0 Apk, L = 18 mH, RG = 25 ) P-Channel Maximum Lead Temperature for Soldering, 0.0625 from case. Time in Solder Bath is 10 seconds. Symbol Value Unit VDSS VGS 30 Vdc 20 Vdc 4.1 3.0 21 15 A TJ, Tstg - 55 to 150 C PD RJA 2.0 Watts 62.5 C/W ID IDM EAS mJ MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 14 November, 2000 - Rev. 6 D2C03 LYWW 1 D2C03 L Y WW = Device Code = Location Code = Year = Work Week PIN ASSIGNMENT N-Source 1 8 N-Drain N-Gate 2 7 N-Drain P-Source 3 6 P-Drain P-Gate 4 5 P-Drain Top View 324 ORDERING INFORMATION 324 TL C 260 Device MMDF2C03HDR2 1. Negative signs for P-Channel device omitted for clarity. 2. Mounted on 2" square FR4 board (1" sq. 2 oz. Cu 0.06" thick single sided) with one die operating, 10 sec. max. Semiconductor Components Industries, LLC, 2000 8 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.) P-Channel N-Channel 439 Package SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MMDF2C03HD/D MMDF2C03HD ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.) Characteristic Symbol Polarity Min Typ Max - 30 - - Unit OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) V(BR)DSS Vdc Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) IDSS (N) (P) - - - - 1.0 1.0 Adc Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS - - - 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) (N) (P) 1.0 1.0 1.7 1.5 3.0 2.0 Vdc Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 3.0 Adc) (VGS = 10 Vdc, ID = 2.0 Adc) RDS(on) (N) (P) - - 0.06 0.17 0.070 0.200 Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 1.5 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) RDS(on) (N) (P) - - 0.065 0.225 0.075 0.300 Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) (VDS = 3.0 Vdc, ID = 1.0 Adc) gFS (N) (P) 2.0 2.0 3.6 3.4 - - Ciss (N) (P) - - 450 397 630 550 Coss (N) (P) - - 160 189 225 250 Crss (N) (P) - - 35 64 70 126 td(on) (N) (P) - - 12 16 24 32 tr (N) (P) - - 65 18 130 36 td(off) (N) (P) - - 16 63 32 126 tf (N) (P) - - 19 194 38 390 td(on) (N) (P) - - 8.0 9.0 16 18 tr (N) (P) - - 15 10 30 20 td(off) (N) (P) - - 30 81 60 162 tf (N) (P) - - 23 192 46 384 ON CHARACTERISTICS (Note 4.) Ohm Ohm mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 24 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 5.) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time (VDD = 15 Vdc, ID = 3.0 Adc, VGS = 4.5 Vdc, RG = 9.1 ) (VDD = 15 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time (VDD = 15 Vdc, ID = 3.0 Adc, VGS = 10 Vdc, RG = 9.1 ) (VDD = 15 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 6.0 ) 3. Negative signs for P-Channel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. http://onsemi.com 440 ns MMDF2C03HD ELECTRICAL CHARACTERISTICS - continued (TA = 25C unless otherwise noted) (Note 6.) Characteristic Symbol Polarity Min Typ Max Unit QT (N) (P) - - 11.5 14.2 16 19 nC SWITCHING CHARACTERISTICS - continued (Note 8.) Total Gate Charge Gate-Source Charge (VDS = 10 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) Q1 (N) (P) - - 1.5 1.1 - - Gate-Drain Charge (VDS = 24 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) Q2 (N) (P) - - 3.5 4.5 - - Q3 (N) (P) - - 2.8 3.5 - - VSD (N) (P) - - 0.82 1.82 1.2 2.0 Vdc trr (N) (P) - - 24 42 - - ns ta (N) (P) - - 17 16 - - tb (N) (P) - - 7.0 26 - - QRR (N) (P) - - 0.025 0.043 - - SOURCE-DRAIN DIODE CHARACTERISTICS (TC = 25C) Forward Voltage (Note 7.) (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc) Reverse Recovery Time (IF = IS, dIS/dt = 100 A/s) Reverse Recovery Storage Charge 6. Negative signs for P-Channel device omitted for clarity. 7. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 8. Switching characteristics are independent of operating junction temperature. http://onsemi.com 441 C MMDF2C03HD TYPICAL ELECTRICAL CHARACTERISTICS N-Channel " 6$ $ 64 6 6 47 6 4$ 4: 44 4 4 # #7 #: #$ # 9 6 8 # " 6$ , " #$ 9 P-Channel 44 # 4 #7 #: #$ 6 9 8 # # Figure 1. On-Region Characteristics $ 6 , " #$ $$ # #$ 4 9 8 # 6 9 8 # Figure 1. On-Region Characteristics 6 6 9 # , " #$ 47 4 4 4: 4$ 4 # , " #$C $$ 4$ $ 6 : 7 # #4 #$ #: #7 4 44 Figure 2. Transfer Characteristics Figure 2. Transfer Characteristics http://onsemi.com 442 4$ 4: MMDF2C03HD N-Channel TYPICAL ELECTRICAL CHARACTERISTICS 9 " $ , " #$ $ 6 4 # # 4 6 $ 9 : 8 7 P-Channel 9 " , " #$ $ 6 4 # $ 9 : 8 # 4 6 8 , " #$ : " 6$ 9 4 4$ 6 , " #$ #$ " 6$ # $ #$ 4 $ # Figure 4. On-Resistance versus Drain Current and Gate Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage $ # $ #$ # 4 < < Figure 3. On-Resistance versus Gate-To-Source Voltage Figure 3. On-Resistance versus Gate-To-Source Voltage $ 7 " " $ $ $ ?$ ?#$ #$ $ :$ #$ $ 9 6 $ " " # # 8 9 ?$ , , F#$ #$ $ :$ #$ , , Figure 5. On-Resistance Variation with Temperature Figure 5. On-Resistance Variation with Temperature http://onsemi.com 443 $ MMDF2C03HD TYPICAL ELECTRICAL CHARACTERISTICS N-Channel " , " #$ P-Channel $ $ # #$ , " #$ 4 " $ $ # #$ Figure 6. Drain-To-Source Leakage Current versus Voltage Figure 6. Drain-To-Source Leakage Current versus Voltage 4 POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) http://onsemi.com 444 MMDF2C03HD N-Channel # " " %!! , " #$C 8 9 (!! %!! 6 $ $ # $ $ # #$ 4 Figure 7. Capacitance Variation #6 8 # @# 9 @4 " 4 , " #$ # 6 9 8 # Figure 7. Capacitance Variation @ $ 4 (!! 4 #$ # #6 @ # 8 9 9 @ # " # , " #$ @# 8 6 6 # @4 # 6 9 8 # 6 9 @D @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge 'CC '( 'C ' " $ " 4 " , " #$ ' ! # @ ' ! $ !! 7 %!! 6 # 9 9 (!! (!! , " #$ 8 !! # " " %!! *. *. P-Channel # " $ " # " , " #$ 'C 'CC '( ' Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 9. Resistive Switching Time Variation versus Gate Resistance http://onsemi.com 445 MMDF2C03HD DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by N-Channel P-Channel # 4 , " #$ " 9 #$ , " #$ " # # $ 8 6 $ $ $$ 9 9$ : :$ 8 $ 8$ : 7 4 $ : 7 Figure 10. Diode Forward Voltage versus Current Figure 10. Diode Forward Voltage versus Current http://onsemi.com 446 MMDF2C03HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For N-Channel P-Channel " # " #$ ! ! ! ! ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L " # " #$ ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L ! ! ! Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Rated Forward Biased Safe Operating Area N-Channel P-Channel http://onsemi.com 447 MMDF2C03HD 4$ " 7 4 - , GG - , 4$ #$ # $ $ #$ $ :$ $ #$ " 9 4 #$ # $ $ #$ $ :$ #$ $ , , , , Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # 2%* $ 6 4 # :$ : #:9 $6 . 8$6 . 4:6 . ' ! 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 448 $::9 :87 . 5 :89 :$$ . 5# +%1' 54 MMDF2C03HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 449 MMDF2C03HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 450 ( #$%& '( N-Channel SO-8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * IDSS Specified at Elevated Temperatures * Avalanche Energy Specified * Mounting Information for SO-8 Package Provided MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Symbol Value Unit VDSS VGS 25 Vdc 20 Vdc ID ID IDM PD 3.6 2.5 18 Adc 2.0 W TJ, Tstg -55 to 150 C EAS Thermal Resistance, Junction to Ambient (Note 1.) RJA 62.5 TL 260 November, 2000 - Rev. 6 N-Channel MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 11 mJ 245 C/W F2N02 LYWW 1 F2N02 L Y WW Apk = Device Code = Location Code = Year = Work Week PIN ASSIGNMENT Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 Top View C ORDERING INFORMATION 1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max. Semiconductor Components Industries, LLC, 2000 2 AMPERES 25 VOLTS RDS(on) = 100 m 8 Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 20 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 6.0 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 0.0625 from case for 10 seconds http://onsemi.com 451 Device Package MMDF2N02ER2 SO-8 Shipping 2500 Tape & Reel Publication Order Number: MMDFN02E/D MMDF2N02E ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 25 - - - - - - 1.0 10 - - 100 1.0 2.0 3.0 - - 0.083 0.110 0.100 0.200 gFS 1.0 2.6 - Mhos Ciss - 380 532 pF Coss - 235 329 Crss - 55 110 td(on) - 7.0 21 tr - 17 30 td(off) - 27 48 tf - 18 30 td(on) - 10 30 OFF CHARACTERISTICS V(BR)DSS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 2.2 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) RDS(on) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) Vdc Ohm DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) ns tr - 35 70 td(off) - 19 38 tf - 25 50 QT - 10.6 30 Q1 - 1.3 - Q2 - 2.9 - Q3 - 2.7 - VSD - 1.0 1.4 Vdc trr - 34 66 ns ta - 17 - tb - 17 - QRR - 0.03 - nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) (IS = 2.0 Adc, VGS = 0 Vdc) Reverse Recovery Time S Fi See Figure 11 (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 452 C MMDF2N02E TYPICAL ELECTRICAL CHARACTERISTICS " 6$ 64 6 $ 4$ 47 44 6 4 4 #7 # #: #$ 9 : 4: #$ $ :$ #$ $ :$ 6 4 #$ # , " $$ $ # 4$ 4 # 4 6 $ 9 : 8 7 , " #$ " 6$ $ # " $ $ :$ $ 9 : , " #$ #$ 6 Figure 4. On-Resistance versus Drain Current and Gate Voltage $ 4 " " 4$ ?#$ 6 $ Figure 3. On-Resistance versus Gate-to-Source Voltage < 4 Figure 2. Transfer Characteristics 6 ?$ #$ $ # # Figure 1. On-Region Characteristics " 4$ , " #$ # $ 9 , " #$ 9 , " #$ : #$ $ #$ $ $ # , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 453 #$ MMDF2N02E POWER MOSFET SWITCHING During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. " *. " # # , " #$C %!! 8 (!! 9 %!! 6 !! # (!! $ $ $ # #$ 9 @ 7 # 9 8 @ @# 6 4 " #4 , " #$ @4 # 6 9 8 @D Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge Figure 7. Capacitance Variation http://onsemi.com 454 # td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. MMDF2N02E : " " # " , " #$ 9 'CC 'C ' ! '( ' , " #$ " $ 6 4 # $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current Figure 9. Resistive Switching Time Variation versus Gate Resistance %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 455 MMDF2N02E #8 ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L " # " #$ ! ! GG - , ! *0 " 7 #6 # 9 # 8 6 #$ $ :$ $ #$ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # 2%* $ 6 4 # :$ : #:9 $6 . 8$6 . 4:6 . ' ! 5 %&' '(( '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 456 :87 . 5 Figure 14. Thermal Response ') $::9 :89 :$$ . 5# +%1' 54 MMDF2N02E INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. These can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 457 MMDF2N02E TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 458 ( 8 Preferred Device #$%& '( N-Channel SO-8, Dual EZFETst are an advanced series of power MOSFETs which contain monolithic back-to-back zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. http://onsemi.com 2 AMPERES 50 VOLTS RDS(on) = 300 m N-Channel * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery * * * * * * Life Logic Level Gate Drive - Can Be Driven by Logic ICs Miniature SO-8 Surface Mount Package - Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SO-8 Package Provided Rating Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 70C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Thermal Resistance - Junction to Ambient Maximum Temperature for Soldering Purposes MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 11 8 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Drain-to-Source Voltage F2N05Z LYWW Symbol Value Unit VDSS VDGR 50 Vdc 50 Vdc VGS ID ID IDM PD 15 Vdc 2.0 1.7 8.0 Adc 2.0 Watts TJ, Tstg - 55 to 150 C Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 RJA 62.5 C/W Source-2 6 Drain-2 TL 260 C 3 Gate-2 4 5 Drain-2 1 F2N05Z L Y WW = Device Code = Location Code = Year = Work Week Apk PIN ASSIGNMENT Top View 1. When mounted on G10/FR-4 glass epoxy board using minimum recommended footprint. ORDERING INFORMATION Device Package MMDF2N05ZR2 SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 459 Publication Order Number: MMDF2N05ZR2/D MMDF2N05ZR2 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 50 - 56 55 - - - - - - 2.0 25 - 0.14 0.5 2.0 - 3.0 -5.0 4.0 - - - 200 350 300 500 - 2.0 - Ciss - 104 - Coss - 58 - Crss - 16 - td(on) - 24 48 tr - 46 92 td(off) - 130 260 Unit OFF CHARACTERISTICS (Cpk 2.0) (Note 4.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 15 Vdc, VGS = 0 Vdc) (VDS = 15 Vdc, VGS = 0 Vdc, TJ = 55C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0) IGSS Vdc mV/C Adc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) (Note 4.) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 1.5 Adc) (VGS = 5.0 Vdc, ID = 0.6 Adc) (Cpk 2.0) (Note 4.) Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc) VGS(th) Vdc RDS(on) mV/C m gFS mMhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 15 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 30 Vdc, ID = 0.6 Adc, VGS = 10 Vdc Vdc, RG = 25 ) Fall Time Gate Charge ( (see fifigure 8) (VDS = 25 Vdc, ID = 1.3 Adc, VGS = 10 Vdc) tf - 71 142 QT - 3.3 4.6 Q1 - 0.7 - Q2 - 1.3 - Q3 - 1.4 - - 0.82 1.4 trr - 66 - ta - 23 - tb - 43 - QRR - 0.08 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 2.0 Adc, VGS = 0 Vdc) Reverse Recovery Time (IS = 2.0 2 0 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 460 VSD Vdc ns C MMDF2N05ZR2 TYPICAL ELECTRICAL CHARACTERISTICS " 4$ , " #$ : 6 9$ 9 4 $$ # $ $ 64 $ 9 6 8 # 9 6 8 , " $$ $ 6$ $$ Figure 2. Transfer Characteristics 8 9 6 # $$ 9 9$ : :$ 8 7 8$ 7$ 6$ $ $ :$ 6 " $ #$ $ $ #$ 4$ , " #$ $ #$ # 4 Figure 4. On-Resistance versus Drain Current and Gate Voltage $ 9$ " " ?#$ 9 9$ Figure 3. On-Resistance versus Gate-to-Source Voltage < 6 Figure 1. On-Region Characteristics ?$ 4$ " $ , " #$ # 4 # $ #$ #$ # # $ 47 # $ 4 #$ #$ , " #$ 4$ 6 #$ $ " , " #$ #$ $ $ # #$ 4 4$ 6 6$ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 461 $ MMDF2N05ZR2 POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) #$ *. # " " , " #$C %!! $ %!! (!! !! $ (!! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 462 #$ 4 6 @ 7 4 9 # @ @# 4 @4 $ " 4 , " #$ #$ 4 # $ @D 4$ 6 " , " #$ 'CC ' ! # MMDF2N05ZR2 'C '( ' Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # " , " #$ :$ $ #$ :$ $ #$ $ $$ 9 9$ : :$ 8 8$ Figure 10. Diode Forward Voltage versus Current http://onsemi.com 463 MMDF2N05ZR2 %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the " # " #$ ! ! Figure 12. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 464 MMDF2N05ZR2 TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # $ ;)E 8 21( )E 1'M(0 2%* 9 64 964 #$4 . 69 . $96 . 4$: #7698 . 64# ::6 . 6 4 # ' ! 5 5 Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 465 5# +%1' 54 MMDF2N05ZR2 INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 466 MMDF2N05ZR2 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 15. Typical Solder Heating Profile http://onsemi.com 467 ( #. Preferred Device #$%& '( P-Channel SO-8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Mounting Information for SO-8 Package Provided http://onsemi.com 2 AMPERES 12 VOLTS RDS(on) = 180 m P-Channel MARKING DIAGRAM MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.) Rating Symbol Value Unit VDSS VDGR VGS 12 Vdc 12 Vdc 8.0 Vdc Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 3.4 2.1 17 Adc Total Power Dissipation @ TA = 25C (Note 2.) PD 2.0 Watts Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Operating and Storage Temperature Range RJA Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 62.5 D2P01 L Y WW C 260 = Device Code = Location Code = Year = Work Week PIN ASSIGNMENT C C/W D2P01 LYWW 1 Apk - 55 to 150 Thermal Resistance - Junction to Ambient (Note 2.) SO-8, Dual CASE 751 STYLE 11 8 Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 1. Negative sign for P-Channel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max. Top View ORDERING INFORMATION Device MMDF2P01HDR2 Package SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 6 468 Publication Order Number: MMDF2P01HD/D MMDF2P01HD ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 3.) Characteristic Symbol Min Typ Max Unit 12 - - 17 - - - - - - 1.0 10 - - 100 0.7 - 1.0 3.0 1.1 - - - 0.16 0.2 0.180 0.220 gFS 3.0 4.75 - mhos Ciss - 530 740 pF Coss - 410 570 Crss - 177 250 td(on) - 21 45 tr - 156 315 td(off) - 38 75 tf - 68 135 td(on) - 16 35 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 12 Vdc, VGS = 0 Vdc) (VDS = 12 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 8.0 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 2.0 Adc) (VGS = 2.7 Vdc, ID = 1.0 Adc) RDS(on) Forward Transconductance (VDS = 2.5 Vdc, ID = 1.0 Adc) Vdc mV/C Ohm DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 6.0 Vdc, ID = 2.0 Adc, VGS = 2 2.7 7 Vdc Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS = 6.0 Vdc, ID = 2.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) Fall Time Gate Charge (VDS = 10 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc) tr - 44 90 td(off) - 68 135 tf - 54 110 QT - 9.3 13 Q1 - 0.8 - Q2 - 4.0 - Q3 - 3.0 - - - 1.69 1.2 2.0 - trr - 48 - ta - 23 - tb - 25 - QRR - 0.05 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 4.) (IS = 2.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 3. Negative sign for P-Channel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. http://onsemi.com 469 VSD Vdc ns C MMDF2P01HD TYPICAL ELECTRICAL CHARACTERISTICS " 8 6$ 4 4 #$ 6 , " #$ 6 #4 #: # # 7 4 # #$ , " ?$$ : $ 4$ # 6 9 8 # 9 6 8 # $ 9 # 6 8 4 < # ## #6 " #: # 6$ $ 8 $ #$ $ :$ 9 #6 4# 6 " " 6$ " # #8 #$ ?#$ #9 Figure 4. On-Resistance versus Drain Current and Gate Voltage # ?$ 8 , " #$ Figure 3. On-Resistance versus Gate-To-Source Voltage 9 Figure 2. Transfer Characteristics # $ 6 Figure 1. On-Region Characteristics #$ # , " #$ " 4 #$ $ , " #$ , , 8 6 Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 470 # MMDF2P01HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) # " , " #$ %!! 9 *. " # (!! 8 %!! 6 !! 8 6 6 8 (!! # E'! Figure 7. Capacitance Variation http://onsemi.com 471 @ 6 8 9 4 # @ " # , " #$ @# 6 # @4 # 6 9 8 ' ! $ MMDF2P01HD " 9 " # " 6$ , " #$ 'CC 'C '( ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # " , " #$ $ $ 6 9 8 # 6 9 8 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 472 MMDF2P01HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the " 8 " #$ ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L ! ! Figure 12. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 473 MMDF2P01HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # 2%* $ 6 4 # :$ : #:9 $6 . 8$6 . 4:6 . ' ! 5 %&' '(( '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 474 :87 . 5 Figure 13. Thermal Response ') $::9 :89 :$$ . 5# +%1' 54 MMDF2P01HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 475 MMDF2P01HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 15. Typical Solder Heating Profile http://onsemi.com 476 ( # #$%& '( P-Channel SO-8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, with Soft Recovery * IDSS Specified at Elevated Temperatures * Avalanche Energy Specified * Mounting Information for SO-8 Package Provided MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 11 8 F2P02 LYWW Unit 25 Vdc 20 Vdc 2.5 1.7 13 Adc 2.0 W 16 mW/C -55 to 150 C Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 mJ Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 TJ, Tstg 1 L Y WW = Location Code = Year = Work Week Apk PIN ASSIGNMENT EAS 245 Top View RJA 62.5 C/W TL 260 C 1. Negative sign for P-Channel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max. November, 2000 - Rev. 6 Value Operating and Storage Temperature Range Semiconductor Components Industries, LLC, 2000 P-Channel VDSS VGS ID ID IDM PD Maximum Lead Temperature for Soldering Purposes, 0.0625 from case for 10 seconds 2 AMPERES 25 VOLTS RDS(on) = 250 m Symbol Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 2.) Derate above 25C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 20 Vdc, VGS = 10 Vdc, Peak IL = 7.0 Apk, L = 10 mH, RG = 25 ) Thermal Resistance, Junction to Ambient (Note 2.) http://onsemi.com 477 ORDERING INFORMATION Device Package MMDF2P02ER2 SO-8 Shipping 2500 Tape & Reel Publication Order Number: MMDF2P02E/D MMDF2P02E ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.) Characteristic Symbol Min Typ Max Unit 25 - - 2.2 - - - - - - 1.0 10 - - 100 1.0 - 2.0 3.8 3.0 - - - 0.19 0.3 0.25 0.4 gFS 1.0 2.8 - Mhos Ciss - 340 475 pF Coss - 220 300 Crss - 75 150 td(on) - 20 40 tr - 40 80 td(off) - 53 106 OFF CHARACTERISTICS V(BR)DSS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 2.0 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) RDS(on) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) Vdc Ohm DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) Fall Time Gate Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) ns tf - 41 82 td(on) - 13 26 tr - 29 58 td(off) - 30 60 tf - 28 56 QT - 10 15 Q1 - 1.0 - Q2 - 3.5 - Q3 - 3.0 - VSD - 1.5 2.0 Vdc trr - 32 64 ns ta - 19 - tb - 12 - QRR - 0.035 - nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 4.) (IS = 2.0 Adc, VGS = 0 Vdc) Reverse Recovery Time S Fi See Figure 11 (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Storage Charge 3. Negative sign for P-Channel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. http://onsemi.com 478 C MMDF2P02E TYPICAL ELECTRICAL CHARACTERISTICS 6 , " #$ 6$ 64 # 6 47 4: 4$ 44 6 8 # 9 #$ , " $$ 4 4$ 6 6$ Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics $ 6 4 # # # " , " #$ 4 4 9 #$ # 6 $ : 9 8 7 9 , " #$ $ 6 " 6$ 4 # $ $ # Figure 3. On-Resistance versus Gate-to-Source Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage " " # " $ 6: 4 < $ " : 6 $ ?$ ?#$ #$ $ :$ #$ $ , " #$ 6 8 # 9 , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 479 # MMDF2P02E POWER MOSFET SWITCHING During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. " , " #$C %!! 8 *. " 9 (!! 6 %!! !! # (!! # $ $ $ # #$ 4 9 @ 7 9 6 @4 8 @# @ 4 # " # , " #$ # 6 9 8 @D Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge Figure 7. Capacitance Variation http://onsemi.com 480 # td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. MMDF2P02E # " " # " , " #$ 9 , " #$ " ' ! # 'CC '( 8 'C ' 6 9 8 # 6 9 Figure 10. Diode Forward Voltage versus Current Figure 9. Resistive Switching Time Variation versus Gate Resistance %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 481 MMDF2P02E #8 ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L " # " #$ ! ! GG - , ! *0 " : #6 # 9 # 8 6 #$ $ :$ $ #$ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # 2%* $ 6 4 # :$ : #:9 $6 . 8$6 . 4:6 . ' ! 5 %&' '(( '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 482 :87 . 5 Figure 14. Thermal Response ') $::9 :89 :$$ . 5# +%1' 54 MMDF2P02E INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. These can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 483 MMDF2P02E TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 484 ( # . Preferred Device #$%& '( P-Channel SO-8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Mounting Information for SO-8 Package Provided Rating Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, IL = 6.0 Apk, L = 18 mH, RG = 25 ) Thermal Resistance - Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol Value Unit VDSS VDGR 20 Vdc 20 Vdc VGS ID ID IDM 20 Vdc 3.3 2.1 20 Adc PD 2.0 Watts TJ, Tstg - 55 to 150 C 324 mJ EAS November, 2000 - Rev. 6 P-Channel D G S MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 11 D2P02 LYWW 1 L Y WW Apk = Location Code = Year = Work Week PIN ASSIGNMENT Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 Top View RJA 62.5 C/W TL 260 C 1. Negative sign for P-Channel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max. Semiconductor Components Industries, LLC, 2000 2 AMPERES 20 VOLTS RDS(on) = 160 m 8 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.) Drain-to-Source Voltage http://onsemi.com 485 ORDERING INFORMATION Device MMDF2P02HDR2 Package SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MMDF2P02HD/D MMDF2P02HD ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.) Characteristic Symbol Min Typ Max Unit 20 - - 25 - - - - - - 1.0 10 - - 100 1.0 - 1.5 4.0 2.0 - - - 0.118 0.152 0.160 0.180 gFS 2.0 3.0 - mhos Ciss - 420 588 pF Coss - 290 406 Crss - 116 232 td(on) - 19 38 tr - 66 132 td(off) - 25 50 tf - 37 74 td(on) - 11 22 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 2.0 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) RDS(on) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) Vdc mV/C Ohm DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS = 10 Vdc, ID = 2.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) Fall Time Gate Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) tr - 21 42 td(off) - 45 90 tf - 36 72 QT - 15 20 Q1 - 1.2 - Q2 - 5.0 - Q3 - 4.0 - - - 1.5 1.24 2.1 - trr - 38 - ta - 17 - tb - 21 - QRR - 0.034 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 4.) (IS = 2.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (VDD = 15 V, IS = 2.0 A, dIS/dt = 100 A/s) 3. Negative sign for P-Channel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%.max. 5. Switching characteristics are independent of operating junction temperature. http://onsemi.com 486 VSD Vdc ns C MMDF2P02HD TYPICAL ELECTRICAL CHARACTERISTICS " 6$ 47 6 , " #$ 4: 6 4$ 4 44 # 4 #7 4 # # 6 9 8 # 6 9 8 , " $$ # $ 9 6 # 9 6 8 # # 4$ , " #$ " 6$ 9 # 8 6 $ $ # #$ 4 4$ 6 Figure 3. On-Resistance versus Gate-To-Source Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage " " # < " , " #$ 4 Figure 2. Transfer Characteristics 6 #$ # Figure 1. On-Region Characteristics 9 #$ #: #$ # " , " #$ 8 9 ?$ F#$ #$ $ :$ #$ $ $ $ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 487 # MMDF2P02HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) # *. " " , " #$ %!! 8 9 (!! %!! 6 !! # (!! $ $ $ # E'! Figure 7. Capacitance Variation http://onsemi.com 488 8 @ # 9 7 @# " # , " #$ # @4 6 8 " " # " , " #$ $ 8 6 @ 9 4 9 # ' ! # GG GG MMDF2P02HD 'CC 'C '( ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # 9 " , " #$ # 8 6 $ : 7 4 $ Figure 10. Diode Forward Voltage versus Current http://onsemi.com 489 MMDF2P02HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For " # " #$ 4$ ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L - , ! ! ! " 9 4 #$ # $ $ #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 490 MMDF2P02HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # 2%* $ 6 4 # :$ : #:9 $6 . 8$6 . 4:6 . ' ! 5 %&' '(( '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 491 :87 . 5 Figure 14. Thermal Response ') $::9 :89 :$$ . 5# +%1' 54 MMDF2P02HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 492 MMDF2P02HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 493 ( #!. Preferred Device #$%& '( ! P-Channel SO-8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Mounting Information for SO-8 Package Provided http://onsemi.com 2 AMPERES 30 VOLTS RDS(on) = 200 m P-Channel D G S MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 11 8 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 6.0 Apk, L = 18 mH, RG = 25 ) Thermal Resistance - Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol Value Unit VDSS VDGR VGS 30 Vdc 30 Vdc 20 Vdc ID ID IDM PD 3.0 1.9 15 Adc 2.0 Watts TJ, Tstg - 55 to 150 C EAS 1 L Y WW mJ = Location Code = Year = Work Week PIN ASSIGNMENT Apk 324 D2P03 LYWW Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 Top View RJA 62.5 C/W TL 260 C 1. Negative sign for P-Channel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max. ORDERING INFORMATION Device MMDF2P03HDR2 Package SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 7 494 Publication Order Number: MMDF2P03HD/D MMDF2P03HD ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 1.) Characteristic Symbol Min Typ Max Unit 30 - - 27 - - - - - - 1.0 10 - - 100 1.0 - 1.5 4.0 2.0 - - - 0.170 0.225 0.200 0.300 gFS 2.0 3.4 - mhos Ciss - 397 550 pF Coss - 189 250 Crss - 64 126 td(on) - 16.25 33 tr - 17.5 35 td(off) - 62.5 125 tf - 194 390 td(on) - 9.0 18 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 2.0 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) RDS(on) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) Vdc mV/C Ohm DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 2.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 2.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) Fall Time Gate Charge S Fi See Figure 8 (VDS = 24 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) ns tr - 10 20 td(off) - 81 162 tf - 192 384 QT - 14.2 19 Q1 - 1.1 - Q2 - 4.5 - Q3 - 3.5 - VSD - - 1.82 1.36 2.0 - Vdc trr - 42.3 - ns ta - 15.6 - tb - 26.7 - QRR - 0.044 - nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 3.) (IS = 2.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time S Fi See Figure 15 (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Negative sign for P-Channel device omitted for clarity. 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperature. http://onsemi.com 495 C MMDF2P03HD TYPICAL ELECTRICAL CHARACTERISTICS " 6$ 4: 4 6 , " #$ 4$ 6 44 47 # 4 #7 #: 4 # , " #$C $$ #$ 9 # 6 9 8 6 # 9 8 $ # # $ 9 : 8 4 6 # 7 4 #7 4 44 $ $ #$ $ :$ #$ 4 $ # 4$ 6 " , " #$ 8 4: " 6$ # " " # F#$ 4$ Figure 4. On-Resistance versus Drain Current and Gate Voltage # 9 ?$ #: #$ < 6 #$ , " #$ Figure 3. On-Resistance versus Gate-to-Source Voltage 9 #4 Figure 2. Transfer Characteristics 4 # Figure 1. On-Region Characteristics 6 7 " , " #$ $ : #$ $ , , Figure 5. On-Resistance Variation with Temperature # Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 496 4 MMDF2P03HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) # " " , " #$ *. %!! 8 9 (!! %!! 6 !! # (!! $ $ $ # #$ 4 E'! Figure 7. Capacitance Variation http://onsemi.com 497 # #6 @ " $ " # " , " #$ 8 9 9 @ # " # , " #$ @# 8 6 6 # @4 # 6 9 8 # 9 6 ' ! # MMDF2P03HD 'C 'CC '( ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # 9 , " #$ " # 8 6 $ : 7 4 $ : 7 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 498 MMDF2P03HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For " # " #$ 4$ ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L - , ! ! ! " 9 4 #$ # $ $ #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 499 MMDF2P03HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # 2%* $ 6 4 # :$ : #:9 $6 . 8$6 . 4:6 . ' ! 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 500 $::9 :87 . 5 :89 :$$ . 5# +%1' 54 MMDF2P03HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 501 MMDF2P03HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 502 (! . Preferred Device #$%& '( ! N-Channel SO-8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Mounting Information for SO-8 Package Provided http://onsemi.com 3 AMPERES 20 VOLTS RDS(on) = 90 m N-Channel MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 11 8 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Symbol Value Unit VDSS VDGR VGS 20 Vdc 20 Vdc 20 Vdc Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) ID ID IDM PD 3.8 2.6 19 Adc 2.0 Watts Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C Gate-to-Source Voltage - Continuous 1 L Y WW EAS 405 mJ Thermal Resistance - Junction to Ambient (Note 1.) RJA 62.5 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 260 C = Location Code = Year = Work Week PIN ASSIGNMENT Apk Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 10 mH, RG = 25 ) D3N02 LYWW Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 Top View ORDERING INFORMATION Device MMDF3N02HDR2 Package SO-8 Shipping 2500 Tape & Reel 1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max. Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 6 503 Publication Order Number: MMDF3N02HD/D MMDF3N02HD ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 20 - - 29 - - - - - - 1.0 10 - - 100 1.0 - 1.5 4.0 2.0 - - - 0.058 0.074 0.090 0.100 gFS 2.0 3.88 - Mhos Ciss - 455 630 pF Coss - 184 250 Crss - 45 90 td(on) - 11 22 tr - 58 116 td(off) - 17 35 tf - 20 40 td(on) - 7.0 21 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 3.0 Adc) (VGS = 4.5 Vdc, ID = 1.5 Adc) RDS(on) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) Vdc mV/C Ohms DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 3.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 3.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) Fall Time Gate Charge S Fi See Figure 8 (VDS = 16 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) ns tr - 32 64 td(off) - 27 54 tf - 21 42 QT - 12.5 18 Q1 - 1.3 - Q2 - 2.8 - Q3 - 2.4 - VSD - - 0.79 0.72 1.3 - Vdc trr - 23 - ns ta - 18 - tb - 5.0 - QRR - 0.025 - nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time S Fi See Figure 15 (IS = 3.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 504 C MMDF3N02HD TYPICAL ELECTRICAL CHARACTERISTICS 44 4: 6 4 4 #7 # #: 9 , " #$ 4$ " 6$ $ 47 9 # 6 9 8 # 6 9 8 , " #$ # $$ # ## #9 4 Figure 2. Transfer Characteristics $ 9 : 8 4 6 # 7 8 , " #$ 46 " 6$ : 9 $ Figure 3. On-Resistance versus Gate-To-Source Voltage # 4 6 $ 9 Figure 4. On-Resistance versus Drain Current and Gate Voltage 9 " " " $ < 8 Figure 1. On-Region Characteristics # 6 6 " $ , " #$ 6 6 #$ 9 # , " #$ #$ 8 9 ?$ ?#$ #$ $ :$ #$ $ , , 6 8 # 9 Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 505 # MMDF3N02HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6 *. # " " , " #$ %!! 8 9 (!! %!! 6 !! # (!! $ $ $ # E'! Figure 7. Capacitance Variation http://onsemi.com 506 # " " 4 " '( , " #$ ' CC # 9 @ 6 9 # " 4 , " #$ @# 8 # 6 @4 # 6 9 8 # ' ! 8 #6 @ K MMDF3N02HD 6 'C ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 4 #$ " , " #$ # $ $ $ $$ 9 9$ : :$ 8 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 507 MMDF3N02HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For " # " #$ 6$ ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L ! - , ! ! 6 " 7 4$ 4 #$ # $ $ #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 508 MMDF3N02HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # 2%* $ 6 4 # :$ : #:9 $6 . 8$6 . 4:6 . ' ! 5 %&' '(( '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 509 :87 . 5 Figure 14. Thermal Response ') $::9 :89 :$$ . 5# +%1' 54 MMDF3N02HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 510 MMDF3N02HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 511 (!!. Preferred Device #$%& '( ! ! N-Channel SO-8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Mounting Information for SO-8 Package Provided http://onsemi.com 3 AMPERES 30 VOLTS RDS(on) = 70 m N-Channel MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 11 8 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 8.0 mH, RG = 25 ) Thermal Resistance - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol Value Unit VDSS VDGR VGS 30 Vdc 30 Vdc 20 Vdc ID ID IDM PD 4.1 3.0 40 Adc 2.0 Watts TJ, Tstg - 55 to 150 C EAS 1 L Y WW mJ = Location Code = Year = Work Week PIN ASSIGNMENT Apk 324 D3N03 LYWW Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 Top View RJA 62.5 C/W TL 260 C ORDERING INFORMATION Device MMDF3N03HDR2 Package SO-8 Shipping 2500 Tape & Reel 1. When mounted on 2 square FR-4 board (1 square 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max. Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 7 512 Publication Order Number: MMDF3N03HD/D MMDF3N03HD ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 30 - - 34.5 - - - - - - 1.0 10 - - 100 1.0 1.7 3.0 Unit OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 3.0 Adc) (VGS = 4.5 Vdc, ID = 1.5 Adc) RDS(on) Vdc mV/C Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) Ohms - - 0.06 0.065 0.07 0.075 2.0 3.6 - Ciss - 450 630 Coss - 160 225 Crss - 35 70 td(on) - 12 24 tr - 65 130 td(off) - 16 32 gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 3.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 9.1 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 3.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (VDS = 10 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) tf - 19 38 td(on) - 8 16 tr - 15 30 td(off) - 30 60 tf - 23 46 QT - 11.5 16 Q1 - 1.5 - Q2 - 3.5 - Q3 - 2.8 - - - 0.82 0.7 1.2 - trr - 24 - ta - 17 - tb - 7 - QRR - 0.025 - ns ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) Reverse Recovery Time S Fi See Figure 12 (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 3.0 3 0 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 513 VSD Vdc ns C MMDF3N03HD TYPICAL ELECTRICAL CHARACTERISTICS " 6$ $ 64 6 6 47 , " #$ 4: 44 4 4 # #7 9 4$ # 9 6 8 # 9 6 8 100 4 #$ # , " $$ # 6 Figure 2. Transfer Characteristics 4 # 4 6 $ 9 : 8 7 8 , " #$ : " 6$ 9 $ $ $ #$ $ :$ $ # #$ 4 Figure 4. On-Resistance versus Drain Current and Gate Voltage " " $ ?#$ $ Figure 3. On-Resistance versus Gate-to-Source Voltage < 4$ Figure 1. On-Region Characteristics 6 ?$ 4 " $ , " #$ # #$ $ # 6 # 9 $ #: #$ 9 #$ $ " , " #$ $ $ # #$ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 514 4 MMDF3N03HD POWER MOSFET SWITCHING During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by http://onsemi.com 515 MMDF3N03HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 7. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 9). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. # " " %!! *. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For , " #$C 8 9 (!! %!! 6 !! # (!! $ $ $ # #$ 4 # 7 @ 4 # @# 9 @4 8 9 #6 @ " 4 , " #$ # 6 9 8 @D # Figure 9. Gate-to-Source and Drain-to-Source Voltage versus Total Charge Figure 8. Capacitance Variation http://onsemi.com 516 MMDF3N03HD , " #$ " #$ ' ! 4 " $ " 4 " , " #$ # $ 'CC '( 'C ' $ $ 9 9$ : :$ 8 $$ Figure 11. Diode Forward Voltage versus Current Figure 10. Resistive Switching Time Variation versus Gate Resistance 4$ " # " #$ ! GG - , ! ! ! 8$ ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L " 7 4 #$ # $ $ #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 517 MMDF3N03HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # 2%* $ 6 4 # :$ : #:9 $6 . 8$6 . 4:6 . ' ! 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 518 $::9 :87 . 5 :89 :$$ . 5# +%1' 54 MMDF3N03HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 519 MMDF3N03HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 520 (!. Preferred Device #$%& '( ! N-Channel SO-8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Mounting Information for SO-8 Package Provided * Avalanche Energy Specified http://onsemi.com 3 AMPERES 40 VOLTS RDS(on) = 80 m N-Channel MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 14 8 D3N04H LYWW 1 L Y WW = Location Code = Year = Work Week PIN ASSIGNMENT N-Source 1 8 N-Drain N-Gate 2 7 N-Drain P-Source 3 6 P-Drain P-Gate 4 5 P-Drain Top View ORDERING INFORMATION Device MMDF3N04HDR2 Package SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 521 Publication Order Number: MMDF3N04HD/D MMDF3N04HD MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Symbol Value Unit VDSS VDGR 40 Vdc 40 Vdc VGS ID ID IDM PD 20 Vdc 3.4 3.0 40 Adc 2.0 16 Watts mW/C PD 1.39 11.11 Watts mW/C TJ, Tstg EAS - 55 to 150 Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C (Note 1.) Drain Current- Continuous @ TA = 70C (Note 1.) Drain Current- Pulsed Drain Current (Note 3.) Total Power Dissipation @ TA = 25C (Note 1.) Linear Derating Factor (1) Total Power Dissipation @ TA = 25C (Note 2.) Linear Derating Factor (2) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 4.0 mH, VDS = 40 Vdc) Apk C mJ 162 THERMAL RESISTANCE Rating Thermal Resistance - Junction to Ambient, PCB Mount (Note 1.) - Junction to Ambient, PCB Mount (Note 2.) Symbol Typ. Max. Unit RJA RJA - - 62.5 90 C/W 1. When mounted on 1 square FR-4 or G-10 board (VGS = 10 V, @ 10 Seconds) 2. When mounted on minimum recommended FR-4 or G-10 board (VGS = 10 V, @ Steady State) 3. Repetitive rating; pulse width limited by maximum junction temperature. http://onsemi.com 522 MMDF3N04HD ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 40 - - 4.3 - - - - 0.015 0.15 2.5 10 - 0.013 500 1.0 - 2.0 4.9 3.0 - - - 55 79 80 100 gFS 2.0 4.5 - Mhos Ciss - 450 900 pF Coss - 130 230 Crss - 32 96 td(on) - 9.0 18 tr - 15 30 td(off) - 28 56 tf - 19 38 td(on) - 13 26 OFF CHARACTERISTICS (Cpk 2.0) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) (Notes 4. & 6.) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 40 Vdc, VGS = 0 Vdc) (VDS = 40 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) (Notes 4. & 6.) (Cpk 2.0) (Notes 4. & 6.) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 3.4 Adc) (VGS = 4.5 Vdc, ID = 1.7 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.7 Adc) (Note 4.) VGS(th) Vdc RDS(on) mV/C m DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 32 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 20 Vdc, ID = 3.4 Adc, VGS = 10 Vdc, RG = 6 ) (Note 4.) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 20 Vdc, ID = 1.7 Adc, VGS = 4.5 Vdc, RG = 6 ) (Note 4.) Fall Time Gate Charge (VDS = 40 Vdc, ID = 3.4 Adc, VGS = 10 Vdc) (Note 4.) tr - 77 144 td(off) - 17 34 tf - 20 40 QT - 13.9 28 Q1 - 2.1 - Q2 - 3.7 - Q3 - 5.4 - - - 0.87 0.8 1.5 - trr - 27 - ta - 20 - tb - 7.0 - QRR - 0.03 - ns ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 3.4 Adc, VGS = 0 Vdc) (Note 4.) (IS = 3.4 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 3.4 3 4 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) (Note 4.) Reverse Recovery Storage Charge 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. 6. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 523 VSD Vdc ns C MMDF3N04HD TYPICAL ELECTRICAL CHARACTERISTICS $ 47 6$ 4: 64 6 6 4$ 4 # 44 #: 9 , " #$ " # 6 9 8 4 #7 # 6 9 8 6 4 # #$ , " $$ 4$ 4 # 4 6 $ 9 : 8 7 , " #$ 7$ 7 8$ " 6$ 8 :$ : 9$ 9 $$ $ # 4 $ 6 9 Figure 4. On-Resistance versus Drain Current and Gate Voltage " " 46 " , " #$ $ $ ?#$ 6$ 6 Figure 2. Transfer Characteristics Figure 3. On-Resistance versus Gate-to-Source Voltage < 4 Figure 1. On-Region Characteristics 6 ?$ #$ $ # # " 46 , " #$ # $ $ # 9 , " #$ 9 #$ $ :$ #$ $ #$ $ $ # #$ 4 4$ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 524 6 MMDF3N04HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) # " " , " #$C *. %!! 7 9 (!! %!! 4 !! (!! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 525 #$ 4 6 @ 4 7 9 @ 4 # @# " 46 , " #$ @4 6 8 @D # 9 " # " 46 " , " #$ ' ! # MMDF3N04HD 'CC 'C '( ' Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 4$ , " #$ " 4 #$ # $ $ $ $$ 9 9$ : :$ 8 8$ 7 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 526 MMDF3N04HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For 9 " # " #$ GG - , ! ! " 7 # 8 6 #$ $ :$ #$ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 527 $ MMDF3N04HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ $ # 2%* ,;'% 6 4 # 9 64 964 #$4 . 69 . $96 . ' ! 5 %&' '(( '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 528 #7698 . 5 Figure 14. Thermal Response ') 4$: 64# ::6 . 5# +%1' 54 MMDF3N04HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 6 6 #8 $#8 #9 4# $ 48 #$9 9$ inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 529 MMDF3N04HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 530 (!. Preferred Device #$%& '( ! N-Channel SO-8, Dual These miniature surface mount MOSFETs feature low RDS(on) and true logic level performance. Dual MOSFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Mounting Information for SO-8 Package Provided http://onsemi.com 3 AMPERES 60 VOLTS RDS(on) = 100 mW N-Channel MARKING DIAGRAM MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Symbol Value Unit VDSS VGS 60 Vdc 20 Vdc ID IDM IS 3.3 16.5 Adc Apk 1.7 Adc PD 2.0 Watts TJ, Tstg - 55 to 150 C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 60 Vdc, VGS = 5.0 Vdc, VDS = 32 Vdc, IL = 15 Apk, L = 10 mH, RG = 25 ) EAS 105 mJ Thermal Resistance - Junction-to-Ambient RJA 62.5 TL 260 Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C Source Current - Continuous @ TA = 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds SO-8, Dual CASE 751 STYLE 11 8 D3N06 LYWW 1 L Y WW = Location Code = Year = Work Week PIN ASSIGNMENT C/W C Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 Top View 1. Mounted on G10/FR4 glass epoxy board using minimum recommended footprint. ORDERING INFORMATION Device MMDF3N06HDR2 This document contains information on a new product. Specifications and information herein are subject to change without notice. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 531 Package SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MMDF3N06HD/D MMDF3N06HD ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 60 - - - - 0.001 0.05 1.0 25 - 12 100 1.0 - - - - 67.5 82.5 100 200 - 7.5 - Ciss - 442 618 Coss - 97.6 137 Crss - 24.4 34.2 td(on) - 10.6 22.1 tr - 15.9 31.8 td(off) - 23.8 47.6 tf - 14.7 29.4 td(on) - 7.0 14 tr - 4.8 9.6 td(off) - 32.4 64.8 tf - 14.2 28.4 QT - 14.5 29 Q1 - 1.8 - Q2 - 3.5 - Q3 - 3.75 - - - 0.78 0.65 1.2 - trr - 27.9 - ta - 23 - tb - 4.9 - QRR - 0.038 - Unit OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 48 Vdc, VGS = 0 Vdc) (VDS = 48 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 3.3 Adc) (VGS = 4.5 Vdc, ID = 2.5 Adc) RDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc) Vdc mW gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 30 Vdc, ID = 3.3 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 30 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 3.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 30 Vdc, ID = 3.3 Adc, VGS = 10 Vdc) ns ns nC SOURCE-DRAIN DIODE CHARACTERISTICS VSD Forward On-Voltage (IS = 1.7 Adc, VGS = 0 Vdc) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 1.7 1 7 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 532 Vdc ns C MMDF3N06HD TYPICAL ELECTRICAL CHARACTERISTICS $ 44 4$ 4: 47 6$ 64 6 6 , " #$ #7 4 #: # #$ 9 4 " 9 # 9 6 8 # 9 6 8 100 25 4 , " $$ # $ #$ #:$ 4 Figure 2. Transfer Characteristics $ $ 4 6 $ 9 : 8 7 4#$ 4$ 6$ $ 7 , " #$ 8$ " 6$ 8 :$ : 9$ 9 $ # #$ 4 4$ 6 Figure 3. On-Resistance versus Gate-to-Source Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 " " $ < ##$ Figure 1. On-Region Characteristics # 6 # #$ 9 :$ " 4 , " #$ # 6 # 4 $ #4 # 9 # 8 9 6 " , " #$ #$ # ?$ ?#$ #$ $ :$ #$ $ $ $ # #$ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 533 4 MMDF3N06HD POWER MOSFET SWITCHING During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by http://onsemi.com 534 MMDF3N06HD '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 7. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 9). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 535 %!! , " #$C *. 8 (!! 9 %!! 6 # !! $ #$ $ $ # 4 # 7 # 8 : 9 $ @ 6 4 # # 'CC 'C '( ' " 4 , " #$ 6 9 8 # @D 6 9 #$ " 4 " 4 " , " #$ Figure 9. Gate-to-Source and Drain-to-Source Voltage versus Total Charge ' ! @# @4 Figure 8. Capacitance Variation 4 @ # MMDF3N06HD , " #$ " # $ $ $ 9 9$ : :$ $$ Figure 11. Diode Forward Voltage versus Current Figure 10. Resistive Switching Time Variation versus Gate Resistance http://onsemi.com 536 8 MMDF3N06HD # " # " #$ ! ! GG - , " 4 8 9 6 # #$ 6$ 9$ 8$ $ #$ 6$ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # 9 2%* ,;'% #$4 . 64 69 . ' ! 964 $96 . %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 537 #7698 . Figure 14. Thermal Response 4$: 64# ::6 . +%1' MMDF3N06HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 538 MMDF3N06HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 539 (! #$%& '( ! N-Channel SO-8, Dual Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * On-resistance Area Product about One-half that of Standard MOSFETs with New Low Voltage, Low RDS(on) Technology * Faster Switching than E-FETt Predecessors * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature * Static Parameters are the Same for both TMOS V and TMOS E-FET * Miniature SO-8 Surface Mount Package - Saves Board Space * Mounting Information for SO-8 Package Provided http://onsemi.com 3 AMPERES 60 VOLTS RDS(on) = 130 m N-Channel MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit VDSS VDGR 60 Vdc 60 Vdc VGS ID ID IDM PD 15 Vdc 3.3 0.7 10 Adc 2.0 W 1 TJ, Tstg -55 to 150 C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 3.3 Apk, L = 10 mH, RG = 25 ) EAS 54 mJ L Y WW Thermal Resistance, Junction to Ambient (Note 1.) RJA 62.5 C/W TL 260 C Rating Drain-to-Source Voltage Drain-to-Gate Voltage, (RGS = 1 M) Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes, 0.0625 from case for 10 seconds Apk MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 11 8 3N06V LYWW = Location Code = Year = Work Week PIN ASSIGNMENT Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 1. Mounted on G10/FR4 glass epoxy board using minimum recommended footprint. Top View ORDERING INFORMATION Device Package MMDF3N06VLR2 SO-8 Shipping 2500 Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 540 Publication Order Number: MMDF3N06VL/D MMDF3N06VL ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 66 - - - - - - 10 100 - - 100 1.0 - 1.5 3.0 2.0 - - 0.12 0.13 - - - - 0.5 0.4 gFS 1.0 3.0 - Mhos pF OFF CHARACTERISTICS V(BR)DSS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 5.0 Vdc, ID = 3.3 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 5.0 Vdc, ID = 3.3 Adc) (VGS = 5.0 Vdc, ID = 1.65 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 1.65 Adc) Vdc mV/C Ohm Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance Ciss - 340 480 Coss - 110 150 Crss - 27 50 td(on) - 10 20 tr - 30 60 td(off) - 32 60 tf - 28 60 QT - 9.0 20 Q1 - 1.5 - Q2 - 4.3 - Q3 - 3.5 - VSD - - 0.84 0.67 1.2 - Vdc trr - 58 - ns ta - 38 - tb - 20 - QRR - 0.11 - SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 30 Vdc, ID = 3.3 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (VDS = 48 Vdc, ID = 3.3 Adc, VGS = 5.0 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) (IS = 3.3 Adc, VGS = 0 Vdc) (IS = 3.3 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 3.3 3 3 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 541 C (. Preferred Device #$%& '( N-Channel SO-8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Mounting Information for SO-8 Package Provided http://onsemi.com 4 AMPERES 20 VOLTS RDS(on) = 45 m N-Channel MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 11 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Symbol Value Unit Drain-to-Source Voltage VDSS 20 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 20 Vdc Gate-to-Source Voltage - Continuous VGS 12 Vdc Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 5.2 4.1 48 Adc Total Power Dissipation @ TA = 25C (Note 1.) PD 2.0 Watts TJ, Tstg - 55 to 150 C Operating and Storage Temperature Range 8 1 L Y WW Apk Thermal Resistance - Junction to Ambient (Note 1.) RJA 62.5 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 260 C 1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max. D4N01 LYWW = Location Code = Year = Work Week PIN ASSIGNMENT Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 Top View ORDERING INFORMATION Device MMDF4N01HDR2 Package SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 6 542 Publication Order Number: MMDF4N01HD/D MMDF4N01HD ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 20 - - 2.0 - - - - - - 1.0 10 - - 100 0.6 - 0.8 2.8 1.1 - - - 0.035 0.043 0.045 0.055 gFS 3.0 6.0 - mhos Ciss - 425 595 pF Coss - 270 378 Crss - 115 230 td(on) - 13 26 tr - 60 120 td(off) - 20 40 tf - 29 58 td(on) - 10 20 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 12 Vdc, VGS = 0 Vdc) (VDS = 12 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 8.0 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 4.0 Adc) (VGS = 2.7 Vdc, ID = 2.0 Adc) RDS(on) Forward Transconductance (VDS = 2.5 Vdc, ID = 2.0 Adc) Vdc mV/C Ohm DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 6.0 Vdc, ID = 4.0 Adc, VGS = 2 2.7 7 Vdc Vdc, RG = 2.3 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 6.0 Vdc, ID = 4.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 2.3 ) Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 10 Vdc, ID = 4.0 Adc, VGS = 4.5 Vdc) tr - 42 84 td(off) - 24 48 tf - 28 56 QT - 9.2 13 Q1 - 1.3 - Q2 - 3.5 - Q3 - 3.0 - - - 0.95 0.78 1.1 - trr - 38 - ta - 17 - tb - 22 - QRR - 0.028 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) (IS = 4.0 Adc, VGS = 0 Vdc) (IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 4.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 543 VSD Vdc ns C MMDF4N01HD TYPICAL ELECTRICAL CHARACTERISTICS 8 , " #$ # 6 7 : # #4 #$ " 8 6$ 4 9 #: $ 4 # 6 9 8 # 6 9 8 6 #$ , " ?$$ # 6 9 # 6 8 $ " #: 6$ 6 6$ 4$ 4 # 8 " " 6$ " 6 , " #$ $ 6 9 Figure 4. On-Resistance versus Drain Current and Gate Voltage # ?#$ ## , " #$ Figure 3. On-Resistance versus Gate-To-Source Voltage < # Figure 2. Transfer Characteristics $ ?$ 8 Figure 1. On-Region Characteristics 9 $ 9 6 , " #$ " # # : 4 9 # 8 #$ $ :$ #$ $ , , 9 8 # 6 Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 544 # MMDF4N01HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) # " *. 9 " , " #$ %!! # (!! 8 %!! !! 6 (!! 8 6 6 8 # Figure 7. Capacitance Variation http://onsemi.com 545 6 8 4 @ 9 @# " 6 , " #$ # 6 # @4 # @ 6 9 8 ' ! $ MMDF4N01HD " 9 " 6 " 6$ , " #$ '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 6 4 " " ,," "#$ #$ # 4 6 $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 546 MMDF4N01HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the " # " #$ ! ! ! ! ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L Figure 12. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 547 MMDF4N01HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # 2%* $ 6 4 # :$ : #:9 $6 . 8$6 . 4:6 . ' ! 5 %&' '(( '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 548 :87 . 5 Figure 13. Thermal Response ') $::9 :89 :$$ . 5# +%1' 54 MMDF4N01HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 549 MMDF4N01HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 15. Typical Solder Heating Profile http://onsemi.com 550 ( 8 #$%& '( N-Channel SO-8, Dual EZFETst are an advanced series of Power MOSFETs which contain monolithic back-to-back zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. * Zener Protected Gates Provide Electrostatic Discharge Protection * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Mounting Information for SO-8 Package Provided http://onsemi.com 5 AMPERES 20 VOLTS RDS(on) = 40 m N-Channel D G S MARKING DIAGRAM MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 70C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Thermal Resistance Ambient - Junction to Symbol Value Unit VDSS VDGR 20 Vdc 20 Vdc VGS ID ID IDM PD 12 Vdc 5.0 4.5 40 Adc 1 Apk 2.0 Watts TJ, Tstg - 55 to 150 C 5N02Z L Y WW RJA 62.5 C/W 260 C Maximum Temperature for Soldering TL 1. When mounted on 1 inch square FR-4 or G-10 board (VGS = 4.5 V, @ 10 Seconds). SO-8, Dual CASE 751 STYLE 11 8 5N02Z LYWW = Device Code = Location Code = Year = Work Week PIN ASSIGNMENT Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 Top View ORDERING INFORMATION Semiconductor Components Industries, LLC, 2001 January, 2001 - Rev. 2 551 Device Package MMDF5N02ZR2 SO-8 Shipping 2500 Tape & Reel Publication Order Number: MMDF5N02Z/D MMDF5N02Z ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 20 - - 15 - - - - - - - - 0.5 15 150 - - 1.5 0.5 - 0.78 3.0 1.1 - - - 34 44 40 50 gFS 3.0 5.6 - Mhos Ciss - 450 630 pF Coss - 330 460 Crss - 160 225 td(on) - 29 37 OFF CHARACTERISTICS (Cpk 2.0) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) (Note 4.) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 12 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc Adc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) Static Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 5.0 Adc) (VGS = 2.7 Vdc, ID = 2.5 Adc) (Cpk 2.0) (Note 4.) (Note 4.) Forward Transconductance (VDS = 9.0 Vdc, ID = 2.0 Adc) VGS(th) Vdc RDS(on) mV/C m DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 6.0 Vdc, ID = 5.0 Adc, VGS = 4.5 Vdc, RG = 6 ) Fall Time Gate Charge (VDS = 10 Vdc, ID = 5.0 Adc, VGS = 4.5 Vdc) tr - 182 258 td(off) - 190 238 tf - 225 274 QT - 10.7 12 Q1 - 1.1 - Q2 - 5.4 - Q3 - 3.5 - - - 0.78 0.65 1.0 - trr - 195 - ta - 72 - tb - 123 - QRR - 0.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 5.0 Adc, VGS = 0 Vdc) (IS = 5.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 5.0 5 0 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 552 VSD Vdc ns C MMDF5N02Z TYPICAL ELECTRICAL CHARACTERISTICS " # 6$ #: 8 8 , " #$ # #4 7 9 8 6 : # 9 $ , " #$ : 9 $ 6 4 # #$ 6 # 8 9 # $ # #$ Figure 2. Transfer Characteristics 9 $ 6 4 # # 4 6 9 : $ 8 8 , " #$ : 9 $ " #: 6 6$ 4 # # 4 6 $ 9 : 8 Figure 3. On-Resistance versus Gate-to-Source Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage 9 " 6$ " #$ " , " #$ # < Figure 1. On-Region Characteristics " $ , " #$ 6 $ : , " $$ 8 9 6 #$ # ?$ ?#$ #$ $ :$ #$ $ #$ $ :$ #$ $ :$ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 553 # MMDF5N02Z POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6 " , " #$C " *. # %!! 8 (!! 9 %!! 6 !! # (!! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 554 9 $ @ 6 $ 6 @4 4 @ 4 @# # # " $ , " #$ # 6 9 8 # 6 ' ! 9 MMDF5N02Z " 9 " $ " 6$ , " #$ 'C 'CC '( ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by http://onsemi.com 555 MMDF5N02Z $ " , " #$ 6$ 6 4$ 4 #$ # $ $ # 4 6 $ 9 : 8 Figure 10. Diode Forward Voltage versus Current %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA the total power averaged over a complete switching cycle must not exceed (T J(MAX) - T C )/(RJC ). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (T C ) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (I DM ) nor rated voltage (V DSS ) is exceeded, and that the transition time (t r, tf ) does not exceed 10 s. In addition http://onsemi.com 556 MMDF5N02Z " # " #$ ! ! Figure 12. Maximum Rated Forward Biased Safe Operating Area TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # $ 6 4 # ' ! 5 5 Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 557 5# 54 MMDF5N02Z INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 0.060 1.52 0.275 7.0 0.155 4.0 0.024 0.6 0.050 1.270 inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 558 MMDF5N02Z TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 15. Typical Solder Heating Profile http://onsemi.com 559 (!. Preferred Device #$%& '( ! N-Channel SO-8, Dual These miniature surface mount MOSFETs feature low RDS(on) and true logic level performance. Dual MOSFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Mounting Information for SO-8 Package Provided http://onsemi.com 6 AMPERES 30 VOLTS RDS(on) = 35 mW N-Channel MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Symbol Value Unit VDSS VGS 30 Vdc 20 Vdc ID IDM IS 6.0 30 Adc Apk 1.7 Adc PD 2.0 Watts TJ, Tstg - 55 to 150 C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 30 Vdc, VGS = 5.0 Vdc, VDS = 20 Vdc, IL = 9.0 Apk, L = 10 mH, RG = 25 W) EAS 325 mJ Thermal Resistance - Junction-to-Ambient RJA 62.5 C/W TL 260 C Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C Drain Current - Single Pulse (tp 10 s) Source Current - Continuous @ TA = 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 sec. MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 11 8 D6N03 LYWW 1 D6N03 L Y WW = Device Code = Location Code = Year = Work Week PIN ASSIGNMENT 1. Mounted on G10/FR4 glass epoxy board using minimum recommended footprint. Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 Top View ORDERING INFORMATION Device MMDF6N03HDR2 Package SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 560 Publication Order Number: MMDF6N03HD/D MMDF6N03HD ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - - - - - 1.0 20 - - 100 1.0 - - - - 28 42 35 50 gFS - 9.0 - Mhos Ciss - 430 600 pF Coss - 217 300 Crss - 67.5 135 td(on) - 8.2 16.4 tr - 8.48 16.9 td(off) - 89.6 179 tf - 61.1 122 td(on) - 11.8 23 tr - 51.3 102 td(off) - 47.2 94.5 tf - 62 104 QT - 15.7 31.4 Q1 - 2.0 - Q2 - 4.6 - Q3 - 3.86 - - - 0.77 0.65 1.2 - trr - 54.5 - ta - 14.8 - tb - 39.7 - QRR - 0.048 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 Vdc) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 5.0 Adc) (VGS = 4.5 Vdc, ID = 3.9 Adc) RDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc) Vdc m DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 24 Vdc, VGS = 0 Vdc, f=1 1.0 0 MH MHz)) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time (VDD = 15 Vdc Vdc, VGS = 10 Vdc, ID = 1.0 Adc, RG = 6 0 ) 6.0 Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time (VDD = 15 Vdc Vdc, VGS = 4.5 Vdc, ID = 1.0 Adc, RG = 6 0 ) 6.0 Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 15 Vdc, ID = 5 5.0 0 Adc Adc, VGS = 10 Vdc) ns ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 1.7 Adc, VGS = 0 Vdc) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 5.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 561 VSD Vdc ns C MMDF6N03HD TYPICAL ELECTRICAL CHARACTERISTICS 47 9 6$ 4$ 64 6 8 44 9 4 6 #7 # # , " #$ 4: # " #$ # 6 9 8 # 6 #: 8 9 8 9 , " $$ # $ # # , " #$ " 9 # $ $ 4 6 $ 9 : 8 7 6$ 6$ $ " 6$ 6 4$ 4 #$ 6 4 # $ 9 : 8 7 Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 " " 4 < 6 , " #$ Figure 3. On-Resistance versus Gate-To-Source Voltage 6 4$ $ 9 4 Figure 2. Transfer Characteristics 4 # #$ Figure 1. On-Region Characteristics #$ #$ 6 # 8 9 6 " , " #$ #$ # $ #$ #$ $ :$ #$ $ , , $ $ # #$ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 562 4 MMDF6N03HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) # , " #$ *. 8 9 %!! 6 !! # (!! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 563 #$ 4 4 7 @ 8 : 9 $ " $ , " #$ 6 4 # @4 # 6 9 8 # 9 6 " $ " 9 " , " #$ # @# @ ' ! # MMDF6N03HD 'CC 'C '( ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by $ 6$ 6 " , " #$ 4$ 4 #$ # $ $ $ $$ 9 9$ : :$ 8 8$ 7 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 564 MMDF6N03HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. " # " #$ - , The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the ! ! 4$ " 9 4 #$ # $ $ #$ 6$ 9$ 8$ $ #$ 6$ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 565 MMDF6N03HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # , 9 W 64 W 964 W 4$: W 64# W #$4 . 69 . $96 . #7698 . ::6 . = $ 6 4 # ' ! 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 566 5 5# 54 MMDF6N03HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.0 Watts 62.5C/W The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 567 MMDF6N03HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 568 (" 8 #$%& '( " N-Channel SO-8, Dual EZFETst are an advanced series of Power MOSFETs which contain monolithic back-to-back zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. http://onsemi.com 7 AMPERES 20 VOLTS RDS(on) = 27 m N-Channel D G * Zener Protected Gates Provide Electrostatic Discharge Protection * Designed to Withstand 200 V Machine Model and 2000 V Human Body Model S * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery * * * * * * Life Logic Level Gate Drive - Can be Driven by Logic ICs Miniature SO-8 Surface Mount Package - Saves Board Space Diode is Characterized for use in Bridge Circuits Diode Exhibits High Speed, with Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SO-8 Package Provided MARKING DIAGRAM SO-8, Dual CASE 751 STYLE 11 8 7N02Z LYWW 1 7N02Z L Y WW = Device Code = Location Code = Year = Work Week PIN ASSIGNMENT Source-1 1 8 Drain-1 Gate-1 2 7 Drain-1 Source-2 3 6 Drain-2 Gate-2 4 5 Drain-2 Top View ORDERING INFORMATION Semiconductor Components Industries, LLC, 2001 January, 2001 - Rev. 1 569 Device Package MMDF7N02ZR2 SO-8 Shipping 2500 Tape & Reel Publication Order Number: MMDF7N02Z/D MMDF7N02Z MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Drain Current Continuous @ TA = 25C (Note 1.) Continuous @ TA = 70C (Note 1.) Pulsed Drain Current (Note 3.) Symbol Max Unit VDSS VDGR VGS 20 Vdc 20 Vdc 12 Vdc Adc Total Power Dissipation @ TA = 25C (Note 1.) Linear Derating Factor @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Linear Derating Factor @ TA = 25C (Note 2.) Operating and Storage Temperature Range ID ID IDM PD 7.0 4.6 35 2.0 16 Watts mW/C PD 1.39 11.11 Watts mW/C TJ, Tstg - 55 to 150 C THERMAL RESISTANCE Parameter Symbol Typ Max Unit RqJA - - 62.5 90 C/W Unit Junction-to-Ambient (Note 1.) Junction-to-Ambient (Note 2.) ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Symbol Characteristic Min Typ Max 20 - - 15 - - - - - - 1.0 10 - - 3.0 0.5 - 0.7 2.5 1.0 - - - 23 30 27 35 11 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) (Cpk 2.0) (Notes 4. & 5.) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc Adc ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (Cpk 2.0) (Notes 4. & 5.) (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) (Cpk 2.0) (Notes 4. & 5.) RDS(on) Static Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 7.0 Adc) (VGS = 2.5 Vdc, ID = 3.5 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc) (Note 4.) 1. 2. 3. 4. 5. Vdc m gFS 5.0 When mounted on 1 square FR4 or G-10 board (VGS = 10 V, @ 10 seconds). When mounted on minimum recommended FR4 or G-10 board (VGS = 10 V, @ Steady State). Repetitive rating; pulse width limited by maximum junction temperature. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 570 mV/C Mhos MMDF7N02Z ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Ciss - 450 630 pF Coss - 350 490 Crss - 110 155 td(on) - 31 62 tr - 230 460 td(off) - 725 1450 DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 7.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 1.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) (Note 6.) Fall Time Gate Charge S Fi See Figure 8 (VDS = 12 Vdc, ID = 5.0 Adc, VGS = 4.5 Vdc) (Note 6.) ns tf - 780 1560 QT - 17 24 Q1 - 1.4 - Q2 - 6.7 - Q3 - 6.5 - VSD - - 0.90 0.84 1.1 - Vdc trr - 780 - ns ta - 190 - tb - 590 - QRR - 5.7 - nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 7.0 Adc, VGS = 0 Vdc) (Note 6.) (IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 7.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 6.) Reverse Recovery Stored Charge 6. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 7. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 571 C MMDF7N02Z 2.1 V , " #$_ 4.5 V # 1.9 V 7 " : 9 4 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 2.3 V 10 V $ $ # 7 #$_ 9 , " _ 4 ?$$_ 4 # # #$ 6 9 8 # $ , " #$_ 6 " #: 4 6$ # Figure 3. On-Resistance versus Drain Current # 6 9 8 # Figure 4. On-Resistance versus Drain Current and Gate Voltage # " 6$ " 4$ I DSS , LEAKAGE (nA) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) $ Figure 2. Transfer Characteristics 6 $ Figure 1. On-Region Characteristics $ $ $ " : , " #$_ 9 $ # RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) ID, DRAIN CURRENT (AMPS) $ ID, DRAIN CURRENT (AMPS) TYPICAL ELECTRICAL CHARACTERISTICS " , " #$_ _ #$_ ?$ ?#$ #$ $ :$ #$ $ , , _ 6 8 # 9 Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 572 # MMDF7N02Z POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) C, CAPACITANCE (pF) 4 " " , " #$_ #$ # %!! $ $ %!! !! (!! !! (!! $ $ $ Figure 7. Capacitance Variation http://onsemi.com 573 # $ @ 6 # 4 7 # @ @# 9 , " #$_ @4 $ # $ 4 @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge td(off) " #$ " , " #$_ t, TIME (ns) $ VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) MMDF7N02Z tf tr td(on) Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by IS, SOURCE CURRENT (AMPS) : 9 , " #$_ $ 6 4 # 6 $ 9 : 8 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 574 MMDF7N02Z '))( 1EE 1!%'H '(( I S, SOURCE CURRENT %&' " 4 &! %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the ID, DRAIN CURRENT (AMPS) " 6$ " #$_ ! ! Figure 12. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 575 MMDF7N02Z TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t) , EFFECTIVE TRANSIENT THERMAL RESISTANCE " $ # $ # P(pk) t1 $ t2 DUTY CYCLE, D = t1/t2 6 4 # ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 t, TIME (s) Figure 13. Thermal Response di/dt IS ta trr tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 576 5# 54 MMDF7N02Z INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD + 150C * 25C + 2.0 Watts 62.5CW The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. T (max) * TA PD + J RqJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 577 MMDF7N02Z TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows < O P # # OP 4 < # Q $ O P . = $ 6 < 4 Q 9 OP 9 9 6 @ . 6 8 . =- . / = $ 4 : > Figure 15. Typical Solder Heating Profile http://onsemi.com 578 : #$ #7 , : $ $ < 6 Q : O P ( # #$%& '( P-Channel SO-8, FETKYt The FETKY product family incorporates low RDS(on), true logic level MOSFETs packaged with industry leading, low forward drop, low leakage Schottky Barrier rectifiers to offer high efficiency components in a space saving configuration. Independent pinouts for MOSFET and Schottky die allow the flexibility to use a single component for switching and rectification functions in a wide variety of applications such as Buck Converter, Buck-Boost, Synchronous Rectification, Low Voltage Motor Control, and Load Management in Battery Packs, Chargers, Cell Phones and other Portable Products. * Power MOSFET with Low VF, Low IR Schottky Rectifier * Lower Component Placement and Inventory Costs along with Board Space Savings * Logic Level Gate Drive - Can be Driven by Logic ICs * Mounting Information for SO-8 Package Provided * IDSS Specified at Elevated Temperature * Applications Information Provided http://onsemi.com 2 AMPERES 20 VOLTS RDS(on) = 160 mW VF = 0.39 Volts P-Channel D G S MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.) Rating Symbol Value Unit Drain-to-Source Voltage VDSS 20 Vdc Drain-to-Gate Voltage (RGS = 1.0 MW) VDGR 20 Vdc Gate-to-Source Voltage - Continuous VGS "20 Vdc Drain Current (Note 3.) - Continuous @ TA = 25C - Continuous @ TA = 100C - Single Pulse (tp v 10 ms) ID ID IDM 3.3 2.1 20 Adc PD 2.0 Watts EAS 324 mJ Total Power Dissipation @ TA = 25C (Note 2.) Single Pulse Drain-to-Source Avalanche Energy - STARTING TJ = 25C VDD = 30 Vdc, VGS = 5.0 Vdc, VDS = 20 Vdc, IL = 9.0 Apk, L = 10 mH, RG = 25 W MARKING DIAGRAM SO-8 CASE 751 STYLE 18 8 1 L Y WW Apk 1. Negative sign for P-channel device omitted for clarity. 2. Pulse Test: Pulse Width 250 s, Duty Cycle 2.0%. 3. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max. 2P102 LYWW = Location Code = Year = Work Week PIN ASSIGNMENT Anode 1 8 Cathode Anode 2 7 Cathode Source 3 6 Drain 4 5 Drain Gate Top View ORDERING INFORMATION Device MMDFS2P102R2 Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 579 Package SO-8 Shipping 2500 Tape & Reel Publication Order Number: MMDFS2P102/D MMDFS2P102 SCHOTTKY RECTIFIER MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Peak Repetitive Reverse Voltage DC Blocking Voltage VRRM VR 20 Volts IO 1.0 Amps Peak Repetitive Forward Current (Note 3.) (Rated VR, Square Wave, 20 kHz) TA = 105C Ifrm 2.0 Amps Non-Repetitive Peak Surge Current (Surge applied at rated load conditions, halfwave, single phase, 60 Hz) Ifsm 20 Amps Average Forward Current (Note 4.) (Rated VR) TA = 100C THERMAL CHARACTERISTICS - SCHOTTKY AND MOSFET Thermal Resistance - Junction-to-Ambient (Note 5.) - MOSFET RqJA 167 Thermal Resistance - Junction-to-Ambient (Note 6.) - MOSFET RqJA 100 Thermal Resistance - Junction-to-Ambient (Note 3.) - MOSFET RqJA 62.5 Thermal Resistance - Junction-to-Ambient (Note 5.) - Schottky RqJA 204 Thermal Resistance - Junction-to-Ambient (Note 6.) - Schottky RqJA 122 Thermal Resistance - Junction-to-Ambient (Note 4.) - Schottky Operating and Storage Temperature Range RqJA 83 Tj, Tstg -55 to 150 4. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max. 5. Mounted with minimum recommended pad size, PC Board FR4. 6. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), Steady State. http://onsemi.com 580 C/W MMDFS2P102 MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 7.) Characteristic Symbol Min Typ Max Unit 20 - - 25 - - Vdc mV/C - - - - 1.0 10 - - 100 1.0 - 1.5 4.0 2.0 - - - 0.118 0.152 0.160 0.180 gFS 2.0 3.0 - mhos pF OFF CHARACTERISTICS Drain-Source Voltage (VGS = 0 Vdc, ID = 0.25 mA) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc nAdc ON CHARACTERISTICS (Note 8.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mA) Temperature Coefficient (Negative) VGS(th) Static Drain-Source Resistance (VGS = 10 Vdc, ID = 2.0 Adc) (VGS = 4.5 Vdc, ID = 2.5 Adc) RDS(on) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) Vdc mV/C Ohms DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance Ciss - 420 588 Coss - 290 406 Crss - 116 232 td(on) - 19 38 tr - 66 132 td(off) - 25 50 tf - 37 74 QT - 15 20 Q1 - 1.2 - Q2 - 5.0 - Q3 - 4.0 - - 1.5 2.1 trr - 38 - ta - 17 - tb - 21 - QRR - 0.034 - SWITCHING CHARACTERISTICS (Note 9.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS = 10 Vdc, ID = 2.0 Adc, 5 Vdc VGS = 4 4.5 Vdc, RG = 6.0 ) Fall Time Gate Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) ns nC DRAIN SOURCE DIODE CHARACTERISTICS Forward On-Voltage (Note 8.) (IS = 2.0 Adc, VGS = 0 Vdc) VSD Reverse Recovery Time (IS = 2.0 2 0 Adc, Adc VDD = 15 V V, dIS/dt = 100 A/s) Reverse Recovery Stored Charge V ns C SCHOTTKY RECTIFIER ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) g (Note ( Maximum Instantaneous Forward Voltage 8.)) IF = 1.0 10A IF = 2.0 A VF Maximum Instantaneous Reverse Current (Note ( 8.)) VR = 20 V IR Maximum Voltage Rate of Change VR = 20 V 7. Negative sign for P-channel device omitted for clarity. 8. Pulse Test: Pulse Width 300 sec, Duty Cycle 2.0%. 9. Switching characteristics are independent of operating temperature. http://onsemi.com 581 dV/dt TJ = 25C TJ = 125C 0.47 0.58 0.39 0.53 TJ = 25C TJ = 125C 0.05 10 10,000 Volts mA V/ms MMDFS2P102 TYPICAL FET ELECTRICAL CHARACTERISTICS 6$ 48 6 , " #$ 6 4 4 # # 4 #$ , " $$ " #6 # 6 9 8 # 6 9 8 $ 9 , " #$ " 6 4 # # 6 9 8 # , " #$ " 6$ 9 # 8 6 $ Figure 3. On-Resistance versus Gate-To-Source Voltage # #$ 4 4$ 6 Figure 4. On-Resistance versus Drain Current and Gate Voltage 9 " " " # < $ 6 4$ 4 Figure 2. Transfer Characteristics Figure 1. On-Region Characteristics #$ $ # # , " #$ 8 9 $ #$ #$ $ :$ #$ $ $ $ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 582 # MMDFS2P102 TYPICAL FET ELECTRICAL CHARACTERISTICS " %!! *. " # , " #$ 8 9 %!! (!! 6 !! # (!! ?$ $ $ 8 # @ 9 6 # 8 @ 6 # 8 @# " # , " #$ # 9 @4 6 8 9 6 # 9 # @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 7. Capacitance Variation # ' ! 'CC 'C '( ' " , " #$ 9 # 8 6 $ ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L " # " #$ ! ! m! m! 4 $ Figure 10. Diode Forward Voltage versus Current 4$ - , 7 Figure 9. Resistive Switching Time Variation versus Gate Resistance : " 9 4 #$ # $ $ #$ $ :$ #$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 583 MMDFS2P102 TYPICAL FET ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # :$ W : W #:9 W $::9 W :89 W , < q, - $6 . 8$6 . 4:6 . :87 . :$$ . $ 6 = 4 # ' ! 5 5# 5 54 Figure 13. FET Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform , " #$ 8$ #$ ?6 # 4 6 $ 9 : 8 7 . . / . . / TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS , " #$ 8$ #$ . . / # 6 9 8 # . > . / Figure 15. Typical Forward Voltage Figure 16. Maximum Forward Voltage http://onsemi.com 584 6 MMDFS2P102 TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS > # , " #$ 4 8$ 6 $ #$ 9 : $ $ # , " #$ # 4 6 #$ $ 9 $ . / - " : *. $ $ # 9 6 *0& " p 8 *0& " $ 9 *0& " 6 *0& " # # . @ " # 0A @ / # # 6 9 9 4 @ / *0& " p *0& " $ 6 *0& " *0& " # # # Figure 20. Current Derating : $ 8 = Figure 19. Typical Capacitance . / / *. Figure 18. Maximum Reverse Current # Figure 17. Typical Reverse Current $ $ $ . / Figure 21. Forward Power Dissipation http://onsemi.com 585 # 6 9 MMDFS2P102 TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ < q, - # 4 W , 6 . $6 W $# W 6$:$ W 4:7 W 8# . $# . #:6 . $896 . $ 6 = 4 # ' ! 5 5 5# Figure 22. Schottky Thermal Response TYPICAL APPLICATIONS STEP DOWN SWITCHING REGULATORS 5 5 % ;' Buck Regulator 5 5 % ;' Synchronous Buck Regulator http://onsemi.com 586 54 MMDFS2P102 TYPICAL APPLICATIONS STEP UP SWITCHING REGULATORS 5 5 % ;' @ Boost Regulator 5 5 % ;' Buck-Boost Regulator MULTIPLE BATTERY CHARGERS Buck Regulator/Charger @ @# # = R 5 % @4 4 = R# http://onsemi.com 587 MMDFS2P102 TYPICAL APPLICATIONS Li-lon BATTERY PACK APPLICATIONS Battery Pack 5 % = SMART IC @ @# - - * Applicable in battery packs which require a high current level. * During charge cycle Q2 is on and Q1 is off. Schottky can reduce power loss during fast charge. * During discharge Q1 is on and Q2 is off. Again, Schottky can reduce power dissipation. * Under normal operation, both transistors are on. http://onsemi.com 588 (!! #$%& '( ! N-Channel SO-8, FETKYt http://onsemi.com The FETKY product family incorporates low RDS(on), true logic level MOSFETs packaged with industry leading, low forward drop, low leakage Schottky Barrier rectifiers to offer high efficiency components in a space saving configuration. Independent pinouts for MOSFET and Schottky die allow the flexibility to use a single component for switching and rectification functions in a wide variety of applications such as Buck Converter, Buck-Boost, Synchronous Rectification, Low Voltage Motor Control, and Load Management in Battery Packs, Chargers, Cell Phones and other Portable Products. * Power MOSFET with Low VF * Lower Component Placement and Inventory Costs along with Board Space Savings * Logic Level Gate Drive -- Can be Driven by Logic ICs * Mounting Information for SO-8 Package Provided * Applications Information Provided * R2 Suffix for Tape and Reel (2500 units/13 reel) * Marking: 6N303 6 AMPERES 30 VOLTS RDS(on) = 35 mW VF = 0.42 Volts N-Channel D G S MARKING DIAGRAM MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.) Rating Symbol Value Drain-to-Source Voltage VDSS 30 Vdc Drain-to-Gate Voltage (RGS = 1.0 MW) VDGR 30 Vdc Gate-to-Source Voltage -- Continuous VGS "20 Vdc Drain Current (Note 2.) - Continuous @ TA = 25C - Single Pulse (tp v 10 ms) ID IDM 6.0 30 Adc Apk PD 2.0 Watts EAS 325 mJ Total Power Dissipation @ TA = 25C (Note 2.) Single Pulse Drain-to-Source Avalanche Energy -- Startin TJ = 25C VDD = 30 Vdc, VGS = 5.0 Vdc, VDS = 20 Vdc, IL = 9.0 Apk, L = 10 mH, RG = 25 W SO-8 CASE 751 STYLE 18 Unit 8 6N303 LYWW 1 6N303 L Y WW = Device Code = Location Code = Year = Work Week PIN ASSIGNMENT 1. Pulse Test: Pulse Width 250 s, Duty Cycle 2.0%. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max. Anode 1 8 Cathode Anode 2 7 Cathode Source 3 6 Drain 4 5 Drain Gate Top View ORDERING INFORMATION Device MMDFS6N303R2 Package SO-8 Shipping 2500 Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 589 Publication Order Number: MMDFS6N303/D MMDFS6N303 SCHOTTKY RECTIFIER MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Peak Repetitive Reverse Voltage DC Blocking Voltage VRRM VR Average Forward Current (Note 3.) (Rated VR) TA = 104C 30 Volts IO Amps 2.0 Peak Repetitive Forward Current (Note 3.) (Rated VR, Square Wave, 20 kHz) TA = 108C Ifrm Amps Non-Repetitive Peak Surge Current (Surge applied at rated load conditions, halfwave, single phase, 60 Hz) Ifsm 30 Amps Thermal Resistance -- Junction-to-Ambient (Note 4.) -- MOSFET RqJA 167 C/W Thermal Resistance -- Junction-to-Ambient (Note 5.) -- MOSFET RqJA 97 Thermal Resistance -- Junction-to-Ambient (Note 2.) -- MOSFET RqJA 62.5 Thermal Resistance -- Junction-to-Ambient (Note 4.) -- Schottky RqJA 197 Thermal Resistance -- Junction-to-Ambient (Note 5.) -- Schottky RqJA 97 4.0 THERMAL CHARACTERISTICS -- SCHOTTKY AND MOSFET Thermal Resistance -- Junction-to-Ambient (Note 3.) -- Schottky Operating and Storage Temperature Range RqJA 62.5 Tj, Tstg -55 to 150 MOSFET ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 6.) Characteristic Symbol Min Typ Max Unit 30 -- -- -- -- -- Vdc mV/C -- -- -- -- 1.0 20 -- -- 100 1.0 -- -- -- -- -- -- -- 28 42 35 50 gFS -- 9.0 -- mhos pF OFF CHARACTERISTICS Drain-Source Voltage (VGS = 0 Vdc, ID = 0.25 mA) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Drain Current (VDS = 24 Vdc, VGS = 0 Vdc) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc nAdc ON CHARACTERISTICS (Note 6.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mA) Temperature Coefficient (Negative) VGS(th) Static Drain-Source Resistance (VGS = 10 Vdc, ID = 5.0 Adc) (VGS = 4.5 Vdc, ID = 3.9 Adc) RDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc) Vdc mW DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance 3. 4. 5. 6. Ciss -- 430 600 Coss -- 217 300 Crss -- 67.5 135 Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max. Mounted with minimum recommended pad size, PC Board FR4. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), Steady State. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. http://onsemi.com 590 MMDFS6N303 MOSFET ELECTRICAL CHARACTERISTICS - continued (TC = 25C unless otherwise noted) (Note 7.) Characteristic Symbol Min Typ Max Unit td(on) -- 8.2 16.5 ns tr -- 8.5 17 td(off) -- 89.6 179 tf -- 61.1 122 QT -- 15.7 31.4 Q1 -- 2.0 -- Q2 -- 4.6 -- Q3 -- 3.9 -- -- 0.77 1.2 trr -- 54.5 -- ta -- 14.8 -- tb -- 39.7 -- QRR -- 0.048 -- SWITCHING CHARACTERISTICS (Note 8.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 1.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) Fall Time Gate Charge (VDS = 15 Vdc, ID = 5.0 Adc, VGS = 10 Vdc) nC DRAIN SOURCE DIODE CHARACTERISTICS Forward On-Voltage (Note 7.) (IS = 1.7 Adc, VGS = 0 Vdc) VSD Reverse Recovery Time (VGS = 0 V V, IS = 5.0 50A A, dIS/dt = 100 A/s) Reverse Recovery Stored Charge Vdc ns C SCHOTTKY RECTIFIER ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) g (Note ( Maximum Instantaneous Forward Voltage 7.)) IF = 100 mAdc Ad IF = 3.0 Adc IF = 6.0 Adc VF Maximum Instantaneous Reverse Current (Note ( 7.)) VR = 30 V IR Maximum Voltage Rate of Change VR = 30 V 7. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. 8. Switching characteristics are independent of operating junction temperature. http://onsemi.com 591 dV/dt TJ = 25C TJ = 125C 0.28 0.42 0.50 0.13 0.33 0.45 TJ = 25C TJ = 125C 250 -- -- 25 10,000 Volts mA mA V/ms MMDFS6N303 TYPICAL FET ELECTRICAL CHARACTERISTICS # 47 6$ , " #$ # 4$ 8 44 9 6 " #7 # # 6 9 8 # 6 9 8 8 #$ 9 6 #$ , " $$ # # #$ $ 4 , " #$ " 9 # 6 # 9 8 $ " 6$ 6 4 # # 6 < 9 $ :$ 9 : 8 7 " " " 9 #$ $ Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 6 4 Figure 3. On-Resistance versus Gate-To-Source Voltage #$ $$ , " #$ # $ 6$ Figure 2. Transfer Characteristics Figure 1. On-Region Characteristics 4$ #$ $ , " #$ $ $ # #$ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 592 4 MMDFS6N303 TYPICAL FET ELECTRICAL CHARACTERISTICS , " #$ %!! *. " 8 " # (!! 9 %!! 6 !! # (!! ?$ $ $ # #$ # 4 @ # 8 @ @# 9 " $ 6 , " #$ # 4 @4 6 8 9 # @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 7. Capacitance Variation $ 'CC ' ! 'C '( ' 4 # " , " #$ 6 $ Figure 9. Resistive Switching Time Variation versus Gate Resistance ! " # " #$ 7 4$ ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 M%'2 1 %1 *1()'%D ! )L ! 8 Figure 10. Diode Forward Voltage versus Current - , : 9 " 9 4 #$ # $ $ #$ $ :$ #$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 593 MMDFS6N303 TYPICAL FET ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # 9 W 64 W 964 W 4$: W 64# W , #$4 . 69 . $96 . #7698 . ::6 . = ' ! Figure 13. FET Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform 8$ ?6 , " #$ #$ # 4 6 $ 9 : . . / . . / TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS 8$ , " #$ . . / # #$ 4 6 $ 9 : . > . / Figure 15. Typical Forward Voltage Figure 16. Maximum Forward Voltage http://onsemi.com 594 8 MMDFS6N303 TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS > , " #$ 8$ #$ , " #$ #$ $ $ # #$ 4 $ . / $ # #$ 4 6$ . @ " # 0A 6 @ / 4$ 4 *0& " p #$ # *0& " $ $ *0& " *0& " # $ # 9 6 $ *0& " p #$ @ / *0& " $ *0& " *0& " # $ #$ # Figure 20. Current Derating :$ :$ 8 = Figure 19. Typical Capacitance 4 $ . / / *. $ #$ Figure 18. Maximum Reverse Current # Figure 17. Typical Reverse Current $ # 4 6 . / Figure 21. Forward Power Dissipation http://onsemi.com 595 $ 6 9 MMDFS6N303 TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS '23)'.. " $ # < q, - $ # W , 476## m. #9:6 W #:78: W 4749 W 4974 W 674#9 m. 4 . ##7# . ##9: . $ 6 = 4 # ' ! 5 5 5# Figure 22. Schottky Thermal Response TYPICAL APPLICATIONS STEP DOWN SWITCHING REGULATORS 5 5 % ;' Buck Regulator 5 5 % ;' Synchronous Buck Regulator http://onsemi.com 596 54 MMDFS6N303 TYPICAL APPLICATIONS STEP UP SWITCHING REGULATORS 5 5 % ;' @ Boost Regulator 5 5 % ;' Buck-Boost Regulator MULTIPLE BATTERY CHARGERS Buck Regulator/Charger @ @# # = R 5 % @4 4 = R# http://onsemi.com 597 MMDFS6N303 TYPICAL APPLICATIONS Li-lon BATTERY PACK APPLICATIONS Battery Pack 5 % = SMART IC @ @# - - * Applicable in battery packs which require a high current level. * During charge cycle Q2 is on and Q1 is off. Schottky can reduce power loss during fast charge. * During discharge Q1 is on and Q2 is off. Again, Schottky can reduce power dissipation. * Under normal operation, both transistors are on. http://onsemi.com 598 (" Preferred Device #$%& '( N-Channel SOT-223 This Power MOSFET is designed for high speed, low loss power switching applications such as switching regulators, dc-dc converters, solenoid and relay drivers. The device is housed in the SOT-223 package which is designed for medium power surface mount applications. * Silicon Gate for Fast Switching Speeds * Low Drive Requirement * The SOT-223 Package can be soldered using wave or reflow. The formed leads absorb thermal stress during soldering eliminating the possibility of damage to the die. http://onsemi.com 250 mA 200 VOLTS RDS(on) = 14 N-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit VDSS 200 Volts VGS 20 Volts Drain Current ID 250 mAdc Total Power Dissipation @ TA = 25C (Note 1.) Derate above 25C PD 0.8 Watts 6.4 mW/C Operating and Storage Temperature Range TJ, Tstg -65 to 150 C Rating Drain-to-Source Voltage Gate-to-Source Voltage - Non-Repetitive Maximum Temperature for Soldering Purposes Time in Solder Bath MARKING DIAGRAM 4 1 THERMAL CHARACTERISTICS Thermal Resistance - Junction-to-Ambient RJA 156 TL 260 10 C/W C Sec 2 TO-261AA CASE 318E STYLE 3 FT107 LWW 3 L WW 1. Device mounted on FR-4 glass epoxy printed circuit using minimum recommended footprint. = Location Code = Work Week PIN ASSIGNMENT 4 ()% 1 )'1 2 ()% 3 ;(1 ORDERING INFORMATION Device Package Shipping MMFT107T1 SOT-223 1000 Tape & Reel MMFT107T3 SOT-223 4000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 4 599 Publication Order Number: MMFT107T1/D MMFT107T1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 200 - - Vdc Zero Gate Voltage Drain Current (VDS = 130 V, VGS = 0) IDSS - - 30 nAdc Gate-Body Leakage Current - Reverse (VGS = 15 Vdc, VDS = 0) IGSS - - 10 nAdc Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) VGS(th) 1.0 - 3.0 Vdc Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 200 mA) RDS(on) - - 14 Ohms Drain-to-Source On-Voltage (VGS = 10 V, ID = 200 mA) VDS(on) - - 2.8 Vdc Forward Transconductance (VDS = 25 V, ID = 250 mA) gfs - 300 - mmhos Ciss - 60 - pF Coss - 30 - Crss - 6.0 - VF - 0.8 - V IS - - 250 mA ISM - - 500 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0, ID = 10 A) ON CHARACTERISTICS (Note 2.) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 V V, VGS = 0 0, f = 1.0 MHz) Transfer Capacitance SOURCE DRAIN DIODE CHARACTERISTICS Diode Forward Voltage Continuous Source Current, Body Diode Pulsed Source Current, Body Diode (VGS = 0, IS = 250 mA) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. TYPICAL ELECTRICAL CHARACTERISTICS #$ $ # $ " " , " #$ $ 9 6 4 $ # 6 9 8 6 4 # , " #$ #$ ?$$ Figure 1. On-Region Characteristics # 4 6 Figure 2. Transfer Characteristics http://onsemi.com 600 $ MMFT107T1 < TYPICAL ELECTRICAL CHARACTERISTICS " 8 , " #$ 9 6 #$ # ?$$ # 4 6 $ Figure 3. On-Resistance versus Drain Current " " ?:$ *. , " #$ $ $ %!! $ #$ !! (!! 4 9 7 # $ . / $ $ # #$ 4 Figure 6. Capacitance Variation # " # 7 D. 2! #$ " C " A , " #$ Figure 5. Source-Drain Diode Forward Voltage 8 : " 9 $ 6 9 4 # ?#$ #$ $ :$ , , #$ # ?$ Figure 4. On-Resistance Variation with Temperature $ $ # #$ 4 4$ @D 6 6$ " $ $ $ , " ?$$ #$ #$ Figure 7. Gate Charge versus Gate-to-Source Voltage http://onsemi.com 601 # 4 6 Figure 8. Transconductance $ MMFT107T1 INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. $ 48 :7 # 7 #4 #68 94 7 #4 :7 # $7 $ $7 $ $7 $ %21! SOT-223 POWER DISSIPATION PD = 150C - 25C = 0.8 watts 156C/W The power dissipation of the SOT-223 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-223 package, PD can be calculated as follows: PD = The 156C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 0.8 watts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the collector pad. By increasing the area of the collector pad, the power dissipation can be increased. Although the power dissipation can almost be doubled with this method, area is taken up on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus collector pad area is shown in Figure 9. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 0.8 watts. http://onsemi.com 602 MMFT107T1 TF21( )E 1!%!')1,;'% , ' +%1'U&/ 9 =)( )'1(%)E " 9#$ G&. G6 # A **1( 6 " #$ 8 /)''! # $ /)''! #$ /)''!S 8 S;'1 '21 C'*(%' # 6 9 (1) !J;)(1 %21! 8 Figure 9. Thermal Resistance versus Collector Pad Area for the SOT-223 Package (Typical) Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT-223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass SOLDERING PRECAUTIONS * The soldering temperature and time should not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 603 MMFT107T1 TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 10 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 10. Typical Solder Heating Profile http://onsemi.com 604 ( Preferred Device #$%& '( " N-Channel SOT-223 This Power MOSFET is designed for high speed, low loss power switching applications such as switching regulators, converters, solenoid and relay drivers. The device is housed in the SOT-223 package which is designed for medium power surface mount applications. * Silicon Gate for Fast Switching Speeds * High Voltage - 240 Vdc * Low Drive Requirement * The SOT-223 Package can be soldered using wave or reflow. The formed leads absorb thermal stress during soldering, eliminating the possibility of damage to the die. http://onsemi.com 700 mA 240 VOLTS RDS(on) = 6.0 N-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDS 240 Vdc Gate-to-Source Voltage - Continuous VGS 20 Vdc Drain Current ID 700 mAdc Total Power Dissipation @ TA = 25C (Note 1.) Derate above 25C PD 1.5 Watts 12 mW/C Operating and Storage Temperature Range TJ, Tstg -65 to 150 C Rating MARKING DIAGRAM 4 1 2 TO-261AA CASE 318E STYLE 3 T2406 LWW 3 THERMAL CHARACTERISTICS Thermal Resistance - Junction-to-Ambient (surface mounted) (Note 1.) RJA 83.3 C/W Lead Temperature for Soldering Purposes, 1/16 from case Time in Solder Bath TL 260 C 10 Sec L WW = Location Code = Work Week PIN ASSIGNMENT 4 ()% 1. Device mounted on a glass epoxy printed circuit board 1.575 in. x 1.575 in. x 0.059 in.; mounting pad for the collector lead min. 0.93 sq. in. 1 )'1 2 ()% 3 ;(1 ORDERING INFORMATION Device Package Shipping MMFT2406T1 SOT-223 1000 Tape & Reel MMFT2406T3 SOT-223 4000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 605 Publication Order Number: MMFT2406T1/D MMFT2406T1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristics Symbol Min Max Unit V(BR)DSS 240 - Vdc Zero Gate Voltage Drain Current (VDS = 120 V, VGS = 0) IDSS - 10 Adc Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0) IGSS - 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) VGS(th) 0.8 2.0 Vdc Static Drain-to-Source On-Resistance (VGS = 2.5 Vdc, ID = 0.1 Adc) (VGS = 10 Vdc, ID = 0.5 Adc) RDS(on) - - 10 6.0 Drain-to-Source On-Voltage (VGS = 10 V, ID = 0.5 A) VDS(on) - 3.0 Vdc gFS 300 - mmhos Ciss - 125 pF Coss - 50 Crss - 20 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0, ID = 100 A) ON CHARACTERISTICS (Note 2.) Forward Transconductance (VDS = 6.0 V, ID = 0.5 A) Ohms DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 V V, VGS = 0, 0 f = 1.0 MHz) Transfer Capacitance 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. http://onsemi.com 606 MMFT2406T1 INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. $ 48 :7 # 7 #4 #68 94 7 #4 :7 # $7 $ $7 $ $7 $ %21! SOT-223 POWER DISSIPATION PD = 150C - 25C = 1.5 watts 83.3C/W The power dissipation of the SOT-223 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-223 package, PD can be calculated as follows: PD = The 83.3C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.5 watts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the collector pad. By increasing the area of the collector pad, the power dissipation can be increased. Although the power dissipation can almost be doubled with this method, area is taken up on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus collector pad area is shown in Figure 1. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 1.5 watts. http://onsemi.com 607 TF21( )E 1!%!')1,;'%' +%1'U&/ , MMFT2406T1 9 =)( )'1(%)E " 9#$ G&. G6 # A **1( 6 " #$ 8 /)''! # $ /)''! #$ /)''!S 8 S;'1 '21 C'*(%' # 6 9 (1) !J;)(1 %21! 8 Figure 1. Thermal Resistance versus Collector Pad Area for the SOT-223 Package (Typical) Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT-223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass SOLDERING PRECAUTIONS * The soldering temperature and time should not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 608 MMFT2406T1 TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 2 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 2. Typical Solder Heating Profile http://onsemi.com 609 ( ) Preferred Device #$%& '( P-Channel SOT-223 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient device also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. The device is housed in the SOT-223 package which is designed for medium power surface mount applications. * Silicon Gate for Fast Switching Speeds * The SOT-223 Package can be Soldered Using Wave or Reflow. The Formed Leads Absorb Thermal Stress During Soldering, Eliminating the Possibility of Damage to the Die http://onsemi.com 1 AMPERE 60 VOLTS RDS(on) = 300 m P-Channel MAXIMUM RATINGS (TA = 25C unless otherwise noted) Symbol Value VDS 60 Gate-to-Source Voltage - Continuous VGS 15 Drain Current - Continuous Drain Current - Pulsed ID IDM 1.2 4.8 Adc Total Power Dissipation @ TA = 25C Derate above 25C PD (Note 1.) 0.8 6.4 Watts mW/C Operating and Storage Temperature Range TJ, Tstg -65 to 150 C EAS 108 mJ Rating Drain-to-Source Voltage Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 V, VGS = 10 V, Peak IL= 1.2 A, L = 0.2 mH, RG = 25 ) Unit MARKING DIAGRAM Vdc 4 1 TO-261AA CASE 318E STYLE 3 2 3 2955E L WW = Device Code = Location Code = Work Week PIN ASSIGNMENT THERMAL CHARACTERISTICS Thermal Resistance - Junction-to-Ambient (surface mounted) Maximum Temperature for Soldering Purposes, Time in Solder Bath 2955E LWW 4 ()% RJA 156 C/W 260 C 10 Sec TL 1 1. Power rating when mounted on FR-4 glass epoxy printed circuit board using recommended footprint. )'1 2 ()% 3 ;(1 ORDERING INFORMATION Device Package Shipping MMFT2955ET1 SOT-223 1000 Tape & Reel MMFT2955ET3 SOT-223 1000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 5 610 Publication Order Number: MMFT2955E/D MMFT2955E ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 60 - - Vdc - - - - 1.0 50 - - 100 4.5 Vdc OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage, (VGS = 0, ID = 250 A) Zero Gate Voltage Drain Current, (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current, (VGS = 15 V, VDS = 0) IGSS Adc nAdc ON CHARACTERISTICS Gate Threshold Voltage, (VDS = VGS, ID = 1 mA) VGS(th) 2.0 - Static Drain-to-Source On-Resistance, (VGS = 10 V, ID = 0.6 A) RDS(on) - - 0.3 Ohms Drain-to-Source On-Voltage, (VGS = 10 V, ID = 1.2 A) VDS(on) - - 0.48 Vdc gFS - 7.5 - mhos Forward Transconductance, (VDS = 15 V, ID = 0.6 A) DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 20 V, VGS = 0, f = 1 MH MHz)) Output Capacitance Reverse Transfer Capacitance Ciss - 460 - Coss - 210 - Crss - 84 - td(on) - 18 - pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 V, ID = 1.6 A VGS = 10 V V, RG = 50 ohms, ohms RGS = 25 ohms) Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge (VDS = 48 V, ID = 1.2 A, VGS = 10 Vdc) S Figures See Fi 15 and d 16 tr - 29 - td(off) - 44 - tf - 32 - Qg - 18 - Qgs - 2.8 - Qgd - 7.5 - - 1.0 - ns nC SOURCE DRAIN DIODE CHARACTERISTICS (Note 3.) Forward On-Voltage IS = 1.2 A, VGS = 0 VSD Forward Turn-On Time IS = 1.2 A, VGS = 0, dlS/dt = 400 A/s, A/s VR = 30 V ton Reverse Recovery Time 2. Switching characteristics are independent of operating junction temperature. 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. http://onsemi.com 611 trr Vdc Limited by stray inductance - 90 - ns MMFT2955E TYPICAL ELECTRICAL CHARACTERISTICS # 8 $ 8 , " #$ '2 < : 9 9 6 $ # " 6 # 6 9 8 # " " 7 8 : ?$ 8 " 9 6 #$ # #$ ?$$ ?$$ ?$$ # 6 9 8 9 , " #$ " # 4 # 6 : 4 9 6 #$ 4 ?$$ # # 6 9 8 Figure 4. On-Resistance versus Drain Current $ " $ Figure 3. Transfer Characteristics 6 $ Figure 2. Gate-Threshold Voltage Variation With Temperature Figure 1. On Region Characteristics $ , , 7 $ 6 " " # 4 # ?$ Figure 5. On-Resistance versus Gate-to-Source Voltage $ , , Figure 6. On-Resistance versus Junction Temperature http://onsemi.com 612 $ MMFT2955E FORWARD BIASED SAFE OPERATING AREA The FBSOA curves define the maximum drain-to-source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a ambient temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various ambient temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, "Transient Thermal Resistance-General Data and Its Use" provides detailed instructions. ('.. < #F ! ! $ ! ! SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, BVDSS. The switching SOA is applicable for both turn-on and turn-off of the devices for switching times less than one microsecond. " # " #$ Figure 7. Maximum Rated Forward Biased Safe Operating Area "$ # $ $ *0 # ' '# ,' " (' , , " $9&/ > - . / / ' ,*0 " *0 ,' - - " '&'# 6 4 # ' ! 5 5 Figure 8. Thermal Response COMMUTATING SAFE OPERATING AREA (CSOA) The Commutating Safe Operating Area (CSOA) of Figure 10 defines the limits of safe operation for commutated source-drain current versus re-applied drain voltage when the source-drain diode has undergone forward bias. The curve shows the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to those of Figure 9 are present. Full or half-bridge PWM DC motor controllers are common applications requiring CSOA data. Device stresses increase with increasing rate of change of source current so dIS/dt is specified with a maximum value. Higher values of dIS/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIS/dt is limited primarily by device, package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking. VDS(pk) is the peak drain-to-source voltage that the device must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of commutation. VR is specified at 80% rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. Stray inductances in ON Semiconductor's test circuit are assumed to be practical minimums. dV DS /dt in excess of 10 V/ns was attained with dI S /dt of 400 A/s. http://onsemi.com 613 MMFT2955E $ . E&' 7B '(( B ' #$ 'C(( *0 ! C > Figure 9. Commutating Waveforms 9 &' 6 &! $ 6 4 5 . # # 4 6 $ 9 : % 5 # " 8B . ! " C 5 % E&' 8 Figure 11. Commutating Safe Operating Area Test Circuit Figure 10. Commutating Safe Operating Area (CSOA) = ' ' ' ' Figure 13. Unclamped Inductive Switching Waveforms Figure 12. Unclamped Inductive Switching Test Circuit http://onsemi.com 614 MMFT2955E 8 9 %!! (!! , " #$ C " A *. 6 !! # 8 9 %!! 6 !! (!! # $ ?$ $ $ # Figure 14. Capacitance Variation with Voltage 7 8 : , " #$ " 68 " # 9 $ 6 4 # 4 :$ 4 @D # Figure 15. Gate Charge versus Gate-To-Source Voltage 58F F 6:F0 % $F F. # 476 # 476 F0 F- F F0 6:F0 . = % " $ *0V / ! - - B Figure 16. Gate Charge Test Circuit http://onsemi.com 615 MMFT2955E INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. $ 48 :7 # 7 #4 #68 94 7 #4 :7 # $7 $ $7 $ $7 $ inches mm SOT-223 POWER DISSIPATION The power dissipation of the SOT-223 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-223 package, PD can be calculated as follows: PD = PD = 150C - 25C = 800 milliwatts 156C/W The 156C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 800 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus drain pad area is shown in Figure 17. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 800 milliwatts. http://onsemi.com 616 MMFT2955E TF21( )E 1!%!')1,;'% , ' +%1'U&/ 9 6 =)( )'1(%)E " 9#$ &. 6 # A **1( " #$ 8 /)''! # #$ /)''!S $ /)''! 8 S;'1 '21 C'*(%' # 6 9 (1) !J;)(1 %21! 8 Figure 17. Thermal Resistance versus Drain Pad Area for the SOT-223 Package (Typical) Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT-223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 617 MMFT2955E TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 618 ( Preferred Device #$%& '( N-Channel SOT-223 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This device is also designed with a low threshold voltage so it is fully enhanced with 5 Volts. This new energy efficient device also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, dc-dc converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. The device is housed in the SOT-223 package which is designed for medium power surface mount applications. * Silicon Gate for Fast Switching Speeds * Low Drive Requirement to Interface Power Loads to Logic Level ICs, VGS(th) = 2 Volts Max * The SOT-223 Package can be Soldered Using Wave or Reflow. The Formed Leads Absorb Thermal Stress During Soldering, Eliminating the Possibility of Damage to the Die http://onsemi.com 2 AMPERES 20 VOLTS RDS(on) = 150 m N-Channel MARKING DIAGRAM MAXIMUM RATINGS (TA = 25C unless otherwise noted) Rating Symbol Value VDS 20 Gate-to-Source Voltage - Continuous VGS 15 Drain Current - Continuous Drain Current - Pulsed ID IDM 1.6 6.4 Adc Total Power Dissipation @ TA = 25C Derate above 25C PD (Note 1.) 0.8 6.4 Watts mW/C Operating and Storage Temperature Range TJ, Tstg -65 to 150 C EAS 66 mJ RJA 156 C/W 260 C 10 Sec Drain-to-Source Voltage Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 10 V, VGS = 5 V, Peak IL= 2 A, L = 0.2 mH, RG = 25 ) Unit 4 Vdc 1 2 TO-261AA CASE 318E STYLE 3 2N02L LWW 3 L WW = Location Code = Work Week PIN ASSIGNMENT 4 ()% THERMAL CHARACTERISTICS Thermal Resistance - Junction-to-Ambient (surface mounted) Maximum Temperature for Soldering Purposes, Time in Solder Bath 1 )'1 2 ()% 3 ;(1 TL 1. Power rating when mounted on FR-4 glass epoxy printed circuit board using recommended footprint. ORDERING INFORMATION Device Package MMFT2N02ELT1 SOT-223 Shipping 1000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 4 619 Publication Order Number: MMFT2N02EL/D MMFT2N02EL ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 20 - - Vdc Zero Gate Voltage Drain Current, (VDS = 20 V, VGS = 0) IDSS - - 10 Adc Gate-Body Leakage Current, (VGS = 15 V, VDS = 0) IGSS - - 100 nAdc Gate Threshold Voltage, (VDS = VGS, ID = 1 mA) VGS(th) 1 - 2 Vdc Static Drain-to-Source On-Resistance, (VGS = 5 V, ID = 0.8 A) RDS(on) - - 0.15 Ohms Drain-to-Source On-Voltage, (VGS = 5 V, ID = 1.6 A) VDS(on) - - 0.32 Vdc Forward Transconductance, (VDS = 10 V, ID = 0.8 A) gFS - 2.6 - mhos Ciss - 580 - Coss - 430 - Crss - 250 - td(on) - 16 - tr - 73 - td(off) - 77 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage, (VGS = 0, ID = 250 A) ON CHARACTERISTICS DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance (VDS = 15 V, VGS = 0, f = 1 MH MHz)) pF SWITCHING CHARACTERISTICS Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 V, ID = 1.6 A VGS = 5 V V, RG = 50 ohms, ohms RGS = 25 ohms) Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge (VDS = 16 V, ID = 1.6 A, VGS = 5 Vdc) S Figures See Fi 15 and d 16 tf - 107 - Qg - 20 - Qgs - 1.7 - Qgd - 6 - VSD - 0.9 - ns nC SOURCE DRAIN DIODE CHARACTERISTICS (Note 2.) Forward On-Voltage IS = 1.6 A, VGS = 0 IS = 1.6 A, VGS = 0, dlS/dt = 400 A/s, A/s Reverse Recovery Time VR = 16 V 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2% Forward Turn-On Time http://onsemi.com 620 ton trr Vdc Limited by stray inductance - 55 - ns MMFT2N02EL TYPICAL ELECTRICAL CHARACTERISTICS : 9 $ # , " #$ 6$ 8 6 9 4$ 6 4 # < " #$ # 4 6 " " 7 8 : ?$ $ 8 , " ?$$ #$ 9 " 8 $ 4 " $ #$ 6 # , " $ # #$ ?$$ $ # 6 9 : $ , " #$ " 9 6 4 # # 4 6 $ 9 : # 4 6 Figure 4. On-Resistance versus Drain Current 8 Figure 3. Transfer Characteristics $ , , Figure 2. Gate-Threshold Voltage Variation With Temperature Figure 1. On Region Characteristics $ 6 " $ " 9 4 # ?$ Figure 5. On-Resistance versus Gate-to-Source Voltage $ , , Figure 6. On-Resistance versus Junction Temperature http://onsemi.com 621 $ MMFT2N02EL FORWARD BIASED SAFE OPERATING AREA The FBSOA curves define the maximum drain-to-source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on an ambient temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various ambient temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, "Transient Thermal Resistance-General Data and Its Use" provides detailed instructions. ('.. < #F ! ! ! $F ! SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, BVDSS. The switching SOA is applicable for both turn-on and turn-off of the devices for switching times less than one microsecond. " $ " #$ Figure 7. Maximum Rated Forward Biased Safe Operating Area "$ # $ $ *0 # ' 6 4 ,' " (' , , " $9&/ > - . / / ' ,*0 " *0 ,' '# - - " '&'# # ' ! 5 5 Figure 8. Thermal Response COMMUTATING SAFE OPERATING AREA (CSOA) The Commutating Safe Operating Area (CSOA) of Figure 10 defines the limits of safe operation for commutated source-drain current versus re-applied drain voltage when the source-drain diode has undergone forward bias. The curve shows the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to those of Figure 9 are present. Full or half-bridge PWM DC motor controllers are common applications requiring CSOA data. Device stresses increase with increasing rate of change of source current so dIS/dt is specified with a maximum value. Higher values of dIS/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIS/dt is limited primarily by device, package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking. VDS(pk) is the peak drain-to-source voltage that the device must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of commutation. VR is specified at 80% rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. Stray inductances in ON Semiconductor's test circuit are assumed to be practical minimums. dVDS/dt in excess of 10 V/ns was attained with dI S /dt of 400 A/s. http://onsemi.com 622 MMFT2N02EL $ . E&' 7B B '(( ' #$ 'C(( *0 ! C > Figure 9. Commutating Waveforms 7 8 &' 6 &! : 9 5 $ . 6 5 4 # # # 6 9 8 % " 8B . ! " C 5 % E&' # 6 9 8 # ## #6 #9 #8 4 Figure 10. Commutating Safe Operating Area (CSOA) Figure 11. Commutating Safe Operating Area Test Circuit = ' ' ' Figure 12. Unclamped Inductive Switching Test Circuit ' Figure 13. Unclamped Inductive Switching Waveforms http://onsemi.com 623 MMFT2N02EL 8 %!! 9 (!! !! , " #$ C " A *. 6 # 8 %!! 9 6 !! # (!! $ $ $ $ # # Figure 14. Capacitance Variation With Voltage , " #$ " 9 " 9 7 8 : 9 $ 6 4 # $ $ @D # Figure 15. Gate Charge versus Gate-To-Source Voltage 58F 6:F0 % $F F $F F0 F. # 476 # 476 F0 6:F0 F- . = % " $ *0V / ! - - B Figure 16. Gate Charge Test Circuit http://onsemi.com 624 MMFT2N02EL INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. $ 48 :7 # 7 #4 #68 94 7 #4 :7 # $7 $ $7 $ $7 $ inches mm SOT-223 POWER DISSIPATION The power dissipation of the SOT-223 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-223 package, PD can be calculated as follows: PD = PD = 150C - 25C = 800 milliwatts 156C/W The 156C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 800 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus drain pad area is shown in Figure 17. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 800 milliwatts. http://onsemi.com 625 MMFT2N02EL TF21( )E 1!%!')1,;'% , ' +%1'U&/ 9 6 =)( )'1(%)E " 9#$ &. 6 # A **1( " #$ 8 /)''! # #$ /)''!S $ /)''! 8 S;'1 '21 C'*(%' # 6 9 (1) !J;)(1 %21! 8 Figure 17. Thermal Resistance versus Drain Pad Area for the SOT-223 Package (Typical) Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT-223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 626 MMFT2N02EL TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 627 (! #$%& '( N-Channel SOT-223 These Power MOSFETs are designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 1 AMPERE 60 VOLTS RDS(on) = 130 m N-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 20 25 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 1.7 1.4 6.0 Adc Total PD @ TA = 25C mounted on 1 sq. Drain pad on FR-4 bd material Total PD @ TA = 25C mounted on 0.70 sq. Drain pad on FR-4 bd material Total PD @ TA = 25C mounted on min. Drain pad on FR-4 bd material Derate above 25C PD 2.1 Watts Rating Drain-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 3.4 Apk, L = 10 mH, RG = 25 ) Thermal Resistance - Junction to Ambient on 1 sq. Drain pad on FR-4 bd material - Junction to Ambient on 0.70 sq. Drain pad on FR-4 bd material - Junction to Ambient on min. Drain pad on FR-4 bd material Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 MARKING DIAGRAM Apk 4 1.7 0.94 TJ, Tstg 1 6.3 mW/C -55 to 175 C EAS 2 TO-261AA CASE 318E STYLE 3 TBD LWW 3 L WW = Location Code = Work Week mJ 58 PIN ASSIGNMENT 4 ()% C/W RJA 70 RJA 88 RJA 159 TL 260 1 )'1 C 2 ()% 3 ;(1 ORDERING INFORMATION 628 Device Package Shipping MMFT3055VT1 SOT-223 1000 Tape & Reel MMFT3055VT3 SOT-223 4000 Tape & Reel Publication Order Number: MMFT3055V/D MMFT3055V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 63 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.8 5.6 4.0 - Vdc mV/C - 0.115 0.13 - - - - 0.27 0.25 gFS 1.0 2.7 - mhos Ciss - 360 500 pF Coss - 110 150 Crss - 25 50 td(on) - 8.0 20 tr - 9.0 20 td(off) - 32 60 tf - 18 40 QT - 13 20 Q1 - 2.0 - Q2 - 5.0 - Q3 - 4.0 - - - 0.85 0.7 1.6 - trr - 40 - ta - 34 - tb - 6.0 - QRR - 0.089 - - 4.5 - - 7.5 - OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) (Note 3.) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 0.85 Adc) (Cpk 2.0) (Note 3.) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 1.7 Adc) (VGS = 10 Vdc, ID = 0.85 Adc, TJ = 150C) VGS(th) RDS(on) Ohm VDS(on) Forward Transconductance (VDS = 8.0 Vdc, ID = 1.7 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 30 Vdc, ID = 1.7 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (VDS = 48 Vdc, ID = 1.7 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 1.7 Adc, VGS = 0 Vdc) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 1.7 1 7 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 629 nH nH MMFT3055V TYPICAL ELECTRICAL CHARACTERISTICS " : 9 4$ 4 6 , " #$C $ $$ #$ # 6$ $ 4 #$ # $ $ 4$ # 4 6 $ 9 : 8 C #$C 6 $ 4$ 6 7 , " F$$C # 4 #$ $ #$C : :$ #$ " $ 9$ #$ $ $ 4 # #$ 4$ $ 6 # 8 9 $ Figure 3. On-Resistance versus Drain Current and Temperature $ 4 # #$ 4$ 6 Figure 4. On-Resistance versus Drain Current and Gate Voltage " " 8$ 6 < 9$ 8 $ 9 7$ F$$C :$ $$ 6 , " C #$ $ , " #$C $$ # :$ 6$ : " ##$ 6 Figure 2. Transfer Characteristics Figure 1. On-Region Characteristics #$ 4$ # 8 9 " , " #$C C 6 # F$ F#$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature $ $ # #$ 4 4$ 6 6$ $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 630 $$ 9 MMFT3055V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) , " #$C %!! 7 *. " " 8 : (!! 9 $ %!! 6 4 !! # (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 631 4 7 #: @ 8 #6 : # 9 @ 8 @# $ $ 6 # 4 " : , " #$ # @4 # 6 9 8 # 7 9 4 6 ' ! MMFT3055V " 4 " : " , " #$ 'CC 'C '( ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS # " , " #$ 8 9 6 # 8 9 6 # $ $$ 9 : 9$ :$ 8 8$ 7 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 632 MMFT3055V SAFE OPERATING AREA 9 " # " #$ - , ! ! $ ! ! 6 4 # #$ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature '23)'.. " : $ " $ # $ # $ 6 4 # ' ! 5 5 Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 633 5# 54 MMFT3055V INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. $ 48 :7 # 7 #4 #68 94 7 #4 :7 # $7 $ $7 $ $7 $ inches mm SOT-223 POWER DISSIPATION The power dissipation of the SOT-223 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-223 package, PD can be calculated as follows: PD = PD = 175C - 25C = 943 milliwatts 159C/W The 159C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 943 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus drain pad area is shown in Figure 17. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 943 milliwatts. http://onsemi.com 634 MMFT3055V TF21( )E 1!%!')1,;'% , ' +%1'U&/ 9 6 =)( )'1(%)E " 9#$ &. 6 # A **1( " #$ 8 /)''! # #$ /)''!S $ /)''! 8 S;'1 '21 C'*(%' # 6 9 (1) !J;)(1 %21! 8 Figure 15. Thermal Resistance versus Drain Pad Area for the SOT-223 Package (Typical) Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT-223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 635 MMFT3055V TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 636 (! #$%& '( N-Channel SOT-223 These Power MOSFETs are designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 1 AMPERE 60 VOLTS RDS(on) = 140 m N-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 15 20 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 1.5 1.2 5.0 Adc Total PD @ TA = 25C mounted on 1 sq. Drain pad on FR-4 bd material Total PD @ TA = 25C mounted on 0.70 sq. Drain pad on FR-4 bd material Total PD @ TA = 25C mounted on min. Drain pad on FR-4 bd material Derate above 25C PD 2.1 Watts Rating Drain-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 3.4 Apk, L = 10 mH, RG = 25 ) Thermal Resistance - Junction to Ambient on 1 sq. Drain pad on FR-4 bd material - Junction to Ambient on 0.70 sq. Drain pad on FR-4 bd material - Junction to Ambient on min. Drain pad on FR-4 bd material Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 MARKING DIAGRAM Apk 4 1.7 0.94 TJ, Tstg 1 6.3 mW/C -55 to 175 C EAS 2 TO-261AA CASE 318E STYLE 3 TBD LWW 3 L WW = Location Code = Work Week mJ 58 PIN ASSIGNMENT 4 ()% C/W RJA 70 RJA 88 RJA 159 TL 260 1 )'1 C 2 ()% 3 ;(1 ORDERING INFORMATION 637 Device Package Shipping MMFT3055VLT1 SOT-223 1000 Tape & Reel MMFT3055VLT3 SOT-223 4000 Tape & Reel Publication Order Number: MMFT3055VL/D MMFT3055VL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 65 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 1.0 - 1.5 3.7 2.0 - Vdc mV/C - 0.125 0.14 Ohm - - - - 0.25 0.24 gFS 1.0 3.5 - mhos Ciss - 350 490 pF Coss - 110 150 Crss - 29 60 td(on) - 9.5 20 tr - 18 40 td(off) - 35 70 tf - 22 40 QT - 9.0 10 Q1 - 1.0 - Q2 - 4.0 - Q3 - 3.5 - - - 0.82 0.68 1.2 - trr - 41 - ta - 29 - tb - 12 - QRR - 0.066 - - 4.5 - - 7.5 - OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) (Note 3.) Static Drain-to-Source On-Resistance (VGS = 5.0 Vdc, ID = 0.75 Adc) (Cpk 2.0) (Note 3.) Drain-to-Source On-Voltage (VGS = 5.0 Vdc, ID = 1.5 Adc) (VGS = 5.0 Vdc, ID = 0.75 Adc, TJ = 150C) VGS(th) RDS(on) VDS(on) Forward Transconductance (VDS = 8.0 Vdc, ID = 1.5 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 30 Vdc, ID = 1.5 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (VDS = 48 Vdc, ID = 1.5 Adc, VGS = 5.0 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 1.5 Adc, VGS = 0 Vdc) (IS = 1.5 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 1.5 1 5 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 638 nH nH MMFT3055VL TYPICAL ELECTRICAL CHARACTERISTICS 9 6$ 4$ 4$ 6 , " #$C 4 6 4 #$ # $ #$ $ # 4 6 $ 9 : 8 4 #$ # $ #$C $ # 4$ 7 $ # , " C :$ $ #$C #$ F$$C :$ $ #$ $ $ 4 # #$ 4$ 6 9 4 4$ 6 6$ $ $$ 9 9$ , " #$C ##$ # :$ $ " #$ $ :$ $ #$ $ $ 4 # #$ 4$ 6 Figure 4. On-Resistance versus Drain Current and Gate Voltage " $ " :$ 6 < 8 #$ #$ Figure 3. On-Resistance versus Drain Current and Temperature # # Figure 2. Transfer Characteristics " $ ##$ $ Figure 1. On-Region Characteristics #$ C , " F$$C # 8 9 " , " #$C C 6 # F$ F#$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature 4 6 # $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 639 9 MMFT3055VL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) *. 8 : " " 7 , " #$C %!! 9 (!! $ 6 %!! 4 # !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 640 4 7 #: @ 8 #6 : # 9 8 $ $ 6 @ # @# 4 7 # " $ 9 , " #$ 4 8 7 @4 # 4 6 $ : 9 ' ! MMFT3055VL " 4 " $ " $ , " #$ 'CC 'C '( ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 9 6 " , " #$ # 8 9 6 # 9 9#$ 9$ 9:$ : :#$ :$ ::$ 8 8#$ 8$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 641 MMFT3055VL SAFE OPERATING AREA 9 " $ " #$ - , ! ! $ ! ! 6 4 # #$ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature '23)'.. " $ $ " $ # $ # $ 6 4 # ' ! 5 5 Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 642 5# 54 MMFT3055VL INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. $ 48 :7 # 7 #4 #68 94 7 #4 :7 # $7 $ $7 $ $7 $ inches mm SOT-223 POWER DISSIPATION The power dissipation of the SOT-223 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-223 package, PD can be calculated as follows: PD = PD = 175C - 25C = 943 milliwatts 159C/W The 159C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 943 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus drain pad area is shown in Figure 17. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 943 milliwatts. http://onsemi.com 643 MMFT3055VL TF21( )E 1!%!')1,;'% , ' +%1'U&/ 9 6 =)( )'1(%)E " 9#$ &. 6 # A **1( " #$ 8 /)''! # #$ /)''!S $ /)''! 8 S;'1 '21 C'*(%' # 6 9 (1) !J;)(1 %21! 8 Figure 15. Thermal Resistance versus Drain Pad Area for the SOT-223 Package (Typical) Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT-223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 644 MMFT3055VL TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 645 (#!. Preferred Device #$%& '( ! P-Channel SOT-223 This miniature surface mount MOSFET features ultra low RDS(on) and true logic level performance. It is capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MMFT5P03HD devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SOT-223 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified http://onsemi.com 5 AMPERES 30 VOLTS RDS(on) = 100 m P-Channel MARKING DIAGRAM 4 1 TO-261AA CASE 318E STYLE 3 2 5P03H LWW 3 L WW = Location Code = Work Week PIN ASSIGNMENT 4 ()% 1 )'1 2 ()% 3 ;(1 ORDERING INFORMATION Device Package MMFT5P03HDT3 SOT-223 Shipping 4000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 646 Publication Order Number: MMFT5P03HD/D MMFT5P03HD MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Negative sign for P-Channel devices omitted for clarity Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous 1 SQ. FR-4 or G-10 PCB 10 seconds Minimum FR-4 or G-10 PCB 10 seconds Thermal Resistance - Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current - Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Thermal Resistance - Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current - Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 30 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.5 mH, RG = 25 W) 1. Repetitive rating; pulse width limited by maximum junction temperature. http://onsemi.com 647 Symbol Max Unit VDSS VDGR 30 V 30 V VGS RTHJA PD 20 V 40 3.13 25 5.2 4.1 26 C/W Watts mW/C A A A 80 1.56 12.5 3.7 2.9 19 C/W Watts mW/C A A A - 55 to 150 C ID ID IDM RTHJA PD ID ID IDM TJ, Tstg EAS mJ 250 MMFT5P03HD ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - 28 - - - - - - 1.0 25 - - 100 1.0 - 1.75 3.5 3.0 - - - 79 119 100 150 gFS 2.0 4.0 - Mhos Ciss - 475 950 pF Coss - 220 440 Crss - 70 140 td(on) - 12 24 tr - 24 48 td(off) - 47 94 tf - 46 92 td(on) - 19 38 OFF CHARACTERISTICS (Cpk 2.0) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) (Notes 2. & 4.) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 Vdc) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS(1) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) (Notes 2. & 4.) (Cpk 2.0) (Notes 2. & 4.) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 5.2 Adc) (VGS = 4.5 Vdc, ID = 2.6 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc) (Note 2.) VGS(th) Vdc RDS(on) mV/C m DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 4.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (Note 2.) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 2.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) (Note 2.) Fall Time Gate Charge (VDS = 24 Vdc, ID = 4.0 Adc, VGS = 10 Vdc) (Note 2.) tr - 55 110 td(off) - 30 60 tf - 40 80 QT - 17 24 Q1 - 1.7 - Q2 - 6.3 - Q3 - 4.6 - - - 1.1 0.89 1.5 - trr - 39 - ta - 20 - tb - 19 - QRR - 0.042 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) (IS = 4.0 Adc, VGS = 0 Vdc) (Note 2.) (IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 4.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 2.) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 648 VSD Vdc ns C MMFT5P03HD TYPICAL ELECTRICAL CHARACTERISTICS " 8 9 8 64 6 , " #$ 9 6$ 47 4: 6 4$ 44 4 # 8 9 6 , " # #: 6 8 # 9 #$ 4 4$ 6 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics # # 9 6 8 " 6 , " #$ 4 6$ , " #$ # " 6$ # 6 4 $ : 9 Figure 3. On-Resistance versus Gate-To-Source Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage # " " # $ 8 " , " #$ $ F$ # 4 ?$$ # < #$ #$ F#$ #$ $ :$ #$ $ 9 # 8 #6 , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 649 4 MMFT5P03HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) $ *. # 7 " " , " #$ %!! (!! 9 %!! 4 !! (!! # Figure 7. Capacitance Variation http://onsemi.com 650 4 MMFT5P03HD @ 8 @ 8 " 6 , " #$ @4 6 8 " $ " 6 " , " #$ 9 @# 6 # 9 # ' ! #6 # 'CC 'C '( ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 6 " , " #$ 4 # $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 651 MMFT5P03HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the #$ " # " #$ ! ! - , ! " 4 " " # *0 " 4$ # $ $ #$ $ :$ #$ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 652 $ MMFT5P03HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. &/ " $ # $ # $ 6 4 # ' ! 5 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 653 5# 54 MMFT5P03HD INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. $ 48 :7 # 7 #4 #68 94 7 #4 :7 # $7 $ $7 $ $7 $ inches mm SOT-223 POWER DISSIPATION The power dissipation of the SOT-223 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-223 package, PD can be calculated as follows: PD = PD = 150C - 25C = 3.13 watts 40C/W The 40C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.13 watts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 3.13 watts. http://onsemi.com 654 MMFT5P03HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 655 () Preferred Device #$%& '( ! N-Channel SOT-223 This Power MOSFET is designed for high speed, low loss power switching applications such as switching regulators, dc-dc converters, solenoid and relay drivers. The device is housed in the SOT-223 package which is designed for medium power surface mount applications. * Silicon Gate for Fast Switching Speeds * Low Drive Requirement * The SOT-223 Package can be soldered using wave or reflow. The formed leads absorb thermal stress during soldering eliminating the possibility of damage to the die. http://onsemi.com 300 mA 60 VOLTS RDS(on) = 1.7 N-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDS 60 Volts Gate-to-Source Voltage - Non-Repetitive VGS 30 Volts Drain Current ID 300 mAdc Total Power Dissipation @ TA = 25C (Note 1.) Derate above 25C PD 0.8 Watts 6.4 mW/C Operating and Storage Temperature Range TJ, Tstg -65 to 150 C Rating Maximum Temperature for Soldering Purposes Time in Solder Bath MARKING DIAGRAM 4 1 THERMAL CHARACTERISTICS Thermal Resistance - Junction-to-Ambient RJA 156 C/W TL 260 C 10 Sec TO-261AA CASE 318E STYLE 3 2 FT960 LWW 3 FT960 L WW 1. Device mounted on a FR-4 glass epoxy printed circuit board using minimum recommended footprint. = Device Code = Location Code = Work Week PIN ASSIGNMENT 4 ()% 1 )'1 2 ()% 3 ;(1 ORDERING INFORMATION Device MMFT960T1 Package SOT-223 Shipping 1000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 4 656 Publication Order Number: MMFT960T1/D MMFT960T1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 60 - - Vdc Zero Gate Voltage Drain Current (VDS = 60 V, VGS = 0) IDSS - - 10 Adc Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0) IGSS - - 50 nAdc Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) VGS(th) 1.0 - 3.5 Vdc Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 1.0 A) RDS(on) - - 1.7 Ohms Drain-to-Source On-Voltage (VGS = 10 V, ID = 0.5 A) (VGS = 10 V, ID = 1.0 A) VDS(on) - - - - 0.8 1.7 gfs - 600 - mmhos Ciss - 65 - pF Coss - 33 - Crss - 7.0 - Qg - 3.2 - Qgs - 1.2 - Qgd - 2.0 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0, ID = 10 A) ON CHARACTERISTICS (Note 2.) Forward Transconductance (VDS = 25 V, ID = 0.5 A) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 V V, VGS = 0 0, f = 1.0 MHz) Output Capacitance Transfer Capacitance Total Gate Charge (VGS = 10 V V, ID = 1.0 1 0 A, A VDS = 48 V) Gate-Source Charge Gate-Drain Charge nC 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. TYPICAL ELECTRICAL CHARACTERISTICS $ 6 , " #$ " 8 4 : # 9 $ , " ?$$ 8 , " #$ , " #$ 9 6 " # 6 # 6 9 8 Figure 1. On-Region Characteristics # 6 9 8 Figure 2. Transfer Characteristics TYPICAL ELECTRICAL CHARACTERISTICS http://onsemi.com 657 < MMFT960T1 $ " 6 4 , " #$ # #$ ?$$ $ $ # #$ Figure 3. On-Resistance versus Drain Current " " ?:$ ?$ ?#$ #$ $ :$ , , #$ $ Figure 4. On-Resistance Variation with Temperature #$ " C " A , " #$ # *. ##$ , " #$ , " #$ :$ $ #$ %!! :$ !! $ (!! #$ 4 9 7 # $ . / 4 # 7 " , " #$ 8 : 9 " 4 " 68 $ 6 4 # $ # #$ Figure 6. Capacitance Variation D. 2! Figure 5. Source-Drain Diode Forward Voltage $ $ $ # #$ 4 @D 4$ " $ #$ $ 6 , " ?$$ #$ Figure 7. Gate Charge versus Gate-to-Source Voltage http://onsemi.com 658 $ $ Figure 8. Transconductance # #$ MMFT960T1 INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. $ 48 :7 # 7 #4 #68 94 7 #4 :7 # $7 $ $7 $ $7 $ %21! SOT-223 POWER DISSIPATION PD = 150C - 25C = 0.8 watts 156C/W The power dissipation of the SOT-223 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-223 package, PD can be calculated as follows: PD = The 156C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 0.8 watts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the collector pad. By increasing the area of the collector pad, the power dissipation can be increased. Although the power dissipation can almost be doubled with this method, area is taken up on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus collector pad area is shown in Figure 9. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 0.8 watts. http://onsemi.com 659 MMFT960T1 TF21( )E 1!%!')1,;'% , ' +%1'U&/ 9 =)( )'1(%)E " 9#$ G&. G6 # A **1( 6 " #$ 8 /)''! # $ /)''! #$ /)''!S 8 S;'1 '21 C'*(%' # 6 9 (1) !J;)(1 %21! 8 Figure 9. Thermal Resistance versus Collector Pad Area for the SOT-223 Package (Typical) Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT-223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass SOLDERING PRECAUTIONS * The soldering temperature and time should not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 660 MMFT960T1 TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 10 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 10. Typical Solder Heating Profile http://onsemi.com 661 ( 8 Preferred Device #$%& '( N-Channel SO-8 EZFETst are an advanced series of Power MOSFETs which contain monolithic back-to-back zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. * Zener Protected Gates Provide Electrostatic Discharge Protection * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Mounting Information for SO-8 Package Provided http://onsemi.com 10 AMPERES 20 VOLTS RDS(on) = 15 m N-Channel MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 70C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Symbol Value Unit VDSS VDGR VGS 20 Vdc 20 Vdc 12 Vdc ID ID IDM PD 10 7.0 80 Adc 2.5 Watts Apk Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C Thermal Resistance - Junction to Ambient RJA 50 C/W Maximum Temperature for Soldering TL 260 C 1. When mounted on 1 square FR-4 or G-10 board (VGS = 4.5 V, @ 10 Seconds) MARKING DIAGRAM SO-8 CASE 751 STYLE 12 8 10N02Z LYWW 1 L Y WW = Location Code = Year = Work Week PIN ASSIGNMENT Source 1 8 Drain Source 2 7 Drain Source 3 6 Drain Gate 4 5 Drain Top View ORDERING INFORMATION Device Package MMSF10N02ZR2 SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 662 Publication Order Number: MMSF10N02Z/D MMSF10N02Z ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 20 - - 17 - - - - - - 10 100 - 0.6 1.5 0.5 - 0.72 2.86 1.1 - - - 13 16 15 19 gFS 11 14 - Mhos Ciss - 1150 1225 pF Coss - 775 810 Crss - 375 480 td(on) - 65 75 tr - 360 440 td(off) - 325 640 tf - 575 860 QT - 26 32 Q1 - 2.5 - Q2 - 13 - Q3 - 9.0 - - - 0.83 0.68 1.2 - trr - 765 - ta - 240 - tb - 530 - QRR - 8.7 - OFF CHARACTERISTICS (Cpk 2.0) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) (Note 4.) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc Adc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) (Note 4.) (Cpk 2.0) (Note 4.) Static Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 10 Adc) (VGS = 2.7 Vdc, ID = 5.0 Adc) Forward Transconductance (VDS = 9.0 Vdc, ID = 5.0 Adc) VGS(th) Vdc RDS(on) mV/C m DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 5.0 Adc, VGS = 4.0 Vdc, RG = 10 ) Fall Time Gate Charge (VDS = 16 Vdc, ID = 10 Adc, VGS = 4.0 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 10 Adc, VGS = 0 Vdc) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 10 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 663 VSD Vdc ns C MMSF10N02Z TYPICAL ELECTRICAL CHARACTERISTICS " # 6$ 9 7 6 8 # : 8 9 9 $ 6 , " #$ 6 # 9 8 # 9 6 # 8 9 6 #$ 8 # $ $ 6 4 6 $ 9 : 8 7 # # #$ 4 , " #$ #$ # " #: $ 6$ $ 4 $ 7 : 4 $ Figure 3. On-Resistance versus Gate-to-Source Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage "6$ " $ , " #$ " # 8 9 6 #$ # ?$ $ Figure 2. Transfer Characteristics # 9 Figure 1. On-Region Characteristics " , " #$ # $ 4 , " $$ #$ < , " #$ # # 6 #: 8 # ?#$ #$ $ :$ #$ $ #$ $ :$ #$ $ :$ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 664 # MMSF10N02Z POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) *. # , " #$C " $ %!! !! (!! $ # 6 9 8 # 6 9 Figure 7. Capacitance Variation http://onsemi.com 665 8 # 9 6 # 9 @ 6 @ @# 8 9 # " , " #$ @4 $ $ # 6 # #$ ' ! 8 MMSF10N02Z " " $ " 6 , " #$ 'C '( 'CC ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # " , " #$ 8 9 6 # # 4 6 $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 666 MMSF10N02Z %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA the total power averaged over a complete switching cycle must not exceed (T J(MAX) - T C )/(RJC ). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (T C ) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (I DM ) nor rated voltage (V DSS ) is exceeded, and that the transition time (t r, tf ) does not exceed 10 s. In addition " " #$ ! ! Figure 12. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 667 MMSF10N02Z TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # $ 6 4 # ' ! 5 5 Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 668 5# 54 MMSF10N02Z INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 6 6 #8 $#8 #9 4# $ 48 #$9 9$ inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.5 Watts 50C/W The 50C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 669 MMSF10N02Z TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 15. Typical Solder Heating Profile http://onsemi.com 670 (!8 Preferred Device #$%& '( ! N-Channel SO-8 EZFETst are an advanced series of Power MOSFETs contain monolithic back-to-back zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. * Zener Protected Gates Provide Electrostatic Discharge Protection * Designed to Withstand 200 V Machine Model and 2000 V Human Body Model * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Mounting Information for SO-8 Package Provided http://onsemi.com 10 AMPERES 30 VOLTS RDS(on) = 13 mW N-Channel MARKING DIAGRAM SO-8 CASE 751 STYLE 12 8 10N03Z LYWW 1 L Y WW = Location Code = Year = Work Week PIN ASSIGNMENT Source 1 8 Drain Source 2 7 Drain Source 3 6 Drain Gate 4 5 Drain Top View ORDERING INFORMATION This document contains information on a new product. Specifications and information herein are subject to change without notice. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 671 Device Package MMSF10N03ZR2 SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MMSF10N03Z/D MMSF10N03Z MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Parameter Symbol Max Unit VDSS VDGR VGS 30 Vdc 30 Vdc 20 Vdc 10 7.7 50 Adc 2.5 20 Watts mW/C PD 1.6 12 Watts mW/C TJ, Tstg - 55 to 150 C Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C (Note 1.) Drain Current - Continuous @ TA = 70C (Note 1.) Drain Current - Pulsed Drain Current (Note 3.) ID ID IDM PD Total Power Dissipation @ TA = 25C (Note 1.) Linear Derating Factor @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Linear Derating Factor @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 30 Vdc, VGS = 10 Vdc, IL = 10 Apk, L = 20 mH, RG = 25 W) EAS mJ 1000 THERMAL RESISTANCE Parameter Junction-to-Ambient (Note 1.) Junction-to-Ambient (Note 2.) Symbol Typ Max Unit RqJA - - 50 80 C/W 1. When mounted on 1 square FR4 or G-10 board (VGS = 10 V, @ 10 seconds). 2. When mounted on minimum recommended FR4 or G-10 board (VGS = 10 V, @ Steady State). 3. Repetitive rating; pulse width limited by maximum junction temperature. http://onsemi.com 672 MMSF10N03Z ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - 65 - - - - - - 1.0 10 - - 3.0 1.0 - 1.2 3.5 1.7 - - - 10 13 13 18 gFS 7.0 13 - Mhos Ciss - 720 1010 pF Coss - 570 800 Crss - 78 110 td(on) - 35 70 tr - 105 210 td(off) - 970 1940 tf - 550 1100 QT - 46 64 Q1 - 3.8 - Q2 - 11 - Q3 - 8.1 - - - 0.80 0.70 1.1 - trr - 460 - ta - 180 - tb - 280 - QRR - 4.2 - OFF CHARACTERISTICS (Cpk 2.0) (Notes 4. & 6.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc Adc ON CHARACTERISTICS(1) Gate Threshold Voltage (Cpk 2.0) (Notes 4. & 6.) (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) (Cpk 2.0) (Notes 4. & 6.) RDS(on) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc) (Note 4.) Vdc mV/C m DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (Note 4.) Fall Time Gate Charge S Fi See Figure 8 (VDS = 15 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (Note 4.) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 10 Adc, VGS = 0 Vdc) (Note 4.) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 2.3 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 4.) Reverse Recovery Stored Charge 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperatures. 6. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 673 VSD Vdc ns C MMSF10N03Z TYPICAL ELECTRICAL CHARACTERISTICS # 4 , " #$ # " #: 9 #$ 8 #4 6 6$ $ $ $ #$ , " $ # $ # #$ Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics " , " #$ 6 4 # # 6 9 8 4 # , " #$ $ 6$ " $ Figure 3. On-Resistance versus Drain Current $ $ # Figure 4. On-Resistance versus Drain Current and Gate Voltage # " " $ < $ $ $ 9 $$ # 7 # $ " , " #$ #$ ?$ ?#$ #$ $ :$ #$ $ , , 8 6 9 # Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 674 # MMSF10N03Z POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) $ *. 6 " " , " #$ %!! 4 # (!! %!! !! (!! $ $ $ Figure 7. Capacitance Variation http://onsemi.com 675 # @ $ 8 # 9 7 @ @# , " #$ " # # $ $ # #$ 4 4$ 6 6$ $ 'CC 'C '( ' 4 @4 " " #$ " , " #$ 9 6 ' ! 8 # MMSF10N03Z @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 7 , " #$ " 8 : 9 $ 6 4 # 6 $ 9 : 8 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 676 MMSF10N03Z %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. m ! ! " " #$ - , The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the " 4 " " *0 " # 8 9 6 # #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 677 MMSF10N03Z TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # *0 ' $ '# - - " '&'# 6 4 # ' ! 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 678 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5# 54 MMSF10N03Z INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 1.6 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 1.6 Watts 80C/W The 80C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.6 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 679 MMSF10N03Z TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 680 (!, Preferred Device #$%& '( " ! N-Channel SO-8 These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * High Speed Switching Provides High Efficiency for DC/DC Converter * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Exhibits High Speed, With Soft Recovery http://onsemi.com 7 AMPERES 30 VOLTS RDS(on) = 30 mW N-Channel MARKING DIAGRAM MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Parameter Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Continuous Drain Current @ TA = 25C (Note 1.) Pulsed Drain Current (Note 2.) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Symbol Max Unit VDSS VDGR 30 Vdc 30 Vdc VGS ID 20 Vdc 7.0 Adc IDM PD 50 TJ, Tstg SO-8 CASE 751 STYLE 12 8 S1308 LYWW 1 2.5 W - 55 to 150 C L Y WW = Location Code = Year = Work Week PIN ASSIGNMENT THERMAL RESISTANCE Junction-to-Ambient (Note 1.) RJA 50 C/W 1. When mounted on 1 square FR-4 or G-10 board (VGS = 10 V, @ 10 Seconds) 2. Repetitive rating; pulse width limited by maximum junction temperature. Source 1 8 Drain Source 2 7 Drain Source 3 6 Drain Gate 4 5 Drain Top View ORDERING INFORMATION Device MMSF1308R2 Package SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 681 Publication Order Number: MMSF1308/D MMSF1308 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - 30 - - - - - - 1.0 10 - - 100 1.0 - 1.6 4.3 2.5 - - - 22 30 30 39 gFS - 4.5 - Mhos Ciss - 690 970 pF Coss - 290 410 Crss - 90 130 td(on) - 7.5 15 tr - 24 48 td(off) - 30 60 tf - 46 92 QT - 20 30 Q1 - 2.5 - Q2 - 6.0 - Q3 - 8.0 - - - 0.85 0.71 1.0 - trr - 35 - ta - 20 - tb - 15 - QRR - 0.03 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 7.0 Adc) (VGS = 4.5 Vdc, ID = 3.5 Adc) RDS(on) Forward Transconductance (VDS = 5.0 Vdc, ID = 1.0 Adc) (Note 3.) Vdc mV/C m DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 24 Vd Vdc, VGS = 0 V V, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 21 Vdc, ID = 7.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (Note 3.) Fall Time Gate Charge (VDS = 15 Vdc, ID = 7.0 Adc, VGS = 10 Vdc) (Note 3.) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 7.0 Adc, VGS = 0 Vdc) (Note 3.) (IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 7.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 3.) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. 5. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA 6. Repetitive rating; pulse width limited by maximum junction temperature. http://onsemi.com 682 VSD Vdc ns C MMSF1308 TYPICAL ELECTRICAL CHARACTERISTICS $ 4$ 4 6$ 8 , " #$ 9 #7 6 #: # " #4 # 6 9 8 # 6 9 8 # 7 9 #$ 4 # , " #$ $$ " : , " #$ 4 # # 9 6 8 $ $ 6 $ , " #$ 6 " 6$ 4 # Figure 3. On-Resistance versus Drain Current Figure 4. On-Resistance versus Drain Current and Gate Voltage : $ $ #$ $ :$ #$ $ 6 , " #$ 8 $ # 4 " " : ?#$ 4 # ?$ # Figure 2. Transfer Characteristics < W Figure 1. On-Region Characteristics 6 7 #$ " , , # #$ $ $ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 683 4 MMSF1308 POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) # " 8 *. 9 " , " #$ %!! 6 # (!! %!! 8 9 !! 6 # (!! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 684 #$ 4 MMSF1308 , " #$ " : " #6 " ' ! 'C 'CC '( ' Figure 8. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 10. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by " , " #$ 8 9 6 # # 6 9 8 Figure 9. Diode Forward Voltage versus Current http://onsemi.com 685 MMSF1308 %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 10. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the " " #$ m! ! ! Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 686 MMSF1308 INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.5 Watts 50C/W The 50C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 687 MMSF1308 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 12. Typical Solder Heating Profile http://onsemi.com 688 (! Preferred Device #$%& '( ! N-Channel SO-8 These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Low RDS(on) Provides Higher Efficiency and Extends Battery Life * High Speed Switching Provides High Efficiency for DC/DC Converter * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Exhibits High Speed, With Soft Recovery http://onsemi.com 10 AMPERES 30 VOLTS RDS(on) = 15 mW N-Channel MARKING DIAGRAM MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Parameter Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Continuous Drain Current @ TA = 25C (Note 1.) Pulsed Drain Current (Note 2.) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Symbol Max Unit VDSS VDGR 30 Vdc 30 Vdc VGS ID 20 Vdc 10 Adc IDM PD 50 TJ, Tstg SO-8 CASE 751 STYLE 12 8 S1310 LYWW 1 2.5 W - 55 to 150 C L Y WW = Location Code = Year = Work Week PIN ASSIGNMENT THERMAL RESISTANCE Junction-to-Ambient (Note 1.) RJA 50 C/W 1. When mounted on 1 square FR-4 or G-10 board (VGS = 10 V, @ 10 Seconds) 2. Repetitive rating; pulse width limited by maximum junction temperature. Source 1 8 Drain Source 2 7 Drain Source 3 6 Drain Gate 4 5 Drain Top View ORDERING INFORMATION Device MMSF1310R2 Package SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 689 Publication Order Number: MMSF1310/D MMSF1310 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - 27 - - - - - - 1.0 10 - - 100 1.0 - 1.3 4.4 2.5 - - - 9.5 12.5 15 19 gFS - 5.0 - Mhos Ciss - 1440 2020 pF Coss - 680 960 Crss - 195 280 td(on) - 10 20 tr - 36 72 td(off) - 82 164 tf - 95 190 QT - 48 68 Q1 - 3.0 - Q2 - 4.0 - Q3 - 7.0 - - - 0.82 0.67 1.0 - trr - 52 - ta - 23 - tb - 30 - QRR - 0.05 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) RDS(on) Forward Transconductance (VDS = 5.0 Vdc, ID = 1.0 Adc) (Note 3.) Vdc mV/C m DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 24 Vd Vdc, VGS = 0 V V, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 24 Vdc, ID = 10 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (Note 3.) Fall Time Gate Charge (VDS = 15 Vdc, ID = 10 Adc, VGS = 10 Vdc) (Note 3.) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 10 Adc, VGS = 0 Vdc) (Note 3.) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 10 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 3.) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. 5. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA 6. Repetitive rating; pulse width limited by maximum junction temperature. http://onsemi.com 690 VSD Vdc ns C MMSF1310 TYPICAL ELECTRICAL CHARACTERISTICS 4 9 # #7 , " #$ # 4$ 6$ #: # 8 " #4 6 # 6 9 8 # 6 9 8 9 # #$ $$ 6 # , " #$ 8 # # 9 6 8 " , " #$ 4 4 $ 6 # , " #$ $ " 6$ $ # 4 Figure 3. On-Resistance versus Drain Current Figure 4. On-Resistance versus Drain Current and Gate Voltage 9 " " $ 6 , " #$ : $ $ # ?$ # Figure 2. Transfer Characteristics $ < W Figure 1. On-Region Characteristics 6 8 7 #$ " ?#$ #$ $ :$ #$ $ , , # #$ $ $ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 691 4 MMSF1310 POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) *. 6 " 4 " , " #$ !! %!! (!! # (!! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 692 #$ 4 MMSF1310 , " #$ " " #6 " ' ! 'C 'CC '( ' Figure 8. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 10. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by " , " #$ 8 9 6 # # 6 9 8 Figure 9. Diode Forward Voltage versus Current http://onsemi.com 693 MMSF1310 %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 10. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the m! ! ! " " #$ Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 694 MMSF1310 INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.5 Watts 50C/W The 50C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 695 MMSF1310 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 12. Typical Solder Heating Profile http://onsemi.com 696 ( # Preferred Device #$%& '( P-Channel SO-8 These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed * Avalanche Energy Specified * Mounting Information for SO-8 Package Provided * IDSS Specified at Elevated Temperature http://onsemi.com 2 AMPERES 20 VOLTS RDS(on) = 250 m P-Channel MARKING DIAGRAM SO-8 CASE 751 STYLE 13 8 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.) Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C (Note 2.) - Continuous @ TA = 100C - Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, IL = 6.0 Apk, L = 12 mH, RG = 25 ) Thermal Resistance - Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol Value Unit VDSS VGS 20 Vdc 20 Vdc 2.5 1.7 13 Adc 2.5 Watts ID ID IDM PD TJ, Tstg EAS C 216 mJ November, 2000 - Rev. 5 L Y WW = Location Code = Year = Work Week PIN ASSIGNMENT N-C 1 8 Drain Source 2 7 Drain Source 3 6 Drain Gate 4 5 Drain Top View RJA 50 C/W TL 260 C 1. Negative sign for P-Channel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max. Semiconductor Components Industries, LLC, 2000 1 Apk - 55 to 150 S4P01 LYWW 697 ORDERING INFORMATION Device Package MMSF2P02ER2 SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MMSF2P02E/D MMSF2P02E ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.) Characteristic Symbol Min Typ Max Unit 20 - - 24.7 - - - - - - 1.0 10 - - 100 1.0 2.0 4.7 3.0 - - - 0.19 0.3 0.25 0.4 gFS 1.0 2.8 - Mhos Ciss - 340 475 pF Coss - 220 300 Crss - 75 150 td(on) - 20 40 tr - 40 80 td(off) - 53 106 tf - 41 82 td(on) - 13 26 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 2.0 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) RDS(on) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) Vdc mV/C Ohm DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) Fall Time Gate Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) ns ns tr - 29 58 td(off) - 30 60 tf - 28 56 QT - 10 15 Q1 - 1.1 - Q2 - 3.3 - Q3 - 2.5 - VSD - 1.5 2.0 Vdc trr - 34 64 ns ta - 18 - tb - 16 - QRR - 0.035 - nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 4.) (IS = 2.0 Adc, VGS = 0 Vdc) Reverse Recovery Time (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 3. Negative sign for P-Channel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. http://onsemi.com 698 C MMSF2P02E TYPICAL ELECTRICAL CHARACTERISTICS 6 , " #$ 6$ 64 # 6 47 4: 4$ 44 6 8 # 9 #$ , " $$ 4 4$ 6 6$ Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics $ 6 4 # # # " , " #$ 4 4 9 #$ # 6 : 9 $ 8 7 9 , " #$ $ 6 " 6$ 4 # $ $ # Figure 3. On-Resistance versus Gate-to-Source Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage " " # " $ 6: 4 < $ " : 6 $ ?$ ?#$ #$ $ :$ #$ , " #$ $ 6 8 # 9 , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 699 # MMSF2P02E POWER MOSFET SWITCHING During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. " , " #$C %!! 8 *. " # 9 @ 7 9 9 (!! 6 %!! !! # (!! $ $ 4 $ # #$ 6 @4 8 @# @ 4 # " # , " #$ # 6 9 8 @D Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge Figure 7. Capacitance Variation http://onsemi.com 700 t = Q/IG(AV) # MMSF2P02E # " " # " , " #$ 9 , " #$ " ' ! # 'CC '( 8 'C ' 6 9 Figure 9. Resistive Switching Time Variation versus Gate Resistance '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') 9 Figure 10. Diode Forward Voltage versus Current %&' " 4 &! 8 # 6 ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 ! )L ! ' " # " #$ ! Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 11. Reverse Recovery Time (trr) http://onsemi.com 701 MMSF2P02E - , #$ " 9 # $ $ #$ $ :$ $ #$ , , Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry '23)'.. " $ # $ # 2%* $ 6 4 # ## # #$8: # . #: . 4$: . ' ! 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 702 :#4 464 . 5 9894 866 . 5# +%1' 54 MMSF2P02E INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C 50C/W = 2.5 Watts The 50C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 703 MMSF2P02E TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 13 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 704 (!! #$%& '( - ! N-Channel SO-8 These Power MOSFETs are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. WaveFETt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. http://onsemi.com 11.5 AMPERES 30 VOLTS RDS(on) = 12.5 mW N-Channel * Characterized Over a Wide Range of Power Ratings * Ultralow RDS(on) Provides Higher Efficiency and Extends Battery * * * * * * Life in Portable Applications Logic Level Gate Drive - Can Be Driven by Logic ICs Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Miniature SO-8 Surface Mount Package - Saves Board Space MARKING DIAGRAM SO-8 CASE 751 STYLE 12 8 MAXIMUM RATINGS (TJ = 25C unless otherwise specified) Parameter Drain-to-Source Voltage Drain-to-Gate Voltage Gate-to-Source Voltage Gate-to-Source Operating Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, L = 18.8 mH, IL(pk) = 7.3 A, VDS = 30 Vdc) Symbol Value Unit VDSS VDGR 30 Vdc 30 Vdc VGS VGS 20 Vdc 16 Vdc TJ, Tstg -55 to 150 C EAS 500 mJ S3300 LYWW 1 L Y WW = Location Code = Year = Work Week PIN ASSIGNMENT Source 1 8 Drain Source 2 7 Drain Source 3 6 Drain Gate 4 5 Drain Top View ORDERING INFORMATION Device MMSF3300R2 Package SO-8 Shipping 2500 Tape & Reel This document contains information on a new product. Specifications and information herein are subject to change without notice. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 5 705 Publication Order Number: MMSF3300/D MMSF3300 POWER RATINGS (TJ = 25C unless otherwise specified) Parameter Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 ms) Mounted on 1 inch square FR-4 or G10 board Total Power Dissipation @ TA = 25C Linear Derating Factor VGS = 10 Vdc Thermal Resistance t 10 seconds - Junction-to-Ambient Continuous Source Current (Diode Conduction) Parameter Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 ms) Mounted on 1 inch square FR-4 or G10 board Total Power Dissipation @ TA = 25C Linear Derating Factor Thermal Resistance VGS = 10 Vdc - Junction-to-Ambient Steady State Continuous Source Current (Diode Conduction) Parameter Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 ms) Mounted on minimum recommended FR-4 or G10 board Total Power Dissipation @ TA = 25C Linear Derating Factor VGS = 10 Vdc Thermal Resistance t 10 seconds - Junction-to-Ambient Continuous Source Current (Diode Conduction) Parameter Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 ms) Mounted on minimum recommended FR-4 or G10 board Total Power Dissipation @ TA = 25C Linear Derating Factor Thermal Resistance VGS = 10 Vdc - Junction-to-Ambient Steady State Continuous Source Current (Diode Conduction) http://onsemi.com 706 Symbol Value Unit ID ID IDM PD 11.5 8.2 50 Adc Adc Adc 2.5 20 Watts mW/C RJA 50 C/W IS 3.0 Adc Symbol Value Unit ID ID IDM PD 9.1 6.5 50 Adc Adc Adc 1.6 12.5 Watts mW/C RJA 80 C/W IS 2.0 Adc Symbol Value Unit ID ID IDM PD 9.1 6.5 50 Adc Adc Adc 1.6 12.5 Watts mW/C RJA 80 C/W IS 2.0 Adc Symbol Value Unit ID ID IDM PD 6.7 4.7 50 Adc Adc Adc 0.8 6.7 Watts mW/C RJA 150 C/W IS 1.0 Adc MMSF3300 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise specified) Characteristic Symbol Min Typ Max Unit 30 - - 24 - - - - 0.004 0.5 1.0 10 - - 100 1.0 - 1.9 4.4 - - - - 10 16 12.5 20 gFS 3.0 18 - Mhos Ciss - 1700 - pF Coss - 600 - Crss - 200 - td(on) - 21 40 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) RDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) Vdc mV/C m DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) Fall Time Gate Charge (VDS = 15 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) tr - 45 90 td(off) - 40 80 tf - 40 80 td(on) - 12 25 tr - 12 25 td(off) - 55 110 tf - 39 80 QT - 45 60 Q1 - 5.1 - Q2 - 14 - Q3 - 13 - - - 0.78 0.60 1.1 - trr - 40 - ta - 21 - tb - 19 - QRR - 0.043 - ns ns nC SOURCE-DRAIN DIODE CHARACTERISTICS VSD Forward On-Voltage (Note 1.) (IS = 2.3 Adc, VGS = 0 Vdc) (IS = 2.3 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 3.5 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 707 Vdc ns C MMSF3300 TYPICAL ELECTRICAL CHARACTERISTICS 7 : 4$ $ 4 6 #7 4 # " #: #$ $ :$ #$ $ :$ 7 , " #$ 9 6$ 6 4: 8 9 44 8 9 , " #$ $ 6 $$ 4 # # #$ : # #$ 4 " $ , " #$ # $ $ # 4 6 $ 9 : 8 7 # , " #$ 8 9 # 8 9 6 # < $ #$ $ :$ 6 " " " ?#$ # # 9 8 6 9 Figure 4. On-Resistance versus Drain Current and Gate Voltage # ?$ " 6$ 6 Figure 3. On-Resistance versus Gate-To-Source Voltage $ 6 4$ Figure 2. Transfer Characteristics Figure 1. On-Region Characteristics #$ 4 #$ $ , " #$ #$ $ , , Figure 5. On-Resistance Variation with Temperature # #$ $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 708 4 MMSF3300 POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) " " 6 *. 4$ , " #$ %!! 4 #$ (!! # %!! $ !! $ (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 709 4 MMSF3300 8 @ " #$ " " , " #$ $ # 9 7 @ 6 # @# 9 " # , " #$ 4 @4 4 # @ $ 6 ' ! 8 # 'CC 'C '( ' Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 16. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high 8 : " , " #$ 9 $ 6 4 # $ $$ 9 9$ : :$ 8 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 710 MMSF3300 %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the $ ! - , m! ! " " #$ " :4 6 4 # #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 711 MMSF3300 TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. - - . " $ # $ # *0 ' '# - - " '&'# $ 6 4 # ' !1! 5 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5# 54 Figure 14. Thermal Response - Various Duty Cycles # 4 6 $ 3) 3) #6# :4 :$ 6# 7$$ 86 $9 #6# 9# #4 69 78# :6 :9 #8 8$ 478 9$4 6969 3E 9 9 : $: # 96 $8 $4 9#$9 #: , # 4 # 4 6 $ 6 $ '23) '23E = '23) 4 # 5 ' !1! 5 5# 5 Figure 15. Thermal Response - Various Mounting/Measurement Conditions 8 9 %&' '(( ') '+ / / '23)'.. #$ '* 6 # ' !1! Figure 16. Diode Reverse Recovery Waveform Figure 17. Single Pulse Power http://onsemi.com 712 MMSF3300 INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.5 Watts 50C/W The 50C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. *Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 713 MMSF3300 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 714 (!# . Preferred Device #$%& '( ! P-Channel SO-8 These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Mounting Information for SO-8 Package Provided Rating Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 14 mH, RG = 25 ) Thermal Resistance - Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol Value Unit VDSS VDGR 20 Vdc 20 Vdc VGS ID ID IDM PD 20 Vdc 5.6 3.6 30 Adc 2.5 Watts TJ, Tstg EAS November, 2000 - Rev. 6 P-Channel MARKING DIAGRAM SO-8 CASE 751 STYLE 13 - 55 to 150 C 567 mJ S3P02 LYWW 1 L Y WW = Location Code = Year = Work Week PIN ASSIGNMENT Apk N-C 1 8 Drain Source 2 7 Drain Source 3 6 Drain Gate 4 5 Drain Top View RJA 50 C/W TL 260 C 1. Negative sign for P-Channel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max. Semiconductor Components Industries, LLC, 2000 3 AMPERES 20 VOLTS RDS(on) = 75 m 8 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.) Drain-to-Source Voltage http://onsemi.com 715 ORDERING INFORMATION Device Package MMSF3P02HDR2 SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MMSF3P02HD/D MMSF3P02HD ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.) Characteristic Symbol Min Typ Max Unit 20 - - 24 - - - - - - 1.0 10 - - 100 1.0 - 1.5 4.0 2.0 - - - 0.06 0.08 0.075 0.095 gFS 3.0 7.2 - mhos Ciss - 1010 1400 pF Coss - 740 920 Crss - 260 490 td(on) - 25 50 tr - 135 270 td(off) - 54 108 tf - 84 168 td(on) - 16 32 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 3.0 Adc) (VGS = 4.5 Vdc, ID = 1.5 Adc) RDS(on) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) Vdc mV/C Ohm DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 3.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 3.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) Fall Time Gate Charge S Fi See Figure 8 (VDS = 16 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) tr - 40 80 td(off) - 110 220 tf - 97 194 QT - 33 46 Q1 - 3.0 - Q2 - 11 - Q3 - 10 - - - 1.35 0.96 1.75 - trr - 76 - ta - 32 - tb - 44 - QRR - 0.133 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 4.) (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time S Fi See Figure 15 (IS = 3.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 3. Negative sign for P-Channel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. http://onsemi.com 716 VSD Vdc ns C MMSF3P02HD TYPICAL ELECTRICAL CHARACTERISTICS 4$ " , " #$ 4: 6$ 47 6 4 4 #7 # #: GG $ 9 44 #$ # 6 9 8 # 6 9 8 < #$ 8 # ## #6 #9 #8 4 Figure 2. Transfer Characteristics # 4 6 $ 9 : 8 7 7 , " #$ 8 " 6$ : 9 $ # 4 $ 6 9 Figure 3. On-Resistance versus Gate-To-Source Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage " " " 4 7 46 4# Figure 1. On-Region Characteristics # 8 ?$ , " # 6 # 4 " $ , " #$ 6 9 # 9 $ $$ GG 9 #$ $ :$ #$ $ , " #$ 6 8 # 9 , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 717 # MMSF3P02HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 4$ *. 4 #$ " , " #$ " %!! # $ (!! %!! !! $ (!! $ $ $ # E'! Figure 7. Capacitance Variation http://onsemi.com 718 #6 @ 8 9 @ 6 # " 4 , " #$ @# 'CC 'C 8 # " " 4 " , " #$ # 9 ' ! # MMSF3P02HD 6 @4 6 8 # 9 # #6 #8 4# 49 '( ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 4 #$ " , " #$ # $ $ 4 6 $ 9 : 8 7 # 4 6 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 719 MMSF3P02HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For 9 " # " #$ ! ! - , ! ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 ! )L " 7 6$ 4 $ #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 720 MMSF3P02HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. $ " $ # $ # 2%* 94 9$# 788 4: . 998 . $$6 . 96 764: . 7$# :#69 . 6 4 # ' ! 5 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 721 5# +%1' 54 MMSF3P02HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.5 Watts 50C/W The 50C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 722 MMSF3P02HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 723 ( . Preferred Device #$%& '( N-Channel SO-8 These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Mounting Information for SO-8 Package Provided http://onsemi.com 5 AMPERES 20 VOLTS RDS(on) = 25 m N-Channel MARKING DIAGRAM SO-8 CASE 751 STYLE 13 8 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Symbol Value Unit VDSS VDGR 20 Vdc 20 Vdc VGS ID ID IDM PD 20 Vdc 8.2 5.6 41 Adc 2.5 Watts TJ, Tstg - 55 to 150 C EAS 675 Thermal Resistance - Junction to Ambient (Note 1.) RJA 50 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 260 C mJ November, 2000 - Rev. 6 L Y WW = Location Code = Year = Work Week PIN ASSIGNMENT N-C 1 8 Drain Source 2 7 Drain Source 3 6 Drain Gate 4 5 Drain Top View ORDERING INFORMATION Device MMSF5N02HDR2 1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max. Semiconductor Components Industries, LLC, 2000 1 Apk Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 6.0 mH, RG = 25 ) S5N02 LYWW 724 Package SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MMSF5N02HD/D MMSF5N02HD ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 20 - - 41 - - - - 0.02 - 1.0 10 - - 100 1.0 - 1.5 4.0 2.0 - - - 0.0185 0.0219 0.025 0.040 gFS 3.0 12 - Mhos Ciss - 1130 1582 pF Coss - 464 650 Crss - 117 235 td(on) - 15 30 tr - 93 185 td(off) - 35 70 tf - 40 80 td(on) - 9.0 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 5.0 Adc) (VGS = 4.5 Vdc, ID = 2.5 Adc) RDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc) Vdc mV/C Ohm DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 5.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 5.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) Fall Time Gate Charge S Fi See Figure 8 (VDS = 16 Vdc, ID = 5.0 Adc, VGS = 10 Vdc) tr - 53 - td(off) - 56 - tf - 39 - QT - 30.3 43 Q1 - 3.0 - Q2 - 7.5 - Q3 - 6.0 - - - 0.82 0.69 1.0 - trr - 32 - ta - 24 - tb - 8.0 - QRR - 0.045 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) (IS = 5.0 Adc, VGS = 0 Vdc) (IS = 5.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time S Fi See Figure 15 (IS = 5.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 725 VSD Vdc ns C MMSF5N02HD TYPICAL ELECTRICAL CHARACTERISTICS " 4 6$ 8 , " #$ 48 9 6 # 8 9 6 , " #$ # $$ #6 # 6 9 8 # 6 9 8 $ # #4 #$ #: #7 Figure 2. Transfer Characteristics # 8 6 # 4 6 $ 9 : 8 7 #4 , " #$ 4 44 " 6$ # 7 : # 6 9 8 Figure 3. On-Resistance versus Gate-to-Source Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage 9 " " " #$ , " #$ 6 # Figure 1. On-Region Characteristics " #$ 7 9 : # < # #$ 8 9 ?$ ?#$ #$ $ :$ #$ $ , , 8 # 6 9 Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 726 # MMSF5N02HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 4$ *. 4 #$ " " , " #$ %!! # $ (!! %!! !! $ (!! $ $ $ # E'! Figure 7. Capacitance Variation http://onsemi.com 727 # #6 @ " " $ " , " #$ 9 @ # " $ , " #$ @# 6 9 8 # ' ! # 8 'CC 'C '( ' 6 @4 MMSF5N02HD 6 8 # 9 # #6 #8 4# @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by $ 6 " , " #$ 4 # $ $$ 9 9$ : :$ 8 8$ Figure 10. Diode Forward Voltage versus Current http://onsemi.com 728 MMSF5N02HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For 9:$ " " #$ ! ! ! - , ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 ! )L " $ $:$ 6:$ 4:$ #:$ :$ :$ ?#$ #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 729 MMSF5N02HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. $ " $ # $ # 2%* 94 9$# 788 4: . 998 . $$6 . 96 764: . 7$# :#69 . 6 4 # ' ! 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 730 5 5# +%1' 54 MMSF5N02HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C 50C/W = 2.5 Watts The 50C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 731 MMSF5N02HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 732 (!. Preferred Device #$%& '( ! N-Channel SO-8 These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Mounting Information for SO-8 Package Provided http://onsemi.com 5 AMPERES 30 VOLTS RDS(on) = 40 m N-Channel MARKING DIAGRAM SO-8 CASE 751 STYLE 13 8 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Symbol Value Unit VDSS VDGR VGS 30 Vdc 30 Vdc 20 Vdc Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) ID ID IDM PD 6.5 4.4 33 Adc 2.5 Watts Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C Gate-to-Source Voltage - Continuous 1 L Y WW EAS 450 mJ Thermal Resistance - Junction to Ambient (Note 1.) RJA 50 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 260 C = Location Code = Year = Work Week PIN ASSIGNMENT Apk Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 4.0 mH, RG = 25 ) S5N03 LYWW N-C 1 8 Drain Source 2 7 Drain Source 3 6 Drain Gate 4 5 Drain Top View ORDERING INFORMATION Device MMSF5N03HDR2 Package SO-8 Shipping 2500 Tape & Reel 1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max. Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 6 733 Publication Order Number: MMSF5N03HD/D MMSF5N03HD ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - 34 - - - - - - 1.0 10 - - 100 1.0 - 2.0 5.0 3.0 - - - 0.033 0.04 0.040 0.050 gFS 3.0 8.0 - Mhos Ciss - 1207 1680 pF Coss - 354 490 Crss - 62 120 td(on) - 20 40 tr - 108 216 td(off) - 36 72 tf - 37 74 td(on) - 11 22 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 5.0 Adc) (VGS = 4.5 Vdc, ID = 2.5 Adc) RDS(on) Forward Transconductance (VDS = 3 Vdc, ID = 2.5 Adc) Vdc mV/C Ohms DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 5.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 9.1 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 5.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge S Fi See Figure 8 (VDS = 24 Vdc, ID = 5.0 Adc, VGS = 10 Vdc) tr - 36 72 td(off) - 68 136 tf - 38 76 QT - 15.2 21 Q1 - 3.4 - Q2 - 6.6 - Q3 - 5.6 - - - 0.88 0.77 1.3 - trr - 33 - ta - 21 - tb - 12 - QRR - 0.037 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) (IS = 5 Adc, VGS = 0 Vdc) (IS = 5 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time S Fi See Figure 15 (IS = 5.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 734 VSD Vdc ns C MMSF5N03HD TYPICAL ELECTRICAL CHARACTERISTICS " 8 , " #$ 6$ 9 48 6 4 # 8 9 6 , " #$ # $$ #6 # 6 9 8 # 6 9 8 # #9 #8 4 4# 8 6 # 4 6 $ 9 : 8 7 49 48 6#$ , " #$ 6 " 6$ 4:$ 4$ 4#$ 4 # 6 9 8 Figure 3. On-Resistance versus Gate-To-Source Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage 9 " " " $ , " #$ # 8 9 ?$ 46 Figure 2. Transfer Characteristics # 6 #6 Figure 1. On-Region Characteristics 9 ## " #$ # # < #$ ?#$ #$ $ :$ #$ $ # , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 735 4 MMSF5N03HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 4$ *. 4 #$ " " , " #$ %!! # $ %!! (!! !! $ (!! $ $ $ # #$ 4 E'! Figure 7. Capacitance Variation http://onsemi.com 736 MMSF5N03HD @ @# $ 9 " $ , " #$ 6 '( 'CC 'C $ # " $ " $ " 6$ , " #$ # ' ! GG @ 8 #$ GG # @4 # 6 9 8 # 6 9 ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by $ 6 " , " #$ 4 # $ $$ 9 9$ : :$ 8 8$ 7 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 737 MMSF5N03HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For 6$ " " #$ - , ! ! ! ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 ! )L " $ 4 $ #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 738 MMSF5N03HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. $ " $ # $ # 2%* 94 9$# 788 4: . 998 . $$6 . 96 764: . 7$# :#69 . 6 4 # ' ! 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 739 5 5# +%1' 54 MMSF5N03HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C 50C/W = 2.5 Watts The 50C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 740 MMSF5N03HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 741 ("!. Preferred Device #$%& '( " ! N-Channel SO-8 These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Mounting Information for SO-8 Package Provided http://onsemi.com 7 AMPERES 30 VOLTS RDS(on) = 28 m N-Channel MARKING DIAGRAM SO-8 CASE 751 STYLE 13 8 MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Symbol Value Unit VDSS VDGR VGS 30 Vdc 30 Vdc 20 Vdc Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) ID ID IDM PD 8.2 5.6 50 Adc 2.5 Watts Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C Gate-to-Source Voltage - Continuous EAS 450 Thermal Resistance - Junction to Ambient (Note 1.) RJA 50 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 260 C mJ November, 2000 - Rev. 4 L Y WW = Location Code = Year = Work Week PIN ASSIGNMENT N-C 1 8 Drain Source 2 7 Drain Source 3 6 Drain Gate 4 5 Drain Top View ORDERING INFORMATION Device MMSF7N03HDR2 1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max. Semiconductor Components Industries, LLC, 2000 1 Apk Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 4.0 mH, RG = 25 ) S7N03 LYWW 742 Package SO-8 Shipping 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MMSF7N03HD/D MMSF7N03HD ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - 41 - - - - 0.02 - 1.0 10 - - 100 1.0 - 1.5 4.0 2.0 - - - 0.023 0.029 0.028 0.040 gFS 3.0 12 - Mhos Ciss - 931 1190 pF Coss - 371 490 Crss - 89 120 td(on) - 15 30 tr - 93 185 td(off) - 35 70 tf - 40 80 td(on) - 9.0 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 7.0 Adc) (VGS = 4.5 Vdc, ID = 3.5 Adc) RDS(on) Forward Transconductance (VDS = 3 Vdc, ID = 2.5 Adc) Vdc mV/C Ohms DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 5.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 9.1 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 5.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge S Fi See Figure 8 (VDS = 16 Vdc, ID = 5.0 Adc, VGS = 10 Vdc) tr - 53 - td(off) - 56 - tf - 39 QT - 30 43 Q1 - 3.0 - Q2 - 7.5 - Q3 - 6.0 - - - 0.82 0.69 1.0 - trr - 32 - ta - 24 - tb - 8.0 - QRR - 0.045 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) (IS = 7.0 Adc, VGS = 0 Vdc) (IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time S Fi See Figure 15 (IS = 7.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 743 VSD Vdc ns C MMSF7N03HD TYPICAL ELECTRICAL CHARACTERISTICS " 6$ 47 4: $ #7 4$ 44 4 6 4 #: # #$ #$ $ :$ #$ $ :$ , " 4 # #$ $$ # #$ 4 4$ Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics $ 6 4 # # 6 9 8 $ , " #$ 6 " 6$ 4 # $ $ Figure 3. On-Resistance versus Gate-To-Source Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage " " 4$ " , " #$ $ #$ ?#$ 6 # ?$ 6 " 4$ , " #$ $ $ $ # 9 , " #$ 9 < 9 : , " #$ : #$ $ :$ #$ $ $ $ # #$ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 744 4 MMSF7N03HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6 *. 4$ 4 " " , " #$ %!! #$ # (!! $ %!! $ !! (!! $ $ $ # #$ 4 E'! Figure 7. Capacitance Variation http://onsemi.com 745 # #6 @ " " $ " , " #$ # 8 9 @ 9 # " $ , " #$ @# 6 8 # 'CC 'C '( ' 6 @4 ' ! MMSF7N03HD 6 8 # 9 # #6 #8 4# @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 8 : " , " #$ 9 $ 6 4 # $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 746 MMSF7N03HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For 68 " " #$ - , ! ! ! ! ;'1 # !J . 6 +)( !J # A ; 9 '2%0 !%DE1 !%1 ! )L " 7 *0 " 7 "6 66 6 49 4# #8 #6 # 9 # 8 6 #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 747 MMSF7N03HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. $ " $ # $ # 2%* 94 9$# 788 4: . 998 . $$6 . 96 764: . 7$# :#69 . 6 4 # ' ! 5 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 748 5# +%1' 54 MMSF7N03HD INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C 50C/W = 2.5 Watts The 50C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 749 MMSF7N03HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 750 ("!8 #$%& '( " ! N-Channel SO-8 EZFETst are an advanced series of Power MOSFETs which contain monolithic back-to-back zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. * Zener Protected Gates Provide Electrostatic Discharge Protection * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Designed to withstand 200V Machine Model and 2000V Human Body Model * Logic Level Gate Drive - Can Be Driven by Logic ICs * Miniature SO-8 Surface Mount Package - Saves Board Space * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Mounting Information for SO-8 Package Provided http://onsemi.com 7 AMPERES 30 VOLTS RDS(on) = 30 mW N-Channel MARKING DIAGRAM SO-8 CASE 751 STYLE 12 8 7N03Z LYWW 1 7N03Z L Y WW = Device Code = Location Code = Year = Work Week PIN ASSIGNMENT Source 1 8 Drain Source 2 7 Drain Source 3 6 Drain Gate 4 5 Drain Top View ORDERING INFORMATION Semiconductor Components Industries, LLC, 2001 January, 2001 - Rev. 1 751 Device Package MMSF7N03ZR2 SO-8 Shipping 2500 Tape & Reel Publication Order Number: MMSF7N03Z/D MMSF7N03Z MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Symbol Value Unit 30 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 30 Vdc Gate-to-Source Voltage - Continuous VGS 15 Vdc ID ID IDM PD 7.5 5.6 60 Adc 2.5 20 Watts mW/C PD 1.6 12 Watts mW/C TJ, Tstg EAS - 55 to 150 Drain-to-Source Voltage Drain Current - Continuous @ TA = 25C (Note 1.) - Continuous @ TA = 70C (Note 1.) - Pulsed Drain Current (Note 3.) Total Power Dissipation @ TA = 25C (Note 1.) Linear Derating Factor (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Linear Derating Factor (Note 2.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 4.0 mH, RG = 25 ) Thermal Resistance - Junction to Ambient (Note 1.) - Junction to Ambient (Note 2.) 1. When mounted on 1 square FR-4 or G-10 board (VGS = 10 V, @ 10 Seconds) 2. When mounted on 1 square FR-4 or G-10 board (VGS = 10 V, @ Steady State) 3. Repetitive rating; pulse width limited by maximum junction temperature. http://onsemi.com 752 Apk C mJ 450 RJA 50 80 C/W MMSF7N03Z ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - 35 - - - - 0.03 0.15 2.0 10 - 1.3 5.0 1.0 - 2.0 5.5 3.0 - - - 22 30 30 40 gFS 4.0 9.5 - Mhos Ciss - 750 1500 pF Coss - 340 680 Crss - 45 90 td(on) - 40 80 tr - 90 180 td(off) - 470 940 tf - 170 340 td(on) - 120 240 OFF CHARACTERISTICS (Cpk 2.0) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) (Notes 4. & 6.) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0) IGSS Vdc mV/C Adc Adc ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Notes 4. & 6.) (Cpk 2.0) (Notes 4. & 6.) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 7.5 Adc) (VGS = 4.5 Vdc, ID = 3.8 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 3.8 Adc) (Note 4.) VGS(th) Vdc RDS(on) mV/C m DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS = 15 Vdc, ID = 5.0 Adc, VGS = 10 Vdc, RG = 6 ) (Note 4.) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 5.0 Adc, VGS = 4.5 Vdc, RG = 6 ) (Note 4.) Fall Time Gate Charge (VDS = 24 Vdc, ID = 5.0 Adc, VGS = 10 Vdc) (Note 4.) tr - 350 700 td(off) - 430 860 tf - 140 280 QT - 34 48 Q1 - 3.5 - Q2 - 9.5 - Q3 - 6.5 - - - 0.83 0.67 1.6 - trr - 110 - ta - 22 - tb - 90 - QRR - 0.17 - ns ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 4.) (IS = 7.5 Adc, VGS = 0 Vdc) (Note 4.) (IS = 7.5 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 7.5 7 5 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) (Note 4.) Reverse Recovery Storage Charge 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperatures. 6. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 753 VSD Vdc ns C MMSF7N03Z TYPICAL ELECTRICAL CHARACTERISTICS , " #$ 4$ " 6$ 48 8 9 44 6 4 # 8 9 6 #$ # #: 6 8 9 # # 8 9 6 # # 6 9 8 $ 46 6 " 6$ 4 # # $ $ #$ $ :$ 8 9 Figure 4. On-Resistance versus Drain Current and Gate Voltage 6 " " #$ ?#$ 48 , " #$ Figure 3. On-Resistance versus Gate-to-Source Voltage < 4 Figure 2. Transfer Characteristics 8 ?$ #9 Figure 1. On-Region Characteristics " #$ , " #$ # ## , " $$ #$ $ " , " #$ $ $ # #$ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 754 4 MMSF7N03Z POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) #$ , " #$C " *. # %!! $ !! $ (!! 9 # 8 #6 Figure 7. Capacitance Variation http://onsemi.com 755 4 # #6 @ # 9 8 9 @ 6 # @# 8 " $ , " #$ # 6 @4 $ $ # #$ 4 4$ ' ! MMSF7N03Z " $ " :$ " , " #$ 'CC 'C '( ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by http://onsemi.com 756 MMSF7N03Z $ " , " #$ 6 4 # $ 9 8 : 7 Figure 10. Diode Forward Voltage versus Current %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 757 MMSF7N03Z $ " $ " #$ GG - , ! ! ! " $ 6 4 # #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. $ " $ # $ # 2%* 94 9$# 788 4: . 998 . $$6 . 96 764: . 7$# :#69 . 6 4 # ' ! 5 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 758 5# +%1' 54 MMSF7N03Z INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 9 $# #:$ : $$ 6 #6 9 $ #: inches mm SO-8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts. The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 2.5 Watts 50C/W The 50C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 759 MMSF7N03Z TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 760 #()! #() #()) Preferred Device 0 0 '( ! ) N-Channel TO-92 http://onsemi.com MAXIMUM RATINGS Symbol MPF930 MPF960 MPF990 Unit Drain-Source Voltage Rating VDS 35 60 90 Vdc Drain-Gate Voltage VDG 35 60 90 Vdc Gate-Source Voltage - Continuous - Non-repetitive (tp 50 s) VGS VGSM Vdc Vpk N-Channel Drain Current Continuous (Note 1.) Pulsed (Note 2.) Adc Total Device Dissipation @ TA = 25C Derate above 25C Operating and Storage Junction Temperature Range 20 40 2 AMPERES 35, 60, 90 VOLTS RDS(on) = 0.7 (MPF930) RDS(on) = 0.8 (MPF960) RDS(on) = 1.2 (MPF990) ID 2.0 IDM 3.0 PD TJ, Tstg 1.0 8.0 Watts mW/C -55 to 150 C TO-92 CASE 29 Style 22 JA 125 C/W 1. The Power Dissipation of the package may result in a lower continuous drain current. 2. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2.0%. Thermal Resistance 12 3 MARKING DIAGRAM & PIN ASSIGNMENT MPF930 YWW 1 Source 3 Drain 2 Gate Y WW = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 763 of this data sheet. Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 761 Publication Order Number: MPF930/D MPF930, MPF960, MPF990 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 35 60 90 - - - - - - IGSS - - 50 nAdc IDSS - - 10 Adc VGS(Th) 1.0 - 3.5 Vdc MPF930 MPF960 MPF990 - - - 0.4 0.6 0.6 0.7 0.8 1.2 (ID = 1.0 Adc) MPF930 MPF960 MPF990 - - - 0.9 1.2 1.2 1.4 1.7 2.4 (ID = 2.0 Adc) MPF930 MPF960 MPF990 - - - 2.2 2.8 2.8 3.0 3.5 4.8 - - - 0.9 1.2 1.2 1.4 1.7 2.0 ID(on) 1.0 2.0 - Amps Input Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Ciss - 70 - pF Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Crss - 20 - pF Output Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Coss - 49 - pF gfs 200 380 - mmhos Turn-On Time ton - 7.0 15 ns Turn-Off Time toff - 7.0 15 ns OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 10 Adc) V(BR)DSX MPF930 MPF960 MPF990 Gate Reverse Current (VGS = 15 Vdc, VDS = 0) Vdc ON CHARACTERISTICS (Note 3.) Zero-Gate-Voltage Drain Current (VDS = Maximum Rating, VGS = 0) Gate Threshold Voltage (ID = 1.0 mAdc, VDS = VGS) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 0.5 Adc) Static Drain-Source On Resistance (VGS = 10 Vdc, ID = 1.0 Adc) VDS(on) Vdc rDS(on) MPF930 MPF960 MPF990 On-State Drain Current (VDS = 25 Vdc, VGS = 10 Vdc) SMALL-SIGNAL CHARACTERISTICS Forward Transconductance (VDS = 25 Vdc, ID = 0.5 Adc) SWITCHING CHARACTERISTICS 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2.0%. http://onsemi.com 762 MPF930, MPF960, MPF990 RESISTIVE SWITCHING 5#$ $ #4 $ % # = $ 6 *. $ ' ;' 'CC 7B 7B ;' B 7B % B / $B Figure 2. Switching Waveforms Figure 1. Switching Test Circuit ORDERING INFORMATION Device $B Package Shipping MPF930 TO-92 1000 Unit/Box MPF930RLRE TO-92 2000 Tape & Reel MPF930A TO-92 1000 Unit/Box MPF930ARLRE TO-92 2000 Tape & Reel MPF960 TO-92 1000 Unit/Box MPF960RLRA TO-92 2000 Tape & Reel MPF990 TO-92 1000 Unit/Box MPF990RLRA TO-92 2000 Tape & Reel MPF990RLRP TO-92 2000 Ammo Pack http://onsemi.com 763 # 8 $ " 9 " *. MPF930, MPF960, MPF990 # $ 6 !! # 8 %!! 9 6 # (!! # $$ 4$ $ 8$ $ 5$ #$ 6$ 9$ , , #$ 6$ $ # #6 #8 " 8 $ # 7 9 4 # 4 6 $ 9 : 8 ?? 7 7 # 8 9 : # 9 8 $ 6 " 6 Figure 5. Transfer Characteristic $ # 4 6 ?? Figure 6. Output Characteristic #8 " #6 7 # 8 9 : # 9 8 $ 6 # $ $ Figure 4. Capacitance Variation #6 Figure 3. On Voltage versus Temperature # 4 6 ?? # 4 6 ?? Figure 7. Saturation Characteristic http://onsemi.com 764 6 4 $ $ ! Preferred Device #$%& '( " ! * %+% N-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Short Heatsink Tab Manufactured - Not Sheared * Specially Designed Leadframe for Maximum Power Dissipation http://onsemi.com 75 AMPERES 30 VOLTS RDS(on) = 6.5 m N-Channel D G S MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 30 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 30 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 20 Vdc Vpk ID ID IDM 75 59 225 Adc Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) PD 150 1.2 2.5 Watts W/C Watts Operating and Storage Temperature Range TJ, Tstg -55 to 150 C Rating Drain Current - Continuous - Continuous @ 100C - Single Pulse (tp 10 s) Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 75 Apk, L = 0.1 mH, RG = 25 ) Thermal Resistance - Junction-to-Case - Junction-to-Ambient - Junction-to-Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 5.0 seconds November, 2000 - Rev.1 D2PAK CASE 418B STYLE 2 2 1 3 MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain Apk EAS MTB1306 YWW 2 Drain 1 Gate mJ 3 Source 280 MTB1306 Y WW C/W RJC RJA RJA 0.8 62.5 50 TL 260 = Device Code = Year = Work Week ORDERING INFORMATION Device C 1. When surface mounted to an FR4 board using the minimum recommended pad size. Semiconductor Components Industries, LLC, 2000 4 765 Package Shipping MTB1306 D2PAK 50 Units/Rail MTB1306T4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MTB1306/D MTB1306 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - - - - - 10 100 - - 100 1.0 1.5 2.0 - - 5.8 7.4 6.5 8.5 - - 0.44 - 0.5 0.38 gFS 15 55 - mhos pF OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 38 Adc) (VGS = 5.0 Vdc, ID = 38 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 75 Adc) (VGS = 10 Vdc, ID = 38 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 3.0 Vdc, ID = 20 Adc) Vdc mW Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance Ciss - 2560 3584 Coss - 1305 1827 Crss - 386 772 td(on) - 17 35 SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 75 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 4.7 ) Fall Time Gate Charge (VDS = 24 Vdc, ID = 75 Adc, VGS = 5.0 Vdc) tr - 170 340 td(off) - 68 136 tf - 145 290 QT - 50 70 Q1 - 8.3 - Q2 - 25.3 - Q3 - 17.2 - - - 0.75 0.64 1.1 - trr - 84 - ta - 35 - tb - 53 - QRR - 0.13 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage VSD (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time Adc VGS = 0 Vdc, Vdc (IS = 20 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 766 Vdc ns C MTB1306 TYPICAL ELECTRICAL CHARACTERISTICS 8 " $ #$ 6 , " #$ :$ $ #$ 9 $ 6 # 8 9 #$ 6 #$ # $ :$ #$ :$ #$ $ # # 7 8 , " : #$ 9 $ $$ 6 4 # # 6 9 8 # 6 7 , " #$ 8 " $ : 9 $ 6 # 4 6 Figure 3. On-Resistance versus Drain Current and Temperature $ 9 : 8 7 # 4 6 $ Figure 4. On-Resistance versus Drain Current and Gate Voltage # " " 48 $ < 6$ Figure 2. Transfer Characteristics Figure 1. On-Region Characteristics , " $$ #$ 4 4$ 6 $ $ #$ #$ $ :$ , , #$ $ , " #$ $ Figure 5. On-Resistance Variation with Temperature $ # #$ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 767 4 MTB1306 POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 7 *. 8 : " " %!! 9 $ (!! 6 4 %!! # !! (!! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 768 #$ 8 $ :$ @ # $ 7 @ @# 9 #$ @4 , " #$ " :$ # 4 6 @ $ " $ " :$ " $ , " #$ ' ! MTB1306 '( 'C 'CC 4 9 ' Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # " , " #$ 8 9 6 # 8 9 6 # 6$ $ $$ 9 9$ : :$ Figure 10. Diode Forward Voltage versus Current http://onsemi.com 769 MTB1306 '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For ! ! #8 " " #$ - , " :$ #6 # 9 # 8 6 #$ Figure 12. Maximum Rated Forward Biased Safe Operating Area $ :$ #$ , , $ Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 770 MTB1306 (' <.. " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' ! 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 771 ,' " (' , - . / / ' ,*0 " *0 ,' 5 Preferred Device #$%& '( N-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Short Heatsink Tab Manufactured - Not Sheared * Specially Designed Leadframe for Maximum Power Dissipation http://onsemi.com 20 AMPERES 200 VOLTS RDS(on) = 160 m N-Channel D G S MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 200 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDSS VDGR 200 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 40 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 20 12 60 Adc MARKING DIAGRAM & PIN ASSIGNMENT Apk Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C, when mounted with the minimum recommended pad size PD 125 1.0 2.5 Watts W/C Watts 4 Drain Rating Drain-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient, when mounted with the minimum recommended pad size Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 4 2 1 TJ, Tstg - 55 to 150 C EAS 600 mJ 3 T20N20E YWW 1.0 62.5 50 TL 260 2 Drain 1 Gate T20N20E Y WW C/W RJC RJA RJA D2PAK CASE 418B STYLE 2 3 Source = Device Code = Year = Work Week ORDERING INFORMATION Device C Package Shipping MTB20N20E D2PAK 50 Units/Rail MTB20N20ET4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 772 Publication Order Number: MTB20N20E/D MTB20N20E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 200 - - 263 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - - 7.0 4.0 - Vdc mV/C - 0.12 0.16 Ohm - - - - 3.84 3.36 gFS 8.0 11 - mhos Ciss - 1880 2700 pF Coss - 378 535 Crss - 68 100 td(on) - 17 40 tr - 86 180 td(off) - 50 100 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 10 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 20 Adc) (ID = 10 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 13 Vdc, ID = 10 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 100 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (See Figure 8) (VDS = 160 Vdc, ID = 20 Adc, VGS = 10 Vdc) tf - 60 120 QT - 54 75 Q1 - 12 - Q2 - 24 - Q3 - 22 - - - 1.0 0.82 1.35 - trr - 239 - ta - 136 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 14) (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) VSD Vdc ns tb - 103 - QRR - 2.09 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 4.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 7.5 - nH Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 773 MTB20N20E TYPICAL ELECTRICAL CHARACTERISTICS , " #$ 6 8 " 7 6 : 4 # 9 $ # 4 6 $ 9 : 8 # $ Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics " , " # $ #$ $$ #$ #$ $ 6 8 9 # # #6 #8 4# 49 6 , " #$ 9 $ 6 " 4 # $ " " # 8 #$ #$ $ :$ , , #$ 8 # # 9 #6 #8 4# 6 49 " , " #$ 9 6 $ 6 Figure 4. On-Resistance versus Drain Current and Gate Voltage < # 8$ : Figure 3. On-Resistance versus Drain Current and Temperature #6 #$ 4 # #$ 4 4$ 6 6$ $ $$ 9 9$ : :$ 8 7 4$ 4 , " $$ $ 4$ $ #$ Figure 5. On-Resistance Variation with Temperature $ $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 774 # MTB20N20E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) $ %!! " " , " #$ *. 6 4 (!! %!! # !! (!! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 775 #$ MTB20N20E @ @ 8 # 9 7 6 9 " # , " #$ # 4 @4 # 4 6 @ " 4 " # " , " #$ $ @# $ 9 ' ! 8 # '( 'C 'CC ' Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS # " , " #$ 9 # 8 6 $ $$ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 776 MTB20N20E SAFE OPERATING AREA 9 " # " #$ - , F! F! F ! F ! " # $ 6 4 # #$ Figure 11. Maximum Rated Forward Biased Safe Operating Area $ $ :$ #$ , , Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 ' ! Figure 13. Thermal Response 4 %&' '(( ') '+ #$ '* / / (' <.. #$ # $ $ RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils #$ $ :$ #$ = Figure 15. D2PAK Power Derating Curve Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 777 $ MTB20N20E INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 44 848 8 #4# 6# 99 #6 979 6 9 # 4$ 94 :# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 2.5 Watts 50C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. TF21( )E 1!%!')1,;'% , ' +%1'U&/ : =)( )'1(%)E " 9#$ &. 6 # A **1( 9 " #$ #$ /)''! $ 4$ /)''! 6 $ /)''! 4 # # 6 9 8 (1) !J;)(1 %21! # 6 9 Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 778 MTB20N20E Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CC CCC CCC CCC CCC CC CCC CC CCC CCC CCCCCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 779 MTB20N20E TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joint. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 780 !# Preferred Device #$%& '( ! P-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 23 AMPERES 60 VOLTS RDS(on) = 120 m P-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 15 25 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 23 15 81 Adc Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) PD 90 0.60 3.0 Watts W/C TJ, Tstg -55 to 175 C MARKING DIAGRAM & PIN ASSIGNMENT EAS 794 mJ 4 Drain RJC RJA RJA TL 1.67 62.5 50 Rating Drain-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 23 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds 4 Apk D2PAK CASE 418B STYLE 2 2 1 3 C/W MTB23P06V YWW C 260 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2 Drain 1 Gate MTB23P06V Y WW 3 Source = Device Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTB23P06V D2PAK 50 Units/Rail MTB23P06VT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev.2 781 Publication Order Number: MTB23P06V/D MTB23P06V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 60.5 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.8 5.3 4.0 - Vdc mV/C - 0.093 0.12 Ohm - - 2.1 - 3.3 3.2 5.0 11.5 - Ciss - 1160 1620 Coss - 380 530 Crss - 105 210 td(on) - 13.8 30 tr - 98.3 200 td(off) - 41 80 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 11.5 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc, ID = 23 Adc) (VGS = 10 Vdc, ID = 11.5 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 10.9 Vdc, ID = 11.5 Adc) Vdc gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time (VDD = 30 Vdc, ID = 23 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 23 Adc, VGS = 10 Vdc) tf - 62 120 QT - 38 50 Q1 - 7.0 - Q2 - 18 - Q3 - 14 - - - 2.2 1.8 3.5 - trr - 142 - ta - 100 - tb - 41 - QRR - 0.804 - - 3.5 4.5 - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 23 Adc, VGS = 0 Vdc) (IS = 23 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 23 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 782 nH nH MTB23P06V TYPICAL ELECTRICAL CHARACTERISTICS 8 6 7 : 4 # 9 $ 6 " , " #$C # 9 6 8 100C #$ # $ # , " C $$C 9 6 $ $ # #$ 4 4$ 6 6$ # 9 : 8 , " #$C $ $ " 7$ $ 7 8$ 8 Figure 3. On-Resistance versus Drain Current and Temperature $ $ # 4 #$ 4$ 6 6$ $ Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 " " " $ < $ Figure 2. Transfer Characteristics 8 6 6 Figure 1. On-Region Characteristics #$C 9 4 #$C 4 # # , " $$C " 6 9 4$ $ 6 $ # 8 9 6 , " #$ # $ #$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature $ # 4 6 Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 783 9 MTB23P06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6 *. %!! 4 " " , " #$C (!! # %!! !! $ (!! $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 784 4 @ 7 8 @# @ : #: #6 # 9 8 $ $ 6 # 4 7 # @4 $ , " #$ " #4 $ # #$ 4 4$ 9 4 6 ' ! MTB23P06V , " #$ " #4 " 4 " '( 'C 'CC ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS #$ , " #$ " # $ $ #$ $ :$ #$ $ :$ # ##$ #$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 785 MTB23P06V SAFE OPERATING AREA 8 " # " #$ - , ! ! ! " #4 : 9 $ 6 4 # #$ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 ' ! Figure 13. Thermal Response 4 %&' '(( ') '+ #$ '* / / (' <.. #$ # $ $ RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils #$ $ :$ #$ $ = Figure 15. D2PAK Power Derating Curve Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 786 :$ MTB23P06V INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 44 848 8 #4# 6# 99 #6 979 6 9 # 4$ 94 :# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 175C - 25C = 3.0 Watts 50C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16. TJ(max) - TA RJA , , = &/ The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. : =)( )'1(%)E " 9#$ &. 6 # A **1( 9 " #$ #$ /)''! $ 4$ /)''! 6 $ /)''! 4 # # 6 9 8 @ # 6 9 Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 787 MTB23P06V Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCC CCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 788 MTB23P06V TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 789 ) Preferred Device #$%& '( ) N-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls. These devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 29 AMPERES 150 VOLTS RDS(on) = 70 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) Symbol Value Unit VDSS VDGR 150 Vdc 150 Vdc 4 VGS VGSM 20 40 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 29 19 102 Adc Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) PD 125 1.0 2.5 Watts W/C Watts Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 29 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds S D2PAK CASE 418B STYLE 2 2 1 3 Apk EAS MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain T29N15E YWW mJ 421 RJC RJA RJA TL 2 Drain C/W 1 Gate C T29N15E Y WW 1.0 62.5 50 260 3 Source = Device Code = Year = Work Week ORDERING INFORMATION 1. When surface mounted to an FR4 board using the minimum recommended pad size. Device Package Shipping MTB29N15E D2PAK 50 Units/Rail MTB29N15ET4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 790 Publication Order Number: MTB29N15E/D MTB29N15E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 150 - - 151 - - - - - - 10 100 - - 100 2.0 - 2.7 5.4 4.0 - - 0.054 0.07 - - - - 2.4 2.1 gFS 10 20 - mhos Ciss - 2300 3220 pF Coss - 450 630 Crss - 130 260 td(on) - 19 40 tr - 95 190 td(off) - 90 180 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 150 Vdc, VGS = 0 Vdc) (VDS = 150 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 14.5 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 10 Vdc) (ID = 29 Adc) (ID = 14.5 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 8.6 Vdc, ID = 14.5 Adc) Vdc mV/C Ohms Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time (VDD = 75 Vdc, ID = 29 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 120 Vdc, ID = 29 Adc, VGS = 10 Vdc) tf - 85 170 QT - 83 120 Q1 - 12 - Q2 - 37 - Q3 - 23 - - - 0.92 0.84 1.3 - trr - 174 - ta - 126 - tb - 48 - QRR - 1.4 - - - 3.5 4.5 - - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS VSD Forward On-Voltage (IS = 29 Adc, VGS = 0 Vdc) (IS = 29 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 29 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 791 nH MTB29N15E TYPICAL ELECTRICAL CHARACTERISTICS : " 7 $ , " #$ 8 9 6 4 $$ # $ 9 9$ 9 # 6 4 $ 9 : 8 $ 6 4 # , " 6$ 6 7 $$ 4 # #$ 9 6 $$ # # 4 6 9 $ 8 :$ : 8 , " #$ 9$ " 9 $ $$ $ 6$ 6 # 6 4 Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage " " " 6$ $ #$ :$ $ $ ##$ # 9 : < , " $ Figure 2. Transfer Characteristics " # 6 Figure 1. On-Region Characteristics 6 #$ 9 , " #$ #$ #$ ?$ ?#$ #$ $ :$ #$ $ , , Figure 5. On-Resistance Variation with Temperature # # 6 9 8 6 Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 792 9 MTB29N15E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: *. td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) :$ " " : 9$ %!! 9 $$ $ (!! 6$ 6 4$ 4 #$ # $ (!! $ $ $ , " #$ %!! !! $ # #$ Figure 7. Capacitance Variation http://onsemi.com 793 # @ 7 8 : @ 9 8 @# $ 9 6 6 4 , " #$ " #7 # @4 # # 4 6 9 $ : 8 7 'C 'CC ' ! MTB29N15E ' '( @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 4 " , " #$ #$ # $ $ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current http://onsemi.com 794 MTB29N15E %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the 6$ " # " #$ m! m! - , ! ! " #7 6 4$ 4 #$ # $ $ #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 795 MTB29N15E TYPICAL ELECTRICAL CHARACTERISTICS ('.. < " $ # $ *0 # ' '# - - " '&'# $ 4 6 # ' !1! Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 796 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MTB29N15E TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 797 ! Preferred Device #$%& '( ! * %+% N-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 30 AMPERES 60 VOLTS RDS(on) = 50 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 15 20 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 30 20 105 Adc Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) PD 90 0.6 3.0 Watts W/C Watts Operating and Storage Temperature Range TJ, Tstg - 55 to 175 C EAS 154 mJ RJC RJA RJA TL 1.67 62.5 50 Rating Drain-to-Source Voltage Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5 Vdc, Peak IL = 30 Apk, L = 0.342 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds G S 4 Apk D2PAK CASE 418B STYLE 2 2 1 3 MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain C/W T30N06VL YWW C 260 1 Gate 2 Drain 3 Source T30N06VL = Device Code Y = Year WW = Work Week 1. When surface mounted to an FR4 board using the minimum recommended pad size. ORDERING INFORMATION Device Package Shipping MTB30N06VL D2PAK 50 Units/Rail MTB30N06VLT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 5 798 Publication Order Number: MTB30N06VL/D MTB30N06VL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 63 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 1.0 - 1.5 4.0 2.0 - Vdc mV/C - 0.033 0.05 Ohms - - 1.1 - 1.8 1.73 gFS 13 21 - Mhos Ciss - 1130 1580 pF Coss - 360 500 Crss - 95 190 td(on) - 14 30 tr - 260 520 td(off) - 54 110 tf - 108 220 QT - 27 40 Q1 - 5 - Q2 - 17 - Q3 - 15 - - - 0.98 0.89 1.6 - trr - 86 - ta - 49 - tb - 37 - QRR - 0.228 - - 4.5 - - 7.5 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 5 Vdc, ID = 15 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 5 Vdc, ID = 30 Adc) (VGS = 5 Vdc, ID = 15 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 6.25 Vdc, ID = 15 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time (VDD = 30 Vdc, ID = 30 Adc, VGS = 5 Vdc, Vdc RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 30 Adc, VGS = 5 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 30 Adc, VGS = 0 Vdc) (IS = 30 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time Adc VGS = 0 Vdc, Vdc (IS = 30 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 799 nH nH MTB30N06VL TYPICAL ELECTRICAL CHARACTERISTICS " 8 $ 9 $ 6 6 4 # 4 8 # 4 6 $ 9 : 8 100C 6 4 # 7 6 $ Figure 2. Transfer Characteristics 6 #$C 4 # F$$C # 6 4 9 $ 9 9 , " #$C $ " $ 6 4 # Figure 3. On-Resistance versus Drain Current and Temperature # 4 6 $ 9 Figure 4. On-Resistance versus Drain Current and Gate Voltage # " $ " $ " , " #$C 6 < 4 Figure 1. On-Region Characteristics $ 9 # , " C 8 9 #$C " : , " $$C $ 9 , " #$C 9 # 8 9 C 6 # F$ F#$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature 4 # 6 $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 800 9 MTB30N06VL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) $ *. 6$ %!! 6 " " , " #$C 4$ 4 (!! #$ # $ %!! $ !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 801 4 6$ #: 6 #6 @ 4$ @# @ 4 # 8 #$ $ # # $ @4 $ $ $ 9 4 7 , " #$ " 4 #$ # ' ! $ MTB30N06VL , " #$ " 4 " 4 " $ '( 'C 'CC ' @ Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge DRAIN-TO-SOURCE DIODE CHARACTERISTICS 4 #$ , " #$ " # $ $ $ $$ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 802 MTB30N06VL SAFE OPERATING AREA " # " #$ 9 - , ! ! ! ! " 4 6 # 8 9 6 # #$ $ :$ #$ :$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature " $ # *0 $ # $ ' '# - - " '&'# 6 4 # ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 ' ! Figure 13. Thermal Response 4 / / (' <.. %&' '(( ') '+ #$ '* #$ # $ $ RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils #$ $ :$ #$ = $ Figure 15. D2PAK Power Derating Curve Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 803 :$ MTB30N06VL INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 44 848 8 #4# 6# 99 #6 979 6 9 # 4$ 94 :# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 175C - 25C = 3.0 Watts 50C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16. TJ(max) - TA RJA , , = &/ The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. : =)( )'1(%)E " 9#$ &. 6 # A **1( 9 " #$ #$ /)''! $ 4$ /)''! 6 $ /)''! 4 # # 6 9 8 @ # 6 9 Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 804 MTB30N06VL Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 805 MTB30N06VL TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 806 !# Preferred Device #$%& '( ! P-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 30 AMPERES 60 VOLTS RDS(on) = 80 m P-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 15 25 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 30 19 105 Adc Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) PD 125 0.83 3.0 Watts W/C TJ, Tstg -55 to 175 C MARKING DIAGRAM & PIN ASSIGNMENT EAS 450 mJ 4 Drain RJC RJA RJA TL 1.2 62.5 50 Rating Drain-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 30 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds 4 Apk D2PAK CASE 418B STYLE 2 2 1 3 C/W MTB30P06V YWW C 260 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2 Drain 1 Gate MTB30P06V Y WW 3 Source = Device Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTB30P06V D2PAK 50 Units/Rail MTB30P06VT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev.2 807 Publication Order Number: MTB30P06V/D MTB30P06V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 62 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.6 5.3 4.0 - Vdc mV/C - 0.067 0.08 Ohm - - 2.0 - 2.9 2.8 5.0 7.9 - Ciss - 1562 2190 Coss - 524 730 Crss - 154 310 td(on) - 14.7 30 tr - 25.9 50 td(off) - 98 200 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 15 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc, ID = 30 Adc) (VGS = 10 Vdc, ID = 15 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 8.3 Vdc, ID = 15 Adc) Vdc gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time (VDD = 30 Vdc, ID = 30 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 30 Adc, VGS = 10 Vdc) tf - 52.4 100 QT - 54 80 Q1 - 9.0 - Q2 - 26 - Q3 - 20 - - - 2.3 1.9 3.0 - trr - 175 - ta - 107 - tb - 68 - QRR - 0.965 - - 3.5 4.5 - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 30 Adc, VGS = 0 Vdc) (IS = 30 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 30 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 808 nH nH MTB30P06V TYPICAL ELECTRICAL CHARACTERISTICS 7 : 6 4 9 # $ 6 # # 6 9 8 #$C 6 4 , " $$C # # 6 $ 9 : Figure 2. Transfer Characteristics , " C #$C 9 $$C 6 # # 4 6 $ 9 8 8 , " #$C " : $ 9 $ 6 Figure 3. On-Resistance versus Drain Current and Temperature # 4 6 $ 9 Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 " " " $ , " #$ < 4 Figure 1. On-Region Characteristics 8 6 # " 9 100C $ 8 " $ 9 , " #$C 9 # 8 9 6 # $ #$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature $ 9 # 4 6 Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 809 : MTB30P06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 9 %!! *. $ 6 " " , " #$C (!! 4 %!! # !! $ (!! $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 810 7 4 #: @ 8 #6 @# @ : # 9 8 $ $ 6 # 4 7 # @4 , " #$ " 4 # 4 6 $ 9 4 9 ' ! MTB30P06V , " #$ " 4 " 4 " 'CC 'C '( ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 4 , " #$ " #$ # $ $ # 6 9 8 # 6 9 8 # ## Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 811 MTB30P06V SAFE OPERATING AREA " # " #$ 6$ - , ! ! ! ! " 4 6 4$ 4 #$ # $ $ #$ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' $ '# - - " '&'# 6 4 # ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* / / 4 #$ # $ $ RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 9 450 mils x 350 mils #$ $ :$ #$ $ = Figure 15. D2PAK Power Derating Curve Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 812 :$ MTB30P06V INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 44 848 8 #4# 6# 99 #6 979 6 9 # 4$ 94 :# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 175C - 25C = 3.0 Watts 50C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16. TJ(max) - TA RJA , , = &/ The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. : =)( )'1(%)E " 9#$ &. 6 # A **1( 9 " #$ #$ /)''! $ 4$ /)''! 6 $ /)''! 4 # # 6 9 8 @ # 6 9 Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 813 MTB30P06V Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CC CCC CCC CC CCCCCC CC CC CCC CCC CCC CCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 814 MTB30P06V TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 815 ! Preferred Device #$%& '( ! N-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 32 AMPERES 60 VOLTS RDS(on) = 40 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 50 s) VGS VGSM 20 25 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 32 22.6 112 Adc Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) PD 90 0.6 3.0 Watts W/C Watts Operating and Storage Temperature Range TJ, Tstg - 55 to 175 C MARKING DIAGRAM & PIN ASSIGNMENT EAS 205 mJ 4 Drain RJC RJA RJA TL 1.67 62.5 50 Rating Drain-to-Source Voltage Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 32 Apk, L = 0.1 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds G S 4 Apk D2PAK CASE 418B STYLE 2 2 1 3 C/W MTB36N06V YWW C 260 1 Gate 2 Drain MTB36N06V Y WW 1. When surface mounted to an FR4 board using the minimum recommended pad size. 3 Source = Device Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTB36N06V D2PAK 50 Units/Rail MTB36N06VT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 816 Publication Order Number: MTB36N06V/D MTB36N06V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 61 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.6 6.0 4.0 - Vdc mV/C - 0.034 0.04 Ohm - - 1.25 - 1.54 1.47 gFS 5.0 7.83 - mhos Ciss - 1220 1700 pF Coss - 337 470 Crss - 74.8 150 td(on) - 14 30 tr - 138 270 td(off) - 54 100 tf - 91 180 QT - 39 50 Q1 - 7 - Q2 - 17 - Q3 - 13 - - - 1.03 0.94 2.0 - trr - 92 - ta - 64 - tb - 28 - QRR - 0.332 - - 3.5 - - 7.5 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 16 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 32 Adc) (VGS = 10 Vdc, ID = 16 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 7.6 Vdc, ID = 16 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time (VDD = 30 Vdc, ID = 32 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 32 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 32 Adc, VGS = 0 Vdc) (IS = 32 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time Adc VGS = 0 Vdc, Vdc (IS = 32 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 817 nH nH MTB36N06V TYPICAL ELECTRICAL CHARACTERISTICS :# : 7 $6 8 9 49 $ 8 , " C :# " , " #$C #$C $6 49 8 $$C 6 # 4 6 9 : Figure 2. Transfer Characteristics $# , " C #$C 6 # 8 7 , " #$C " 49 F$$C 8 66 9 49 $6 #8 :# $ Figure 3. On-Resistance versus Drain Current and Temperature 8 49 $6 :# Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 " " 9 " , " #$C < $ Figure 1. On-Region Characteristics " 9 6 4 8 # 6 # C 25C 8 9 F$ F#$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature 4 # 6 $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 818 9 MTB36N06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6 *. " 4 " , " #$C %!! # %!! (!! !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 819 @ #$ 8 # @# @ $ 9 6 @4 # , " #$ " 4# $ $ $ # #$ 4 4$ 6 ' ! 4 # MTB36N06V , " #$ " 4# " 4 " '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 4# , " #$ " #6 9 8 $ $$ 9 9$ : :$ 8 8$ 7 7$ $ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 820 MTB36N06V SAFE OPERATING AREA " # " #$ ##$ - , ! ! ! ! " 4# # :$ $ #$ :$ $ #$ #$ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 ' ! Figure 13. Thermal Response 4 / / (' <.. %&' '(( ') '+ #$ '* #$ # $ $ RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils #$ $ :$ #$ $ = Figure 15. D2PAK Power Derating Curve Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 821 :$ MTB36N06V INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 44 848 8 #4# 6# 99 #6 979 6 9 # 4$ 94 :# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 175C - 25C = 3.0 Watts 50C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16. TJ(max) - TA RJA , , = &/ The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. : =)( )'1(%)E " 9#$ &. 6 # A **1( 9 " #$ #$ /)''! $ 4$ /)''! 6 $ /)''! 4 # # 6 9 8 @ # 6 9 Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 822 MTB36N06V Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CC CCC CCC CC CCCCCC CC CC CCC CCC CCC CCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 823 MTB36N06V TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 824 Preferred Device #$%& '( N-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 40 AMPERES 100 VOLTS RDS(on) = 40 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) Symbol Value Unit VDSS VDGR 100 Vdc 100 Vdc 4 VGS VGSM 20 40 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 40 29 140 Adc Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) PD 169 1.35 2.5 Watts W/C Watts Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 75 Vdc, VGS = 10 Vdc, Peak IL = 40 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds S D2PAK CASE 418B STYLE 2 2 1 3 Apk EAS MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain T40N10E YWW mJ 800 RJC RJA RJA TL C/W 1 Gate C T40N10E Y WW 0.74 62.5 50 260 2 Drain 3 Source = Device Code = Year = Work Week ORDERING INFORMATION 1. When surface mounted to an FR4 board using the minimum recommended pad size. Device Package Shipping MTB40N10E D2PAK 50 Units/Rail MTB40N10ET4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 825 Publication Order Number: MTB40N10E/D MTB40N10E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 100 - - 112 - - - - - - 10 100 - - 100 2.0 - 2.9 6.7 4.0 - - 0.033 0.04 - - - - 1.9 1.7 gFS 17 21 - mhos Ciss - 2305 3230 pF Coss - 620 1240 Crss - 205 290 td(on) - 19 40 OFF CHARACTERISTICS V(BR)DSS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) (Cpk 2.0) (Note 4.) Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) (Cpk 2.0) (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 20 Adc) (Cpk 2.0) (Note 4.) Drain-to-Source On-Voltage (VGS = 10 Vdc) (ID = 40 Adc) (ID = 20 Adc, TJ = 125C) VGS(th) Vdc RDS(on) Ohms VDS(on) Forward Transconductance (VDS = 8.4 Vdc, ID = 20 Adc) mV/C Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time (VDD = 50 Vdc, ID = 40 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 80 Vdc, ID = 40 Adc, VGS = 10 Vdc) tr - 165 330 td(off) - 75 150 tf - 97 190 QT - 80 110 Q1 - 15 - Q2 - 40 - Q3 - 29 - - - 0.96 0.88 1.0 - trr - 152 - ta - 117 - tb - 35 - QRR - 1.0 - - - 3.5 4.5 - - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage VSD (IS = 40 Adc, VGS = 0 Vdc) (IS = 40 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 14) (IS = 40 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Cpk + Max limit - Typ 3 sigma http://onsemi.com 826 nH MTB40N10E TYPICAL ELECTRICAL CHARACTERISTICS " : 7 9 8 , " #$ 8 8 : $ 6 9 4 # $ # 4 6 $ 9 : 8 7 $ , " $$ 6 4 # # 4 6 $ 9 : , " $ 6 #$ 4 $$ # # 4 6 $ 9 : 8 $ , " #$ 6$ 6 " 4$ 4 $ #$ # $ # # 9 4 6 $ 9 : 8 Figure 4. On-Resistance versus Drain Current and Gate Voltage " " " # 6 < Figure 3. On-Resistance versus Drain Current and Temperature 8 8 Figure 2. Transfer Characteristics " 9 #$ 9 Figure 1. On-Region Characteristics : : # 8 9 , " #$ 6 # $ #$ #$ $ :$ , , #$ $ Figure 5. On-Resistance Variation with Temperature # 4 6 9 : 8 $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 827 7 MTB40N10E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 8 *. 9 $ " " : , " #$C %!! (!! 6 4 %!! # !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 828 8 7 :# @ 8 96 : $9 9 @ 68 @# $ 6 6 4# 4 # #6 " 6 , " #$ @4 9 # 4 6 $ 9 : 8 8 " $ " 6 " , " #$ ' ! MTB40N10E '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 6 " , " #$ 4$ 4 #$ # $ $ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 829 MTB40N10E SAFE OPERATING AREA m! " # " #$ m! ! ! 8 - , " 6 : 9 $ 6 4 # #$ $ :$ #$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 ' !1! Figure 13. Thermal Response 4 %&' '(( ') '+ #$ '* / / (' <.. #$ # $ $ RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils #$ $ :$ #$ = Figure 15. D2PAK Power Derating Curve Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 830 $ MTB40N10E INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 44 848 8 #4# 6# 99 #6 979 6 9 # 4$ 94 :# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 2.5 Watts 50C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16. TJ(max) - TA RJA , , = &/ The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. : =)( )'1(%)E " 9#$ &. 6 # A **1( 9 " #$ #$ /)''! $ 4$ /)''! 6 $ /)''! 4 # # 6 9 8 @ # 6 9 Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 831 MTB40N10E Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 832 MTB40N10E TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 833 Preferred Device #$%& '( N-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 42 AMPERES 60 VOLTS RDS(on) = 28 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 25 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 42 30 147 Adc Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) PD 125 0.83 3.0 Watts W/C Watts Operating and Storage Temperature Range TJ, Tstg - 55 to 175 C MARKING DIAGRAM & PIN ASSIGNMENT EAS 400 mJ 4 Drain RJC RJA RJA TL 1.2 62.5 50 Rating Drain-Source Voltage Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 42 Apk, L = 0.454 H, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds G S 4 Apk D2PAK CASE 418B STYLE 2 2 1 3 C/W MTB50N06V YWW C 260 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2 Drain 1 Gate MTB50N06V Y WW 3 Source = Device Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTB50N06V D2PAK 50 Units/Rail MTB50N06VT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 4 834 Publication Order Number: MTB50N06V/D MTB50N06V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 69 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.7 3.0 4.0 - Vdc mV/C - 0.025 0.028 Ohm - - 1.4 - 1.7 1.6 gFS 16 23 - mhos Ciss - 1644 2320 pF Coss - 465 660 Crss - 112 230 td(on) - 12 20 tr - 122 250 td(off) - 64 110 tf - 54 90 QT - 47 70 Q1 - 9 - Q2 - 21 - Q3 - 16 - - - 1.06 0.99 2.5 - trr - 84 - ta - 73 - tb - 11 - QRR - 0.28 - - - 3.5 4.5 - - - 7.5 - OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 21 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 42 Adc) (ID = 21 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 6.25 Vdc, ID = 20 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time (VDD = 25 Vdc, ID = 42 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 42 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) (IS = 42 Adc, VGS = 0 Vdc) (IS = 42 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (S Figure (See Fi 14) Adc VGS = 0 Vdc, Vdc (IS = 42 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 835 nH nH MTB50N06V TYPICAL ELECTRICAL CHARACTERISTICS : 9 9 6 $ # 9 8 6 #6 4# #$ 9 , " $$ 6 # 6 # 4 6 $ 9 : 8 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics " , " #8 #$ ## 9 $$ # 6 9 8 44 7 , " #$ 4 #: " $ #6 # # 6 9 8 Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage #$ # " " " # , " #$ < 8 46 8 7 8 " , " #$ $ #$ $ $ #$ #$ $ :$ #$ $ :$ # 4 6 $ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 836 9 MTB50N06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 9 *. $ " " , " #$ %!! 6 4 (!! # %!! !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 837 $9 # 68 @ 6 8 @ 4# @# 9 #6 " 6# , " #$ 6 9 8 # @4 # 4 @ 6 $ ' ! 6 MTB50N06V " #$ " 6# " , " #$ '( 'C 'CC ' Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS $ " , " #$ 6 4 # $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 838 MTB50N06V SAFE OPERATING AREA 6 " # " #$ F! F! F ! F ! - , " 6# 4# #6 9 8 $ $ :$ #$ , , #$ Figure 11. Maximum Rated Forward Biased Safe Operating Area :$ Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature " $ # $ *0 # ' $ '# - - " '&'# 6 4 # ' ! ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 Figure 13. Thermal Response 4 / / (' <.. %&' '(( ') '+ #$ '* #$ # $ $ RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils #$ $ :$ #$ $ = Figure 15. D2PAK Power Derating Curve Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 839 :$ MTB50N06V INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 44 848 8 #4# 6# 99 #6 979 6 9 # 4$ 94 :# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 175C - 25C = 3.0 Watts 50C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16. TJ(max) - TA RJA , , = &/ The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. : =)( )'1(%)E " 9#$ &. 6 # A **1( 9 " #$ #$ /)''! $ 4$ /)''! 6 $ /)''! 4 # # 6 9 8 @ # 6 9 Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 840 MTB50N06V Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 841 MTB50N06V TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 842 Preferred Device #$%& '( * %+% N-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 42 AMPERES 60 VOLTS RDS(on) = 32 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 15 20 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 42 30 147 Adc Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) PD 125 0.83 3.0 Watts W/C Watts Operating and Storage Temperature Range TJ, Tstg - 55 to 175 C EAS 265 mJ RJC RJA RJA TL 1.2 62.5 50 Rating Drain-to-Source Voltage Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5 Vdc, Peak IL = 42 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds G S 4 Apk D2PAK CASE 418B STYLE 2 2 1 3 MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain C/W T50N06VL YWW C 260 1 Gate 2 Drain 3 Source T50N06VL = Device Code Y = Year WW = Work Week 1. When surface mounted to an FR4 board using the minimum recommended pad size. ORDERING INFORMATION Device Package Shipping MTB50N06VL D2PAK 50 Units/Rail MTB50N06VLT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 843 Publication Order Number: MTB50N06VL/D MTB50N06VL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 64 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 1.0 - 1.4 4.3 2.0 - Vdc mV/C - 0.025 0.032 Ohms - - 1.2 - 1.6 1.5 gFS 17 28 - Mhos Ciss - 1570 2200 pF Coss - 508 710 Crss - 135 270 td(on) - 16 30 tr - 355 701 td(off) - 80 160 tf - 160 320 QT - 40 60 Q1 - 11 - Q2 - 20 - Q3 - 16 - - - 1.03 0.94 2.5 - trr - 91.1 - ta - 63.8 - tb - 27.3 - QRR - 0.299 - - - 3.5 4.5 - - - 7.5 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = .25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 5 Vdc, ID = 21 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 5 Vdc, ID = 42 Adc) (VGS = 5 Vdc, ID = 21 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 6 Vdc, ID = 20 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time (VDD = 30 Vdc, ID = 42 Adc, VGS = 5 Vdc, Vdc RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 42 Adc, VGS = 5 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 42 Adc, VGS = 0 Vdc) (IS = 42 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time Adc VGS = 0 Vdc, Vdc (IS = 42 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 844 nH nH MTB50N06VL TYPICAL ELECTRICAL CHARACTERISTICS , " #$C 8 7 $ " 8 : : 9 6 9 $ 6 4 4 # $ $ # #$ : #$C $ 6 4 # 4 #$C # F$$C 7 8 49 6$ $6 94 #: :# 8 7 6 9 $ , " #$C 4$ 4 " $ #$ # $ $ Figure 3. On-Resistance versus Drain Current and Temperature 9 6 Figure 2. Transfer Characteristics , " C 8 4 Figure 1. On-Region Characteristics 6 # # " $ $ # 6 $ 4 9 : 8 7 Figure 4. On-Resistance versus Drain Current and Gate Voltage " $ " # 6 < 100C 9 4 9 , " $$C 8 7 # 8 9 " , " #$C C 6 # F$ F#$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature 4 # 6 $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 845 9 MTB50N06VL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 9 $ *. " %!! 6 , " #$C (!! 4 %!! # !! " $ (!! $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 846 4 @ #$ 8 9 $ @# @ 6 , " #$ " 6# # # @4 $ # 4 $ 6 ' ! # MTB50N06VL , " #$ " 6# " 4 " $ '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS #$ # , " #$ " $ $ $ $$ 9 9$ : :$ 8 8$ 7 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 847 MTB50N06VL SAFE OPERATING AREA " # " #$ 4 - , ! ! ! ! " 6# #$ # $ $ $ $ :$ #$ , , #$ Figure 11. Maximum Rated Forward Biased Safe Operating Area :$ Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature " $ # *0 $ # $ ' '# - - " '&'# 6 4 # ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 ' ! Figure 13. Thermal Response 4 / / (' <.. %&' '(( ') '+ #$ '* #$ # $ $ RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils #$ $ :$ #$ $ = Figure 15. D2PAK Power Derating Curve Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 848 :$ MTB50N06VL INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 44 848 8 #4# 6# 99 #6 979 6 9 # 4$ 94 :# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 175C - 25C = 3.0 Watts 50C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16. TJ(max) - TA RJA , , = &/ The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. : =)( )'1(%)E " 9#$ &. 6 # A **1( 9 " #$ #$ /)''! $ 4$ /)''! 6 $ /)''! 4 # # 6 9 8 @ # 6 9 Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 849 MTB50N06VL Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 850 MTB50N06VL TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 851 #!. Preferred Device #$%& '( ! * %+% P-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Short Heatsink Tab Manufactured - Not Sheared * Specially Designed Leadframe for Maximum Power Dissipation http://onsemi.com 50 AMPERES 30 VOLTS RDS(on) = 25 m P-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 30 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 30 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 15 20 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 50 31 150 Adc MARKING DIAGRAM & PIN ASSIGNMENT Apk 4 Drain Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C, when mounted with the minimum recommended pad size PD 125 1.0 2.5 Watts W/C Watts Rating Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 50 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient, when mounted with the minimum recommended pad size Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 4 D2PAK CASE 418B STYLE 2 2 1 3 M50P03HDL YWW TJ, Tstg - 55 to 150 C EAS 1250 mJ C/W RJC RJA RJA 1.0 62.5 50 TL 260 2 Drain 1 Gate M50P03HDL Y WW 3 Source = Device Code = Year = Work Week ORDERING INFORMATION C Device Package Shipping MTB50P03HDL D2PAK 50 Units/Rail MTB50P03HDLT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2001 January, 2001 - Rev. 4 852 Publication Order Number: MTB50P03HDL/D MTB50P03HDL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - 26 - - - - - - 1.0 10 - - 100 1.0 - 1.5 4.0 2.0 - - 20.9 25 - - 0.83 - 1.5 1.3 15 20 - Ciss - 3500 4900 Coss - 1550 2170 Crss - 550 770 td(on) - 22 30 tr - 340 466 td(off) - 90 117 tf - 218 300 QT - 74 100 Q1 - 13.6 - Q2 - 44.8 - Q3 - 35 - - - 2.39 1.84 3.0 - trr - 106 - ta - 58 - tb - 48 - QRR - 0.246 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 3.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 7.5 - nH OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 3.0) (Note 3.) Static Drain-Source On-Resistance (VGS = 5.0 Vdc, ID = 25 Adc) (Cpk 3.0) (Note 3.) Drain-Source On-Voltage (VGS = 5.0 Vdc) (ID = 50 Adc) (ID = 25 Adc, TJ =125C) Vdc RDS(on) Vdc gFS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance mV/C mOhm VDS(on) Forward Transconductance (VDS = 5.0 Vdc, ID = 25 Adc) DYNAMIC CHARACTERISTICS Output Capacitance VGS(th) mhos pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD= 15 Vdc, ID = 50 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 2.3 ) Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 24 Vdc, ID = 50 Adc, VGS = 5.0 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 50 Adc, VGS = 0 Vdc) (IS = 50 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 15) (IS = 50 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 853 MTB50P03HDL TYPICAL ELECTRICAL CHARACTERISTICS , " #$ " 8 8 $ 9 6 6$ 9 4$ 6 4 # , " F$$ $ #$ 8 9 6 # #$ 6 # 9 8 # 9 6 #4 #: 47 4$ 4 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics " $ #$ , " #4 #$ # 7 F$$ : $ 7 #7 #: $ # 8 # 6 9 8 ## " $ , " #$ # 64 # 7 8 : 9 $ # 6 9 8 Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 4$ #$ " " $ " #$ < $ $ , " #$ 7$ 8$ F$ F#$ #$ $ :$ #$ $ $ $ # #$ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 854 4 MTB50P03HDL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6 " *. " # %!! , " #$ 8 (!! 9 %!! 6 !! # (!! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 855 #$ 4 @ $ #$ @ 6 @# # $ 4 " $ , " #$ # $ @4 # 4 6 $ 8 : 9 ' ! 9 MTB50P03HDL " 4 " " $ , " #$ '( 'C 'CC ' @ 2 ! Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by $ " , " #$ 6 4 # 6 9 8 # 6 9 8 # ## #6 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 856 MTB50P03HDL %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For 6 - , " # " #$ ! ! " $ # ! 8 9 6 # #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 857 MTB50P03HDL ('.. < TYPICAL ELECTRICAL CHARACTERISTICS " $ # *0 $ ,' " (' , - . / / ' ,*0 " *0 ,' # ' '# - - " '&'# $ 6 4 # 5 5 ' ! Figure 14. Thermal Response %&' '(( ') '+ #$ '* / / 4 #$ # $ $ RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils #$ $ :$ #$ = Figure 16. D2PAK Power Derating Curve Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 858 $ MTB50P03HDL INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 44 848 8 #4# 6# 99 #6 979 6 9 # 4$ 94 :# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 2.5 Watts 50C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 17. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. , , = &/ : =)( )'1(%)E " 9#$ &. 6 # A **1( 9 " #$ #$ /)''! $ 4$ /)''! 6 $ /)''! 4 # # 6 9 8 @ # 6 Figure 17. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 859 9 MTB50P03HDL Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 18 shows a typical stencil for the DPAK and D2PAK packages. The CCC CCC CCC CC CCCCCCCCC CC CCC CCC CC CCCCCCCC Figure 18. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 860 MTB50P03HDL TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 19 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 19. Typical Solder Heating Profile http://onsemi.com 861 Preferred Device #$%& '( N-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 52 AMPERES 60 VOLTS RDS(on) = 22 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 25 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 52 41 182 Adc Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) PD 188 1.25 3.0 Watts W/C Watts Operating and Storage Temperature Range TJ, Tstg - 55 to 175 C MARKING DIAGRAM & PIN ASSIGNMENT EAS 406 mJ 4 Drain RJC RJA RJA TL 0.8 62.5 50 Rating Drain-Source Voltage Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 52 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds G S 4 Apk D2PAK CASE 418B STYLE 2 2 1 3 C/W MTB52N06V YWW C 260 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2 Drain 1 Gate MTB52N06V Y WW 3 Source = Device Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTB52N06V D2PAK 50 Units/Rail MTB52N06VT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 4 862 Publication Order Number: MTB52N06V/D MTB52N06V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 66 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.7 6.4 4.0 - Vdc mV/C - 0.019 0.022 - - - - 1.4 1.2 gFS 17 24 - mhos Ciss - 1900 2660 pF Coss - 580 810 Crss - 150 300 td(on) - 12 20 tr - 298 600 td(off) - 70 140 tf - 110 220 QT - 125 175 Q1 - 10 - Q2 - 30 - Q3 - 40 - - - 1.0 0.98 1.5 - trr - 100 - ta - 80 - tb - 20 - QRR - 0.341 - - - 3.5 4.5 - - - 7.5 - OFF CHARACTERISTICS (Cpk 2.0) (Note 4.) Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) (Cpk 2.0) (Note 4.) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 26 Adc) (Cpk 2.0) (Note 4.) Drain-Source On-Voltage (VGS = 10 Vdc, ID = 52 Adc) (VGS = 10 Vdc, ID = 26 Adc, TJ = 150C) VGS(th) RDS(on) Ohm VDS(on) Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time (VDD = 30 Vdc, ID = 52 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 52 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) (IS = 52 Adc, VGS = 0 Vdc) (IS = 52 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (S Figure Fi 14) (See (IS = 52 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 863 nH nH MTB52N06V TYPICAL ELECTRICAL CHARACTERISTICS " 7 7 , " #$ : 7 8 : 9 9 $ 6 4 $ # 4$ 6 4 # 9 $ 8 : 7 : 9 $ 6 4 # , " $$ #$ # 4 6 4$ 6$ $ $$ 9 : 9$ Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics , " #$ #$ # $ $$ $ # 4 6 $ 9 : 8 7 #4 :$ 8 7$ $ , " #$ ## # " # 7 $ 8 : 9 $ $ #$ $ 4$ 6$ $$ 9$ :$ 8$ Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage # :$ " " " #9 $ < #$ " 4 8 8 #$ :$ , " #$ $ #$ $ #$ #$ $ :$ #$ $ :$ , , # 4 6 $ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 864 9 MTB52N06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) : *. 9 %!! " " , " #$ $ 6 (!! 4 %!! # !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 865 @ 4 #: 8 #6 # @# @ 9 8 $ 6 # 7 " $# , " #$ # @4 # 6 9 8 @ # 9 4 6 ' ! 49 44 # MTB52N06V " 4 " $# " , " #$ 'C 'CC ' '( Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS $$ " , " #$ $ 6$ 6 4$ 4 #$ # $ $ # 4 6 $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 866 MTB52N06V SAFE OPERATING AREA 6$ " # " #$ - , F! F! F ! F ! " $# 6 4$ 4 #$ # $ $ #$ Figure 11. Maximum Rated Forward Biased Safe Operating Area $ :$ #$ $ , , :$ Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature " $ # $ *0 # ' '# - - " '&'# $ 6 4 # ' ! ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 Figure 13. Thermal Response 4 %&' '(( ') '+ #$ '* / / (' <.. #$ # $ $ RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils #$ $ :$ #$ $ = Figure 15. D2PAK Power Derating Curve Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 867 :$ MTB52N06V INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 44 848 8 #4# 6# 99 #6 979 6 9 # 4$ 94 :# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 175C - 25C = 3.0 Watts 50C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16. TJ(max) - TA RJA , , = &/ The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. : =)( )'1(%)E " 9#$ &. 6 # A **1( 9 " #$ #$ /)''! $ 4$ /)''! 6 $ /)''! 4 # # 6 9 8 @ # 6 9 Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 868 MTB52N06V SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CC CCC CCC CCC CC CCCCCC CC CCC CCCCCC CCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 869 MTB52N06V TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 870 Preferred Device #$%& '( * %+% N-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 52 AMPERES 60 VOLTS RDS(on) = 25 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 15 25 Vdc Vpk ID ID IDM PD 52 41 182 Adc 188 1.25 3.0 Watts W/C Watts - 55 to 175 C MARKING DIAGRAM & PIN ASSIGNMENT 406 mJ 4 Drain C/W MTB52N06VL YWW Rating Drain-to-Source Voltage Drain Current - Continuous - Continuous @ 100C - Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5 Vdc, Peak IL = 52 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds TJ, Tstg EAS RJC RJA RJA TL G S 4 D2PAK CASE 418B STYLE 2 Apk 2 1 3 0.8 62.5 50 1 Gate C 260 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2 Drain MTB52N06VL Y WW 3 Source = Device Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTB52N06VL D2PAK 50 Units/Rail MTB52N06VLT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 4 871 Publication Order Number: MTB52N06VL/D MTB52N06VL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 65 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 1.0 - 1.5 4.5 2.0 - Vdc mV/C - 0.022 0.025 - - - - 1.6 1.4 gFS 17 30 - Mhos Ciss - 1900 2660 pF Coss - 550 770 Crss - 170 340 td(on) - 15 30 tr - 500 1000 td(off) - 100 200 tf - 200 400 QT - 62 90 Q1 - 4.0 - Q2 - 31 - Q3 - 16 - - - 1.03 0.9 1.5 - trr - 104 - ta - 63 - tb - 41 - QRR - 0.28 - - - 3.5 4.5 - - - 7.5 - OFF CHARACTERISTICS (Cpk 2.0) (Note 4.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = .25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) (Note 4.) Static Drain-to-Source On-Resistance (VGS = 5 Vdc, ID = 26 Adc) (Cpk 2.0) (Note 4.) Drain-to-Source On-Voltage (VGS = 5 Vdc, ID = 52 Adc) (VGS = 5 Vdc, ID = 26 Adc, TJ = 150C) VGS(th) RDS(on) Ohm VDS(on) Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 30 Vdc, ID = 52 Adc, VGS = 5 Vdc, Vdc RG = 9.1 ) Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 52 Adc, VGS = 5 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 52 Adc, VGS = 0 Vdc) (IS = 52 Adc, VGS = 0 Vdc, TJ = 150 C) Reverse Recovery Time (IS = 52 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 872 nH nH MTB52N06VL TYPICAL ELECTRICAL CHARACTERISTICS " 8 7 : 8 9 $ 7 : 6 $ 6 4 # 4 # : 6 4 9 $ 8 : 7 : #$ 9 $ 6 4 # $ # #$ 4$ 4 6 6$ $ Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics $ 6 , " 4 #$ # $$ # 4 6 $ 9 : 8 7 6 $$ 4 " $ #$ # $ $ # 4 6 9 $ : 8 7 Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 9 " $ " #9 9 , " #$ 4$ " , " #$ 6 < 8 " $ , " $$ 9 $ 9 , " #$ # 8 9 6 # $ #$ #$ $ :$ #$ $ :$ , , # 4 6 $ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 873 9 MTB52N06VL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 8 *. : " " , " #$ %!! 9 $ (!! 6 4 %!! # !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 874 4 @ 7 #: 8 #6 : # 9 8 @# @ $ $ 6 # 4 7 " $# , " #$ # @4 # 4 6 $ @ 9 4 : 9 ' ! MTB52N06VL " 4 " $# " $ , " #$ '( 'C 'CC ' Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS $$ $ 6$ " , " #$ 6 4$ 4 #$ # $ $ $ $$ 9 9$ : :$ 8 8$ 7 7$ $ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 875 MTB52N06VL SAFE OPERATING AREA 6$ " $ " #$ - , F! F! F ! F ! " $# 6 4$ 4 #$ # $ $ #$ Figure 11. Maximum Rated Forward Biased Safe Operating Area $ :$ #$ $ , , :$ Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature " $ # $ *0 # ' '# - - " '&'# $ 6 4 # ' ! ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 Figure 13. Thermal Response 4 / / (' <.. %&' '(( ') '+ #$ '* #$ # $ $ RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils #$ $ :$ #$ $ = Figure 15. D2PAK Power Derating Curve Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 876 :$ MTB52N06VL INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 44 848 8 #4# 6# 99 #6 979 6 9 # 4$ 94 :# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 175C - 25C = 3.0 Watts 50C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16. TJ(max) - TA RJA , , = &/ The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. : =)( )'1(%)E " 9#$ &. 6 # A **1( 9 " #$ #$ /)''! $ 4$ /)''! 6 $ /)''! 4 # # 6 9 8 @ # 6 9 Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 877 MTB52N06VL SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CC CCC CCC CCC CC CCCCCC CC CCC CCCCCC CCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 878 MTB52N06VL TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 879 8 Preferred Device #$%& '( N-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche mode and switch efficiently. This high energy device also offers a drain-to-source diode with fast recovery time. Designed for high voltage, high speed switching applications in power supplies, PWM motor controls and other inductive loads, the avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Capability Specified at Elevated Temperature * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Low Stored Gate Charge for Efficient Switching * Internal Source-to-Drain Diode Designed to Replace External Zener Transient Suppressor-Absorbs High Energy in the Avalanche Mode * ESD Protected. Designed to Typically Withstand 400 V Machine Model and 4000 V Human Body Model. http://onsemi.com 55 AMPERES 60 VOLTS RDS(on) = 18 m N-Channel D G S MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 40 Vdc Vpk Drain Current - Continuous @ TC = 25C - Continuous @ TC = 100C - Single Pulse (tp 10 s) ID ID IDM 55 35.5 165 Adc PD 113 0.91 2.5 Watts W/C TJ, Tstg - 55 to 150 C EAS 454 mJ Rating Total Power Dissipation @ TC = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VDS = 60 Vdc, VGS = 10 Vdc, Peak IL = 55 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds November, 2000 - Rev. 2 D2PAK CASE 418B STYLE 2 2 1 3 MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain Apk MTB55N06Z YWW 2 Drain 1 Gate MTB55N06Z Y WW C/W RJC RJC RJA 1.1 62.5 50 TL 260 C 880 3 Source = Device Code = Year = Work Week ORDERING INFORMATION Device 1. When surface mounted to an FR4 board using the minimum recommended pad size. Semiconductor Components Industries, LLC, 2000 4 Package Shipping MTB55N06Z D2PAK 50 Units/Rail MTB55N06ZT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MTB55N06Z/D MTB55N06Z ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 53 - - - - - - 1.0 10 - - 100 2.0 - 3.0 6.0 4.0 - - 14 18 - - 0.825 0.74 1.2 1.0 gFS 12 15 - Mhos Ciss - 1390 1950 pF Coss - 520 730 Crss - 119 238 td(on) - 27 54 tr - 157 314 td(off) - 116 232 OFF CHARACTERISTICS (Cpk 2.0) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 27.5 Adc) (Cpk 2.0) Drain-to-Source On-Voltage (VGS = 10 Vdc) (ID = 55 Adc) (ID = 27.5 Adc, TJ = 125C) VGS(th) Vdc RDS(on) m VDS(on) Forward Transconductance (VDS = 4.0 Vdc, ID = 27.5 Adc) mV/C Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time (VDD = 30 Vdc, ID = 55 Adc, VGS(on) Vdc, GS( ) = 10 Vdc RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 55 Adc, VGS = 10 Vdc) tf - 126 252 QT - 40 56 Q1 - 7.0 - Q2 - 18 - Q3 - 15 - - - 0.93 0.82 1.1 - trr - 57 - ta - 32 - tb - 25 - QRR - 0.11 - - - 3.5 4.5 - - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 55 Adc, VGS = 0 Vdc) (IS = 55 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 55 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 881 nH MTB55N06Z 9 , " #$ 9 : 6 4 # $ " 6 $ $ # #$ 4 4$ 6$ 6 $ 6 4 #$ # , " $$ # #6 #8 4# 49 66 6 68 $# $9 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics #6 " , " # 9 #$ # $$ 8 $ # 4 6 9 $ W W 7 8 $ < 9 , " #$ 69 " 6# 48 $ 46 4 # 6 4 $ Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 9 " " $ # , " #$ 8 9 $ 9 #$ " 6 96 $ 9 #$ #$ $ :$ #$ $ # 4 6 $ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 882 9 " *. , " #$ %!! 4# 68 # " 6 @ 6 8 #6 (!! 9 %!! $ $ $ # #$ 6 '( 'C 'CC # #6 #8 4# 49 6 # $ $6 $8 9# 99 : :6 :8 8# 89 7 76 Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current m! - , " # " #$ m! ! ! 9 , " #$ " # 4 , " #$ " 4 " 4 " ' ! 8 Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge ' 8 @ Figure 7. Capacitance Variation , " #$ " 4 @4 #6 9 # (!! @# 6 !! 8 @ 9 4# MTB55N06Z $ " 4 6 4 # #$ $ :$ #$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 883 MTB55N06Z ('.. < " $ # $ # ' !1! Figure 13. Thermal Response http://onsemi.com 884 . Preferred Device #$%& '( * %+% N-Channel D2PAK The D2PAK package has the capability of housing a larger die than any existing surface mount package which allows it to be used in applications that require the use of surface mount components with higher power and lower RDS(on) capabilities. This advanced high-cell density HDTMOS power FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Short Heatsink Tab Manufactured - Not Sheared * Specially Designed Leadframe for Maximum Power Dissipation N-Channel D G S 4 D2PAK CASE 418B STYLE 2 2 3 Symbol Value Unit Drain-to-Source Voltage VDSS 50 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 50 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 15 20 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 60 42 180 Adc Total Power Dissipation Derate above 25C PD 150 1.0 Watts W/C TJ, Tstg - 55 to 175 C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 ) EAS 540 mJ Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient RJC RJA 1.0 62.5 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 5 seconds TL 260 C Operating and Storage Temperature Range 60 AMPERES 50 VOLTS RDS(on) = 14 m 1 MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating http://onsemi.com MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain T60N05HDL YWW Apk 2 Drain 1 Gate T60N05HDL Y WW 3 Source = Device Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTB60N05HD D2PAK 50 Units/Rail MTB60N05HDT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev.2 885 Publication Order Number: MTB60N05HDL/D MTB60N05HDL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 50 - - 55 - - - - - - 10 100 - - 100 1.0 - 1.5 4.5 2.0 - - 0.010 0.014 - - - - 1.0 0.75 15 48 - Unit OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 50 Vdc, VGS = 0 Vdc) (VDS = 50 Vdc, VGS = 0 Vdc, TJ = -25C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 5.0 Vdc, ID = 30 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 5.0 Vdc) (ID = 60 Adc) (ID = 30 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 4.0 Vdc, ID = 20 Adc) Vdc mV/C Ohms Vdc gFS mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance Ciss - 2775 4000 Coss - 750 1070 Crss - 150 300 td(on) - 21 40 pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 Vdc, ID = 60 Adc, VGS = 5.0 Vdc, RG = 9.1 ) Fall Time Gate Charge g (VDS = 40 Vdc, ID = 60 Adc, VGS = 5.0 Vdc) tr - 570 1150 td(off) - 86 170 tf - 200 400 QT - 42 62 Q1 - 8.0 - Q2 - 24 - Q3 - 17 - - - 0.95 0.85 1.1 - trr - 50 - ta - 34 - tb - 15 - QRR - 0.085 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 60 Adc, VGS = 0 Vdc) (IS = 60 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery y Time (IS = 30 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 886 VSD Vdc ns C MTB60N05HDL TYPICAL ELECTRICAL CHARACTERISTICS # 6 # , " #$ 8 4$ $ 9 6 4 # $ 6 $ # #$ 4 4$ 6 6$ #$ # $ $ # #$ 4 4$ Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics , " 6 # #$ 8 $$ , " #$ 9 # 4 $ 6 9 : 8 7 # 6 6 4 , " #$ # " $ 7 8 : 9 # 6 9 8 # Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 9 " " " $ , " #$ < 9 $$ 8 9 8 #$ 8 9 6$ " 6 # 8 9 F$ #$ F#$ #$ $ :$ #$ $ $ $ # #$ 4 4$ 6 , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 887 6$ $ MTB60N05HDL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) " " 7 8 *. , " #$ %!! : (!! 9 $ 6 %!! 4 # !! (!! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 888 #$ 9 9 $ @ 6 6 4 @ # @# # , " 9 " $ @4 # 4 6 $ " #$ " 9 " $ , " #$ ' ! 8 MTB60N05HDL '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 9 $ " , " #$ 6 4 # $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 889 MTB60N05HDL '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. - , The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For " $ " #$ ! ! 9 6 4 # " 9 $ #$ $ :$ #$ $ :$ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 890 MTB60N05HDL " $ # *0 $ # ' '# - - " '&'# ' ! ,' " (' , - . / / ' ,*0 " *0 ,' Figure 14. Thermal Response 4 %&' '(( ') '+ #$ '* / / ('.. < TYPICAL ELECTRICAL CHARACTERISTICS #$ # $ $ #$ RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils $ :$ #$ = Figure 16. D2PAK Power Derating Curve Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 891 $ MTB60N05HDL INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 44 848 8 #4# 6# 99 #6 979 6 9 # 4$ 94 :# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 2.5 Watts 50C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 17. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. , , = &/ : =)( )'1(%)E " 9#$ &. 6 # A **1( 9 " #$ #$ /)''! $ 4$ /)''! 6 $ /)''! 4 # # 6 9 8 @ # 6 Figure 17. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 892 9 MTB60N05HDL Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 18 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 18. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 893 MTB60N05HDL TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 19 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 19. Typical Solder Heating Profile http://onsemi.com 894 . Preferred Device #$%& '( N-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Short Heatsink Tab Manufactured - Not Sheared * Specially Designed Leadframe for Maximum Power Dissipation http://onsemi.com 60 AMPERES 60 VOLTS RDS(on) = 14 m N-Channel D G S MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 30 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 60 42.3 180 Adc MARKING DIAGRAM & PIN ASSIGNMENT Apk 4 Drain Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) PD 125 1.0 2.5 Watts W/C Watts Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C EAS 540 mJ Rating Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient, when mounted with the minimum recommended pad size Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 4 2 1 3 T60N06HD YWW 1 Gate 1.0 62.5 50 TL 260 2 Drain 3 Source T60N06HD = Device Code Y = Year WW = Work Week C/W RJC RJA RJA D2PAK CASE 418B STYLE 2 ORDERING INFORMATION C 1. When mounted with the minimum recommended pad size. Device Package Shipping MTB60N06HD D2PAK 50 Units/Rail MTB60N06HDT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev.3 895 Publication Order Number: MTB60N06HD/D MTB60N06HD ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 71 - - - - - - 10 100 - - 100 2.0 - 3.0 7.0 4.0 - - 0.011 0.014 - - - - 1.0 0.9 15 20 - Ciss - 1950 2800 Coss - 660 920 Crss - 147 300 td(on) - 14 26 tr - 197 394 td(off) - 50 102 tf - 124 246 QT - 51 71 Q1 - 12 - Q2 - 24 - Q3 - 21 - - - 0.99 0.89 1.0 - trr - 60 - ta - 36 - tb - 24 - QRR - 0.143 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 4.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 7.5 - nH OFF CHARACTERISTICS (Cpk 2.0) (Note 4.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 3.0) (Note 4.) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 30 Adc) (Cpk 3.0) (Note 4.) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 60 Adc) (ID = 30 Adc, TJ =125C) Vdc RDS(on) Vdc gFS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance mV/C Ohm VDS(on) Forward Transconductance (VDS = 4.0 Vdc, ID = 30 Adc) DYNAMIC CHARACTERISTICS Output Capacitance VGS(th) mhos pF SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD= 30 Vdc, ID = 60 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 60 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 60 Adc, VGS = 0 Vdc) (IS = 60 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 15) (IS = 60 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 896 MTB60N06HD TYPICAL ELECTRICAL CHARACTERISTICS 8 " 7 , " #$ 8 9 9 6 $ # $ $ # #$ 4$ 4 6 6$ #$ , " F$$ #8 49 66 $# 9 98 Figure 2. Transfer Characteristics 6 #$ # F$$ 8 # 4 6 $ 9 : 8 7 # 4# #6 # " 9 # 8 $ 6 # 4 6 $ 9 : 8 7 # Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 9 :9 , " #$ #8 " " " 4 , " #$ < Figure 1. On-Region Characteristics , " 6 # $ " 9 9 9 8 # 8 # # : # 6 # #$ 8 9 F$ F#$ #$ $ :$ #$ $ # 4 6 $ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 897 9 MTB60N06HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) $ *. 6 %!! " " , " #$ 4 (!! %!! # !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 898 9 @ $ 8 @ 6 @# 9 4 6 # # " 9 , " #$ @4 8 9 #6 4# 6 68 $9 ' ! # MTB60N06HD " 4 " 9 " , " #$ '( 'C 'CC ' @ 2 ! Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 9 $ " , " #$ 6 4 # $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 899 MTB60N06HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. - , The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For " # " #$ ! ! ! ! 9 6 4 # " 9 $ #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 900 MTB60N06HD " $ # *0 $ ,' " (' , - . / / ' ,*0 " *0 ,' # ' '# - - " '&'# $ 6 # ' ! 4 5 5 Figure 14. Thermal Response 4 %&' '(( ') '+ #$ '* / / ('.. < TYPICAL ELECTRICAL CHARACTERISTICS #$ # $ $ #$ RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils $ :$ #$ = Figure 16. D2PAK Power Derating Curve Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 901 $ MTB60N06HD INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 44 848 8 #4# 6# 99 #6 979 6 9 # 4$ 94 :# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 2.5 Watts 50C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 17. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. , , = &/ : =)( )'1(%)E " 9#$ &. 6 # A **1( 9 " #$ #$ /)''! $ 4$ /)''! 6 $ /)''! 4 # # 6 9 8 @ # 6 Figure 17. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 902 9 MTB60N06HD Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 18 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 18. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 903 MTB60N06HD TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 19 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 19. Typical Solder Heating Profile http://onsemi.com 904 "!. Preferred Device #$%& '( " * %+% N-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Short Heatsink Tab Manufactured - Not sheared * Specially Designed Leadframe for Maximum Power Dissipation http://onsemi.com 75 AMPERES 25 VOLTS RDS(on) = 9 m N-Channel D G S MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 25 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 25 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 15 20 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 75 59 225 Adc Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) PD 125 1.0 2.5 Watts W/C Watts Rating Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 75 Apk, L = 0.1 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 4 D2PAK CASE 418B STYLE 2 2 1 3 mJ C/W 1.0 62.5 50 TL 260 T75N03HDL YWW C 280 RJC RJA RJA 4 Drain Apk - 55 to 150 EAS MARKING DIAGRAM & PIN ASSIGNMENT 2 Drain 1 Gate T75N03HDL Y WW 3 Source = Device Code = Year = Work Week ORDERING INFORMATION C Device Package Shipping MTB75N03HDL D2PAK 50 Units/Rail MTB75N03HDLT4 D2PAK 800/Tape & Reel 1. When mounted with the minimum recommended pad size. Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 905 Publication Order Number: MTB75N03HDL/D MTB75N03HDL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 25 - - Unit OFF CHARACTERISTICS (Cpk 2.0) (Note 4.) Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Vdc mV/C Zero Gate Voltage Drain Current (VDS = 25 Vdc, VGS = 0 Vdc) (VDS = 25 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 V) IGSS Adc - - - - 100 500 - - 100 1.0 1.5 2.0 nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) (Cpk 3.0) (Note 4.) Static Drain-Source On-Resistance (VGS = 5.0 Vdc, ID = 37.5 Adc) (Cpk 2.0) (Note 4.) VGS(th) Vdc mV/C Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 75 Adc) (ID = 37.5 Adc, TJ = 125C) RDS(on) m - 6.0 9.0 - - - - 0.68 0.6 gFS 15 55 - mhos Ciss - 4025 5635 pF Coss - 1353 1894 Crss - 307 430 td(on) - 24 48 tr - 493 986 td(off) - 60 120 tf - 149 300 QT - 61 122 Q1 - 14 28 Q2 - 33 66 Q3 - 27 54 - - 0.97 0.87 1.1 - trr - 58 - ta - 27 - tb - 30 - QRR - 0.088 - VDS(on) Forward Transconductance (VDS = 3 Vdc, ID = 20 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS= 15 Vdc, ID = 75 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 4.7 ) Fall Time Gate Charge (VDS = 24 Vdc, ID = 75 Adc, VGS = 5.0 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 75 Adc, VGS = 0 Vdc) (IS = 75 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 75 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 906 VSD Vdc ns C MTB75N03HDL TYPICAL ELECTRICAL CHARACTERISTICS " $ 8 # $ 6$ , " #$C 6 9 $ 7 4$ 9 4 4 # # 7 9 4 6 9 8 # 6 9 8 $ # #$C $$C 6 # 4 9 7 # $ , " C 9 , " #$C 8 : " $ 9 $ 6 :$ $ Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage " " 4:$ 9 6$ 7 # # 8 6 # #$ 4 4$ 6 Figure 2. Transfer Characteristics " $ 8 < Figure 1. On-Region Characteristics #$ , " $$C #$ #$ #$ $ , " #$ #$ $ #$ #$ $ :$ , , #$ $ " Figure 5. On-Resistance Variation with Temperature $ $ # #$ Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 907 4 MTB75N03HDL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) $ *. # " " , " #$C %!! 7 9 (!! %!! !! 4 (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 908 #8 9 #6 @ $ @# @ 6 # 9 # 4 , " #$ " :$ # 6 @4 $ # 4 6 @ 8 9 : ' ! : MTB75N03HDL '( 'C 'CC ' , " #$ " :$ " $ " $ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by :$ 9 , " #$ " 6$ 4 $ $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 909 MTB75N03HDL SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For #8 " # " #$ - , ! ! ! " :$ #6 # 9 # 8 6 #$ $ :$ #$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 910 MTB75N03HDL ('.. < TYPICAL ELECTRICAL CHARACTERISTICS " $ # *0 $ ,' " (' , - . / / ' ,*0 " *0 ,' # ' $ '# - - " '&'# 6 4 # 5 5 ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* / / 4 #$ # $ $ RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils #$ $ :$ #$ = Figure 15. D2PAK Power Derating Curve Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 911 $ MTB75N03HDL INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 44 848 8 #4# 6# 99 #6 979 6 9 # 4$ 94 :# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 2.5 Watts 50C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 17. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. , , = &/ : =)( )'1(%)E " 9#$ &. 6 # A **1( 9 " #$ #$ /)''! $ 4$ /)''! 6 $ /)''! 4 # # 6 9 8 @ # 6 Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 912 9 MTB75N03HDL Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 18 shows a typical stencil for the DPAK and D2PAK packages. The CCC CCC CC CC CCCCCCCC CC CCC CCC CC CCCCCCCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 913 MTB75N03HDL TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 19 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 914 ". Preferred Device #$%& '( " N-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Short Heatsink Tab Manufactured - Not Sheared * Specially Designed Leadframe for Maximum Power Dissipation http://onsemi.com 75 AMPERES 50 VOLTS RDS(on) = 9.5 m N-Channel D G S MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Symbol Value Unit Volts Drain-to-Source Voltage VDSS 50 Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 50 Gate-to-Source Voltage - Continuous VGS 20 Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 75 65 225 Amps Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (minimum footprint, FR-4 board) PD 125 1.0 2.5 Watts W/C Watts Operating and Storage Temperature Range TJ, Tstg - 55 to 150 C EAS 500 mJ Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 V, VGS = 10 V, Peak IL = 75 A, L = 0.177 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (minimum footprint, FR-4 board) Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds 4 D2PAK CASE 418B STYLE 2 2 1 3 MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain MTB75N05HD YWW 1 Gate C/W RJC RJA RJA 1.0 62.5 50 TL 260 2 Drain 3 Source MTB75N05HD = Device Code Y = Year WW = Work Week ORDERING INFORMATION C Device Package Shipping MTB75N05HD D2PAK 50 Units/Rail MTB75N05HDT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev.4 915 Publication Order Number: MTB75N05HD/D MTB75N05HD ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 50 - - 54.9 - - Vdc mV/C - - - - 10 100 - - 100 2.0 - - 6.3 4.0 - - 7.0 9.5 - - 0.63 - - 0.34 OFF CHARACTERISTICS (Cpk 2) (Note 2.) Drain-to-Source Breakdown Voltage (VGS = 0, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 50 V, VGS = 0) (VDS = 50 V, VGS = 0, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 1.5) (Note 2.) Static Drain-to-Source On-Resistance (Note 3.) (VGS = 10 Vdc, ID = 20 Adc) (Cpk 3.0) (Note 2.) VGS(th) RDS(on) Vdc mV/C m Drain-to-Source On-Voltage (VGS = 10 Vdc) (Note 3.) (ID = 75 A) (ID = 20 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS (Note 2.) gFS 15 - - mhos pF Input Capacitance Output Capacitance Transfer Capacitance V VGS = 0 0) (VDS = 25 V, 0, (Cpk 2 2.0) f = 1.0 MHz)) (C ( pk k 2.0)) (Cpk 2.0)) Vdc Ciss - 2600 3900 Coss - 1000 1300 Crss - 230 300 td(on) - 15 30 tr - 170 340 td(off) - 70 140 SWITCHING CHARACTERISTICS (Note 4.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 V, ID = 75 A, VGS = 10 V V, RG = 9.1 ) Fall Time Gate Charge (VDS = 40 V, ID = 75 A, VGS = 10 V) ns tf - 100 200 QT - 71 100 Q1 - 13 - Q2 - 33 - Q3 - 26 - 0.97 0.80 0.68 - 1.00 - Vdc - - trr - 57 - ns ta - 40 - tb - 17 - QRR - 0.17 - - - 3.5 4.5 - - - 7.5 - nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) (IS = 75 A, VGS = 0) (Cpk 10) (IS = 20 A, VGS = 0) (IS = 20 A, VGS = 0, TJ = 125C) Reverse Recovery Time (IS = 37.5 A, VGS = 0, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD C INTERNAL PACKAGE INDUCTANCE 1. 2. 3. 4. Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS Pulse Test: Pulse Width 300 s, Duty Cycle 2%. Reflects Typical Values. Cpk = Absolute Value of (SPEC - AVG) / 3 * SIGMA). For accurate measurements, good Kelvin contact required. Switching characteristics are independent of operating junction temperature. http://onsemi.com 916 nH MTB75N05HD TYPICAL ELECTRICAL CHARACTERISTICS (Note 5.) 6 9 , " #$ # 8 9 9 6 $ # $ $ # , " ?F$$ 6 #$ 4 6 4$ $ 6$ #$ # 4 $ 6 9 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics # , " #$ 8 9 F?$$ 6 # 6 9 8 # 6 7 : 8 6 9 , " #$ 8 " : $ 9 $ # 6 9 8 # Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage # " " 4:$ " $ , " #$ < 9 " 8 # 6 # 6 # : " 9 $ #$ F$ F#$ #$ $ :$ #$ $ $ $ # #$ 4 4$ 6 , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage 5. Pulse Tests: Pulse Width 250 s, Duty Cycle 2%. http://onsemi.com 917 6$ $ MTB75N05HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board-mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in a RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 8 *. : 9 " " , " #$ %!! $ 6 4 %!! (!! !! # (!! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 918 #$ # 9 @ 9 @# 4 , " #$ " :$ 6 # ' ! 6 @ , " #$ " :$ " 4$ " $ 8 'C '( 'CC ' # MTB75N05HD @4 :$ #$ $ @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 6 8 , " #$ : " 9 $ 6 4 # 4 %&' " 4 &! '(( '(( '+ ') # F F# F4 # 4 6 $ 9 : 8 7 F6 F# F F8 F9 F6 F# ' ! Figure 10. Diode Forward Voltage versus Current Figure 11. Reverse Recovery Time (trr) http://onsemi.com 919 # 6 9 8 MTB75N05HD SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For $ " # " #$ ! ! - , ! ! " :$ 6$ 6 4$ 4 #$ # $ $ #$ ('.. < Figure 12. Maximum Rated Forward Biased Safe Operating Area $ $ :$ #$ , , :$ Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature " $ # *0 $ # ' '# - - " '&'# F$ F6 F4 F# ' ! F Figure 14. Thermal Response http://onsemi.com 920 ,' " (' , , " &/ > - . / / ' ,*0 " *0 ,' 5 5 MTB75N05HD / / 4 RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils #$ # $ $ #$ $ :$ #$ = Figure 15. D2PAK Power Derating Curve http://onsemi.com 921 $ ". Preferred Device #$%& '( " N-Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Short Heatsink Tab Manufactured - Not Sheared * Specially Designed Leadframe for Maximum Power Dissipation http://onsemi.com 75 AMPERES 60 VOLTS RDS(on) = 10 m N-Channel D G S MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 30 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 75 50 225 Adc MARKING DIAGRAM & PIN ASSIGNMENT Apk 4 Drain Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C (Note NO TAG) PD 125 1.0 2.5 Watts W/C Watts Rating Operating and Storage Temperature Range 4 D2PAK CASE 418B STYLE 2 2 1 3 T75N06HD YWW C - 55 to 150 Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 75 Apk, L = 0.177 mH, RG = 25 ) EAS 500 mJ Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note NO TAG) RJC RJA RJA 1.0 62.5 50 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 260 C 1 Gate 2 Drain 3 Source T75N06HD = Device Code Y = Year WW = Work Week ORDERING INFORMATION 1. When surface mounted to an FR4 board using the minimum recommended pad size. Device Package Shipping MTB75N06HD D2PAK 50 Units/Rail MTB75N06HDT4 D2PAK 800/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev.2 922 Publication Order Number: MTB75N06HD/D MTB75N06HD ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - 68 60.4 - - - - - - 10 100 - 5.0 100 2.0 - 3.0 8.38 4.0 - - 8.3 10 - - 0.7 0.53 0.9 0.8 gFS 15 32 - mhos Ciss - 2800 3920 pF Coss - 928 1300 Crss - 180 252 td(on) - 18 26 tr - 218 306 td(off) - 67 94 tf - 125 175 QT - 71 100 Q1 - 16.3 - Q2 - 31 - Q3 - 29.4 - - - 0.97 0.88 1.1 - trr - 56 - ta - 44 - tb - 12 - QRR - 0.103 - - 3.5 - - 7.5 - OFF CHARACTERISTICS (Cpk 2.0) (Note 4.) Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 V) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) (Cpk 5.0) (Note 4.) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 37.5 Adc) (Cpk 2.0) (Note 4.) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 75 Adc) (ID = 37.5 Adc, TJ = 125C) VGS(th) Vdc RDS(on) m VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 37.5 Adc) mV/C Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS = 30 Vdc, ID = 75 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (VDS = 48 Vdc, ID = 75 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 75 Adc, VGS = 0 Vdc) (IS = 75 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 75 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 923 nH nH MTB75N06HD TYPICAL ELECTRICAL CHARACTERISTICS : :$ 9 $ #$ $ $ $ #$ #$ # , " ?$$ # 4 6 $ 9 : Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics , " #$ " 6 , " # #$ 8 ?$$ 9 6 :$ $ 9 $ #$ :$ #$ $ # 8 , " #$ " 7 $ 8 : 9 #$ $ :$ #$ $ Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 7 " " " 4:$ , " #$ 9 < 7 #$ #$ $ 8 " , " #$ $ 4 #$ : F$ F#$ #$ $ :$ #$ $ # 4 6 $ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 924 9 MTB75N06HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) : *. 9 $ " " , " #$ %!! 6 4 %!! (!! # !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 925 MTB75N06HD $ 8 @ 6 @# 9 4 6 # @4 # " :$ , " #$ # 4 6 $ 9 : 8 ' ! 9 @ # " 4 " :$ " , " #$ '( 'C 'CC ' @ 2 ! Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by :$ " , " #$ $ #$ $ $8 99 :6 8# 7 78 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 926 MTB75N06HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. " # " #$ ! ! ! ! - , The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For $ " :$ 4:$ #$ #$ #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 927 MTB75N06HD " $ # *0 $ ,' " (' , - . / / ' ,*0 " *0 ,' # ' '# - - " '&'# $ 6 4 # ' ! 5 5 Figure 14. Thermal Response 4 / / ('.. < TYPICAL ELECTRICAL CHARACTERISTICS %&' '(( ') '+ #$ '* #$ # $ $ #$ RJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils $ :$ #$ = Figure 16. D2PAK Power Derating Curve Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 928 $ MTB75N06HD INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 44 848 8 #4# 6# 99 #6 979 6 9 # 4$ 94 :# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 2.5 Watts 50C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 17. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows. , , = &/ : =)( )'1(%)E " 9#$ &. 6 # A **1( 9 " #$ #$ /)''! $ 4$ /)''! 6 $ /)''! 4 # # 6 9 8 @ # 6 Figure 17. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com 929 9 MTB75N06HD Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 18 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 18. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 930 MTB75N06HD TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 19 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 19. Typical Solder Heating Profile http://onsemi.com 931 ! #$%& '( ! N-Channel DPAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters, and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode Is Characterized for Use In Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 20 AMPERES 30 VOLTS RDS(on) = 22 m N-Channel D G S MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction-to-Ambient Junction-to-Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 5.0 seconds Symbol Value Unit VDSS VDGR 30 Vdc 30 Vdc VGS VGSM ID ID IDM PD 20 20 Vdc Vpk 20 16 60 Adc 74 0.592 1.75 Watts W/C Watts TJ, Tstg - 55 to 150 C EAS 200 mJ RJC RJA RJA TL 1.67 100 71.4 4 Apk Y WW T = Year = Work Week = MOSFET 4 Drain C/W C 260 1 Gate 932 2 Drain 3 Source ORDERING INFORMATION Device This document contains information on a new product. Specifications and information herein are subject to change without notice. November, 2000 - Rev. 1 1 2 3 YWW T 1302 CASE 369A DPAK STYLE 2 PIN ASSIGNMENT 1. When surface mounted to an FR4 board using the minimum recommended pad size. Semiconductor Components Industries, LLC, 2000 MARKING DIAGRAM Package Shipping MTD1302 DPAK 75 Units/Rail MTD1302-1 DPAK 75 Units/Rail MTD1302T4 DPAK 2500 Tape & Reel Publication Order Number: MTD1302/D MTD1302 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 30 - - - - - - 10 100 - - 100 1.0 1.5 2.0 - - 0.019 0.026 0.022 0.029 - - 0.38 - 0.5 0.33 10 16 - Ciss - 755 1162 Coss - 370 518 Crss - 102 204 td(on) - 7.2 15 Unit OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 10 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 10 Adc) Vdc Ohms Vdc gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (VDS = 24 Vdc, ID = 20 Adc, VGS = 5.0 Vdc) Gate Charge (VDS = 24 Vdc, ID = 20 Adc, VGS = 10 Vdc) tr - 52 104 td(off) - 45 90 tf - 73 146 QT - 14.5 21.8 Q1 - 2.2 - Q2 - 8.8 - Q3 - 6.8 - QT - 27 40.5 Q1 - 2.2 - Q2 - 10 - Q3 - 7.2 - - - 0.83 0.79 1.1 - trr - 38 - ta - 19 - tb - 20 - QRR - 36 - ns nC nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 933 VSD Vdc ns C MTD1302 TYPICAL ELECTRICAL CHARACTERISTICS 4$ 4 $ 6 6 4 , " #$ #$ # $ " 4 $ #$ # $ , " #$ ?$$ 6 # 9 8 # 6 9 8 # $ #$ ?$$ # $ 4 #$ 4$ 6 , " 4$ 6 6$ $ , " #$ 4$ 4 " 6$ #$ # $ $ $ # 4 #$ 4$ 6 Figure 4. On-Resistance versus Drain Current and Gate Voltage 4 " # " 4 6 Figure 3. On-Resistance versus Drain Current and Temperature < " #$ Figure 2. Transfer Characteristics 4 # # Figure 1. On-Region Characteristics #$ $ $ #$ #$ $ :$ #$ $ , " #$ #$ $ $ # #$ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 934 4 MTD1302 POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) #$ %!! *. # $ (!! %!! $ !! " " $ $ (!! $ # Figure 7. Capacitance Variation http://onsemi.com 935 #$ 6 8 # $ @ # 8 7 9 6 # @ @# 9 " # , " #$ @4 4 # 6 9 8 # 6 9 8 # ## #6 #9 #8 4 ' ! MTD1302 " $ " # " , " #$ 'C '( 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # 8 , " #$ 9 6 # 8 9 6 # 6 6$ $ $$ 9 9$ : :$ 8 8$ 7 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 936 MTD1302 '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For # " # " #$ - , m! ! ! " # $ $ #$ $ :$ #$ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 937 $ ('.. < MTD1302 " $ # *0 $ # ' '# - - " '&'# ' ! Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 938 ,' " (' , - . / / ' ,*0 " *0 ,' MTD1302 INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 9$ 67 #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 1.75 Watts 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ :$ /)''! 8 " #$ 9 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( $ /)''! # 6 9 @ 8 Figure 16. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 939 MTD1302 Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 940 MTD1302 TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 941 Preferred Device #$%& '( N-Channel DPAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 15 AMPERES 60 VOLTS RDS(on) = 120 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-Source Voltage - Continuous - Single Pulse (tp 50 ms) VGS VGSM 20 25 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 15 8.7 45 Adc Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size PD 55 0.36 2.1 Watts W/C Watts TJ, Tstg -55 to 175 C EAS 113 mJ Rating Drain-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient, when mounted to minimum recommended pad size Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds G S MARKING DIAGRAM Apk 4 YWW T 15N06V CASE 369A DPAK STYLE 2 1 2 3 Y WW T = Year = Work Week = MOSFET PIN ASSIGNMENT 4 Drain C/W RJC RJA RJA 2.73 100 71.4 TL 260 C 1 Gate 2 Drain 3 Source ORDERING INFORMATION Device Package Shipping MTD15N06V DPAK 75 Units/Rail MTD15N06V1 DPAK 75 Units/Rail MTD15N06VT4 DPAK 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 942 Publication Order Number: MTD15N06V/D MTD15N06V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 67 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.7 5.0 4.0 - Vdc mV/C - 0.08 0.12 Ohm - - 2.0 - 2.2 1.9 gFS 4.0 6.2 - mhos Ciss - 469 660 pF Coss - 148 200 Crss - 35 60 td(on) - 7.6 20 tr - 51 100 td(off) - 18 40 tf - 33 70 QT - 14.4 20 Q1 - 2.8 - Q2 - 6.4 - Q3 - 6.1 - - - 1.05 1.5 1.6 - trr - 59.3 - ta - 46 - tb - 13.3 - QRR - 0.165 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 4.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 7.5 - nH OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 7.5 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 15 Adc) (ID = 7.5 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 30 Vdc, ID = 15 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 15 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 15 Adc, VGS = 0 Vdc) (IS = 15 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (S Figure (See Fi 14) Adc VGS = 0 Vdc, Vdc (IS = 15 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 943 MTD15N06V TYPICAL ELECTRICAL CHARACTERISTICS #$ 4 8 " 7 , " #$C : # $ 9 $ $ # # 6 4 #$ #$C , " F$$C # $ $ : # 9 8 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics , " C #$C F$$C $ $ #$ $ # 4 4 , " #$ " 7 $ : $ $ $ # #$ Figure 4. On-Resistance versus Drain Current and Gate Voltage # " " " :$ 9 # 8 , " #$C , , 4 # 6 $ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage #$ #$ $ :$ 4 Figure 3. On-Resistance versus Drain Current and Temperature < 6 " 6 $ C $ 9 $ 4 #$ $ :$ http://onsemi.com 944 9 MTD15N06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) $ " *. # " , " #$C %!! 7 9 %!! (!! 4 !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 945 @ $ 8 @# @ 9 6 4 6 " $ , " #$ # # @4 4 9 7 # $ ' ! 9 # MTD15N06V " 4 " $ " , " #$ '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS $ # " , " #$ 7 9 4 $ : 7 4 $ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 946 MTD15N06V SAFE OPERATING AREA # " " #$ - , ! ! ! ! 8 9 6 # " $ #$ $ :$ #$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area :$ Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' $ '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 947 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MTD15N06V INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection 9$ 67 interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 175C - 25C = 2.1 Watts 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.1 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ :$ /)''! 8 " #$ 9 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( $ /)''! # 6 9 @ 8 Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 948 MTD15N06V Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 16. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 949 MTD15N06V TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 17. Typical Solder Heating Profile http://onsemi.com 950 #$%& '( N-Channel DPAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 15 AMPERES 60 VOLTS RDS(on) = 85 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 15 25 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 15 12 53 Adc Total Power Dissipation Derate above 25C Total Power Dissipation @ 25C (Note 1.) PD 60 0.4 2.1 Watts W/C Watts TJ, Tstg -55 to 175 C EAS 113 mJ RJC RJA RJA TL 2.5 100 71.4 Rating Drain-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds G S MARKING DIAGRAM Apk 4 YWW T 15N06VL CASE 369A DPAK STYLE 2 1 2 3 Y WW T = Year = Work Week = MOSFET PIN ASSIGNMENT C/W 4 Drain C 260 1. When surface mounted to an FR4 board using the minimum recommended pad size. 1 Gate 2 Drain 3 Source ORDERING INFORMATION Device Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 951 Package Shipping MTD15N06VL DPAK 75 Units/Rail MTD15N06VL1 DPAK 75 Units/Rail MTD15N06VLT4 DPAK 2500 Tape & Reel Publication Order Number: MTD15N06VL/D MTD15N06VL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 68 - - - - - - 10 100 - - 100 1.0 - 1.5 4.0 2.0 - - 0.075 0.085 - - - - 1.5 1.3 gFS 8.0 10 - mhos Ciss - 570 880 pF Coss - 180 380 Crss - 45 110 td(on) - 11 50 tr - 150 210 td(off) - 27 160 OFF CHARACTERISTICS (Cpk 2.0) (Note 4.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) (Cpk 2.0) (Note 4.) Static Drain-to-Source On-Resistance (VGS = 5.0 Vdc, ID = 7.5 Adc) (Cpk 2.0) (Note 4.) Drain-to-Source On-Voltage (VGS = 5.0 Vdc, ID = 15 Adc) (VGS = 5.0 Vdc, ID = 7.5 Adc, TJ = 150C) Vdc RDS(on) Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance mV/C Ohm VDS(on) Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc) DYNAMIC CHARACTERISTICS Output Capacitance VGS(th) Vdc SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time (VDD = 30 Vdc, ID = 15 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 15 Adc, VGS = 5.0 Vdc) tf - 70 140 QT - 12 20 Q1 - 3.0 - Q2 - 7.0 - Q3 - 11 - - - 0.96 0.85 1.6 - trr - 63 - ta - 42 - tb - 21 - QRR - 0.140 - - - 3.5 4.5 - - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) (IS = 15 Adc, VGS = 0 Vdc) (IS = 15 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 15 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 952 nH nH MTD15N06VL TYPICAL ELECTRICAL CHARACTERISTICS 7 " , " #$C 6$ 8 $ : 6 4$ $ 4 #$ # $ # 4 6 $ 9 : 7 8 6 C 4$ 4 #$ # $ #$C 8 $$C 9 6 # $ $ #$ # 4 4$ 9 $ 6 9 : 8 7 6$ $ , " #$C 6 # " $ 8 9 6 # Figure 3. On-Resistance versus Drain Current and Temperature $ $ #$ # 4 4$ 6 Figure 4. On-Resistance versus Drain Current and Gate Voltage " $ " :$ " , " #$ 9 < 4 Figure 2. Transfer Characteristics # 8 # Figure 1. On-Region Characteristics , " C # " $ 6 #$C , " $$C $ $ $ 6$ 9 $ 6 # 8 9 6 # $ #$ #$ $ :$ #$ , , $ :$ $ $ # #$ 4 4$ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 953 6 6$ MTD15N06VL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) ## " # %!! " , " #$C *. 8 9 6 # (!! 8 %!! 9 6 !! # (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 954 4 @ 7 8 #: #6 : 9 @ $ # 8 @# $ 6 # 4 7 # @4 $ , " #$ " $ $ # #$ 4 9 4 4$ ' ! MTD15N06VL , " #$ " $ " 4 " $ '( 'C 'CC ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS $ 6 , " #$ 4 " # 7 8 : 9 $ 6 4 # $ $$ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 955 MTD15N06VL " $ " #$ - , SAFE OPERATING AREA ! ! ! ! # " $ 7 8 : 9 $ 6 4 # #$ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 956 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MTD15N06VL INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection 9$ 67 interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 175C - 25C = 2.1 Watts 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.1 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ :$ /)''! 8 " #$ 9 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( $ /)''! # 6 9 @ 8 Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 957 MTD15N06VL SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CC CCC CCC CCC CC CCCCCC CC CCC CCCCCC CCC Figure 16. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 958 MTD15N06VL TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 17. Typical Solder Heating Profile http://onsemi.com 959 !. Preferred Device #$%& '( ! * %+% N-Channel DPAK This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 20 AMPERES 30 VOLTS RDS(on) = 35 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Symbol Value Unit Drain-Source Voltage VDSS 30 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 30 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 15 20 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 20 16 60 Adc Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C, when mounted with the minimum recommended pad size PD 74 0.6 1.75 Watts W/C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient, when mounted with the minimum recommended pad size Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Apk S MARKING DIAGRAM 4 YWW T 20N03HL CASE 369A DPAK STYLE 2 1 2 3 20N03HL Y WW T = Device Code = Year = Work Week = MOSFET PIN ASSIGNMENT TJ, Tstg -55 to 150 C EAS 200 mJ RJC RJA RJA 1.67 100 71.4 TL 260 4 Drain 1 Gate C/W 2 Drain 3 Source ORDERING INFORMATION C Device Package Shipping MTD20N03HDL DPAK 75 Units/Rail MTD20N03HDL1 DPAK 75 Units/Rail MTD20N03HDLT4 DPAK 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 960 Publication Order Number: MTD20N03HDL/D MTD20N03HDL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 30 - - 43 - - - - - - 10 100 - - 100 1.0 - 1.5 5.0 2.0 - - 0.034 0.030 0.040 0.035 - - 0.55 - 0.8 0.7 10 13 - Ciss - 880 1260 Coss - 300 420 Crss - 80 150 td(on) - 13 20 tr - 212 238 td(off) - 23 40 Unit OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) (Note 3.) Static Drain-to-Source On-Resistance (VGS = 4.0 Vdc, ID = 10 Adc) (VGS = 5.0 Vdc, ID = 10 Adc) (Cpk 2.0) (Note 3.) Drain-to-Source On-Voltage (VGS = 5.0 Vdc) (ID = 20 Adc) (ID = 10 Adc, TJ = 125C) VGS(th) Vdc RDS(on) Ohm VDS(on) Forward Transconductance (VDS = 5.0 Vdc, ID = 10 Adc) mV/C Vdc gFS mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 20 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 24 Vdc, ID = 20 Adc, VGS = 5.0 Vdc) tf - 84 140 QT - 13.4 18.9 Q1 - 3.0 - Q2 - 7.3 - Q3 - 6.0 - - - 0.95 0.87 1.1 - trr - 33 - ta - 23 - tb - 10 - QRR - 33 - - 4.5 - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Cpk 2.0) (Note 3.) (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 15) (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Cpk = Absolute Value of Spec (Spec-AVG/3.516 A). http://onsemi.com 961 nH nH MTD20N03HDL TYPICAL ELECTRICAL CHARACTERISTICS , " #$ " 6 6$ $ # 4$ 4 #$ # $# 6 9 8 # 6 9 8 # #$ , " F$$ 6 8 ## #9 4 46 48 6# E'! Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics " $ , " 49 #$ #8 F$$ < 4 E'! 66 # # 8 #6 9 4# 6 6 9 69 $ 49 , " #$ 4# " $ #8 #6 # 8 9 #6 4# *! *! Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 9 " $ " 8 4 6 6 " , " #$ # #$ 8 9 F$ 6 F#$ #$ $ :$ #$ $ 9 # 8 #6 , , E'! Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 962 4 MTD20N03HDL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) #8 " " , " #$ *. #6 # %!! 9 # (!! %!! 8 6 !! (!! $ $ $ # E'! Figure 7. Capacitance Variation http://onsemi.com 963 #$ #8 # #6 @ # 8 9 @ # @# 6 # 9 8 " # , " #$ 6 @4 # 6 9 8 # 6 ' ! 6 MTD20N03HDL " $ " # " $ , " #$ '( 'C 'CC ' @ 2 ! Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # 9 " , " #$ # 8 6 $ $$ 9 9$ : :$ 8 8$ 7 7$ E'! Figure 10. Diode Forward Voltage versus Current http://onsemi.com 964 MTD20N03HDL %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For " # " #$ - , ! ! ! # " # 9 # 8 6 #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 965 MTD20N03HDL ('.. < TYPICAL ELECTRICAL CHARACTERISTICS " $ # *0 $ ,' " (' , - . / / ' ,*0 " *0 ,' # ' '# - - " '&'# $ 6 4 # 5 ' ! Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 966 5 MTD20N03HDL INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 9$ 67 #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 1.75 Watts 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ :$ /)''! 8 " #$ 9 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( $ /)''! # 6 9 @ 8 Figure 16. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 967 MTD20N03HDL Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 968 MTD20N03HDL TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 969 . Preferred Device #$%& '( N-Channel DPAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 20 AMPERES 60 VOLTS RDS(on) = 45 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Symbol Value Unit Drain-Source Voltage VDSS 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 30 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 20 16 60 Adc Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size PD 40 0.32 1.75 Watts W/C Watts Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient, when mounted with the minimum recommended pad size Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds S MARKING DIAGRAM 4 YWW T 20N06HD CASE 369A DPAK STYLE 2 1 2 3 Apk Y WW T = Year = Work Week = MOSFET PIN ASSIGNMENT TJ, Tstg -55 to 150 C EAS 60 mJ 4 Drain 1 Gate C/W RJC RJA RJA 3.13 100 71.4 3 Source ORDERING INFORMATION Device TL 2 Drain C 260 Package Shipping MTD20N06HD DPAK 75 Units/Rail MTD20N06HD1 DPAK 75 Units/Rail MTD20N06HDT4 DPAK 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 970 Publication Order Number: MTD20N06HD/D MTD20N06HD ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 60 - - 54 - - - - - - 10 100 - - 100 2.0 - - 7.0 4.0 - - 0.035 0.045 - - - - 1.2 1.1 5.0 6.0 - Ciss - 607 840 Coss - 218 290 Crss - 55 110 td(on) - 9.2 18 tr - 61.2 122 td(off) - 19 38 tf - 36 72 QT - 17 24 Q1 - 3.4 - Q2 - 7.75 - Q3 - 7.46 - - - 0.95 0.88 1.0 - trr - 35.7 - ta - 24 - tb - 11.7 - QRR - 0.055 - - 4.5 - - 7.5 - Unit OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) (Note 3.) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 10 Adc) (Cpk 2.0) (Note 3.) Drain-to-Source On-Voltage (VGS = 10 Vdc) (ID = 20 Adc) (ID = 10 Adc, TJ = 125C) VGS(th) Vdc RDS(on) Ohm VDS(on) Forward Transconductance (VDS = 4.0 Vdc, ID = 10 Adc) mV/C Vdc gFS mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 30 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (S Figure (See Fi 7) (VDS = 48 Vdc, ID = 20 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Cpk 8.0) (Note 3.) (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 14) (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Cpk = Absolute Value of Spec (Spec-AVG/3.516 A). http://onsemi.com 971 nH nH MTD20N06HD TYPICAL ELECTRICAL CHARACTERISTICS #6 9 9 8 $ $# $ $ # #$ 4 4$ 6 6$ #$ , " F$$ # 4 6 $ 9 : Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics , " 6 49 #$ 4# #8 F$$ #6 # 4 6 , " #$ 48 " 49 46 4# $ 4 #8 # 4 *! Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 9 6 " " # 8 9 F$ F#$ #$ $ :$ #$ , , Figure 5. On-Resistance Variation with Temperature http://onsemi.com 972 8 6 *! < E'! 66 # # E'! " 68 4 $ , " #$ : 8 4# 6 7 " 6 $ 6 MTD20N06HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 9 *. 6 # " , " #$ " %!! 8 (!! %!! 9 6 !! # (!! $ $ $ # E'! Figure 6. Capacitance Variation http://onsemi.com 973 #$ 9 @ $ 8 @ 6 @# 4 9 " # , " #$ 6 # @4 # 6 # 9 8 # 6 9 8 " 4 " # " , " #$ ' ! # MTD20N06HD 'C 'CC '( ' @ 2 ! Figure 7. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 8. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 10. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # " , " #$ 8 9 6 # 8 9 6 # $ $8 :6 99 8# 7 78 E'! Figure 9. Diode Forward Voltage versus Current http://onsemi.com 974 MTD20N06HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 10. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. " # " #$ - , The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For ! ! ! ! 9 6 4 # " # $ #$ $ :$ #$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 975 MTD20N06HD ('.. < TYPICAL ELECTRICAL CHARACTERISTICS " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 976 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MTD20N06HD INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 9$ 67 #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 1.75 Watts 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ :$ /)''! 8 " #$ 9 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( $ /)''! # 6 9 @ 8 Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 977 MTD20N06HD Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 16. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 978 MTD20N06HD TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 17. Typical Solder Heating Profile http://onsemi.com 979 . Preferred Device #$%& '( * %+% N-Channel DPAK This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low-voltage, high-speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits, and inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 20 AMPERES 60 VOLTS RDS(on) = 45 m N-Channel D G S MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Symbol Value Unit Drain-Source Voltage VDSS 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 15 20 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 20 12 60 Adc Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C (Note 1.) PD 40 0.32 1.75 Watts W/C Watts -55 to 150 C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 20 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds TJ, Tstg Apk EAS MARKING DIAGRAM 4 YWW T 20N06HL CASE 369A DPAK STYLE 2 1 2 3 Y WW T = Year = Work Week = MOSFET PIN ASSIGNMENT 4 Drain mJ 200 1 Gate 2 Drain 3 Source C/W RJC RJA RJA 3.13 100 71.4 TL 260 ORDERING INFORMATION C 1. When surface mounted to an FR-4 board using the minimum recommended pad size. Device Package Shipping MTD20N06HDL DPAK 75 Units/Rail MTD20N06HDL1 DPAK 75 Units/Rail MTD20N06HDLT4 DPAK 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 980 Publication Order Number: MTD20N06HDL/D MTD20N06HDL ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 25 - - - - - - 10 100 - - 100 1.0 - 1.5 6.0 2.0 - - - 0.045 0.037 0.070 0.045 - - 0.76 - 1.2 1.1 gFS 6.0 12 - mhos Ciss - 863 1232 pF Coss - 216 300 Crss - 53 73 td(on) - 11 15 tr - 151 190 td(off) - 34 35 tf - 75 98 QT - 14.6 22 Q1 - 3.25 - Q2 - 7.75 - Q3 - 7.0 - - - 0.95 0.88 1.1 - trr - 22 - ta - 12 - tb - 34 - QRR - 0.049 - - 4.5 - - 7.5 - OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 4.0 Vdc, ID = 10 Adc) (VGS = 5.0 Vdc, ID = 10 Adc) RDS(on) Drain-Source On-Voltage (VGS = 5.0 Vdc) (ID = 20 Adc) (ID = 10 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 4.0 Vdc, ID = 10 Adc) Vdc mV/C Ohm Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS = 30 Vdc, ID = 20 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (VDS = 48 Vdc, ID = 20 Adc, VGS = 5.0 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 20 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 981 nH nH MTD20N06HDL TYPICAL ELECTRICAL CHARACTERISTICS , " #$ 4 6 " 8 9 $ 6$ 6 6 4$ # 4 4 # # 9 6 8 # 9 6 8 #$ #$ $ # , " F$$ # , " $ 4 F$$ # # 4 6 $ 6 6$ , " #$ 6$ $ 6 4$ " 4 #$ # 4 6 *! *! Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 9 6 " $ " < " $ #$ 4$ Figure 2. Transfer Characteristics : 6 4 E'! Figure 1. On-Region Characteristics 9 #$ # " , " #$ #$ 8 9 F$ F#$ #$ $ :$ #$ $ , , # 4 6 $ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 982 9 MTD20N06HDL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 4 " " , " #$ *. #$ %!! # $ (!! %!! $ (!! $ $ !! $ # E'! Figure 7. Capacitance Variation http://onsemi.com 983 #$ 9 @ $ 8 6 4 9 @ @# " # , " #$ 6 # # @4 # 6 9 8 # 9 6 " 4 " # " $ , " #$ '( 'C ' ! # MTD20N06HDL 'CC ' @ 2 ! Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 10. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # " , " #$ 9 # 8 6 $ $$ 9 9$ : :$ 8 7 7$ E'! Figure 10. Diode Forward Voltage versus Current http://onsemi.com 984 MTD20N06HDL %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. " # " #$ - , The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For ! ! ! ! # " # $ $ #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 985 MTD20N06HDL ('.. < TYPICAL ELECTRICAL CHARACTERISTICS " $ # *0 $ # ' '# - - " '&'# ' ! Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 986 ,' " (' , - . / / ' ,*0 " *0 ,' MTD20N06HDL INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 9$ 67 #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 1.75 Watts 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ :$ /)''! 8 " #$ 9 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( $ /)''! # 6 9 @ 8 Figure 16. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 987 MTD20N06HDL Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 988 MTD20N06HDL TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 989 #!. Preferred Device #$%& '( ! * %+% P-Channel DPAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. http://onsemi.com 20 AMPERES 30 VOLTS RDS(on) = 99 m * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete * * P-Channel Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 30 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDSS VDGR 30 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tpv10 ms) VGS VGSM "15 "20 Vdc Vpk ID ID IDM PD 19 12 57 Adc 75 0.6 1.75 Watts W/C TJ, Tstg -55 to 150 C PIN ASSIGNMENT EAS 200 mJ 4 Drain RJC RJA RJA TL 1.67 100 71.4 Rating Drain-Source Voltage Drain Current - Continuous - Continuous @ 100C - Single Pulse (tpv10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 19 Apk, L = 1.1 mH, RG = 25 ) Thermal Resistance - Junction-to-Case - Junction-to-Ambient - Junction-to-Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Apk MARKING DIAGRAM 4 YWW T 20P03HL CASE 369A DPAK STYLE 2 1 2 3 20P03HL Y WW T = Device Code = Year = Work Week = MOSFET C/W 1 Gate C 260 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2 Drain 3 Source ORDERING INFORMATION Device Package Shipping MTD20P03HDL DPAK 75 Units/Rail MTD20P03HDL1 DPAK 75 Units/Rail MTD20P03HDLT4 DPAK 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 4 990 Publication Order Number: MTD20P03HDL/D MTD20P03HDL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - 15 - - - - - - 10 100 - - 100 1.0 - 1.5 4.0 2.0 - - 120 90 - 99 - - 0.94 - 2.2 1.9 gFS 5.0 6.0 - mhos Ciss - 770 1064 pF Coss - 360 504 Crss - 130 182 td(on) - 18 25.2 tr - 178 246.4 td(off) - 21 26.6 tf - 72 98 QT - 15 22.4 Q1 - 3.0 - Q2 - 11 - Q3 - 8.2 - - - 3.1 2.56 3.4 - trr - 78 - ta - 50 - tb - 28 - QRR - 0.209 - - 4.5 - - 7.5 - OFF CHARACTERISTICS (Cpk 2.0) (Note 4.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) (Note 4.) Static Drain-to-Source On-Resistance (VGS = 4.0 Vdc, ID = 10 Adc) (VGS = 5.0 Vdc, ID = 9.5 Adc) (Cpk 2.0) (Note 4.) Drain-to-Source On-Voltage (VGS = 5.0 Vdc) (ID = 19 Adc) (ID = 9.5 Adc, TJ = 125C) VGS(th) Vdc RDS(on) m VDS(on) Forward Transconductance (VDS = 8.0 Vdc, ID = 9.5 Adc) mV/C Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 19 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 1.3 ) Fall Time Gate Charge (S Figure Fi 8) (See (VDS = 24 Vdc, ID =19 19 Adc, VGS = 5.0 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Cpk 2.0) (Note 4.) (IS = 19 Adc, VGS = 0 Vdc) (IS = 19 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 15) (IS = 19 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Cpk = Absolute Value of Spec (Spec-AVG/3.516 A). http://onsemi.com 991 nH nH MTD20P03HDL TYPICAL ELECTRICAL CHARACTERISTICS " , " #$ 6 9 $ 8 4# 6 6$ #6 6 9 4$ 8 4 #$ # 4 6 $ #$ 4# #6 9 8 $ $ , " #$ 8 F$$ 6 8 # 9 # #6 #8 4# 49 6 9 4$ 4 6 6$ $ $$ 49 6 , " #$ 6 # " $ 8 9 6 8 # 9 # #6 #8 4# Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 4 # " $ " 9 < 6 #$ Figure 2. Transfer Characteristics " $ # # Figure 1. On-Region Characteristics 9 , " F$$ " , " #$ 7 8 F$ F#$ #$ $ :$ #$ $ 6 8 # 9 # #6 #8 , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 992 4# MTD20P03HDL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) #8 *. #6 # " , " #$ " %!! 9 # (!! %!! 8 !! 6 (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 993 4$ 9 @ 4 $ @# #$ @ 6 # 4 $ " 7 , " #$ # @4 # 6 9 8 # 6 $ 9 ' ! : MTD20P03HDL " $ " 7 " $ , " #$ '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # " , " #$ 9 # 8 6 4 : $ 7 #4 #: 4 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 994 MTD20P03HDL %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. " # " #$ - , The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For ! ! ! # " 7 9 # 8 6 #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 995 MTD20P03HDL ('.. < TYPICAL ELECTRICAL CHARACTERISTICS " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' ! Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 996 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MTD20P03HDL INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection 9$ 67 interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ " #$ 9 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( :$ /)''! 8 $ /)''! # = 1.75 Watts 6 9 @ 8 Figure 16. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 997 MTD20P03HDL Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCC CCC CCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 998 MTD20P03HDL TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 999 #. Preferred Device #$%& '( * %+% P-Channel DPAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low-voltage, high-speed switching applications in power supplies, converters and PWM motor controls, and other inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients. * Ultra Low RDS(on), High-Cell Density, HDTMOS * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Avalanche Energy Specified http://onsemi.com 20 AMPERES 60 VOLTS RDS(on) = 175 m P-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tpv10 ms) VGS VGSM "15 "20 Vdc Vpk ID ID IDM PD 15 9.0 45 Adc 72 0.58 1.75 Watts W/C Watts TJ, Tstg -55 to 150 C EAS 300 mJ RJC RJA RJA TL 1.73 100 71.4 Rating Drain-Source Voltage Drain Current - Continuous - Continuous @ 100C - Single Pulse (tpv10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 15 Apk, L = 2.7 mH, RG = 25 ) Thermal Resistance - Junction-to-Case - Junction-to-Ambient - Junction-to-Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds MARKING DIAGRAM 4 Apk YWW T 20P06HL CASE 369A DPAK STYLE 2 1 2 3 20P06HL Y WW T = Device Code = Year = Work Week = MOSFET PIN ASSIGNMENT 4 Drain C/W C 260 1. When surface mounted to an FR4 board using the minimum recommended pad size. 1 Gate 2 Drain 3 Source ORDERING INFORMATION Device Package Shipping MTD20P06HDL DPAK 75 Units/Rail MTD20P06HDLT4 DPAK 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 1000 Publication Order Number: MTD20P06HDL/D MTD20P06HDL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 81.3 - - - - - - 1.0 10 - - 100 1.0 - 1.7 3.9 2.0 - mV/C - 143 175 m - - 2.3 1.6 3.0 2.0 gFS 9.0 11 - mhos Ciss - 850 1190 pF Coss - 210 290 Crss - 66 130 td(on) - 19 38 tr - 175 350 td(off) - 41 82 tf - 68 136 QT - 20.6 29 Q1 - 3.7 - Q2 - 7.6 - Q3 - 8.4 - - - 2.5 1.9 3.0 - trr - 64 - ta - 50 - tb - 14 - QRR - 0.177 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 4.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 7.5 - nH OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 5.0 Vdc, ID = 7.5 Adc) RDS(on) Drain-Source On-Voltage (VGS = 5.0 Vdc) (ID = 15 Adc) (ID = 7.5 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 7.5 Adc) Vdc Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS = 30 Vdc, ID = 15 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (VDS = 48 Vdc, ID = 15 Adc, VGS = 5.0 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 15 Adc, VGS = 0 Vdc) (IS = 15 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 15 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1001 MTD20P06HDL TYPICAL ELECTRICAL CHARACTERISTICS " , " #$ 4 7 8 # : $ 9 $ $ 6 6 # 4 6 9 $ : 8 7 $ $ # 6 4 $ 9 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics #6 , " #$ 9 F$$ 8 $ $ #$ # 4 #:$ , " #$ #$ ##$ # :$ " $ $ #$ $ $ # #$ Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 9 " $ " :$ 4 " 6 < # " $ #$ , " F$$ 4# $ #$ #$ 4 # 8 9 , " #$ 6 # F$ F#$ #$ $ :$ #$ $ # 4 6 $ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1002 9 MTD20P06HDL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) #$ *. # %!! " , " #$ " $ (!! %!! $ !! (!! $ $ $ # E'! Figure 7. Capacitance Variation http://onsemi.com 1003 #$ $ @ 6$ $ 6 4$ 6 4 4 #$ @ @# " $ , " #$ # # $ @4 6 $ 8 # 9 # #6 " 4 " $ " $ , " #$ '( 'C ' ! 9 MTD20P06HDL 'CC ' @ 2 ! Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by $ " , " #$ # 7 9 4 $ :$ #$ $ :$ # ##$ #$ E'! Figure 10. Diode Forward Voltage versus Current http://onsemi.com 1004 MTD20P06HDL %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. " # " #$ ! ! ! - , The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For 4 " $ #6 8 # 9 #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 1005 MTD20P06HDL ('.. < TYPICAL ELECTRICAL CHARACTERISTICS " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' ! Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 1006 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MTD20P06HDL INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 9$ 67 #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ :$ /)''! 8 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( " #$ 9 $ /)''! # = 1.75 Watts 6 9 @ 8 Figure 16. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 1007 MTD20P06HDL Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCC CCC CCC Figure 17. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 1008 MTD20P06HDL TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 1009 ) #$%& '( P-Channel DPAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 12 AMPERES 60 VOLTS RDS(on) = 230 m P-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 20 25 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 12 8.0 42 Adc Total Power Dissipation Derate above 25C Total Power Dissipation @ 25C (Note 1.) PD 60 0.4 2.1 Watts W/C Watts TJ, Tstg -55 to 175 C EAS 216 mJ RJC RJA RJA TL 2.5 100 71.4 Rating Drain-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds MARKING DIAGRAM Apk 4 1 2 3 Y WW T = Year = Work Week = MOSFET PIN ASSIGNMENT C/W 260 YWW T 2955V CASE 369A DPAK STYLE 2 4 Drain C 1. When surface mounted to an FR4 board using the minimum recommended pad size. 1 Gate 2 Drain 3 Source ORDERING INFORMATION Device Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 4 1010 Package Shipping MTD2955V DPAK 75 Units/Rail MTD2955V1 DPAK 75 Units/Rail MTD2955VT4 DPAK 2500 Tape & Reel Publication Order Number: MTD2955V/D MTD2955V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 58 - - - - - - 10 100 - - 100 2.0 - 2.8 5.0 4.0 - - 0.185 0.230 - - - - 2.9 2.5 gFS 3.0 5.0 - mhos Ciss - 550 770 pF Coss - 200 280 Crss - 50 100 td(on) - 15 30 tr - 50 100 td(off) - 24 50 OFF CHARACTERISTICS (Cpk 2.0) (Note 4.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) (Note 4.) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 6.0 Adc) (Cpk 1.5) (Note 4.) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 12 Adc) (VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150C) Vdc RDS(on) Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance mV/C Ohm VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Output Capacitance VGS(th) Vdc SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time (VDD = 30 Vdc, ID = 12 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 12 Adc, VGS = 10 Vdc) tf - 39 80 QT - 19 30 Q1 - 4.0 - Q2 - 9.0 - Q3 - 7.0 - - - 1.8 1.5 3.0 - trr - 115 - ta - 90 - tb - 25 - QRR - 0.53 - - - 3.5 4.5 - - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 12 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1011 nH nH MTD2955V TYPICAL ELECTRICAL CHARACTERISTICS #6 7 8 " # : $ 9 $ , " #$C $ # 4 6 $ 9 : 8 7 C #$C 8 $ # 7 9 4 # 6 $ 9 : 8 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 7 # #6 #$ " 4$ , " #$C ##$ 4 " # , " C :$ #$ #$C # $ $ $ #$ F$$C :$ $ 4 9 7 $ 8 # # #6 $ Figure 3. On-Resistance versus Drain Current and Temperature # 8 9 9 4 7 8 # $ Figure 4. On-Resistance versus Drain Current and Gate Voltage " " " 9 6 < , " F$$C 4 6 # #$ # 8 9 , " #$C C 6 # F$ F#$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature # 4 6 $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1012 9 MTD2955V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 8 *. 9 6 # " " , " #$C %!! (!! 8 %!! 9 6 !! # (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1013 4 @ 7 8 @ #: #6 @# : # 9 8 $ $ 6 # 4 " # 7 , " #$ 9 # @4 # 6 9 8 # 6 9 8 4 # ' ! MTD2955V " 4 " # " , " #$ '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS # " , " #$ 7 8 : 9 $ 6 4 # $ : 7 4 $ : 7 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1014 MTD2955V SAFE OPERATING AREA ##$ " $ " #$ - , ! ! ! " # # :$ $ #$ :$ $ #$ #$ $ :$ #$ :$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1015 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MTD2955V INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 9$ 67 #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 175C - 25C = 2.1 Watts 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.1 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ :$ /)''! 8 " #$ 9 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( $ /)''! # 6 9 @ 8 Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 1016 MTD2955V Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 16. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 1017 MTD2955V TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 15. Typical Solder Heating Profile http://onsemi.com 1018 ! Preferred Device #$%& '( N-Channel DPAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 12 AMPERES 60 VOLTS RDS(on) = 150 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 20 25 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 12 7.3 37 Adc Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size PD 48 0.32 1.75 Watts W/C Watts TJ, Tstg -55 to 175 C EAS 72 mJ Rating Drain-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient, when mounted to minimum recommended pad size Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds G S MARKING DIAGRAM Apk 4 1 2 3 Y WW T YWW T 3055V CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET PIN ASSIGNMENT 4 Drain C/W RJC RJA RJA 3.13 100 71.4 TL 260 C 1 Gate 2 Drain 3 Source ORDERING INFORMATION Device Package Shipping MTD3055V DPAK 75 Units/Rail MTD3055V1 DPAK 75 Units/Rail MTD3055VT4 DPAK 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 1019 Publication Order Number: MTD3055V/D MTD3055V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 65 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.7 5.4 4.0 - Vdc mV/C - 0.10 0.15 Ohm - - 1.3 - 2.2 1.9 gFS 4.0 5.0 - mhos Ciss - 410 500 pF Coss - 130 180 Crss - 25 50 td(on) - 7.0 10 tr - 34 60 td(off) - 17 30 tf - 18 50 QT - 12.2 17 Q1 - 3.2 - Q2 - 5.2 - Q3 - 5.5 - - - 1.0 0.91 1.6 - trr - 56 - ta - 40 - tb - 16 - QRR - 0.128 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 4.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 7.5 - nH OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 6.0 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 12 Adc) (ID = 6.0 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 7.0 Vdc, ID = 6.0 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 30 Vdc, ID = 12 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 12 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (S Figure (See Fi 15) Adc VGS = 0 Vdc, Vdc (IS = 12 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1020 MTD3055V TYPICAL ELECTRICAL CHARACTERISTICS " 7 , " #$C # #6 8 #6 : 9 # 9 8 $ 6 4 # 4 6 9 # 8 6 $ 9 : 7 8 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics # , " C $ #$C $$C $ 6 8 # 9 # #6 $ , " #$C 6 4 # " $ 7 8 Figure 3. On-Resistance versus Drain Current and Temperature 6 8 9 # # #6 Figure 4. On-Resistance versus Drain Current and Gate Voltage 9 " " " 9 < 4 # " 6 C #$C #$ # $ , " F$$C 6 6 # , " #$C 8 9 F$ F#$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature # 4 6 $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1021 9 MTD3055V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) # " *. " , " #$C %!! 8 9 (!! %!! 6 !! # (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1022 @ $ @ 8 @# 6 9 4 6 # # " # , " #$ @4 # 4 6 $ 9 : 8 7 # 4 ' ! 9 # MTD3055V " 4 " # " , " #$ '( 'CC 'C ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS # " , " #$ 8 9 6 # $ $$ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1023 MTD3055V SAFE OPERATING AREA :$ ! " # " #$ - , ! ! ! " # $ #$ #$ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' $ '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1024 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MTD3055V INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 9$ 67 #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 175C - 25C = 2.1 Watts 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.1 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ :$ /)''! 8 " #$ 9 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( $ /)''! # 6 9 @ 8 Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 1025 MTD3055V Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 16. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 1026 MTD3055V TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 15. Typical Solder Heating Profile http://onsemi.com 1027 ! Preferred Device #$%& '( N-Channel DPAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 12 AMPERES 60 VOLTS RDS(on) = 180 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-Source Voltage - Continuous - Single Pulse (tp 50 ms) VGS VGSM 15 20 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 12 8.0 42 Adc Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size PD 48 0.32 1.75 Watts W/C Watts TJ, Tstg -55 to 175 C EAS 72 mJ Rating Drain-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient, when mounted to minimum recommended pad size Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds Apk G 4 S 4 1 2 3 12 CASE 369A DPAK (Bent Lead) STYLE 2 3 CASE 369 DPAK (Straight Lead) STYLE 2 MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain YWW T 3055VL1 YWW T 3055VL C/W RJC RJA RJA TL 1 Gate 3.13 100 71.4 260 C 2 Drain 3055VL Y WW T 3 Source 1 Gate = Device Code = Year = Work Week = MOSFET 3 Source 2 Drain ORDERING INFORMATION Device Package Shipping MTD3055VL DPAK 75 Units/Rail MTD3055VL1 DPAK (Straight Lead) 75 Units/Rail MTD3055VLT4 DPAK 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2001 March, 2001 - Rev. 4 1028 Publication Order Number: MTD3055VL/D MTD3055VL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 62 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 1.0 - 1.6 3.0 2.0 - Vdc mV/C - 0.12 0.18 Ohm - - 1.6 - 2.6 2.5 gFS 5.0 8.8 - mhos Ciss - 410 570 pF Coss - 114 160 Crss - 21 40 td(on) - 9.0 20 tr - 85 190 td(off) - 14 30 tf - 43 90 QT - 8.1 10 Q1 - 1.8 - Q2 - 4.2 - Q3 - 3.8 - - - 0.97 0.86 1.3 - trr - 55.7 - ta - 37 - tb - 18.7 - QRR - 0.116 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 3.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 7.5 - nH OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 5.0 Vdc, ID = 6.0 Adc) RDS(on) Drain-Source On-Voltage (VGS = 5.0 Vdc) (ID = 12 Adc) (ID = 6.0 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 8.0 Vdc, ID = 6.0 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 30 Vdc, ID = 12 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 12 Adc, VGS = 5 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (S Figure (See Fi 14) Adc VGS = 0 Vdc, Vdc (IS = 12 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1029 MTD3055VL TYPICAL ELECTRICAL CHARACTERISTICS #6 9 6$ 6 # 4$ 8 4 #$ 4# # 6 4 # 9 # 8 6 4 4$ 6$ 6 $$ $ Figure 2. Transfer Characteristics , " C 6 #$C F$$C 8 6 # 8 # 9 #6 #: ## : $ # " : 6 $ $ #$ $ :$ #$ $ 8 # 9 # #6 Figure 4. On-Resistance versus Drain Current and Gate Voltage " $ " 9 F#$ 9 , " #$C Figure 3. On-Resistance versus Drain Current and Temperature < #$ Figure 1. On-Region Characteristics # F$ C " $ # , " F$$C #$C #9 # # $ # 6 #6 $ " , " #$C :$ " , " #$C C , , 4 # 6 $ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1030 9 MTD3055VL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6 *. " " # , " #$C %!! 8 9 %!! (!! 6 !! # (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1031 9 @ $ 6 6 4 # @# @ # " # , " #$ @4 # 6 9 8 ' ! 9 MTD3055VL " 4 " # " $ , " #$ '( 'C 'CC ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS # " , " #$ 8 9 6 # $ $$ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1032 MTD3055VL SAFE OPERATING AREA :$ " $ " #$ - , ! ! ! ! " # $ #$ #$ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' $ '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1033 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MTD3055VL INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 9$ 67 #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 175C - 25C = 2.1 Watts 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.1 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ :$ /)''! 8 " #$ 9 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( $ /)''! # 6 9 @ 8 Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 1034 MTD3055VL Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 16. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 1035 MTD3055VL TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 17. Typical Solder Heating Profile http://onsemi.com 1036 !! #$%& '( , ! N-Channel DPAK This Power MOSFET is capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. These devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Characterized Over a Wide Range of Power Ratings * Ultralow RDS(on) Provides Higher Efficiency and Extends Battery Life in Portable Applications * Logic Level Gate Drive - Can Be Driven by Logic ICs * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified MAXIMUM RATINGS (TJ = 25C unless otherwise specified) Parameter Drain-to-Source Voltage Drain-to-Gate Voltage Gate-to-Source Voltage Gate-to-Source Operating Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, L = 20 mH, IL(pk) = 10 A, VDS = 30 Vdc) Symbol Value Unit VDSS VDGR VGS 30 Vdc 30 Vdc 20 Vdc 16 Vdc -55 to 150 C VGS TJ, Tstg EAS http://onsemi.com 18 AMPERES 30 VOLTS RDS(on) = 10 m N-Channel D G S MARKING DIAGRAM 4 1 2 3 Y WW T YWW T 3302 CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET PIN ASSIGNMENT 4 Drain mJ 1000 1 Gate 2 Drain 3 Source ORDERING INFORMATION Device Package Shipping MTD3302 DPAK 75 Units/Rail MTD3302T4 DPAK 2500 Tape & Reel This document contains information on a new product. Specifications and information herein are subject to change without notice. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 1037 Publication Order Number: MTD3302/D MTD3302 POWER RATINGS (TJ = 25C unless otherwise specified) Parameter Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 ms) Mounted on heat sink Tcase = 25C Total Power Dissipation @ TA = 25C Linear Derating Factor Thermal Resistance VGS = 10 Vdc - Junction-to-Case Steady State Continuous Source Current (Diode Conduction) Parameter Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 ms) Mounted on 1 inch square FR-4 or G10 board Total Power Dissipation @ TA = 25C Linear Derating Factor VGS = 10 Vdc Thermal Resistance t 10 seconds - Junction-to-Ambient Continuous Source Current (Diode Conduction) Parameter Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 ms) Mounted on 1 inch square FR-4 or G10 board Total Power Dissipation @ TA = 25C Linear Derating Factor Thermal Resistance VGS = 10 Vdc - Junction-to-Ambient Steady State Continuous Source Current (Diode Conduction) Parameter Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 ms) Mounted on minimum recommended FR-4 or G10 board Total Power Dissipation @ TA = 25C Linear Derating Factor Thermal Resistance VGS = 10 Vdc - Junction-to-Ambient Steady State Continuous Source Current (Diode Conduction) http://onsemi.com 1038 Symbol Value Unit ID ID IDM PD 30 30 90 Adc Adc Adc 96 769 Watts mW/C RJC 1.3 C/W IS 30 Adc Symbol Value Unit ID ID IDM PD 18.3 11.2 60 Adc Adc Adc 5.0 40 Watts mW/C RJA 25 C/W IS 6.4 Adc Symbol Value Unit ID ID IDM PD 11.2 8.6 40 Adc Adc Adc 1.9 15 Watts mW/C RJA 67 C/W IS 2.5 Adc Symbol Value Unit ID ID IDM PD 8.3 5.2 30 Adc Adc Adc 1.0 8.3 Watts mW/C RJA 120 C/W IS 1.4 Adc MTD3302 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise specified) Characteristic Symbol Min Typ Max Unit 30 - 33 23 - - - - 0.005 0.5 1.0 10 - 2 100 1.0 - 1.9 4.6 - - - - 8.9 13 10 16 gFS 12 19 - Mhos Ciss - 1760 - pF Coss - 610 - Crss - 185 - td(on) - 10 20 tr - 30 60 td(off) - 65 130 tf - 58 110 td(on) - 20 40 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) RDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) Vdc mV/C m DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) Fall Time Gate Charge (VDS = 15 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) tr - 86 170 td(off) - 44 80 tf - 48 90 QT - 47 60 Q1 - 4.8 - Q2 - 16.7 - Q3 - 11.2 - - - 0.87 0.72 1.1 - trr - 41 - ta - 21 - tb - 20 - QRR - 0.047 - ns ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) VSD (IS = 2.3 Adc, VGS = 0 Vdc) (IS = 2.3 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 2.3 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 1039 Vdc ns C MTD3302 TYPICAL ELECTRICAL CHARACTERISTICS " 9 $ 9 6$ 64 , " #$ 6 6 9 47 4 4: # 4$ 44 #$ $ :$ #$ 6 4 , " #$ # #$ 4 $ $ :$ # $$ # # 6 $ 9 : 8 6$ $ $$ 9 7 , " #$ 8 9 " 6$ 6 # 8 9 6 # 4 6 # Figure 3. On-Resistance versus Gate-To-Source Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage # $ 9 " " " $ $ ?$ 6 # < " $ , " #$ 4 4$ Figure 2. Transfer Characteristics 4 # 4 Figure 1. On-Region Characteristics #$ ?#$ #$ $ :$ #$ $ , " #$ #$ , , $ $ # #$ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1040 4 MTD3302 POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6$ %!! *. 6 4$ 4 #$ " , " #$ " (!! %!! # $ !! (!! $ $ $ $ # #$ 4 Figure 7. Capacitance Variation http://onsemi.com 1041 8 @ $ # 8 7 9 @ @# , " #$ " 4 6 @4 # 9 4 4 # $ 6 , " #$ " " #$ " ' ! # MTD3302 'CC 'C '( ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 4 " , " #$ #$ # $ $ $ $$ 9 9$ : :$ 8 8$ 7 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 1042 MTD3302 %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the - , m! ! " " #$ ! " 7 8 : 9 $ 6 4 # #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 1043 MTD3302 TYPICAL ELECTRICAL CHARACTERISTICS . '23)'.. - - " $ # $ # ' '# - - " '&'# ,' " (' , - . / / ' ,*0 " *0 ,' *0 $ 6 4 # ' !1! 5 5# 5 54 Figure 14. Thermal Response - Various Duty Cycles '23)'.. # 4 6 $ 3) 3) #4 #$9 :$4 #9 49# 486 77: 46 $# #$ #4 $: $ :6 4 79 8$6 6: :7 :$ 3 4#6 # 68: 9 879 6 696 :4 999 68# , # # 4 6 4 6 $ = '23) '23) $ '23 )!1 " #$ $ 4 6 # ' !1! 5 5 5# 54 Figure 15. Thermal Response - Various Mounting/Measurement Conditions # # @ . 6 = @ # < 9 / / $ %&' '(( ') $ '+ #$ '* ' !1! Figure 17. Diode Reverse Recovery Waveform Figure 16. Single Pulse Power http://onsemi.com 1044 MTD3302 INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 9$ 67 #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 1.75 Watts 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. Note that these values may vary depending on the device type. Consult the maximum ratings table on the data sheet to find the actual PD and RqJA values for a particular device. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 18. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ :$ /)''! 8 " #$ 9 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( $ /)''! # 6 9 @ 8 Figure 18. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 1045 MTD3302 Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 19. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 1046 MTD3302 TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 20 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 20. Typical Solder Heating Profile http://onsemi.com 1047 Preferred Device #$%& '( N-Channel DPAK This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage-blocking capability without degrading performance over time. In addition this advanced high voltage MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 4 AMPERES 200 VOLTS RDS(on) = 1.2 N-Channel D G S MARKING DIAGRAM MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 200 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 200 Vdc Gate-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 20 40 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 4.0 2.6 12 Adc Total Power Dissipation @ TC = 25C Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size PD 40 0.32 1.75 Watts W/C Watts TJ, Tstg -55 to 150 C EAS 80 mJ Rating Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 80 Vdc, VGS = 10 Vdc, IL = 4.0 Apk, L = 10 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient, when mounted to minimum recommended pad size Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds Apk C/W RJC RJA RJA 3.13 100 71.4 TL 260 4 1 2 3 4N20E Y WW T = Device Code = Year = Work Week = MOSFET PIN ASSIGNMENT 4 Drain 1 Gate 2 Drain 3 Source ORDERING INFORMATION Device C YWW T 4N20E CASE 369A DPAK STYLE 2 Package Shipping MTD4N20E DPAK 75 Units/Rail MTD4N20E1 DPAK 75 Units/Rail MTD4N20ET4 DPAK 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 1048 Publication Order Number: MTD4N20E/D MTD4N20E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 200 - - 263 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 3.0 7.0 4.0 - Vdc mV/C - 0.98 1.2 Ohm - - 3.5 - 5.8 5.0 gFS 1.5 2.1 - mhos Ciss - 311 430 pF Coss - 66 80 Crss - 11 20 td(on) - 10 17 tr - 4.0 26 td(off) - 15 29 tf - 6.0 18 QT - 9.2 14 Q1 - 2.4 - Q2 - 4.1 - Q3 - 5.6 - - - 0.92 0.82 - trr - 123 - ta - 82 - tb - 41 - QRR - 0.58 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 4.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 7.5 - nH OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 2.0 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 4.0 Adc) (ID = 2.0 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 100 Vdc, ID = 4.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 160 Vdc, ID = 4.0 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 4.0 Adc, VGS = 0 Vdc) (IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 14) 4 0 Adc, Adc VGS = 0 Vdc, Vdc (IS = 4.0 dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1049 MTD4N20E TYPICAL ELECTRICAL CHARACTERISTICS , " #$ 7 9 : $ 6 4 9 # $ # 6$ 6 9 8 # 6 4 # # 4 6 $ 9 : 8 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 4 #$ , " # $ #$ $ F$$ $ 4$ #$ 9 6 " 6 , " F$$ # 4 6 $ 9 : 8 #8 7 , " #$ #6 # 9 " # $ 8 6 # 4 6 $ 9 : 8 Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage #$ # " " 6 " , " #$ < : 8 : 8 " 8 $ #$ $ F$ F#$ #$ $ :$ #$ $ $ $ # , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1050 #$ MTD4N20E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) *. 8 " 9 6 " %!! (!! %!! # , " #$C !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1051 MTD4N20E 9 @ 6 6 # # @ 8 @# 8 9 9 " 6 , " #$ 6 # @4 # 6 9 8 6 # ' ! 8 9 8 " " 6 " , " #$ 'CC ' 'C '( @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 6 " , " #$ 4# #6 9 8 $ $$ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1052 MTD4N20E " # " #$ - , SAFE OPERATING AREA ! ! ! ! 8 9 6 # " 6F #$ $ :$ #$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area $ Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # $ $ *0 # ' '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1053 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MTD4N20E INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 9$ 67 #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 1.75 Watts 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ :$ /)''! 8 " #$ 9 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( $ /)''! # 6 9 @ 8 Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 1054 MTD4N20E Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 16. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 1055 MTD4N20E TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 17. Typical Solder Heating Profile http://onsemi.com 1056 # Preferred Device #$%& '( P-Channel DPAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 5 AMPERES 60 VOLTS RDS(on) = 450 m P-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 15 25 Vdc Vpk ID ID IDM PD 5 4 18 Adc 40 0.27 2.1 Watts W/C W/ C Watts -55 to 175 C 125 mJ Rating Drain-to-Source Voltage Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C 25 C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 5 Apk, L = 10 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds TJ, Tstg EAS MARKING DIAGRAM Apk 4 1 2 3 Y WW T YWW T 5P06V CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET PIN ASSIGNMENT 4 Drain C/W RJC RJA RJA TL 3.75 100 71.4 260 C 1 Gate 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2 Drain 3 Source ORDERING INFORMATION Device Package Shipping MTD5P06V DPAK 75 Units/Rail MTD5P06V1 DPAK 75 Units/Rail MTD5P06VT4 DPAK 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 1057 Publication Order Number: MTD5P06V/D MTD5P06V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 61.2 - - - - - - 10 100 - - 100 2.0 - 2.8 4.7 4.0 - mV/C - 0.34 0.45 Ohm - - - - 2.7 2.6 1.5 3.6 - Ciss - 367 510 Coss - 140 200 Crss - 29 60 td(on) - 11 20 tr - 26 50 td(off) - 17 30 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 2.5 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc, ID = 5 Adc) (VGS = 10 Vdc, ID = 2.5 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc) Vdc Vdc gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time (VDD = 30 Vdc, ID = 5 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 5 Adc, VGS = 10 Vdc) tf - 19 40 QT - 12 20 Q1 - 3.0 - Q2 - 5.0 - Q3 - 5.0 - - - 1.72 1.34 3.5 - trr - 97 - ta - 73 - tb - 24 - QRR - 0.42 - - 4.5 - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 5 Adc, VGS = 0 Vdc) (IS = 5 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 5 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1058 nH nH MTD5P06V TYPICAL ELECTRICAL CHARACTERISTICS " 8 8 7 : , " #$C 9 9 6 $ # 9 # 4 6 $ 9 : 8 $ 6 4 # # 6 $ 9 : Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics , " C 6 6 #$C 4$ 4 8 , " #$C " 4$ 6$ $ 4 #$ $$C #$ # 4 6 $ 9 : 8 7 # Figure 3. On-Resistance versus Drain Current and Temperature 8 9 # 4 6 $ : 9 8 7 Figure 4. On-Resistance versus Drain Current and Gate Voltage " " #$ 6 < 4 $ # 9 " $$ 100C : 7 #$C 8 6 , " $$C 7 # 8 9 " , " #$ 6 # $ #$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature $ # 4 6 Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1059 9 MTD5P06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) " %!! 7 , " #$C *. 8 : 9 (!! $ %!! 6 4 !! # (!! " $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1060 7 9 $6 @ 68 8 : @# @ 6# 9 49 $ 4 6 #6 4 8 # @4 # , " #$ " $ 6 9 8 # # 9 6 ' ! MTD5P06V , " #$ " $ " 4 " 'CC 'C '( ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS $ , " #$ " 6$ 6 4$ 4 #$ # $ $ # 6 9 8 # 6 9 8 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1061 MTD5P06V SAFE OPERATING AREA 6 " # " #$ - , ! ! ! " $ # 8 9 6 # #$ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1062 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MTD5P06V INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 9$ 67 #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 175C - 25C = 2.1 Watts 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.1 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ :$ /)''! 8 " #$ 9 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( $ /)''! # 6 9 @ 8 Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 1063 MTD5P06V Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 16. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 1064 MTD5P06V TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 17. Typical Solder Heating Profile http://onsemi.com 1065 Preferred Device #$%& '( N-Channel DPAK This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 6 AMPERES 200 VOLTS RDS(on) = 700 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 200 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 200 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 20 40 Vdc Vpk ID ID IDM 6.0 3.8 18 Adc PD 50 0.4 1.75 Watts W/C Watts Rating Drain Current - Continuous - Continuous @ 100C - Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 80 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient, when mounted to minimum recommended pad size Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds Apk S MARKING DIAGRAM 4 1 2 3 Y WW T YWW T 6N20E CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET PIN ASSIGNMENT TJ, Tstg -55 to 150 C EAS 54 mJ 4 Drain 1 Gate C/W RJC RJA RJA 2.50 100 71.4 TL 260 2 Drain 3 Source ORDERING INFORMATION Device C Package Shipping MTD6N20E DPAK 75 Units/Rail MTD6N20E1 DPAK 75 Units/Rail MTD6N20ET4 DPAK 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 1066 Publication Order Number: MTD6N20E/D MTD6N20E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 200 - - 689 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 3.0 7.1 4.0 - Vdc mV/C - 0.46 0.700 Ohm - - 2.9 - 5.0 4.4 gFS 1.5 - - mhos Ciss - 342 480 pF Coss - 92 130 Crss - 27 55 td(on) - 8.8 17.6 tr - 29 58 td(off) - 22 44 tf - 20 40.8 QT - 13.7 21 Q1 - 2.7 - Q2 - 7.1 - Q3 - 5.9 - - - 0.99 0.9 1.2 - trr - 138 - ta - 93 - tb - 45 - QRR - 0.74 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 4.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 7.5 - nH OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = ?20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 3.0 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 6.0 Adc) (ID = 3.0 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 100 Vdc, ID = 6.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 160 Vdc, ID = 6.0 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 6.0 Adc, VGS = 0 Vdc) (IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 14) 6 0 Adc, Adc VGS = 0 Vdc, Vdc (IS = 6.0 dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1067 MTD6N20E TYPICAL ELECTRICAL CHARACTERISTICS 8 : 8 9 6 9 # $ # 4 6 $ 9 : 8 9 6 # 4 6 $ 9 : 8 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics " , " 8 9 #$ 6 ?$$ # #$ 8 7 # , " ?$$ # # 6 9 8 # # 7 < " , " #$ 7 : , " #$ 9$ 9 $$ " $ 6$ 6 $ # 6 9 8 # Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage #$ # " " 4 # $ " , " #$ #$ $ $ #$ #$ $ :$ #$ $ $ $ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1068 # MTD6N20E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 7 " , " #$ %!! :$ *. " 9 6$ %!! (!! 4 !! $ (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1069 # 7 @ @ 8 :$ @# 9 9 6$ 6 4 " 9 , " #$ # @4 # 6 9 8 @ # $ 6 ' ! MTD6N20E " " 9 " , " #$ '( 'CC 'C ' Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 9 " , " #$ $ 6 4 # $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1070 MTD6N20E SAFE OPERATING AREA 9 " # " #$ - , ! ! ! ! " 9 $ 6 4 # #$ Figure 11. Maximum Rated Forward Biased Safe Operating Area $ :$ #$ , , $ Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # $ *0 # $ ' '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1071 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MTD6N20E INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 9$ 67 #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 1.75 Watts 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ :$ /)''! 8 " #$ 9 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( $ /)''! # 6 9 @ 8 Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 1072 MTD6N20E Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 16. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 1073 MTD6N20E TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 17. Typical Solder Heating Profile http://onsemi.com 1074 # Preferred Device #$%& '( P-Channel DPAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 6 AMPERES 100 VOLTS RDS(on) = 660 m P-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 100 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 100 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 15 20 Vdc Vpk ID ID IDM 6.0 3.9 18 Adc PD 50 0.4 1.75 Watts W/C Watts Rating Drain Current - Continuous - Continuous @ 100C - Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 10 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient, when mounted to minimum recommended pad size Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds Apk MARKING DIAGRAM 4 1 2 3 Y WW T YWW T 6P10E CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET PIN ASSIGNMENT TJ, Tstg -55 to 150 C EAS 180 mJ 4 Drain 1 Gate C/W RJC RJA RJA 2.50 100 71.4 TL 260 2 Drain 3 Source ORDERING INFORMATION Device C Package Shipping MTD6P10E DPAK 75 Units/Rail MTD6P10ET4 DPAK 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 1075 Publication Order Number: MTD6P10E/D MTD6P10E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 100 - - 124 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.9 4.0 4.0 - Vdc mV/C - 0.56 0.66 Ohm - - 3.6 - 4.8 4.2 gFS 1.5 3.0 - mhos Ciss - 550 840 pF Coss - 154 240 Crss - 27 56 td(on) - 12 25 tr - 29 60 td(off) - 18 40 tf - 9 20 QT - 15.3 22 Q1 - 4.1 - Q2 - 7.1 - Q3 - 6.8 - - - 1.8 1.5 5.0 - trr - 112 - ta - 92 - tb - 20 - QRR - 0.603 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 4.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 7.5 - nH OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 3.0 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 6.0 Adc) (ID = 3.0 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 50 Vdc, ID = 6.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 80 Vdc, ID = 6.0 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 6.0 Adc, VGS = 0 Vdc) (IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 14) 6 0 Adc, Adc VGS = 0 Vdc, Vdc (IS = 6.0 dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1076 MTD6P10E TYPICAL ELECTRICAL CHARACTERISTICS # " , " #$ 8 8 9 : 6 9 # # 6 9 8 # 6 9 8 9 6 # 4 6 $ 9 : 8 7 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics " , " 7 8 : #$ 9 $ ?$$ 6 4 8 # 4 # #$ # $ , " ?$$ # 6 9 8 # , " #$ 7 8 : " 9 $ $ 6 # 6 9 8 Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 9 # " " 4 " 6 < 7 # # 8 , " #$ 9 6 $ #$ #$ $ :$ #$ $ # 8 9 6 # , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1077 MTD6P10E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 9 *. " " 6 , " #$ %!! # 8 (!! 9 %!! 6 # !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1078 # 7 @ @ :$ @# 8 9 9 6$ 6 # 4 " 9 , " #$ @4 # 6 9 8 @ # 6 $ 9 ' ! MTD6P10E " $ " 9 " , " #$ '( 'CC ' 'C Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 9 " , " #$ $ 6 4 # $ :$ #$ $ :$ # Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1079 MTD6P10E SAFE OPERATING AREA # " " #$ - , ! ! ! 9 # 8 6 " 9 #$ Figure 11. Maximum Rated Forward Biased Safe Operating Area $ :$ #$ , , $ Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # $ *0 # $ ' '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1080 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MTD6P10E INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 9$ 67 #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 1.75 Watts 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. , , = &/ :$ /)''! 8 " #$ 9 4 /)''! 6 # =)( )'1(%)E " 9#$ &. 6 # A **1( $ /)''! # 6 9 @ 8 Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 1081 MTD6P10E Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 16. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 1082 MTD6P10E TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 17. Typical Solder Heating Profile http://onsemi.com 1083 ) Preferred Device #$%& '( ) N-Channel DPAK This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Replaces MTD6N10 http://onsemi.com 9 AMPERES 100 VOLTS RDS(on) = 250 m N-Channel D G S MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 100 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 100 Vdc Rating Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) 4 VGS VGSM 20 30 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 9.0 5.0 27 Adc Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size PD 40 0.32 1.75 Watts W/C Watts Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 9.0 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient, when mounted to minimum recommended pad size Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds MARKING DIAGRAM Apk 1 2 3 Y WW T9 YWW T9 N10E CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET PIN ASSIGNMENT 4 Drain TJ, Tstg -55 to 150 C EAS 40 mJ 1 Gate C/W RJC RJA RJA 3.13 100 71.4 TL 260 3 Source ORDERING INFORMATION Device C 2 Drain Package Shipping MTD9N10E DPAK 75 Units/Rail MTD9N10E1 DPAK 75 Units/Rail MTD9N10ET4 DPAK 2500 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2001 February, 2001 - Rev. 4 1084 Publication Order Number: MTD9N10E/D MTD9N10E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 100 - - 103 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - - 6.0 4.0 - Vdc mV/C - 0.17 0.25 Ohm - - - - 2.43 2.40 gFS 4.0 - - mhos Ciss - 610 1200 pF Coss - 176 400 Crss - 14 30 td(on) - 8.8 20 tr - 28 60 td(off) - 16 30 tf - 4.8 10 QT - 14 21 Q1 - 5.2 - Q2 - 3.2 - Q3 - 6.6 - - - 0.98 0.9 1.8 - trr - 91 - ta - 71 - OFF CHARACTERISTICS V(BR)DSS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 4.5 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 9.0 Adc) (ID = 4.5 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 8.0 Vdc, ID = 4.5 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 50 Vdc, ID = 9.0 Adc, Vdc VGS = 10 Vdc, RG = 9.1 ) Fall Time Gate Charge g (S Figure (See Fi 8) (VDS = 80 Vdc, ID = 9.0 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 9.0 Adc, VGS = 0 Vdc) (IS = 9.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery y Time (S Figure (See Fi 14) (IS = 9.0 9 0 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) VSD Vdc ns tb - 20 - QRR - 0.4 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 4.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 7.5 - nH Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1085 MTD9N10E TYPICAL ELECTRICAL CHARACTERISTICS 8 8 : # 8 9 9 6 $ # 6 4 # 6 $ 9 : 7 8 8 9 6 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics " , " 4 #$ #$ # $ F$$ #$ # 4$ 6 # #$ 4 4$ 6 6$ $ $$ 9 9$ : :$ 8 8$ 7 6$ 6 # 6 9 8 # 6 8 9 #$ , " #$ #4 # 7 "FF : $ $ 7 8 9 # 6 9 8 "FF " "F6$ $ 4 7 , " #$ #$ : $ F$ 6 Figure 4. On-Resistance versus Drain Current and Gate Voltage < # Figure 3. On-Resistance versus Drain Current and Temperature : , " F$$ # 6 9 9 8 , " #$ "FF F#$ #$ $ :$ , , #$ $ 4 Figure 5. On-Resistance Variation with Temperature 6 9 $ : 8 7 Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1086 MTD9N10E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) # *. " " %!! , " #$ 8 9 %!! (!! 6 !! # (!! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 1087 #$ # " $ " 7 " , " #$ @# 8 8 @ 9 9 6 " 7 , " #$ 6 # # @4 # 6 # 6 9 8 @ ' ! # @ MTD9N10E '( 'CC ' 'C Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 7 " , " #$ 8 : 9 $ 6 4 # $ $$ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1088 MTD9N10E SAFE OPERATING AREA 6 " # " #$ ! ! ! ! " 7 - , 4# #6 9 8 #$ Figure 11. Maximum Rated Forward Biased Safe Operating Area $ :$ #$ , , $ Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1089 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MTD9N10E INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 9$ 67 #$6 8 4 94 9 7 68#9 #64 9:# inches mm POWER DISSIPATION FOR A SURFACE MOUNT DEVICE PD = 150C - 25C = 1.75 Watts 71.4C/W The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows: PD = The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows. TF21( )E 1!%!')1,;'% , ' +%1'U&/ =)( )'1(%)E " 9#$ &. 6 # A **1( :$ /)''! 8 " #$ 9 4 /)''! 6 # $ /)''! # 6 9 (1) !J;)(1 %21! 8 Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical) http://onsemi.com 1090 MTD9N10E Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The CC CC CC CC CCC CCC CC CCCCCC CC CCC CCC CCCCCC Figure 16. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 1091 MTD9N10E TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 17. Typical Solder Heating Profile http://onsemi.com 1092 ( . Preferred Device #$%& '( N-Channel Micro8t, Dual These Power MOSFET devices are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. Micro8 devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Miniature Micro8 Surface Mount Package - Saves Board Space * Extremely Low Profile (<1.1 mm) for thin applications such as PCMCIA cards * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Mounting Information for Micro8 Package Provided http://onsemi.com 1 AMPERE 20 VOLTS RDS(on) = 120 m N-Channel MARKING DIAGRAM Micro8, Dual CASE 846A STYLE 2 8 WW BA 1 WW = Date Code PIN ASSIGNMENT Source-1 Gate-1 Source-2 Gate-2 1 8 7 6 5 2 3 4 Drain-1 Drain-1 Drain-2 Drain-2 Top View ORDERING INFORMATION Device Package MTDF1N02HDR2 Micro8 Shipping 4000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 6 1093 Publication Order Number: MTDF1N02HD/D MTDF1N02HD MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous 1 SQ. FR-4 or G-10 PCB Figure 1 below 1 die operating Steady State Minimum FR-4 or G-10 PCB Figure 2 below 1 die operating Steady State Minimum FR-4 or G-10 PCB Figure 2 below 2 die operating Steady State Thermal Resistance - Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current - Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Thermal Resistance - Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current - Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Thermal Resistance - Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current - Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Operating and Storage Temperature Range 1. Repetitive rating; pulse width limited by maximum junction temperature. Figure 1. 1, Square FR-4 or G-10 PCB Symbol Typical Max Unit VDSS VDGR VGS - 20 V - 20 V - 8.0 V RTHJA PD 80 - - - - - 100 1.25 10 2.8 2.3 23 C/W Watts mW/C A A A 160 - - - - - 200 0.63 5.0 1.7 1.6 16 C/W Watts mW/C A A A 240 - - - - - 300 0.42 3.33 1.6 1.3 13 C/W Watts mW/C A A A - - 55 to 150 C ID ID IDM RTHJA PD ID ID IDM RTHJA PD ID ID IDM TJ, Tstg Figure 2. Minimum FR-4 or G-10 PCB http://onsemi.com 1094 MTDF1N02HD ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 20 - - 5.0 - - - - - - 1.0 25 - - 100 0.7 - 0.9 2.5 1.1 - - - 99 133 120 160 gFS 2.0 - - Mhos Ciss - 145 - pF Coss - 90 - Crss - 38 - td(on) - 8.0 - tr - 27 - td(off) - 23 - tf - 34 - td(on) - 16 - OFF CHARACTERISTICS (Cpk 2.0) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) (Notes 2. & 4.) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 8.0 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Note 4.) (Cpk 2.0) (Note 4.) Static Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 1.7 Adc) (VGS = 2.7 Vdc, ID = 0.85 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 0.85 Adc) VGS(th) Vdc RDS(on) mV/C m DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 15 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS = 10 Vdc, ID = 1.7 Adc, VGS = 4.5 Vdc, RG = 6 ) (Note 2.) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 0.85 Adc, VGS = 2.7 Vdc, RG = 6 ) (Note 2.) Fall Time Gate Charge (VDS = 16 Vdc, ID = 1.7 Adc, VGS = 4.5 Vdc) tr - 79 - td(off) - 24 - tf - 31 - QT - 3.9 5.5 Q1 - 0.4 - Q2 - 1.7 - Q3 - 1.5 - - - 0.84 0.71 1.0 - trr - 29 - ta - 14 - tb - 15 - QRR - 0.018 - ns ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 1.7 Adc, VGS = 0 Vdc) (Note 2.) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 1.7 1 7 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) (Note 2.) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1095 VSD Vdc ns C MTDF1N02HD TYPICAL ELECTRICAL CHARACTERISTICS 6 , " #$ " 6$ #: #4 4 6 7 # # : $ 4 # #$ , " $$ 6 9 # 8 # " : , " #$ 4 # # 6 9 8 $ #: , " #$ 4 " 6$ 7 : $ < # 8 6 #$ $ :$ # 4 6 Figure 6. On-Resistance versus Drain Current and Gate Voltage " 6$ " 8$ ?#$ Figure 5. On-Resistance versus Gate-to-Source Voltage ?$ #$ Figure 4. Transfer Characteristics 6 9 # Figure 3. On-Region Characteristics $ # $ 9 $ #$ $ " , " #$ #$ $ $ , , Figure 7. On-Resistance Variation with Temperature Figure 8. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 1096 # MTDF1N02HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) *. 8 9 6 " " , " #$C %!! (!! # %!! !! (!! $ $ $ Figure 9. Capacitance Variation http://onsemi.com 1097 # 8 @ $ $ 6 # 4 @ 7 @# 9 # " : , " #$ @4 # 4 6 @D 4 $ ' ! 9 MTDF1N02HD " " : " 6$ , " #$ 'C '( 'CC ' Figure 10. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 11. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 13. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # " , " #$ 9 # 8 6 $ $$ 9 9$ : :$ 8 8$ 7 Figure 12. Diode Forward Voltage versus Current http://onsemi.com 1098 MTDF1N02HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 13. Reverse Recovery Time (trr) SAFE OPERATING AREA Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). The Forward Biased Safe Operating Area curve (Figure 14) defines the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." " 8 " #$ ! ! ! Figure 14. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 1099 MTDF1N02HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. &/ " $ # $ # *0 ' '# - - " '&'# $ 6 4 # ' ! 5 5 Figure 15. Thermal Response %&' '(( ') '+ #$ '* Figure 16. Diode Reverse Recovery Waveform http://onsemi.com 1100 ,' " (' , - . / / ' ,*0 " *0 ,' 5# 54 MTDF1N02HD INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 6 6 #8 $#8 #9 4# $ 48 #$9 9$ inches mm Micro8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 0.63 Watts. The power dissipation of the Micro8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the Micro8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 0.63 Watts 200C/W The 200C/W for the Micro8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 0.63 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 1101 MTDF1N02HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 17. Typical Solder Heating Profile http://onsemi.com 1102 MTDF1N02HD TAPE & REEL INFORMATION Micro8 Dimensions are shown in millimeters (inches) 1.60 (.063) 1.50 (.059) 2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B 1.85 (.072) 1.65 (.065) A 0.35 (.013) 0.25 (.010) 5.55 (.218) 5.45 (.215) 12.30 11.70 (.484) (.461) 3.50 (.137) 3.30 (.130) 1.60 (.063) 1.50 (.059) TYP. A FEED DIRECTION 8.10 (.318) 7.90 (.312) 1.50 (.059) 1.30 (.052) SECTION A-A 5.40 (.212) 5.20 (.205) SECTION B-B NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 18.4 (.724) MAX. NOTE 3 13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN. 14.4 (.57) 12.4 (.49) NOTE 4 NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB. http://onsemi.com 1103 (!. Preferred Device #$%& '( ! N-Channel Micro8t, Dual These Power MOSFET devices are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. Micro8 devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Miniature Micro8 Surface Mount Package - Saves Board Space * Extremely Low Profile (<1.1mm) for thin applications such as PCMCIA cards * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Mounting Information for Micro8 Package Provided http://onsemi.com 1 AMPERE 30 VOLTS RDS(on) = 120 m N-Channel MARKING DIAGRAM Micro8, Dual CASE 846A STYLE 2 8 WW BB 1 WW = Date Code PIN ASSIGNMENT Source-1 Gate-1 Source-2 Gate-2 1 8 7 6 5 2 3 4 Drain-1 Drain-1 Drain-2 Drain-2 Top View ORDERING INFORMATION Device Package MTDF1N03HDR2 Micro8 Shipping 4000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 5 1104 Publication Order Number: MTDF1N03HD/D MTDF1N03HD MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Negative sign for P-Channel devices omitted for clarity Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous 1 SQ. FR-4 or G-10 PCB Figure 1 below Steady State Minimum FR-4 or G-10 PCB Figure 2 below 1 die operating Steady State Minimum FR-4 or G-10 PCB Figure 2 below 2 die operating Steady State Thermal Resistance - Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current - Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Thermal Resistance - Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current - Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Thermal Resistance - Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current - Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 30 Vdc, VGS = 10 Vdc, Peak IL = 2.4 Apk, L = 69 mH, RG = 25 W) 1. Repetitive rating; pulse width limited by maximum junction temperature. Figure 1. 1, Square FR-4 or G-10 PCB Symbol Max Unit VDSS VDGR 30 V 30 V VGS RTHJA PD 20 V 100 1.25 10 2.8 2.2 23 C/W Watts mW/C A A A 200 0.63 5.0 2.0 1.6 16 C/W Watts mW/C A A A 300 0.42 3.33 1.6 1.3 13 C/W Watts mW/C A A A - 55 to 150 C ID ID IDM RTHJA PD ID ID IDM RTHJA PD ID ID IDM TJ, Tstg EAS mJ 200 Figure 2. Minimum FR-4 or G-10 PCB http://onsemi.com 1105 MTDF1N03HD ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - 29 - - - - - - 1.0 25 - - 100 1.0 - 1.6 3.7 - - - - 96 135 120 160 gFS 1.0 2.0 - Mhos Ciss - 140 - pF Coss - 70 - Crss - 30 - td(on) - 7.5 - tr - 10 - td(off) - 22 - tf - 18 - td(on) - 7.0 - OFF CHARACTERISTICS (Cpk 2.0) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) (Notes 2. & 4.) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 Vdc) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Note 4.) (Cpk 2.0) (Note 4.) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 1.7 Adc) (VGS = 4.5 Vdc, ID = 0.85 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 0.85 Adc) (Note 2.) VGS(th) Vdc RDS(on) mV/C m DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS = 15 Vdc, ID = 1.7 Adc, VGS = 10 Vdc, RG = 6 ) (Note 2.) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 0.85 Adc, VGS = 4.5 Vdc, RG = 6 ) (Note 2.) Fall Time Gate Charge (VDS = 24 Vdc, ID = 1.7 Adc, VGS = 10 Vdc) tr - 8.2 - td(off) - 22 - tf - 14.5 - QT - 5.0 7.0 Q1 - 0.5 - Q2 - 1.65 - Q3 - 1.3 - - - 0.84 0.7 1.0 - trr - 20 - ta - 12 - tb - 8.0 - QRR - 0.012 - ns ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 1.7 Adc, VGS = 0 Vdc) (Note 2.) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 1.7 1 7 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) (Note 2.) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1106 VSD Vdc ns C MTDF1N03HD TYPICAL ELECTRICAL CHARACTERISTICS " 47 4 9 6$ 4: 6 , " #$ 4$ 6 44 4 # #7 #: 4 # #$ #$ #4 $ $ $ # 4$ 6 6 4 # # 6 9 8 6$ 8 , " #$ 9 " 6$ 6 # 8 # 4 6 Figure 5. On-Resistance versus Gate-to-Source Voltage Figure 6. On-Resistance versus Drain Current and Gate Voltage " " 8$ < 4 Figure 4. Transfer Characteristics $ # #$ Figure 3. On-Region Characteristics " : , " #$ #$ # 9 , " $$ $ " , " #$ #$ $ ?$ ?#$ #$ $ :$ #$ $ $ $ # #$ , , Figure 7. On-Resistance Variation with Temperature Figure 8. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 1107 4 MTDF1N03HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 11) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) $ *. 6 4 " " , " #$C %!! (!! # %!! !! (!! $ $ $ # Figure 9. Capacitance Variation http://onsemi.com 1108 #$ 4 4 @ #$ # 8 6 @ # 9 $ @# $ " : , " #$ @4 6 # 4 @D 9 $ ' ! # MTDF1N03HD " $ " : " , " #$ 'CC 'C '( ' Figure 10. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 11. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 13. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # " , " #$ $ $ 9 9$ : :$ 8 8$ 7 Figure 12. Diode Forward Voltage versus Current http://onsemi.com 1109 MTDF1N03HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 13. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 16). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curve (Figure 14) defines the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For # " # " #$ GG - , ! ! ! ! " 4 " " #6 " 97 9 # 8 6 #$ $ :$ #$ $ , , Figure 14. Maximum Rated Forward Biased Safe Operating Area Figure 15. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 1110 MTDF1N03HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ # *0 ' '# - - " '&'# $ 6 4 # ' ! 5 5 Figure 16. Thermal Response %&' '(( ') '+ #$ '* Figure 17. Diode Reverse Recovery Waveform http://onsemi.com 1111 ,' " (' , - . / / ' ,*0 " *0 ,' 5# 54 MTDF1N03HD INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 6 6 #8 $#8 #9 4# $ 48 #$9 9$ inches mm Micro8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 0.63 Watts. The power dissipation of the Micro8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the Micro8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 0.63 Watts 200C/W The 200C/W for the Micro8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 0.63 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 1112 MTDF1N03HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 1113 MTDF1N03HD TAPE & REEL INFORMATION Micro8 Dimensions are shown in millimeters (inches) 1.60 (.063) 1.50 (.059) 2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B 1.85 (.072) 1.65 (.065) A 0.35 (.013) 0.25 (.010) 5.55 (.218) 5.45 (.215) 12.30 11.70 (.484) (.461) 3.50 (.137) 3.30 (.130) 1.60 (.063) 1.50 (.059) TYP. A FEED DIRECTION 8.10 (.318) 7.90 (.312) 1.50 (.059) 1.30 (.052) SECTION A-A 5.40 (.212) 5.20 (.205) SECTION B-B NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 18.4 (.724) MAX. NOTE 3 13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN. 14.4 (.57) 12.4 (.49) NOTE 4 NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB. http://onsemi.com 1114 ( . Preferred Device #$%& '( N-Channel Micro8t, Dual Micro8 devices are an advanced series of Power MOSFETs that contain monolithic back-to-back zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Miniature Micro8 Surface Mount Package - Saves Board Space * Diode is Characterized for Use in Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Mounting Information for Micro8 Package Provided http://onsemi.com 2 AMPERES 60 VOLTS RDS(on) = 220 mW N-Channel MARKING DIAGRAM MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Parameter Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Continuous Drain Current @ TA = 25C (Note 1.) Pulsed Drain Current (Note 2.) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Continuous Source Current (Diode Conduction) (Note 3.) Symbol Max Unit VDSS VDGR 60 Vdc 60 Vdc VGS ID IDM 20 Vdc 1.5 12 Adc PD 1.25 W TJ, Tstg - 55 to 150 C IS 0.9 Adc Micro8, Dual CASE 846A STYLE 2 8 WW BA 1 WW = Date Code PIN ASSIGNMENT THERMAL RESISTANCE Junction-to-Ambient (Note 1.) RJA 100 C/W 1. When mounted on 1 square FR-4 or G-10 board (VGS = 10 V, @ 10 Seconds) 2. Repetitive rating; pulse width limited by maximum junction temperature. 3. When mounted on FR-4 board, t 10 seconds Source-1 Gate-1 Source-2 Gate-2 1 8 7 6 5 2 3 4 Drain-1 Drain-1 Drain-2 Drain-2 Top View ORDERING INFORMATION Device Package MTDF2N06HDR2 Micro8 Shipping 4000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 1115 Publication Order Number: MTDF2N06HD/D MTDF2N06HD ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - - - - - 1.0 10 - - 100 1.0 1.6 3.0 - - 180 220 220 260 gFS 0.5 2.5 - Mhos pF OFF CHARACTERISTICS (Cpk 2.0) (Notes 4. & 6.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc Adc nAdc ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) (Cpk 2.0) (Notes 4. & 6.) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 1.5 Adc) (VGS = 4.5 Vdc, ID = 0.75 Adc) (Cpk 2.0) (Notes 4. & 6.) Forward Transconductance (VDS = 8.0 Vdc, ID = 1.0 Adc) (Note 4.) VGS(th) Vdc RDS(on) m DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 V V, f = 1.0 MHz) Output Capacitance Transfer Capacitance Ciss - 140 200 Coss - 40 60 Crss - 12 18 td(on) - 7.5 15 tr - 8.0 16 td(off) - 25 50 tf - 14.5 29 QT - 18 26 Q1 - 3.1 - Q2 - 6.8 - Q3 - 5.0 - - - 0.9 0.83 1.5 - trr - 24 - ta - 18 - tb - 6.0 - QRR - 0.02 - SWITCHING CHARACTERISTICS (Note 5.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 30 Vdc, ID = 1.5 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (Note 4.) Fall Time Gate Charge (S Figure (See Fi 8) (VGS = 10 Vdc, ID = 1.5 Adc, VDD = 30 Vdc) (Note 4.) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 1.5 Adc, VGS = 0 Vdc) (Note 4.) (IS = 1.5 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 1.5 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 4.) Reverse Recovery Stored Charge 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperatures. 6. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1116 VSD Vdc ns C MTDF2N06HD TYPICAL ELECTRICAL CHARACTERISTICS 4: 4$ 9 4 6 , " #$ 6$ 6 44 # #7 4 # , " #$ #$ $$ " #$ # 6 9 8 # 6 9 8 # " $ , " #$ 9 6 # # 9 6 8 4 $ 6 4 , " #$ #9 " 6$ ## 8 6 $ 4 # Figure 3. On-Resistance versus Drain Current Figure 4. On-Resistance versus Drain Current and Gate Voltage # 6 : " " $ , " #$ $ 8 $ ?$ # Figure 2. Transfer Characteristics < W Figure 1. On-Region Characteristics 8 ?#$ #$ $ :$ #$ $ 7 #$ " , , # 6 4 Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1117 $ MTDF2N06HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) $ *. 6 4 " " , " #$ %!! (!! # %!! (!! $ !! $ $ # Figure 7. Capacitance Variation http://onsemi.com 1118 #$ 4 @ #$ 8 # 9 $ 6 @ # @# , " #$ " $ @4 $ $ # $ ' ! 4 # MTDF2N06HD , " #$ " $ " 4 " 'C 'CC '( ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # " , " #$ $ $ # 6 9 8 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 1119 MTDF2N06HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the " " #$ m! ! ! Figure 12. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 1120 MTDF2N06HD INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 6 6 #8 $#8 #9 4# $ 48 #$9 9$ inches mm Micro8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 1.25 Watts. The power dissipation of the Micro8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the Micro8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 1.25 Watts 100C/W The 100C/W for the Micro8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.25 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 1121 MTDF2N06HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 13 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 13. Typical Solder Heating Profile http://onsemi.com 1122 # Preferred Device #$%& '( N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers drain-to-source diodes with fast recovery times. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating area are critical, and offer additional safety margin against unexpected voltage transients. * Internal Source-to-Drain Diode Designed to Replace External Zener Transient Suppressor - Absorbs High Energy in the Avalanche Mode - Unclamped Inductive Switching (UIS) Energy Capability Specified at 100C * Commutating Safe Operating Area (CSOA) Specified for Use in Half and Full Bridge Circuits * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits http://onsemi.com 10 AMPERES 100 VOLTS RDS(on) = 250 m N-Channel D G S MARKING DIAGRAM & PIN ASSIGNMENT MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 100 Vdc Drain-Gate Voltage (RGS = 1.0 M) Rating VDGR 100 Vdc Gate-Source Voltage VGS 20 Vdc Drain Current - Continuous Drain Current - Pulsed ID IDM 10 25 Adc Total Power Dissipation Derate above 25C PD 75 0.6 Watts W/C TJ, Tstg -65 to 150 C Operating and Storage Temperature Range Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds 4 Drain 4 TO-220AB CASE 221A STYLE 5 1 2 1 Gate 3 1.67 62.5 TL 275 C 3 Source 2 Drain C/W RJC RJA MTP10N10E LLYWW MTP10N10E LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP10N10E Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 1123 Publication Order Number: MTP10N10E/D MTP10N10E ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)DSS 100 - Vdc - - 10 80 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 0.25 mA) Zero Gate Voltage Drain Current (VDS = Rated VDSS, VGS = 0) (VDS = 0.8 Rated VDSS, VGS = 0, TJ = 125C) A IDSS Gate-Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) IGSSF - 100 nAdc Gate-Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) IGSSR - 100 nAdc 2.0 1.5 4.5 4.0 - 0.25 - - 2.7 2.4 4.0 - - - - 60 100 40 Ciss - 600 Coss - 400 Crss - 100 td(on) - 50 tr - 80 td(off) - 100 tf - 80 ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) TJ = 100C VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 5.0 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 V) (ID = 10 Adc) (ID = 5.0 Adc, TJ = 100C) VDS(on) gFS Forward Transconductance (VDS = 15 V, ID = 5.0 A) Vdc Ohm Vdc mhos DRAIN-TO-SOURCE AVALANCHE CHARACTERISTICS Unclamped Drain-to-Source Avalanche Energy See Figures 14 and 15 (ID = 25 A, VDD = 25 V, TC = 25C, Single Pulse, Non-repetitive) (ID = 10 A, VDD = 25 V, TC = 25C, P.W. 200 s, Duty Cycle 1%) (ID = 4.0 A, VDD = 25 V, TC = 100C, P.W. 200 s, Duty Cycle 1%) WDSR mJ DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) S Fi See Figure 16 pF SWITCHING CHARACTERISTICS (Note 1.) (TJ = 100C) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 V, ID = 5.0 A, RG = 50 ) See Figure 9 Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge (VDS = 0.8 Rated VDSS, ID = Rated ID, VGS = 10 V) S Figures See Fi 17 and d 18 Qg 15 (Typ) 30 Qgs 8.0 (Typ) - Qgd 7.0 (Typ) - VSD 1.4 (Typ) 1.7 ns nC SOURCE-DRAIN DIODE CHARACTERISTICS (Note 1.) Forward On-Voltage Forward Turn-On Time (IS = Rated R t d ID VGS = 0) Reverse Recovery Time ton trr Vdc Limited by stray inductance 70 (Typ) - 3.5 (Typ) 4.5 (Typ) - - 7.5 (Typ) - ns INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Ld Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) Ls 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. http://onsemi.com 1124 nH MTP10N10E # " 8 , " #$ : 9 9 # 8 $ 6 6 6 8 # 9 # '2 < TYPICAL ELECTRICAL CHARACTERISTICS # 7 8 : $ , " $$ " 9 " $ # 8 5#$ 6 # 6 9 8 = = / < Figure 1. On-Region Characteristics # < 6 , " #$ $$ # 6 9 #$ $ # 9 " " #$ # 8 6 $ $ $ # Figure 4. Breakdown Voltage Variation With Temperature " #$ $ :$ , , , , $ # #$ Figure 2. Gate-Threshold Voltage Variation With Temperature Figure 3. Transfer Characteristics 4 " " 8 # 9 " " $ # 8 6 $ $ $ , , Figure 5. On-Resistance versus Drain Current Figure 6. On-Resistance Variation With Temperature http://onsemi.com 1125 # MTP10N10E SAFE OPERATING AREA INFORMATION 6 ! ! ! ! " # " #$ 4 4 4 # , $ 4 Figure 7. Maximum Rated Forward Biased Safe Operating Area # 6 9 8 Figure 8. Maximum Rated Switching Safe Operating Area FORWARD BIASED SAFE OPERATING AREA and a maximum junction temperature of 150C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, "Transient Thermal Resistance-General Data and Its Use" provides detailed instructions. The FBSOA curves define the maximum drain-to-source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25C SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) of Figure 8 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, V(BR)DSS. The switching SOA shown in Figure 8 is applicable for both turn-on and turn-off of the devices for switching times less than one microsecond. The power averaged over a complete switching cycle must be less than: ' ! 'CC " #$ " $ " , " #$ $ 4 # : $ 4 # '( 'C ' : $ 4 # TJ(max) - TC RJC # 4 $ # 4 $ # 4 $ Figure 9. Resistive Switching Time versus Gate Resistance http://onsemi.com 1126 (' < MTP10N10E : $ " $ 4 # # : $ 4 *0 $ ' '# - - " '&'# # # 4 $ ,' " (' , , " 9:&/ > - . / / ' ,*0 " *0 ,' # 4 $ # 4 $ ' ! # $ 4 # 4 $ Figure 10. Thermal Response COMMUTATING SAFE OPERATING AREA (CSOA) Stray inductances in ON Semiconductor's test circuit are assumed to be practical minimums. dVDS/dt in excess of 10 V/ns was attained with dIs/dt of 400 A/s. The Commutating Safe Operating Area (CSOA) of Figure 12 defines the limits of safe operation for commutated source-drain current versus re-applied drain voltage when the source-drain diode has undergone forward bias. The curve shows the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to those of Figure 11 are present. Full or half-bridge PWM DC motor controllers are common applications requiring CSOA data. Device stresses increase with increasing rate of change of source current so dIs/dt is specified with a maximum value. Higher values of dIs/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIs/dt is limited primarily by device, package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking. VDS(pk) is the peak drain-to-source voltage that the device must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of commutation. VR is specified at 80% of V(BR)DSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. $ . 7B E!&' B '(( ' #$ *0 C &' ! > Figure 11. Commutating Waveforms http://onsemi.com 1127 MTP10N10E 4 5 . #$ 5 # # $ " 8B . ! " C 5 % E!&' !&' 6 &! Figure 13. Commutating Safe Operating Area Test Circuit $ % # 6 9 8 GG # = !' Figure 12. Commutating Safe Operating Area (CSOA) ' 6: . #$ ' ' ' $ = / F +F F F # F # = FWF Figure 14. Unclamped Inductive Switching Test Circuit Figure 15. Unclamped Inductive Switching Waveforms http://onsemi.com 1128 MTP10N10E *. #$ , " #$ %!! !! :$ $ %!! #$ # !! (!! # 4 $ 8 9 6 " # Figure 16. Capacitance Variation 6 8 # @ 6: 0 $ 9 Figure 17. Gate Charge versus Gate-To-Source Voltage 58 % , " #$ " 4 8 0 # 476 . - # 476 0 6: 0 . = % " $ *0V / ! - - B Figure 18. Gate Charge Test Circuit http://onsemi.com 1129 # # Preferred Device #$%& '( * %+% N-Channel TO-220 http://onsemi.com This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature 10 AMPERES 100 VOLTS RDS(on) = 22 m N-Channel D G S MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 100 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 100 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 15 20 Vdc Vpk Rating Drain Current - Continuous @ TC = 25C - Continuous @ TC = 100C - Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Derate above 25C Total Power Dissipation @ TC = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 10 Adc, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient - Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds ID ID IDM 10 6.0 35 Adc PD 40 0.32 1.75 Watts W/C Watts -55 to 150 C TJ, Tstg EAS 50 C/W 3.13 100 71.4 TL 260 4 Drain 4 TO-220AB CASE 221A STYLE 5 MTP10N10EL LLYWW Apk mJ RJC RJA RJA MARKING DIAGRAM & PIN ASSIGNMENT 1 2 3 1 Gate 3 Source 2 Drain MTP10N10EL LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTP10N10EL TO-220AB 50 Units/Rail C Preferred devices are recommended choices for future use and best overall value. 1. When surface mounted to an FR4 board using the minimum recommended pad size. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 1130 Publication Order Number: MTP10N10EL/D MTP10N10EL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 100 - - 115 - - - - - - 10 100 - - 100 1.0 - 1.45 4.0 2.0 - mV/C - 0.17 0.22 Ohm - - 1.85 - 2.6 2.3 gFS 5.0 7.9 - mhos Ciss - 741 1040 pF Coss - 175 250 Crss - 18.9 40 td(on) tr - 11 20 - 74 150 td(off) tf - 17 30 - 38 80 QT - 9.3 15 Q1 - 2.56 Q2 - 4.4 - Q3 - 4.6 - - - 0.98 0.898 1.6 - trr ta - 124.7 - - 86 - tb QRR - 38.7 - - 0.539 - - 4.5 - - 7.5 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 5.0 Vdc, ID = 5.0 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 5.0 Vdc, ID = 10 Adc) (VGS = 5.0 Vdc, ID = 5.0 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 8.0 Vdc, ID = 5.0 Adc) Vdc Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 1 0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time (VDD = 50 Vdc, ID = 10 Adc, VGS = 5.0 Vdc, Rg = 9.1 ) Turn-Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 80 Vdc, ID = 10 Adc, VGS = 5.0 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2.) (IS = 10 Adc, VGS = 0 Vdc) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery y Time Reverse Recovery Stored Charge Vdc (IS = 10 Adc Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Ld Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad.) Ls 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1131 nH MTP10N10EL TYPICAL ELECTRICAL CHARACTERISTICS # : " , " #$ 6$ $ 6 4$ $ 4 # # 6 4 $ $ # $$ $ #$ $ $ # 4 6 " $ #$ , " #$ $ $ $$ $ $ # #$ , " #$ " $ # $ $ # Figure 4. On-Resistance versus Drain Current and Gate Voltage " $ " $ " , " #$ $ < $ Figure 3. On-Resistance versus Drain Current and Temperature # $ Figure 2. Transfer Characteristics Figure 1. On-Region Characteristics 4$ , " $ $ #$ #$ $ :$ , , #$ $ Figure 5. On-Resistance Variation with Temperature # 6 9 8 Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1132 MTP10N10EL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 8 *. 9 %!! 6 " " , " #$C # 8 %!! (!! 9 6 !! # (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1133 MTP10N10EL @ :$ 8 9 6$ @# @ 6 @4 # 4 , " #$ " 6 9 8 $ ' ! 7 # , " #$ " " " $ '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS " , " #$ 8 9 6 # $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1134 MTP10N10EL - , SAFE OPERATING AREA " # " #$ ! ! ! ! $ " F 6 4 # #$ $ :$ #$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area $ Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # $ *0 # ' '# - - " '&'# ' Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1135 ,' " (' , - . / / ' ,*0 " *0 ,' # # Preferred Device #$%& '( P-Channel TO-220 This Power MOSFET is designed for medium voltage, high speed power switching applications such as switching regulators, converters, solenoid and relay drivers. * Silicon Gate for Fast Switching Speeds - Switching Times Specified at 100C * Designer's Data - IDSS, VDS(on), VGS(th) and SOA Specified at Elevated Temperature * Rugged - SOA is Power Dissipation Limited * Source-to-Drain Diode Characterized for Use With Inductive Loads http://onsemi.com 12 AMPERES 100 VOLTS RDS(on) = 300 m P-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Symbol Value Unit Drain-Source Voltage VDSS 100 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 100 Vdc Gate-Source Voltage - Continuous - Non-repetitive (tp 50 s) VGS VGSM 20 40 Vdc Vpk Drain Current - Continuous Drain Current - Pulsed ID IDM 12 28 Adc Total Power Dissipation Derate above 25C PD 75 0.6 Watts W/C TJ, Tstg -65 to 150 C Operating and Storage Temperature Range Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds MARKING DIAGRAM & PIN ASSIGNMENT TO-220AB CASE 221A STYLE 5 C/W RJC RJA 1.67 62.5 TL 260 C 4 Drain 4 1 2 MTP12P10 LLYWW 1 Gate 3 3 Source 2 Drain MTP12P10 LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP12P10 Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 1136 Publication Order Number: MTP12P10/D MTP12P10 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)DSS 100 - Vdc - - 10 100 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 0.25 mA) Zero Gate Voltage Drain Current (VDS = Rated VDSS, VGS = 0) (VDS = Rated VDSS, VGS = 0, TJ = 125C) Adc IDSS Gate-Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) IGSSF - 100 nAdc Gate-Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) IGSSR - 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) TJ = 100C VGS(th) 2.0 1.5 4.5 4.0 Vdc Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 6.0 Adc) RDS(on) - 0.3 Ohm Drain-Source On-Voltage (VGS = 10 V) (ID = 12 Adc) (ID = 6.0 Adc, TJ = 100C) VDS(on) - - 4.2 3.8 gFS 2.0 - mhos Ciss - 920 pF Coss - 575 Crss - 200 td(on) - 50 tr - 150 td(off) - 150 tf - 150 Qg 33 (Typ) 50 Qgs 16 (Typ) - Qgd 17 (Typ) - VSD 4.0 (Typ) 5.5 ON CHARACTERISTICS (Note 1.) Forward Transconductance (VDS = 15 V, ID = 6.0 A) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) S Fi See Figure 10 SWITCHING CHARACTERISTICS (Note 1.) (TJ = 100C) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 V, ID = 0.5 Rated ID, RG = 50 ) See Figures 12 and 13 Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge (VDS = 0.8 Rated VDSS, ID = Rated ID, VGS = 10 V) S Fi See Figure 11 ns nC SOURCE-DRAIN DIODE CHARACTERISTICS (Note 1.) Forward On-Voltage Forward Turn-On Time (IS = Rated R t d ID, VGS = 0) Reverse Recovery Time ton Vdc Limited by stray inductance trr 300 (Typ) - ns Internal Drain Inductance (Measured from the contact screw on the header closer to the source pin and the center of the die) Ld 5.0 (Typ) - nH Internal Source Inductance (Measured from the source pin, 0.25 from the package to the source bond pad) Ls 12.5 (Typ) - 3.5 (Typ) 4.5 (Typ) - - 7.5 (Typ) - INTERNAL PACKAGE INDUCTANCE (TO-204) INTERNAL PACKAGE INDUCTANCE (TO-220) Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Ld Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) Ls 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. http://onsemi.com 1137 nH MTP12P10 # " # 8 9 , " #$ 8 6 # : 8 9 9 6 $ # # 4 6 $ 9 : 8 7 '2 < TYPICAL ELECTRICAL CHARACTERISTICS # 7 8 $ #$ 9 , " $$ # 8 " # 6 6 8 # 9 # 9 < #$ # $$ 6 8 # 9 # #6 #8 4# " " #$ # 8 6 $ :$ #$ $ :$ #$ $ Figure 4. Normalized Breakdown Voltage versus Temperature , " 4 #$ , , $ " $ #$ $ :$ , , # Figure 3. Transfer Characteristics 6 #$ Figure 2. Gate-Threshold Voltage Variation With Temperature = = / < Figure 1. On-Region Characteristics # " " 49 6 8 " " 9 9 6 # 8 9 6 # $ #$ #$ $ :$ #$ $ , , Figure 5. On-Resistance versus Drain Current Figure 6. On-Resistance Variation With Temperature http://onsemi.com 1138 $ MTP12P10 SAFE OPERATING AREA INFORMATION $ ! ! ! ! " # " #$ &#9 &# 6 4 # &#9 &# Figure 7. Maximum Rated Forward Biased Safe Operating Area 4 $ : # 6 9 8 7 Figure 8. Maximum Rated Switching Safe Operating Area FORWARD BIASED SAFE OPERATING AREA SWITCHING SAFE OPERATING AREA The FBSOA curves define the maximum drain-to-source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, "Transient Thermal Resistance-General Data and Its Use" provides detailed instructions. The switching safe operating area (SOA) of Figure 8 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, V(BR)DSS. The switching SOA shown in Figure 8 is applicable for both turn-on and turn-off of the devices for switching times less than one microsecond. The power averaged over a complete switching cycle must be less than: TJ(max) - TC RJC (' <.. " $ $ 4 # # $ *0 $ # 4 ' # # '# - - " '&'# $ # $ # $ ' ! Figure 9. Thermal Response http://onsemi.com 1139 # ,' " (' , , " 9:&/ > - . / / ' ,*0 " *0 ,' $ # $ MTP12P10 *. 9 " #$ " C " A # %!! 8 !! 6 (!! 4 # 6 9 8 " 4 # $ 6 9 6 , " #$ " # # 8 $ $ # #$ 4 4$ 6 6$ @D Figure 10. Capacitance Variation Figure 11. Gate Charge versus Gate-To-Source Voltage RESISTIVE SWITCHING ' ' '( 7B ;' D1 $ % ;' A " $ 'CC 'CC 'C 7B B 7B $ % Figure 12. Switching Test Circuit $B $B B / Figure 13. Switching Waveforms http://onsemi.com 1140 $ #! Preferred Device #$%& '( ! N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating area are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode Is Characterized for Use In Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 42 AMPERES 30 VOLTS RDS(on) = 22 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 42 Apk, L = 0.25 mH, RG = 25 ) Thermal Resistance Junction to Case Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 5 seconds Symbol Value Unit VDSS VDGR 30 Vdc 30 Vdc VGS VGSM ID ID IDM PD 20 20 Vdc Vpk 42 20 126 Adc 74 0.592 Watts W/C TJ, Tstg - 55 to 150 C EAS 220 mJ S MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 Apk TO-220AB CASE 221A STYLE 5 1 2 MTP1302 LLYWW 1 Gate 3 3 Source 2 Drain C/W RJC RJA 1.67 62.5 TL 260 MTP1302 LL Y WW C = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP1302 Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 1141 Publication Order Number: MTP1302/D MTP1302 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 30 - - - - - - 10 100 - - 100 1.0 1.5 2.0 - - - 19 26 19.5 22 29 - - - - 0.38 - 0.82 0.5 0.33 - 10 16 - Ciss - 755 1162 Coss - 370 518 Crss - 102 204 td(on) - 7.2 15 tr - 52 104 td(off) - 45 90 tf - 73 146 QT - 14.5 21.8 Q1 - 2.2 - Q2 - 8.8 - Q3 - 6.8 - QT - 27 40.5 Q1 - 2.2 - Q2 - 10 - Q3 - 7.2 - - - 0.83 0.79 1.1 - trr - 38 - ta - 19 - tb - 20 - QRR - 36 - Unit OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) (VGS = 10 Vdc, ID = 42 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 10 Adc, TJ = 150C) (VGS = 10 Vdc, ID = 42 Adc) VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 10 Adc) Vdc mW Vdc gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (VDS = 24 Vdc, ID = 20 Adc, VGS = 5.0 Vdc) Gate Charge (VDS = 24 Vdc, ID = 20 Adc, VGS = 10 Vdc) ns nC nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1142 VSD Vdc ns C MTP1302 TYPICAL ELECTRICAL CHARACTERISTICS 4$ 4 $ 6 6 4 , " #$ #$ # $ " 4 $ #$ # $ , " #$ ?$$ # 9 6 8 # 6 9 8 # $ # #$ ?$$ $ #$ # 4$ 4 6 , " $ , " #$ 4$ " 6$ 4 #$ # $ $ $ # #$ 4 4$ 6 6$ Figure 4. On-Resistance versus Drain Current and Gate Voltage 4 " # # " 6$ 6 6 Figure 3. On-Resistance versus Drain Current and Temperature < " 4$ Figure 2. Transfer Characteristics 4 # 4 #$ Figure 1. On-Region Characteristics #$ $ $ #$ #$ $ :$ #$ $ , " #$ #$ $ $ # #$ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1143 4 MTP1302 POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) #$ %!! *. # $ (!! %!! $ !! " " $ $ (!! $ # Figure 7. Capacitance Variation http://onsemi.com 1144 #$ 6 8 # $ @ # 8 7 9 6 # @ @# 9 " # , " #$ @4 4 # 6 9 8 # 6 9 8 # ## #6 #9 #8 4 ' ! MTP1302 " $ " # " , " #$ 'C '( 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # 8 , " #$ 9 6 # 8 9 6 # 6 6$ $ $$ 9 9$ : :$ 8 8$ 7 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 1145 MTP1302 '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For ## " " #$ - , m! m! ! ! # " 6# 8 9 6 # 8 9 6 # #$ $ :$ #$ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 1146 $ ('.. < MTP1302 " $ # *0 $ # ' '# - - " '&'# ' ! Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 1147 ,' " (' , - . / / ' ,*0 " *0 ,' #! Preferred Device #$%& '( " ! N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating area are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 75 AMPERES 30 VOLTS RDS(on) = 6.5 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 30 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 30 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 20 Vdc Vpk ID ID IDM 75 59 225 Adc PD 150 1.2 Watts W/C TJ, Tstg -55 to 150 C Rating Drain Current - Continuous - Continuous @ 100C - Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 75 Apk, L = 0.1 mH, RG = 25 ) Thermal Resistance - Junction-to-Case - Junction-to-Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 5.0 seconds EAS S MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 TO-220AB CASE 221A STYLE 5 Apk 1 2 1 Gate 3 MTP1306 LL Y WW C/W 0.8 62.5 TL 260 3 Source 2 Drain mJ 280 RJC RJA MTP1306 LLYWW C = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP1306 Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 1148 Publication Order Number: MTP1306/D MTP1306 ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - - - - - 10 100 - - 100 1.0 1.5 2.0 - - 5.8 7.4 6.5 8.5 - - 0.44 - 0.5 0.38 gFS 15 55 - mhos pF OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 38 Adc) (VGS = 5.0 Vdc, ID = 38 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 75 Adc) (VGS = 10 Vdc, ID = 38 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 3.0 Vdc, ID = 20 Adc) Vdc mW Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance Ciss - 2560 3584 Coss - 1305 1827 Crss - 386 772 td(on) - 17 35 SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 75 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 4.7 ) Fall Time Gate Charge (VDS = 24 Vdc, ID = 75 Adc, VGS = 5.0 Vdc) tr - 170 340 td(off) - 68 136 tf - 145 290 QT - 50 70 Q1 - 8.3 - Q2 - 25.3 - Q3 - 17.2 - - - 0.75 0.64 1.1 - trr - 84 - ta - 35 - tb - 53 - QRR - 0.13 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage VSD (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time Adc VGS = 0 Vdc, Vdc (IS = 20 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1149 Vdc ns C MTP1306 TYPICAL ELECTRICAL CHARACTERISTICS 8 " $ #$ 6 , " #$ :$ $ #$ 9 $ 6 # 8 9 #$ 6 #$ # $ :$ #$ :$ #$ $ # # 7 8 , " : #$ 9 $ $$ 6 4 # # 6 9 8 # 6 7 , " #$ 8 " $ : 9 $ 6 Figure 3. On-Resistance versus Drain Current and Temperature # 4 6 $ 9 : 8 7 # 4 6 $ Figure 4. On-Resistance versus Drain Current and Gate Voltage # " " 48 $ < 6$ Figure 2. Transfer Characteristics Figure 1. On-Region Characteristics , " $$ #$ 4 4$ 6 $ $ #$ #$ $ :$ , , #$ $ , " #$ $ Figure 5. On-Resistance Variation with Temperature $ # #$ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1150 4 MTP1306 POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 7 *. 8 : " " %!! 9 $ (!! 6 4 %!! # !! (!! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 1151 #$ $ :$ @ # $ 7 @ @# 9 #$ @4 , " #$ " :$ # 4 6 @ $ " $ " :$ " $ , " #$ ' ! 8 MTP1306 '( 'C 'CC 4 9 ' Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # " , " #$ 8 9 6 # 8 9 6 # 6$ $ $$ 9 9$ : :$ Figure 10. Diode Forward Voltage versus Current http://onsemi.com 1152 MTP1306 '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For ! ! #8 " " #$ - , Figure 12. Maximum Rated Forward Biased Safe Operating Area " :$ #6 # 9 # 8 6 #$ $ :$ #$ , , $ Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 1153 MTP1306 (' <.. " $ # *0 $ ,' " (' , - . / / ' ,*0 " *0 ,' # ' '# - - " '&'# $ 6 4 # ' ! 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 1154 5 # Preferred Device #$%& '( N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 15 AMPERES 60 VOLTS RDS(on) = 120 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-Source Voltage - Continuous - Single Pulse (tp 50 s) VGS VGSM 20 25 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 15 8.7 45 Adc Total Power Dissipation @ 25C Derate above 25C PD 55 0.5 Watts W/C TJ, Tstg -55 to 175 C EAS 113 mJ Rating Drain-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds G S MARKING DIAGRAM & PIN ASSIGNMENT Apk RJC RJA 2.73 62.5 C/W TL 260 C 4 Drain 4 TO-220AB CASE 221A STYLE 5 1 2 3 MTP15N06V LLYWW 1 Gate 3 Source 2 Drain MTP15N06V LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP15N06V Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 1155 Publication Order Number: MTP15N06V/D MTP15N06V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 67 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.7 5.0 4.0 - Vdc mV/C - 0.08 0.12 Ohm - - 2.0 - 2.2 1.9 gFS 4.0 6.2 - mhos Ciss - 469 660 pF Coss - 148 200 Crss - 35 60 td(on) - 7.6 20 tr - 51 100 td(off) - 18 40 tf - 33 70 QT - 14.4 20 Q1 - 2.8 - Q2 - 6.4 - Q3 - 6.1 - - - 1.05 1.5 1.6 - trr - 59.3 - ta - 46 - tb - 13.3 - QRR - 0.165 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 4.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 7.5 - nH OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 7.5 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 15 Adc) (ID = 7.5 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 30 Vdc, ID = 15 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 15 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 15 Adc, VGS = 0 Vdc) (IS = 15 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (S Figure (See Fi 14) Adc VGS = 0 Vdc, Vdc (IS = 15 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1156 MTP15N06V TYPICAL ELECTRICAL CHARACTERISTICS , " #$C : # $ 9 $ $ # # 4 6 9 $ #$C $ $ # 6 9 8 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics " , " C #$C 8 F$$C $ #$ $ # 4 4 , " #$C " 7 $ : $ Figure 3. On-Resistance versus Drain Current and Temperature $ $ # #$ 4 Figure 4. On-Resistance versus Drain Current and Gate Voltage # " " " :$ 9 < F$$C # 6 # , " C #$ : #$ 7 4 8 " 4 # 8 6 $ #$ #$ $ :$ #$ $ :$ , " #$C , , 4 # 6 $ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1157 9 MTP15N06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) $ " *. # " , " #$C %!! 7 9 %!! (!! 4 !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1158 9 @ $ 8 6 @# @ 9 4 6 # " $ , " #$ # @4 4 9 7 # $ ' ! # MTP15N06V " 4 " $ " , " #$ '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS $ # " , " #$ 7 9 4 $ : 7 4 $ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1159 MTP15N06V SAFE OPERATING AREA # " " #$ - , ! ! ! ! 8 9 6 # #$ " $ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # $ *0 # ' '# - - " '&'# $ 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1160 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 # Preferred Device #$%& '( * %+% N-Channel TO-220 http://onsemi.com This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature 15 AMPERES 60 VOLTS RDS(on) = 85 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 15 25 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 15 12 53 Adc Total Power Dissipation Derate above 25C PD 60 0.40 Watts W/C TJ, Tstg -55 to 175 C EAS 113 mJ Rating Drain-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds G S MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 Apk TO-220AB CASE 221A STYLE 5 1 RJC RJA 2.5 62.5 C/W TL 260 C 2 3 MTP15N06VL LLYWW 1 Gate 3 Source 2 Drain MTP15N06VL LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTP15N06VL TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 1161 Publication Order Number: MTP15N06VL/D MTP15N06VL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 68 - - Vdc mV/C - - - - 10 100 - - 100 1.0 - 1.5 4.0 2.0 - - 0.075 0.085 - - - - 1.5 1.3 gFS 8.0 10 - mhos Ciss - 570 800 pF Coss - 180 250 Crss - 45 90 td(on) - 11 20 tr - 150 300 td(off) - 27 50 tf - 70 140 QT - 32 40 Q1 - 3.0 - Q2 - 7.0 - Q3 - 11 - - - 0.96 0.85 1.6 - trr - 63 - ta - 42 - tb - 21 - QRR - 0.140 - - - 3.5 4.5 - - - 7.5 - OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) (Note 3.) Static Drain-to-Source On-Resistance (VGS = 5.0 Vdc, ID = 7.5 Adc) (Cpk 2.0) (Note 3.) Drain-to-Source On-Voltage (VGS = 5.0 Vdc, ID = 15 Adc) (VGS = 5.0 Vdc, ID = 7.5 Adc, TJ = 150C) VGS(th) Vdc RDS(on) Ohm VDS(on) Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc) mV/C Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 30 Vdc, ID = 15 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 15 Adc, VGS = 5.0 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 15 Adc, VGS = 0 Vdc) (IS = 15 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 15 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die.) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1162 nH nH MTP15N06VL TYPICAL ELECTRICAL CHARACTERISTICS 7 " , " #$C 6$ 8 $ : 6 4$ $ 4 #$ # $ # 4 6 $ 9 : 7 8 6 C 4$ 4 #$ # $ $ 6 9 : Figure 2. Transfer Characteristics #$C 8 $$C 9 6 # $ $ #$ # 4 4$ 9 8 7 6$ $ , " #$C 6 # " $ 8 9 6 # Figure 3. On-Resistance versus Drain Current and Temperature $ $ #$ # 4 4$ 6 Figure 4. On-Resistance versus Drain Current and Gate Voltage " $ " :$ " , " #$ 9 < 4 Figure 1. On-Region Characteristics # 8 # , " C # " $ 6 #$C , " $$C $ $ $ 6$ 9 $ 6 # 8 9 6 # $ #$ #$ $ :$ #$ , , $ :$ $ $ # #$ 4 4$ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1163 6 6$ MTP15N06VL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) ## " # %!! " , " #$C *. 8 9 6 # (!! %!! 8 9 6 !! # (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1164 4 @ 7 8 #: #6 : 9 @ $ # 8 @# $ 6 # 4 7 # @4 $ , " #$ " $ $ # #$ 4 9 4 4$ ' ! MTP15N06VL , " #$ " $ " 4 " $ '( 'C 'CC ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS $ 6 , " #$ 4 " # 7 8 : 9 $ 6 4 # $ $$ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1165 MTP15N06VL " $ " #$ - , SAFE OPERATING AREA ! ! ! ! # " $ 7 8 : 9 $ 6 4 # #$ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' $ '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1166 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 # Preferred Device #$%& '( N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 20 AMPERES 60 VOLTS RDS(on) = 80 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 25 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 20 13 70 Adc Total Power Dissipation Derate above 25C PD 60 0.40 Watts W/C TJ, Tstg -55 to 175 C EAS 200 mJ Rating Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds G S MARKING DIAGRAM & PIN ASSIGNMENT Apk TO-220AB CASE 221A STYLE 5 1 C/W RJC RJA 2.5 62.5 TL 260 4 Drain 4 2 3 MTP20N06V LLYWW 1 Gate 3 Source 2 Drain C MTP20N06V LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP20N06V Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2001 January, 2001 - Rev. 3 1167 Publication Order Number: MTP20N06V/D MTP20N06V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 69 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.8 5.0 4.0 - Vdc mV/C - 0.065 0.080 - - - - 2.0 1.9 gFS 6.0 8.0 - mhos Ciss - 590 830 pF Coss - 180 250 Crss - 40 80 td(on) - 8.7 20 tr - 77 150 td(off) - 26 50 tf - 46 90 QT - 28 40 Q1 - 4.0 - Q2 - 9.0 - Q3 - 8.0 - - - 1.05 0.96 1.6 - trr - 60 - ta - 52 - tb - 8.0 - QRR - 0.172 - - - 3.5 4.5 - - - 7.5 - OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) (Note 3.) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 10 Adc) (Cpk 2.0) (Note 3.) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 10 Adc, TJ = 150C) VGS(th) RDS(on) Ohm VDS(on) Forward Transconductance (VDS = 6.0 Vdc, ID = 10 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 30 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 20 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 20 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1168 nH nH MTP20N06V TYPICAL ELECTRICAL CHARACTERISTICS , " #$C 4 : #$ # 9 $ $ $ 6 8 8 4 # 6 $ 9 : 7 8 C #$ # $ # #$C 8 9 $$C 6 # $ $ #$ # 4 4$ 6 9 : 7 8 " : 9 $ $ 6 4$ " " #$ :$ $ # 4 $ #$ 4$ 6 , " #$ #$ # $ $ #$ $ $ " 4 $ #$ $ :$ #$ , , 7 Figure 4. On-Resistance versus Drain Current and Gate Voltage # #$ 8 , " #$C Figure 3. On-Resistance versus Drain Current and Temperature < $ Figure 2. Transfer Characteristics $ 6 Figure 1. On-Region Characteristics , " C :$ 4 # #$C 6 , " $$C 4 " 9 4$ $ 4$ 6 7 " 6 :$ Figure 5. On-Resistance Variation with Temperature $ # 4 6 Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1169 9 MTP20N06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 9 *. 6 %!! # " " , " #$C (!! 8 %!! 9 6 # $ (!! !! $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1170 7 4 @ #: 8 #6 : # 9 8 @# @ $ $ 6 # 4 7 # , " #$ " # @4 $ $ # #$ 9 4 4 ' ! MTP20N06V , " #$ " # " 4 " '( 'C 'CC ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS # 8 9 , " #$ " 6 # 8 9 6 # $ $$ 9 9$ : :$ 8 8$ 7 7$ $ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1171 MTP20N06V SAFE OPERATING AREA # " # " #$ ! ! ! ! - , " # 8 9 6 # 8 9 6 # #$ $ :$ #$ :$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' $ '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1172 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 # Preferred Device #$%& '( N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 20 AMPERES 150 VOLTS RDS(on) = 130 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating S Symbol Value Unit Drain-Source Voltage VDSS 150 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 150 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 32 Vdc Drain - Continuous - Continuous @ 100C - Single Pulse (tp 10 s) ID ID IDM 20 12 60 Adc Total Power Dissipation Derate above 25C PD 112 0.9 Watts W/C Operating and Storage Temperature Range TJ, Tstg -55 to 150 C Single Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 120 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 0.3 mH) EAS 60 mJ Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds C/W RJC RJA 1.1 62.5 TL 260 C MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 TO-220AB CASE 221A STYLE 5 1 2 MTP20N15E LLYWW 1 Gate 3 3 Source 2 Drain MTP20N15E LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP20N15E Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2001 January, 2001 - Rev. 0 1173 Publication Order Number: MTP20N15E/D MTP20N15E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 150 - - TBD - - Vdc mV/C - - - - 10 100 - - - - 100 100 nAdc 2.0 - - TBD 4.0 - Vdc mV/C - 0.12 0.13 Ohm - - - - 2.8 2.6 gFS 8.0 11 - mhos Ciss - 1133 1627 pF Coss - 332 474 Crss - 105 174 td(on) - 11 25 tr - 77 153 td(off) - 33 67 tf - 49 97 QT - 39.1 55.9 Q1 - 7.5 - Q2 - 22 - Q3 - 17 - - - - - 1.5 - trr - 160 - ta - 123 - tb - 36.5 - QRR - 1.1 - OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Collector Current (VDS = 150 Vdc, VGS = 0 Vdc) (VDS = 150 Vdc, VGS = 0 Vdc, TJ = 125C) Adc IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS(f) IGSS(r) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 10 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 20 Adc) (ID = 10 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 13 Vdc, ID = 10 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 75 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (VDS = 120 Vdc, ID = 20 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 20 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1174 VSD Vdc ns C # Preferred Device #$%& '( N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 20 AMPERES 200 VOLTS RDS(on) = 160 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating S Symbol Value Unit Drain-Source Voltage VDSS 200 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 200 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 40 Vdc Vpk Drain - Continuous - Continuous @ 100C - Single Pulse (tp 10 s) ID ID IDM 20 12 60 Adc Total Power Dissipation Derate above 25C PD 125 1.0 Watts W/C TJ, Tstg -55 to 150 C EAS 600 mJ Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 1.00 62.5 TL 260 C 4 Drain 4 TO-220AB CASE 221A STYLE 5 Apk C/W RJC RJA MARKING DIAGRAM & PIN ASSIGNMENT 1 2 MTP20N20E LLYWW 1 Gate 3 3 Source 2 Drain MTP20N20E LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP20N20E Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 1175 Publication Order Number: MTP20N20E/D MTP20N20E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 200 - - 263 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - - 7.0 4.0 - Vdc mV/C - 0.12 0.16 Ohm - - - - 3.84 3.36 gFS 8.0 11 - mhos Ciss - 1880 2700 pF Coss - 378 535 Crss - 68 100 td(on) - 17 40 tr - 86 180 td(off) - 50 100 tf - 60 120 QT - 54 75 Q1 - 12 - Q2 - 24 - Q3 - 22 - - - 1.0 0.82 1.35 - trr - 239 - ta - 136 - tb - 103 - QRR - 2.09 - - - 3.5 4.5 - - - 7.5 - OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 10 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 20 Adc) (ID = 10 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 13 Vdc, ID = 10 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 100 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 160 Vdc, ID = 20 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure Fi 14) (See (IS = 20 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1176 nH nH MTP20N20E TYPICAL ELECTRICAL CHARACTERISTICS " 7 8 4 : # 9 6 , " #$ $ # 4 6 $ 9 : 7 8 #$ 4 #$ # $ Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics " 4 , " #$ # $ #$ $$ 6 8 9 #6 # # #8 4# 6 49 : , " #$ 9 $ 6 " 4 # $ #6 # 8 #$ $ :$ , , #$ # 9 # #6 #8 4# 49 6 , " #$ #$ 8 " " " 9 6 $ 6 Figure 4. On-Resistance versus Drain Current and Gate Voltage < Figure 3. On-Resistance versus Drain Current and Temperature # , " $$ # #$ 4 4$ 6 6$ $ $$ 9 9$ : :$ 8 8$ 4$ $ 4$ $ 6 $ #$ Figure 5. On-Resistance Variation with Temperature $ $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1177 # MTP20N20E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) $ " %!! " , " #$ *. 6 4 (!! %!! # !! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 1178 #$ # @ @# # 8 7 9 " # , " #$ 6 9 4 # @4 4 6 # @ " " # " , " #$ $ $ 9 ' ! 8 @ MTP20N20E '( 'C 'CC ' Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS # 9 " , " #$ # 8 6 $ $$ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1179 MTP20N20E SAFE OPERATING AREA " # " #$ - , F! F! F ! F ! 9 " # $ 6 4 # #$ Figure 11. Maximum Rated Forward Biased Safe Operating Area $ $ :$ #$ , , Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1180 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 # !# Preferred Device #$%& '( ! P-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 23 AMPERES 60 VOLTS RDS(on) = 120 m P-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 15 25 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 23 15 81 Adc Total Power Dissipation @ 25C Derate above 25C PD 90 0.60 Watts W/C TJ, Tstg -55 to 175 C EAS 794 mJ RJC RJA 1.67 62.5 C/W TL 260 C Rating Drain-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 23 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds MARKING DIAGRAM & PIN ASSIGNMENT Apk 4 Drain 4 TO-220AB CASE 221A STYLE 5 1 2 MTP23P06V LLYWW 1 Gate 3 3 Source 2 Drain MTP23P06V LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP23P06V Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 1181 Publication Order Number: MTP23P06V/D MTP23P06V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 60.5 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.8 5.3 4.0 - Vdc mV/C - 0.093 0.12 Ohm - - - - 3.3 3.2 5.0 11.5 - Ciss - 1160 1620 Coss - 380 530 Crss - 105 210 td(on) - 13.8 30 tr - 98.3 200 td(off) - 41 80 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 11.5 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc, ID = 23 Adc) (VGS = 10 Vdc, ID = 11.5 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 10.9 Vdc, ID = 11.5 Adc) Vdc gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 30 Vdc, ID = 23 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 23 Adc, VGS = 10 Vdc) tf - 62 120 QT - 38 50 Q1 - 7.0 - Q2 - 18 - Q3 - 14 - - - 2.2 1.8 3.5 - trr - 142.2 - ta - 100.5 - tb - 41.7 - QRR - 0.804 - - 3.5 4.5 - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 23 Adc, VGS = 0 Vdc) (IS = 23 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 23 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1182 nH nH MTP23P06V TYPICAL ELECTRICAL CHARACTERISTICS 8 6 7 : 4 # 9 $ 6 " , " #$C # 9 6 8 100C #$ # $ # , " C $$C 9 6 $ $ # #$ 4 4$ 6 6$ # 9 : 8 , " #$C $ $ " 7$ $ 7 8$ 8 Figure 3. On-Resistance versus Drain Current and Temperature $ $ # 4 4$ #$ 6 6$ $ Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 " " " $ < $ Figure 2. Transfer Characteristics 8 6 6 Figure 1. On-Region Characteristics #$C 9 4 #$C 4 # # , " $$C " 6 9 4$ $ 6 $ # 8 9 6 , " #$ # $ #$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature $ # 4 6 Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1183 9 MTP23P06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6 *. %!! 4 " " , " #$C (!! # %!! !! $ (!! $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1184 4 @ 7 8 @# @ : #: #6 # 9 8 $ $ 6 # 4 7 # @4 $ , " #$ " #4 $ # 4 #$ 4$ 9 4 6 ' ! MTP23P06V , " #$ " #4 " 4 " '( 'C 'CC ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS #$ , " #$ " # $ $ #$ $ :$ #$ $ :$ # ##$ #$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1185 MTP23P06V SAFE OPERATING AREA 8 " # " #$ - , ! ! ! " #4 : 9 $ 6 4 # #$ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1186 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 # " Preferred Device #$%& '( " N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 27 AMPERES 100 VOLTS RDS(on) = 70 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating S Symbol Value Unit Drain-to-Source Voltage VDSS 100 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 100 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 40 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 27 17 95 Adc Total Power Dissipation @ 25C Derate above 25C PD 104 0.83 Watts W/C TJ, Tstg -55 to 150 C EAS 109 mJ Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 75 Vdc, VGS = 10 Vdc, IL = 27 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 1.2 62.5 TL 260 C 4 Drain 4 TO-220AB CASE 221A STYLE 5 Apk C/W RJC RJA MARKING DIAGRAM & PIN ASSIGNMENT 1 2 MTP27N10E LLYWW 1 Gate 3 3 Source 2 Drain MTP27120E LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP27N10E Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 1187 Publication Order Number: MTP27N10E/D MTP27N10E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 100 - - 120 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 3.1 7.0 4.0 - Vdc mV/C - 0.058 0.07 - - - - 2.3 2.0 gFS 6.0 11 - mhos Ciss - 1131 1580 pF Coss - 468 660 Crss - 186 370 td(on) - 13 30 tr - 142 280 td(off) - 29 60 tf - 59 120 QT - 41 60 Q1 - 9.0 - Q2 - 25 - Q3 - 22 - - - 1.0 0.94 1.5 - trr - 126 - ta - 98 - tb - 28 - QRR - 0.685 - - 3.5 4.5 - - 7.5 - OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) (Note 3.) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 13.5 Adc) (Cpk 2.0) (Note 3.) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 27 Adc) (VGS = 10 Vdc, ID = 13.5 Adc, TJ = 125C) VGS(th) RDS(on) Ohm VDS(on) Forward Transconductance (VDS = 7.7 Vdc, ID = 13.5 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 50 Vdc, ID = 27 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 80 Vdc, ID = 27 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 27 Adc, VGS = 0 Vdc) (IS = 27 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 27 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1188 nH nH MTP27N10E TYPICAL ELECTRICAL CHARACTERISTICS 9 , " #$ 6 7 $ 9 " 8 4 : # 9 $ 6 4 , " $$ # $ 4 $ : 6 9 8 7 # # 4 " # , " 8 #$ 9 $$ 6 # 4 # 6 $ 9 8 : " 9$ 9 $$ $ $ 6$ 6 # 4 6 $ 9 Figure 4. On-Resistance versus Drain Current and Gate Voltage " " 4$ " , " #$ 8 < #6 , " #$ :$ Figure 3. On-Resistance versus Drain Current and Temperature ## # 6 $ 9 : 8 7 Figure 2. Transfer Characteristics Figure 1. On-Region Characteristics 6 #$ 9 6 # 8 9 6 # $ #$ #$ $ :$ , , #$ $ Figure 5. On-Resistance Variation with Temperature # 6 9 8 4 $ : Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1189 7 MTP27N10E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 4$ *. 4 %!! " " , " #$ #$ # %!! $ (!! !! $ $ (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1190 9 , " #$ " #: 7 8 $6 @ 68 : 9 @ 6# 49 @# $ 4 6 #6 4 8 # # $ 9 @4 #$ $ # 4 4$ @ 6 6$ " $ " #: " , " #$ ' ! MTP27N10E '( 'C 'CC ' Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 4 " , " #$ #$ # $ $ 9 9$ : :$ 8 8$ 7 7$ $ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1191 MTP27N10E SAFE OPERATING AREA # " # " #$ - , F! F! F ! F ! " #: 8 9 6 # #$ Figure 11. Maximum Rated Forward Biased Safe Operating Area $ $ :$ #$ , , Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 # $ $ ' '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1192 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 # ) Preferred Device #$%& '( P-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 12 AMPERES 60 VOLTS RDS(on) = 230 m P-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 15 25 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 12 8.0 42 Adc Total Power Dissipation Derate above 25C PD 60 0.40 Watts W/C TJ, Tstg -55 to 175 C 216 mJ Rating Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds EAS MARKING DIAGRAM & PIN ASSIGNMENT Apk TO-220AB CASE 221A STYLE 5 1 C/W RJC RJA 2.5 62.5 TL 260 4 Drain 4 2 MTP2955V LLYWW 1 Gate 3 3 Source 2 Drain C MTP2955V LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP2955V Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 4 1193 Publication Order Number: MTP2955V/D MTP2955V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 58 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.8 5.0 4.0 - Vdc mV/C - 0.185 0.230 - - - - 2.9 2.5 gFS 3.0 5.0 - mhos Ciss - 550 700 pF Coss - 200 280 Crss - 50 100 td(on) - 15 30 tr - 50 100 td(off) - 24 50 tf - 39 80 QT - 19 30 Q1 - 4.0 - Q2 - 9.0 - Q3 - 7.0 - - - 1.8 1.5 3.0 - trr - 115 - ta - 90 - tb - 25 - QRR - 0.53 - - 4.5 - - 7.5 - OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) (Note 3.) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 6.0 Adc) (Cpk 1.5) (Note 3.) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 12 Adc) (VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150C) VGS(th) RDS(on) Ohm VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 30 Vdc, ID = 12 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 12 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 12 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1194 nH nH MTP2955V TYPICAL ELECTRICAL CHARACTERISTICS #6 7 8 : $ 9 $ # 4 6 $ 9 : 8 7 $ # 7 9 4 # 6 $ 9 : 8 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 7 # #6 #$ " 4$ , " #$C ##$ 4 " # , " C #$ :$ #$C # $ $ $ #$ F$$C $ :$ 4 9 7 8 $ # #6 # $ Figure 3. On-Resistance versus Drain Current and Temperature # 8 9 9 4 7 8 # $ Figure 4. On-Resistance versus Drain Current and Gate Voltage " " " 9 6 < C #$C 4 6 , " F$$C 8 $ # " # , " #$C #$ # 8 9 , " #$C C 6 # F$ F#$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature 4 6 # $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1195 9 MTP2955V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 8 *. 9 6 # " " , " #$C %!! (!! 8 %!! 9 6 !! # (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1196 4 @ 7 8 @ #: #6 @# : # 9 8 $ $ 6 # 4 " # 7 , " #$ 9 # @4 # 6 9 8 # 6 9 8 4 # ' ! MTP2955V " 4 " # " , " #$ '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS # " , " #$ 7 8 : 9 $ 6 4 # $ : 7 4 $ : 7 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1197 MTP2955V SAFE OPERATING AREA ##$ " $ " #$ - , ! ! ! " # # :$ $ #$ :$ $ #$ #$ $ :$ #$ :$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # $ *0 # $ ' '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1198 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 # ) Preferred Device #$%& '( ) N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls. These devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 29 AMPERES 150 VOLTS RDS(on) = 70 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 150 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 150 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM ? 20 ? 40 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 29 19 102 Adc Total Power Dissipation Derate above 25C PD 125 1.0 Watts W/C TJ, Tstg -55 to 150 C 421 mJ Rating Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 29 Apk, L = 1.0 mH, RG = 25 W) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds EAS S MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 TO-220AB CASE 221A STYLE 5 Apk 1 2 MTP29N15E LLYWW 1 Gate 3 3 Source 2 Drain C/W RJC RJA 1.0 62.5 TL 260 MTP29N15E LL Y WW = Device Code = Location Code = Year = Work Week C ORDERING INFORMATION Device MTP29N15E Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 1199 Publication Order Number: MTP29N15E/D MTP29N15E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 150 - - 151 - - - - - - 10 100 - - 100 2.0 - 2.7 5.4 4.0 - - 0.054 0.07 - - - - 2.4 2.1 gFS 10 20 - mhos Ciss - 2300 3220 pF Coss - 450 630 Crss - 130 260 td(on) - 19 40 tr - 95 190 td(off) - 90 180 OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 150 Vdc, VGS = 0 Vdc) (VDS = 150 Vdc, VGS = 0 Vdc, TJ =125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 14.5 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 29 Adc) (VGS = 10 Vdc, ID = 14.5 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 8.6 Vdc, ID = 14.5 Adc) Vdc mV/C Ohms Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 75 Vdc, ID = 29 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 120 Vdc, ID = 29 Adc, VGS = 10 Vdc) tf - 85 170 QT - 83 120 Q1 - 12 - Q2 - 37 - Q3 - 23 - - - 0.92 0.84 1.3 - trr - 174 - ta - 126 - tb - 48 - QRR - 1.4 - - - 3.5 4.5 - - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS VSD Forward On-Voltage (IS = 29 Adc, VGS = 0 Vdc) (IS = 29 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 29 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1200 nH MTP29N15E TYPICAL ELECTRICAL CHARACTERISTICS : " 7 $ , " #$ 8 9 6 4 $$ # $ 9 9$ 9 # 6 4 $ 9 : 8 $ 6 4 # , " 6$ 6 7 $$ 4 # #$ 9 6 $$ # # 4 6 9 $ 8 :$ : 8 , " #$ 9$ " 9 $ $$ $ 6$ 6 # 6 4 Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage " " " 6$ $ #$ :$ $ $ ##$ # 9 : < , " $ Figure 2. Transfer Characteristics " # 6 Figure 1. On-Region Characteristics 6 #$ 9 , " #$ #$ #$ ?$ ?#$ #$ $ :$ #$ $ , , Figure 5. On-Resistance Variation with Temperature # # 6 9 8 6 Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1201 9 MTP29N15E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: *. td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) :$ " " : 9$ %!! 9 $$ $ (!! 6$ 6 4$ 4 #$ # $ (!! $ $ $ , " #$ %!! !! $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1202 # @ 7 8 : @ 9 8 @# $ 9 6 6 4 , " #$ " #7 # @4 # # 4 6 9 $ : 8 7 'C 'CC ' ! MTP29N15E ' '( @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 4 " , " #$ #$ # $ $ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current http://onsemi.com 1203 MTP29N15E %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the 6$ " # " #$ m! m! - , ! ! " #7 6 4$ 4 #$ # $ $ #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 1204 MTP29N15E TYPICAL ELECTRICAL CHARACTERISTICS ('.. < " $ # $ *0 # ' '# - - " '&'# $ 4 6 # ' !1! Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 1205 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 MTP29N15E TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 1206 # # Preferred Device #$%& '( P-Channel TO-220 This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage-blocking capability without degrading performance over time. In addition, this Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Robust High Voltage Termination * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 2 AMPERES 500 VOLTS RDS(on) = 6 P-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit VDSS 500 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 500 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 40 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 2.0 1.6 6.0 Adc Total Power Dissipation Derate above 25C PD 75 0.6 Watts W/C TJ, Tstg -55 to 150 C EAS 80 mJ RJC RJA 1.67 62.5 TL 260 Rating Drain-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 100 Vdc, VGS = 10 Vdc, IL = 4.0 Apk, L = 10 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 TO-220AB CASE 221A STYLE 5 Apk 1 C/W C 2 MTP2P50E LLYWW 1 Gate 3 3 Source 2 Drain MTP2P50E LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP2P50E Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 1207 Publication Order Number: MTP2P50E/D MTP2P50E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 500 - - 564 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 3.0 4.0 4.0 - Vdc mV/C - 4.5 6.0 Ohm - - 9.5 - 14.4 12.6 gFS 0.5 - - mhos Ciss - 845 1183 pF Coss - 100 140 Crss - 26 52 td(on) - 12 24 tr - 14 28 td(off) - 21 42 tf - 19 38 QT - 19 27 Q1 - 3.7 - Q2 - 7.9 - Q3 - 9.9 - - - 2.3 1.85 3.5 - trr - 223 - ta - 161 - tb - 62 - QRR - 1.92 - - - 3.5 4.5 - - - 7.5 - OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 500 Vdc, VGS = 0 Vdc) (VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 1.0 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 2.0 Adc) (ID = 1.0 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 250 Vdc, ID = 2.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 400 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 2.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 14) 2 0 Adc, Adc VGS = 0 Vdc, Vdc (IS = 2.0 dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1208 nH nH MTP2P50E TYPICAL ELECTRICAL CHARACTERISTICS 6 4$ 4 9 #$ # $ $ 4 #$ #$ # $ 6 # 8 9 # #6 # 4$ 6 $ 6$ $$ 9 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics , " 8 9 #$ 6 $$ # $ # #$ $ 4 4$ 6 9 , " #$ $:$ $$ $#$ $ " 6:$ $ 6$ 6#$ 6 # 4 $ #$ 6 4$ " " " , " #$ $ $ #$ : 9$ Figure 4. On-Resistance versus Drain Current and Gate Voltage # $ $ 4 #$ " #8 Figure 3. On-Resistance versus Drain Current and Temperature GG < , " $$ $ 6 4$ 8 $ GG 6 : GG " , " #$ #$ $ :$ #$ $ #$ $ $ # #$ 4 4$ 6 , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1209 6$ $ MTP2P50E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 8 9 " , " #$ %!! # *. *. 6 " %!! 8 9 (!! 6 # %!! !! (!! !! (!! $ " , " #$ $ $ # #$ Figure 7b. High Voltage Capacitance Variation Figure 7a. Capacitance Variation http://onsemi.com 1210 MTP2P50E #$ 8 # @ @# 9 $ " # , " #$ 6 # $ @4 # 6 9 8 # 6 9 # 8 ' ! GG 4 @ GG # " #$ " # " , " #$ 'CC 'C '( ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS # " , " #$ 9 # 8 6 9 8 # 6 9 8 # ## #6 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1211 MTP2P50E SAFE OPERATING AREA 8 " # " #$ - , ! ! ! ! 9 6 # " # #$ $ :$ $ #$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ ' $ ,' " (' , - . / / ' ,*0 " *0 ,' # 6 '# - - " '&'# 4 # ' ! 5 Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1212 5 #! Preferred Device #$%& '( N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * On-resistance Area Product about One-half that of Standard MOSFETs with New Low Voltage, Low RDS(on) Technology * Faster Switching than E-FET Predecessors * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature * Static Parameters are the Same for both TMOS V and TMOS E-FET http://onsemi.com 12 AMPERES 50 VOLTS RDS(on) = 150 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) S Symbol Value Unit Drain-Source Voltage VDSS 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Rating Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) 4 Drain 4 VGS VGSM 20 25 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 12 7.3 37 Adc Total Power Dissipation @ 25C Derate above 25C PD 48 0.32 Watts W/C TJ, Tstg -55 to 175 C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25 ) EAS 72 mJ Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient RJC RJA 3.13 62.5 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 260 C Operating and Storage Temperature Range MARKING DIAGRAM & PIN ASSIGNMENT TO-220AB CASE 221A STYLE 5 Apk 1 2 MTP3055V LLYWW 1 Gate 3 3 Source 2 Drain MTP3055V LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP3055V Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2001 February, 2001 - Rev. 3 1213 Publication Order Number: MTP3055V/D MTP3055V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 65 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.7 5.4 4.0 - Vdc mV/C - 0.10 0.15 Ohm - - 1.3 - 2.2 1.9 gFS 4.0 5.0 - mhos Ciss - 410 500 pF Coss - 130 180 Crss - 25 50 td(on) - 7.0 10 tr - 34 60 td(off) - 17 30 tf - 18 50 QT - 12.2 17 Q1 - 3.2 - Q2 - 5.2 - Q3 - 5.5 - - - 1.0 0.91 1.6 - trr - 56 - ta - 40 - tb - 16 - QRR - 0.128 - - 3.5 4.5 - - 7.5 - OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 6.0 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 12 Adc) (ID = 6.0 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 7.0 Vdc, ID = 6.0 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 30 Vdc, ID = 12 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 12 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (S Figure (See Fi 15) Adc VGS = 0 Vdc, Vdc (IS = 12 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1214 nH nH MTP3055V TYPICAL ELECTRICAL CHARACTERISTICS " 7 , " #$C # #6 8 #6 : 9 # 9 8 $ , " F$$C # #$C C 9 # 8 6 6 6 # 4 6 9 : 7 8 Figure 2. Transfer Characteristics , " C $ #$C F$$C $ 6 # 8 9 # #6 $ , " #$C 6 4 # " $ 7 8 6 Figure 3. On-Resistance versus Drain Current and Temperature # 9 8 # #6 Figure 4. On-Resistance versus Drain Current and Gate Voltage 9 " " 9 < $ Figure 1. On-Region Characteristics " 6 6 # 4 # 4 #$ $ # " , " #$C 8 9 F$ F#$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature 4 6 # $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1215 9 MTP3055V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) # " *. " , " #$C %!! 8 9 (!! %!! 6 !! # (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1216 MTP3055V " 4 " # " , " #$ $ @ 8 @# 6 9 4 6 # # " # , " #$ @4 # 4 6 $ 9 : 8 7 # 4 ' ! 9 @ # '( 'CC 'C ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 4 7 8 # " , " #$ # @ # &' " &! " #$ , " #$ 6 9 8 8 9 6 # $ $$ 9 9$ : :$ 8 8$ # 7 7$ Figure 10. Stored Charge Figure 11. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1217 MTP3055V SAFE OPERATING AREA :$ " # " #$ - , ! ! ! ! " # $ #$ #$ $ :$ #$ :$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # $ *0 # ' '# - - " '&'# $ 6 4 # ' ! Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 1218 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 #! Preferred Device #$%& '( * %+% N-Channel TO-220 http://onsemi.com This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature 12 AMPERES 60 VOLTS RDS(on) = 180 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Gate-Source Voltage - Continuous - Single Pulse (tp 50 s) VGS VGSM 15 20 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 12 8.0 42 Adc Total Power Dissipation @ 25C Derate above 25C PD 48 0.32 Watts W/C TJ, Tstg -55 to 175 C 72 mJ Rating Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 12 Apk, L = 1.0 mH, RG =25 ) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds EAS G S MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 Apk TO-220AB CASE 221A STYLE 5 1 2 3 MTP3055VL LLYWW 1 Gate C/W RJC RJA 3.13 62.5 TL 260 C 3 Source 2 Drain MTP3055VL LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP3055VL Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 1219 Publication Order Number: MTP3055VL/D MTP3055VL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 62 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 1.0 - 1.6 3.0 2.0 - Vdc mV/C - 0.12 0.18 Ohm - - 1.6 - 2.6 2.5 gFS 5.0 8.8 - mhos Ciss - 410 570 pF Coss - 114 160 Crss - 21 40 td(on) - 9.0 20 tr - 85 190 td(off) - 14 30 tf - 43 90 QT - 8.1 10 Q1 - 1.8 - Q2 - 4.2 - Q3 - 3.8 - - - 0.97 0.86 1.3 - trr - 55.7 - ta - 37 - tb - 18.7 - QRR - 0.116 - - 3.5 4.5 - - 7.5 - OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 5.0 Vdc, ID = 6.0 Adc) RDS(on) Drain-Source On-Voltage (VGS = 5.0 Vdc) (ID = 12 Adc) (ID = 6.0 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 8.0 Vdc, ID = 6.0 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 30 Vdc, ID = 12 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 12 Adc, VGS = 5.0 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (S Figure (See Fi 14) Adc VGS = 0 Vdc, Vdc (IS = 12 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1220 nH nH MTP3055VL TYPICAL ELECTRICAL CHARACTERISTICS #6 9 6$ 6 # 4$ 8 4 #$ 4# # 6 4 # 9 # 8 6 4 4$ 6 6$ $$ $ Figure 2. Transfer Characteristics , " C 6 #$C F$$C 8 6 # 8 # 9 #6 #: ## : $ # : " 6 $ $ #$ $ :$ #$ $ 8 # 9 # #6 Figure 4. On-Resistance versus Drain Current and Gate Voltage " $ " 9 F#$ 9 , " #$C Figure 3. On-Resistance versus Drain Current and Temperature < #$ Figure 1. On-Region Characteristics # F$ C " $ # , " F$$C #$C #9 # # $ # 6 #6 $ " , " #$C :$ " , " #$C C , , 4 # 6 $ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1221 9 MTP3055VL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6 *. " " # , " #$C %!! 8 9 %!! (!! 6 !! # (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1222 9 @ $ 6 6 4 # @# @ # " # , " #$ @4 # 6 9 8 ' ! 9 MTP3055VL " 4 " # " $ , " #$ '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS # " , " #$ 8 9 6 # $ $$ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1223 MTP3055VL SAFE OPERATING AREA :$ " $ " #$ - , ! ! ! ! $ #$ " # #$ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # $ *0 # $ ' '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1224 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 #! Preferred Device #$%& '( ! * %+% N-Channel TO-220 http://onsemi.com This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature 30 AMPERES 60 VOLTS RDS(on) = 50 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 15 20 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 30 20 105 Adc Total Power Dissipation Derate above 25C PD 90 0.6 Watts W/C TJ, Tstg -55 to 175 C EAS 154 mJ Rating Drain-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5 Vdc, Peak IL = 30 Apk, L = 0.342 mH, RG = 25 ) Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds G S MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 Apk TO-220AB CASE 221A STYLE 5 1 RJC RJA 1.67 62.5 C/W TL 260 C 2 3 MTP30N06VL LLYWW 1 Gate 3 Source 2 Drain MTP30N06VL LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTP30N06VL TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 5 1225 Publication Order Number: MTP30N06VL/D MTP30N06VL ELECTRICAL CHARACTERISTICS (TJ = 25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 63 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 1.0 - 1.5 4.0 2.0 - Vdc mV/C - 0.033 0.05 Ohm - - - - 1.8 1.73 gFS 13 21 - Mhos Ciss - 1130 1580 pF Coss - 360 500 Crss - 95 190 td(on) - 14 30 tr - 260 520 td(off) - 54 110 tf - 108 220 QT - 27 40 Q1 - 5 - Q2 - 17 - Q3 - 15 - - - 0.98 0.89 1.6 - trr - 86.4 - ta - 49.6 - tb - 36.8 - QRR - 0.228 - - 4.5 - - 7.5 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150 C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 5 Vdc, ID = 15 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 5 Vdc, ID = 30 Adc) (VGS = 5 Vdc, ID = 15 Adc, TJ = 150 C) VDS(on) Forward Transconductance (VDS = 6.25 Vdc, ID = 15 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 30 Vdc, ID = 30 Adc, VGS = 5 Vdc, Vdc RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 30 Adc, VGS = 5 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 30 Adc, VGS = 0 Vdc) (IS = 30 Adc, VGS = 0 Vdc, TJ = 150 C) Reverse Recovery Time Adc VGS = 0 Vdc, Vdc (IS = 30 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1226 nH nH MTP30N06VL TYPICAL ELECTRICAL CHARACTERISTICS " 8 9 $ 6 6 4 # 4 8 # 4 6 $ 9 : 8 100C 6 4 # 7 6 $ Figure 2. Transfer Characteristics 6 #$C 4 # F$$C 6 # 4 $ 9 9 9 , " #$C $ " $ 6 4 # Figure 3. On-Resistance versus Drain Current and Temperature 6 # 4 $ 9 Figure 4. On-Resistance versus Drain Current and Gate Voltage # " $ " $ " , " #$C 6 < 4 Figure 1. On-Region Characteristics $ 9 # , " C 8 9 #$C " : , " $$C $ $ 9 , " #$C 9 # 8 9 C 6 # F$ F#$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature 4 # 6 $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1227 9 MTP30N06VL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) $ *. 6$ %!! 6 " " , " #$C 4$ 4 (!! #$ # $ %!! $ !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1228 4 6$ #: 6 #6 @ 4$ @# @ 4 # 8 #$ $ # # $ @4 $ $ $ 9 4 7 , " #$ " 4 #$ # ' ! $ MTP30N06VL , " #$ " 4 " 4 " $ '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 4 #$ , " #$ " # $ $ $ $$ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1229 MTP30N06VL SAFE OPERATING AREA " # " #$ 9 - , ! ! ! ! " 4 6 # 8 9 6 # #$ $ :$ #$ :$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # $ ' '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1230 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 #!# Preferred Device #$%& '( ! P-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 30 AMPERES 60 VOLTS RDS(on) = 80 m P-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 15 25 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 30 19 105 Adc Total Power Dissipation @ 25C Derate above 25C PD 125 0.83 Watts W/C TJ, Tstg -55 to 175 C EAS 450 mJ RJC RJA 1.2 62.5 C/W TL 260 C Rating Drain-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 30 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds MARKING DIAGRAM & PIN ASSIGNMENT Apk 4 Drain 4 TO-220AB CASE 221A STYLE 5 1 2 MTP30P06V LLYWW 1 Gate 3 3 Source 2 Drain MTP30P06V LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP30P06V Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 1231 Publication Order Number: MTP30P06V/D MTP30P06V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 62 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.6 5.3 4.0 - Vdc mV/C - 0.067 0.08 Ohm - - 2.0 - 2.9 2.8 5.0 7.9 - Ciss - 1562 2190 Coss - 524 730 Crss - 154 310 td(on) - 14.7 30 tr - 25.9 50 td(off) - 98 200 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 15 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc, ID = 30 Adc) (VGS = 10 Vdc, ID = 15 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 8.3 Vdc, ID = 15 Adc) Vdc gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 30 Vdc, ID = 30 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 30 Adc, VGS = 10 Vdc) tf - 52.4 100 QT - 54 80 Q1 - 9.0 - Q2 - 26 - Q3 - 20 - - - 2.3 1.9 3.0 - trr - 175 - ta - 107 - tb - 68 - QRR - 0.965 - - 3.5 4.5 - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 30 Adc, VGS = 0 Vdc) (IS = 30 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 30 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1232 nH nH MTP30P06V TYPICAL ELECTRICAL CHARACTERISTICS 7 : 6 4 9 # $ 6 # # 6 9 8 4 , " $$C # 6 $ 9 : Figure 2. Transfer Characteristics , " C #$C 9 $$C 6 # # 4 6 $ 9 8 8 , " #$C " : $ 9 $ 6 Figure 3. On-Resistance versus Drain Current and Temperature # 4 6 $ 9 Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 " " " $ , " #$ < 4 Figure 1. On-Region Characteristics 8 6 # " 9 #$C 6 # 100C $ 8 " $ 9 , " #$C 9 # 8 9 6 # $ #$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature $ 9 # 4 6 Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1233 : MTP30P06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 9 %!! *. $ 6 " " , " #$C (!! 4 %!! # !! $ (!! $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1234 7 4 #: @ 8 #6 @# @ : # 9 8 $ $ 6 # 4 7 # @4 , " #$ " 4 # 4 6 $ 9 4 9 ' ! MTP30P06V , " #$ " 4 " 4 " 'CC 'C '( ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 4 , " #$ " #$ # $ $ # 6 9 8 # 6 9 8 # ## Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1235 MTP30P06V SAFE OPERATING AREA " # " #$ 6$ - , ! ! ! ! " 4 6 4$ 4 #$ # $ $ #$ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' $ '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1236 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 #! Preferred Device #$%& '( ! N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 32 AMPERES 60 VOLTS RDS(on) = 40 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 20 25 Vdc Vpk Drain Current - Continuous @ 25 C Drain Current - Continuous @ 100 C Drain Current - Single Pulse (tp 10 s) ID ID IDM 32 22.6 112 Adc Total Power Dissipation @ 25 C Derate above 25 C PD 90 0.6 Watts W/C TJ, Tstg -55 to 175 C EAS 205 mJ Rating Drain-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 32 Apk, L = 0.1 mH, RG = 25 ) Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds G S MARKING DIAGRAM & PIN ASSIGNMENT Apk RJC RJA 1.67 62.5 C/W TL 260 C 4 Drain 4 TO-220AB CASE 221A STYLE 5 1 2 3 MTP30N06V LLYWW 1 Gate 3 Source 2 Drain MTP30N06V LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP36N06V Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 1237 Publication Order Number: MTP36N06V/D MTP36N06V ELECTRICAL CHARACTERISTICS (TJ = 25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 61 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.6 6.0 4.0 - Vdc mV/C - 0.034 0.04 Ohm - - 1.25 - 1.54 1.47 gFS 5.0 7.83 - mhos Ciss - 1220 1700 pF Coss - 337 470 Crss - 74.8 150 td(on) - 14 30 tr - 138 270 td(off) - 54 100 tf - 91 180 QT - 39 50 Q1 - 7.0 - Q2 - 17 - Q3 - 13 - - - 1.03 0.94 2.0 - trr - 92 - ta - 64 - tb - 28 - QRR - 0.332 - - 3.5 4.5 - - 7.5 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150 C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 16 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 32 Adc) (VGS = 10 Vdc, ID = 16 Adc, TJ = 150 C) VDS(on) Forward Transconductance (VDS = 7.6 Vdc, ID = 16 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 30 Vdc, ID = 32 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 32 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 32 Adc, VGS = 0 Vdc) (IS = 32 Adc, VGS = 0 Vdc, TJ = 150 C) Reverse Recovery Time Adc VGS = 0 Vdc, Vdc (IS = 32 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1238 nH nH MTP36N06V TYPICAL ELECTRICAL CHARACTERISTICS :# : 7 $6 8 9 49 $ 8 , " C :# " , " #$C #$C $6 49 8 $$C 6 # 6 4 9 : Figure 2. Transfer Characteristics , " C 9 #$C 6 F$$C # 8 $6 49 :# $# 8 7 , " #$C 66 " 49 #8 $ 8 Figure 3. On-Resistance versus Drain Current and Temperature 49 $6 :# Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 " " " 9 , " #$C < $ Figure 1. On-Region Characteristics " 9 6 4 8 # 6 # C 25C 8 9 F$ F#$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature 4 # 6 $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1239 9 MTP36N06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6 *. " 4 " , " #$C %!! # %!! (!! !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1240 @ #$ 8 # @# @ $ 9 6 @4 # , " #$ " 4# $ $ $ # #$ 4 4$ 6 ' ! 4 # MTP36N06V , " #$ " 4# " 4 " '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 4# , " #$ " #6 9 8 $ $$ 9 9$ : :$ 8 8$ 7 7$ $ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1241 MTP36N06V SAFE OPERATING AREA " # " #$ ##$ - , ! ! ! ! :$ $ #$ :$ $ #$ " 4# # #$ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1242 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 # Preferred Device #$%& '( N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 40 AMPERES 100 VOLTS RDS(on) = 40 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 100 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 100 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM ? 20 ? 40 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 40 29 140 Adc Total Power Dissipation Derate above 25C PD 169 1.35 Watts W/C TJ, Tstg -55 to 150 C 800 mJ Rating Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 75 Vdc, VGS = 10 Vdc, Peak IL = 40 Apk, L = 1.0 mH, RG = 25 W) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds EAS S MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 TO-220AB CASE 221A STYLE 5 Apk 1 2 MTP40N10E LLYWW 1 Gate 3 3 Source 2 Drain C/W RJC RJA 0.74 62.5 TL 260 MTP40N10E LL Y WW = Device Code = Location Code = Year = Work Week C ORDERING INFORMATION Device MTP40N10E Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 1243 Publication Order Number: MTP40N10E/D MTP40N10E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 100 - - 112 - - - - - - 10 100 - - 100 2.0 - 2.9 6.7 4.0 - - 0.033 0.04 - - - - 1.9 1.7 gFS 17 21 - mhos Ciss - 2305 3230 pF Coss - 620 1240 Crss - 205 290 td(on) - 19 40 OFF CHARACTERISTICS V(BR)DSS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) (Cpk 2.0) (Note 3.) Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ =125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) (Note 3.) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 20 Adc) (Cpk 2.0) (Note 3.) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 40 Adc) (VGS = 10 Vdc, ID = 20 Adc, TJ = 125C) VGS(th) Vdc RDS(on) Ohms VDS(on) Forward Transconductance (VDS = 8.4 Vdc, ID = 20 Adc) mV/C Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 50 Vdc, ID = 40 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 80 Vdc, ID = 40 Adc, VGS = 10 Vdc) tr - 165 330 td(off) - 75 150 tf - 97 190 QT - 80 110 Q1 - 15 - Q2 - 40 - Q3 - 29 - - - 0.96 0.88 1.0 - trr - 152 - ta - 117 - tb - 35 - QRR - 1.0 - - - 3.5 4.5 - - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage VSD (IS = 40 Adc, VGS = 0 Vdc) (IS = 40 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 14) (IS = 40 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Cpk + Max limit - Typ 3 sigma http://onsemi.com 1244 nH MTP40N10E TYPICAL ELECTRICAL CHARACTERISTICS " : 7 9 8 , " #$ 8 8 : $ 6 9 4 # $ # 4 6 $ 9 : 8 $ , " $$ 6 4 # 7 # 4 6 $ 9 : $ #$ 4 $$ # # 4 6 $ 9 : 8 , " 6 $ , " #$ 6$ 6 " 4$ 4 $ #$ # $ # # 9 4 6 $ 9 : 8 Figure 4. On-Resistance versus Drain Current and Gate Voltage " " " # 6 < Figure 3. On-Resistance versus Drain Current and Temperature 8 8 Figure 2. Transfer Characteristics " 9 #$ 9 Figure 1. On-Region Characteristics : : # 8 9 , " #$ 6 # $ #$ #$ $ :$ , , #$ $ Figure 5. On-Resistance Variation with Temperature # 4 6 9 : 8 $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1245 7 MTP40N10E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 8 *. 9 $ " " : , " #$C %!! (!! 6 4 %!! # !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1246 MTP40N10E 8 96 : $9 9 68 @ @# $ 6 6 4# 4 # 4 6 $ 9 '( 'C 'CC 9 @4 #6 " 6 , " #$ # " $ " 6 " , " #$ :# @ ' ! 7 8 : 8 8 ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 6 " , " #$ 4$ 4 #$ # $ $ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1247 MTP40N10E SAFE OPERATING AREA 8 m! " # " #$ m! - , ! ! " 6 : 9 $ 6 4 # #$ $ :$ #$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' !1! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1248 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 # Preferred Device #$%& '( N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * On-resistance Area Product about One-half that of Standard MOSFETs with New Low Voltage, Low RDS(on) Technology * Faster Switching than E-FET Predecessors * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature * Static Parameters are the Same for both TMOS V and TMOS E-FET http://onsemi.com 42 AMPERES 60 VOLTS RDS(on) = 28 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) S Symbol Value Unit Drain-Source Voltage VDSS 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Rating Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) 4 Drain 4 VGS VGSM 20 25 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 42 30 147 Adc Total Power Dissipation @ 25C Derate above 25C PD 125 0.83 Watts W/C TJ, Tstg -55 to 175 C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc IL = 42 Apk, L = 0.454 H, RG = 25 ) EAS 400 mJ Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient RJC RJA 1.2 62.5 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 260 C Operating and Storage Temperature Range MARKING DIAGRAM & PIN ASSIGNMENT TO-220AB CASE 221A STYLE 5 Apk 1 2 MTP50N06V LLYWW 1 Gate 3 3 Source 2 Drain MTP50N06V = Device Code LL = Location Code Y = Year WW = Work Week ORDERING INFORMATION Device MTP50N06V Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2001 February, 2001 - Rev. 4 1249 Publication Order Number: MTP50N06V/D MTP50N06V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 69 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.7 3.0 4.0 - Vdc mV/C - 0.025 0.028 Ohm - - 1.4 - 1.7 1.6 gFS 16 23 - mhos Ciss - 1644 2320 pF Coss - 465 660 Crss - 112 230 td(on) - 12 20 tr - 122 250 td(off) - 64 110 tf - 54 90 QT - 47 70 Q1 - 9 - Q2 - 21 - Q3 - 16 - - - 1.06 0.99 2.5 - trr - 84 - ta - 73 - tb - 11 - QRR - 0.28 - - 3.5 4.5 - - 7.5 - OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 21 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 42 Adc) (ID = 21 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 6.25 Vdc, ID = 20 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 25 Vdc, ID = 42 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 42 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 42 Adc, VGS = 0 Vdc) (IS = 42 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (S Figure (See Fi 14) Adc VGS = 0 Vdc, Vdc (IS = 42 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1250 nH nH MTP50N06V TYPICAL ELECTRICAL CHARACTERISTICS 7 8 : 9 9 6 $ # 8 " , " #$C 6 8 9 #6 4# , " F$$C 9 6 # 6 $ 9 8 : Figure 2. Transfer Characteristics #8 #$C ## 9 F$$C 6 9 # 8 44 7 , " #$C 4 #: " #6 $ # Figure 3. On-Resistance versus Drain Current and Temperature # 6 9 8 Figure 4. On-Resistance versus Drain Current and Gate Voltage #$ " " " # , " #$C $ C #$C $ $ 4 Figure 1. On-Region Characteristics , " C < # " # C #$C 46 8 6 #$ #$ $ :$ #$ $ :$ , , 4 6 # $ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1251 9 MTP50N06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 9 " *. $ " , " #$C %!! 6 4 (!! # %!! !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1252 # 68 @ 6 8 4# @# @ 9 #6 6 9 # @4 " 6# , " #$ 8 # 6 4 $ " 9 " 6# " , " #$ '( 'C ' ! $9 6 MTP50N06V 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS $ " , " #$ 6 4 # $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1253 MTP50N06V SAFE OPERATING AREA 6 " # " #$ ! ! - , ! ! " 6# 4# #6 9 8 #$ $ :$ #$ $ , , :$ Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # $ *0 # ' $ '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1254 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 # Preferred Device #$%& '( * %+% N-Channel TO-220 http://onsemi.com This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature 42 AMPERES 60 VOLTS RDS(on) = 32 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 15 20 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 42 30 147 Adc Total Power Dissipation @ 25C Derate above 25C PD 125 0.83 Watts W/C TJ, Tstg -55 to 175 C EAS 265 mJ Rating Drain-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5 Vdc, Peak IL = 42 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds G S MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 Apk TO-220AB CASE 221A STYLE 5 1 RJC RJA 1.2 62.5 C/W TL 260 C 2 3 MTP50N06VL LLYWW 1 Gate 3 Source 2 Drain MTP50N06VL LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTP50N06VL TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 1255 Publication Order Number: MTP50N06VL/D MTP50N06VL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 64 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 1.0 - 1.4 4.3 2.0 - Vdc mV/C - 0.025 0.032 Ohm - - - - 1.6 1.5 gFS 17 28 - Mhos Ciss - 1570 2200 pF Coss - 508 710 Crss - 135 270 td(on) - 16 30 tr - 355 701 td(off) - 80 160 tf - 160 320 QT - 40 60 Q1 - 11 - Q2 - 20 - Q3 - 16 - - - 1.03 0.94 2.5 - trr - 91.1 - ta - 63.8 - tb - 27.3 - QRR - 0.299 - - - 3.5 4.5 - - - 7.5 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = .25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 5 Vdc, ID = 21 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 5 Vdc, ID = 42 Adc) (VGS = 5 Vdc, ID = 21 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 6 Vdc, ID = 20 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 30 Vdc, ID = 42 Adc, VGS = 5 Vdc, Vdc RG = 9.1 ) Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 42 Adc, VGS = 5 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 42 Adc, VGS = 0 Vdc) (IS = 42 Adc, VGS = 0 Vdc, TJ = 150 C) Reverse Recovery Time Adc VGS = 0 Vdc, Vdc (IS = 42 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1256 nH nH MTP50N06VL TYPICAL ELECTRICAL CHARACTERISTICS , " #$C 8 7 $ " 8 : : 9 6 9 $ 6 4 4 # $ $ # #$ : #$C $ 6 4 # 4 #$C # F$$C 7 8 49 6$ $6 94 #: :# 8 7 6 9 $ , " #$C 4$ 4 " $ #$ # $ $ Figure 3. On-Resistance versus Drain Current and Temperature 9 6 Figure 2. Transfer Characteristics , " C 8 4 Figure 1. On-Region Characteristics 6 # # " $ $ # 6 $ 4 9 : 8 7 Figure 4. On-Resistance versus Drain Current and Gate Voltage " $ " # 6 < 100C 9 4 9 , " $$C 8 7 # 8 9 " , " #$C C 6 # F$ F#$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature 4 # 6 $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1257 9 MTP50N06VL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 9 $ *. " %!! 6 , " #$C (!! 4 %!! # !! " $ (!! $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1258 4 @ #$ 8 9 $ @# @ 6 , " #$ " 6# # # @4 $ # 4 $ 6 ' ! # MTP50N06VL , " #$ " 6# " 4 " $ '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS #$ # , " #$ " $ $ $ $$ 9 9$ : :$ 8 8$ 7 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1259 MTP50N06VL SAFE OPERATING AREA " # " #$ 4 - , ! ! ! ! " 6# #$ # $ $ Figure 11. Maximum Rated Forward Biased Safe Operating Area $ $ :$ #$ , , #$ :$ Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # $ ' '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1260 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 ##!. Preferred Device #$%& '( ! * %+% P-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 50 AMPERES 30 VOLTS RDS(on) = 25 m P-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 30 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 30 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 15 20 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 50 31 150 Adc Total Power Dissipation Derate above 25C PD 125 1.0 Watts W/C TJ, Tstg -55 to 150 C 1250 mJ Rating Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 50 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient, when mounted with the minimum recommended pad size Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds EAS MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 TO-220AB CASE 221A STYLE 5 Apk 1 2 MTP50N03HDL LLYWW 1 Gate 3 3 Source 2 Drain C/W RJC RJA 1.0 62.5 TL 260 MTP50N03HDL LL Y WW = Device Code = Location Code = Year = Work Week C ORDERING INFORMATION Device Package Shipping MTP50N03HDL TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 1261 Publication Order Number: MTP50P03HDL/D MTP50P03HDL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 30 - - 26 - - - - - - 1.0 10 - - 100 1.0 - 1.5 4.0 2.0 - - 0.020 0.025 - - 0.83 - 1.5 1.3 15 20 - Ciss - 3500 4900 Coss - 1550 2170 Crss - 550 770 td(on) - 22 30 Unit OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 3.0) (Note 3.) Static Drain-to-Source On-Resistance (VGS = 5.0 Vdc, ID = 25 Adc) (Cpk 3.0) (Note 3.) Drain-to-Source On-Voltage (VGS = 10 Vdc) (ID = 50 Adc) (ID = 25 Adc, TJ = 125C) VGS(th) Vdc RDS(on) Ohm VDS(on) Forward Transconductance (VDS = 5.0 Vdc, ID = 25 Adc) mV/C Vdc gFS mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 50 Adc, VGS = 5 5.0 Vdc, 0 Vdc RG = 2.3 ) Fall Time Gate Charge g (S Figure (See Fi 8) (VDS = 24 Vdc, ID = 50 Adc, VGS = 5.0 Vdc) tr - 340 466 td(off) - 90 117 tf - 218 300 QT - 74 100 Q1 - 13.6 - Q2 - 44.8 - Q3 - 35 - - - 2.39 1.84 3.0 - trr - 106 - ta - 58 - tb - 48 - QRR - 0.246 - - - 3.5 4.5 - - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage Reverse Recovery y Time (S Figure (See Fi 15) (IS =50 Adc, VGS = 0 Vdc) (IS = 50 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 50 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1262 nH nH MTP50P03HDL TYPICAL ELECTRICAL CHARACTERISTICS " 8 , " #$ 8 $ 6$ 9 6 9 4$ 6 4 # #$ # 6 9 8 # 6 9 8 9 6 # 7 #4 #: 4 4$ 47 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics #$ , " #4 #$ # 7 F$$ : # 6 9 8 ## , " #$ # 64 " $ # 7 8 : 9 $ # 6 9 8 Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 4$ #$ " $ " #$ $ #$ " $ #: , " F$$ 8 $ # #7 < $ $ " , " #$ 7$ 8$ F$ F#$ #$ $ :$ #$ $ $ $ # #$ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1263 4 MTP50P03HDL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6 " " , " #$ *. # %!! 8 9 (!! %!! 6 # (!! $ $ !! $ # Figure 7. Capacitance Variation http://onsemi.com 1264 #$ 4 @ $ @ #$ @# 6 # 4 $ # " $ , " #$ @4 $ # 4 6 $ 9 ' ! 9 MTP50P03HDL " $ , " #$ '( 'C 'CC ' 8 : " 4 " @ 2 ! Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by $ 6 " , " #$ 4 # 6 9 8 # 6 9 8 # ## #6 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 1265 MTP50P03HDL %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. - , The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For " # " #$ ! ! ! 6 8 9 6 # " $ # #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 1266 ('.. < MTP50P03HDL " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' ! Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 1267 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 # Preferred Device #$%& '( N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 52 AMPERES 60 VOLTS RDS(on) = 22 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 25 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 52 41 182 Adc Total Power Dissipation Derate above 25C PD 188 1.25 Watts W/C TJ, Tstg -55 to 175 C EAS 406 mJ Rating Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 52 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds G S MARKING DIAGRAM & PIN ASSIGNMENT Apk TO-220AB CASE 221A STYLE 5 1 C/W RJC RJA 0.8 62.5 TL 260 4 Drain 4 2 3 MTP52N06V LLYWW 1 Gate 3 Source 2 Drain C MTP52N06V LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP52N06V Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 4 1268 Publication Order Number: MTP52N06V/D MTP52N06V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 66 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 2.7 6.4 4.0 - Vdc mV/C - 0.019 0.022 - - - - 1.4 1.2 gFS 17 24 - mhos Ciss - 1900 2660 pF Coss - 580 810 Crss - 150 300 td(on) - 12 20 tr - 298 600 td(off) - 70 140 tf - 110 220 QT - 125 175 Q1 - 10 - Q2 - 30 - Q3 - 40 - - - 1.0 0.98 1.5 - trr - 100 - ta - 80 - tb - 20 - QRR - 0.341 - - - 3.5 4.5 - - - 7.5 - OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) (Cpk 2.0) (Note 3.) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 26 Adc) (Cpk 2.0) (Note 3.) Drain-Source On-Voltage (VGS = 10 Vdc, ID = 52 Adc) (VGS = 10 Vdc, ID = 26 Adc, TJ = 150C) VGS(th) RDS(on) Ohm VDS(on) Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 30 Vdc, ID = 52 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 52 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 52 Adc, VGS = 0 Vdc) (IS = 52 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (S Figure Fi 14) (See (IS = 52 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1269 nH nH MTP52N06V TYPICAL ELECTRICAL CHARACTERISTICS 7 , " #$ : 7 8 : 9 9 $ 6 4 $ # 8 " 7 4$ 6 4 # 9 $ 8 : 7 : 9 $ 6 4 # , " $$ #$ # 4 6 4$ 6$ $ $$ 9 : 9$ Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics , " #$ #$ # $ $$ $ # 4 6 $ 9 : 8 7 #4 :$ 8 7$ $ , " #$ ## # " # 7 $ 8 : 9 $ $ #$ $ 4$ 6$ $$ 9$ :$ 8$ Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage # :$ " " " #9 $ < #$ " 4 8 #$ :$ , " #$ $ #$ $ #$ #$ $ :$ #$ $ :$ , , # 4 6 $ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1270 9 MTP52N06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) : *. 9 %!! " " , " #$ $ 6 (!! 4 %!! # !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1271 @ 4 #: 8 #6 # @# @ 9 8 $ 6 # 7 " $# , " #$ # @4 # 6 9 8 @ # 9 4 6 ' ! 49 44 # MTP52N06V " 4 " $# " , " #$ 'C 'CC ' '( Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS $$ " , " #$ $ 6$ 6 4$ 4 #$ # $ $ # 4 6 $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1272 MTP52N06V SAFE OPERATING AREA 6$ " # " #$ - , F! F! F ! F ! " $# 6 4$ 4 #$ # $ $ #$ Figure 11. Maximum Rated Forward Biased Safe Operating Area $ :$ #$ $ , , :$ Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # $ *0 # ' $ '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1273 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 # Preferred Device #$%& '( * %+% N-Channel TO-220 http://onsemi.com This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature 52 AMPERES 60 VOLTS RDS(on) = 25 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 15 25 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 52 41 182 Adc Total Power Dissipation Derate above 25C PD 188 1.25 Watts W/C TJ, Tstg -55 to 175 C EAS 406 mJ Rating Drain-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5 Vdc, Peak IL = 52 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds G S MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 Apk TO-220AB CASE 221A STYLE 5 1 RJC RJA 0.8 62.5 C/W TL 260 C 2 3 MTP52N06VL LLYWW 1 Gate 3 Source 2 Drain MTP52N06VL LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTP52N06VL TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 4 1274 Publication Order Number: MTP52N06VL/D MTP52N06VL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 65 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 1.0 - 1.5 4.5 2.0 - Vdc mV/C - 0.022 0.025 - - - - 1.6 1.4 gFS 17 30 - Mhos Ciss - 1900 2660 pF Coss - 550 770 Crss - 170 340 td(on) - 15 30 tr - 500 1000 td(off) - 100 200 tf - 200 400 QT - 62 90 Q1 - 4.0 - Q2 - 31 - Q3 - 16 - - - 1.03 0.9 1.5 - trr - 104 - ta - 63 - tb - 41 - QRR - 0.28 - - - 3.5 4.5 - - - 7.5 - OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = .25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 2.0) (Note 3.) Static Drain-to-Source On-Resistance (VGS = 5 Vdc, ID = 26 Adc) (Cpk 2.0) (Note 3.) Drain-to-Source On-Voltage (VGS = 5 Vdc, ID = 52 Adc) (VGS = 5 Vdc, ID = 26 Adc, TJ = 150C) VGS(th) RDS(on) Ohm VDS(on) Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 30 Vdc, ID = 52 Adc, VGS = 5 Vdc, Vdc RG = 9.1 ) Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 52 Adc, VGS = 5 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 52 Adc, VGS = 0 Vdc) (IS = 52 Adc, VGS = 0 Vdc, TJ = 150 C) Reverse Recovery Time (IS = 52 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1275 nH nH MTP52N06VL TYPICAL ELECTRICAL CHARACTERISTICS " 8 7 : 8 9 $ 7 9 6 $ 6 4 # 4 : # 6 4 9 $ 8 : 7 #$ $ 6 4 # $ #$ # 4 4$ 6 6$ $ Figure 2. Transfer Characteristics , " 4 #$ # $$ # 4 6 $ 9 : 8 7 6 $$ 4 " $ #$ # $ $ # 4 6 9 $ : 8 7 Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 9 9 , " #$ 4$ " $ " #9 " , " #$ 6 < : 9 Figure 1. On-Region Characteristics 6 8 $ , " $$ " $ 9 $ : , " #$ # 8 9 6 # $ #$ #$ $ :$ #$ $ :$ , , # 4 6 $ Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1276 9 MTP52N06VL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 8 *. : " " , " #$ %!! 9 $ (!! 6 4 %!! # !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1277 4 @ 7 #: 8 #6 : # 9 8 @# @ $ $ 6 # 4 7 " $# , " #$ # @4 # 4 6 $ @ 9 4 : 9 ' ! MTP52N06VL " 4 " $# " $ , " #$ '( 'C 'CC ' Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS $$ $ 6$ " , " #$ 6 4$ 4 #$ # $ $ $ $$ 9 9$ : :$ 8 8$ 7 7$ $ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1278 MTP52N06VL SAFE OPERATING AREA 6$ " $ " #$ - , F! F! F ! F ! " $# 6 4$ 4 #$ # $ $ #$ Figure 11. Maximum Rated Forward Biased Safe Operating Area $ :$ #$ $ , , :$ Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # $ *0 # ' $ '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1279 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 ## Preferred Device #$%& '( P-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 5 AMPERES 60 VOLTS RDS(on) = 450 m P-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit 60 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDSS VDGR 60 Vdc Gate-to-Source Voltage - Continuous - Non-repetitive (tp 10 ms) VGS VGSM 15 25 Vdc Vpk Drain Current - Continuous @ 25C Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 5 4 18 Adc Total Power Dissipation @ TC = 25C Derate above 25C PD 40 0.27 Watts W/C TJ, Tstg -55 to 175 C EAS 125 mJ Rating Drain-to-Source Voltage Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 5 Apk, L = 10 mH, RG = 25 ) Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds MARKING DIAGRAM & PIN ASSIGNMENT Apk RJC RJA 3.75 62.5 C/W TL 260 C 4 Drain 4 TO-220AB CASE 221A STYLE 5 1 2 MTP5P06V LLYWW 1 Gate 3 3 Source 2 Drain MTP5P06V LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP5P06V Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 1280 Publication Order Number: MTP5P06V/D MTP5P06V ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - - 61.2 - - - - - - 10 100 - - 100 2.0 - 2.8 4.7 4.0 - mV/C - 0.34 0.45 Ohm - - - - 2.7 2.6 1.5 3.6 - Ciss - 367 510 Coss - 140 200 Crss - 29 60 td(on) - 11 20 tr - 26 50 td(off) - 17 30 OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 2.5 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc, ID = 5 Adc) (VGS = 10 Vdc, ID = 2.5 Adc, TJ = 150C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc) Vdc Vdc gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 30 Vdc, ID = 5 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 5 Adc, VGS = 10 Vdc) tf - 19 40 QT - 12 20 Q1 - 3.0 - Q2 - 5.0 - Q3 - 5.0 - - - 1.72 1.34 3.5 - trr - 97 - ta - 73 - tb - 24 - QRR - 0.42 - - 3.5 4.5 - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 5 Adc, VGS = 0 Vdc) (IS = 5 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 5 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1281 nH nH MTP5P06V TYPICAL ELECTRICAL CHARACTERISTICS " 8 8 7 : , " #$C 9 9 6 $ # 9 # 4 6 $ 9 : 8 $ 6 4 # # 6 $ 9 : Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics , " C 6 6 #$C 4$ 4 8 , " #$C " 4$ 6$ $ 4 #$ $$C #$ # 4 6 $ 9 : 8 7 # Figure 3. On-Resistance versus Drain Current and Temperature 8 9 # 4 6 $ : 9 8 7 Figure 4. On-Resistance versus Drain Current and Gate Voltage " " #$ 6 < 4 $ # 9 " $$ 100C : 7 #$C 8 6 , " $$C 7 # 8 9 " , " #$ 6 # $ #$ #$ $ :$ #$ , , $ :$ Figure 5. On-Resistance Variation with Temperature $ # 4 6 Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1282 9 MTP5P06V POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) " %!! 7 , " #$C *. 8 : 9 (!! $ %!! 6 4 !! # (!! " $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1283 7 9 $6 @ 68 8 : @# @ 6# 9 49 $ 4 6 #6 4 8 # @4 # , " #$ " $ 6 9 8 # # 9 6 ' ! MTP5P06V , " #$ " $ " 4 " 'CC 'C '( ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS $ , " #$ " 6$ 6 4$ 4 #$ # $ $ # 6 9 8 # 6 9 8 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1284 MTP5P06V SAFE OPERATING AREA 6 " # " #$ - , ! ! ! ! " $ # 8 9 6 # #$ $ :$ #$ $ :$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' $ '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1285 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 #. Preferred Device #$%& '( N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 60 AMPERES 60 VOLTS RDS(on) = 14 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 30 Vdc Vpk Drain Current - Continuous - Continuous @ 100C - Single Pulse (tp 10 s) ID ID IDM 60 42.3 180 Adc Total Power Dissipation Derate above 25C PD 150 1.0 Watts W/C TJ, Tstg -55 to 175 C 540 mJ Rating Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds EAS S MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 TO-220AB CASE 221A STYLE 5 Apk 1 2 MTP60N06HD LLYWW 1 Gate 3 3 Source 2 Drain C/W RJC RJA 1.0 62.5 TL 260 C MTP60N06HD LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTP60N06HD TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 1286 Publication Order Number: MTP60N06HD/D MTP60N06HD ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 60 - - 71 - - - - - - 10 100 - - 100 2.0 - 3.0 7.0 4.0 - - 0.011 0.014 - - - - 1.0 0.9 15 20 - Ciss - 1950 2800 Coss - 660 924 Crss - 147 300 td(on) - 14 26 tr - 197 394 td(off) - 50 102 Unit OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) Vdc IGSS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Cpk 3.0) (Note 3.) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 30 Adc) (Cpk 3.0) (Note 3.) Drain-to-Source On-Voltage (VGS = 10 Vdc) (ID = 60 Adc) (ID = 30 Adc, TJ = 125C) nAdc VGS(th) Vdc RDS(on) Vdc gFS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance mV/C Ohm VDS(on) Forward Transconductance (VDS = 5.0 Vdc, ID = 30 Adc) DYNAMIC CHARACTERISTICS mV/C Adc IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Output Capacitance V(BR)DSS mhos pF SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 30 Vdc, ID = 60 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge g (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 60 Adc, VGS = 10 Vdc) tf - 124 246 QT - 51 71 Q1 - 12 - Q2 - 24 - Q3 - 21 - - - 0.99 0.89 1.2 - trr - 60 - ta - 36 - tb - 24 - QRR - 0.143 - - - 3.5 4.5 - - - 7.5 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage Reverse Recovery y Time (S Figure (See Fi 15) (IS = 60 Adc, VGS = 0 Vdc) (IS = 60 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 60 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1287 nH nH MTP60N06HD TYPICAL ELECTRICAL CHARACTERISTICS , " #$ 9 9 6 $ # $ $ # #$ 4 4$ 6 6$ #$ , " F$$ #8 49 66 $# 9 98 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 6 #$ # F$$ 8 # $ , " 6 E'! 9 9 9 E'! " 8 8 # # # 4 6 $ 9 : 8 7 # 4# #6 # " 9 # 8 $ 6 # 4 6 $ 9 : 8 7 # *! *! Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 8 9 :9 , " #$ #8 " " " 4 , " #$ < 7 8 # : 8 " # 6 # #$ 8 9 F$ F#$ #$ $ :$ #$ $ # 4 6 $ , , E'! Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1288 9 MTP60N06HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) $ *. 6 %!! " " , " #$ 4 (!! %!! # !! (!! $ $ $ # #$ E'! Figure 7. Capacitance Variation http://onsemi.com 1289 9 @ $ 8 @ 6 @# 9 4 6 # # " 9 , " #$ @4 8 9 #6 4# 6 68 $9 ' ! # MTP60N06HD " 4 " 9 " , " #$ '( 'C 'CC ' @ 2 ! Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 9 $ " , " #$ 6 4 # $ 9 : 8 7 E'! Figure 10. Diode Forward Voltage versus Current http://onsemi.com 1290 MTP60N06HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. - , The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For " # " #$ ! ! ! ! 9 6 4 # " 9 $ #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 1291 ('.. < MTP60N06HD " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' ! 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 1292 ,' " (' , - . / / ' ,*0 " *0 ,' 5 ## Preferred Device #$%& '( P-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 6 AMPERES 200 VOLTS RDS(on) = 1 P-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 200 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 200 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 40 Vdc Vpk Drain Current - Continuous - Continuous @ 100C - Single Pulse (tp 10 s) ID ID IDM 6.0 3.9 21 Adc Total Power Dissipation Derate above 25C PD 75 0.6 Watts W/C TJ, Tstg -55 to 150 C 180 mJ Rating Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 10 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds EAS MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 Apk TO-220AB CASE 221A STYLE 5 1 2 MTP6P20E LLYWW 1 Gate 3 3 Source 2 Drain C/W RJC RJA 1.67 62.5 TL 260 MTP6P20E LL Y WW = Device Code = Location Code = Year = Work Week C ORDERING INFORMATION Device MTP6P20E Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 1293 Publication Order Number: MTP6P20E/D MTP6P20E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 200 - - 211 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 3.1 4.0 4.0 - Vdc mV/C - 0.81 1.0 Ohm - - 6.0 - 7.2 6.3 gFS 1.5 3.8 - mhos Ciss - 540 750 pF Coss - 128 180 Crss - 40 90 td(on) - 12 25 tr - 32 65 td(off) - 24 50 tf - 16 30 QT - 22 30 Q1 - 4.0 - Q2 - 11 - Q3 - 9.0 - - - 2.8 2.6 4.0 - trr - 188 - ta - 152 - tb - 36 - QRR - 1.595 - - - 3.5 4.5 - - - 7.5 - OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 3.0 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 6.0 Adc) (ID = 3.0 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 8.0 Vdc, ID = 3.0 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 100 Vdc, ID = 6.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 160 Vdc, ID = 6.0 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 6.0 Adc, VGS = 0 Vdc) (IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 14) 6 0 Adc, Adc VGS = 0 Vdc, Vdc (IS = 6.0 dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1294 nH nH MTP6P20E TYPICAL ELECTRICAL CHARACTERISTICS , " #$ # " # 8 7 8 : 6 9 # # 6 9 8 # 6 9 6 4 $ : 7 Figure 2. Transfer Characteristics # #$ 8 $$ 6 # 6 9 8 # 6 " $ 8 # $ $ #$ $ :$ 9 8 # Figure 4. On-Resistance versus Drain Current and Gate Voltage 6 " " 4 ?#$ , " #$ # Figure 3. On-Resistance versus Drain Current and Temperature < Figure 1. On-Region Characteristics , " ?$ " # , " ?$$ 9 #$ 8 9 # $ #$ $ " #$ # 9 # 8 6 , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1295 MTP6P20E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) # *. 9 # %!! " " , " #$ (!! 8 %!! 6 !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1296 # 9 @ 8 8 9 6 " 9 , " #$ # @4 $ 6 $ @D " " 9 " , " #$ # @# @ # #$ ' ! MTP6P20E '( 'CC 'C Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge ' Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 9 " , " #$ $ 6 4 # $ $ # #$ 4 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1297 MTP6P20E SAFE OPERATING AREA 8 " # " #$ - , ! ! ! " 9 66 8 :# 49 #$ $ :$ #$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # $ *0 # ' '# - - " '&'# $ 6 # 4 ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1298 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 #"!. Preferred Device #$%& '( " * %+% N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low-voltage, high-speed switching applications in power supplies, converters and PWM motor controls, and inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients. * SPICE Parameters Available * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Avalanche Energy Specified http://onsemi.com 75 AMPERES 25 VOLTS RDS(on) = 9 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Symbol Value Unit Drain-Source Voltage VDSS 25 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 25 Vdc Gate-Source Voltage - Continuous - Single Pulse (tp 10 ms) VGS 15 20 Vdc Vpk Drain Current - Continuous - Continuous @ 100C - Single Pulse (tp 10 s) ID ID IDM 75 59 225 Adc Total Power Dissipation Derate above 25C PD 150 1.0 Watts W/C TJ, Tstg -55 to 175 C EAS 280 mJ Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 75 Apk, L = 0.1 mH, RG = 25 ) Thermal Resistance -Junction to Case -Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds S MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 Apk TO-220AB CASE 221A STYLE 5 1 2 MTP75N03HDL LLYWW 1 Gate 3 2 Drain C/W RJC RJA 1.0 62.5 TL 260 C 3 Source MTP75N03HDL LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTP75N03HDL TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 1299 Publication Order Number: MTP75N03HDL/D MTP75N03HDL ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max 25 - - Unit OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mA) Temperature Coefficient (Positive) V(BR)DSS Vdc mV/C Zero Gate Voltage Drain Current (VDS = 25 Vdc, VGS = 0 Vdc) (VDS = 25 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 V) IGSS Adc - - - - 100 500 - - 100 1.0 1.5 2.0 nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mA) Temperature Coefficient (Negative) (Cpk 3.0) (Note 3.) Static Drain-Source On-Resistance (VGS = 5.0 Vdc, ID = 37.5 Adc) (Cpk 2.0) (Note 3.) VGS(th) Vdc mV/C RDS(on) m - Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 75 Adc) (ID = 37.5 Adc, TJ = 125C) 6.0 9.0 - - - 0.68 0.6 gFS 15 55 - mhos Ciss - 4025 5635 pF Coss - 1353 1894 Crss - 307 430 td(on) - 24 48 tr - 493 986 td(off) - 60 120 tf - 149 300 QT - 61 122 Q1 - 14 28 Q2 - 33 66 Q3 - 27 54 - - 0.97 0.87 1.1 - trr - 58 - ta - 27 - tb - 30 - QRR - 0.088 - VDS(on) Forward Transconductance (VDS = 3.0 Vdc, ID = 20 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS = 15 Vdc, ID = 75 Adc, VGS = 5 5.0 0 Vdc Vdc, Rg = 4.7 ) Fall Time Gate Charge (VDS = 24 Vdc, ID = 75 Adc, VGS = 5.0 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 75 Adc, VGS = 0 Vdc) (IS = 75 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 75 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1300 VSD Vdc ns C MTP75N03HDL TYPICAL ELECTRICAL CHARACTERISTICS " $ 8 # $ 6$ , " #$C 6 9 $ 7 4$ 9 4 4 # # 7 9 4 6 9 8 # 6 9 8 $ # #$C $$C 6 # 4 9 7 # $ , " C 9 6$ 7 , " #$C 8 : " $ 9 $ 6 :$ $ Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage # #$ " " 4:$ 9 # 8 6 # #$ 4 4$ 6 Figure 2. Transfer Characteristics " $ 8 < Figure 1. On-Region Characteristics #$ , " $$C #$ #$ $ , " #$ #$ $ #$ #$ $ :$ , , #$ $ " Figure 5. On-Resistance Variation with Temperature $ $ # #$ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1301 4 MTP75N03HDL POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) $ *. # " " , " #$C %!! 7 9 (!! %!! !! 4 (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1302 #8 9 #6 @ $ @# @ 6 # 9 # 4 , " #$ " :$ # 6 @4 8 $ # 4 6 @ 9 : ' ! : MTP75N03HDL '( 'C 'CC ' , " #$ " :$ " $ " $ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by :$ , " #$ " 9 6$ 4 $ $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 1303 MTP75N03HDL SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For #8 " # " #$ - , ! ! ! " :$ #6 # 9 # 8 6 #$ $ :$ #$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 1304 MTP75N03HDL TYPICAL ELECTRICAL CHARACTERISTICS (' <.. " $ # *0 $ # ' $ 6 '# - - " '&'# 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1305 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 #". Preferred Device #$%& '( " N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy-efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low-voltage, high-speed switching applications in power supplies, converters and PWM motor controls, and other inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients. * SPICE Parameters Available * Diode is Characterized for Use in Bridge Circuits * Diode Exhibits High Speed, Yet Soft Recovery * IDSS and VDS(on) Specified at Elevated Temperature * Avalanche Energy Specified http://onsemi.com 75 AMPERES 50 VOLTS RDS(on) = 9.5 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Symbol Value Unit Drain-Source Voltage VDSS 50 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 50 Vdc Gate-Source Voltage - Continuous VGS 20 Vdc Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 75 65 225 Adc Total Power Dissipation Derate above 25C PD 150 1 Watts W/C TJ, Tstg -55 to 175 C EAS 500 mJ Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vpk, IL = 75 Apk, L = 0.177 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds S MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 Apk TO-220AB CASE 221A STYLE 5 1 2 MTP75N05HD LLYWW 1 Gate 3 2 Drain C/W RJC RJA 1.00 62.5 TL 260 C 3 Source MTP75N05HD LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTP75N05HD TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 4 1306 Publication Order Number: MTP75N05HD/D MTP75N05HD ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 50 - - 54.9 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - - 6.3 4.0 - Vdc mV/C - 7.0 9.5 - - - - 0.86 0.64 gFS 15 - - mhos Ciss - 2600 3900 pF Coss - 1000 1300 Crss - 230 300 td(on) - 15 30 tr - 170 340 td(off) - 70 140 tf - 100 200 QT - 71 100 Q1 - 13 - Q2 - 33 - Q3 - 26 - - - 0.97 0.88 1.1 - trr - 57 - ta - 40 - tb - 17 - QRR - 0.17 - - - 3.5 4.5 - - - 7.5 - OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-Source Breakdown Voltage (VGS = 0 V, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 50 Vdc, VGS = 0) (VDS = 50 Vdc, VGS = 0, TJ = 150C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) (Cpk 1.5) (Note 3.) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 37.5 Adc) (Cpk 3.0) (Note 3.) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 75 Adc) (ID = 37.5 Adc, TJ = 150C) VGS(th) RDS(on) mW VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 20 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) (Cpk 2.0) 2 0)(2) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 25 Vdc, ID = 75 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (VDS = 40 Vdc, ID = 75 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 75 Adc, VGS = 0) (IS = 75 Adc, VGS = 0, TJ = 150C) (Cpk 10)(2) Reverse Recovery Time (IS = 37.5 Adc, VGS = 0, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1307 nH nH MTP75N05HD TYPICAL ELECTRICAL CHARACTERISTICS (Note 4.) 6 9 , " #$ # 8 9 9 6 $ # $ $ # , " ?F$$ 6 #$ 4 6 4$ $ 6$ #$ # 4 $ 6 9 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics # , " #$ 8 9 F?$$ 6 # 6 9 8 # 6 7 : 8 6 9 , " #$ 8 " : $ 9 $ # 6 9 8 # Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage # " " 4:$ $ $ " , " #$ < 9 " 8 # 6 # 6 # : " 9 #$ F$ F#$ #$ $ :$ #$ $ $ $ # #$ 4 4$ 6 , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage 4. Pulse Tests: Pulse Width 250 s, Duty Cycle 2%. http://onsemi.com 1308 6$ $ MTP75N05HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board-mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 8 " *. : 9 " , " #$ %!! $ 6 (!! %!! 4 # !! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 1309 #$ MTP75N05HD 9 8 9 4 6 , " #$ " :$ @4 ' :$ #$ $ @ '( 'C 'CC # # 6 @# @ , " #$ " :$ " 4$ " $ ' ! @ # Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 6 8 9 , " #$ " : $ 6 4 # 4 %&' " 4 &! '(( '(( '+ ') # F F# F4 # 4 6 $ 9 : 8 7 F6 F# F F8 Figure 10. Diode Forward Voltage versus Current F9 F6 F# ' ! # 6 9 Figure 11. Reverse Recovery Time (trr) http://onsemi.com 1310 8 MTP75N05HD SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr,tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For $ " # " #$ ! ! ! ! - , " :$ 6 4 # #$ Figure 12. Maximum Rated Forward Biased Safe Operating Area $ :$ #$ $ , , :$ Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 1311 MTP75N05HD (' < " $ # $ *0 # ' $ '# - - " '&'# 6 4 # ' ! Figure 14. Thermal Response http://onsemi.com 1312 ,' " (' , , " &/ > - . / / ' ,*0 " *0 ,' 5 5 #". Preferred Device #$%& '( " N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low-voltage, high-speed switching applications in power supplies, converters and PWM motor controls, and inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients. * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Avalanche Energy Specified http://onsemi.com 75 AMPERES 60 VOLTS RDS(on) = 10 m N-Channel D MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Symbol Value Unit Drain-Source Voltage VDSS 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Gate-Source Voltage - Continuous Gate-Source Voltage - Single Pulse VGS 20 30 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 75 50 225 Adc Total Power Dissipation Derate above 25C PD 150 1.0 Watts W/C TJ, Tstg -55 to 175 C EAS 500 mJ Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 75 Apk, L = 0.177 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds G S MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 Apk TO-220AB CASE 221A STYLE 5 1 2 MTP75N06HD LLYWW 1 Gate 3 3 Source C/W RJC RJA 1.0 62.5 TL 260 2 Drain C MTP75N06HD LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device Package Shipping MTP75N06HD TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 1313 Publication Order Number: MTP75N06HD/D MTP75N06HD ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 - 68 60.4 - - - - - - 10 100 - 5.0 100 2.0 - 3.0 8.38 4.0 - - 8.3 10 - - 0.7 0.53 0.9 0.8 gFS 15 32 - mhos Ciss - 2800 3920 pF Coss - 928 1300 Crss - 180 252 td(on) - 18 26 tr - 218 306 td(off) - 67 94 tf - 125 175 QT - 71 100 Q1 - 16.3 - Q2 - 31 - Q3 - 29.4 - - - 0.97 0.88 1.1 - trr - 56 - ta - 44 - tb - 12 - QRR - 0.103 - - 3.5 - - 7.5 - OFF CHARACTERISTICS (Cpk 2.0) (Note 3.) Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 V) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) (Cpk 5.0) (Note 3.) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 37.5 Adc) (Cpk 2.0) (Note 3.) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 75 Adc) (ID = 37.5 Adc, TJ = 125C) VGS(th) Vdc RDS(on) m VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 37.5 Adc) mV/C Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS = 30 Vdc, ID = 75 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Fall Time Gate Charge (VDS = 48 Vdc, ID = 75 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 75 Adc, VGS = 0 Vdc) (IS = 75 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 75 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1314 nH nH MTP75N06HD TYPICAL ELECTRICAL CHARACTERISTICS : :$ 9 $ #$ $ $ $ #$ # , " ?$$ # 4 6 $ 9 : Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics , " # #$ 8 ?$$ 9 #$ #$ , " #$ " 6 6 :$ $ 9 :$ $ #$ $ # 8 , " #$ " 7 $ 8 : 9 #$ $ :$ #$ $ Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage 7 " " " 4:$ , " #$ 9 < 7 #$ #$ $ 8 " , " #$ $ 4 #$ : F$ F#$ #$ $ :$ #$ $ # 4 6 $ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1315 9 MTP75N06HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) : *. 9 $ " " , " #$ %!! 6 4 %!! (!! # !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1316 9 @ $ 8 @ 6 @# 9 4 6 # @4 # " :$ , " #$ # 4 6 $ 9 : 8 ' ! # MTP75N06HD " 4 " :$ " , " #$ '( 'C 'CC ' @ 2 ! Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by :$ " , " #$ $ #$ $ $8 99 :6 8# 7 78 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 1317 MTP75N06HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. " # " #$ ! ! ! ! - , The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For $ " :$ 4:$ #$ #$ #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 1318 MTP75N06HD ('.. < TYPICAL ELECTRICAL CHARACTERISTICS " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' ! Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 1319 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 #" Preferred Device #$%& '( " N-Channel TO-220 This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 7 AMPERES 200 VOLTS RDS(on) = 700 m N-Channel D G MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 200 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 200 Vdc Gate-to-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 40 Vdc Vpk ID ID IDM 7.0 3.8 21 Adc PD 50 0.4 Watts W/C TJ, Tstg -55 to 150 C Rating Drain Current - Continuous - Continuous @ 100C - Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 7.0 Adc, L = 10 mH, RG = 25 ) Thermal Resistance - Junction to Case - Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds EAS S MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain 4 TO-220AB CASE 221A STYLE 5 Apk 1 2 1 Gate 3 C/W 2.5 62.5 TL 260 C 3 Source 2 Drain mJ 74 RJC RJA MTP7N20E LLYWW MTP7N20E LL Y WW = Device Code = Location Code = Year = Work Week ORDERING INFORMATION Device MTP7N20E Package Shipping TO-220AB 50 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 1 1320 Publication Order Number: MTP7N20E/D MTP7N20E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 200 - - 689 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - 3.1 7.1 4.0 - Vdc mV/C - 0.46 0.7 Ohm - - 3.4 - 5.9 5.1 gFS 1.5 - - mhos Ciss - 342 480 pF Coss - 92 130 Crss - 27 55 td(on) tr - 8.8 17.6 - 29 58 td(off) tf - 22 44 - 20 40.8 QT - 13.7 21 Q1 - 3.3 Q2 - 6.6 - Q3 - 5.9 - - - 1.02 0.9 1.2 - trr ta - 138 - - 93 - tb QRR - 45 - - 0.74 - - - 3.5 4.5 - - - 7.5 - OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 3.5 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 7.0 Adc) (VGS = 10 Vdc, ID = 3.5 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 14 Vdc, ID = 3.5 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 1 0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 100 Vdc, ID = 7.0 Adc, VGS = 10 Vdc, Rg = 9.1 ) Fall Time Gate Charge (See Figure 8) (VDS = 160 Vdc, ID = 7.0 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 7.0 Adc, VGS = 0 Vdc) (IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery y Time (See Figure 14) Reverse Recovery Stored Charge 7 0 Adc, Adc VGS = 0 Vdc, Vdc (IS = 7.0 dIS/dt = 100 A/s) VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Ld Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad.) Ls 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1321 nH MTP7N20E TYPICAL ELECTRICAL CHARACTERISTICS , " #$ " # 6 7 8 6 8 : 9 6 9 # $ # 6 9 8 , " #$ 8 9 6 # # # 4 6 9 8 $ : 7 # " 9 , " #$ 6 $$ # # 6 9 8 # 6 : , " #$ 9$ 9 " $$ $ $ 6$ 6 " " 4$ $ " #$ #$ $ :$ , , 9 8 # 6 #$ $ , " #$ #$ $ $ 6 Figure 4. On-Resistance versus Drain Current and Gate Voltage < # # Figure 3. On-Resistance versus Drain Current and Temperature #$ Figure 2. Transfer Characteristics Figure 1. On-Region Characteristics 8 $$ # Figure 5. On-Resistance Variation with Temperature $ $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1322 # MTP7N20E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 7 *. :$ " %!! , " #$C 9 6$ (!! %!! 4 !! $ " (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1323 MTP7N20E @ $ 8 # @# @ 9 7 6 9 # , " #$ " : @4 # 4 6 9 8 6 # ' ! 8 # , " #$ " : " " '( 'CC 'C ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS : " , " #$ 9 $ 6 4 # $ 9 : 8 7 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1324 MTP7N20E - , SAFE OPERATING AREA " # " #$ ! ! ! ! 8 " :F : 9 $ 6 4 # #$ $ :$ #$ , , ( '.. < Figure 11. Maximum Rated Forward Biased Safe Operating Area $ Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature " $ # $ *0 # ' '# - - " '&'# ' Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1325 ,' " (' , - . / / ' ,*0 " *0 ,' (# . Preferred Device #$%& '( P-Channel Micro8t These Power MOSFET devices are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. Micro8 devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Miniature Micro8 Surface Mount Package - Saves Board Space * Extremely Low Profile (<1.1mm) for thin applications such as PCMCIA cards * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Mounting Information for Micro8 Package Provided http://onsemi.com 1 AMPERE 20 VOLTS RDS(on) = 160 m P-Channel MARKING DIAGRAM Micro8 CASE 846A STYLE 1 8 WW AB 1 WW = Date Code PIN ASSIGNMENT Source Source Source Gate 1 8 7 6 5 2 3 4 Drain Drain Drain Drain Top View ORDERING INFORMATION Device Package MTSF1P02HDR2 Micro8 Shipping 4000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. This document contains information on a new product. Specifications and information herein are subject to change without notice. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 1326 Publication Order Number: MTSF1P02HD/D MTSF1P02HD MAXIMUM RATINGS (TJ = 25C unless otherwise noted) * Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C (Note 2.) Drain Current - Continuous @ TA = 70C (Note 2.) Drain Current - Pulsed Drain Current (Note 3.) Total Power Dissipation @ TA = 25C (Note 1.) Linear Derating Factor (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Linear Derating Factor (Note 2.) Operating and Storage Temperature Range Symbol Value Unit VDSS VDGR 20 Vdc 20 Vdc VGS ID ID IDM PD 8.0 Vdc 1.8 1.6 14.4 Adc 1.8 14.3 Watts mW/C PD 0.78 6.25 Watts mW/C TJ, Tstg - 55 to 150 C Apk THERMAL RESISTANCE Rating Thermal Resistance - Junction to Ambient, PCB Mount (Note 1.) Thermal Resistance - Junction to Ambient, PCB Mount (Note 2.) Symbol Typ. Max. Unit RJA RJA 55 125 70 160 C/W *Negative signs for P-Channel device omitted for clarity. 1. When mounted on 1 square FR-4 or G-10 board (VGS = 4.5 V, @ Steady State) 2. When mounted on minimum recommended FR-4 or G-10 board (VGS = 4.5 V, @ Steady State) 3. Repetitive rating; pulse width limited by maximum junction temperature. http://onsemi.com 1327 MTSF1P02HD ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 4.) Characteristic Symbol Min Typ Max Unit 20 - - 12.8 - - - - - - 1.0 10 - - 100 0.6 - 0.8 2.5 - - - - 120 160 160 190 gFS 2.0 4.0 - Mhos Ciss - 440 - pF Coss - 300 - Crss - 150 - td(on) - 15 - tr - 35 - td(off) - 55 - tf - 75 - td(on) - 20 - OFF CHARACTERISTICS (Cpk 2.0) Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) (Notes 4. & 6.) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 8.0 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 5.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Note 6.) Static Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 1.8 Adc) (VGS = 2.7 Vdc, ID = 0.9 Adc) (Note 6.) Forward Transconductance (VDS = 10 Vdc, ID = 0.9 Adc) (Note 4.) VGS(th) Vdc RDS(on) mV/C m DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 6.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS = 10 Vdc, ID = 1.8 Adc, VGS = 4.5 Vdc, RG = 6.0 ) (Note 4.) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 0.9 Adc, VGS = 2.7 Vdc, RG = 6.0 ) (Note 4.) Fall Time Gate Charge (VDS = 10 Vdc, ID = 1.8 Adc, VGS = 4.5 Vdc) tr - 93 - td(off) - 50 - tf - 75 - QT - 11 22 Q1 - 0.7 - Q2 - 5.5 - Q3 - 3.8 - - - 1.24 0.9 2.0 - trr - 120 - ta - 33 - tb - 87 - QRR - 0.223 - ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 1.8 Adc, VGS = 0 Vdc) (Note 4.) (IS = 1.8 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 1.8 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 4.) Reverse Recovery Stored Charge 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. 6. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1328 VSD Vdc ns C MTSF1P02HD TYPICAL ELECTRICAL CHARACTERISTICS " 6$ #: # 9 # 8 , " #$ 9 : 7 # # # 9 8 , " 8 $ 6 #$ 6 $$ 6 6 # 8 9 6 # 9 # Figure 2. Transfer Characteristics Figure 1. On-Region Characteristics " 8 , " #$ $ 6 4 # # # 9 8 # 9 6 8 8 , " #$ #: 9 6 6$ # $ $ # Figure 3. On-Resistance versus Gate-To-Source Voltage Figure 4. On-Resistance versus Drain Current and Gate Voltage " #: " 8 " , " #$ $ < $ ?$ ?#$ #$ $ :$ #$ $ #$ 6 8 # 9 , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1329 # MTSF1P02HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) # *. %!! " , " #$ " $ (!! %!! $ !! (!! $ $ $ E'! Figure 7. Capacitance Variation http://onsemi.com 1330 # 9 8 @ 6 # 4 7 # @# 9 @4 " 8 , " #$ 4 " " 8 " 6$ , " #$ $ @ 7 9 4 # ' ! $ MTSF1P02HD 'C 'CC '( ' @D Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by # 9 " , " #$ # 8 6 6 $ 9 : 8 7 # 4 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 1331 MTSF1P02HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curve (Figure 12) defines the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For 49 " 8 " #$ - , ! ! " 9 " $ " 9 " # 4# #8 #6 # 9 # 8 6 #$ $ :$ #$ $ , , Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 1332 MTSF1P02HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. " $ # $ *0 # $ ' '# - - " '&'# 6 4 # ' ! 5 5 Figure 14. Thermal Response %&' '(( ') '+ #$ '* Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 1333 ,' " (' , - . / / ' ,*0 " *0 ,' 5# 54 MTSF1P02HD INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 6 6 #8 $#8 #9 4# $ 48 #$9 9$ inches mm Micro8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 1.8 Watts. The power dissipation of the Micro8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the Micro8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 1.8 Watts 70C/W The 70C/W for the Micro8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.8 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 1334 MTSF1P02HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 1335 MTSF1P02HD TAPE & REEL INFORMATION Micro8 Dimensions are shown in millimeters (inches) 1.60 (.063) 1.50 (.059) 2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B 1.85 (.072) 1.65 (.065) A 0.35 (.013) 0.25 (.010) 5.55 (.218) 5.45 (.215) 12.30 11.70 (.484) (.461) 3.50 (.137) 3.30 (.130) 1.60 (.063) 1.50 (.059) TYP. A FEED DIRECTION 8.10 (.318) 7.90 (.312) 1.50 (.059) 1.30 (.052) SECTION A-A 5.40 (.212) 5.20 (.205) SECTION B-B NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 18.4 (.724) MAX. NOTE 3 13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN. 14.4 (.57) 12.4 (.49) NOTE 4 NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB. http://onsemi.com 1336 (! . Preferred Device #$%& '( ! N-Channel Micro8t These Power MOSFET devices are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. Micro8 devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Miniature Micro8 Surface Mount Package - Saves Board Space * Extremely Low Profile (<1.1mm) for thin applications such as PCMCIA cards * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Mounting Information for Micro8 Package Provided http://onsemi.com 3 AMPERES 20 VOLTS RDS(on) = 40 m N-Channel MARKING DIAGRAM Micro8 CASE 846A STYLE 1 8 WW AC 1 WW = Date Code PIN ASSIGNMENT Source Source Source Gate 1 8 7 6 5 2 3 4 Drain Drain Drain Drain Top View ORDERING INFORMATION Device Package MTSF3N02HDR2 Micro8 Shipping 4000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 5 1337 Publication Order Number: MTSF3N02HD/D MTSF3N02HD MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous 1 SQ. FR-4 or G-10 PCB Figure 1 below Steady State Minimum FR-4 or G-10 PCB Figure 2 below Steady State Thermal Resistance - Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current - Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Thermal Resistance - Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current - Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Operating and Storage Temperature Range 1. Repetitive rating; pulse width limited by maximum junction temperature. Figure 1. 1, Square FR-4 or G-10 PCB Symbol Max Unit VDSS VDGR 20 V 20 V VGS RTHJA PD 8.0 V 70 1.79 14.29 6.1 4.9 49 C/W Watts mW/C A A A 160 0.78 6.25 4.0 3.2 32 C/W Watts mW/C A A A - 55 to 150 C ID ID IDM RTHJA PD ID ID IDM TJ, Tstg Figure 2. Minimum FR-4 or G-10 PCB http://onsemi.com 1338 MTSF3N02HD ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 20 - - 16 - - - - - - 1.0 25 - - 100 0.7 - 0.98 2.65 1.1 - - - 30 40 40 50 gFS 4.0 7.5 - Mhos Ciss - 475 - pF Coss - 255 - Crss - 110 - td(on) - 9.5 - tr - 45 - td(off) - 50 - tf - 62 - td(on) - 19 - OFF CHARACTERISTICS (Cpk 2.0) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) (Notes 2. & 4.) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 8.0 Vdc, VDS = 0 Vdc) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Note 4.) (Cpk 2.0) (Note 4.) Static Drain-to-Source On-Resistance (VGS = 4.5 Vdc, ID = 3.8 Adc) (VGS = 2.7 Vdc, ID = 1.9 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 1.9 Adc) (Note 2.) VGS(th) Vdc RDS(on) mV/C m DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 15 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS = 10 Vdc, ID = 3.8 Adc, VGS = 4.5 Vdc, RG = 6 ) (Note 2.) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 10 Vdc, ID = 1.9 Adc, VGS = 2.7 Vdc, RG = 6 ) (Note 2.) Fall Time Gate Charge (VDS = 16 Vdc, ID = 3.8 Adc, VGS = 4.5 Vdc) tr - 130 - td(off) - 38 - tf - 47 - QT - 12 17 Q1 - 1.0 - Q2 - 5.0 - Q3 - 3.5 - - - 0.83 0.68 1.0 - trr - 46 - ta - 23 - tb - 23 - QRR - 0.05 - ns ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 3.8 Adc, VGS = 0 Vdc) (Note 2.) (IS = 3.8 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 3.8 3 8 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) (Note 2.) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1339 VSD Vdc ns C MTSF3N02HD TYPICAL ELECTRICAL CHARACTERISTICS : 9 $ 8 , " #$ " 6$ #7 #$ #4 # 7 8 : 6 4 $ # 6 9 # 8 $ 6 4 , " $$ # # #$ 6 4 # 9 # 6 8 9 8 $ " #: 6 6$ 4 # $ $ #$ $ :$ 4 $ 6 9 : 8 Figure 6. On-Resistance versus Drain Current and Gate Voltage # " 6$ " 7 ?#$ # , " #$ Figure 5. On-Resistance versus Gate-to-Source Voltage < 9 Figure 4. Transfer Characteristics $ ?$ 6 Figure 3. On-Region Characteristics " 48 , " #$ # # 9 9 : #$ $ " , " #$ #$ 6 8 # 9 , , Figure 7. On-Resistance Variation with Temperature Figure 8. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 1340 # MTSF3N02HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 11) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) #$ # *. , " #$C " %!! (!! $ %!! !! $ 8 6 (!! 6 8 # Figure 9. Capacitance Variation http://onsemi.com 1341 9 # 8 @ $ $ 6 4 @ # 7 @# 9 # " 48 , " #$ @4 4 9 7 @D # 4 $ " " 48 " 6$ , " #$ ' ! 9 MTSF3N02HD '( 'C 'CC ' Figure 10. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 11. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 6 4 " , " #$ # 6 $ 9 : 8 7 Figure 12. Diode Forward Voltage versus Current http://onsemi.com 1342 MTSF3N02HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 13. Reverse Recovery Time (trr) SAFE OPERATING AREA Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (I DM ) nor rated voltage (V DSS ) is exceeded, and that the transition time (t r, tf ) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (T J(MAX) - T C )/(RJC ). The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." " 8 " #$ ! ! ! Figure 14. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 1343 MTSF3N02HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. &/ " $ # $ *0 # $ ' '# - - " '&'# 6 4 # ' ! 5 5 Figure 15. Thermal Response %&' '(( ') '+ #$ '* Figure 16. Diode Reverse Recovery Waveform http://onsemi.com 1344 ,' " (' , - . / / ' ,*0 " *0 ,' 5# 54 MTSF3N02HD INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 6 6 #8 $#8 #9 4# $ 48 #$9 9$ inches mm Micro8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 0.78 Watts. The power dissipation of the Micro8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the Micro8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 0.78 Watts 160C/W The 160C/W for the Micro8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 0.78 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 1345 MTSF3N02HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 17. Typical Solder Heating Profile http://onsemi.com 1346 MTSF3N02HD TAPE & REEL INFORMATION Micro8 Dimensions are shown in millimeters (inches) 1.60 (.063) 1.50 (.059) 2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B 1.85 (.072) 1.65 (.065) A 0.35 (.013) 0.25 (.010) 5.55 (.218) 5.45 (.215) 12.30 11.70 (.484) (.461) 3.50 (.137) 3.30 (.130) 1.60 (.063) 1.50 (.059) TYP. A FEED DIRECTION 8.10 (.318) 7.90 (.312) 1.50 (.059) 1.30 (.052) SECTION A-A 5.40 (.212) 5.20 (.205) SECTION B-B NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 18.4 (.724) MAX. NOTE 3 13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN. 14.4 (.57) 12.4 (.49) NOTE 4 NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB. http://onsemi.com 1347 (!!. Preferred Device #$%& '( ! ! N-Channel Micro8t These Power MOSFET devices are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. Micro8 devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Miniature Micro8 Surface Mount Package - Saves Board Space * Extremely Low Profile (<1.1 mm) for thin applications such as PCMCIA cards * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life * Logic Level Gate Drive - Can Be Driven by Logic ICs * Diode Is Characterized for Use In Bridge Circuits * Diode Exhibits High Speed, With Soft Recovery * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Mounting Information for Micro8 Package Provided http://onsemi.com 3 AMPERES 30 VOLTS RDS(on) = 40 m N-Channel MARKING DIAGRAM Micro8 CASE 846A STYLE 1 8 WW AA 1 WW = Date Code PIN ASSIGNMENT Source Source Source Gate 1 8 7 6 5 2 3 4 Drain Drain Drain Drain Top View ORDERING INFORMATION Device Package MTSF3N03HDR2 Micro8 Shipping 4000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 4 1348 Publication Order Number: MTSF3N03HD/D MTSF3N03HD MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous 1 SQ. FR-4 or G-10 PCB Figure 1 below Steady State Minimum FR-4 or G-10 PCB Figure 2 below Steady State Thermal Resistance - Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current - Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Thermal Resistance - Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current - Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 5.0 mH, RG = 25 W) 1. Repetitive rating; pulse width limited by maximum junction temperature. Figure 1. 1, Square FR-4 or G-10 PCB Symbol Max Unit VDSS VDGR 30 V 30 V VGS RTHJA PD 20 V 70 1.79 14.29 5.7 4.5 45 C/W Watts mW/C A A A 160 0.78 6.25 3.8 3.0 30 C/W Watts mW/C A A A ID ID IDM RTHJA PD ID ID IDM TJ, Tstg - 55 to 150 EAS 200 Figure 2. Minimum FR-4 or G-10 PCB http://onsemi.com 1349 C mJ MTSF3N03HD ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 - - 27 - - - - - - 1.0 25 - - 100 1.0 - 1.5 4.5 - - - - 35 45 40 60 gFS 2.0 - - Mhos Ciss - 420 - pF Coss - 190 - Crss - 65 - td(on) - 7.0 - tr - 19 - td(off) - 32 - tf - 36 - td(on) - 7.0 - OFF CHARACTERISTICS (Cpk 2.0) Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) (Notes 2. & 4.) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 Vdc) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Vdc mV/C Adc nAdc ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) (Note 4.) (Cpk 2.0) (Note 4.) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 3.8 Adc) (VGS = 4.5 Vdc, ID = 1.9 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 1.9 Adc) VGS(th) Vdc RDS(on) mV/C m DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDS = 15 Vdc, ID = 3.7 Adc, VGS = 10 Vdc, RG = 6 ) (Note 2.) Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 1.9 Adc, VGS = 4.5 Vdc, RG = 6 ) (Note 2.) Fall Time Gate Charge (VDS = 24 Vdc, ID = 3.7 Adc, VGS = 10 Vdc) tr - 11 - td(off) - 29 - tf - 23 - QT - 18.5 26 Q1 - 1.4 - Q2 - 5.5 - Q3 - 7.1 - - - 0.82 0.7 1.0 - trr - 28 - ta - 14 - tb - 14 - QRR - 0.028 - ns ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 3.7 Adc, VGS = 0 Vdc) (Note 2.) (IS = 3.7 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 3.7 3 7 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) (Note 2.) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA http://onsemi.com 1350 VSD Vdc ns C MTSF3N03HD TYPICAL ELECTRICAL CHARACTERISTICS " 6$ $ 44 9 , " #$ #7 9 4 6 #: 4 # #$ #4 $ 6 4 # #$ , " $$ # $ $ # 4 4$ 6 4 # # 6 9 8 , " #$ $$ " 6$ $ 6$ 6 4$ 4 $ $ #$ $ :$ # 4 6 $ 9 Figure 6. On-Resistance versus Drain Current and Gate Voltage " " 7 ?#$ 6 9 Figure 5. On-Resistance versus Gate-to-Source Voltage < #$ Figure 4. Transfer Characteristics $ ?$ # Figure 3. On-Region Characteristics " 48 , " #$ # $ 9 #$ $ " , " #$ #$ $ $ # #$ , , Figure 7. On-Resistance Variation with Temperature Figure 8. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 1351 4 MTSF3N03HD POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 11) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) $ *. # " " , " #$C %!! 7 (!! 9 %!! 4 !! (!! $ $ $ # Figure 9. Capacitance Variation http://onsemi.com 1352 #$ 4 4 @ #$ # 8 9 $ 6 @ @# # @4 4 " 4: , " #$ 9 7 # $ @D 8 $ # " $ " 4: " , " #$ ' ! # MTSF3N03HD 'C 'CC '( ' Figure 10. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 11. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 13. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 6 " , " #$ 4 # $ 9 : 8 7 Figure 12. Diode Forward Voltage versus Current http://onsemi.com 1353 MTSF3N03HD %&' " 4 &! '))( 1EE 1!%'H '(( %D2 1EE 1!%'H '(( '+ ') ' Figure 13. Reverse Recovery Time (trr) SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 15). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curve (Figure 14) defines the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For #$ " # " #$ ! ! GG - , ! " 4 " $ " 7 "$ # $ $ #$ $ :$ #$ , , Figure 14. Maximum Rated Forward Biased Safe Operating Area Figure 15. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 1354 $ MTSF3N03HD TYPICAL ELECTRICAL CHARACTERISTICS '23)'.. &/ " $ # $ *0 # $ ' '# - - " '&'# 6 4 # ' ! 5 5 Figure 16. Thermal Response %&' '(( ') '+ #$ '* Figure 17. Diode Reverse Recovery Waveform http://onsemi.com 1355 ,' " (' , - . / / ' ,*0 " *0 ,' 5# 54 MTSF3N03HD INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 6 6 #8 $#8 #9 4# $ 48 #$9 9$ inches mm Micro8 POWER DISSIPATION into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 0.78 Watts. The power dissipation of the Micro8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the Micro8 package, PD can be calculated as follows: PD = PD = 150C - 25C = 0.78 Watts 160C/W The 160C/W for the Micro8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 0.78 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) - TA RJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 1356 MTSF3N03HD TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 "SOAK" 160C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT 150C 150C 100C 140C 100C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile http://onsemi.com 1357 MTSF3N03HD TAPE & REEL INFORMATION Micro8 Dimensions are shown in millimeters (inches) 1.60 (.063) 1.50 (.059) 2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B 1.85 (.072) 1.65 (.065) A 0.35 (.013) 0.25 (.010) 5.55 (.218) 5.45 (.215) 12.30 11.70 (.484) (.461) 3.50 (.137) 3.30 (.130) 1.60 (.063) 1.50 (.059) TYP. A FEED DIRECTION 8.10 (.318) 7.90 (.312) 1.50 (.059) 1.30 (.052) SECTION A-A 5.40 (.212) 5.20 (.205) SECTION B-B NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 18.4 (.724) MAX. NOTE 3 13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN. 14.4 (.57) 12.4 (.49) NOTE 4 NOTES: 1. CONFORMS TO EIA-481-1. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB. http://onsemi.com 1358 9! Preferred Device #$%& '( ! N-Channel TO-247 This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Isolated Mounting Hole http://onsemi.com 32 AMPERES 200 VOLTS RDS(on) = 75 m N-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) 4 Symbol Value Unit Drain-Source Voltage VDSS 200 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 200 Vdc Gate-Source Voltage - Continuous VGS 20 Vdc Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 32 19 128 Adc Total Power Dissipation Derate above 25C PD 180 1.44 Watts W/C TJ, Tstg -55 to 150 C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 50 Vdc, VGS = 10 Vpk, IL = 32 Apk, L = 1.58 mH, RG = 25 ) EAS 810 mJ Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient RJC RJA 0.7 40 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 260 C Rating Operating and Storage Temperature Range TO-247AE CASE 340K Style 1 1 2 MARKING DIAGRAM & PIN ASSIGNMENT 3 4 Drain Apk MTW32N20E LLYWW 1 Gate 3 Source 2 Drain LL Y WW = Location Code = Year = Work Week ORDERING INFORMATION Device MTW32N20E Package Shipping TO-247 30 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 4 1359 Publication Order Number: MTW32N20E/D MTW32N20E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Symbol Min Typ Max Unit 200 - - 247 - - Vdc mV/C - - - - 250 1000 - - 100 nAdc 2.0 - - 8.0 4.0 - Vdc mV/C - 0.064 0.075 Ohm - - - - 3.0 2.7 gFS 12 - - mhos Ciss - 3600 5000 pF Coss - 130 250 Crss - 690 1000 td(on) - 25 50 tr - 120 240 td(off) - 75 150 tf - 91 182 QT - 85 120 Q1 - 12 - Q2 - 40 - Q3 - 30 - - - 1.1 0.9 2.0 - trr - 280 - ta - 195 - tb - 85 - QRR - 2.94 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 5.0 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 13 - nH Characteristic OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 V, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0) (VDS = 200 Vdc, VGS = 0, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 16 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 32 Adc) (ID = 16 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 16 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 0, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 1. & 2.) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 100 Vdc, ID = 32 Adc, VGS = 10 Vdc Vdc, RG = 6.2 ) Fall Time Gate Charge (VDS = 160 Vdc, ID = 32 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS (Note 1.) .(M)( E')D1 (IS = 32 Adc, VGS = 0) (IS = 16 Adc, VGS = 0, TJ = 125C) Reverse Recovery Time (IS = 32 Adc, VGS = 0, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1360 MTW32N20E TYPICAL ELECTRICAL CHARACTERISTICS " , " #$ $ 7 8 8 9 : 6 9 # , " ?$$ 6 #$ 4 # $ # 9 8 6 9 8 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics , " 8 #$ 9 ?$$ 6 # # # " 6 8 #6 9 4# 6 68 $9 96 9 6 , " #$ 7 8 " : $ 9 $ 8 9 #6 4# 6 68 $9 96 Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage #$ " " " 9 # # < , " #$ $ # # $ $ #$ #$ $ :$ #$ $ #$ $ $ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1361 # MTW32N20E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by L di/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) " " , " #$ *. 8 (!! 9 6 %!! # !! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1362 MTW32N20E 9 # 8 9 6 # @ 8 8 @# @ 9 6 6 # @4 # 4 6 $ 9 : @ 8 7 'CC , " #$ " 4# " " # ' ! # , " #$ " 4# " 9 # '( 'C ' # # Figure 9. Gate-To-Source and Drain-To-Source Voltage versus Total Charge # # Figure 8. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS , " #$ " 4 # # 6 9 8 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1363 MTW32N20E " # " #$ # ! # # # - , SAFE OPERATING AREA # # # :$ " 4# 9 6$ 4 $ #$ Figure 13. Maximum Rated Forward Biased Safe Operating Area (' < # # $ Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature " $ # $ *0 # # $ :$ #$ , , ' '# - - " '&'# # # # ' ! Figure 11. Thermal Response http://onsemi.com 1364 # ,' " (' , , " :&/ > - . / / ' ,*0 " *0 ,' # 9! Preferred Device #$%& '( ! N-Channel TO-247 This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Isolated Mounting Hole Reduces Mounting Hardware http://onsemi.com 32 AMPERES 250 VOLTS RDS(on) = 80 m N-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 250 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 250 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 40 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 32 25 96 Adc Total Power Dissipation Derate above 25C PD 250 2.0 Watts W/C TJ, Tstg -55 to 150 C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 100 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 ) EAS 600 mJ Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient RJC RJA 0.50 40 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 260 C Rating Operating and Storage Temperature Range 4 TO-247AE CASE 340K Style 1 1 2 MARKING DIAGRAM & PIN ASSIGNMENT 3 4 Drain Apk MTW32N25E LLYWW 1 Gate 3 Source 2 Drain LL Y WW = Location Code = Year = Work Week ORDERING INFORMATION Device MTW32N25E Package Shipping TO-247 30 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 1365 Publication Order Number: MTW32N25E/D MTW32N25E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 250 - 300 380 - - Vdc mV/C - - - - 10 100 - - 100 2.0 - - 7.0 4.0 - mV/C - 0.07 0.08 Ohm - - 2.2 - 2.6 2.5 gFS 11 20 - mhos Ciss - 3800 5350 pF Coss - 726 1020 Crss - 183 370 td(on) - 31 60 tr - 133 266 td(off) - 93 186 tf - 108 216 QT - 97 136 Q1 - 22 - Q2 - 43 - Q3 - 41 - - - 1.0 0.92 1.5 - trr - 312 - ta - 220 - tb - 93 - QRR - 3.6 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 4.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 13 - nH OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 250 Vdc, VGS = 0 Vdc) (VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 16 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 32 Adc) (ID = 16 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 16 Adc) Vdc Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD= 125 Vdc, ID = 32 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 200 Vdc, ID = 32 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 32 Adc, VGS = 0 Vdc) (IS = 32 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 14) Adc VGS = 0 Vdc, Vdc (IS = 32 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1366 MTW32N25E TYPICAL ELECTRICAL CHARACTERISTICS 7 8 68 6 9 4# #6 9 $ 8 $9 96 : " , " #$ 9 4 # 6 $ 9 : 7 8 #$ 68 6 4# #6 9 # 8 #$ 9 $$ 6 8 9 4# 68 #6 6 $9 96 86 9 : 8 , " #$ 8 :9 " :# $ 98 96 8 Figure 3. On-Resistance versus Drain Current and Temperature 9 #6 6 4# 68 $9 96 Figure 4. On-Resistance versus Drain Current and Gate Voltage " " # " , " #$ 9 < $ Figure 2. Transfer Characteristics # # 8 6 F$ 6 Figure 1. On-Region Characteristics , " # 4 " , " $$ 6 # $9 8 96 F#$ #$ $ :$ , , #$ $ #$ Figure 5. On-Resistance Variation with Temperature $ $ # Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1367 #$ MTW32N25E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: *. td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 8 " : %!! " , " #$ 9 $ 6 %!! (!! 4 # !! (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1368 # 4 @ " #$ " 4# " , " #$ #$ 8 @ # @# 9 $ 6 # @4 # " 4# , " #$ 4 6 $ 9 : 8 7 $ ' ! MTW32N25E '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 4# " , " #$ #6 9 8 $ $$ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1369 MTW32N25E SAFE OPERATING AREA 9 " # " #$ - , ! ! ! 6 4 # #$ $ :$ #$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 14. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " 4# $ " $ # $ # *0 ' '# - - " '&'# $ 6 4 # ' ! Figure 12. Thermal Response %&' '(( ') '+ #$ '* Figure 13. Diode Reverse Recovery Waveform http://onsemi.com 1370 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 9! Preferred Device #$%& '( ! N-Channel TO-247 This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Isolated Mounting Hole Reduces Mounting Hardware http://onsemi.com 35 AMPERES 150 VOLTS RDS(on) = 50 m N-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 150 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 150 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 40 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 35 26.9 105 Adc Total Power Dissipation Derate above 25C PD 180 1.45 Watts W/C TJ, Tstg -55 to 150 C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 80 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 ) EAS 600 mJ Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient RJC RJA 0.70 62.5 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 260 C Rating Operating and Storage Temperature Range 4 TO-247AE CASE 340K Style 1 1 2 MARKING DIAGRAM & PIN ASSIGNMENT 3 4 Drain Apk MTW35N15E LLYWW 1 Gate 3 Source 2 Drain LL Y WW = Location Code = Year = Work Week ORDERING INFORMATION Device MTW35N15E Package Shipping TO-247 30 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 4 1371 Publication Order Number: MTW35N15E/D MTW35N15E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 150 - - 210 - - Vdc mV/C - - - - 10 100 - - 100 nAdc 2.0 - - 7.0 4.0 - Vdc mV/C - - 0.05 Ohm - - 1.45 - 1.8 1.7 gFS 11 18 - mhos Ciss - 3600 5040 pF Coss - 855 1170 Crss - 165 330 td(on) - 28 56 tr - 170 346 td(off) - 90 180 tf - 103 210 QT - 98 137 Q1 - 19 - Q2 - 49 - Q3 - 40 - - - 0.95 0.9 1.5 - trr - 200 - ta - 167 - tb - 32 - QRR - 1.63 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 4.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 13 - nH OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 150 Vdc, VGS = 0 Vdc) (VDS = 150 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 17.5 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 35 Adc) (ID = 17.5 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 17.5 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 75 Vdc, ID = 35 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 120 Vdc, ID = 35 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 35 Adc, VGS = 0 Vdc) (IS = 35 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 14) Adc VGS = 0 Vdc, Vdc (IS = 35 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1372 MTW35N15E TYPICAL ELECTRICAL CHARACTERISTICS 8 : $ 6 4 9 # $ GG 7 $ $ # #$ 4$ 4 4 # #$ 6 4 $$ # # $ 4 6 9 : 6: 9 : 8 6$ 64 " 6 47 $ 4: 4$ # 4 6 $ 9 : Figure 4. On-Resistance versus Drain Current and Gate Voltage " " :$ GG < $ , " #$ Figure 3. On-Resistance versus Drain Current and Temperature $ $ F$ 6 Figure 2. Transfer Characteristics $ # , " $$ 4 Figure 1. On-Region Characteristics 9 #$ #$ , " 6 : $ # 6 " 8 9 GG 9 : " 7 , " #$ : " , " #$ #$ F#$ #$ $ :$ , , #$ $ Figure 5. On-Resistance Variation with Temperature $ Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1373 $ MTW35N15E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) " " , " #$ *. 8 9 (!! %!! 6 # (!! $ $ !! $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1374 # @ @# @ 8 9 9 6 6 , " #$ " 4$ # @4 # 6 9 " :$ " 4$ " , " #$ 8 8 # ' ! # MTW35N15E '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 4$ " , " #$ 4 #$ # $ $ $ $$ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1375 MTW35N15E SAFE OPERATING AREA 9 " # " #$ - , ! ! ! ! " 4$ $ 6 4 # #$ $ :$ #$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # $ *0 # ' $ '# - - " '&'# 6 # ' ! 4 Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1376 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 9 Preferred Device #$%& '( N-Channel TO-247 This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Isolated Mounting Hole Reduces Mounting Hardware http://onsemi.com 45 AMPERES 100 VOLTS RDS(on) = 35 m N-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 100 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 100 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 40 Vdc Vpk Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) ID ID IDM 45 34.6 135 Adc Total Power Dissipation Derate above 25C PD 180 1.44 Watts W/C TJ, Tstg -55 to 150 C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 45 Apk, L = 0.8 mH, RG = 25 ) EAS 810 mJ Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient RJC RJA 0.70 62.5 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 260 C Rating Operating and Storage Temperature Range 4 TO-247AE CASE 340K Style 1 1 2 MARKING DIAGRAM & PIN ASSIGNMENT 3 4 Drain Apk MTW45N10E LLYWW 1 Gate 3 Source 2 Drain LL Y WW = Location Code = Year = Work Week ORDERING INFORMATION Device MTW45N10E Package Shipping TO-247 30 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 1377 Publication Order Number: MTW45N10E/D MTW45N10E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 100 - - 116 - - Vdc mV/C - - - - 10 100 - - 100 2.0 - - 7.0 4.0 - mV/C - 0.027 0.035 Ohm - - 1.13 - 2.16 1.53 gFS 12 - - mhos Ciss - 3480 5000 pF Coss - 1240 2000 Crss - 315 650 td(on) - 25 50 tr - 234 470 td(off) - 83 170 tf - 116 240 QT - 106 220 Q1 - 26 - Q2 - 54 - Q3 - 44 - - - 1.09 1.04 1.635 - trr - 166 - ta - 118 - tb - 48 - QRR - 1.1 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 4.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 7.5 - nH OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 22.5 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 45 Adc) (ID = 22.5 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 22.5 Adc) Vdc Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD= 50 Vdc, ID = 45 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 80 Vdc, ID = 45 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 1.) (IS = 45 Adc, VGS = 0 Vdc) (IS = 45 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 14) Adc VGS = 0 Vdc, Vdc (IS = 45 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1378 MTW45N10E TYPICAL ELECTRICAL CHARACTERISTICS , " #$ : 7 8 : 7 9 9 $ 6 4 $ # 6 $ $ $ #$ 4 4$ 6 6$ : #$ 9 $ 6 4 # # #$ 4 4$ 6 6$ $ $$ 9 9$ : :$ 8 8$ 7 $ Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics " , " 4 #$ $$ # # 4 $ 6 9 : 8 7 4# , " #$ 4 " #8 #9 $ #6 ## # 4 $ 6 9 : 8 7 Figure 4. On-Resistance versus Drain Current and Gate Voltage " " ##$ " 9 < Figure 3. On-Resistance versus Drain Current and Temperature # , " $$ 6 # 8 8 " 7 # 8 , " #$C C #$C 6 F$ F#$ #$ $ :$ , , #$ $ Figure 5. On-Resistance Variation with Temperature # 6 9 8 Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1379 MTW45N10E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) *. 8 " " , " #$ %!! 9 6 (!! %!! !! # (!! $ $ $ # #$ Figure 7. Capacitance Variation http://onsemi.com 1380 MTW45N10E @# 8 8 @ 9 9 6 6 # # " 6$ , " #$ @4 4 6 $ : 9 8 7 # ' ! " $ " 6$ " , " #$ # @ # '( 'C 'CC ' @ Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 6$ " 6 " #$ , 4$ 4 #$ # $ $ $ $9 9# 98 :6 8 89 7# 78 6 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1381 MTW45N10E SAFE OPERATING AREA " # " #$ ! ! - , ! ! " 6$ 8 9 6 # #$ $ :$ $ #$ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature (' <.. " $ # *0 $ # ' $ '# - - " '&'# 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1382 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 5 Preferred Device #$%& '( N-Channel TO-264 This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain-to-source diode with fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters, PWM motor controls, and other inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 55 AMPERES 200 VOLTS RDS(on) = 28 m N-Channel MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-Source Voltage VDSS 200 Vdc Drain-Gate Voltage (RGS = 1 M) VDGR 200 Vdc Gate-Source Voltage - Continuous - Non-Repetitive (tp 10 ms) VGS VGSM 20 40 Vdc Vpk Drain Current - Continuous @ TC = 25C Drain Current - Single Pulse (tp 10 s) ID IDM 55 165 Adc Apk Total Power Dissipation Derate above 25C PD 300 2.38 Watts W/C TJ, Tstg -55 to 150 C Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 110 Apk, L = 0.3 mH, RG = 25 ) EAS 3000 mJ Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient RJC RJA 0.42 40 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 260 C Rating Operating and Storage Temperature Range TO-264 CASE 340G Style 1 1 2 3 MARKING DIAGRAM & PIN ASSIGNMENT MTY55N20E LLYWW 1 Gate 3 Source 2 Drain LL Y WW = Location Code = Year = Work Week ORDERING INFORMATION Device MTY55N20E Package Shipping TO-264 25 Units/Rail Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 3 1383 Publication Order Number: MTY55N20E/D MTY55N20E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 200 - - 250 - - Vdc mV/C - - - - 10 200 - - 100 nAdc 2 - - 7 4 - Vdc mV/C - - 0.028 Ohm - - 1.3 - 1.6 1.8 gFS 30 37 - mhos Ciss - 7200 10080 pF Coss - 1800 2520 Crss - 460 920 td(on) - 33 66 tr - 200 400 td(off) - 150 300 tf - 170 340 QT - 245 343 Q1 - 33 - Q2 - 128 - Q3 - 79 - - - 0.75 1.1 1.2 - trr - 310 - ta - 220 - tb - 90 - QRR - 4.6 - C Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) LD - 4.5 - nH Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) LS - 13 - nH OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 250 A) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS Adc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 27.5 Adc) RDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 55 Adc) (ID = 27.5 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 27.5 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn-On Delay Time (VDD = 100 Vdc, ID = 55 Adc, VGS = 10 Vdc Vdc, RG = 4.7 ) Rise Time Turn-Off Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 160 Vdc, ID = 55 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 55 Adc, VGS = 0 Vdc) (IS = 55 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure Fi 14) (See (IS = 55 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns INTERNAL PACKAGE INDUCTANCE 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 1384 MTY55N20E TYPICAL ELECTRICAL CHARACTERISTICS 7 8 9 9 6 $ # 6 $ $ # #$ 4 4$ 6 8 9 6 # , " ?$$ #$ # #$ 4 4$ 6 6$ $ $$ 9 Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics $ " , " 6 4 #$ # ?$$ # 6 9 8 # < : # 8 " , " #$ 9$ : #: , " #$ #9 " #$ #6 $ #4 ## # 6 9 8 # Figure 3. On-Resistance versus Drain Current and Temperature Figure 4. On-Resistance versus Drain Current and Gate Voltage # :$ " " #:$ $ " , " #$ # #$ :$ $ #$ #$ ?$ ?#$ #$ $ :$ #$ $ $ $ , , Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 1385 # MTY55N20E POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) #6 " *. # " , " #$ %!! 9 (!! # %!! 8 !! 6 (!! $ $ $ # Figure 7. Capacitance Variation http://onsemi.com 1386 #$ # @ 8 9 9 @# @ # , " #$ " $$ 6 # 8 6 @4 $ $ #$ # ' ! #6 # MTY55N20E " " $$ " , " #$ '( 'C 'CC ' @D Figure 8. Gate Charge versus Gate-to-Source Voltage Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 9 $ " , " #$ 6 4 # $ $$ 9 9$ : :$ 8 8$ 7 7$ Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 1387 MTY55N20E SAFE OPERATING AREA 4 " # " #$ - , ! ! ( '.. < ! ! " $$ # #$ $ :$ #$ $ , , Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature " $ # *0 $ # ' '# - - " '&'# $ 6 4 # ' ! Figure 13. Thermal Response %&' '(( ') '+ #$ '* Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 1388 ,' " (' , - . / / ' ,*0 " *0 ,' 5 5 ! Preferred Device 0 0 '( N-Channel TO-92 http://onsemi.com MAXIMUM RATINGS Rating Symbol Value Unit Drain-Source Voltage VDSS 60 V Drain-Gate Voltage VDGR 60 V Gate-Source Voltage - Continuous - Non-repetitive (tp 50 s) VGS VGSM 20 40 Vdc Vpk ID 200 mA Pulsed Drain Current IDM 500 mA Power Dissipation @ TC = 25C Derate above 25C PD 350 2.8 mW mW/C TJ, Tstg - C Characteristics Symbol Max Unit Thermal Resistance, Junction to Ambient RJA 312.5 C/W Maximum Lead Temperature for Soldering Purposes, 1/16" from case for 10 seconds TL 300 C Continuous Drain Current Operating and Storage Temperature 200 mAMPS 60 VOLTS RDS(on) = 1.2 N-Channel THERMAL CHARACTERISTICS TO-92 CASE 29 Style 22 12 MARKING DIAGRAM & PIN ASSIGNMENT 3 VN0300L YWW 1 Source 3 Drain 2 Gate Y WW = Year = Work Week ORDERING INFORMATION Device Package Shipping VN0300L TO-92 1000 Units/Box VN0300LRLRA TO-92 2000 Tape & Reel VN0300LRLRE TO-92 2000 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 1389 Publication Order Number: VN0300L/D VN0300L ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)DSS 30 - V - - 10 500 STATIC CHARACTERISTICS Drain-Source Breakdown Voltage (VDS = 0, ID = 10 A) A Zero Gate Voltage Drain Current (VDS = 48 Vdc, VGS = 0) (VDS = 48 Vdc, VGS = 0, TA = 125C) IDSS Gate-Body Leakage (VDS = 0, VGS = 30 V) IGSS - 100 nA VGS(th) 0.8 2.5 V ID(on) 1.0 - A - - 3.3 1.2 gfs 200 - mS Ciss - 100 pF Coss - 95 pF Crss - 25 pF ton - 30 ns toff - 30 ns Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) On-State Drain Current (Note 1.) (VDS = VGS, ID = 1.0 mA) Drain-Source On Resistance (Note 1.) (VGS = 5.0 V, ID = 0.3 A) (VGS = 10 V, ID = 1.0 A) rDS(on) Forward Transconductance (Note 1.) (VDS = 10 V, ID = 0.5 A) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 15 Vd Vdc, VGS = 0 0, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS Turn-On Time Turn-Off Time (VDD = 25 Vdc, ID = 1.0 A, RL = 24 , RG = 25 ) 1. Pulse Test; Pulse Width < 300 ms, Duty Cycle v 2.0%. http://onsemi.com 1390 Preferred Device 0 0 '( N-Channel TO-92 http://onsemi.com MAXIMUM RATINGS Symbol Value Unit Drain-Source Voltage Rating VDSS 60 Vdc Drain-Gate Voltage (RGS = 1.0 M) VDGR 60 Vdc Gate-Source Voltage - Continuous - Non-repetitive (tp 50 s) VGS VGSM 20 40 Vdc Vpk Drain Current - Continuous - Pulsed 150 1000 PD 400 3.2 mW mW/C TJ, Tstg -55 to +150 C Characteristic Symbol Max Unit Thermal Resistance, Junction to Ambient RJA 312.5 C/W TL 300 C Operating and Storage Temperature Range N-Channel mAdc ID IDM Total Power Dissipation @ TA = 25C Derate above 25C 150 mAMPS 60 VOLTS RDS(on) = 7.5 THERMAL CHARACTERISTICS Maximum Lead Temperature for Soldering Purposes, 1/16 from case for 10 seconds TO-92 CASE 29 Style 22 12 3 MARKING DIAGRAM & PIN ASSIGNMENT VN2222LL YWW 1 Source 3 Drain 2 Gate Y WW = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 1393 of this data sheet. Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 1391 Publication Order Number: VN2222LL/D VN2222LL ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Symbol Min Max Unit V(BR)DSS 60 - Vdc - - 10 500 IGSSF - -100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) VGS(th) 0.6 2.5 Vdc Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 0.5 Adc) (VGS = 10 Vdc, ID = 0.5 Vdc, TC = 125C) rDS(on) - - 7.5 13.5 Drain-Source On-Voltage (VGS = 5.0 Vdc, ID = 200 mAdc) (VGS = 10 Vdc, ID = 500 mAdc) VDS(on) Characteristic OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 100 Adc) Zero Gate Voltage Drain Current (VDS = 48 Vdc, VGS = 0) (VDS = 48 Vdc, VGS = 0, TJ = 125C) Adc IDSS Gate-Body Leakage Current, Forward (VGSF = 30 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) On-State Drain Current (VGS = 10 Vdc, VDS 2.0 VDS(on)) Forward Transconductance (VDS = 10 Vdc, ID = 500 mAdc) - - Vdc 1.5 3.75 ID(on) 750 - mA gfs 100 - mhos Ciss - 60 pF Coss - 25 Crss - 5.0 ton - 10 toff - 10 DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 0, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 1.) Turn-On Delay Time Turn-Off Delay Time (VDD = 15 Vdc, ID = 600 mA, Rgen = 25 , RL = 23 ) 1. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2.0%. http://onsemi.com 1392 ns VN2222LL # " 7 6 # 8 : 8 9 9 6 $ 6 # ( < #$ " 8 ?$$ #$ 9 6 # 4 # 4 6 $ 9 : 8 7 4 6 $ 9 : 8 Figure 2. Transfer Characteristics " " # 9 6 # 8 9 6 9 # Figure 1. Ohmic Region ## 8 ?? #6 # ? # 5# 59 56 5 '2 < 8 9 " #$ " " $ 7$ 7 8$ 8 :$ : 9 # 5# 59 5 Figure 4. Temperature versus Gate Threshold Voltage ORDERING INFORMATION Package Shipping VN2222LL TO-92 1000 Unit/Box VN2222LLRL TO-92 2000 Tape & Reel VN2222RLRA TO-92 2000 Tape & Reel VN2222RLRM TO-92 1000 Unit/Box http://onsemi.com 1393 # $ Figure 3. Temperature versus Static Drain-Source On-Resistance Device 7 56 Preferred Device 0 0 '( N-Channel TO-92 http://onsemi.com MAXIMUM RATINGS Rating Symbol Value Unit Drain-Source Voltage VDSS 240 Vdc Drain-Gate Voltage VDGR 60 Vdc Gate-Source Voltage - Continuous - Non-repetitive (tp 50 s) VGS VGSM 20 40 Vdc Vpk ID 200 mAdc Pulsed Drain Current IDM 500 mAdc Power Dissipation @ TC = 25C Derate above 25C PD 350 2.8 mW mW/C TJ, Tstg - C Characteristic Symbol Max Unit Thermal Resistance, Junction to Ambient RJA 312.5 C/W Maximum Lead Temperature for Soldering Purposes, 1/16 from case for 10 seconds TL 300 C Continuous Drain Current Operating and Storage Temperature 200 mAMPS 240 VOLTS RDS(on) = 6 N-Channel THERMAL CHARACTERISTICS TO-92 CASE 29 Style 22 12 3 MARKING DIAGRAM & PIN ASSIGNMENT VN2406L YWW 1 Source 3 Drain 2 Gate Y WW = Year = Work Week ORDERING INFORMATION Device Package Shipping VN2406L TO-92 1000 Units/Box VN2406LZL1 TO-92 2000 Ammo Pack Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 1394 Publication Order Number: VN2406L/D VN2406L ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)DSS 240 - Vdc - - 10 500 STATIC CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 100 A) Adc Zero Gate Voltage Drain Current (VDS = 120 Vdc, VGS = 0) (VDS = 120 Vdc, VGS = 0, TA = 125C) IDSS Gate- Body Leakage (VDS = 0, VGS = 15 V) IGSS - 100 nAdc VGS(th) 0.8 2.0 Vdc ID(on) 1.0 - Adc - - 10 6.0 gfs 300 - mS Ciss - 125 pF Coss - 50 pF Crss - 20 pF t(on) - 8.0 ns Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) On-State Drain Current (Note 1.) (VGS = 10 V, VDS 2.0 VDS(on)) Drain-Source On Resistance (Note 1.) (VGS = 2.5 V, ID = 0.1 A) (VGS = 10 V, ID = 0.5 A) rDS(on) Forward Transconductance (Note 1.) (VDS = 10 V, ID = 0.5 A) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 0, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS Turn-On Time (VDD = 60 Vd Vdc, ID = 0.4 0 4 A, A RL = 150 , RG = 25 ) Turn-Off Time 1. Pulse Test; Pulse Width < 300 s, Duty Cycle v 2.0%. http://onsemi.com 1395 t(r) - 8.0 ns t(off) - 23 ns t(f) - 34 ns Preferred Device 0 0 '( N-Channel TO-92 http://onsemi.com MAXIMUM RATINGS Rating Symbol Value Unit Drain-Source Voltage VDSS 240 Vdc Drain-Gate Voltage VDGR 60 Vdc Gate-Source Voltage - Continuous - Non-repetitive (tp 50 s) VGS VGSM 20 40 Vdc Vpk ID 200 mAdc Pulsed Drain Current IDM 500 mAdc Power Dissipation @ TC = 25C Derate above 25C PD 350 2.8 mW mW/C TJ, Tstg - C Characteristic Symbol Max Unit Thermal Resistance, Junction to Ambient RJA 312.5 C/W Maximum Lead Temperature for Soldering Purposes, 1/16 from case for 10 seconds TL 300 C Continuous Drain Current Operating and Storage Temperature 200 mAMPS 60 VOLTS RDS(on) = 10 N-Channel THERMAL CHARACTERISTICS TO-92 CASE 29 Style 22 12 3 MARKING DIAGRAM & PIN ASSIGNMENT VN2410L YWW 1 Source 3 Drain 2 Gate Y WW = Year = Work Week ORDERING INFORMATION Device Package Shipping VN2410L TO-92 1000 Units/Box VN2410LZL1 TO-92 2000 Ammo Pack Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2000 November, 2000 - Rev. 2 1396 Publication Order Number: VN2410L/D VN2410L ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)DSS 240 - Vdc - - 10 500 STATIC CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 100 A) Adc Zero Gate Voltage Drain Current (VDS = 120 Vdc, VGS = 0) (VDS = 120 Vdc, VGS = 0, TA = 125C) IDSS Gate- Body Leakage (VDS = 0, VGS = 15 V) IGSS - 100 nAdc VGS(th) 0.8 2.0 Vdc ID(on) 1.0 - Adc - - 10 10 gfs 300 - mS Ciss - 125 pF Coss - 50 pF Crss - 20 pF t(on) - 8.0 ns Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) On-State Drain Current (Note 1.) (VGS = 10 V, VDS 2.0 VDS(on)) Drain-Source On Resistance (Note 1.) (VGS = 2.5 V, ID = 0.1 A) (VGS = 10 V, ID = 0.5 A) rDS(on) Forward Transconductance (Note 1.) (VDS = 10 V, ID = 0.5 A) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vd Vdc, VGS = 0 0, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS Turn-On Time (VDD = 60 Vd Vdc, ID = 0.4 0 4 A, A RL = 150 , RG = 25 ) Turn-Off Time 1. Pulse Test; Pulse Width < 300 s, Duty Cycle v 2.0%. http://onsemi.com 1397 t(r) - 8.0 ns t(off) - 23 ns t(f) - 34 ns http://onsemi.com 1398 CHAPTER 2 MOSFET Application Note Abstracts http://onsemi.com 1399 http://onsemi.com 1400 AN1040 - Mounting Considerations for Power Semiconductors The operating environment is a vital factor in setting current and power ratings of a semiconductor device. Reliability is increased considerably for relatively small reductions in junction temperature. Faulty mounting not only increases the thermal gradient between the device and its heat sink, but can also cause mechanical damage. This comprehensive note shows correct and incorrect methods of mounting all types of discrete packages, and discusses methods of thermal system evaluation. AN1083 - Basic Thermal Management of Power Semiconductors Switching audio amplifiers were impractical before the availability of complementary Power MOSFETs. Now, gate drive circuitry is simpler than for bipolar transistors, and the MOS devices operate more efficiently at higher frequencies. This detailed discussion of switching amplifier design is supported by a 72W Class D circuit. AN1090 - Understanding and Predicting Power MOSFET Switching Behavior SPICE is a user-friendly, general-purpose circuit simulation program for non-linear DC, non-linear transient and linear AC analysis. It is now available in various commmercial versions for use on personnel computers. ON and LAAS-CNRS Research Laboratory have bult a TMOS Power MOSFET library to simplify power dissipation simulation using SPICE. This note describes how to use the library; the physics of the Power MOSFET; the implementation of the model within SPICE; the method of extracting the parameters for the library; and a comparison of practical and simulated characteristics. AN1102 - Interfacing Power MOSFETs to Logic Devices Most popular power MOSFETs need 10 volts of gate drive to support their maximum drain current. This creates problems when attempting to drive from 5V logic. The new logic level power MOSFETs solve some but not all of the problems. This note discusses easy methods of directly interfacing both types of MOSFET to TTL and CMOS logic, and to microprocessors such as the M68HC11. Discusses a method of calculating switching times, to minimize switching losses, and stresses the significance of logic power supply variations. AN1317 - High-Current DC Motor Drive Uses Low On-Resistance Surface Mount MOSFETs Surface mount technology have often been used in controllers for small disk drive motors with peak currents of 1 or 2 amps. Now the availability of low ON-resistance, surface mount power MOSFETs has increased the current handling capability of surface mount technology. This application note presents a 5 amp DC motor drive board (DEVB148) using all surface mount components apart from the filter capacitor. It features a cycle-by-cycle current limit and is intended for direct control from a microcontroller. AN1319 - Design Considerations for a Low Voltage N-Channel H-Bridge Motor Drive Complementary MOSFET half-bridges are commonly used in low voltage motor drives to simplify gate drive design. However, the P-channel FET in the half-bridge usually has higher ON-resistance or is larger and more expensive then the N-channel half-bridge, which uses silicon more efficiently and minimizes cost and conduction losses. The trade-off is usually a more complex gate drive; this note looks at ways of minimizing gate drive complexity, and also discusses diode snap, shoot-through current and general design considerations. A design is implemented in the dEVB151 development board. AN1520 - HDTMOS POWER MOSFETs Excel in Synchronous Rectifier Applications The new HDTMOS technology combines VLSI techniques with the ruggedness of vertical power structures to obtain increased cell density and to provide devices with lower overall on-resistance. The reverse recovery characteristic of the parasitic body diode is also faster than in MOSFETs that use conventional technologies. This note examines the advantages of using HDTMOS transistors as synchronous rectifiers in a high power buck converter, and in a 5V DC to 3.3V DC buck converter, in order to increase circuit performance and efficiency while minimizing parts count. AN1541/D - Introduction to insulated Gate Bipolar Transistors The ideal switch for use in power conversion applications would have zero voltage drop in the ON state, infinite resistance in the OFF state, would switch with infinite speed and not need any power to make it operate. IN practice, the designer must make a compromise and choose a device that suits the application with minimal loss of efficiency. Combining the low conduction losses of a BJT with the switching speed of a power MOSFET would create an optimal solid state switch. The insulated Gate Bipolar Transistor (IGBT) offers a combination of these attributes. This note explains how it is made, how it works, and how it compares with BJTs and power MOSFETs. http://onsemi.com 1401 AN1570 - Basic Semiconductor Thermal Measurement This application note provides basic information about power semiconductor thermal parameters, how they are measured, and how they are used. The intention is to enable the reader to better describe power semiconductors and to answer many common questions relating to their power handling capability. Four key topics are covered: Understanding basic semiconductor thermal parameters; Semiconductor thermal test equipment; Thermal parameter test procedures; Using thermal parameters to solve frequently asked thermal questions. AN211A - Field Effect Transistors in Theory and Practice There are two types of field-effect transistor: the Junction Field-Effect Transistor (JFET) and the Metal Oxide Semiconductor Field-Effect Transistor (MOSFET). The principles on which these devices operate are very similar, the main difference being in the method by which the control element is made. This difference, however, results in a considerable difference in device characteristics and necessitates different approaches in circuit design. AN220 - FETs in Chopper and Analog Switching Circuits The author's discussion begins with elementary chopper and analog switch characteristics, explores fully the considerations required for conventional and FET chopper and anlog switch design, and finishes with specific FET circuit examples. AN861 - Power Transistor Safe Operating Area: Special Considerations for Motor Drives Motor drives present a unique set of safe operating area conditions for power output transistors. Starting with the basics of forward and reverse safe operating area, considerations unique to motor drives are discussed. The industrial motor drive application is sufficiently different from the electronics uses of power transistors that a new safe operating area specification has been developed. It is called overload safe operating area (OSLOA). The concept and that data sheet curves that go with it are presented. AN873 - Understanding Power Transistor Dynamic Behavior: dv/dt Effects on Switching RBSOA Power transistor dynamic behavior can be affected to a large extent by dv/dt limitations. A look at the internal workings of the transistor readily shows how these limitations arise. A simple circuit model is developed which reproduces the behavior of power transistors in dv/dt-limited modes of operation. Experience with the model gives some guidelines for minimizing dv/dt limitations in practical circuits. AN875 - Power Transistor Safe Operating Area: Special Considerations for Switching Power Supplies The purpose of this application note is to take a look at some of the more subtle aspects of how stress imposed by the power supply relates to transistor safe operating area, and to differentiate those stresses that the transistor can handle from those it cannot. In order to provide a proper foundation, special considerations are preceded by a review of forward bias safe operating area. AN876 - Using Power MOSFETs in Stepping Motor Control Stepping Motor control techniques and circuits utilizing Power MOSFETs driven from CMOS Integrated Circuits are discussed. The techniques described are shift register phase generation, comparator switched current limiting, utilization of synchronous rectification, transient current suppression by use of the Power FET transfer characteristic, and the transient voltage protection requirements of the Power FET. The techniques are presented as components for an 88% efficient stepping motor drive circuit; however they are also applicable to other power control tasks. AN913 - Designing with TMOS Power MOSFETs Clearly, the advantages and disadvantages that the power MOSFET gives technology are its specific realm of usefulness. Some designers also favor the power MMOSFET because of its extended FBSOA or its other more subtle advantages. The most common considerations that designers should be aware of when designing with TMOS power MOSFETs are outlined and explained here. AN918 - Paralleling Power MOSFETs in Switching Applications The present TDT series of application notes are updated in this note with a more detailed analysis and design guide for TMOS power MOSFET parallel applications to account for device-to-device parameter http://onsemi.com 1402 AN929 - Insuring Reliable Performance from Power MOSFETs Due to their many unique advantages, power MOSFETs are being used in an increasing number of applications. To aid the circuit designer in developing reliable power MOSFET circuits, this application note examines six potential problem areas and offers suggestions for eliminating or minimizing problems in each area. In addition, as an aid to the many designers who are using power MOSFETs in switched-mode power supplies, this note includes a section on improving switching power supply circuits. EB125 - Testing Power MOSFET Gate Charge Most power MOSFET manufacturers now specify Gate Charge, as well as Input Capacitance, as an indication of the drive current required to turn on the device. The data can be useful in predicting switching speeds and drive losses. Commercially available gate charge test equipment is not yet widely used, and this simple tester for both N and P-channel devices is a practical alternative for smaller users. EB131 - Curve Tracer Measurement Techniques for Power MOSFETs Most curve tracers are designed to measure the parameters of bipolar transistors, but because of similarities in their characteristics, the same techniques can also be used to measure the parameters of power MOSFETs. This bulletin explains how, with particular reference to the Tektronix 370A Curve Tracer. EB201 - High Cell Density MOSFETs HDTMOS technology brings high cell density with additional advantages such as greatly improved body diode performance. The technological advances are sufficiently great that they are fundamentally changing low voltage power transistor technology. This bulletin discusses high cell density technology and its benefits for the end user. http://onsemi.com 1403 http://onsemi.com 1404 CHAPTER 3 MOSFET Case Outlines and Package Dimensions http://onsemi.com 1405 http://onsemi.com 1406 CASE OUTLINE AND PACKAGE DIMENSIONS CHIPFET CASE 1206A-01 ISSUE A A 8 7 I -6$ 78# # I 4 = > 4 6 . =- .. < > 8 $ = > . = 9 . / = . M 6 K 5 S 5 6 7 8 4 3 2 1 B 1 2 3 4 L D J G C ! $# #7$ 4 $$ : #$ 4$ 9$= $ 4 6$ $$= $ 8 9 ## 9 9: 47 64 6 #$= 6 8 # 8 ##= $ : SO-8 CASE 751-07 ISSUE W -X- I -6$ 78# # I 4 = 6 > $ 9 $ = /= = = #: $ > . > A % $ #$ S B - # K -Y- G C N X 45 _ " -Z- 6 H D #$ < - > M http://onsemi.com 1407 J ! 68 $ 48 6 4$ :$ 44 $ #:= #$ 7 #$ 6 #: _ 8_ #$ $ $8 9# 87 7: $ $: $4 97 4 # $= 6 : 9 $ _ 8_ # ##8 #66 CASE OUTLINE AND PACKAGE DIMENSIONS Micro8 CASE 846A-02 ISSUE E I -6$ 78# # I 4 . = . = > $ 9 6 = . . > #$ -A- -B- K PIN 1 ID G D 8 PL 84 -T- = " 48$ ! C 6 ## 6 ## 64 9 #9= # 9 $ 7 8: 77 9 #8 L J H #7 4 #7 4 #$ 6 9$= $ $ 4 #4 6:$ $$ 6 : SOT-223 (TO-261) CASE 318E-04 ISSUE K A F I TU -6$ 78# TU# I # S & ' B D L G J C 84 H M K http://onsemi.com 1408 #67 #94 4 6$ 9 98 #6 4$ ( $ #9 8: 76 8 6 7 6 ! 9 :8 44 6 _ _ #96 #8: 94 9: 44 4: $ :$ 9 87 #7 4# ## #6 # #6 4$ $ # 8$ $ _ _ 9: :4 CASE OUTLINE AND PACKAGE DIMENSIONS TSOP-6 CASE 318G-02 ISSUE G A I -6$ 78# # I 4 > . . = L ) S $ # & ' B D G M J C $# ! K H #7 4 4 : 7 #$ $ 8$ $ 4 #9 # 9 #$ $$ _ _ #$ 4 6# ## $# 997 4$6 644 78 7: 44$ 64 $ 6 6 # :7 #49 674 9 _ _ 78$ 8 TSSOP-8 CASE 948S-01 ISSUE O 8x #8 K REF 6 2X L/2 8 B -U- 1 J J1 4 PIN 1 IDENT 5 L #8 CCC EEEE EEEE CCC EEEE CCC K1 K A -V- SECTION N-N -W- C :94 -T- " I TU -6$ 78# TU# I TU4 . = . = > $ 9 TU6 = . . > #$ TU$ = / . . - TU9 = = / D DETAIL E G P #$ N M N P1 F DETAIL E http://onsemi.com 1409 ( ! ! " " #7 4 64 6$ $ $ $ : 9$= 7 # 7 9 7 4 7 #$ 96= 8 _ _ ## 4# 6 ## 97 :: 64 # 9 # #8 #9= 6 8 6 9 : # : #$#= 8 _ _ 8: #9 CASE OUTLINE AND PACKAGE DIMENSIONS SOT-23 (TO-236) CASE 318-08 ISSUE AF I TU -6$ 78# TU# I TU4 > . . = A L ' B S & V G C H D ! * J K # 7: 6:# $$ 4$ 66 $ # : 8: $ 6 46 : 6 #8$ 4$ 6 84 47 :: #49 #8 46 # 6 87 4: $ :8 #6 4 8$ :: 4$ 97 87 # # #96 6$ 9 SC-70/SOT-323 CASE 419-04 ISSUE L A L I -6$ 78# # I ' B S & D G C $# J N K H http://onsemi.com 1410 ! : 8: 6$ $4 4# 6 # 9 6: $$ 6 6 : . #9= #8 . :7 7$ 8 ## $ 4$ 8 4 6 # 6 #$ 6#$ . 9$= : . # #6 CASE OUTLINE AND PACKAGE DIMENSIONS SC-88 (SOT-363) CASE 419B-01 ISSUE G I -6$ 78# # I A G V ) $ # & ' -B- S #8 D 6 PL = ! * : 8: 6$ $4 4 64 6 # #9= 6 6 6 # 8 . :7 8: # 9 8 ## $ 4$ 8 4 9$= #$ 4 # . # ## 4 6 N J C K H DPAK CASE 369A-13 ISSUE AA C B V I -6$ 78# # I " -T- E R # Z A S & ' U K F ! + * , J L H D G 2 PL 4$ ( http://onsemi.com 1411 #4$ #$ #$ #9$ 89 76 #: 4$ 44 6 4: 6: 8= 46 6 8 #4 # 6 7= :$ #$ # $ # 4 $ 48 $7: 94$ 94$ 9:4 #7 #48 97 88 86 76 7 6$8= 8: 69 $8 #9 #87 ##7= 66$ $69 $ #: $ :: #: 4$ CASE OUTLINE AND PACKAGE DIMENSIONS D2PAK CASE 418B-03 ISSUE D C E V -B- # I -6$ 78# # I A & S ' -T- K " J G D 3 PL 4$ ! * H = 46 48 48 6$ 9 7 # 4$ 6$ $$ = 8 8 #$ 7 $:$ 9#$ 6$ $$ 896 79$ 79$ #7 69 684 $ 87 6 6 #$6= #4 #:7 69 96 ##7 #:7 69 $88 6 6 TO-220 THREE-LEAD TO-220AB CASE 221A-09 ISSUE AA -T- B " C F T S # ( A Q & ' U H K Z L ! + * , R V I -6$ 78# # I 4 < . < / =- / J G D N http://onsemi.com 1412 $: 9# 48 6$ 9 7 #$ 4$ 6# 6: 7$ $ $$ 8 #$ $ $9# 6$ 9 7 # # 8 6$ $$ #4$ #$$ $ 6$ 8 668 $:$ 799 #8 6: 68# 96 88 49 4:4 #6# #99 #8 474 69 96 #: 6#: $ $# 684 $44 #$6 46 #6 #:7 $ 47 $7: 96: #: $ #6 CASE OUTLINE AND PACKAGE DIMENSIONS TO-247 CASE 340K-01 ISSUE C #$ -T- -Q- = E -B- C L U A ( R K # & ' -Y- P V H F - @ J G D #$ I -6$ 78# # I ! " + * 7: #4 $4 $7 6: $4 6 #: . # #6 $$= ## #9 6 8 6# 68 $$ 4: 64 4$$ 49$ $ $$= 4 46 ::9 :77 9# 9#9 8$ #7 47 $$ $ . :7 76 #9= 8: # 9 4 $$7 $84 #: 69 97 6 66 7: #:= 8 46 TO-264 CASE 340G-02 ISSUE H #$ = -Q- -B- -T- C E U N ( A R & L ' -Y- P K W F 2 PL G J H D 3 PL #$ - @ I -6$ 78# # I http://onsemi.com 1413 ! " + . #8 #7 74 #4 6: $4 74 68 7 # ## #6 $6$= #9 4 64 :8 :9 88 6 47$ 6:$ ## #9 4 4$ #$ #4$ 9 9$ #8 4# # 6# :9 8 8$ #7 4: $8 :$ 84 8: # #$= # 8 : 4 974 :6 644 667 $9 8: 8: # ## 4: 8$ 74 #6 #$9 #$ CASE OUTLINE AND PACKAGE DIMENSIONS DPAK CASE 936D-03 ISSUE B -T- OPTIONAL CHAMFER A TERMINAL 6 E U S K B V H & ' # $ M L J D #$6 P N G R I TU -6$ 78# TU# I TU4 = / TU6 = . . 9 TU$ = . . > #$ 94$ > ! " + * C 489 64 4$9 498 : 8 #9 49 6$ $$ 9:= $47 $:7 #$> $ . 88 # 8 #9 $8 :8 _ $ . 9 . # #$ 786 #49 76# 746: 648 6$:# 99 76 64 47: :#= 497 6:: 4:$> #: . #$6 ##4$ #$7 6$: 99 6:4 78 _ $ . #769 . $8 94$ TO-92 CASE 29-11 ISSUE AL A I -6$ 78# # I 4 . =- 6 =- B R P L " K D X X G J H V C SECTION X-X N N http://onsemi.com 1414 ! " * :$ #$ : # #$ 9$ 9 # 6$ $$ 7$ $ $ # $ #$ 8 $ $ 4$ 66$ $# 64# $44 48 67 6: $44 $ 47 #6# #99 47 $ #: 94$ #6 #99 #$6 #74 464 CHAPTER 4 Index http://onsemi.com 1415 http://onsemi.com 1416 Index Device Number Page Device Number Page Device Number Page 2N7000 264 MMDF2N02E 451 MPF990 761 2N7002LT1 267 MMDF2N05ZR2 459 MTB1306 765 BS107 271 MMDF2P01HD 468 MTB20N20E 772 BS107A 271 MMDF2P02E 477 MTB23P06V 781 BS108 275 MMDF2P02HD 485 MTB29N15E 790 BS170 277 MMDF2P03HD 494 MTB30N06VL 798 BSS123LT1 280 MMDF3N02HD 503 MTB30P06V 807 BSS138LT1 284 MMDF3N03HD 512 MTB36N06V 816 BSS84LT1 289 MMDF3N04HD 521 MTB40N10E 825 MGB15N35CL 293 MMDF3N06HD 531 MTB50N06V 834 MGB15N40CL 301 MMDF3N06VL 540 MTB50N06VL 843 MGB19N35CL 309 MMDF4N01HD 542 MTB50P03HDL 852 MGP15N35CL 293 MMDF5N02Z 551 MTB52N06V 862 MGP15N40CL 301 MMDF6N03HD 560 MTB52N06VL 871 MGP19N35CL 309 MMDF7N02Z 569 MTB55N06Z 880 MGSF1N02ELT1 316 MMDFS2P102 579 MTB60N05HDL 885 MGSF1N02LT1 320 MMDFS6N303 589 MTB60N06HD 895 MGSF1N03LT1 324 MMFT107T1 599 MTB75N03HDL 905 MGSF1P02ELT1 328 MMFT2406T1 605 MTB75N05HD 915 MGSF1P02LT1 332 MMFT2955E 610 MTB75N06HD 922 MGSF2P02HD 336 MMFT2N02EL 619 MTD1302 932 MGSF3442VT1 344 MMFT3055V 628 MTD15N06V 942 MGSF3454VT1 349 MMFT3055VL 637 MTD15N06VL 951 MLD1N06CL 354 MMFT5P03HD 646 MTD20N03HDL 960 MLP1N06CL 360 MMFT960T1 656 MTD20N06HD 970 MLP2N06CL 366 MMSF10N02Z 662 MTD20N06HDL 980 MMBF0201NLT1 372 MMSF10N03Z 671 MTD20P03HDL 990 MMBF0202PLT1 377 MMSF1308 681 MTD20P06HDL 1000 MMBF1374T1 382 MMSF1310 689 MTD2955V 1010 MMBF170LT1 384 MMSF2P02E 697 MTD3055V 1019 MMBF2201NT1 388 MMSF3300 705 MTD3055VL 1028 MMBF2202PT1 392 MMSF3P02HD 715 MTD3302 1037 MMDF1300 396 MMSF5N02HD 724 MTD4N20E 1048 MMDF1N05E 399 MMSF5N03HD 733 MTD5P06V 1057 MMDF2C01HD 404 MMSF7N03HD 742 MTD6N20E 1066 MMDF2C02E 416 MMSF7N03Z 751 MTD6P10E 1075 MMDF2C02HD 427 MPF930 761 MTD9N10E 1084 MMDF2C03HD 439 MPF960 761 MTDF1N02HD 1093 http://onsemi.com 1417 Index (continued) Device Number Page Device Number Page Device Number MTDF1N03HD 1104 MTP75N06HD 1313 NTHS5402T1 100 MTDF2N06HD 1115 MTP7N20E 1320 NTHS5404T1 106 MTP10N10E 1123 MTSF1P02HD 1326 NTHS5441T1 109 MTP10N10EL 1130 MTSF3N02HD 1337 NTHS5443T1 112 MTP12P10 1136 MTSF3N03HD 1348 NTHS5445T1 114 MTP1302 1141 MTW32N20E 1359 NTMD3P03R2 120 MTP1306 1148 MTW32N25E 1365 NTMD6N02R2 127 MTP15N06V 1155 MTW35N15E 1371 NTMD6P02R2 134 MTP15N06VL 1161 MTW45N10E 1377 NTMD7C02 141 MTP20N06V 1167 MTY55N20E 1383 NTMS10P02R2 143 MTP20N15E 1173 NGD15N41CL 21 NTMS3P03R2 150 MTP20N20E 1175 NIB6404-5L 23 NTMS4N01R2 157 MTP23P06V 1181 NIMD6302R2 27 NTMS4P01R2 164 MTP27N10E 1187 NTB45N06 210 NTMS5P02R2 171 MTP2955V 1193 NTB45N06L 215 NTMSD2P102LR2 178 MTP29N15E 1199 NTB75N03-06 220 NTMSD3P102R2 188 MTP2P50E 1207 NTB75N03L09 225 NTMSD3P303R2 198 MTP3055V 1213 NTD20N03L27 29 NTP27N06 208 MTP3055VL 1219 NTD20N06 33 NTP45N06 210 MTP30N06VL 1225 NTD3055-094 35 NTP45N06L 215 MTP30P06V 1231 NTD3055L104 37 NTP75N03-06 220 MTP36N06V 1237 NTD32N06 39 NTP75N03L09 225 MTP40N10E 1243 NTD32N06L 44 NTQD6866 230 MTP50N06V 1249 NTD4302 49 NTQS6463 232 MTP50N06VL 1255 NTGS3433T1 57 NTTD1P02R2 234 MTP50P03HDL 1261 NTGS3441T1 61 NTTD2P02R2 241 MTP52N06V 1268 NTGS3443T1 67 NTTS2P02R2 248 MTP52N06VL 1274 NTGS3446T1 73 NTTS2P03R2 255 MTP5P06V 1280 NTGS3455T1 76 NTUD01N02 262 MTP60N06HD 1286 NTHD5902T1 80 VN0300L 1389 MTP6P20E 1293 NTHD5903T1 85 VN2222LL 1391 MTP75N03HDL 1299 NTHD5904T1 90 VN2406L 1394 MTP75N05HD 1306 NTHD5905T1 95 VN2410L 1396 http://onsemi.com 1418 Page ON SEMICONDUCTOR MAJOR WORLDWIDE SALES OFFICES UNITED STATES ALABAMA Huntsville . . . . . . . . . . . 256-774-1000 CALIFORNIA Irvine . . . . . . . . . . . . . . . 949-623-8485 San Jose . . . . . . . . . . . 408-350-4800 Encino . . . . . . . . . . . . . . 818-654-9040 CANADA INTERNATIONAL (continued) ITALY ONTARIO Ottawa . . . . . . . . . . . . . 613-226-3491 QUEBEC St. Laurent . . . . . . . . . . 514-333-2125 MALAYSIA Littleton . . . . . . . . . . . . . 303-256-5884 Tampa . . . . . . . . . . . . . . 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