2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Features Parallel NOR Flash Automotive Memory MT28FW02GBBA1HPC-0AAT, MT28FW02GBBA1LPC-0AAT Features * BLANK CHECK operation to verify an erased block * CYCLIC REDUNDANCY CHECK (CRC) operation to verify a program pattern * VPP/WP# protection - Protects first or last block regardless of block protection settings * Software protection - Volatile protection - Nonvolatile protection - Password protection * Extended memory block - 512-word block for permanent, secure identification - Programmed or locked at the factory or by the customer * JESD47-compliant - 100,000 (minimum) ERASE cycles per block - Data retention: 20 years (TYP) * Package - 64-ball LBGA, 11mm x 13mm (PC) * RoHS-compliant, halogen-free packaging * Automotive operating temperature - Ambient: -40C to 105C * 2Gb stacked device (Two 1Gb die) * Single-level cell (SLC) process technology * Supply voltage - VCC = 2.7-3.6V (program, erase, read) - VCCQ = 1.65-VCC (I/O buffers) * Asynchronous random/page read - Page size: 16 words - Page access: 20ns (VCC = V CCQ = 2.7-3.6V) - Random access: 105ns (VCC = V CCQ = 2.7-3.6V) - Random access: 110ns (VCCQ = 1.65-VCC) * Buffer program (512-word program buffer) - 2.0 MB/s (TYP) when using full buffer program - 2.5 MB/s (TYP) when using accelerated buffer program (VHH) * Word program: 25s per word (TYP) * Block erase (128KB): 0.2s (TYP) * Memory organization - Uniform blocks: 128KB or 64KW each - x16 data bus * Program/erase suspend and resume capability - Read from another block during a PROGRAM SUSPEND operation - Read or program another block during an ERASE SUSPEND operation * Unlock bypass, block erase, die erase, and write to buffer capability CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Features Part Numbering Information For available options, such as packages or high/low protection, or for further information, contact your Micron sales representative. Part numbers can be verified at www.micron.com. Feature and specification comparison by device type is available at www.micron.com/products. Contact the factory for devices not found. Figure 1: Part Number Chart MT 28F W 02G B B A 1 H PC - 0 A AT Micron Technology Production Status Device type Blank = Production ES = Engineering sample 28F = Embedded Parallel NOR Flash memory (3V core, page, uniform block) Operating Temperature AT = -40C to +105C (Grade 2 AEC-Q100) Voltage Special Options W = 2.7-3.6V core; 1.7-3.6V I/O A = Automotive quality Density Security Features 02G = 2Gb 0 = No extra security Stack B = Dual die Package Device generation PC = 64-ball LBGA, 11mm x 13mm, lead-free, halogen-free, RoHS-compliant B = Second generation Block structure Die revision H = High lock L = Low lock A = Rev. A Configuration 1 = x16 CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Features Contents Important Notes and Warnings ......................................................................................................................... 7 General Description ......................................................................................................................................... 8 Automatic Power Savings Feature .................................................................................................................. 8 Signal Assignments ......................................................................................................................................... 10 Signal Descriptions ......................................................................................................................................... 11 Memory Organization .................................................................................................................................... 13 Memory Configuration ............................................................................................................................... 13 Memory Map ............................................................................................................................................. 13 Bus Operations ............................................................................................................................................... 14 Read .......................................................................................................................................................... 14 Write .......................................................................................................................................................... 14 Standby ..................................................................................................................................................... 14 Output Disable ........................................................................................................................................... 15 Reset .......................................................................................................................................................... 15 Registers ........................................................................................................................................................ 16 Data Polling Register .................................................................................................................................. 16 Read Status Register ................................................................................................................................... 21 Clear Status Register ................................................................................................................................... 22 Lock Register .............................................................................................................................................. 23 Standard Command Definitions - Address-Data Cycles .................................................................................... 25 READ and AUTO SELECT Operations .............................................................................................................. 27 READ/RESET Command ............................................................................................................................ 27 READ CFI Command .................................................................................................................................. 27 AUTO SELECT Command ........................................................................................................................... 27 Read Electronic Signature ........................................................................................................................... 28 Cyclic Redundancy Check Operation ............................................................................................................... 29 CYCLIC REDUNDANCY CHECK Command ................................................................................................. 29 Cyclic Redundancy Check Operation Command Sequence .......................................................................... 29 Bypass Operations .......................................................................................................................................... 32 UNLOCK BYPASS Command ...................................................................................................................... 32 UNLOCK BYPASS RESET Command ............................................................................................................ 32 Program Operations ....................................................................................................................................... 33 PROGRAM Command ................................................................................................................................ 33 UNLOCK BYPASS PROGRAM Command ..................................................................................................... 33 WRITE TO BUFFER PROGRAM Command .................................................................................................. 33 UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command ....................................................................... 36 WRITE TO BUFFER PROGRAM CONFIRM Command .................................................................................. 36 BUFFERED PROGRAM ABORT AND RESET Command ................................................................................ 36 PROGRAM SUSPEND Command ................................................................................................................ 36 PROGRAM RESUME Command .................................................................................................................. 37 ACCELERATED BUFFERED PROGRAM Operations ...................................................................................... 37 Erase Operations ............................................................................................................................................ 38 DIE ERASE Command ................................................................................................................................ 38 UNLOCK BYPASS DIE ERASE Command ..................................................................................................... 38 BLOCK ERASE Command ........................................................................................................................... 38 UNLOCK BYPASS BLOCK ERASE Command ................................................................................................ 39 ERASE SUSPEND Command ....................................................................................................................... 39 ERASE RESUME Command ........................................................................................................................ 40 ACCELERATED DIE ERASE Operations ............................................................................................................ 40 BLANK CHECK Operation .............................................................................................................................. 40 CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Features Device Protection ........................................................................................................................................... Hardware Protection .................................................................................................................................. Software Protection .................................................................................................................................... Volatile Protection Mode ............................................................................................................................. Nonvolatile Protection Mode ...................................................................................................................... Password Protection Mode .......................................................................................................................... Block Protection Command Definitions - Address-Data Cycles ........................................................................ Protection Operations .................................................................................................................................... LOCK REGISTER Commands ...................................................................................................................... PASSWORD PROTECTION Commands ....................................................................................................... NONVOLATILE PROTECTION Commands .................................................................................................. NONVOLATILE PROTECTION BIT LOCK BIT Commands ............................................................................ VOLATILE PROTECTION Commands .......................................................................................................... EXTENDED MEMORY BLOCK Commands .................................................................................................. EXIT PROTECTION Command .................................................................................................................... Common Flash Interface ................................................................................................................................ Power-Up and Reset Characteristics ................................................................................................................ Absolute Ratings and Operating Conditions ..................................................................................................... DC Characteristics .......................................................................................................................................... Read AC Characteristics .................................................................................................................................. Write AC Characteristics ................................................................................................................................. Data Polling/Toggle AC Characteristics ............................................................................................................ Program/Erase Characteristics ........................................................................................................................ Package Dimensions ....................................................................................................................................... Revision History ............................................................................................................................................. Rev. F -10/18 .............................................................................................................................................. Rev. E - 5/18 ............................................................................................................................................... Rev. D - 9/17 .............................................................................................................................................. Rev. C - 11/16 ............................................................................................................................................. Rev. B - 10/16 ............................................................................................................................................. Rev. A - 05/16 ............................................................................................................................................. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 4 42 42 42 43 43 44 46 49 49 49 49 50 51 51 52 53 58 60 62 64 66 71 73 74 75 75 75 75 75 75 75 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Features List of Figures Figure 1: Part Number Chart ............................................................................................................................ 2 Figure 2: Logic Diagram ................................................................................................................................... 9 Figure 3: Dual Die Configuration - 2Gb ............................................................................................................ 9 Figure 4: 64-Ball Fortified BGA ....................................................................................................................... 10 Figure 5: Data Polling Flowchart .................................................................................................................... 18 Figure 6: Toggle Bit Flowchart ........................................................................................................................ 19 Figure 7: Data Polling/Toggle Bit Flowchart .................................................................................................... 20 Figure 8: Lock Register Program Flowchart ..................................................................................................... 24 Figure 9: Boundary Condition of Program Buffer Size ..................................................................................... 34 Figure 10: WRITE TO BUFFER PROGRAM Flowchart ...................................................................................... 35 Figure 11: Software Protection Scheme .......................................................................................................... 44 Figure 12: Set/Clear Nonvolatile Protection Bit Algorithm Flowchart ............................................................... 50 Figure 13: Power-Up Timing .......................................................................................................................... 58 Figure 14: Reset AC Timing - No PROGRAM/ERASE Operation in Progress ...................................................... 59 Figure 15: Reset AC Timing During PROGRAM/ERASE Operation .................................................................... 59 Figure 16: AC Measurement Load Circuit ....................................................................................................... 61 Figure 17: AC Measurement I/O Waveform ..................................................................................................... 61 Figure 18: Random Read AC Timing ............................................................................................................... 65 Figure 19: Page Read AC Timing ..................................................................................................................... 65 Figure 20: WE#-Controlled Program AC Timing .............................................................................................. 67 Figure 21: CE#-Controlled Program AC Timing ............................................................................................... 69 Figure 22: Chip/Block Erase AC Timing .......................................................................................................... 70 Figure 23: Accelerated Program AC Timing ..................................................................................................... 70 Figure 24: Data Polling AC Timing .................................................................................................................. 71 Figure 25: Toggle/Alternative Toggle Bit Polling AC Timing .............................................................................. 72 Figure 26: 64-Ball LBGA - 11mm x 13mm (Package Code: PC) ......................................................................... 74 CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Features List of Tables Table 1: Signal Descriptions ........................................................................................................................... Table 2: Blocks[2047:0] .................................................................................................................................. Table 3: Bus Operations ................................................................................................................................. Table 4: Data Polling Register Bit Definitions .................................................................................................. Table 5: Operations and Corresponding Bit Settings ........................................................................................ Table 6: Status Register Definitions ................................................................................................................ Table 7: Lock Register Bit Definitions ............................................................................................................. Table 8: Standard Command Definitions - Address-Data Cycles ...................................................................... Table 9: Block Protection ............................................................................................................................... Table 10: Read Electronic Signature - 2Gb ...................................................................................................... Table 11: Command Sequence - Range of Blocks ............................................................................................ Table 12: Command Sequence - Entire Chip .................................................................................................. Table 13: ACCELERATED PROGRAM Requirements and Recommendations .................................................... Table 14: ACCELERATED DIE ERASE Requirements and Recommendations .................................................... Table 15: V PP/WP# Functions ......................................................................................................................... Table 16: Block Protection Status ................................................................................................................... Table 17: Block Protection Command Definitions - Address-Data Cycles ......................................................... Table 18: Extended Memory Block Address and Data ...................................................................................... Table 19: Query Structure Overview ............................................................................................................... Table 20: CFI Query Identification String ........................................................................................................ Table 21: CFI Query System Interface Information .......................................................................................... Table 22: Device Geometry Definition ............................................................................................................ Table 23: Primary Algorithm-Specific Extended Query Table ........................................................................... Table 24: Power-Up Specifications ................................................................................................................. Table 25: Reset AC Specifications ................................................................................................................... Table 26: Absolute Maximum/Minimum Ratings ............................................................................................ Table 27: Operating Conditions ...................................................................................................................... Table 28: Input/Output Capacitance .............................................................................................................. Table 29: DC Current Characteristics .............................................................................................................. Table 30: DC Voltage Characteristics .............................................................................................................. Table 31: Read AC Characteristics - V CC = V CCQ = 2.7-3.6V ............................................................................... Table 32: Read AC Characteristics - V CCQ = 1.65V-VCC ..................................................................................... Table 33: WE#-Controlled Write AC Characteristics ......................................................................................... Table 34: CE#-Controlled Write AC Characteristics ......................................................................................... Table 35: Data Polling/Toggle AC Characteristics ............................................................................................ Table 36: Program/Erase Characteristics ........................................................................................................ CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 6 11 13 14 16 17 21 23 25 28 28 29 31 37 40 42 45 46 51 53 53 54 54 55 58 59 60 60 61 62 63 64 64 66 68 71 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Important Notes and Warnings Important Notes and Warnings Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR General Description General Description The device is an asynchronous, uniform block, parallel NOR Flash memory device. It is a 2Gb stacked device that contains two 1Gb dies. It is selected by the A[max]. While A[max] = 0, the lower 1Gb die is selected, and while A[max] = 1, the upper 1Gb die is selected. READ, ERASE, and PROGRAM operations are performed using a single lowvoltage supply. Upon power-up, the device defaults to read array mode. The main memory array is divided into uniform blocks that can be erased independently so that valid data can be preserved while old data is purged. PROGRAM and ERASE commands are written to the command interface of the memory. An on-chip program/ erase controller simplifies the process of programming or erasing the memory by taking care of all special operations required to update the memory contents. The end of a PROGRAM or ERASE operation can be detected and any error condition can be identified. The command set required to control the device is consistent with JEDEC standards. CE#, OE#, and WE# control the bus operation of the device and enable a simple connection to most microprocessors, often without additional logic. The device supports asynchronous random read and page read from all blocks of the array. It also features an internal program buffer that improves throughput by programming 512 words via one command sequence. A 512-word extended memory block overlaps addresses with array block 0. Users can program this additional space and then protect it to permanently secure the contents. The device also features different levels of hardware and software protection to secure blocks from unwanted modification. Automatic Power Savings Feature The automatic power savings feature provides low power operation during reads. After data is read from the memory array and the address lines are quiescent, the automatic power savings feature reduces device current to a low value of ICCAPS. During automatic power savings mode, average current is measured over 5ms time interval 5s after the following events happen: * No internal read, program or erase activity occurring * RST# is deasserted and CE# is asserted * All other signals are quiescent and at V SS or V CCQ CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR General Description Figure 2: Logic Diagram VCC VCCQ VPP/WP# 16 DQ[15:0] A[MAX:0] WE# CE# OE# RY/BY# RST# VSS Figure 3: Dual Die Configuration - 2Gb VPP / WP# CE# OE# CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN VCC WE# VCCQ RST# VSS A[26:0] Note: Upper die (1Gb) Lower die (1Gb) DQ[15:0] RY/BY# 1. A[26] = VIH selects the upper die; A[26] = VIL selects the lower die. 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Signal Assignments Signal Assignments Figure 4: 64-Ball Fortified BGA 6 7 8 A7 RY/BY# WE# A9 A13 NC A4 A17 VPP/WP# RST# A8 A12 A22 NC A2 A6 A18 A21 A10 A14 A23 NC A1 A5 A20 A19 A11 A15 VCCQ NC A0 DQ0 DQ2 DQ5 DQ7 A16 VSS RFU A24 1 2 NC A3 A26 3 4 5 A B C D E F VCCQ CE# DQ8 DQ10 DQ12 DQ14 G NC OE# DQ9 DQ11 VCC DQ13 DQ15 A25 NC VSS DQ1 DQ3 DQ4 DQ6 VSS H CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 10 NC Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Signal Descriptions Signal Descriptions The signal description table below is a comprehensive list of signals for this device family. All signals listed may not be supported on this device. See Signal Assignments for information specific to this device. Table 1: Signal Descriptions Name Type Description A[MAX:0] Input Address: Selects the cells in the array to access during READ operations. During WRITE operations, they control the commands sent to the command interface of the program/erase controller. A[max] is used as a virtual CE pin. When A[max] = 0, the lower 1Gb die is selected, When A[max] = 1, the upper 1Gb is selected. CE# Input Chip enable: Activates the device, enabling READ and WRITE operations to be performed. When CE# is HIGH, the device goes to standby and data outputs are High-Z. OE# Input Output enable: Active LOW input. OE# LOW enables the data output buffers during READ cycles. When OE# is HIGH, data outputs are High-Z. WE# Input Write enable: Controls WRITE operations to the device. Address is latched on the falling edge of WE# and data is latched on the rising edge. VPP/WP# Input VPP/Write Protect: Provides WRITE PROTECT function and VHH function. These functions protect the lowest or highest block and enable the device to enter unlock bypass mode, respectively. (Refer to Hardware Protection and Bypass Operations for details.) RST# Input Reset: Applies a hardware reset to the device control logic and places it in standby, which is achieved by holding RST# LOW for at least tPLPH. After RST# goes HIGH, the device is ready for READ and WRITE operations (after tPHEL or tPHWL, whichever occurs last). DQ[15:0] I/O Data I/O: Outputs the data stored at the selected address during a READ operation. During WRITE operations, they represent the commands sent to the command interface of the internal state machine. RY/BY# Output Ready busy: Open-drain output that can be used to identify when the device is performing a PROGRAM or ERASE operation. During PROGRAM or ERASE operations, RY/BY# is LOW, and is High-Z during read mode, auto select mode, and erase suspend mode. The use of an open-drain output enables the RY/BY# pins from several devices to be connected to a single pull-up resistor to VCCQ. A low value will then indicate that one (or more) of the devices is (are) busy. A 10K Ohm or bigger resistor is recommended as pull-up resistor to achieve 0.1V VOL. VCC Supply Supply voltage: Provides the power supply for READ, PROGRAM, and ERASE operations. The device is disabled when VCC VLKO. If the program/erase controller is programming or erasing during this time, then the operation aborts and the contents being altered will be invalid. A 0.1F and 0.01F capacitor should be connected between VCC and VSS to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during PROGRAM and ERASE operations (see DC Characteristics). VCCQ Supply I/O supply voltage: Provides the power supply to the I/O pins and enables all outputs to be powered independently from VCC. A 0.1F and 0.01F capacitor should be connected between VCCQ and VSS to decouple the current surges from the power supply. VSS Supply Ground: All VSS pins must be connected to the system ground. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Signal Descriptions Table 1: Signal Descriptions (Continued) Name Type RFU -- Reserved for future use: Reserved by Micron for future device functionality and enhancement. Recommend that these be left floating. May be connected internally, but external connections will not affect operation. DNU -- Do not use: Do not connect to any other signal, or power supply; must be left floating. NC -- No connect: No internal connection; can be driven or floated. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN Description 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Memory Organization Memory Organization Memory Configuration The main memory array is divided into 128KB or 64KW uniform blocks. Memory Map Table 2: Blocks[2047:0] Address Range Block Start End 2047 7FF 0000h 7FF FFFFh 1023 3FF 0000h 3FF FFFFh 511 1FF 0000h 1FF FFFFh 255 0FF 0000h 0FF FFFFh 127 07F 0000h 07F FFFFh 63 03F 0000h 03F FFFFh 0 000 0000h 000 FFFFh Note: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. Block 0-1023 is the lower die, block 1024-2047 is the upper die. 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Bus Operations Bus Operations Table 3: Bus Operations Notes 1 and 2 apply to entire table Operation CE# OE# WE# RST# VPP/WP# A[MAX:0] DQ[15:0] READ L L H H X Address Data output WRITE L H L H H3 Command address Data input4 STANDBY H X X H X X High-Z OUTPUT DISABLE L H H H X X High-Z RESET X X X L X X High-Z Notes: 1. Typical glitches of less than 3ns on CE#, OE#, and WE# are ignored by the device and do not affect bus operations. 2. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW. 3. If WP# is LOW, then the highest or the lowest block remains protected, depending on line item. 4. Data input is required when issuing a command sequence or when performing data polling or block protection. Read Bus READ operations read from the memory cells, registers, extended memory block, or CFI space. To accelerate the READ operation, the memory array can be read in page mode where data is internally read and stored in a page buffer. Page size is 16 words and is addressed by address inputs A[3:0]. The extended memory blocks and CFI area support page read mode. A valid bus READ operation involves setting the desired address on the address inputs, taking CE# and OE# LOW, and holding WE# HIGH. The data I/Os will output the value. If CE# goes HIGH and returns LOW for a subsequent access, a random read access is performed and tACC or tCE is required. (See AC Characteristics for details about when the output becomes valid.) Write Bus WRITE operations write to the command interface. A valid bus WRITE operation begins by setting the desired address on the address inputs. The address inputs are latched by the command interface on the falling edge of CE# or WE#, whichever occurs last. The data I/Os are latched by the command interface on the rising edge of CE# or WE#, whichever occurs first. OE# must remain HIGH during the entire bus WRITE operation (See AC Characteristics for timing requirement details). Standby Driving CE# HIGH in read mode causes the device to enter standby and data I/Os to be High-Z (See DC Characteristics). CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Bus Operations During PROGRAM or ERASE operations, the device will continue to use the program/ erase supply current (ICC3) until the operation completes. The device cannot be placed into standby mode during a PROGRAM/ERASE operation. Output Disable Data I/Os are High-Z when OE# is HIGH. Reset During reset mode the device is deselected and the outputs are High-Z. The device is in reset mode when RST# is LOW. The power consumption is reduced to the standby level, independently from CE#, OE#, or WE# inputs. When RST# is HIGH, a time of tPHEL is required before a READ operation can access the device, and a delay of tPHWL is required before a write sequence can be initiated. After this wake-up interval, normal operation is restored, the device defaults to read array mode, and the data polling register is reset. If RST# is driven LOW during a PROGRAM/ERASE operation or any other operation that requires writing to the device, the operation will abort within tPLRH, and memory contents at the aborted block or address are no longer valid. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Registers Registers The device features two methods for monitoring internal status during modify operations: data polling status and read status register. Users must not mix the two methods. Only one method at a time must be used to monitor internal operations. Data Polling Register The device has two 1Gb dies, the selected die automatically enters data polling status mode upon command issuance. The data polling status information uses the following to indicate information: DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7; DQ[15:8] are reserved and will output 00h. The deselected die is in standby mode. Table 4: Data Polling Register Bit Definitions Note 1 applies to entire table Bit Name Settings Description Notes DQ7 Data polling 0 or 1, depending on bit operations Monitors whether the program/erase controller has successfully completed its operation, or has responded to an ERASE SUSPEND operation. 2, 4 DQ6 Toggle bit Toggles: 0 to 1; 1 to 0; and so on Monitors whether the program, erase, or blank check controller has successfully completed its operations, or has responded to an ERASE SUSPEND operation. During a PROGRAM/ERASE/ BLANK CHECK operation, DQ6 toggles from 0 to 1, 1 to 0, and so on, with each successive READ operation from any address. 3, 4, 5 DQ5 Error bit 0 = Success 1 = Failure Identifies errors detected by the program/erase controller. DQ5 is set to 1 when a PROGRAM, BLOCK ERASE, or DIE ERASE operation fails to write the correct data to the memory, or when a BLANK CHECK or CRC operation fails. 4, 6 DQ3 Erase timer bit 0 = Erase not in progress 1 = Erase in progress Identifies the start of program/erase controller operation during a BLOCK ERASE command. Before the program/erase controller starts, this bit set to 0. 4 DQ2 Alternative toggle bit Toggles: 0 to 1; 1 to 0; and so on During DIE ERASE, BLOCK ERASE, and ERASE SUSPEND operations, DQ2 toggles from 0 to 1, 1 to 0, and so on, with each successive READ operation from addresses within the blocks being erased. 3, 4 DQ1 Buffered program abort bit 1 = Abort Indicates a BUFFER PROGRAM, BLANK CHECK, or CRC operation abort. The BUFFERED PROGRAM ABORT and RESET command must be issued to return the device to read mode (see WRITE TO BUFFER PROGRAM command). Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. The data polling register can be read during PROGRAM, ERASE, or ERASE SUSPEND operations; the READ operation outputs data on DQ[7:0]. 2. For a PROGRAM operation in progress, DQ7 outputs the complement of the bit being programmed. For a READ operation from the address previously programmed successfully, DQ7 outputs existing DQ7 data. For a READ operation from addresses with blocks to be erased while an ERASE SUSPEND operation is in progress, DQ7 outputs 0; upon successful completion of the ERASE SUSPEND operation, DQ7 outputs 1. For an ERASE operation in progress, DQ7 outputs 0; upon ERASE operation's successful completion, DQ7 outputs 1. During a BUFFER PROGRAM operation, the data polling bit is valid only for the last word being programmed in the write buffer. 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Registers 3. After successful completion of a PROGRAM, ERASE, or BLANK CHECK operation, the device returns to read mode. 4. During erase suspend mode, READ operations to addresses within blocks not being erased output memory array data as if in read mode. A protected block is treated the same as a block not being erased. See the Toggle Flowchart for more information. 5. During erase suspend mode, DQ6 toggles when addressing a cell within a block being erased. The toggling stops when the program/erase controller has suspended the ERASE operation. See the Toggle Flowchart for more information. 6. When DQ5 is set to 1, a READ/RESET (F0h) command must be issued before any subsequent command. Table 5: Operations and Corresponding Bit Settings Note 1 and 2 apply to entire table Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RY/BY# Notes PROGRAM Any address DQ7# Toggle 0 - - 0 0 3 CRC range of blocks Any address 1 Toggle 0 - - 0 0 CRC chip Any address DQ7# Toggle 0 - - 0 0 DIE ERASE Any address 0 Toggle 0 1 Toggle - 0 Blank-checking block 0 Toggle 0 1 Toggle - 0 Non-blank-checking block 0 Toggle 0 1 No toggle - 0 Erasing block 0 Toggle 0 1 Toggle - 0 Non-erasing block 0 Toggle 0 1 No toggle - 0 BLANK CHECK BLOCK ERASE PROGRAM SUSPEND Programming block Invalid operation High-Z Nonprogramming block Outputs memory array data as if in read mode High-Z Erasing block ERASE SUSPEND Non-erasing block PROGRAM during ERASE SUSPEND Erasing block DQ7# Toggle 0 - Toggle - 0 3 Non-erasing block DQ7# Toggle 0 - No Toggle - 0 3 BUFFERED PROGRAM ABORT Any address DQ7# Toggle 0 - - 1 High-Z PROGRAM Error Any address DQ7# Toggle 1 - - - High-Z ERASE Error Any address 0 Toggle 1 1 Toggle - High-Z BLANK CHECK Error Any address 0 Toggle 1 1 Toggle - High-Z CRC range of blocks error Any address 1 Toggle 1 - - - High-Z CRC chip error Any address DQ7# Toggle 1 - - - High-Z Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1 No Toggle 0 - Toggle - 4 Outputs memory array data as if in read mode High-Z High-Z 3 4 1. Unspecified data bits should be ignored. 2. The table is only for selected die. The non-select die will output the array content. 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Registers 3. DQ7# for buffer program is related to the last address location loaded. 4. DQ7# is the reverse DQ7 of the last word or byte loaded before CRC chip confirm command cycle. Figure 5: Data Polling Flowchart Start Read DQ7, DQ5, and DQ1 at valid address1 Yes DQ7 = Data No No DQ1 = 13 No DQ5 = 12 Yes Yes Read DQ7 at valid address DQ7 = Data Yes No Failure Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN Success 1. Valid address is the last address being programmed or an address within the block being erased. 2. Failure results: DQ5 = 1 indicates an operation error. A READ/RESET (F0h) command must be issued before any subsequent command. 3. Failure results: DQ1 = 1 indicates a WRITE TO BUFFER PROGRAM ABORT operation. A full three-cycle RESET (AAh/55h/F0h) command sequence must be used to reset the aborted device. 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Registers Figure 6: Toggle Bit Flowchart Start Read DQ6 at valid address Read DQ6, DQ5, and DQ1 at valid address DQ6 = Toggle Yes No DQ1 = 1 No No DQ5 = 1 Yes Yes Read DQ6 (twice) at valid address DQ6 = Toggle No Yes Failure1 Note: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN Success 1. Failure results: DQ5 = 1 indicates an operation error; DQ1 = 1 indicates a WRITE TO BUFFER PROGRAM ABORT operation. 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Registers Figure 7: Data Polling/Toggle Bit Flowchart Start Read 1 DQ7 = Valid data Yes Read 2 Read 3 PROGRAM operation Yes Read 3 correct data? Yes No No No DQ5 = 1 Yes PROGRAM operation failure Read 2 No DQ6 = Toggling Yes Read2.DQ6 = Read3.DQ6 Read 3 Device error No DQ6 = Toggling Yes Read1.DQ6 = Read2.DQ6 DQ2 = Toggling Timeout failure Read2.DQ2 = Read3.DQ2 No Yes No DQ1 = 1 Erase/suspend mode No ERASE operation complete Device busy: Repolling WRITE TO BUFFER PROGRAM Yes Yes PROGRAM operation complete WRITE TO BUFFER PROGRAM abort No Device busy: Repolling CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Registers Read Status Register The device has two status registers: Each die has one status register. The operation initiated in one die must be terminated before attempting to start a new operation in another die. During PROGRAM or ERASE operations in one die, the related status register should be monitored by asserting A[max]. The device's status register displays PROGRAM, ERASE, and BLANK CHECK operations status. A device's status can be read after writing the READ STATUS REGISTER command (70h). When the READ STATUS REGISTER command is issued, the current status is captured by the register and the device is in read status register mode. The first read access in the status register mode exits the mode and returns to the output state when the READ STATUS REGISTER command was issued. No other command should be sent before reading the status register to exit the status register mode. The status register bits are output on DQ[7:0], while DQ[15:8] outputs are 00h. Table 6: Status Register Definitions Bit Name Settings Description SR[15:8] - Reserved Reserved for future use. Will always be set to 0. SR7 Device program/ erase/blank check status 0 = Busy 1 = Ready Indicates erase, program, or blank check completion in the device. SR[6:1] are invalid; SR7 = 0. SR6 Erase suspend status 0 = Erase in progress/ Indicates whether the device is erase suspended. After issuing an complete ERASE SUSPEND command, SR7 and SR6 are set to 1. SR6 remains 1 = Erase suspended set until the device receives an ERASE RESUME command. SR5 Erase/blank check status SR4 Program status SR3 SR2 SR1 SR0 0 = Erase/blank check successful 1 = Erase/blank check error Set to 1 if an attempted erase or blank check failed. 0 = Program success 1 = Program error Indicates whether the program failed or the buffer program has aborted. Writer buffer abort 0 = Program not Indicates whether the buffer program has aborted. status aborted 1 = Program aborted during buffer program Program suspend status 0 = Program in pro- Indicates whether the device is program suspended. After receivgress/complete ing a PROGRAM SUSPEND command, SR7 and SR2 are set to 1, 1 = Program suspen- and remain set at 1 until a RESUME command is received. ded Device protect status 0 = Unlocked Indicates whether program or erase was attempted on a locked 1 = Aborted erase/ block. If an ERASE or PROGRAM operation is attempted on a program attempt on locked block, SR1 is set to 1 and the operation aborts. a locked block - CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN Reserved Reserved for future use. Will always be set to 0. 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Registers Clear Status Register The status register content can be cleared by CLEAR STATUS REGISTER command (71h). The CLEAR STATUS REGISTER command clears the status register bits SR[6:1]. SR7 remains at 0, which indicates the device is busy. However, for buffer program abort only, the CLEAR STATUS REGISTER command would change also SR7 to 1, which reverts the device to main array read mode. The status register can also be cleared by using RESET Command (F0h). CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Registers Lock Register The device has two lock registers: Each die has one lock register. Micron recommends programming both of the lock registers with the same contents in order to have the same protection scheme for both the upper and lower die. Table 7: Lock Register Bit Definitions Note 1 applies to entire table Bit Name Settings Description Notes DQ[15:9] - Default value = 1 DQ[15:9] are reserved and are set to a default value of 1. DQ8 - Default value = 0 DQ8 is reserved and is set to a default value of 0. DQ[7:3] - Default value =1 DQ[7:3] are reserved and are set to a default value of 1. DQ2 Password pro- 0 = Password protectection mode tion mode enabled lock bit 1 = Password protection mode disabled (default) Places the device permanently in password protection mode. 2 DQ1 Nonvolatile 0 = Nonvolatile proprotection tection mode enabled mode lock bit with password protection mode permanently disabled 1 = Nonvolatile protection mode enabled (default) Places the device in nonvolatile protection mode, with password protection mode permanently disabled. When shipped from the factory, the device will operate in nonvolatile protection mode, and the memory blocks are unprotected. 2 DQ0 Extended 0 = Protected memory 1 = Unprotected (deblock protec- fault) tion bit If the device is shipped with the extended memory block unlocked, the block can be protected by setting this bit to 0. The extended memory block protection status can be read in auto select mode by issuing an AUTO SELECT command. Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. The lock register is a 16-bit, one-time programmable register. DQ[15:3] are reserved. 2. The password protection mode lock bit and nonvolatile protection mode lock bit cannot both be programmed to 0. Any attempt to program one while the other is programmed causes the operation to abort, and the device returns to read mode. The device is shipped from the factory with the default setting. 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Registers Figure 8: Lock Register Program Flowchart Start Enter LOCK REGISTER command set Address/data (unlock) cycle 1 Address/data (unlock) cycle 2 Address/data cycle 3 PROGRAM LOCK REGISTER Address/data cycle 1 Address/data cycle 2 Polling algorithm No Done? Yes Read lock register No Match expected value, 0? Yes Success: EXIT PROTECTION command set Address/data cycle 1 Address/data cycle 2 Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. Each lock register bit can be programmed only once. 2. See the Block Protection Command Definitions table for address-data cycle details. 3. DQ5 and DQ1 are ignored in this algorithm flow. 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Standard Command Definitions - Address-Data Cycles Standard Command Definitions - Address-Data Cycles Table 8: Standard Command Definitions - Address-Data Cycles Note 1 applies to entire table Address and Data Cycles Command and Code/Subcode 1st A 2nd D 3rd 4th A D A D 2AA 55 X F0 2AA 55 555 90 555 20 555 A0 A 5th D A 6th D A D Notes READ and AUTO SELECT Operations READ/RESET (F0h) 555 AA READ CFI (98h) 555 98 EXIT READ CFI (F0h) X F0 AUTO SELECT (90h) 555 AA X F0 READ STATUS (70h) 555 70 CLEAR STATUS (71h) 555 71 555 AA 2AA 55 X 90 X 00 PROGRAM (A0h) 555 AA 2AA 55 UNLOCK BYPASS PROGRAM (A0h) X A0 PA PD WRITE TO BUFFER PROGRAM (25h) 555 AA 2AA 55 BAd 25 UNLOCK BYPASS WRITE TO BUFFER PROGRAM (25h) BAd 25 BAd N PA PD WRITE TO BUFFER PROGRAM CONFIRM (29h) BAd 29 BUFFERED PROGRAM ABORT and RESET (F0h) 555 AA PROGRAM SUSPEND (B0h) X B0 PROGRAM RESUME (30h) X 30 PROGRAM SUSPEND (51h) X 51 PROGRAM RESUME (50h) X 50 DIE ERASE (80/10h) 555 UNLOCK BYPASS DIE ERASE (80/10h) X EXIT AUTO SELECT (F0h) 2 Note 3 Note 3 4, 5 BYPASS Operations UNLOCK BYPASS (20h) UNLOCK BYPASS RESET (90h/00h) PROGRAM Operations PA PD 6 BAd N PA PD 7, 8, 9 6 7 2AA 55 555 F0 AA 2AA 55 555 80 80 X 10 ERASE Operations CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 555 AA 2AA 55 555 10 6 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Standard Command Definitions - Address-Data Cycles Table 8: Standard Command Definitions - Address-Data Cycles (Continued) Note 1 applies to entire table Address and Data Cycles 1st Command and Code/Subcode 2nd 3rd 4th 5th 6th A D A D A D A D A D A D BLOCK ERASE (80/30h) 555 AA 2AA 55 555 80 555 AA 2AA 55 BAd 30 UNLOCK BYPASS BLOCK ERASE (80/30h) X 80 BAd 30 ERASE SUSPEND (B0h) X B0 ERASE RESUME (30h) X 30 555 33 Notes 6 BLANK CHECK Operations BLANK CHECK Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. A = Address; D = Data; X = "Don't Care"; BAd = Any address in the block; N = Number of words to be programmed; PA = Program address; PD = Program data; Gray shading = Not applicable. All values in the table are hexadecimal. Some commands require both a command code and subcode. All the commands are effective for the selected die only. 2. A full three-cycle RESET command sequence must be used to reset the device in the event of a buffered program abort error (DQ1 = 1). 3. These cells represent READ cycles (versus WRITE cycles for the others). 4. AUTO SELECT enables the device to read the manufacturer code, device code, block protection status, and extended memory block protection indicator. 5. AUTO SELECT addresses and data are specified in the Electronic Signature table and the Extended Memory Block Protection table. 6. For any UNLOCK BYPASS ERASE/PROGRAM command, the first two UNLOCK cycles are unnecessary. 7. BAd must be the same as the address loaded during the WRITE TO BUFFER PROGRAM 3rd and 4th cycles. 8. WRITE TO BUFFER PROGRAM operation: maximum cycles = 517. UNLOCK BYPASS WRITE TO BUFFER PROGRAM operation: maximum cycles = 515. WRITE TO BUFFER PROGRAM operation: N + 1 = words to be programmed; maximum buffer size = 512 words. 9. A[MAX:9] address pins should remain unchanged while A[8:0] pins are used to select a word within the N+1 word page. 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR READ and AUTO SELECT Operations READ and AUTO SELECT Operations READ/RESET Command The READ/RESET (F0h) command returns the device to read mode and resets the errors in the data polling register. One or three bus WRITE operations can be used to issue the READ/RESET command. Note: A full three-cycle RESET command sequence must be used to reset the device in the event of a buffered program abort error (DQ1 = 1). Once a PROGRAM, ERASE, or SUSPEND operation begins, RESET commands are ignored until the operation is complete. Read/reset serves primarily to return the device to read mode from a failed PROGRAM or ERASE operation. Read/reset may cause a return to read mode from undefined states that might result from invalid command sequences. A hardware reset may be required to return to normal operation from some undefined states. To exit the unlock bypass mode, the system must issue a two-cycle UNLOCK BYPASS RESET command sequence. A READ/RESET command will not exit unlock bypass mode. READ CFI Command The READ CFI (98h) command puts the device in read CFI mode and is only valid when the device is in read array or auto select mode. One bus WRITE cycle is required to issue the command. Once in read CFI mode, bus READ operations will output data from the CFI memory area (Refer to the Common Flash Interface for details). Read CFI mode is exited by performing a READ/RESET command (F0h). The device returns to read mode unless it entered read CFI mode after an ERASE SUSPEND or PROGRAM SUSPEND command, in which case it returns to erase or program suspend mode. AUTO SELECT Command At power-up or after a hardware reset, the device is in read mode. It can then be put in auto select mode by issuing an AUTO SELECT (90h) command. Auto select mode enables the following device information to be read: * Electronic signature, which includes manufacturer and device code information as shown in the Electronic Signature table. * Block protection, which includes the block protection status and extended memory block protection indicator, as shown in the Block Protection table. Electronic signature or block protection information is read by executing a READ operation with control signals and addresses set, as shown in the Read Electronic Signature table or the Block Protection table, respectively. In addition, this device information can be read or set by issuing an AUTO SELECT command. Auto select mode can be used by the programming equipment to automatically match a device with the application code to be programmed. Three consecutive bus WRITE operations are required to issue an AUTO SELECT command. The device remains in auto select mode until a READ/RESET or READ CFI command is issued. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR READ and AUTO SELECT Operations The device cannot enter auto select mode when a PROGRAM or ERASE operation is in progress (RY/BY# LOW). However, auto select mode can be entered if the PROGRAM or ERASE operation has been suspended by issuing a PROGRAM SUSPEND or ERASE SUSPEND command. Auto select mode is exited by performing a READ/RESET command (F0h). The device returns to read mode unless it entered auto select mode after an ERASE SUSPEND or PROGRAM SUSPEND command, in which case it returns to erase or program suspend mode. Table 9: Block Protection Note 1 applies to entire table Address Input READ Cycle CE# OE# WE# A[MAX:16] A[15:2] Data Input/Output A1 A0 DQ[15:0] 128-bit (0x0~0x7) Factory-Programmable Extended Memory Protection Indicator (Bit DQ7) Low lock L L H L L H 0009h2 H 0089h3 High lock L L H L L H 0019h2 H 0099h3 Block protection status Protected L L H Unprotected L L H Notes: Block base address L H L 0001h L H L 0000h 1. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW. 2. Customer-lockable (default). 3. Micron prelocked. Read Electronic Signature Table 10: Read Electronic Signature - 2Gb Note 1 applies to entire table Data Input/ Output Address Input READ Cycle CE# OE# WE# A[MAX:4] A3 A2 A1 A0 DQ[15:0] Manufacturer code L L H L L L L L 0089h Device code 1 L L H L L L L H 227Eh Device code 2 L L H L H H H L 2248h Device code 3 L L H L H H H H 2201h Note: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW. 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Cyclic Redundancy Check Operation Cyclic Redundancy Check Operation The device has two dies, and the CRC command is only effective for one die at one time. CYCLIC REDUNDANCY CHECK Command The CYCLIC REDUNDANCY CHECK (CRC) command is a nonsecure hash function designed to detect accidental changes to raw data. Typically, it is used in digital networks and storage devices such as hard disk drives. A CRC-enabled device calculates a short, fixed-length binary sequence known as the CRC code (or CRC). The device CRC operation will generate the CRC result of the whole device or of an address range specified by the operation. Then the CRC result is compared with the expected CRC data provided in the sequence. Finally, the device indicates a pass or fail through the data polling register. If the CRC fails, corrective action is possible, such as re-verifying with a normal READ mode or rewriting the array data. CRC is a higher performance alternative to reading data directly to verify recently programmed data, or as a way to periodically check the data integrity of a large block of data against a stored CRC reference over the life of the product. CRC helps improve test efficiency for programmer or burn-in stress tests. No system hardware changes are required to enable CRC. The CRC-64 operation follows the ECMA standard; the generating polynomial is: G(x) = x64 + x62 + x57 + x55 + x54 + x53 + x52 + x47 + x46 + x45 + x40 + x39 + x38 + x37 + x35 + x33 + x32+ x31 + x29 + x27 + x24 + x23 + x22 + x21 + x19 + x17 + x13 + x12 + x10 + x9 + x7 + x4 + x + 1 Note: The data stream sequence is from LSB to MSB and the default initial CRC value is all zeros. The CRC command sequences are shown in the tables below, for an entire die or for a selected range, respectively. Cyclic Redundancy Check Operation Command Sequence Table 11: Command Sequence - Range of Blocks Note 1 and 2 apply to entire table. Address DQ[15:0] Description Notes 0000555 00AAh UI unlock cycle 1 00002AA 0055h UI unlock cycle 2 0000000 00EBh Extended function interface command 0000000 0027h CRC sub-op code 0000000 000Ah N-1 data count 0000000 FFFEh CRC operation option data 0000001 Data 1st word of 64-bit expected CRC 0000002 Data 2nd word of 64-bit expected CRC 0000003 Data 3rd word of 64-bit expected CRC 0000004 Data 4th word of 64-bit expected CRC CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Cyclic Redundancy Check Operation Table 11: Command Sequence - Range of Blocks (Continued) Note 1 and 2 apply to entire table. Address DQ[15:0] Description Notes 0000005 DQ15 = A14 DQ14 = A13 ... DQ2 = A1 DQ1 = A0 DQ0 = set to zero Byte address to start 3 0000006 A30-A15 Byte address to start 3 0000007 Reserved 0000008 DQ15 = A14 DQ14 = A13 ... DQ2 = A1 DQ1 = A0 DQ0 = set to zero Byte address to stop 3 0000009 A30-A15 Byte address to stop 3 000000A Reserved 0000000 0029h Confirm command 0000000 Read Continue data polling to wait for device to be ready Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN Default as 0000h Default as 0000h 1. If the CRC check fails, a check error is generated by setting DQ5 = 1. 2. This is a byte-aligned operation. 3. The stop address must be bigger than the start address; otherwise, the algorithm will take no action. 4. The start address and stop address must be within one die range. 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Cyclic Redundancy Check Operation Table 12: Command Sequence - Entire Chip Address DQ[15:0] 0000555 00AAh UI unlock cycle 1 00002AA 0055h UI unlock cycle 2 0000000 00EBh Extended function interface command 0000000 0027h CRC sub-op code 0000000 0004h N-1 data count 0000000 FFFFh CRC operation option data 0000001 Data 1st word of 64-bit expected CRC 0000002 Data 2nd word of 64-bit expected CRC 0000003 Data 3rd word of 64-bit expected CRC 0000004 Data 4th word of 64-bit expected CRC 0000000 0029h Confirm command 0000000 Read Continue data polling to wait for device to be ready Note: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN Description 1. Applies to entire table: If the CRC check fails, a check error is generated by setting DQ5 = 1. 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Bypass Operations Bypass Operations UNLOCK BYPASS Command The UNLOCK BYPASS (20h) command is only effective for the selected die. If customer wants to program/erase the other die with the UNLOCK BYPASS command, the UNLOCK BYPASS command should be entered again. The UNLOCK BYPASS command is used to place the device in unlock bypass mode. Three bus WRITE operations are required to issue the UNLOCK BYPASS command. When the device enters unlock bypass mode, the two initial UNLOCK cycles required for a standard PROGRAM or ERASE operation are not needed, thus enabling faster total program or erase time. The UNLOCK BYPASS command is used in conjunction with UNLOCK BYPASS PROGRAM or UNLOCK BYPASS ERASE commands to program or erase the device faster than with standard PROGRAM or ERASE commands. Using these commands can save considerable time when the cycle time to the device is long. When in unlock bypass mode, only the following commands are valid: * The UNLOCK BYPASS PROGRAM command can be issued to program addresses within the device. * The UNLOCK BYPASS BLOCK ERASE command can then be issued to erase one or more memory blocks. * The UNLOCK BYPASS DIE ERASE command can be issued to erase the whole memory array. * The UNLOCK BYPASS WRITE TO BUFFER PROGRAM and UNLOCK BYPASS ENHANCED WRITE TO BUFFER PROGRAM commands can be issued to speed up the programming operation. * The UNLOCK BYPASS RESET command can be issued to return the device to read mode. In unlock bypass mode, the device can be read as if in read mode. In addition to the UNLOCK BYPASS command, when V PP/WP# is raised to V HH, the device automatically enters unlock bypass mode. When V PP/WP# returns to V IH or V IL, the device is no longer in unlock bypass mode, and normal operation resumes. The transitions from V IH to V HH and from V HH to V IH must be slower than tVHVPP. (See the Accelerated Program, Data Polling/Toggle AC Characteristics.) Note: Micron recommends entering and exiting unlock bypass mode using the ENTER UNLOCK BYPASS and UNLOCK BYPASS RESET commands rather than raising V PP/WP# to V HH. V PP/WP# should never be raised to V PPH from any mode except read mode; otherwise, the device may be left in an indeterminate state. V PP/WP# should not remain at VHH for than 80 hours cumulative. UNLOCK BYPASS RESET Command The UNLOCK BYPASS RESET (90/00h) command is used to return to read/reset mode from unlock bypass mode. Two bus WRITE operations are required to issue the UNLOCK BYPASS RESET command. The READ/RESET command does not exit from unlock bypass mode. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Program Operations Program Operations PROGRAM Command The PROGRAM (A0h) command can be used to program a value to one address in the memory array. The command requires four bus WRITE operations, and the final WRITE operation latches the address and data in the internal state machine and starts the program/erase controller. After programming has started, bus READ operations output the data polling register content. Programming can be suspended and then resumed by issuing a PROGRAM SUSPEND command and a PROGRAM RESUME command, respectively. If the address falls in a protected block, the PROGRAM command is ignored, and the data remains unchanged. The data polling register is not read, and no error condition is given. After the PROGRAM operation has completed, the device returns to read mode, unless an error has occurred. When an error occurs, bus READ operations to the device continue to output the data polling register. A READ/RESET command must be issued to reset the error condition and return the device to read mode. The PROGRAM command cannot change a bit set to 0 back to 1, and an attempt to do so is masked during a PROGRAM operation. Instead, an ERASE command must be used to set all bits in one memory block or in the entire memory from 0 to 1. The PROGRAM operation is aborted by performing a hardware reset or by powering down the device. In this case, data integrity cannot be ensured, and it is recommended that the words or bytes that were aborted be reprogrammed. UNLOCK BYPASS PROGRAM Command When the device is in unlock bypass mode, the UNLOCK BYPASS PROGRAM (A0h) command can be used to program one address in the memory array. The command requires two bus WRITE operations instead of four required by a standard PROGRAM command; the final WRITE operation latches the address and data and starts the program/erase controller (The standard PROGRAM command requires four bus WRITE operations). The PROGRAM operation using the UNLOCK BYPASS PROGRAM command behaves identically to the PROGRAM operation using the PROGRAM command. The operation cannot be aborted. A bus READ operation to the memory outputs the data polling register. WRITE TO BUFFER PROGRAM Command The WRITE TO BUFFER PROGRAM (25h) command makes use of the program buffer to speed up programming and dramatically reduces system programming time compared to the standard non-buffered PROGRAM command. This product supports a 512-word maximum program buffer. When issuing a WRITE TO BUFFER PROGRAM command, V PP/WP# can be held HIGH or raised to V HH. Also, it can be held LOW if the block is not the lowest or highest block, depending on the part number. The following successive steps are required to issue the WRITE TO BUFFER PROGRAM command: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Program Operations First, two UNLOCK cycles are issued. Next, a third bus WRITE cycle sets up the WRITE TO BUFFER PROGRAM command. The set-up code can be addressed to any location within the targeted block. Then, a fourth bus WRITE cycle sets up the number of words to be programmed. Value n is written to the same block address, where n + 1 is the number of words to be programmed. Value n + 1 must not exceed the size of the program buffer, or the operation will abort. A fifth cycle loads the first address and data to be programmed. Last, n bus WRITE cycles load the address and data for each word into the program buffer. Addresses must lie within the range from the start address +1 to the start address + (n - 1). Optimum programming performance and lower power usage are achieved by aligning the starting address at the beginning of a 512-word boundary (A[8:0] = 0x000h). Any buffer size smaller than 512 words is allowed within a 512-word boundary, while all addresses used in the operation must lie within the 512-word boundary. In addition, any crossing boundary buffer program will result in a program abort. To program the content of the program buffer, this command must be followed by a WRITE TO BUFFER PROGRAM CONFIRM command. If an address is written several times during a WRITE TO BUFFER PROGRAM operation, the address/data counter will be decremented at each data load operation, and the data will be programmed to the last word loaded into the buffer. Invalid address combinations or the incorrect sequence of bus WRITE cycles will abort the WRITE TO BUFFER PROGRAM command. The data polling register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status during a WRITE TO BUFFER PROGRAM operation. The WRITE TO BUFFER PROGRAM command should not be used to change a bit set to 0 back to 1, and an attempt to do so is masked during the operation. Rather than the WRITE TO BUFFER PROGRAM command, the ERASE command should be used to set memory bits from 0 to 1. Figure 9: Boundary Condition of Program Buffer Size 0000h 512 Words Any buffer program attempt is not allowed 0200h 512 Words 511 words or less are allowed in the program buffer 512-word program buffer is allowed 512-word program buffer is allowed 0400h CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Program Operations Figure 10: WRITE TO BUFFER PROGRAM Flowchart Start WRITE TO BUFFER command, block address WRITE TO BUFFER confirm, block address Write n,1 block address Perform polling algorithm First three cycles of the WRITE TO BUFFER PROGRAM command Write buffer data, start address Polling status = done? No X=n No X=0 Yes Error? Yes Yes No Abort WRITE TO BUFFER Yes Buffer program abort? Write to a different block address No Yes No Write next data,2 program address pair Failure: Issue BUFFERED PROGRAM ABORT AND RESET command Failure: Issue RESET command to return to read array mode Success: Return to read array mode X=X-1 Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. n + 1 is the number of addresses to be programmed. 2. The BUFFERED PROGRAM ABORT AND RESET command (3 cycles reset) must be issued to return the device to read mode. 3. When the block address is specified, any address in the selected block address space is acceptable. However, when loading program buffer address with data, all addresses must fall within the selected program buffer page. 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Program Operations UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command When the device is in unlock bypass mode, the UNLOCK BYPASS WRITE TO BUFFER (25h) command can be used to program the device in fast program mode. The command requires two bus WRITE operations fewer than the standard WRITE TO BUFFER PROGRAM command. The UNLOCK BYPASS WRITE TO BUFFER PROGRAM command behaves the same way as the WRITE TO BUFFER PROGRAM command: the operation cannot be aborted, and a bus READ operation to the memory outputs the data polling register. The WRITE TO BUFFER PROGRAM CONFIRM command is used to confirm an UNLOCK BYPASS WRITE TO BUFFER PROGRAM command and to program the n + 1 words loaded in the program buffer by this command. WRITE TO BUFFER PROGRAM CONFIRM Command The WRITE TO BUFFER PROGRAM CONFIRM (29h) command is used to confirm a WRITE TO BUFFER PROGRAM command and to program the n + 1 words loaded in the program buffer by this command. BUFFERED PROGRAM ABORT AND RESET Command A BUFFERED PROGRAM ABORT AND RESET (F0h) command must be issued to reset the device to read mode when the BUFFER PROGRAM operation is aborted. The buffer programming sequence can be aborted in the following ways: * Load a value that is greater than the page buffer size during the number of locations to program in the WRITE TO BUFFER PROGRAM command. * Write to an address in a different block than the one specified during the WRITE BUFFER LOAD command. * Write an address/data pair to a different write buffer page than the one selected by the starting address during the program buffer data loading stage of the operation. * Write data other than the CONFIRM command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DQ7# (for the last address location loaded), DQ6 = toggle, and DQ5 = 0 (all of which are data polling register bits). A BUFFERED PROGRAM ABORT and RESET command sequence must be written to reset the device for the next operation. Note: The full three-cycle BUFFERED PROGRAM ABORT and RESET command sequence is required when using buffer programming features in unlock bypass mode. PROGRAM SUSPEND Command The PROGRAM SUSPEND command can be used to interrupt a program operation so that data can be read from another block. When the PROGRAM SUSPEND command is issued during a program operation, the device suspends the operation within the program suspend latency time and updates the data polling register bits. After the PROGRAM operation has been suspended, data can be read from any address. However, data is invalid when read from an address where a program operation has been suspended. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Program Operations The PROGRAM SUSPEND command may also be issued during a PROGRAM operation while an erase is suspended. In this case, data may be read from any address not in erase suspend or program suspend mode. To read from the extended memory block area (one-time programmable area), the ENTER/EXIT EXTENDED MEMORY BLOCK command sequences must be issued. The system may also issue the AUTO SELECT command sequence when the device is in program suspend mode. The system can read as many auto select codes as required. When the device exits auto select mode, the device reverts to program suspend mode and is ready for another valid operation. The PROGRAM SUSPEND operation is aborted by performing a device reset or powerdown. In this case, data integrity cannot be ensured, and it is recommended that the words that were aborted be reprogrammed. This device has two different command codes for program suspend, B0h and 51h. Code B0h is available for legacy compatibility. Code 51h is recommended for use. PROGRAM RESUME Command The PROGRAM RESUME command must be issued to exit a program suspend mode and resume a PROGRAM operation. The controller can use DQ7 or DQ6 data polling bits to determine the status of the PROGRAM operation. After a PROGRAM RESUME command is issued, subsequent PROGRAM RESUME commands are ignored. Another PROGRAM SUSPEND command can be issued after the device has resumed programming. This device has two different command codes for Program Resume (30h or 50h). Code 30h is available for legacy compatibility. Code 50h is recommended to use. ACCELERATED BUFFERED PROGRAM Operations ACCELERATED BUFFER PROGRAM operations provides faster performance than standard program command sequences. Operations are enabled through V PP/WP# under the V HH voltage supply. When the system asserts V HH on input, the device automatically enters the UNLOCK BYPASS mode, which enables the system to use the UNLOCK BYPASS WRITE TO BUFFER PROGRAM (25h) command sequence. Removing V HH from the V PP upon completion of the embedded program operation returns the device to normal operation. Table 13: ACCELERATED PROGRAM Requirements and Recommendations Device State Requirements/Recommendations Device blocks Requirement: Must be unprotected prior to raising VPP/WP# to VHH VHH applied to VPP/WP# Requirement: Maximum cumulative period of 80 hours. VPP/WP# Requirement: Must not be at VHH for operations except ACCELERATED BUFFERED PROGRAM and DIE ERASE; otherwise device can be damaged Recommendation: Keep stable to VHH during ACCELERATED BUFFERED PROGRAM operation Power-up Recommendation: Apply VHH on VPP/WP# after VCC/VCCQ is stable on. Power-down Recommendation: Adjust VPP/WP# from VHH to VIH/VIL before VCC/VCCQ goes LOW. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Erase Operations Erase Operations DIE ERASE Command The DIE ERASE (80/10h) command erases the selected die. Six bus WRITE operations are required to issue the command and start the program/erase controller. Protected blocks are not erased. If all blocks are protected, the data remains unchanged. No error is reported when protected blocks are not erased. During the DIE ERASE operation, the selected die ignores all other commands, including ERASE SUSPEND. It is not possible to abort the operation. All bus READ operations during DIE ERASE output the data polling register on the data I/Os. See the Data Polling Register section for more details. After the DIE ERASE operation completes, the device returns to read mode, unless an error has occurred. If an error occurs, the device will continue to output the data polling register. When the operation fails, a READ/RESET command must be issued to reset the error condition and return to read mode. The status of the array must be confirmed through the BLANK CHECK operation and the BLOCK ERASE command re-issued to the failed block. The DIE ERASE command sets all of the bits in unprotected blocks of the device to 1. All previous data is lost. The operation is aborted by performing a reset or by powering down the device. In this case, data integrity cannot be ensured, and it is recommended that the entire chip be erased again. To erase the whole 2Gb array, two DIE ERASE operations are required. No parallel ERASE is allowed. The second DIE ERASE command must be issued after the completion of the first one. UNLOCK BYPASS DIE ERASE Command When the device is in unlock bypass mode, the UNLOCK BYPASS DIE ERASE (80/10h) command can be used to erase all memory blocks at one time. The command requires only two bus WRITE operations instead of six using the standard DIE ERASE command. The final bus WRITE operation starts the program/erase controller. The UNLOCK BYPASS DIE ERASE command behaves the same way as the DIE ERASE command: the operation cannot be aborted, and a bus READ operation to the memory outputs the data polling register. BLOCK ERASE Command The BLOCK ERASE (80/30h) command erase one block. It sets all bits in the unprotected selected block to 1. All previous data in the selected block are lost. Six bus WRITE operations are required to select the block to be erased. After the sixth bus WRITE operation, a bus READ operation outputs the data polling register. See the WE#-Controlled Program waveforms for details on how to identify if the program/erase controller has started the BLOCK ERASE operation. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Erase Operations After the BLOCK ERASE operation completes, the device returns to read mode, unless an error has occurred. If an error occurs, bus READ operations will continue to output the data polling register. A READ/RESET command must be issued to reset the error condition and return to read mode. If the selected block is protected, it is ignored and the data remains unchanged. No error condition is given when protected block is not erased. During the BLOCK ERASE operation, the device ignores all commands except the ERASE SUSPEND command and the READ STATUS command. The operation is aborted by performing a hardware reset or powering down the device. In this case, data integrity cannot be ensured, and it is recommended that the aborted blocks be erased again. UNLOCK BYPASS BLOCK ERASE Command When the device is in unlock bypass mode, the UNLOCK BYPASS BLOCK ERASE (80/30h) command can be used to erase one memory block. The command requires two bus WRITE operations instead of six using the standard BLOCK ERASE command. The final bus WRITE operation latches the address of the block and starts the program/ erase controller. The UNLOCK BYPASS BLOCK ERASE command behaves the same way as the BLOCK ERASE command: the operation cannot be aborted, and a bus READ operation to the memory outputs the data polling register. See the BLOCK ERASE Command section for details. ERASE SUSPEND Command The ERASE SUSPEND (B0h) command temporarily suspends a BLOCK ERASE operation. One bus WRITE operation is required to issue the command. The block address is "Don't Care." The program/erase controller suspends the ERASE operation within the erase suspend latency time of the ERASE SUSPEND command being issued. However, when the ERASE SUSPEND command is written during the block erase timeout, the device immediately terminates the timeout period and suspends the ERASE operation. After the program/erase controller has stopped, the device operates in read mode, and the erase is suspended. During an ERASE SUSPEND operation, it is possible to execute these operations in arrays that are not suspended: * * * * * * * * READ (main memory array) PROGRAM WRITE TO BUFFER PROGRAM AUTO SELECT READ CFI UNLOCK BYPASS Extended memory block commands READ/RESET Reading from a suspended block will output the data polling register. If an attempt is made to program in a protected or suspended block, the PROGRAM command is ignor- CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR ACCELERATED DIE ERASE Operations ed and the data remains unchanged; also, the data polling register is not read and no error condition is given. Before the RESUME command is initiated, the READ/RESET command must to issued to exit AUTO SELECT and READ CFI operations. In addition, the EXIT UNLOCK BYPASS and EXIT EXTENDED MEMORY BLOCK commands must be issued to exit unlock bypass and the extended memory block modes. An ERASE SUSPEND command is ignored if it is written during a DIE ERASE operation. If the ERASE SUSPEND operation is aborted by performing a device hardware reset or power-down, data integrity cannot be ensured, and it is recommended that the suspended blocks be erased again. ERASE RESUME Command The ERASE RESUME (30h) command restarts the program/erase controller after an ERASE SUSPEND operation. The device must be in read array mode before the RESUME command will be accepted. An erase can be suspended and resumed more than once. ACCELERATED DIE ERASE Operations The ACCELERATED DIE ERASE operation provides faster performance than the standard DIE ERASE command sequence. Operations are enabled through V PP/WP# under the V HH voltage supply. Note that the command is effective for the selected die only. When the system asserts V HH on input, the device automatically enters the UNLOCK BYPASS mode, which enables the system to use the UNLOCK BYPASS DIE ERASE (80/30h) command sequence. When a block is protected, the DIE ERASE command skips the protected block and continues with next block erase. The command algorithm skips a block that failed to erase and continues with the remaining blocks. The fail flag will be set for the operation. Removing V HH from the V PP/WP# upon completion of the embedded erase operation returns the device to normal operation. When an error occurs or when the operation fails, the array status should be confirmed through the BLANK CHECK operation and the BLOCK ERASE command re-issued to the failed block. Table 14: ACCELERATED DIE ERASE Requirements and Recommendations Device Component/State Requirements/Recommendations VPP/WP# Requirement: Must not be at VHH for operations except ACCELERATED PROGRAM and DIE ERASE; otherwise device can be damaged. VHH applied to VPP/WP# Requirement: Maximum cumulative period of 80 hours. Power-up Recommendation: Apply VHH on VPP/WP# after VCC/VCCQ is stable on. Power-down Recommendation: Adjust VPP/WP# from VHH to VIH/VIL before VCC/VCCQ goes LOW. BLANK CHECK Operation The BLANK CHECK operation determines whether a specified block is blank (that is, completely erased). It can also be used to determine whether a previous ERASE operaCCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR BLANK CHECK Operation tion was successful, including ERASE operations that might have been interrupted by power loss. The BLANK CHECK operation checks for cells that are programmed or over-erased. If it finds any, it returns a failure status, indicating that the block is not blank. If it returns a passing status, the block is guaranteed blank (all 1s) and is ready to program. Before executing, the ERASE operation initiates an embedded BLANK CHECK operation, and if the target block is blank, the ERASE operation is skipped, benefitting overall cycle performance; otherwise, the ERASE operation continues. The BLANK CHECK operation can occur in only one block at a time, and during its execution, reading the data polling register is the only other operation allowed. Reading from any address in the device enables reading the data polling register to monitor blank check progress or errors. Operations such as READ (array data), PROGRAM, ERASE, and any suspended operation are not allowed. After the BLANK CHECK operation has completed, the device returns to read mode unless an error has occurred. When an error occurs, the device continues to output data polling register data. A READ/RESET command must be issued to reset the error condition and return the device to read mode. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Device Protection Device Protection Hardware Protection The V PP/WP# function provides a hardware method of protecting either the highest or lowest block. When V PP/WP# is LOW, PROGRAM and ERASE operations on either of these block options is ignored to provide protection. When V PP/WP# is HIGH, the device reverts to the previous protection status for the highest or lowest block. PROGRAM and ERASE operations can modify the data in either of these block options unless block protection is enabled. Note: Micron highly recommends driving V PP/WP# HIGH or LOW. If a system needs to float the V PP/WP# pin, without a pull-up/pull-down resistor and no capacitor, then an internal pull-up resistor is enabled. Table 15: VPP/WP# Functions VPP/WP# Settings Function VIL Highest or lowest block is protected. VIH Highest or lowest block is unprotected unless software protection is activated. Software Protection The following software protection modes are available: * Volatile protection * Nonvolatile protection * Password protection The device is shipped with all blocks unprotected. On first use, the device defaults to the nonvolatile protection mode but can be activated in either the nonvolatile protection or password protection mode. The desired protection mode is activated by setting either the nonvolatile protection mode lock bit or the password protection mode lock bit of the lock register (see the Lock Register section). Both bits are one-time-programmable and nonvolatile; therefore, after the protection mode has been activated, it cannot be changed, and the device is set permanently to operate in the selected protection mode. It is recommended that the desired software protection mode be activated when first programming the device. For the highest or lowest block, a higher level of block protection can be achieved by locking the block using nonvolatile protection mode and holding V PP /WP# LOW. Blocks with volatile protection and nonvolatile protection can coexist within the memory array. If the user attempts to program or erase a protected block, the device ignores the command and returns to read mode. The block protection status can be read by performing a read electronic signature or by issuing an AUTO SELECT command (see the Block Protection table). Refer to the Block Protection Status table and the Software Protection Scheme figure for details on the block protection scheme. Refer to the Protection Operations section for a description of the command sets. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Device Protection The device is two die stacked, so following command is only effective for the selected die, * CLEAR VOLATILE PROTECTION BIT command * CLEAR ALL NONVOLATILE PROTECTION BITS command And the pass word protection is valid for one die only, therefore customer should set the full chip password protection to each die. Micron recommends customer to use the same password. Volatile Protection Mode Volatile protection enables the software application to protect blocks against inadvertent change and can be disabled when changes are needed. Volatile protection bits are unique for each block and can be individually modified. Volatile protection bits control the protection scheme only for unprotected blocks whose nonvolatile protection bits are cleared to 1. Issuing a PROGRAM VOLATILE PROTECTION BIT or CLEAR VOLATILE PROTECTION BIT command sets to 0 or clears to 1 the volatile protection bits and places the associated blocks in the protected (0) or unprotected (1) state, respectively. The volatile protection bit can be set or cleared as often as needed. When the device is first shipped, or after a power-up or hardware reset, the volatile protection bits default to 1 (unprotected). Nonvolatile Protection Mode A nonvolatile protection bit is assigned to each block. Each of these bits can be set for protection individually by issuing a PROGRAM NONVOLATILE PROTECTION BIT command. Also, each device has one global volatile bit called the nonvolatile protection bit lock bit; it can be set to protect all nonvolatile protection bits at once. This global bit must be set to 0 only after all nonvolatile protection bits are configured to the desired settings. When set to 0, the nonvolatile protection bit lock bit prevents changes to the state of the nonvolatile protection bits. When cleared to 1, the nonvolatile protection bits can be set and cleared using the PROGRAM NONVOLATILE PROTECTION BIT and CLEAR ALL NONVOLATILE PROTECTION BITS commands, respectively. No software command unlocks the nonvolatile protection bit lock bit unless the device is in password protection mode; in nonvolatile protection mode, the nonvolatile protection bit lock bit can be cleared only by taking the device through a hardware reset or power-up. Nonvolatile protection bits cannot be cleared individually; they must be cleared all at once using a CLEAR ALL NONVOLATILE PROTECTION BITS command. They will remain set through a hardware reset or a power-down/power-up sequence. If one of the nonvolatile protection bits needs to be cleared (unprotected), additional steps are required: First, the nonvolatile protection bit lock bit must be cleared to 1, using either a power-cycle or hardware reset. Then, the nonvolatile protection bits can be changed to reflect the desired settings. Finally, the nonvolatile protection bit lock bit must be set to 0 to lock the nonvolatile protection bits. The device now will operate normally. To achieve the best protection, the PROGRAM NONVOLATILE PROTECTION LOCK BIT command should be executed early in the boot code, and the boot code should be protected by holding V PP/WP# LOW. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Device Protection Nonvolatile protection bits and volatile protection bits have the same function when VPP/WP# is HIGH or when V PP/WP# is at the voltage for program acceleration (VHH ). Password Protection Mode The password protection mode provides a higher level of security than the nonvolatile protection mode by requiring a 64-bit password to unlock the nonvolatile protection bit lock bit. In addition to this password requirement, the nonvolatile protection bit lock bit is set to 0 after power-up and reset to maintain the device in password protection mode. Executing the UNLOCK PASSWORD command by entering the correct password clears the nonvolatile protection bit lock bit, enabling the block nonvolatile protection bits to be modified. If the password provided is incorrect, the nonvolatile protection bit lock bit remains locked, and the state of the nonvolatile protection bits cannot be modified. To place the device in password protection mode, the following two steps are required: First, before activating the password protection mode, a 64-bit password must be set and the setting verified. Password verification is allowed only before the password protection mode is activated. Next, password protection mode is activated by programming the password protection mode lock bit to 0. This operation is irreversible. After the bit is programmed, it cannot be erased, the device remains permanently in password protection mode, and the 64-bit password can be neither retrieved nor reprogrammed. In addition, all commands to the address where the password is stored are disabled. Note: There is no means to verify the password after password protection mode is enabled. If the password is lost after enabling the password protection mode, there is no way to clear the nonvolatile protection bit lock bit. Figure 11: Software Protection Scheme Volatile protection bit 1 = unprotected 0 = protected (Default setting depends on the product order option) Volatile protection Nonvolatile protection bit 1 = unprotected (default) 0 = protected Nonvolatile protection Nonvolatile protection bit lock bit (volatile) Array block 1 = unlocked (default, after power-up or hardware reset) 0 = locked Nonvolatile protection mode Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN Password protection mode 1. Volatile protection bits are programmed and cleared individually. Nonvolatile protection bits are programmed individually and cleared collectively. 2. Once programmed to 0, the nonvolatile protection bit lock bit can be reset to 1 only by taking the device through a power-up or hardware reset. 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Device Protection Table 16: Block Protection Status Nonvolatile Protection Bit Lock Bit1 Nonvolatile Protection Bit2 Volatile Protection Bit3 Block Protection Status4 1 1 1 00h Block unprotected; nonvolatile protection bit changeable. 1 1 0 01h Block protected by volatile protection bit; nonvolatile protection bit changeable. 1 0 1 01h Block protected by nonvolatile protection bit; nonvolatile protection bit changeable. 1 0 0 01h Block protected by nonvolatile protection bit and volatile protection bit; nonvolatile protection bit changeable. 0 1 1 00h Block unprotected; nonvolatile protection bit unchangeable. 0 1 0 01h Block protected by volatile protection bit; nonvolatile protection bit unchangeable. 0 0 1 01h Block protected by nonvolatile protection bit; nonvolatile protection bit unchangeable. 0 0 0 01h Block protected by nonvolatile protection bit and volatile protection bit; nonvolatile protection bit unchangeable. Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN Block Protection Status 1. Nonvolatile protection bit lock bit: when cleared to 1, all nonvolatile protection bits are unlocked; when set to 0, all nonvolatile protection bits are locked. 2. Block nonvolatile protection bit: when cleared to 1, the block is unprotected; when set to 0, the block is protected. 3. Block volatile protection bit: when cleared to 1, the block is unprotected; when set to 0, the block is protected. 4. Block protection status is checked under AUTO SELECT mode. 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Block Protection Command Definitions - Address-Data Cycles Block Protection Command Definitions - Address-Data Cycles Table 17: Block Protection Command Definitions - Address-Data Cycles Notes 1 and 2 apply to entire table Address and Data Cycles Command and Code/Subcode 1st A 2nd 3rd 4th D A D A D 555 AA 2AA 55 555 40 PROGRAM LOCK REGISTER (A0h) X A0 X Data READ LOCK REGISTER X Data EXIT LOCK REGISTER (90h/00h) X 90 A nth D ... A D Notes LOCK REGISTER Commands ENTER LOCK REGISTER COMMAND SET (40h) 3 5 4, 5, 6 X 00 3 PASSWORD PROTECTION Commands ENTER PASSWORD PROTECTION COMMAND SET (60h) 555 AA 2AA 55 555 60 3 PROGRAM PASSWORD (A0h) X A0 PWAn PWDn READ PASSWORD 00 PWD0 01 PWD1 02 PWD2 03 PWD3 UNLOCK PASSWORD (25h/03h) 00 25 00 03 00 PWD0 01 PWD1 EXIT PASSWORD PROTECTION (90h/00h) X 90 X 00 7 4, 6, 8 ... 00 29 8 3 NONVOLATILE PROTECTION Commands ENTER NONVOLATILE PROTECTION COMMAND SET (C0h) 555 AA 2AA 55 PROGRAM NONVOLATILE PROTECTION BIT (A0h) X A0 BAd 00 BAd READ (DQ0) CLEAR ALL NONVOLATILE PROTECTION BITS (80h/30h) X 80 00 30 10 EXIT NONVOLATILE PROTECTION (90h/00h) X 90 X 00 3 READ NONVOLATILE PROTECTION BIT STATUS 555 C0 3 9 4, 6, 9 NONVOLATILE PROTECTION BIT LOCK BIT Commands CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Block Protection Command Definitions - Address-Data Cycles Table 17: Block Protection Command Definitions - Address-Data Cycles (Continued) Notes 1 and 2 apply to entire table Address and Data Cycles 1st Command and Code/Subcode 2nd 3rd 4th A D A D A D 555 AA 2AA 55 555 50 PROGRAM NONVOLATILE PROTECTION BIT LOCK BIT (A0h) X A0 X 00 READ NONVOLATILE PROTECTION BIT LOCK BIT STATUS X READ (DQ0) EXIT NONVOLATILE PROTECTION BIT LOCK BIT (90h/00h) X 90 X 00 ENTER NONVOLATILE PROTECTION BIT LOCK BIT COMMAND SET (50h) A nth D ... A D Notes 3 9 4, 6, 9 3 VOLATILE PROTECTION Commands ENTER VOLATILE PROTECTION COMMAND SET (E0h) 555 AA 2AA 55 PROGRAM VOLATILE PROTECTION BIT (A0h) X A0 BAd 00 BAd READ (DQ0) CLEAR VOLATILE PROTECTION BIT (A0h) X A0 BAd 01 9 EXIT VOLATILE PROTECTION (90h/00h) X 90 X 00 3 READ VOLATILE PROTECTION BIT STATUS 555 E0 3 9 4, 6 EXTENDED MEMORY BLOCK Operations ENTER EXTENDED MEMORY BLOCK (88h) 555 AA 2AA 55 555 88 PROGRAM EXTENDED MEMORY BLOCK (A0h) 555 AA 2AA 55 555 A0 Word address data READ EXTENDED MEMORY BLOCK Word address data EXIT EXTENDED MEMORY BLOCK (90h/00h) 555 AA 2AA 55 555 90 X 00 Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. Key: A = Address and D = Data; X = "Don't Care;" BAd = Any address in the block; PWDn = Password words, n = 0 to 3; PWAn = Password address, n = 0 to 3; Gray = Not applicable. All values in the table are hexadecimal. 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Block Protection Command Definitions - Address-Data Cycles 2. DQ[15:8] are "Don't Care" during UNLOCK and COMMAND cycles. A[MAX:16] are "Don't Care" during UNLOCK and COMMAND cycles, unless an address is required. 3. The ENTER command sequence must be issued prior to any operation. It disables READ and WRITE operations from and to block 0. READ and WRITE operations from and to any other block are allowed. Also, when an ENTER COMMAND SET command is issued, an EXIT COMMAND SET command must be issued to return the device to READ mode. 4. READ REGISTER/PASSWORD commands have no command code; CE# and OE# are driven LOW and data is read according to a specified address. 5. Data = Lock register content. 6. All address cycles shown for this command are READ cycles. 7. Only one portion of the password can be programmed or read by each PROGRAM PASSWORD command. 8. Each portion of the password can be entered or read in any order as long as the entire 64-bit password is entered or read. 9. Both nonvolatile and volatile protection bit settings are as follows: Protected state = 00; Unprotected state = 01. 10. The CLEAR ALL NONVOLATILE PROTECTION BITS command programs all nonvolatile protection bits before erasure. This prevents over-erasure of previously cleared nonvolatile protection bits. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Protection Operations Protection Operations Blocks can be protected individually against accidental PROGRAM or ERASE operations. The block protection scheme is shown in the Software Protection Scheme figure. Memory block and extended memory block protection is configured through the lock register. LOCK REGISTER Commands After the ENTER LOCK REGISTER COMMAND SET (40h) command has been issued, all bus READ or PROGRAM operations can be issued to the lock register. The PROGRAM LOCK REGISTER (A0h) command allows the lock register to be configured. The programmed data can then be checked with a READ LOCK REGISTER command by driving CE# and OE# LOW with the appropriate address data on the address bus. PASSWORD PROTECTION Commands After the ENTER PASSWORD PROTECTION COMMAND SET (60h) command has been issued, the commands related to password protection mode can be issued to the device. The PROGRAM PASSWORD (A0h) command is used to program the 64-bit password used in the password protection mode. To program the 64-bit password, the complete command sequence must be entered four times at four consecutive addresses selected by A[1:0]. By default, all password bits are set to 1. The password can be checked by issuing a READ PASSWORD command. Note: A password must be programmed per Flash memory die to enable password protection. The READ PASSWORD command is used to verify the password used in password protection mode. To verify the 64-bit password, the complete command sequence must be entered four times at four consecutive addresses selected by A[1:0]. If the password mode lock bit is programmed and the user attempts to read the password, the device will output 00h onto the I/O data bus. The UNLOCK PASSWORD (25/03h) command is used to clear the nonvolatile protection bit lock bit, allowing the nonvolatile protection bits to be modified. The UNLOCK PASSWORD command must be issued, along with the correct password, and requires a 6s delay between successive UNLOCK PASSWORD commands in order to prevent hackers from cracking the password by trying all possible 64-bit combinations. If this delay does not occur, the latest command will be ignored. Approximately 6s is required for unlocking the device after the valid 64-bit password has been provided. NONVOLATILE PROTECTION Commands After the ENTER NONVOLATILE PROTECTION COMMAND SET (C0h) command has been issued, the commands related to nonvolatile protection mode can be issued to the device. A block can be protected from program or erase by issuing a PROGRAM NONVOLATILE PROTECTION BIT (A0h) command, along with the block address. This command sets the nonvolatile protection bit to 0 for a given block. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Protection Operations The status of a nonvolatile protection bit for a given block or group of blocks can be read by issuing a READ NONVOLATILE MODIFY PROTECTION BIT command, along with the block address. The nonvolatile protection bits are erased simultaneously by issuing a CLEAR ALL NONVOLATILE PROTECTION BITS (80/30h) command. No specific block address is required. If the nonvolatile protection bit lock bit is set to 0, the command fails. Figure 12: Set/Clear Nonvolatile Protection Bit Algorithm Flowchart Start ENTER NONVOLATILE PROTECTION command set PROGRAM/CLEAR NONVOLATILE PROTECTION BIT Polling algorithm No Done? Yes READ NONVOLATILE PROTECTION BIT STATUS Match expected value? DQ0 = 1 (clear) or 0 (set) No Yes Success EXIT PROTECTION command set Notes: 1. See the Block Protection Command Definitions table for address-data cycle details. 2. DQ5 and DQ1 are ignored in this algorithm flow. NONVOLATILE PROTECTION BIT LOCK BIT Commands After the ENTER NONVOLATILE PROTECTION BIT LOCK BIT COMMAND SET (50h) command has been issued, the commands that allow the nonvolatile protection bit lock bit to be set can be issued to the device. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Protection Operations The PROGRAM NONVOLATILE PROTECTION BIT LOCK BIT (A0h) command is used to set the nonvolatile protection bit lock bit to 0, thus locking the nonvolatile protection bits and preventing them from being modified. The READ NONVOLATILE PROTECTION BIT LOCK BIT STATUS command is used to read the status of the nonvolatile protection bit lock bit. VOLATILE PROTECTION Commands After the ENTER VOLATILE PROTECTION COMMAND SET (E0h) command has been issued, commands related to the volatile protection mode can be issued to the device. The PROGRAM VOLATILE PROTECTION BIT (A0h) command individually sets a volatile protection bit to 0 for a given block. If the nonvolatile protection bit for the same block is set, the block is locked regardless of the value of the volatile protection bit (see the Block Protection Status table). The status of a volatile protection bit for a given block can be read by issuing a READ VOLATILE PROTECTION BIT STATUS command along with the block address. The CLEAR VOLATILE PROTECTION BIT (A0h) command individually clears (sets to 1) the volatile protection bit for a given block. If the nonvolatile protection bit for the same block is set, the block is locked regardless of the value of the volatile protection bit (see the Block Protection Status table). EXTENDED MEMORY BLOCK Commands The device has one extra 512-word extended memory block that can be accessed only by the ENTER EXTENDED MEMORY BLOCK (88h) command. It is used as a security block to provide a permanent 128-bit secure ID number or to store additional information. The device can be shipped with the extended memory block prelocked permanently by Micron, including the 128-bit security identification number. Or, the device can be shipped with the extended memory block unlocked, enabling customers to permanently program and lock it (default) (see Lock Register, the AUTO SELECT command, and the Block Protection table.) Table 18: Extended Memory Block Address and Data Data Address Micron Prelocked Customer Lockable 000000h- 000007h Secure ID number Determined by customer (default) 000008h- 0001FFh Protected and unavailable After the ENTER EXTENDED MEMORY BLOCK command has been issued, the device enters the extended memory block mode. All bus READ or PROGRAM operations are conducted on the extended memory block, and the extended memory block is addressed using the addresses occupied by block 0 in the other operating modes (see the Memory Map table). In extended memory block mode, ERASE, DIE ERASE, ERASE SUSPEND, and ERASE RESUME commands are not allowed. The extended memory block cannot be erased, and each bit of the extended memory block can only be programmed once. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Protection Operations The extended memory block is protected from further modification by programming lock register bit 0. Once invoked, this protection cannot be undone. The device remains in extended memory block mode until the EXIT EXTENDED MEMORY BLOCK (90/00h) command is issued, which returns the device to read mode, or until power is removed from the device. After a power-up sequence or hardware reset, the device will revert to reading memory blocks in the main array. EXIT PROTECTION Command The EXIT PROTECTION COMMAND SET (90/00h) command is used to exit the lock register, password protection, nonvolatile protection, volatile protection, and nonvolatile protection bit lock bit command set modes and return the device to read mode. Note that the READ/RESET command (F0h) is ignored under these modes. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Common Flash Interface Common Flash Interface The common Flash interface (CFI) is a JEDEC-approved, standardized data structure that can be read from the Flash memory device. It allows a system's software to query the device to determine various electrical and timing parameters, density information, and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the READ CFI command is issued, the device enters CFI query mode and the data structure is read from memory. The following tables show the addresses (A[7:0]) used to retrieve the data. The query data is always presented on the lowest order data outputs (DQ[7:0]), and the other data outputs (DQ[15:8]) are set to 0. Table 19: Query Structure Overview Note 1 applies to the entire table Address Subsection Name Description 10h CFI query identification string Command set ID and algorithm data offset 1Bh System interface information Device timing and voltage information 27h Device geometry definition Flash device layout 40h Primary algorithm-specific extended query table Additional information specific to the primary algorithm (optional) Note: 1. Query data are always presented on the lowest order data outputs (DQ[7:0]). DQ[15:8] are set to 0. Table 20: CFI Query Identification String Note 1 applies to the entire table Address Data Description Value 10h 0051h 11h 0052h Query unique ASCII string "QRY" "R" 12h 0059h "Y" 13h 14h 0002h 0000h Primary algorithm command set and control interface ID code 16-bit ID code defining a specific algorithm - 15h 16h 0040h 0000h Address for primary algorithm extended query table (see the Primary AlgorithmSpecific Extended Query Table) P = 40h 17h 18h 0000h 0000h Alternate vendor command set and control interface ID code second vendor-specified algorithm supported - 19h 1Ah 0000h 0000h Address for alternate algorithm extended query table - Note: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN "Q" 1. Query data are always presented on the lowest order data outputs (DQ[7:0]). DQ[15:8] are set to 0. 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Common Flash Interface Table 21: CFI Query System Interface Information Note 1 applies to the entire table Address Data Description Value 1Bh 0027h VCC logic supply minimum program/erase voltage Bits[7:4] BCD value in volts Bits[3:0] BCD value in 100mV 2.7V 1Ch 0036h VCC logic supply maximum program/erase voltage Bits[7:4] BCD value in volts Bits[3:0] BCD value in 100mV 3.6V 1Dh 0085h VHH (programming) supply minimum program/erase voltage Bits[7:4] hex value in volts Bits[3:0] BCD value in 100mV 8.5V 1Eh 0095h VHH (programming) supply maximum program/erase voltage Bits[7:4] hex value in volts Bits[3:0] BCD value in 10mV 9.5V 1Fh 0005h Typical timeout for single byte/word program = 2ns 32s 20h 0009h Typical timeout for maximum size buffer program = 21h 0008h Typical timeout per individual block erase = 22h 0011h Typical timeout for full die erase = 2nms 23h 24h 0003h 0002h 2nms 2n 2n 256ms times typical times typical 2n 25h 0003h Maximum timeout per individual block erase = 26h 0003h Maximum timeout for die erase = 2n times typical Note: 512s 131s Maximum timeout for byte/word program = Maximum timeout for buffer program = 2ns times typical 256s 2048s 2s 1048s 1. The values in this table are valid for all packages. Table 22: Device Geometry Definition Address Data Description Value 2n 27h 001Ch Device size = 28h 29h 0001h 0000h Flash device interface code description 2Ah 2Bh 000Ah 0000h Maximum number of bytes in multi-byte program or page = 2n 2Ch 0001h Number of erase block regions. It specifies the number of regions containing contiguous erase blocks of the same size. 2Dh 2Eh 00FFh 0007h Erase block region 1 information Number of identical-size erase blocks = 07FFh + 1 2Fh 30h 0000h 0002h Erase block region 1 information Block size in region 1 = 0200h x 256 bytes 31h 32h 33h 34h 0000h 0000h 0000h 0000h Erase block region 2 information CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN in number of bytes 54 256MB x16 asynchronous 1024 1 2048 128KB 0 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Common Flash Interface Table 22: Device Geometry Definition (Continued) Address Data Description 35h 36h 37h 38h 0000h 0000h 0000h 0000h Erase block region 3 information Value 0 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Erase block region 4 information 0 3Dh 3Eh 3Fh FFFFh FFFFh FFFFh Reserved - Table 23: Primary Algorithm-Specific Extended Query Table Note 1 applies to the entire table Address Data Description Value 40h 0050h 41h 0052h 42h 0049h 43h 0031h Major version number, ASCII "1" 44h 0035h Minor version number, ASCII "5" 45h 001Ch Address sensitive unlock (bits[1:0]): 00 = Required 01 = Not required Process technology (bits [7:2]) 0111b: Second generation 46h 0002h Erase suspend: 00 = Not supported 01 = Read only 02 = Read and write 2 47h 0001h Block protection: 00 = Not supported x = Number of blocks per group 1 48h 0000h Temporary block unprotect scheme: 00 = Not supported 01 = Supported 49h 0008h Protect/unprotect scheme: 08 = Advanced sector protection method 8 4Ah 0000h Simultaneous operations: Not supported - 4Bh 0000h Burst mode: 00 = Not supported 01 = Supported CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN Primary algorithm extended query table unique ASCII string "PRI" "P" "R" "I" Required Not supported Not supported 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Common Flash Interface Table 23: Primary Algorithm-Specific Extended Query Table (Continued) Note 1 applies to the entire table Address Data Description Value 4Ch 0003h Page mode: 00 = Not supported 01 = 4-word page 02 = 8-word page 03 = 16-word page 4Dh 0085h VHH supply minimum program/erase voltage: Bits[7:4] hex value in volts Bits[3:0] BCD value in 100mV 8.5V 4Eh 0095h VHH supply maximum program/erase voltage: Bits[7:4] hex value in volts Bits[3:0] BCD value in 100mV 9.5V 4Fh 00xxh WP# protection: xx = 04h: Uniform device, HW protection for lowest block xx = 05h: Uniform device, HW protection for highest block 50h 0001h Program suspend: 00 = Not supported 01 = Supported Supported 51h 0001h Unlock bypass: 00 = Not supported 01 = Supported Supported 52h 000Ah Extended memory block (customer OTP area): 2n bytes 1024 bytes CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 16-word page 56 Uniform + VPP/WP# protecting highest or lowest block Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Common Flash Interface Table 23: Primary Algorithm-Specific Extended Query Table (Continued) Note 1 applies to the entire table Address Data Description 53h 008Fh Value Software Features - bit 0: Status register polling 00 = Not supported 01 = Supported) bit 1: DQ polling 00 = Not supported 01 = Supported) bit 2: Program suspend/resume commands 00 = Not supported 01 = Supported) bit 3: Word programming 00 = Not supported 01 = Supported) bit 4: Bit-field programming 00 = Not supported 01 = Supported) bit 5: Autodetect programming 00 = Not supported 01 = Supported) bit 6: RFU bit 7: Multiple writes per line 00 = Not supported 01 = Supported) 54h 0005h Page size: 2n bytes 32 bytes 2n 55h 0005h Erase suspend timeout maximum: 56h 0004h Program suspend timeout maximum: 2n (s) 57h to 77h FFFFh Reserved 0005h tPLRH 0009h tVCCPH 78h 79h 32s 16s - 2n maximum: Power-on reset Note: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN maximum: (s) (s) 2n 32s (s) 512s 1. The values in this table are valid for both packages. 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Power-Up and Reset Characteristics Power-Up and Reset Characteristics Table 24: Power-Up Specifications Note 1 applies to entire table. Symbol Parameter Legacy JEDEC Min Unit Notes - tVCHVCQH 0 s 2 VCC HIGH to rising edge of RST# tVCS tVCHPH 300 s 3, 4 VCCQ HIGH to rising edge of RST# tVIOS tVCQHPH 0 s 3, 4 tRH tPHEL 50 ns - tPHWL 150 ns VCC HIGH to VCCQ HIGH RST# HIGH to chip enable LOW RST# HIGH to write enable LOW Notes: 1. Sampled only; not 100% tested. 2. VCC should attain VCC,min from VSS simultaneously with or prior to applying VCCQ during power up. VCC should attain VSS during power down. 3. If RST# is not stable for tVCS or tVIOS, the device will not allow any READ or WRITE operations, and a hardware reset is required. 4. Power supply transitions should only occur when RST# is LOW. Figure 13: Power-Up Timing tVCHVCQH VCC VSS VCCQ VSSQ tRH CE# tVIOS RST# tVCS WE# tPHWL CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Power-Up and Reset Characteristics Table 25: Reset AC Specifications Symbol Condition/Parameter Legacy JEDEC Min Max Unit Notes RST# LOW to read mode during program or erase tREADY tPLRH - 25 s 1 RST# pulse width tRP tPLPH 100 - ns RST# HIGH to CE# LOW, OE# LOW tRH tPHEL, tPHGL 50 - ns tRPD - 0 - s 0 - s 0 - ns RST# LOW to standby mode during read mode RST# LOW to standby mode during program or erase tRB RY/BY# HIGH to CE# LOW, OE# LOW Note: tRHEL, tRHGL 1 1 1. Sampled only; not 100% tested. Figure 14: Reset AC Timing - No PROGRAM/ERASE Operation in Progress RY/BY# CE#, OE# tRH RST# tRP Figure 15: Reset AC Timing During PROGRAM/ERASE Operation tREADY RY/BY# tRB CE#, OE# tRH RST# tRP CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Absolute Ratings and Operating Conditions Absolute Ratings and Operating Conditions Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 26: Absolute Maximum/Minimum Ratings Parameter Symbol Min Max Unit Temperature under bias TBIAS -50 125 C Storage temperature TSTG -65 150 C Supply voltage VCC -0.6 VCC + 2 V 1, 2 Input/output supply voltage VCCQ -0.6 VCCQ + 2 V 1, 2 VPP -0.6 9.5 V 3 Program/erase voltage Notes: Notes 1. During signal transitions, minimum voltage may undershoot to -2V for periods less than 20ns. 2. During signal transitions, maximum voltage may overshoot to VCC + 2V for periods less than 20ns. 3. VPP must not remain at 9.5V for more than 80 hours cumulative. Table 27: Operating Conditions Parameter Symbol Min Max Unit Supply voltage VCC 2.7 3.6 V Input/output supply voltage (VCCQ VCC) VCCQ 1.65 3.6 V Accelerated buffered program/die erase voltage VHH 8.5 9.5 V Ambient operating temperature TA -40 Load capacitance CL Input rise and fall times (VIL to VIH) - Input pulse voltages - Input and output timing reference voltages - Address to address skew - Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 105 30 0.3 C pF 2.5 0 to VCCQ ns 1, 2 V VCCQ/2 - Notes V 3 ns 1. If the rise/fall time is slower than 2.5ns, all timing specs must be derated by 0.5ns for every nanosecond push-out in rise/fall time. (Example: for a 10ns rise/fall time, all timing specs must be derated by (10 - 2.5) x (0.5ns) = 3.75ns. 2. Applies to Address, CE#, OE#, and WE# signals. 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Absolute Ratings and Operating Conditions Figure 16: AC Measurement Load Circuit VCCQ VCC 25k Device under test CL 25k 0.1F Note: 1. CL includes jig capacitance. Figure 17: AC Measurement I/O Waveform VCCQ VCCQ/2 0V Table 28: Input/Output Capacitance Parameter Input capacitance RST# input capacitance Output capacitance CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN Symbol Test Condition Min Max Unit CIN VIN = 0V 5 13 pF CIN_RST# VIN = 0V 18 22 pF COUT VOUT = 0V 5 12 pF 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR DC Characteristics DC Characteristics Table 29: DC Current Characteristics Parameter Input load current Symbol Conditions Min Typ Max Unit Notes ILI 0V VIN VCC - - 1 A 1 Output leakage current ILO 0V VOUT VCC - - 1 A VCC read current ICC1 CE# = VIL, OE# = VIH, f = 5 MHz - 26 31 mA CE# = VIL, OE# = VIH, f = 13 MHz - 12 16 mA ICC2 CE# = VCCQ 0.2V, RST# = VCCQ 0.2V - 150 460 A ICC APS VCC = VCC,max, VCCQ = VCCQ,max CE# = VSSQ, RST# = VCCQ, All inputs are at VCCQ or VSS - - 4 mA VPP/WP# = VIL or VIH - 35 50 mA VPP/WP# = VHH - 35 50 mA - 4 30 A - 0.4 10 A Random read Page read VCC standby current VCC automatic power saving (APS) current VCC program/erase/blank check current VPP current ICC3 Read IPP1 Standby IPP2 PROGRAM operation ongoing IPP3 ERASE operation ongoing IPP4 Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN Program/ erase controller active VPP/WP# VCC VPP/WP# = VHH - 5 10 mA VPP/WP# = VCC - 0.1 0.2 mA VPP/WP# = VHH - 5 10 mA VPP/WP# = VCC - 0.1 0.2 mA 2 1. The maximum input load current is 5A on the VPP/WP# pin. 2. Sampled only; not 100% tested. 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR DC Characteristics Table 30: DC Voltage Characteristics Parameter Input LOW voltage Symbol Conditions Min Typ Max Unit VIL VCC 2.7V -0.5 - 0.3 x VCCQ V Notes Input HIGH voltage VIH VCC 2.7V 0.7 x VCCQ - VCCQ + 0.4 V Output LOW voltage VOL IOL = 100A, VCC = VCC,min, VCCQ = VCCQ,min - - 0.15 x VCCQ V Output HIGH voltage VOH IOH = 100A, VCC = VCC,min, VCCQ = VCCQ,min 0.85 x VCCQ - - V Voltage for VPP/WP# program acceleration VPP - 8.5 - 9.5 V 1 Program/erase lockout supply voltage VLKO - 2.0 - - V 2, 3 Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. VPP must not remain at 9.5V for more than 80 hours cumulative. 2. Sampled only; not 100% tested. 3. WRITE operations are not valid when VCC supply drops below VLKO. 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Read AC Characteristics Read AC Characteristics Table 31: Read AC Characteristics - VCC = VCCQ = 2.7-3.6V Symbol Parameter Legacy JEDEC Condition Min Max Unit tRC tAVAV CE# = VIL, OE# = VIL 105 - ns tACC tAVQV CE# = VIL, OE# = VIL - 105 ns tPAGE tAVQV1 CE# = VIL, OE# = VIL - 20 ns CE# LOW to output valid tCE tELQV OE# = VIL - 105 ns OE# LOW to output valid tOE tGLQV CE# = VIL - 25 ns CE# HIGH to output High-Z tHZ tEHQZ OE# = VIL - 20 ns 1 OE# HIGH to output High-Z tDF tGHQZ CE# = VIL - 15 ns 1 CE# HIGH, OE# HIGH, or address transition to output transition tOH tEHQX, - 0 - ns Address valid to next address valid Address valid to output valid Address valid to output valid (page) Notes tGHQX, tAXQX Note: 1. Sampled only; not 100% tested. Table 32: Read AC Characteristics - VCCQ = 1.65V-VCC Symbol Parameter Address valid to next address valid Address valid to output valid Address valid to output valid (page) Legacy JEDEC Condition Min Max Unit tRC tAVAV CE# = VIL, OE# = VIL 110 - ns tACC tAVQV CE# = VIL, OE# = VIL - 110 ns tPAGE tAVQV1 CE# = VIL, OE# = VIL - 25 ns Notes CE# LOW to output valid tCE tELQV OE# = VIL - 110 ns OE# LOW to output valid tOE tGLQV CE# = VIL - 25 ns CE# HIGH to output High-Z tHZ tEHQZ OE# = VIL - 20 ns 1 OE# HIGH to output High-Z tDF tGHQZ CE# = VIL - 15 ns 1 CE# HIGH, OE# HIGH, or address transition to output transition tOH tEHQX, - 0 - ns tGHQX, tAXQX Note: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. Sampled only; not 100% tested. 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Read AC Characteristics Figure 18: Random Read AC Timing tRC A[MAX:0] Valid tACC tOH CE# tCE tOH tLZ tHZ OE# tOLZ tOH tOE tDF DQ[15:0] Valid Figure 19: Page Read AC Timing A[MAX:4] Valid A[3:0] Valid Valid Valid Valid Valid Valid Valid tACC CE# tCE tOH tHZ OE# tOE tPAGE tOH tDF DQ[15:0] Valid Note: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN Valid Valid Valid Valid Valid Valid 1. Page size is 16 words and is addressed by address inputs A[3:0]. 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Write AC Characteristics Write AC Characteristics Table 33: WE#-Controlled Write AC Characteristics Symbol Parameter Legacy JEDEC Min tWC - 60 - - ns CE# LOW to WE# LOW tCS tELWL 0 - - ns WE# LOW to WE# HIGH tWP tWLWH 35 - - ns Input valid to WE# HIGH tDS tDVWH 30 - - ns WE# HIGH to input transition tDH tWHDX 0 - - ns WE# HIGH to CE# HIGH tCH tWHEH 0 - - ns WE# HIGH to WE# LOW tWPH tWHWL 20 - - ns Address valid to WE# LOW tAS tAVWL 0 - - ns WE# LOW to address transition tAH tWLAX 45 - - ns OE# HIGH to WE# LOW - tGHWL 0 - - ns WE# HIGH to OE# LOW tOEH tWHGL 0 - - ns Program/erase valid to RY/BY# LOW tBUSY tWHRL - - 90 ns - tWHQV tAVQV - - ns - - ns WRITE cyle time WE# HIGH to OE# valid Typ Max Unit Notes 1 2 + 30 VHH rise or fall time on VPP/WP# Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN tVHVPP - 250 1. The user's write timing must comply with this specification. Any violation of this write timing specification may result in permanent damage to the NOR Flash device. 2. Sampled only; not 100% tested. 66 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Write AC Characteristics Figure 20: WE#-Controlled Program AC Timing 3rd Cycle 4th Cycle Data Polling tWC READ Cycle tWC A[MAX:0] 555h PA tAS PA tAH tCH tCS tCE CE# tGHWL tOE OE# tWP tWPH WE# tWHWH1 tDS DQ[15:0] A0h PD DQ7# tDF DOUT tOH DOUT tDH Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. Only the third and fourth cycles of the PROGRAM command are represented. The PROGRAM command is followed by checking of the status register data polling bit and by a READ operation that outputs the data (DOUT) programmed by the previous PROGRAM command. 2. PA is the address of the memory location to be programmed. PD is the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit [DQ7]). 4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled Write AC Characteristics, and CE#-Controlled Write AC Characteristics. 5. For tWHWH1 timing details, see the Program/Erase Characteristics table. 67 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Write AC Characteristics Table 34: CE#-Controlled Write AC Characteristics Symbol Parameter Legacy JEDEC Min WRITE cycle time tWC - 60 - - ns WE# LOW to CE# LOW tWS tWLEL 0 - - ns CE# LOW to CE# HIGH tCP tELEH 35 - - ns Input valid to CE# HIGH tDS tDVEH 30 - - ns CE# HIGH to input transition tDH tEHDX 0 - - ns CE# HIGH to WE# HIGH tWH tEHWH 0 - - ns CE# HIGH to CE# LOW tCPH tEHEL 20 - - ns Address valid to CE# LOW tAS tAVEL 0 - - ns CE# LOW to address transition tAH tELAX 45 - - ns OE# HIGH to CE# LOW - tGHEL 0 - - ns VHH rise or fall time on VPP/WP# - tVHVPP 250 - - ns tBUSY tWHRL - - 90 ns - tWHQV - - ns Program/erase valid to RY/BY# LOW WE# HIGH to OE# valid tAVQV Typ + Max Unit Notes 1 2 30 Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. The user's write timing must comply with this specification. Any violation of this write timing specification may result in permanent damage to the NOR Flash device. 2. Sampled only; not 100% tested. 68 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Write AC Characteristics Figure 21: CE#-Controlled Program AC Timing 3rd Cycle 4th Cycle Data Polling 555h PA PA tWC A[MAX:0] tAS tAH tWH tWS WE# tGHEL OE# tCP tCPH CE# tWHWH1 tDS DQ[15:0] A0h PD DQ7# DOUT tDH Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. Only the third and fourth cycles of the PROGRAM command are represented. The PROGRAM command is followed by checking of the status register data polling bit. 2. PA is the address of the memory location to be programmed. PD is the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit [DQ7]). 4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled Write AC Characteristics, and CE#-Controlled Write AC Characteristics. 5. For tWHWH1 timing details, see the Program/Erase Characteristics table. 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Write AC Characteristics Figure 22: Chip/Block Erase AC Timing tWC A[MAX:0] 555h 2AAh 555h 555h tAS 555h BAh1 2AAh tAH tCH tCS CE# tGHWL OE# tWP tWPH WE# tDS DQ[15:0] AAh 55h 80h AAh 55h 10h/ 30h tDH Notes: 1. For a DIE ERASE command, the address is 555h, and the data is 10h; for a BLOCK ERASE command, the address is BAd, and the data is 30h. 2. BAd is the block address. 3. See the following tables for timing details: Read AC Characteristics, WE#-Controlled Write AC Characteristics, and CE#-Controlled Write AC Characteristics. 4. For tWHWH1 timing details, see the Program/Erase Characteristics table. Figure 23: Accelerated Program AC Timing VPP/WP# VHH VIL or VIH tVHVPP CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 70 tVHVPP Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Data Polling/Toggle AC Characteristics Data Polling/Toggle AC Characteristics Table 35: Data Polling/Toggle AC Characteristics Note 1 applies to entire table Symbol Parameter Legacy JEDEC Min Max Unit Address setup time to CE# or OE# LOW tASO tAXGL 15 - ns Address hold time from OE# or CE# HIGH tAHT tGHAX, tEHAX 0 - ns CE# HIGH time tEPH tEHEL2 20 - ns OE# HIGH time tOPH tGHGL2 20 - ns WE# HIGH to OE# LOW (toggle and data polling) tOEH tWHGL2 10 - ns Note: 1. Sampled only; not 100% tested. Figure 24: Data Polling AC Timing tCH tCE tHZ/tDF CE# tOE tOPH OE# tOEH WE# DQ7 Data DQ7# DQ7# Valid DQ7 Data DQ[6:0] Data Output flag Output flag Valid DQ[6:0] Data tBUSY RY/BY# Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. DQ7 returns a valid data bit when the PROGRAM or ERASE command has completed. 2. See the following tables for timing details: Read AC Characteristics and Data Polling/ Toggle AC Characteristics. 71 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Data Polling/Toggle AC Characteristics Figure 25: Toggle/Alternative Toggle Bit Polling AC Timing A[MAX:0] tAHT tASO CE# tOEH tAHT tASO WE# tOPH tEPH tOPH OE# tDH DQ6/DQ2 tOE Data Toggle tCE Toggle Toggle Stop toggling Output Valid tBUSY RY/BY# Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. DQ6 stops toggling when the PROGRAM or ERASE command has completed. DQ2 stops toggling when the DIE ERASE or BLOCK ERASE command has completed. 2. See the following tables for timing details: Read AC Characteristics and Data Polling/ Toggle AC Characteristics. 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Program/Erase Characteristics Program/Erase Characteristics Table 36: Program/Erase Characteristics Notes 1 and 2 apply to entire table Buffer Size Byte Word Min Typ Max Unit Notes Block erase (128KB) - - - - 200 1100 ms - Die erase - - - - 208 - s - Erase suspend latency time - - - - - 20 s - Erase or erase resume to suspend - - - - 100 - s 3, 4 Accelerated die erase - - - - 190 - s - - - - - 25 200 s - 32 - 32 - 92 460 s - 64 - 64 - 117 600 s - 128 - 128 - 171 900 s - 256 - 256 - 285 1500 s - 512 - 512 - 512 2000 s - 32 - 1 - 2.88 14.38 s - 64 - 1 - 1.83 9.38 s - 128 - 1 - 1.34 7.03 s - 256 - 1 - 1.11 5.86 s - 512 - 1 - 1.0 3.90 s - Accelerated full buffer program time - - - - 410 - s - Program suspend latency time - - - - - 15 s - Set nonvolatile protection bit time - - - - 25 320 s - Clear nonvolatile protection bit time - - - - 80 1100 ms - Blank check: main block - - - - 3.2 - ms - CRC check time: main block - - - - 5 - ms - CRC check time: full die (1Gb) - - - - 10 - s - PROGRAM/ERASE cycles (per block) - - - 100,000 - - cycles - Parameter Erase Program Single-word program Buffer Program Word write to buffer program (tWHWH1) Effective write to buffer program per word (tWHWH1) Nonvolatile protection Blank Check, CRC, and Program/Erase Endurance Notes: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. Typical values measured at room temperature and nominal voltages (VCC = 3V). 2. Typical and maximum values are sampled, but not 100% tested. 3. Erase to suspend is the time between an initial BLOCK ERASE or ERASE RESUME command and a subsequent ERASE SUSPEND command. 4. This typical value allows an ERASE operation to progress to completion--it is important to note that the algorithm might never finish if the ERASE operation is always suspended less than this specification. 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Package Dimensions Package Dimensions Figure 26: 64-Ball LBGA - 11mm x 13mm (Package Code: PC) Seating plane A 64X O0.60 Dimensions apply to solder balls postreflow on O0.50 SMD ball pads. 0.08 A Ball A1 ID (covered with SR) 8 7 6 5 4 3 2 Ball A1 ID 1 A B C 7 CTR D E 13 0.1 F G 1 TYP H 1.3 0.1 1.0 TYP 7 CTR 0.49 0.05 11 0.1 Note: CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 1. All dimensions are in millimeters. 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved. 2Gb: x16, 3V, MT28FW, Automotive Parallel NOR Revision History Revision History Rev. F -10/18 * Updated CFI Query System Interface Information table Rev. E - 5/18 * Added Important Notes and Warnings section for further clarification aligning to industry standards Rev. D - 9/17 * Updated BGA signal assignments to allow usage of unused balls Rev. C - 11/16 * Updated DC Voltage Characteristics table in DC Characteristics Rev. B - 10/16 * Updated legal status to Production * Updated Input/Output Capacitance table in Absolute Ratings and Operating Conditions section Rev. A - 05/16 * Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. CCMTD-1718347970-10367 mt28fw_2gb_automotive.pdf - Rev. F 10/18 EN 75 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2016 Micron Technology, Inc. All rights reserved.