OUTx
GNDOGNDI
INx
VCCO
VCCI Isolation
Capacitor
ENx
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
ISO734x Robust EMC, Low-Power, Quad-Channel Digital Isolators
1
1 Features
1• Signaling Rate: 25 Mbps
• Integrated Noise Filter on the Inputs
• Default Output High and Low Options
• Low Power Consumption, Typical ICC per Channel
at 1 Mbps:
– ISO7340x: 0.9 mA (5-V Supplies),
0.7 mA (3.3-V Supplies)
– ISO7341x: 1.2 mA (5-V Supplies),
0.9 mA (3.3-V Supplies)
– ISO7342x: 1.3 mA (5-V Supplies),
0.9 mA (3.3-V Supplies)
• Low Propagation Delay: 31 ns
Typical (5-V Supplies)
• 3.3-V and 5-V Level Translation
• Wide Temperature Range: –40°C to 125°C
• 70-KV/μs Transient Immunity,
Typical (5-V Supplies)
• Robust Electromagnetic Compatibility (EMC)
– System-level ESD, EFT, and Surge Immunity
– Low Emissions
• Operates from 3.3-V and 5-V Supplies
• Wide-Body SOIC-16 Package
• Safety-Related Certifications:
– 4242-VPK Basic Isolation per DIN V VDE V
0884-10 and DIN EN 61010-1
– 3-KVRMS Isolation for 1 minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 61010-1 End Equipment
Standards
– GB4943.1-2011 CQC Certified
2 Applications
• Optocoupler Replacement in:
– Industrial Fieldbus
– Profibus
– Modbus
– DeviceNet Data Buses
– Servo Control Interface
– Motor Control
– Power Supplies
– Battery Packs
3 Description
The ISO734x family of devices provides galvanic
isolation up to 3000 VRMS for 1 minute per UL 1577
and 4242 VPK per VDE V 0884-10. These devices
have four isolated channels comprised of logic input
and output buffers separated by a silicon dioxide
(SiO2) insulation barrier.
The ISO7340x device has four channels in forward
direction, the ISO7341x device has three forward and
one reverse-direction channels, and the ISO7342x
device has two forward and two reverse-direction
channels. In case of input power or signal loss, the
default output is low for devices with suffix Fand high
for devices without suffix F. See the Device
Functional Modes section for further details.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE
ISO7340C
SOIC (16) 10.30 mm × 7.50 mm
ISO7340FC
ISO7341C
ISO7341FC
ISO7342C
ISO7342FC
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VCCI and GNDI are supply and ground
connections respectively for the input
channels.
VCCO and GNDO are supply and ground
connections respectively for the output.
2
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Description (continued)......................................... 5
6 Pin Configuration and Functions......................... 6
7 Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information.................................................. 8
7.5 Power Ratings........................................................... 8
7.6 Insulation Specifications............................................ 9
7.7 Safety-Related Certifications................................... 10
7.8 Safety Limiting Values ............................................ 10
7.9 Electrical Characteristics—5-V Supply ................... 11
7.10 Supply Current Characteristics—5-V Supply........ 11
7.11 Electrical Characteristics—3.3-V Supply .............. 12
7.12 Supply Current Characteristics—3.3-V Supply..... 12
7.13 Switching Characteristics—5-V Supply................. 13
7.14 Switching Characteristics—3.3-V Supply.............. 13
7.15 Insulation Characteristics Curves ......................... 14
7.16 Typical Characteristics.......................................... 15
8 Parameter Measurement Information ................ 17
9 Detailed Description............................................ 19
9.1 Overview................................................................. 19
9.2 Functional Block Diagram....................................... 19
9.3 Feature Description................................................. 20
9.4 Device Functional Modes........................................ 21
10 Application and Implementation........................ 22
10.1 Application Information.......................................... 22
10.2 Typical Application................................................ 22
11 Power Supply Recommendations ..................... 26
12 Layout................................................................... 27
12.1 Layout Guidelines ................................................. 27
12.2 Layout Example .................................................... 27
13 Device and Documentation Support................. 28
13.1 Documentation Support ........................................ 28
13.2 Related Links ........................................................ 28
13.3 Receiving Notification of Documentation Updates 28
13.4 Community Resource............................................ 28
13.5 Trademarks........................................................... 28
13.6 Electrostatic Discharge Caution............................ 28
13.7 Glossary................................................................ 28
14 Mechanical, Packaging, and Orderable
Information........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (August 2016) to Revision G Page
• Deleted Reinforced from the data sheet title.......................................................................................................................... 1
• the production tested note for the UL VRMS value from the Safety-Related Certifications ................................................... 10
Changes from Revision E (April 2015) to Revision F Page
• Changed the minimum air gap (clearance) parameter (L(I01)) to the external clearance parameter.................................... 9
• Changed the minimum external tracking (creepage) parameter (L(I02)) to the external creepage parameter...................... 9
• Changed the typ value for the enable propagation delay, high impedance-to-high output parameter of the FC
devices and the typ value for the enable propagation delay, high impedance-to-low output parameter of the C
devices from 16 to 16000 in the Switching Characteristics—3.3-V Supply table ................................................................ 13
• Added the Receiving Notification of Documentation Updates section ................................................................................ 28
Changes from Revision D (March 2015) to Revision E Page
• Deleted "(VDE V0884-10):2006-12" and "(VDE 0411-1:2011-07)" from the Features Safety and Regulatory Approvals:.... 1
• Deleted "(Approval Pending)" From the CSA Component Acceptance list item in the Features........................................... 1
• Deleted IEC from the section title: Insulation and Safety-Related Specifications for DW-16 Package ................................ 9
• Changed the TEST Conditions of CTI in Insulation and Safety-Related Specifications for DW-16 Package........................ 9
• Changed the Test Conditions of VISO in Insulation Characteristics ....................................................................................... 9
• Changed column CSA in the Safety-Related Certifications table ....................................................................................... 10
• Changed From: VCC1 To: VCCI in Switching Characteristics Test Circuit and Voltage Waveforms ..................................... 17
• Changed From: VCC1 To: VCCI and From: VCC2 To: VCCO in Common-Mode Transient Immunity Test Circuit..................... 18
3
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
www.ti.com
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
Changes from Revision C (December 2014) to Revision D Page
• Changed the DIN V VDE 0884-10 number in the Features Safety and Regulatory Approvals:............................................ 1
• Added "(Approval Pending)" to the CSA Component Acceptance list item in the Features.................................................. 1
• Deleted "All Agencies Approvals Planned" from the Features Safety and Regulatory Approvals:........................................ 1
• Changed the Simplified Schematic: VCC1 To VCCI, VCC2 to VCCO and GND1 to GNDI, GND2 to GNDO. Added Notes
1 and 2.................................................................................................................................................................................... 1
• Added Note: "Maximum voltage must not exceed 6 V:" to Absolute Maximum Ratings........................................................ 7
• Added "DT1" to the Minimum internal gap in Insulation and Safety-Related Specifications for DW-16 Package................. 9
• Changed VIORM "Maximum repetitive peak voltage" To: "Maximum repetitive peak isolation voltage per DIN V VDE V
0884-10" in Insulation Characteristics ................................................................................................................................... 9
• Changed VIOTM From: "DIN V VDE 0884-10 " To: "DIN V VDE V 0884-10" in Insulation Characteristics ............................ 9
• Changed VIOSM "Maximum surge voltage per DIN V VDE 0884-10 " To: "Maximum surge isolation voltage per DIN V
VDE V 0884-100" in Insulation Characteristics ..................................................................................................................... 9
• Changed VIOSM Test Conditions in Insulation Characteristics ............................................................................................... 9
• Changed VPR From: "DIN V VDE 0884-10 " To: "DIN V VDE V 0884-10" in Insulation Characteristics ............................... 9
• Changed RSTest Conditions in Insulation and Safety-Related Specifications for DW-16 Package From: TSTo: TS=
150°C ..................................................................................................................................................................................... 9
• Changed the Safety-Related Certifications table ................................................................................................................ 10
• Changed title From: " IEC Safety Limiting Values" To: Safety Limiting Values ................................................................... 10
• Changed MIN value for VOH in the Electrical Characteristics From: VCCx - 0.5 To: VCCO - 0.5 ............................................ 11
• Changed VCCx To VCCO in Note 1 of the Electrical Characteristics....................................................................................... 11
• Changed MIN value for VOH in the Electrical Characteristics From: VCCx - 0.5 To: VCCO - 0.5 ............................................ 12
• Changed VCCx To VCCO in Note 1 of the Electrical Characteristics....................................................................................... 12
• Changed Function Table Header information From: INPUT-SIDE VCC To: VCCIand OUTPUT-SIDE VCC To: VCCO ......... 21
• Changed Device I/O Schematics From: VCC To: VCCI on the inputs and VCCO on Output and Enabled............................... 21
• Moved Typical ISO7340x Circuit Hook-up to Typical ISO7342x-Q1 Circuit Hook-up from the Design Requirements
section to the Detailed Design Procedure section................................................................................................................ 23
Changes from Revision B (November 2014) to Revision C Page
• Changed the Handling Ratings table to ESD Ratings............................................................................................................ 7
• Changed Minimum internal gap MIN value in Insulation and Safety-Related Specifications for DW-16 Package
From: 0.014 mm To: 13.5 µm................................................................................................................................................. 9
• Changed Minimum internal gap MIN value in Insulation and Safety-Related Specifications for DW-16 Package
From: 13.5 µm To: 13 µm....................................................................................................................................................... 9
• Delete text "per DIN V VDE 0884-10" from VIORM in the table in section Insulation Characteristics ..................................... 9
• Changed From: VPEAK To VPK in the UNIT column of the table in section Insulation Characteristics.................................... 9
• Added VIOSM to the table in section Insulation Characteristics .............................................................................................. 9
• Changed the table in Safety-Related Certifications section - removed text "Certified according to", "Approved
under", "Recognized under", changed "pending" To: "planned" .......................................................................................... 10
• Changed Maximum Repetitive Peak Voltage, 1414 VPK To: Maximum surge voltage , 6000 VPK in the VDE column
of the table in section Safety-Related Certifications............................................................................................................. 10
• Changed the ICC2, Supply current, DC to 1 Mbps TYP value From: 3 To 3.2 mA .............................................................. 11
• Changed the ICC2, Supply current, 10 Mbps TYP value From: 5.1 To 5.6 mA .................................................................... 11
• Changed the ICC2, Supply current, 25 Mbps TYP value From: 8.6 To 9.3 mA .................................................................... 11
• Changed the ICC1, Supply current, 10 Mbps TYP value From: 0.8 To 0.9 mA .................................................................... 12
• Changed the ICC2, Supply current, 10 Mbps TYP value From: 0.3.6 To 3.9 mA ................................................................. 12
• Changed the ICC2, Supply current, 25 Mbps TYP value From: 5.9 To 6.3 mA .................................................................... 12
4
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
• Added ISO7340 Supply Current vs Data Rate (15-pF Load) and ISO7340x Supply Current vs Data Rate (No Load)....... 15
• Changed ISO7341x Supply Current vs Data Rate (No Load).............................................................................................. 15
Changes from Revision A (Octoberr 2014) to Revision B Page
• Added Test Condition to IEC 60664-1 Ratings Table: Rated mains voltage ≤1000 VRMS ................................................... 9
• Changed the RIO Test Conditions in Insulation and Safety-Related Specifications for DW-16 Package : Added TA=
25°C at MIN = 1012 ................................................................................................................................................................. 9
• Changed the RIO Test Conditions in Insulation and Safety-Related Specifications for DW-16 Package : Added VIO =
500 V, 100°C ≤TA≤125°C at MIN = 1011 ............................................................................................................................. 9
• Added ISO7341x Supply Current vs Data Rate (15-pF Load) and ISO7341x Supply Current vs Data Rate (No Load)..... 15
Changes from Original (September 2014) to Revision A Page
• Changed From a 1 page Product Preview to the full datasheet ........................................................................................... 1
• Changed the Simplified Schematic, added ground symbols.................................................................................................. 1
5
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
www.ti.com
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
5 Description (continued)
Used in conjunction with isolated power supplies, these devices help prevent noise currents on a data bus or
other circuits from entering the local ground and interfering with or damaging sensitive circuitry. The ISO734x
device has integrated noise filter for harsh industrial environment where short noise pulses may be present at the
device input pins. The ISO734x device has TTL input thresholds and operates from 3-V to 5.5-V supply levels.
Through innovative chip design and layout techniques, electromagnetic compatibility of the ISO734x family of
devices has been significantly enhanced to enable system-level ESD, EFT, surge, and emissions compliance.
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
INA
GND2
GND2
INB
OUTC
OUTA
INC
OUTB
IND
EN2EN1
GND1
GND1
VCC1
OUTD
VCC2
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
EN1
INA
GND1
INB
INC
OUTD
GND1
VCC1
GND2
GND2
OUTA
OUTC
OUTB
EN2
IND
VCC2
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
NC
INA
GND1
GND2
GND2
INB
INC
OUTA
OUTC
OUTB
EN
IND OUTD
GND1
VCC1 VCC2
6
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
6 Pin Configuration and Functions
DW Package
16-Pin SOIC
ISO7340x Top View
DW Package
16-Pin SOIC
ISO7341x Top View
DW Package
16-Pin SOIC
ISO7342x Top View
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
ISO7340x ISO7341x ISO7342x
EN 10 — — I Output enable. All output pins are enabled when EN is high or
disconnected and disabled when EN is low.
EN1 — 7 7 I Output enable 1. Output pins on side-1 are enabled when EN1 is
high or disconnected and disabled when EN1 is low.
EN2 — 10 10 I Output enable 2. Output pins on side-2 are enabled when EN2 is
high or disconnected and disabled when EN2 is low.
GND1 2 2 2 — Ground connection for VCC1
8 8 8
GND2 9 9 9 — Ground connection for VCC2
15 15 15
INA 3 3 3 I Input, channel A
INB 4 4 4 I Input, channel B
INC 5 5 12 I Input, channel C
IND 6 11 11 I Input, channel D
NC 7 — — — No connect pins are floating with no internal connection
OUTA 14 14 14 O Output, channel A
OUTB 13 13 13 O Output, channel B
OUTC 12 12 5 O Output, channel C
OUTD 11 6 6 O Output, channel D
VCC1 1 1 1 — Power supply, VCC1
VCC2 16 16 16 — Power supply, VCC2
7
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
www.ti.com
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V.
7 Specifications
7.1 Absolute Maximum Ratings
See (1)
MIN MAX UNIT
VCC Supply voltage(2) VCC1, VCC2 –0.5 6 V
Voltage INx, OUTx, ENx –0.5 VCC + 0.5(3) V
IOOutput current ±15 mA
TJMaximum junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2) ±1500 V
(1) To maintain the recommended operating conditions for TJ, see the Thermal Information table.
7.3 Recommended Operating Conditions MIN NOM MAX UNIT
VCC1, VCC2 Supply voltage 3 5.5 V
IOH High-level output current –4 mA
IOL Low-level output current 4 mA
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0 0.8 V
tui Input pulse duration 40 ns
1 / tui Signaling rate 0 25 Mbps
TJJunction temperature(1) 136 °C
TAAmbient temperature –40 25 125 °C
8
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Thermal Information
THERMAL METRIC(1) ISO734x
UNITDW (SOIC)
16 PINS
RθJA Junction-to-ambient thermal resistance 78.4 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 41 °C/W
RθJB Junction-to-board thermal resistance 43 °C/W
ψJT Junction-to-top characterization parameter 15.6 °C/W
ψJB Junction-to-board characterization parameter 42.5 °C/W
RθJC(bottom) Junction-to-case(bottom) thermal resistance n/a °C/W
7.5 Power Ratings
VCC1 = VCC2 = 5.5 V, TJ= 150°C, CL= 15 pF, Input a 12.5-MHz 50% duty cycle square wave
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PDMaximum power dissipation by both sides of ISO7340x 92 mWPD1 Maximum power dissipation by side-1 of ISO7340x 24
PD2 Maximum power dissipation by side-2 of ISO7340x 68
PDMaximum power dissipation by both sides of ISO7341x 102 mWPD1 Maximum power dissipation by side-1 of ISO7341x 42
PD2 Maximum power dissipation by side-2 of ISO7341x 60
PDMaximum power dissipation by both sides of ISO7342x 111 mWPD1 Maximum power dissipation by side-1 of ISO7342x 55.5
PD2 Maximum power dissipation by side-2 of ISO7342x 55.5
9
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
www.ti.com
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device
7.6 Insulation Specifications
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest terminal-to-terminal distance through air >8 mm
CPG External creepage(1) Shortest terminal-to-terminal distance across the
package surface >8 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >13 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 >400 V
Material group II
Overvoltage Category Rated mains voltage ≤300 VRMS I–IV
Rated mains voltage ≤600 VRMS I–III
Rated mains voltage ≤1000 VRMS I-II
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1414 VPK
VIOTM Maximum transient isolation voltage VTEST = VIOTM;
t = 60 s (qualification); t = 1 s (100% production) 4242 VPK
VIOSM Maximum surge isolation voltage(3) Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.3 × VIOSM = 7800 VPK (qualification) 6000 VPK
qpd Apparent charge(4)
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 1697 VPK, tm= 10 s ≤5
pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 2262 VPK, tm= 10 s ≤5
Method b1: At routine test (100% production) and
preconditioning (type test) Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM = 2651 VPK, tm= 1 s (100%
production)
≤5
CIO Barrier capacitance, input to output(5) VIO = 0.4 sin (2πft), f = 1 MHz 2.4 pF
RIO Isolation resistance, input to output(5) VIO = 500 V, TA= 25°C >1012
ΩVIO = 500 V, 100°C ≤TA≤x°C >1011
VIO = 500 V at TS= 150°C >109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 3000 VRMS, t = 60 s (qualification);
VTEST = 1.2 × VISO = 3600 VRMS, t = 1 s (100%
production) 3000 VRMS
10
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
7.7 Safety-Related Certifications
VDE CSA UL CQC
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 and DIN EN 61010-
1 (VDE 0411-1):2011-07
Approved under CSA Component
Acceptance Notice 5A, IEC 60950-1, and
IEC 61010-1
Recognized under UL 1577
Component Recognition
Program
Certified according to
GB4943.1-2011
Basic Insulation;
Maximum Transient Overvoltage, 4242 VPK;
Maximum Surge Isolation Voltage, 6000 VPK;
Maximum Repetitive Peak Isolation Voltage,
1414 VPK
800 VRMS Basic Insulation and 400 VRMS
Reinforced Insulation working voltage per
CSA 60950-1-07+A1+A2 and IEC 60950-1
2nd Ed.+A1+A2;
300 VRMS Basic Insulation working voltage
per CSA 61010-1-12 and IEC 61010-1 3rd
Ed.
Single protection, 3000 VRMS Reinforced Insulation, Altitude ≤
5000 m, Tropical Climate, 250
VRMS maximum working voltage
Certificate number: 40016131 Master contract number: 220991 File number: E181974 Certificate number:
CQC15001121716
7.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISSafety input, output, or supply
current
RθJA = 78.4 °C/W, VI= 5.5 V, TJ= 150°C, TA= 25°C,
see Figure 1 290 mA
RθJA = 78.4 °C/W, VI= 3.6 V, TJ= 150°C, TA= 25°C,
see Figure 1 443
TSSafety temperature 150
The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that
of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
11
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
www.ti.com
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
(1) VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.
(2) Measured from input pin to ground.
7.9 Electrical Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 14 VCCO(1) – 0.5 4.7 V
IOH = –20 μA; see Figure 14 VCCO(1) – 0.1 5
VOL Low-level output voltage IOL = 4 mA; see Figure 14 0.2 0.4 V
IOL = 20 μA; see Figure 14 0 0.1
VI(HYS) Input threshold voltage
hysteresis 480 mV
IIH High-level input current VIH = VCC at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
CMTI Common-mode transient
immunity VI= VCC or 0 V; see Figure 17 25 70 kV/μs
CIInput capacitance(2) VI= VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V 3.4 pF
7.10 Supply Current Characteristics—5-V Supply
All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 5 V ± 10% (over
recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY
CURRENT MIN TYP MAX UNIT
ISO7340x
Supply current
EN = 0 V Disable ICC1 0.6 1.4
mA
ICC2 0.4 0.8
DC Signal: VI= VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL= 15 pF
DC to 1 Mbps ICC1 0.6 1.4
ICC2 3.2 4.8
10 Mbps ICC1 1.4 2.3
ICC2 5.6 7.1
25 Mbps ICC1 2.7 4
ICC2 9.3 12
ISO7341x
Supply current
EN1 = EN2 = 0 V Disable ICC1 0.8 1.8
mA
ICC2 0.7 1.3
DC Signal: VI= VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL= 15 pF
DC to 1 Mbps ICC1 2 3.2
ICC2 2.9 4.4
10 Mbps ICC1 3.2 4.5
ICC2 4.9 6.5
25 Mbps ICC1 5 7
ICC2 7.8 11
ISO7342x
Supply current
EN1 = EN2 = 0 V Disable ICC1, ICC2 0.7 1.6
mA
DC Signal: VI= VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL= 15 pF
DC to 1 Mbps ICC1, ICC2 2.5 4
10 Mbps ICC1, ICC2 4.1 5.6
25 Mbps ICC1, ICC2 6.4 9
12
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
(1) VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.
7.11 Electrical Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 14 VCCO(1) – 0.5 3 V
IOH = –20 μA; see Figure 14 VCCO(1) – 0.1 3.3
VOL Low-level output voltage IOL = 4 mA; see Figure 14 0.2 0.4 V
IOL = 20 μA; see Figure 14 0 0.1
VI(HYS) Input threshold voltage
hysteresis 450 mV
IIH High-level input current VIH = VCC at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
CMTI Common-mode transient
immunity VI= VCC or 0 V; see Figure 17 25 50 kV/μs
7.12 Supply Current Characteristics—3.3-V Supply
All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 3.3 V ± 10% (over
recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY
CURRENT MIN TYP MAX UNIT
ISO7340x
Supply current
EN = 0 V Disable ICC1 0.4 0.7
mA
ICC2 0.3 0.6
DC Signal: VI= VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL= 15 pF
DC to 1 Mbps ICC1 0.4 0.7
ICC2 2.3 3.6
10 Mbps ICC1 0.9 1.3
ICC2 3.9 5.1
25 Mbps ICC1 1.6 2.4
ICC2 6.3 8
ISO7341x
Supply current
EN1 = EN2 = 0 V Disable ICC1 0.6 1
mA
ICC2 0.5 0.8
DC Signal: VI= VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL= 15 pF
DC to 1 Mbps ICC1 1.4 2.3
ICC2 2.2 3.2
10 Mbps ICC1 2.2 3
ICC2 3.4 4.5
25 Mbps ICC1 3.3 4.7
ICC2 5.2 7.2
ISO7342x
Supply current
EN1 = EN2 = 0 V Disable ICC1, ICC2 0.5 0.9
mA
DC Signal: VI= VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL= 15 pF
DC to 1 Mbps ICC1, ICC2 1.8 2.8
10 Mbps ICC1, ICC2 2.8 4
25 Mbps ICC1, ICC2 4.3 5.8
13
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
www.ti.com
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
(4) The enable signal rate should be ≤43 Kbps.
7.13 Switching Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 14 20 31 58 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 4 ns
tsk(o)(2) Channel-to-channel output skew time Same-direction Channels 2.5 ns
Opposite-direction Channels 17 ns
tsk(pp)(3) Part-to-part skew time 23 ns
trOutput signal rise time See Figure 14 2.1 ns
tfOutput signal fall time 1.7 ns
tPHZ Disable propagation delay, high-to-high impedance output
See Figure 15
7 13 ns
tPLZ Disable propagation delay, low-to-high impedance output 7 13 ns
tPZH Enable propagation delay, high
impedance-to-high output ISO734xC 7 13 ns
ISO734xFC 15000 23000(4)
tPZL Enable propagation delay, high
impedance-to-low output ISO734xC 15000 23000(4) ns
ISO734xFC 7 13
tfs Fail-safe output delay time from input power loss See Figure 16 9.4 μs
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
(4) The enable signal rate should be ≤45 Kbps.
7.14 Switching Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 14 22 35 66
ns
PWD(1) Pulse width distortion |tPHL – tPLH| 2.5
tsk(o) (2) Channel-to-channel output skew time Same-direction Channels 3
Opposite-direction Channels 16
tsk(pp) (3) Part-to-part skew time 28
trOutput signal rise time See Figure 14 2.8 ns
tfOutput signal fall time 2.1
tPHZ Disable propagation delay, high-to-high impedance output
See Figure 15
9 18
ns
tPLZ Disable propagation delay, low-to-high impedance output 9 18
tPZH Enable propagation delay, high impedance-
to-high output ISO734xC 9 18
ISO734xFC 16000 24000(4)
tPZL Enable propagation delay, high impedance-
to-low output ISO734xC 16000 24000(4)
ISO734xFC 9 18
tfs Fail-safe output delay time from input power loss See Figure 16 9.4 μs
14
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
7.15 Insulation Characteristics Curves
Figure 1. Thermal Derating Curve for Limiting Current per VDE
Data Rate (Mbps)
Supply Current (mA)
0 5 10 15 20 25 30
0
1
2
3
4
5
6
7
D001
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
Data Rate (Mbps)
Supply Current (mA)
0 5 10 15 20 25 30
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
D002
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
Data Rate (Mbps)
Supply Current (mA)
0 5 10 15 20 25 30
0
1
2
3
4
5
6
7
8
9
D001
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
Data Rate (Mbps)
Supply Current (mA)
0 5 10 15 20 25 30
0
1
2
3
4
5
6
D001
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
Data Rate (Mbps)
Supply Current (mA)
0 5 10 15 20 25 30
0
1
2
3
4
5
6
7
8
9
10
D001
ICC2 at 5 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC1 at 3.3 V
Data Rate (Mbps)
Supply Current (mA)
0 5 10 15 20 25 30
0
1
2
3
4
5
6
D001
ICC2 at 5 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC1 at 3.3 V
15
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
www.ti.com
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
7.16 Typical Characteristics
TA= 25°C CL= 15 pF
Figure 2. ISO7340x Supply Current vs Data Rate
(15-pF Load)
TA= 25°C CL= No Load
Figure 3. ISO7340x Supply Current vs Data Rate
(No Load)
TA= 25°C CL= 15 pF
Figure 4. ISO7341x Supply Current vs Data Rate
(15-pF Load)
TA= 25°C CL= No Load
Figure 5. ISO7341x Supply Current vs Data Rate
(No Load)
TA= 25°C CL= 15 pF
Figure 6. ISO7342x Supply Current vs Data Rate
(15-pF Load)
TA= 25°C CL= No Load
Figure 7. ISO7342x Supply Current vs Data Rate
(No Load)
Free-Air Temperature (qC)
Input Glitch Suppression Time (ns)
-40 -5 30 65 100 135
15
17
19
21
23
25
27
29
D007
tGS at 3.3 V
tGS at 5 V
Free-Air Temperature (qC)
Power Supply Under-Voltage Threshold (V)
-50 0 50 100 150
2.32
2.34
2.36
2.38
2.4
2.42
2.44
2.46
D005
VCC Rising
VCC Falling
Free-Air Temperature (qC)
Propagation Delay Time (ns)
-40 -20 0 20 40 60 80 100 120 140
28
30
32
34
36
38
40
42
D006
tPHL at 3.3 V
tPHL at 5 V
tPLH at 3.3 V
tPLH at 5 V
High-Level Output Current (mA)
High-Level Output Voltage (V)
-15 -10 -5 0
0
1
2
3
4
5
6
D003
VCC at 3.3 V
VCC at 5 V
Low-Level Output Current (mA)
Low-Level Output Voltage (V)
0 5 10 15
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
D004
VCC at 3.3 V
VCC at 5 V
16
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
Typical Characteristics (continued)
TA= 25°C
Figure 8. High-Level Output Voltage vs High-level Output
Current
TA= 25°C
Figure 9. Low-Level Output Voltage vs Low-Level Output
Current
Figure 10. Power Supply Undervoltage Threshold vs Free-
Air Temperature Figure 11. Propagation Delay Time vs Free-Air Temperature
Figure 12. Input Glitch Suppression Time vs Free-Air
Temperature
TA= 25°C
Figure 13. Output Jitter vs Data Rate
Input
Generator
See Note A 50 Ω
OUT
RL= 1 kΩ
EN
VO
V
I
IN
0 V
CL
1%
±
See
Note B
0 V
V
O
VI
0.5 V
50%
50 Ω
OUT
RL= 1 kΩ
EN
V
O
VI
IN
3 V
CL1%
±
0 V
0 V
VI
50% 0.5 V
tPZH
V
O
VOH
tPHZ
V /2
CC V /2
CC
VCC
tPZL
VCC
V /2
CC
VCC
tPLZ
VCC
V /2
CC
VOL
Input
Generator
See Note A
See
Note B
ISOLATION BARRIER
ISOLATION BARRIER
IN
ISOLATION BARRIER
OUT
VO
CL
Input
Generator
See Note A
50 Ω
VI
See Note B 10%
90%
50%
0 V
50%
VIV /2
CC
VO
tPLH
VOH
tPHL
trtf
VCCI
VOL
V /2
CC
17
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
www.ti.com
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
8 Parameter Measurement Information
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle, tr≤3
ns, tf≤3ns, ZO= 50 Ω. At the input, 50 Ωresistor is required to terminate Input Generator signal. It is not needed in
actual application.
B. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 14. Switching Characteristics Test Circuit and Voltage Waveforms
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤10 kHz, 50% duty cycle,
tr≤3 ns, tf≤3 ns, ZO= 50 Ω.
B. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 15. Enable/Disable Propagation Delay Time Test Circuit and Waveform
Isolation Barrier
C = 0.1 µF ±1%
IN
VOH or VOL
OUT
VCCI
+–
VCM
VCCO
GNDOGNDI
S1
+
–
Pass-fail criteria –
output must remain
stable.
CL
See Note A
C = 0.1 µF ±1%
VO
OUT
IN
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
CC
See Note A
CL
VI
0 V
tfs
fs high
VO
VI2.7 V
50%
VCC VCC
VOL
VOH
fs low
ISOLATION BARRIER
18
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
Parameter Measurement Information (continued)
A. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 16. Failsafe Delay Time Test Circuit and Voltage Waveforms
A. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 17. Common-Mode Transient Immunity Test Circuit
OSC
PWM VREF LPF
VREF DCL
OUT
IN
0
1S
Isolation Barrier
Low t Frequency
Channel
(DC...100 kbps)
High t Frequency
Channel
(100 kbps...25 Mbps)
Polarity and Threshold
Selection
Polarity and Threshold Selection
19
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
www.ti.com
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
9 Detailed Description
9.1 Overview
The isolator in Figure 18 is based on a capacitive isolation-barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to 25
Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC.
In principle, a single-ended input signal entering the HF channel is split into a differential signal through the
inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses,
which then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator
can be either above or below the common-mode voltage VREF depending on whether the input bit transitioned
from 0 to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic
(DCL) at the output of the HF channel comparator measures the durations between signal transients. If the
duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency
signal), the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter
(LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
9.2 Functional Block Diagram
Figure 18. Conceptual Block Diagram of a Digital Capacitive Isolator
20
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
(1) See the Safety-Related Certifications section for detailed isolation ratings.
9.3 Feature Description
The ISO734x family of devices are available in multiple channel configurations and default output state options to
enable wide variety of application uses.
PART NUMBER CHANNEL DIRECTION RATED ISOLATION MAXIMUM DATA RATE DEFAULT OUTPUT
ISO7340C 4 Forward,
0 Reverse
3000 VRMS / 4242 VPK(1) 25 Mbps
High
ISO7340FC Low
ISO7341C 3 Forward,
1 Reverse High
ISO7341FC Low
ISO7342C 2 Forward,
2 Reverse High
ISO7342FC Low
9.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge, and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO734x
family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
INx
5 Am
500 W
Input (Devices Without Suffix F)
Output
VCCI VCCI
ENx
500 W
Enable
VCCO VCCO VCCO
VCCI
5 Am
OUTx
VCCO
40 W
INx
5 Am
500 W
Input (Devices With Suffix F)
VCCI VCCI
VCCI VCCI
VCCO
21
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
www.ti.com
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥3 V); PD = Powered down (VCC ≤2.1 V); X = Irrelevant; H =
High level; L = Low level ; Z = High Impedance
(2) In fail-safe condition, output defaults to high level
(3) In fail-safe condition, output defaults to low level
9.4 Device Functional Modes
Table 1 lists the functional modes for the ISO734x family of devices.
Table 1. Function Table(1)
VCCI VCCO INPUT
(INx) OUTPUT ENABLE
(ENx)
OUTPUT
(OUTx)
ISO734xC ISO734xFC
PU PU
H H or Open H H
L H or Open L L
X L Z Z
Open H or Open H(2) L(3)
PD PU X H or Open H(2) L(3)
X PU X L Z Z
X PD X X Undetermined Undetermined
9.4.1 Device I/O Schematics
Figure 19. Device I/O Schematics
14
13
INA
OUTD
3
4
5
6
EN1EN2 710
INB
12
11
OUTC
IND
INC
DVDD
DGND
2
GAIN1 24
25
26
GAIN0
SPEED
PWDN
AIN3+
AIN3±
AIN4+
A0
A1
AIN1+
AIN1±
AIN2+
SCLK
DOUT
REF+
REF±
AIN4±
1
VCC1
16 VCC2
2,89,15 GND1GND2
23
20
19
28
8
7
27
P3.1
P3.0
CLK
SOMI
13
11
12
14
4
2
MSP430
F2132
DVss
DVcc
14
13
OUTD
3
4
5
6
NCEN 710
12
11
OUTC
IND
INC
1
VCC1
16 VCC2
2,89,15 GND1GND2
ISO7340
ISO7341
5VISO
5VISO
3.3 V
3.3 V
P3.7
P3.6
18
17
3.3 V
22
AVDD
AGND
21
5VISO
AIN2±
13
14
17
16
15
11
12
18
INA
INBOUTB
OUTA
OUTA
OUTB
1
5VISO 5VISO
Thermo
couple
Current
shunt
RTD
Bridge
XOUT
XIN
5
6
P3.4
15 P3.5 16
ADS1234
ISO-BARRIER
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
22
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The ISO734x family of devices use single-ended TTL-logic switching technology. The supply voltage range is
from 3 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that
because of the single-ended design structure, digital isolators do not conform to any specific interface standard
and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed
between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the
interface type or standard.
10.2 Typical Application
10.2.1 Isolated Data Acquisition System for Process Control
The ISO734x family of devices combined with Texas Instruments' precision analog-to-digital converter and mixed
signal micro-controller can create an advanced isolated data acquisition system as shown in Figure 20.
Figure 20. Isolated Data-Acquisition System for Process Control
ISO7340
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INA
INB
INC
IND
OUTA
OUTB
OUTC
OUTD
GND2
VCC2
0.1 µF
2 mm max
from VCC2
EN
GND2
NC
GND1
2 mm max
from VCC1
GND1
0.1 µF
VCC1
ISO7341
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INA
INB
INC
OUTD
OUTA
OUTB
OUTC
IND
GND2
VCC2
0.1 µF
2 mm max
from VCC2
EN2
GND2
EN1
GND1
2 mm max
from VCC1
GND1
0.1 µF
VCC1
23
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
www.ti.com
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
Typical Application (continued)
10.2.1.1 Design Requirements
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO734x family of devices only requires two external bypass capacitors to operate.
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Typical Supply Current Equations
For the equations in this section, the following is true:
• ICC1 and ICC2 are typical supply currents measured in mA
• f is data rate measured in Mbps
• CLis the capacitive load measured in pF
10.2.1.2.1.1 ISO7340x
At VCC1 = VCC2 = 5 V:
ICC1 = 0.54366 + (0.0873 × f) (1)
ICC2 = 2.74567 + (0.08433 × f) + (0.01 × f × CL) (2)
At VCC1 = VCC2 = 3.3 V:
ICC1 = 0.3437 + (0.04922 × f) (3)
ICC2 = 2.1068 + (0.04374 × f) + (0.007045 × f × CL) (4)
10.2.1.2.1.2 ISO7341x
At VCC1 = VCC2 = 5 V:
ICC1 = 1.7403 + (0.1006 × f) + (0.001711 × f × CL) (5)
ICC2 = 2.502 + (0.09629 × f) + (0.00687 × f × CL) (6)
At VCC1 = VCC2 = 3.3 V:
ICC1 = 1.2915 + (0.046 × f) + (0.00185 × f × CL) (7)
ICC2 = 1.8833 + (0.0566 × f) + (0.004514 × f × CL) (8)
10.2.1.2.1.3 ISO7342x
At VCC1 = VCC2 = 5 V:
ICC1, ICC2 = 2.1254 + (0.08694 × f) + (0.004868 × f × CL) (9)
At VCC1 = VCC2 = 3.3 V:
ICC1, ICC2 = 1.5912 + (0.0410 × f) + (0.003785 × f × CL) (10)
Figure 21. Typical ISO7340x Circuit Hook-up Figure 22. Typical ISO7341x Circuit Hook-up
ISO7342
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INA
INB
INC
OUTD
OUTA
OUTB
OUTC
IND
GND2
VCC2
0.1 µF
2 mm max
from VCC2
EN2
GND2
EN1
GND1
2 mm max
from VCC1
GND1
0.1 µF
VCC1
24
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
Typical Application (continued)
Figure 23. Typical ISO7342x Circuit Hook-up
10.2.1.3 Application Curves
The typical eye diagrams of the ISO734x family of devices indicate low jitter and a wide open eye at the
maximum data rate of 25 Mbps.
Figure 24. Eye Diagram at 25 Mbps, 5 V and 25°C Figure 25. Eye Diagram at 25 Mbps, 3.3 V and 25°C
VCC1 VCC2
GND1 GND2
OUTA
16
14
13
2, 8 9, 15
4
XOUT
XIN
5
6
2
MSP430
G2132
(14-PW)
INA
OUTD
1
3
4
5
6
ISO7341
DVss
DVCC
0.1 F
0.1 F 0.1 F
EN1 EN2
7 10
INB
12
11
OUTB
OUTC
IND
0.1 F
INC
SDI
P1.4
SCLK
SDO
9
6
7
8
4.7 k4.7 k
28
VBD
AGND
CH0
1, 22
CS
26
23
24
25
SCLK
SDI
20
SDO
ADS7953
CH15 5
BDGND
27
32
VA
31
REFP
2
MXO
3
AINP
REFM
30
VIN
GND
VOUT
2 6
4
REF5025
1 F
10 F
VS
0.1 F
MBR0520L
MBR0520L
1:1.33
0.1 F
3
1
D2
SN6501
D1
VCC
4, 5
2
GND
3.3 V
IN
EN GND
OUT
4 1
23
TLV70733 10 F
3.3VISO
10 F22 F
16 Analog
Inputs
ISO-BARRIER
25
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
www.ti.com
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
Typical Application (continued)
10.2.2 Typical Application for Module With 16 Inputs
The ISO7341x device and several other components from Texas Instruments can be used to create an isolated
serial peripheral interface (SPI) for input module with 16 inputs.
Figure 26. Isolated SPI for an Analog Input Module With 16 Inputs
10.2.2.1 Design Requirements
Refer to Isolated Data Acquisition System for Process Control for the design requirements.
10.2.2.2 Detailed Design Procedure
Refer to Isolated Data Acquisition System for Process Control for the detailed design procedures.
10.2.2.3 Application Curves
Refer to Isolated Data Acquisition System for Process Control for the application curves.
VCC1 VCC2
GND1 GND2
OUTA
16
14
12
2, 8 9, 15
P3.1
P3.0
UCA0TXD
UCA0RXD
11
15
16
12
4
XOUT
XIN
5
6
2
MSP430
F2132
INA
OUTD
1
3
5
4
6
ISO7342
DVSS
DVCC
0.1 F
0.1 F 0.1 F
EN1 EN2
7 10
INB 13
11
OUTB
INC
IND
16
0.1 F
OUTC
VCC
GND
15
T1IN
9
11
12
10
C2-
3
R1OUT
T2IN
14
13
5
7
8
VS-
6
4
2
1
R2OUT
VS+
C1+
C1-
C2+
TRS232
4.7 k4.7 k
R1IN
T1OUT
R2IN
T2OUT
1 F 1 F
1 F 1 F
TxD
RxD
RST
CST
ISOGND
10 F0.1 F
MBR0520L
MBR0520L
1:2.1
0.1 F
3
1
D2
SN6501
D1
VCC
4, 5
2
GND
3.3 V
IN
ON GND
OUT
15
43
LP2985-50 3.3 F
10 F
ISO-BARRIER
VIN
5VISO
2
BP
10 nF
26
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
Typical Application (continued)
10.2.3 Typical Application for RS-232 Interface
Typical isolated RS-232 interface implementation is shown in Figure 27.
Figure 27. Isolated RS-232 Interface
10.2.3.1 Design Requirements
Refer to Isolated Data Acquisition System for Process Control for the design requirements.
10.2.3.2 Detailed Design Procedure
Refer to Isolated Data Acquisition System for Process Control for the detailed design procedures.
10.2.3.3 Application Curves
Refer to Isolated Data Acquisition System for Process Control for the application curves.
11 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 Transformer Driver for Isolated Power Supplies.
10 mils
10 mils
40 mils FR-4
0r ~ 4.5
Keep this
space free
from planes,
traces, pads,
and vias
Ground plane
Power plane
Low-speed traces
High-speed traces
27
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
www.ti.com
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 28). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see the Digital Isolator Design Guide.
12.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
12.2 Layout Example
Figure 28. Recommended Layer Stack
28
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
•Isolation Glossary
•Digital Isolator Design Guide
•SN6501-Q1 Transformer Driver for Isolated Power Supplies
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS PRODUCT FOLDER ORDER NOW TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
ISO7340C Click here Click here Click here Click here Click here
ISO7340FC Click here Click here Click here Click here Click here
ISO7341C Click here Click here Click here Click here Click here
ISO7341FC Click here Click here Click here Click here Click here
ISO7342C Click here Click here Click here Click here Click here
ISO7342FC Click here Click here Click here Click here Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
29
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
www.ti.com
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
14X 1.27
16X 0.51
0.31
2X
8.89
TYP
0.33
0.10
0 - 8
0.3
0.1
(1.4)
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
10.5
10.1
B
NOTE 4
7.6
7.4
4221009/B 07/2016
SOIC - 2.65 mm max height
DW0016B
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
116
0.25 C A B
9
8
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
TYPICAL
DETAIL A
SCALE 1.500
30
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
www.ti.com
EXAMPLE BOARD LAYOUT
(9.75)
R0.05 TYP
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
(9.3)
14X (1.27)
R0.05 TYP
16X (1.65)
16X (0.6)
14X (1.27)
16X (2)
16X (0.6)
4221009/B 07/2016
SYMM
SOIC - 2.65 mm max height
DW0016B
SOIC
SYMM
SEE
DETAILS
1
89
16
SYMM
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
SCALE:4X
LAND PATTERN EXAMPLE
SYMM
1
89
16
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SEE
DETAILS
31
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
www.ti.com
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
www.ti.com
EXAMPLE STENCIL DESIGN
R0.05 TYP
R0.05 TYP
16X (1.65)
16X (0.6)
14X (1.27)
(9.75)
16X (2)
16X (0.6)
14X (1.27)
(9.3)
4221009/B 07/2016
SOIC - 2.65 mm max height
DW0016B
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
89
16
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
BASED ON 0.125 mm THICK STENCIL
SOLDER PASTE EXAMPLE
SCALE:4X
SYMM
SYMM
1
89
16
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
32
ISO7340C
,
ISO7340FC
,
ISO7341C
,
ISO7341FC
,
ISO7342C
,
ISO7342FC
SLLSEI6G –SEPTEMBER 2014–REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 10-Nov-2016
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ISO7340CDW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7340C
ISO7340CDWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7340C
ISO7340FCDW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7340FC
ISO7340FCDWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7340FC
ISO7341CDW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7341C
ISO7341CDWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7341C
ISO7341FCDW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7341FC
ISO7341FCDWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7341FC
ISO7342CDW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7342C
ISO7342CDWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7342C
ISO7342FCDW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7342FC
ISO7342FCDWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ISO7342FC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Nov-2016
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ISO7340CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7340FCDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7341CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7341FCDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7342CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7342FCDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Nov-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO7340CDWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7340FCDWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7341CDWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7341FCDWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7342CDWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7342FCDWR SOIC DW 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Nov-2016
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
ISO7340FCDW ISO7340FCDWR