TB62719AF TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic TB62719AF 16ch constant current drivers and controller for full-color LED modules and panels The TB62719AF is an LED driver which is suitable for driving full-color LED modules. This device has built-in 8-bit PWM grayscale and each output current adjustment functions. It can turn on to 16 LEDs. This device has a heat sink fitting side on the surface of the package. Then, a heat sink will dissipate heat generated in the device. In addition, this device built-in TSD (Thermal Shut Down) and output-open detection functions to protect the device. Weight: 0.26 g (typ.) Features * Output current capability and number of outputs: 90 mA x 16 outputs * Recommended constant current range: 2.5 to 75 mA * Application output voltage: 0.7 V (IOUT = 2.5 to 90 mA) 0.4 V (IOUT = 2.5 to 40 mA) * Adjustment function 1. Standard current adjustment (8-bit serial data input) This function supports standard current adjustment using an external resistance connected to the REXT pin. 2 high-order bits: Output current can be adjusted to any one of 4 levels in the range 25 to 100%. 6 low-order bits: Output current can be adjusted to any one of 64 levels in the range 40 to 100%. 2. Each dot adjustment (128-bit serial data input) This function allows adjustment of the current value for each output (dot). : Output current can be adjusted to any one of 64 levels in the range 20 to 100%. 3. All dot adjustment 1 (8-bit parallel data input) This function allows adjustment of brightness for each LED module. 5 low-order bits: Output current can be adjusted to any one of 32 levels in the range 50 to 100%. 4. All dot adjustment 2 (8-bit parallel data input) This function allows changes to the frequency of the PWM clock and allows major brightness adjustment for the display. 3 high-order bits: PWM clock frequency can be adjusted to any one of 8 levels in the range 1/1 to 1/8. 5. 256-grayscale PWM function (8-bit parallel data input) This function controls the pulse width for each output, yielding 256 grayscales. Maximum PWM clock frequency 10 MHz (for all temperature range), Minimum pulse width 2 s. * Accuracy of bits in constant-current output levels prior to adjustment 6.0% max (for output current of 5 mA to 75 mA) * Protection functions 1. Thermal shutdown function (TSD) This function monitors the rise in junction temperature. Connect a pull-up resistor to the ALARM1 pin in order to monitor the temperature. Step 1 When junction temperature is 120 or more: Error signal is driven out from the ALARM1 pin. Step 2 When junction temperature is 140 or more: Error signal is driven out from the ALARM1 pin and all outputs are turned off. 2. Output Open Detection (OOD) This function operates when an output pin is open. Connect a pull-up resistor to the ALARM2 pin in order to monitor this. * For anode-common LEDs * Input signal voltage level: CMOS level (schmitt trigger input) 1 2006-06-14 TB62719AF * Power supply voltage range: VDD = 4.5 V to 5.5 V * Maximum output pin voltage: 26 V * Serial and parallel data transfer rate: 20 MHz (max, cascade connection) * Operating temperature range: Topr = -40 to 85C * Package: HQFP64-P-1010-0.50. A Heat sink can be fitted * Existing product: The same pin assignment and function as TB62718AF Warnings Short-circuiting an output pin to GND or to the power supply pin may destroy the device. Take care when wiring the output pins, the power supply pin and the GND pins (VSS, VSS2). Do not apply either positive or negative voltages to the heat sink on the surface of the IC. In addition, do not solder anything to the heat sink. 2 2006-06-14 TB62719AF PI SEL PI LATCH PI CLK VSS PI DATA 0 PI DATA 1 PI DATA 2 PI DATA 3 PI DATA 4 PI DATA 5 PI DATA 6 PI DATA 7 VDD NC VSS2 OUT 00 Pin Assignment (top view) and Markings 48 DOE SI DATA SI CLK SI LATCH SI SEL PWMCLK BCEN DCEN 33 49 32 TB62719AF RESET LED TEST BLANK REXT VSS SO DATA TSENA TEST0 4WWKA** 64 17 16 TEST1 ALARM1 ALARM2 VSS PO DATA 0 PO DATA 1 PO DATA 2 PO DATA 3 PO DATA 4 PO DATA 5 PO DATA 6 PO DATA 7 VDD NC VSS2 OUT 15 1 OUT 01 OUT 02 OUT 03 OUT 04 OUT 05 OUT 06 OUT 07 VSS2 VSS2 OUT 08 OUT 09 OUT 10 OUT 11 OUT 12 OUT 13 OUT 14 Note: Indicates device name on the upper surface of the package. Indicates weekly code on the lower surface of the package. Details of weekly code on lower surface: From left, st 1 character = rightmost digit of year 3 for 2003, 4 for 2004 nd rd 2 and 3 characters = week of manufacture during year: maximum value = 52. th 4 characters = manufacturing factory (`K' means the Kita Kyushu factory.) th th 5 to 7 characters = lot number within week st nd rd 1 lot is A11, 2 lot is A1 and 3 lot is A. th th th 4 lot is B11, 5 lot is B1 and 6 lot is B. th th th 64 lot is Z11, 65 lot is Z1 and 66 lot is Z. The four characters of `I', `M', `O' and `W' are not used. 3 2006-06-14 TB62719AF Block Diagram (entire device) PI DATA [0 to 7] PI SEL PWMCLK SI DATA SI SEL 8 8 3 8 3-bit Clock counter PI CLK SI CLK PI REG2 PI REG1 All dot adjustment data register & latch (1 x 8 bits) BCEN PWM data register & latch (16 x 8 bits) 8 8-bit clock counter SI REG2 SI REG1 Each dot adjustment data register & latch (1 x 128 bits) Standard current adjustment data register & latch (1 x 8 bits) 8 PI LATCH DCEN SI LATCH 8 8 PWM pulse generator circuit (8 bits) 5 8 DOE PO DATA [0 to 7] OUT [00 to 15] BLANK& LED TEST SO DATA 128 DAC1 8 DAC4 16 16 x 6 bit DACs and 16 constant-current outputs ALARM2 TSD2 circuit DAC3 V/I conversion circuit 1 x 5-bit DAC Output-open detection circuit 1 x 2-bit DAC DAC2 1 x 6-bit DAC ALARM1 TSD1 circuit REXT TSENA For PI REG1, PI REG2, SI REG1 and SI REG2 4 RESET 2006-06-14 TB62719AF Constant Current Adjustment Range (graph) This Graph Shows How Current May Be Adjusted to a Fraction of Its Full-Scale Value. Note: In each case, the value input to each DAC is the value output from the previous DAC. Reference: Current adjustment functions DAC1 to DAC3 are the current adjustment functions for all outputs. The adjustment width of DAC1 is large and approximate (1LSB - 25%). The adjustment width of DAC2 is the smallest and has a large error (1LSB - 0.95%). The adjustment width of DAC3 is small. DAC3 is a high-performance DAC with a small error (1LSB - 1.61%). Therefore, It is recommended that DAC1 and DAC2 be used for adjusting the REXT resistance. It is recommended that DAC3 be used for adjusting brightness between module. (after it was set and it had DAC4 adjusted to the dot.) The beginning is set in about 75% of the middle value, after that it is effective to use 25% of set width. DAC4 is the current adjustment function for each outputs. The adjustment width of DAC4 is small. But it is a high-performance DAC with a small error (1LSB - 1.27%). And also, DAC4 has a very wide setting range. Therefore, DAC4 can be used to adjust the brightness of LEDs without a rank classification. This method allows brightness to be adjusted with a degree of accuracy of 1.27% of full scale. Note: Assuming precise linear correlation between output current and LED brightness 5 2004-05-12 TB62719AF Equivalent Input and Output Circuit (resistance values are typical values.) 1. Input pins with pull-up resistor 2. Input pins with pull-down resistor. TSENA, BLANK SI/PI LATCH, PI DATA0 to DATA7, BC/DCEN, LED TEST R (UP) = 300 k VDD VDD 1 k IN IN 1 k GND R (DOWN) = 300 k GND 3. Input terminals (A) (B) 4. Output terminals SI DATA, SI/PI CLK, PWMCLK RESET , DOE, PI/SI SEL PO DATA0 to DATA7, SO DATA VDD VDD IN 100 Rin GND OUT GND (A) Rin = 250 (B) Rin = 1 k 5. Protection circuit for monitor terminals 6. Constant-current output terminals ALARM1, 2 OUT 00 to 15 Parasitic diode Parasitic diode VSS VSS2 6 2004-05-12 TB62719AF Explanation of Pin Functions Table No. Name I/O 4, 45 VSS P Pull up Unused This pin is used to reset the IC's built-in temperature monitoring circuit (TSD). Rising edge of input signal re-enables outputs which had been forced to OFF. The latched data as the setting is not reset. Either in case of H- or L-level of this terminal can be operated TSD circuit. 35, 14 NC Function Explanation Logic ground pins. Be sure to use all. 63 TSENA I Pull up 15, 24, 25, 34 VSS2 P Ground pin for output. Be sure to use all. 13, 36 VDD P Logic power supply input pins. Be sure to use all. 16 to 23, 26 to 33 OUT 00 to 15 O LED drive output pins. Connect to cathode of LED. 50 SI DATA I Serial data input pin. Used for input of standard current adjustment data and dot adjustment data 51 SI CLK I Serial data transfer clock input pin. Data is transferred at positive edge. 52 SI LATCH I 53 SI SEL I 62 SO DATA O 37 to 44 PI DATA [0 to 7] I 46 PI CLK I Pull Serial data latch signal input pin. Data is held on positive edge. down Serial data selection pin. Either standard current adjustment data or dot adjustment data may be selected. Serial data output pin. The output data type is selected using SI SEL. Pull Input pins for parallel data. Inputs for all output adjustment data and PWM data down Input pin for parallel data transfer clock. Data is transferred on positive edge. Pull Input pin for parallel data latch signal. Data is held on positive edge. down 47 PI LATCH I 48 PI SEL I Parallel data selection pin. Either total dot adjustment data or PWM data may be selected. 5 to 12 PO DATA [0 to 7] O Output pin for parallel data. The output data type is selected using PI SEL. 49 DOE I Control pin for parallel data output PO DATA. PI DATA is out on input of an H-level signal. PI DATA is set to High-impedance by input of an L-level signal. 59 BLANK I Pull up PWM circuit control signal input pin. Output is turn OFF by input of an H-level signal. PWM output is initiated by input of an L-level signal accordingly to the input data. 54 PWMCLK I 55 BCEN I Pull up Selection signal input pin for all output adjustment functions. All output adjustment is fixed to 100% when this signal is Low. All bit adjustments become effective when it is High. It is not influent anything to all output adjustment by PWM clock. 56 DCEN I Pull up Selection signal input pin for dot adjustment function. Dot adjustment value is fixed to 100% when this signal is Low. Dot adjustment becomes effective when it is High. 57 RESET I 58 LED TEST I 60 REXT P Connection pin of resistor for setting for the current. 2 ALARM1 O Open-collector monitor pin for TSD circuit. When the TSD circuit detects an abnormal temperature, this signal is turned ON. IO monitor the TSD circuit connect this pin to a pull-up resistor. ALARM1 is independent of the RESET signal. 3 ALARM2 O Open-collector monitor pin for output-open detection circuit. When an open output is detected, this signal is turned ON. 1, 64 TEST [0:1] I Pins for the device testing. Connect all these pins to ground. Pin attributes Standard clock input pin for PWM circuit. One clock cycle is equivalent to the minimum pulse width of the PWM output. Reset signal input pin. Setting and registered data are reset when it is Low. A reset also releases TSD. Connection confirmation signal input pin for an LED. When this signal is High, all outputs Pull are ON. down This signal should normally be kept Low. P: power supply/ground/other, I: input pin, O: output pin Note: It is recommended that pins with pull-up or pull-down resistors not be left open. Ambient noise may cause malfunction of the device. 7 2004-05-12 TB62719AF Absolute Maximum Ratings (Ta = 25C) Characteristics Supply voltage Constant-current output voltage Symbol Rating Unit VDD -0.3 to +7 V VO -0.3 to +26 V Output current IOUT +90 mA/bit Logic output voltage VOUT -0.3 to +7 V VIN -0.3 to VDD + 0.3 V IVSS2 1.44 A Logic input voltage Total VSS2 current (Note 1) When device mounted on PCB Power dissipation When device mounted on PCB of any size 1.19 (Note 3) 5.0 (Note 4) Pd W (Note 2) When device mounted on PCB (j-a) 105 (Note 3) When device mounted on PCB of any size (j-c) 25 (Note 4) Operating temperature Topr -40 to 85 C Storage temperature Tstg -55 to 150 C Saturation heat resistance of package C/W Note 1: All four VSS2 pins must be connected. If not, device characteristics cannot be guaranteed. Note 2: If the operating temperature exceeds 25C, derate the power dissipation rating by 0.95 mW/C. Note 3: When device mounted on PCB with dimensions 100 x 100 x 1.6 mm Note 4: When using heat sink fin which allows the device for more heat dispersion Recommended Operating Conditions DC Characteristics (unless otherwise specified, VDD = 4.5 to 5.5 V, Topr = -40 to 85C) Characteristics Symbol Conditions & Terminals Min Typ. Max Unit Supply voltage VDD 4.5 5.0 5.5 V High-level input voltage VIH PI DATA, PI CLK, PI SEL, PI LATCH, SI DATA, SI CLK, SI SEL, SI LATCH, PWM CLK 0.7 x VDD VDD V Low-level input voltage VIL BLANK, LED TEST, TSENA, DOE, DCEN, BCEN VSS 0.3 x VDD V High-level output current IOH DATA PO0 to 7, SO DATA -1 mA Low-level output current IOL VDD = 4.5 V, ALARM1/2 1 mA Constant-current output IOUT OUT00 to 15 5 80 mA/bit VOUT OUT00 to 15 OFF 26 V VOH ALARM1/2 OFF 5 V -40 85 C Output voltage Operating temperature Topr 8 2004-05-12 TB62719AF Timing Recommended Operating Conditions (unless otherwise specified, VDD = 4.5 V to 5.5 V, Topr = -40 to 85C) Characteristics Symbol Min Typ. Max PWM CLK, Ratio of High-level: Low level = 50%, 10 fPI1 PI CLK 15 fPI2 PI CLK, connected in cascade 10 fSI1 SI CLK 15 fSI2 SI CLK, connected in cascade 10 fPWM Clock frequency PWM CLK 30 PI CLK, SI CLK 30 PI LATCH, SI LATCH 50 twrstH/twrstL RESET 50 twblkH/twblkL BLANK 400 twledH/twledL LED TEST 400 PI DATA PI CLK 10 PI LATCH PI CLK 10 SI DATA SI CLK 10 SI LATCH SI CLK 10 SI LATCH SI CEL 50 PI DATA PI CLK 5 PI LATCH PI CLK 5 SI DATA SI CLK 5 SI LATCH SI CLK 5 SI LATCH SI CEL 50 twH/twL Minimum pulse width Set-up time Hold time Condition & Terminals twltH/tpltL tsetup thold 9 Unit MHz ns ns ns 2004-05-12 TB62719AF Electrical Characteristics 1 (unless otherwise specified, typ.: VDD = 5.0 V, Topr = 25C, load capacitance = 50 pF, min/max: VDD = 4.5 to 5.5 V, Topr = -40 to 85C, load capacitance = 50 pF) Characteristics High-level output voltage Low-level output voltage Symbol Test Terminals VOH PO DATA 0 to 7 SO DATA IOH = -1.0 mA PO DATA 0 to 7 SO DATA Min Typ. Max Unit VDD -0.5 V IOL = +1.0 mA PO DATE 0 to 7, SD DATE 0.5 IOL = +2.5 mA 0.5 VOUT = VDD or VSS 0.5 5 A II All pins without pull-up/pull-down resistors 1 A IDD1 PI DATA = 1/2 PI CLK SI DATA = 1/2 SI CLK PI CLK = SI CLK = 20 MHz PWMCLK = "L", BLANK = "H" Topr = 25C Settings *1 4 13 23 IDD2 PI DATA = SI DATA = "L" PI CLK = SI CLK = "L" PWMCLK = 20 MHz Topr = 25C Settings *5a 12 21 35 PI DATA = 1/2 PI CLK SI DATA = 1/2 SI CLK PI CLK = SI CLK = PWMCLK = 20 MHz Settings *5a 20 32 47 Topr = -40C, Other conditions are the same as above. 55 PI DATA = SI DATA = "L" PI CLK = SI CLK = "L" PWMCLK = 20 MHz Topr = 25C Settings *6a 14 27 44 PI DATA = 1/2 PI CLK SI DATA = 1/2 SI CLK PI CLK = SI CLK = PWMCLK = 20 MHz Topr = 25C Settings *6a 22 38 56 Topr = -40C, Other conditions are the same as above. 70 VOL ALARM1, 2 Tri-state output leakage current Input current IOZ PO DATA 0 to 7 IDD3 Supply current VDD IDD4 IDD5 10 Test Conditions V mA 2004-05-12 TB62719AF Electrical Characteristic Settings (unless otherwise specified, OUT00 to 15 ON, VOUT = 0.7 V and REXT = 910 k) NO. All Dot Adjustment (DAC3) DAC Settings Constant Output Current (typ.) *1 OUT00 to 15 OFF, VOUT = 26 V, DAC1, 2, 4 = initial setting, BLANK = "H" IOUT = 0 mA *2a DAC1 = 0, DAC2 = 0, DAC4 = 39, BLANK = "L" IOUT = 5 mA *3a DAC1 = 0, DAC2 = 18, DAC4 = 63, BLANK = "L" IOUT = 10 mA DAC3 = 31 *4a DAC1 = 1, DAC2 = 18, DAC4 = 63, BLANK = "L" *5a DAC1 = 2, DAC2 = 38, DAC4 = 63, BLANK = "L" IOUT = 20 mA IOUT = 40 mA *6a DAC1 = 3, DAC2 = 46, DAC4 = 63, BLANK = "L" IOUT = 60 mA *7 DAC1 = 3, DAC2 = 63, DAC4 = 63, BLANK = "L" IOUT = 70 mA *2b DAC1 = 0, DAC2 = 0, DAC4 = 39, BLANK = "L" IOUT = 2.5 mA *3b DAC1 = 0, DAC2 = 18, DAC4 = 63, BLANK = "L" IOUT = 5 mA *4b DAC1 = 1, DAC2 = 18, DAC4 = 63, BLANK = "L" *5b DAC1 = 2, DAC2 = 38, DAC4 = 63, BLANK = "L" IOUT = 20 mA *6b DAC1 = 3, DAC2 = 46, DAC4 = 63, BLANK = "L" IOUT = 30 mA DAC3 = 00 IOUT = 10 mA Electrical Characteristics 2 (unless otherwise specified, typ.: VDD = 5.0 V, Topr = 25C, load capacitance = 50 pF, min/max: VDD = 4.5 to 5.5 V, Topr = -40 to 85C, load capacitance = 50 pF) Characteristics Symbol Constant-current output IOUT2 Settings *6a 51.0 60.0 69.0 IOUT3 Settings *5a 34.0 40.0 46.0 IOUT4 Settings *4a 16.6 20.0 23.4 IOUT5 Settings *3a 7.8 10.0 12.2 IOUT6 Settings *2a 3.2 5.0 6.8 IOUT = 2.5 to 75 mA, VOUT = 1.0 V, Topr is varied in the range -40C to 85C 25 50 A/C Settings *1, VOUT = 26 V 0.1 A IOUT = 2.5 to 75 mA 1.5 6 % %IOUT IOUT = 2.5 to 75 mA 1 2.5 % %VOUT IOUT = 2.5 to 75 mA, VOUT is varied in the range 0.7 V to 3 V. 3 5 % Settings *4a, 5a, 6a VDD = 4.5 5.5 V -2.0 2.0 Settings *3a, 2a VDD = 4.5 5.5 V -5.0 5.0 IOUT Output-open detection voltage Pull-up/down resistor Unit 81.6 Constant current accuracy between bits TSD detection temperature Max 71.0 IOLK Constant-current output depends on supply voltage Typ. 60.4 Leakage current for constant-current output Constant-current output depends on output voltage Min Settings *7 %TOPR1 (Note) Test Condition IOUT1 Constant-current output Depends on temperature Dot adjustment deviation between bits Test Terminals OUT 00 to 15 %VDD V % Tsd1 120 Tsd2 140 0.04 x VDD V 150 300 600 k VARL Rup/Rdw ALARM2 C Note: When DAC3 data were changed from MSB to LSB. 11 2004-05-12 TB62719AF Electrical Characteristic Settings (unless otherwise specified, OUT00 to 15 ON, VOUT = 0.7 V and REXT = 910 ) NO. All Dot Adjustment (DAC3) DAC Settings Constant Output Current (typ.) *1 OUT00 to 15 OFF, VOUT = 26 V, DAC1, 2, 4 = initial setting, BLANK = "H" IOUT = 0 mA *2a DAC1 = 0, DAC2 = 0, DAC4 = 39, BLANK = "L" IOUT = 5 mA *3a DAC1 = 0, DAC2 = 18, DAC4 = 63, BLANK = "L" IOUT = 10 mA DAC3 = 31 *4a DAC1 = 1, DAC2 = 18, DAC4 = 63, BLANK = "L" *5a DAC1 = 2, DAC2 = 38, DAC4 = 63, BLANK = "L" IOUT = 20 mA IOUT = 40 mA *6a DAC1 = 3, DAC2 = 46, DAC4 = 63, BLANK = "L" IOUT = 60 mA *7 DAC1 = 3, DAC2 = 63, DAC4 = 63, BLANK = "L" IOUT = 70 mA *2b DAC1 = 0, DAC2 = 0, DAC4 = 39, BLANK = "L" IOUT = 2.5 mA *3b DAC1 = 0, DAC2 = 18, DAC4 = 63, BLANK = "L" IOUT = 5 mA *4b DAC1 = 1, DAC2 = 18, DAC4 = 63, BLANK = "L" *5b DAC1 = 2, DAC2 = 38, DAC4 = 63, BLANK = "L" IOUT = 20 mA *6b DAC1 = 3, DAC2 = 46, DAC4 = 63, BLANK = "L" IOUT = 30 mA DAC3 = 00 IOUT = 10 mA Switching Characteristics (unless otherwise specified, typ.: VDD = 5.0 V, Topr = 25C, load capacitance = 50 pF, min/max: VDD = 4.5 to 5.5 V, Topr = -40 to 85C, load capacitance = 50 pF) Characteristics Symbol Test Condition Min Typ. Max Unit fMAX1 When connected in cascade 15 fMAX2 Without a board 20 Maximum PWMCLK frequency fMAX3 Without a board 15 Tri-state output enable propagation delay time tpZH/ZL DOE PO DATA0 to PO DATA7 8 16 30 ns Tri-state output disable propagation delay time tpHZ/LZ DOE PO DATA0 to PO DATA7 8 16 30 ns OUT00 to OUT15 25 120 220 s ns Maximum SI CLK/PI CLK frequency Rise time tr Fall time ALARM1, 2 65 120 170 OUT00 to OUT15 15 60 105 ALARM1, 2 5 15 25 tpHL BLANK OUT00 to OUT15 40 230 410 tpLH PWM CLK OUT00 to OUT15 35 85 130 tpHL PWM CLK OUT00 to OUT15 40 230 410 30 75 120 tf tpLH Propagation delay time (Note) ns LED TEST OUT00 to OUT15 tpHL tpHL tpd (voltage waveform) MHz 40 230 410 RESET OUT00 to OUT15 30 100 170 PI CLK PO DATA0 to PO DATA7 20 30 70 PI SEL PO DATA0 to PO DATA7 20 30 70 SI SEL SO DATA 10 18 40 SI SEL SO DATA 10 20 40 ns Note: For the switching test condition, refer to No. *5a in the table "Electrical Characteristic Settings". 12 2004-05-12 TB62719AF Explanation of Operation and Truth Tables Serial Data Transfer: Standard Current Adjustment Using DAC1 and DAC2 (data register SI REG1 [7:0]) Process SI DATA SI CLK SI LATCH SI SEL SO DATA Operation and Function L H H or L Selects standard current adjustment (8 bits, 2 bits and 6 bits) for input data. When SI REL is high, data is transferred to SI REG [1] on 8th positive edge of SI CLK input. 1 (x8) H or L 2 H L (x1) Holds the data transferred to SI REG [1] on positive edge of SI Latch. No change Set is reflected on standard current adjustment from the moment when it is held. Serial Data Transfer Timing (standard current adjustment, SI SEL = H, single device) RESET SI SEL SI DATA Data held on positive edge of SI LATCH after the data transfer by single device (after 8 clock cycles) SI CLK SI LATCH SO DATA (1st device) Data reset by RESET = L SO DATA is synchronized with 8th clock cycle after reset, and the first data is out. Indicates undefined logic state after reset and before input. Serial Data Transfer Timing (standard current adjustment, SI SEL = H, two devices connected in cascade) RESET SI SEL SI DATA SI CLK SI LATCH SO DATA (1st device) Data reset by RESET = L Indicates undefined logic state after reset and before input. Data held on positive edge of SI LATCH after the data transfer by two devices (after 16 clock cycles) SO DATA is synchronized with 8th clock cycle after reset, and the first data is out. 13 2004-05-12 TB62719AF Serial Data Transfer: Dot Adjustment DAC4. (data register SI REG1 [127:0]) Process SI DATA SI CLK SI LATCH SI SEL SO DATA Operation and Function L L H or L Selects dot adjustment (128 bits) for input data. Data is transferred to SI REG2 on 128th positive edge of SI CLK. L No change Holds the data transferred to SI REG2 on positive edge of SI Latch. Set is reflected on dot adjustment from the moment when it is held. 1 H or L 2 (x128) L (x1) Serial Data Transfer Timing (dot adjustment, SI SEL = L, single device) RESET SI SEL These pairs of bits are "Don't care". SI DATA SI CLK Dot adjustment data for OUT15 (1st device). Dot adjustment data for OUT00 (1st device). Data held on positive edge of SI LATCH after data transfer by single device (after 128 clock cycles) SI LATCH SO DATA (1st device) Data reset by RESET = L SO DATA is synchronized with 128th clock cycle after reset, and the first data is out. Indicates undefined logic state after reset and before input. Serial Data Transfer Timing (dot adjustment, SI SEL = L, two devices connected in cascade) RESET SI SEL These pairs of bits are "don't care". SI DATA SI CLK Dot adjustment data for OUT15 (1st device). Dot adjustment data for OUT00 (1st device). Dot adjustment data for OUT15 (2nd device). Dot adjustment data for OUT00 (2nd device). SI LATCH SO DATA (1st device) Data reset by RESET = L Indicates undefined logic state after reset and before input. SO DATA is synchronized with 128th clock cycle after reset, and the first data is out. Data held on positive edge of SI LATCH after data transfer by two devices (after 256 clock cycles) 14 2004-05-12 TB62719AF DAC1: Standard Current Adjustment Settings for DAC1 (SI REG1 [7:6]) RESET SI SEL SI REG (7:6) SI REG (5:0) Current Rate H H HH XXXXXX 100% (1.0) 100% of base current setting as determined by REXT () H H HL XXXXXX 75% (0.75) 75% of base current setting as determined by REXT () H H LH XXXXXX 50% (0.5) 50% of base current setting as determined by REXT () H H LL XXXXXX 25% (0.25) 25% of base current setting as determined by REXT () X LL LLLLLL 25% (0.25) Initial state after input of reset signal: 25% of base current setting as determined by REXT () (as described above) Operation and Function Notes When SI SEL = H, 2 bits on MSB sides are corresponding to set of standard current adjustment DAC1. The output current can be set to one of 4 levels. DAC2: Standard Current Adjustment Settings for DAC2 (SI REG1 [5:0]) RESET SI SEL SI REG (7:6) SI REG (5:0) Current Rate H H XX HHHHHH 100% (1.0) HHHHHL (0.9905) H H H Operation and Function 100% of base current value as set using DAC1 current adjustment Any one or 64 levels in the range 1LSB = 100 to 40% of the current can be 0.95% set. (1LSB = 0.95%) (0.0095) 6-bit DAC performance XX LLLLLH (0.4095) Notes H XX LLLLLL 40% (0.4) 40% of base current value as set using DAC1 current adjustment X LL LLLLLL 40% (0.4) Initial state after input of reset signal: 40% of base current value set as described above When SI SEL = H, 6 bits on MSB sides are corresponding to set of standard current adjustment DAC2. The output current can be set to one of 64 levels. DAC4: Set Details of Dot Adjustment DAC4 (SI REG2 [127:0]) RESET H SI SEL L DCEN H About 8 bits Unit of SI REG [127:0] Current Rate Operation and Function XXHHHHHH 100% (1.0) Output current is 100% of base current value as set using DAC1 and DAC2 base current adjustment and DAC3 surface brightness adjustment XXHHHHHL H L H XXLLLLLH H H Notes When SI SEL = L 8 bits out of 128 bits are corresponding to set of each (0.9874) Any one of 64 levels in the range output, and the 6 bits on MSB 100 to 20% of the current can be sides of 8 bits are data on dot set. (1LSB - 1.27%) adjustment 1LSB = The output current can be set to 1.269% (6-bit DAC performance) 1LSB variation: 1.269% (typ.) one of 64 levels. (0.0126) Non linearity error: 1/2LSB SI REG2 [7:0] Differential non linearity error: adjustment data for OUT0. 1/2LSB (20.0126) SI REG2 [15:8] adjustment data for OUT1. 20% 20% of base current value as set SI REG2 [127:120] (0.2) using DAC3 current adjustment. adjustment data for OUT15. L H XXLLLLLL X H XXLLLLLL 20% (0.2) Initial state after input of reset signal: 20% of base current value set as described above X L XXHHHHHH 100% (1.0) Output current is 100% of base current value set as described above. 15 Data input is still enabled if DCEN = L. If DCEN = H, adjustment is performed at the same time. 2004-05-12 TB62719AF Polarity of Serial Input Data for Standard Current Adjustment (SI REG1 [7:0]) and Dot Adjustment (SI REG2 [127:0]) Serial Data Transfer Timing SI SEL = H, Input of Standard Current Adjustment Data for DAC1 and DAC2 Standard current adjustment data (6 bits) Standard current adjustment data (2 bits) SI DATA SO DATA D-F/F D-F/F D-F/F D-F/F D-F/F D-F/F D-F/F D-F/F SI REG1 (0) SI REG1 (7) LSB MSB D-LAT D-LAT D-LAT D-LAT D-LAT D-LAT D-LAT D-LAT SI LATCH SI SEL = L, Input of Dot Adjustment Data for DAC4 Not used Not used Dot adjustment data (6 bits) Dot adjustment data (6 bits) SI DATA SI REG2 (0) LSB x x SI REG2 (7) SO DATA x x SI REG2 (120) SI REG2 (127) MSB SI LATCH DAC4 (6-bit DAC) DAC4 (6-bit DAC) OUT00 OUT15 16 2004-05-12 TB62719AF Parallel Data Transfer: All Dot Adjustment DAC3. (data register: PI REG1 [7:0]) Process PI DATA [7:0] PI CLK PI LATCH PI SEL PO DATA [7:0] L H H or L H No change 1 H or L 2 (x1) L Operation and Function Selects total dot adjustment (8-bit, 3-bit and 5-bit) for input data. Data is transferred to PI REG1 on 128th positive edge of PI CLK. Holds the data transferred to PI REG1. Set is reflected on all dot adjustment from the moment when it is held. (x1) Parallel Data Transfer Timing (all dot adjustment, PI SEL = H, single device) RESET PI SEL PI DATA [7:0] 111_11111 PI CLK Data held on positive edge of PI LATCH after data transfer by single device (after 1 clock cycle) PI LATCH PO DATA [7:0] 111_11111 000_00000 Indicates undefined logic state after reset and before input. PO DATA is synchronized with 1st clock cycle after reset, and the first data is out. Parallel Data Transfer Timing (all dot adjustment, PI SEL = H, two devices connected in cascade) RESET PI SEL PI DATA [7:0] 111_11111 110_11110 101_11101 PI CLK PI LATCH PO DATA [7:0] (1st device) 111_11111 000_00000 Indicates undefined logic state after reset and before input. 110_11110 Data held on positive edge of PI LATCH after the data transfer by two devices (2 clock cycles) PO DATA is synchronized with 2nd clock cycle after reset, and the second data is out. PO DATA is synchronized with 1st clock cycle after reset, and the first data is out. 17 2004-05-12 TB62719AF Parallel Data Transfer PMW Display Data (data register: PI REG2 [127:0]) Process PI DATA PI CLK PI LATCH PI SEL PO DATA L L H or L 1 Selects for input data of PWM display data (8 bit x 16). Data is transferred to PI REG2 on 16th positive edge of PI CLK. (x16) H or L 2 Holds the data transferred to PI REG2. Set is reflected No change on PWM 256 grayscales from the next BLANK = L when it is held. L L Operation and Function (x1) Parallel Data Transfer Timing (PWM data SI SEL = L, single device) RESET PWM data for OUT15 PWM data for OUT00 PI SEL PI DATA [7:0] 01H 02H 0EH 0FH 10H PI CLK Data held on positive edge of PI LATCH after data transfer by single device (after 1 clock PI LATCH PO DATA [7:0] 00H 00H 01H PO DATA is synchronized with 16th clock cycle after reset, and the first data is out. Indicates undefined logic state after reset and before input. Parallel Data Transfer Timing (PWM data SI SEL = L, two devices connected in cascade) RESET PI SEL PI DATA [7:0] 00H 01H 02H 0EH 0FH 10H 01H 02H 0EH 0FH 10H PI CLK PI LATCH PO DATA [7:0] (1st device) PWM data for OUT15 (1st device) 00H PWM data for OUT00 (1st device) 00H Indicates undefined logic state after reset and before input. 01H 02H 0FH 10H 01H PO DATA is synchronized with 16th clock cycle after reset, and the first data is out. Data held on positive edge of PI LATCH after data transfer by two devices (32 clock cycles) 18 2004-05-12 TB62719AF Parallel Data Transfer: Optional Function to Change PO DATA [7:0] Delay Time 8 Bits of SI REG [127:120] PO DATA [7:0] LLXXXXXXXX tpd, constant Operation and Function Normal operating mode. Same as in the specification. LHXXXXXXXX Small delay mode. HLXXXXXXXX Switching Characteristics are minimized for 2 ns to 3 ns compare to the values in the specification. HHXXXXXXXX tpd, 2 ns to 3 ns minimized 19 Notes Delay time in PO DATA [7:0] can be varied using 2 bits of dot adjustment register SI REG [127:126]. 2004-05-12 TB62719AF Details All Dot Adjustment Setting Using PWMCLK Division (PI REG1 [7:5]) RESET PI SEL BCEN PI REG1 [7:5] H H H LLL PWMCLK = 8/8 PWMCLK (Hz) LLH H H 1LSB = 1/8 divides PWMCLK H HHL H H PWMCLK Divisor H H HHH PWMCLK = 1/8 PWMCLK (Hz) X H LLL PWMCLK = 8/8 PWMCLK (Hz) H L Refer to notes Refer to notes Operation and Function Notes The period of PWMCLK is set to equal the change in the PWM pulse width data. 1LSB. When PI SEL = H is selected, 3 bits on MSB sides are corresponding to set of total dot Variable does the frequency of adjustment by PWM frequency PWMCLK to 1/8 of the minimal. It dividing. is set in 8 levels. PI REG [7:5] varies the pulse width of PWM data corresponding to 1LSB for eight The period of PWMCLK is set to levels and adjusts brightness. one-eighth the change in the PWM pulse width data. 1LSB. This setting values affects pulse widths on all outputs. The period of PWMCLK is set to equal the change in the PWM pulse width data. 1LSB. BCEN signal does not affect PWMCLK frequency dividing. Data input is still enabled if BCEN = L. Output current level reflects input settings. DAC3: Details of All Dot Adjustment Setting for DAC3 (PI REG2 [4:0]) RESET PI SEL PI REG1 [4:0] BCEN Current Rate Operation and Function H H HHHHH H 100% (1.0) 100% of base current value as set using DAC1 and DAC2 current adjustment and DAC4 dot adjustment (0.9839) Any one of 32 levels in the range 100 to 50% of the current can be set. (1LSB = 1.61%) HHHHL H H H LLLLH H H 1LSB = (5-bit DAC performance) 1.61% 1LSB variation: 1.61% (0.0161) Non linearity error: 1/2LSB Differential non linearity error: 1/2LSB (0.5161) (no guarantee for monotonicity) H LLLLL H 50% (0.5) 50% of base current value as set using DAC1 and DAC2 current adjustment and DAC4 dot adjustment X HHHHH H 100% (1.0) Initial state after input of reset signal: 100% of base current value set as described above X HHHHH L 100% (1.0) Initial state after input of DCEN signal: 100% of base current value set as described above 20 Notes When PI SEL = H is selected, 5 bits on LSB side are corresponding to set of surface brightness adjustment. The output current can be set to one of 32 levels. Data input is still enabled if BCEN = L. If BCEN = H, adjustment is performed at the same time. 2004-05-12 TB62719AF Detailed PWM 256 Grayscales Setting (PI REG2 [127:0], 16 x 1 word (8 bits)) RESET PI SEL 1 word (8 bits) of PI REG2 Output Pulse Rate H L HHHHHHHH 255/255 100% Output pulse width is at its maximum value when input data is FF. HHHHHHHL H Outputs are OFF when the input data is 00. The input data can be used to control the PWM pulse width and hence generate 256 grayscales. L LLLLLLLH H Operation and Function L LLLLLLLL 0/255 0% Outputs are OFF when the input data is 00. X LLLLLLLL 0/255 0% Early condition after the reset signal input is set in 0/256 (output off). Notes When PI SEL = L, The PWM grayscale controls the output pulse width. 1 word (8 bits) x 16 are transferred in parallel. 1 word is the PWM data of each output pulse width is set in 256 step. PI REG2 [7:0] PWM data for OUT0. PI REG2 [15:8] PWM data for OUT1. PI REG2 [127:120] PWM data for OUT15. Minimum output pulse width is 1/PWMCLK. Polarity of Serial Input Data for All Dot Adjustment (PI REG [7:0]) and PWM 256 grayscales (PI REG2 [127:0]) Parallel Data Transfer Timing PI SEL = H, Selects Data Input for All Dot Adjustment for DAC3. PI REG1 [7] MSB PI DATA [7] All dot adjustment (3 bits) PO DATA [7] All dot adjustment (5 bits) PI DATA [0] PO DATA [0] LSB PI REG1 [0] PI LATCH PI SEL = L, Selects Data Input for PWM 256 Grayscales. PI REG2 [7] MSB PO REG2 [127] MSB PI DATA [7] PO DATA [7] PWM pulse data PWM pulse data PI DATA [0] PO DATA [0] LSB PI REG2 [0] LSB PI REG2 [120] PI LATCH PWM pulse generator circuit PWM pulse generator circuit OUT00 OUT15 21 2004-05-12 TB62719AF Reference Table: Output Current Setting Vales (1) DAC1 (2 bit) DAC2 (6 bit) DAC3 (5 bit) DAC4 (6 bit) No. Input Data Current Rate1 No. Input Data Current Rate2 No. Input Data Current Rate3 No. Input Data 3 11 1.00 63 111111 1.000 31 **11111 **1.000 63 111111 Current Rate4 1.000 2 10 0.75 62 111110 0.990 30 11110 0.984 62 111110 0.987 1 01 0.50 61 111101 0.981 29 11101 0.968 61 111101 0.975 0 **00 **0.25 60 111100 0.971 28 11100 0.952 60 111100 0.962 59 111011 0.962 27 11011 0.936 59 111011 0.949 58 111010 0.952 26 11010 0.919 58 111010 0.937 57 111001 0.943 25 11001 0.903 57 111001 0.924 56 111000 0.933 24 11000 0.887 56 111000 0.911 55 110111 0.924 23 10111 0.871 55 110111 0.898 54 110110 0.914 22 10110 0.855 54 110110 0.886 53 110101 0.905 21 10101 0.839 53 110101 0.873 52 110100 0.895 20 10100 0.823 52 110100 0.860 51 110011 0.886 19 10011 0.807 51 110011 0.848 50 110010 0.876 18 10010 0.790 50 110010 0.835 49 110001 0.867 17 10001 0.774 49 110001 0.822 48 110000 0.857 16 10000 0.758 48 110000 0.810 47 101111 0.848 15 01111 0.742 47 101111 0.797 46 101110 0.838 14 01110 0.726 46 101110 0.784 45 101101 0.829 13 01101 0.710 45 101101 0.771 44 101100 0.819 12 01100 0.694 44 101100 0.759 43 101011 0.820 11 01011 0.677 43 101011 0.746 42 101010 0.800 10 01010 0.661 42 101010 0.733 41 101001 0.791 9 01001 0.645 41 101001 0.721 40 101000 0.781 8 01000 0.629 40 101000 0.708 39 100111 0.771 7 00111 0.613 39 100111 0.695 38 100110 0.762 6 00110 0.597 38 100110 0.683 37 100101 0.752 5 00101 0.581 37 100101 0.670 36 100100 0.743 4 00100 0.565 36 100100 0.657 35 100011 0.733 3 00011 0.549 35 100011 0.644 34 100010 0.724 2 00010 0.532 34 100010 0.632 33 100001 0.714 1 00001 0.516 33 100001 0.619 32 100000 0.705 0 00000 0.500 32 100000 0.606 31 011111 0.695 31 011111 0.594 30 011110 0.686 30 011110 0.581 29 011101 0.676 29 011101 0.568 28 011100 0.667 28 011100 0.556 27 011011 0.657 27 011011 0.543 26 011010 0.648 26 011010 0.530 25 011001 0.638 25 011001 0.517 24 011000 0.629 24 011000 0.505 23 010111 0.619 23 010111 0.492 22 010110 0.610 22 010110 0.479 21 010101 0.600 21 010101 0.467 20 010100 0.591 20 010100 0.454 19 010011 0.581 19 010011 0.441 18 010010 0.571 18 010010 0.429 17 010001 0.562 17 010001 0.416 16 010000 0.552 16 010000 0.403 15 001111 0.543 15 001111 0.390 14 001110 0.533 14 001110 0.378 13 001101 0.524 13 001101 0.365 12 001100 0.514 12 001100 0.352 11 001011 0.505 11 001011 0.340 10 001010 0.495 10 001010 0.327 9 001001 0.486 9 001001 0.314 8 001000 0.476 8 001000 0.302 7 000111 0.467 7 000111 0.289 6 000110 0.457 6 000110 0.276 5 000101 0.448 5 000101 0.263 4 000100 0.438 4 000100 0.251 3 000011 0.429 3 000011 0.238 2 000010 0.419 2 000010 0.225 1 000001 0.410 1 000001 0.213 0 **000000 **0.4 0 **000000 0.200 Note 1: **: Indicates post-reset initialization value (RESET= L). Note 2: The formula for calculating resistance settings is as follows: This value is theory value. Actual current value contains error and so on in this value. REXT [k] = { (1.8 x current rate 1 x current rate 2 x current rate 3) x (current rate 4 x 34.5) } / output current [mA] 22 2004-05-12 TB62719AF Reference Table: Output Current Setting Value (2) Reference Value for Standard Current Adjustment Under Conditions: REXT = 910 k (fixed), All Dot Adjustment = MSB and Dot Adjustment = MSB Unit [mA] DAC 1 DAC 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 5.8 5.9 6.0 6.2 6.3 6.4 6.6 6.7 6.8 7.0 7.1 7.2 7.4 7.5 7.6 7.8 1 11.6 11.8 12.1 12.3 12.6 12.9 13.1 13.4 13.7 13.9 14.2 14.5 14.7 15.0 15.3 15.5 2 17.3 17.7 18.1 18.5 18.9 19.3 19.7 20.1 20.5 20.9 21.3 21.7 22.1 22.5 22.9 23.3 3 23.1 23.6 24.2 24.7 25.2 25.8 26.3 26.8 27.3 27.9 28.4 28.9 29.5 30.0 30.5 31.1 DAC 1 DAC 2 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 7.9 8.0 8.2 8.3 8.4 8.6 8.7 8.8 9.0 9.1 9.2 9.4 9.5 9.6 9.7 9.9 1 15.8 16.1 16.3 16.6 16.8 17.1 17.4 17.6 17.9 18.2 18.4 18.7 19.0 19.2 19.5 19.8 2 23.7 24.1 24.5 24.9 25.3 25.7 26.1 26.5 26.9 27.3 27.7 28.1 28.4 28.8 29.2 29.6 3 31.6 32.1 32.6 33.2 33.7 34.2 34.8 35.3 35.8 36.3 36.9 37.4 37.9 38.5 39.0 39.5 DAC 1 DAC 2 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 0 10.0 10.1 10.3 10.4 10.5 10.7 10.8 10.9 11.1 11.2 11.3 11.5 11.6 11.7 11.9 12.0 1 20.0 20.3 20.6 20.8 21.1 21.3 21.6 21.9 22.1 22.4 22.7 22.9 23.2 23.5 23.7 24.0 2 30.0 30.4 30.8 31.2 31.6 32.0 32.4 32.8 33.2 33.6 34.0 34.4 34.8 35.2 35.6 36.0 3 40.0 40.6 41.1 41.6 42.2 42.7 43.2 43.8 44.3 44.8 45.3 45.9 46.4 46.9 47.5 48.0 DAC 1 DAC 2 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 0 12.1 12.3 12.4 12.5 12.7 12.8 12.9 13.1 13.2 13.3 13.5 13.6 13.7 13.8 14.0 14.1 1 24.3 24.5 24.8 25.1 25.3 25.6 25.8 26.1 26.4 26.6 26.9 27.2 27.4 27.7 28.0 28.2 2 36.4 36.8 37.2 37.6 38.0 38.4 38.8 39.2 39.6 40.0 40.4 40.8 41.2 41.5 41.9 42.3 3 48.5 49.0 49.6 50.1 50.6 51.2 51.7 52.2 52.7 53.3 53.8 54.3 54.9 55.4 55.9 56.5 Note: If the second decimal is less than five, round off to the first decimal place. If the second decimal is more than five, round up to the first decimal place. 23 2004-05-12 TB62719AF Temperature detection function (can be monitored via the ALARM1 pin.) Perform two-stage temperature detection as described in the table below (TSD1/TSD2). Junction Temperature C ALARM1 Output Terminals OUT (15:0) Function -40 to 120 OFF (high impedance) Normal operation 120 to ON (low level) Normal operation 140 to ON (low level) Forced OFF (high impedance) When the chip temperature reaches the specified range the ALARM1 signal goes Low (TSD1), Other functions are not affected. When the chip temperature reaches the specified range the ALARM1 signal goes Low and all output pins are turned OFF (TSD2). Outputs are re-enabled on the TSENA signal goes Low or when the RESET signal goes Low. Neither of these causes the internal data to be reset. If RESET pin = L, all internal data is reset. Output-Open Detection Function (can be monitored via the ALARM2 pin.) Reform output-open detection as described in the table below. Output Voltage V (typ.) ALARM2 Function > = VDD x 0.04 OFF (high impedance) < = VDD x 0.04 ON (low level) The output-open condition is detected when the ARARM2 pin signal is ON and the specified voltage level is detected. (it is also detected when the output voltage falls to near GND for some reason) Pulse Cancellation Circuit (when monitored using output-open detection pin ARARM2.) PWMCLK ALARM2 Function Input signal Operating Output open detection operates when the LED string is disconnected for the specified period. No input Always high impedance The device incorporates pulse cancel circuit to avoid detecting instantaneous errors, for example, output switching noise. However, if there is no input on PWMCLK, ALARM2 output will not be turned ON (low level). 24 2004-05-12 TB62719AF Block Diagram of Protection Circuit RESET Output-OFF condition is released and internal data is reset. Output ON LED TEST Release of output OFF on positive edge TSENA ConstantCurrent Output ALARM1 (Open Drain) ALARM2 (Open Drain) Output OFF TSD2 TSD1 Pulse cancel Output-open detection Continue one, open condition is detected. 16 OUT00 to OUT15 Protection Circuit Function Operating Chart (terminals for TESNA, ALARM1 and outputs OUT00 to OUT15) Junction Temperature TSD2 TSD1 Tj < = 120C 140 < 120 < = Tj = Tj ALARM1 OUT00 to OUT15 high impedance OFF Device reset H high impedance OFF Outputs operate normally. X L ON (low level) OFF Device reset X H ON (low level) Normal operation X L ON (low level) Even after a reset, if the junction Forced OFF temperature is high, outputs are forced OFF. X H ON (low level) ALARM1 goes Low, indicating a Forced OFF rise in temperature. Outputs are forced OFF. TSENA RESET X L X Function ALARM1 goes Low, indicating a rise in temperature. Outputs operate normally. Note: The internal operation of the TSD circuit is independent of the TSENA and RESET pin voltage levels. When pins TSENA and RESET are High, the forced OFF mode by the TSD circuit can not be canceled. 25 2004-05-12 TB62719AF Serial Data Input Timing Chart BLANK Output ON Output OFF RESET SI DATA Data of DAC3 for OUT 15 Data of DAC3 for OUT 00 x8 x8 Data of DAC1 to 2 x8 SI CLK SI LATCH SI SEL Selects input of standard current adjustment data. Selects input of each dot adjustment data. SO DATA The data read with 1st time The data read with 1st time SO DATA outputs standard current SO DATA outputs each dot adjustment data. Note 10: Serial data input has no effect on the ON/OFF state of the outputs. When the SI LATCH signal holds the serial data, the output current values and output pulse width are affected. Parallel Data Input Timing Chart Output OFF & data hold BLANK Output ON & data transfer Output ON & data transfer RESET DOE PWM data for OUT 15 PWM data for OUT 00 PI DATA [7:0] for total dot adjustment PI CLK 16 Times 1 Time PI LATCH Holds PWM data, output-ON data and total dot adjustment data. Selects input of total dot adjustment Selects input of PWM data and output-ON data. PI SEL PO DATA 00 t o High-Impedance Selects input of PWM data and output-ON data. High-Impedance The data read with 1st time The data read with 1st time PO DATA 00~PODATA 07 output PWM data. PO DATA 00~PODATA 07 output PWM data. PO DATA 00~PODATA 07 output total dot adjustment data. OUT 00 to OUT 15 Output ON (output-OFF if PWM data = 0) OFF Starts output of PWM data after synchronizing with rising edge of BLANK. Note 11: The BLANK signal has not effect on parallel data input. The PWM pulse can be controlled using the BLANK signal. It is recommended that, on completion of data transfer, BLANK be set to High and outputs be turned OFF. 26 2004-05-12 TB62719AF PWM Operating Timing Chart and All Bit Adjustment Using Division by PWMCLK Output OFF, data hold Output OFF, data change Output can be turned ON. BLANK Output can be turned ON. RESET OUT 00 to OUT 15 ON OFF ON tBLANK (8) tBLANK (7) tBLANK (6) PWMCLK division tBLANK (5) tBLANK (4) tBLANK (6) = (1/ (6/8PWMCLK) ) x 256 tBLANK (5) = (1/ (5/8PWMCLK) ) x 256 tBLANK (4) = (1/ (4/8PWMCLK) ) x 256 tBLANK (3) = (1/ (3/8PWMCLK) ) x 256 tBLANK (2) tBLANK (2) = (1/ (2/8PWMCLK) ) x 256 Maximum PWM control time tBLANK (1) = (1/ (1/8PWMCLK) ) x 256 tBLANK (1) OUT 00 to 15 PWM data = 01 H PWMCLK8 OUT 00 to 15 PWM data = 80 H PWMCLK8 OUT 00 to 15 PWM data = FE H PWMCLK8 Minimum PWM control time tBLANK (8) = (1/ (8/8PWMCLK) ) x 256 tBLANK (7) = (1/ (7/8PWMCLK) ) x 256 tBLANK (3) OUT 00 to 15 PWM data = 00 H OFF Output OFF because data is 00H though it can on. Because data is 01 H output is ON with 1/255 of tBLANK. Because data is 80 H output is ON with 128/255 of tBLANK. Because data is 80 H output is ON with 254/255 of tBLANK. Note 12: PWM operation timing: PWM pulse output on the output pins is initiated when BLANK goes Low. (there is simultaneous output on all 16 pins) Output pulse only once toward BLANK signal's changing once in L from H. Hence, if PWM data is to be re-used, BLANK must be pulled Low again. PWMCLK division: As shown in the central part of the upper figure, the brightness of the LED module can be set to any one of eight levels without adjusting the current value, simply by dividing by PWMCLK. For large-scale brightness adjustment, division by PWMCLK is recommended. 27 2004-05-12 TB62719AF Logic Input and Output Timing Waveforms 1. PI CLK (SI CLK) vs PI DATA [7:0] (SI DATA) PI CLK (SI CLK) vs PO DATA [7:0] (SO DATA) twH PI CLK (SI CLK) PI DATA [7:0] (SI DATA) 50% twL 50% 50% 50% 50% thold tsetup PO DATA [7:0] (SO DATA) 50% 50% tpd tpd 2. PI SEL (SI SEL) vs PI CLK (SI CLK) twH PI CLK (SI CLK) 50% twL 50% 50% PI DATA [7:0] (SI DATA) PI SEL (SI SEL) 50% 50% tsetup 50% thold tsetup 28 50% thold 2004-05-12 TB62719AF 3. PI LATCH (SI LATCH) vs PI CLK (SI CLK) twH PI CLK (SI CLK) twL 50% 50% 50% PI DATA [7:0] (SI DATA) (INTERNAL FLIP/ FLOP DATA) tsetup PI LATCH (SI LATCH) thold 50% 50% twltH 50% twltL 4. PI SEL (SI SEL) vs PO DATA [7:0] (SO DATA) PI SEL (SI SEL) 50% 50% PO DATA [7:0] (SO DATA) 50% 50% tpd tpd 5. DOE vs PO DATA [7:0] DOE 50% 50% PO DATA [7:0] tpzH/zL 29 tpzH/zL 2004-05-12 TB62719AF Logic Input and Constant-current Output Timing Waveforms 1. BLANK vs OUT [15:0] with PWMCLK twblkL BLANK 50% twblkH 50% 50% 50% PWMCLK Maximum delay time is 1 PWMCLK cycle. OUT [15:0] (current waveform) Maximum delay time is 1 PMCLK cycle. 50% 50% tpLH tpHL 2. RESET vs OUT [15:0] BLANK twrstL RESET 50% 50% OUT [15:0] (current waveform) 50% tpHL 3. LED TEST vs OUT [15:0] LED TEST 50% 50% tpLH OUT [15:0] (current waveform) 50% 30 50% 2004-05-12 TB62719AF Package Dimensions Weight: 0.26 g (typ.) 31 2004-05-12 TB62719AF Notes on Contents 1. Block Diagrams Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. Timing Charts Timing charts may be simplified for explanatory purposes. 4. Application Circuits The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. Test Circuits Components in the test circuits are used only to obtain and confirm the device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. 32 2004-05-12 TB62719AF IC Usage Considerations Notes on Handling of ICs (1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. (2) Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. (3) If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition. (4) Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. In addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. (5) Carefully select external components (such as inputs and negative feedback capacitors) and load components (such as speakers), for example, power amp and regulator. If there is a large amount of leakage current such as input or negative feedback condenser, the IC output DC voltage will increase. If this output voltage is connected to a speaker with low input withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied Load (BTL) connection type IC that inputs output DC voltage to a speaker directly. 33 2004-05-12 TB62719AF Points to Remember on Handling of ICs (1) Thermal Shutdown Circuit Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal shutdown circuits operate against the over temperature, clear the heat generation status immediately. Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the thermal shutdown circuit to not operate properly or IC breakdown before operation. (2) Heat Radiation Design In using an IC with large current flow such as power amp, regulator or driver, please design the device so that heat is appropriately radiated, not to exceed the specified junction temperature (Tj) at any time and condition. These ICs generate heat even during normal use. An inadequate IC heat radiation design can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown. In addition, please design the device taking into considerate the effect of IC heat radiation with peripheral components. (3) Back-EMF When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor's power supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the device's motor power supply and output pins might be exposed to conditions beyond maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in system design. 34 2004-05-12 TB62719AF RESTRICTIONS ON PRODUCT USE 060116EBA * The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C * The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E 35 2004-05-12