www.fairchildsemi.com TDC1035 Monolithic Peak Digitizer 8-Bit, 30ns Full Response Peak Width Features Description * * * * * * * * * * * * * The TDC1035 is a unique variant of the full-parallel ("flash") analog-to-digital converter, capable of capturing the maximum peak amplitude of one or more pulses applied to its input between asynchronous reset pulses. Multiple "peak read" operations can be performed between resets. Peaks are detected digitally, so operation is stable and predictable. Packaged in a 24-pin CERDIP, the TDC1035 features lower power consumption and smaller size than an analog peak detector/ADC combination. All digital inputs and outputs are TTL compatible, and all outputs are registered and three-state. 8-bit resolution Full DC linearity for pulses--30ns wide Does not require analog peak-hold circuit Continuous peak capture between resets Multiple read operations between resets 1/2 LSB linearity Narrow ambiguity region around reset Detects pulses as small as 12ns wide Guaranteed monotonic Selectable data format Available in 24-pin CERDIP and 28-lead PLCC packages 1.0W power consumption Three-state registered outputs Applications * * * * Radar pulse classification Electronic countermeasures Radiation measurement Instrumentation Block Diagram VRT R/2 + - 0 VIN R R R 1 2 + 252 - + 253 - + 254 - R/2 VRB Q S Q R Q S Q R Q + - R Q R + - R S RESET S Q R Q S Q R Q S Q R Q MAX 8 BIT OUTPUT REGISTER CLK TS0 65-1035-01 Rev. 1.0.0 TDC1035 Functional Description PRODUCT SPECIFICATION input signal slew rate to 250V/ms. This corresponds to a full-scale transition time of 8ns. General Information The TDC1035 peak detector operates on ground-referenced negative-going signals. Within tRP nanoseconds after the rising edge of the clock signal CLK, it outputs the most negative value reached since the previous RESET pulse. The active-HIGH RESET control is independent of CLK, but may be connected to CLK to provide a single-control peak detector. Multiple output cycles are permitted between reset operations. The TDC1035 contains parallel array of comparators, an array of latches, and an encoder which outputs the location of the highest-valued latch which is set. The TDC1035's response characteristics are determined by its comparator array. A comparator's response time is determined by the degree of overdrive, since the output changes only when the area above threshold reaches a characteristic value. Therefore, the digitization accuracy of a pulse's peak value depends on the shape of the pulse. To permit accurate, repeatable characterization, the TDC1035 is tested with a slew-rate limited "square" pulse. It will digitize (to its DC accuracy) the peak value of a square pulse having a minimum duration of 30ns. The accuracy degrades gracefully as the duration decreases from 30 down to 12ns, where it understates the applied amplitude by 15% (see Figure 5). Production characterization of the TDC1035 uses "square" pulses with controlled rise and fall times of 8ns. Performance of the TDC1035 with other pulse shapes (such as Gaussian or bandwidth-limited square pulse) can be estimated by applying an energy above threshold model, with area of 120 picoVolt-seconds. The operation of all asynchronous sequential logic circuits involves some temporal ambiguity. The most common form of this ambiguity, metastability, occurs in data synchronizers. In a peak digitizer such as the TDC1035, this ambiguity comes in the form of periods during which the accuracy of the measurement of a pulse may be affected, or the pulse may not even be detected. There is a 10ns (tRP) ambiguity period after the falling edge of the RESET signal, during which detection or accuracy of detection of any pulse is not guaranteed. There is also a region of 40ns (tPC) before the rising edge of the (output) clock (CLK) where a pulse may be missed or detected inaccurately. These regions are shown in the timing diagrams, Figure 1 and Figure 2. During the latter period, if the input signal increases to a new peak larger than the previously latched value, the value loaded into the output register may be incorrect (and will most likely be zero); nonetheless, the peak detection latches will hold the (correct) new peak value. As shown in Figure 3, the TDC1035's comparator inputs have emitter-follower buffers, which limit the permissible 2 Power The TDC1035 operates from two supply voltages: +5.0V and -5.2V. The current return for the positive supply is DGND, and the return for the negative (analog) supply is AGND. All power and ground pins MUST be connected. Reference The reference for the TDC1035 is a negative voltage applied across a chain of 255 resistors. The top of this chain is connected to the RT pin, and the voltage applied to the RT pin (VRT) should be within 0.1V of the analog ground. Note that the difference between the voltage applied to the pin and the voltage at the reference chain is the offset specification (EOT and EOB). The bottom of the reference resistor chain is connected to the RB pin, and the voltage applied to the RB pin (VRB) should be between 1.8 and 2.2V negative with respect to the RT pin for full-specification operation. Reduced reference voltage operation is possible at reduced accuracy (for example, for generating a nonlinear transfer function). The RT-RB reference source should be able to deliver at least 45mA. Due to the variation in the reference currents with clock and input signals, RT and RB should be connected to circuit nodes with a low impedance to ground. For circuits in which the reference is not varied at a high rate, a bypass capacitor to ground is recommended. If the reference inputs are exercised dynamically (e.g., for AGC or nonlinear operation), a low-impedance reference source is required. The reference voltages may be varied dynamically; contact the factory for information on limitations when the device is used in this mode. The performance of the TDC1035 is specified with DC references of VRT = 0.0V and VRB = -2.0V. Control Two function control pins, MINV and LINV, are provided. These names stand for active-LOW Most significant bit INVert and active-LOW Least significant bits INVert, respectively These controls are for DC (i.e., steadystate), not dynamic, use. They permit the output coding to be either straight binary or offset two's complement, in either true or inverted sense, according to the Output Coding Table. A single output state control pin, OE, is provided. The three-state outputs may be placed in a high-impedance state by applying a logic HIGH to the OE control pin, and enabled by driving OE LOW. The function control pins may be tied to VCC for a logic HIGH, and DGND for a logic LOW; however, a 2.2 kOhm pull-up resistor is preferred over direct connection to VCC. If a pull-up resistor is not used, the absolute maximum voltage rating for the part becomes that of the TTL input, 5.5V, rather than the higher value for the VCC terminal. PRODUCT SPECIFICATION TDC1035 Command Two pins, RESET and CLK, control the TDC1035. When brought HIGH, the level-sensitive RESET control resets the peak-storing latches. The edge-sensitive CLK control causes the peak value to be loaded into the output register when a rising-edge (LOW-to-HIGH) signal is applied. As noted above, there is a data ambiguity period associated with the operation of each of these inputs. Analog Input Although the TDC1035's 255 comparators have emitterfollower isolated inputs, the input impedance can vary up to 25 percent with the signal level, as comparator input transistors switch on or off. As a result, for optimal performance, the source impedance of the driving device must be less than 25 Ohms. The input signal will not damage the TDC1035 if it remains in the range VEE-0.5V to VAGND+0.5V. If the input signal stays between the VRT and VRB reference voltages, the 8-bit digital equivalent of the most negative voltage reached will be latched into the array of latches, subject to the dynamic effects mentioned above. A transient more negative than VRB will cause a full-scale output tDO after the CLK line rises. Outputs The outputs of the TDC1035 are TTL compatible, capable of driving four low-power Schottky TTL (54LS/74LS) unit loads or the equivalent. The outputs hold the previous data a minimum time tHO after the rising edge of the CLK input, and are guaranteed to have the new output value after a maximum time tDO. Under light DC load conditions (such as driving CMOS loads or base-input low-power Schottky such as the 74L5374) 2.2k pull-up resistors to +5.0V are recommended. Pin Assignments 28 Lead PLCC VIN AGND RT 21 20 19 D7 D1 (MSB) 1 15 D6 D2 2 14 D5 D3 3 13 LINV D4 4 12 DGND DGND 10 15 AGND RT RESET D8 (LSB) LINV D5 11 14 D7 12 13 D6 VEE 16 11 28 NC D8 MINV 10 16 RESET 17 VCC 9 NC VEE 22 17 18 27 9 8 NC 18 23 7 RMID VIN 26 8 19 RB OE CLK VEE CLK VCC 6 RMID 20 24 DGND 5 RB AGND 7 21 VEE 22 4 AGND 3 D4 MINV OE 6 23 5 24 2 NC 1 DGND D1 (MSB) D2 D3 25 24 Lead Ceramic DIP 65-1035-02 65-1035-03 3 TDC1035 PRODUCT SPECIFICATION Pin Definitions Pin Number Pin Name Ceramic DIP PLCC Value Pin Function Description VCC 8 9 +5.0V Positive Supply Voltage VEE 6,9 7,11 -5.2v Negative Supply Voltage DGND 5,10 5,12 0.0V Digital Ground AGND 18, 21 20, 25 0.0V Analog Ground RT 17 19 0.0V Reference Resistor, Top RMID 20 24 -1.0V Reference Resistor, Middle RB 22 26 -2.0V Reference Resistor, Bottom MINV 24 28 TTL (Active LOW) MSB Invert LINV 11 13 TTL (Active LOW) LSB Invert OE 23 27 TTL (Active LOW) Output Enable RESET 16 18 TTL (Active HIGH) Resets Peak Value to Zero CLK 7 8 TTL (Rising Edge) Loads Output Register 19 21 0.0V to -2.0V D1 1 1 TTL D2 2 2 TTL D3 3 3 TTL D4 4 4 TTL D5 12 14 TTL Power Reference Control Command Analog Input VIN Analog Input Signal Outputs D6 13 15 TTL D7 14 16 TTL D8 15 17 TTL MSB Output LSB Output Absolute Maximum Ratings1 (beyond which the device may be damaged) Parameter Min. Max. Unit VCC (measured to DGND) -0.5 +7.0 V VEE (measured to DGND) -7.0 +0.5 V AGND (measured to DGND) -0.5 +0.5 V Supply Voltages Input Voltages RESET, CLK, OE, MINV, LINV (measured to AGND) VIN, VRT, VRB (measured to AGND) VRT (measured to VRB) 4 -0.5 +5.5 V VEE - 0.5 +0.5 V -2.2 +2.2 V PRODUCT SPECIFICATION TDC1035 Absolute Maximum Ratings1 (continued) (beyond which the device may be damaged) Parameter Min. Max. Unit -0.5 +0.5 V -1.0 6.0 mA 1 Second +125 C +175 C +300 C +150 C Outputs Applied voltage (measured to DGND)2 Applied current (externally forced)3,4 Short-circuit duration (single output HIGH to shorted to ground) Temperature Operating Ambient -55 Junction Lead, soldering (10 seconds) Storage -65 Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. Device performance is guaranteed only if specified operating conditions are met. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as positive current flowing into the device. Operating Conditions Temperature Range Standard Parameter Min. Extended Nom. Max. Min. Nom. Max. Units VCC Positive Supply Voltage 4.75 5.0 5.25 4.50 5.0 5.5 V VEE Negative Supply Voltage -4.90 -5.2 -5.5 -4.90 -5.2 -5.5 V VAGND Analog Ground Voltage -0.1 0.0 0.1 -0.1 0.0 0.1 V tPWHR Reset Minimum Pulse Width, HIGH 20 20 ns tPWLC CLK Minimum Pulse Width, LOW 20 20 ns tPWHC CLK Minimum Pulse Width, HIGH 20 SR Input Signal Slew Rate 250 250 V/mS VIL Input Voltage, Logic LOW 0.8 0.8 V VIH Input Voltage, Logic HIGH lOL Output Current, Logic LOW 4.0 mA 20 2.0 ns 2.0 V 4.0 IOH Output Current, Logic HIGH -400 mA VRT Reterence Voltage, Top -0.1 0.0 0.1 -0.1 0.0 0.1 V VRB Reference Voltage, Bottom -1.8 -2.0 -2.2 -1.8 -2.0 -2.2 V VRT- Reference Voltage Span 1.8 2.0 2.2 1.8 2.0 2.2 V VIN Input Voltage Range VRT VRB VRT VRB V TA Ambient Temperature, Still Air 0 70 TC Case Temperature -55 +125 -400 C C 5 TDC1035 PRODUCT SPECIFICATION DC Electrical Characteristics Temperature Range Standard Parameter Test Conditions Min. Max. Extended Min. Max. Units ICC Positive Supply Current VCC = Max, Static 35 35 mA IEE Negative Supply Current VEE = Max, Static -160 -160 mA IREF Reference Current VRT-VRB = Nom 35 35 mA RREF Reference Resistance Total, RT to RB 57 57 Ohms RIN Input Equivalent Resistance (DC) VRT, VRB = Nom, VIN = VRB 50 50 kOhms CIN Input Capacitance, Analog VRT, VRB = Nom, VIN = VRB 50 50 pF ICB Input Constant Bias Current VEE = Max 250 350 mA IIL Input Current Logic LOW VCC = Max, VIL = 0.4V -500 -500 mA IIH Input Current Logic HIGH VCC = Max, VIH = 2.4V 50 50 mA IIM Input Current, VlN = Max VCC = Max, VIH = 5.5V 1 1 mA IOZL Hi-Z Output Leakage Current, Output LOW VCC = Max, VO = 0V -30 30 -30 30 mA IOZH Hi-Z Output Leakage Current, Output HIGH VCC = Max, VO = 5V -30 30 -30 30 mA IOS Short-Circuit Output1 VCC = Max, Output HIGH, one output tied to DGND for 1 second. -50 -50 mA VOL Output Voltage, Logic LOW VCC = Max, lOL = Max 0.5 0.5 V VOH Output Voltage, Logic HIGH VCC = Min, IOH = Max CIN Input Capacitance, Digital 2.4 2.4 10 V 10 pF Note: 1. Worst case all digtal inputs and outputs LOW. AC Electrical Characteristics Temperature Range Standard Parameter Test Conditions Max. Min. Max. Units tPC CLK Setup Time VCC = Min, VEE = Min, Load 1 30 30 ns tRP RESET Delay VCC = Min, VEE = Min, Load 1 5 5 ns tDO Output Delay VCC = Min, VEE = Min, Load 1 35 35 ns tHO Output Hold Time VCC = Min, VEE = Min, Load 1 tDIS Output Disable Time VCC = Min, VEE = Min, Load 1 20 20 ns tENA Output Enable Time VCC = Min, VEE = Min, Load 1 70 90 ns Note: 1. tRP and tPC are the guaranteed maximum lengths of the ambiguity periods. 6 Min. Extended 5 5 ns PRODUCT SPECIFICATION TDC1035 Timing Diagrams tRP ANALOG INPUT tMIN tPC FULL SCALE PEAK N 8ns RESET tRP ANALOG INPUT 8ns RESET & CLK tPWHR CLK PEAK N-1 PEAK N tPC FULL SCALE PEAK N 8ns tPWHR, tPWHR tPWHC DATA tMIN 8ns tPWHC PEAK N-1 DATA tHO PEAK N tHO tDO tDO 65-1035-04 Figure 1. Timing with Separate RESET and CLK 65-1035-05 Figure 2. Timing with Common RESET and CLK System Performance Characteristics Temperature Range Standard Extended Parameter Test Conditions Min. Max. Min. Max. ELI Linearity Error, Integral, Independent VRT, VRB = Nom 0.2 0.2 %FS ELD Linearity Error, Differential VRT, VRB = Nom 0.2 0.2 %FS CS Code Size VRT, VRB = Nom 170 % Nominal tMIN Analog Input Pulse Width Square Pulse EOT Offset Error, Top VIN = VRT 8 8 mV EOB Offset Error, Bottom VIN = VRB 15 15 mV TCO Offset Error, Temperature VRT, VRB, VCC, Coefficent VEE = Nom 20 20 mV/C 30 15% Accuracy 12 DC Accuracy 30 170 30 12 Units ns 30 ns 7 TDC1035 PRODUCT SPECIFICATION Equivalent Circuits VIN ICB CIN RIN VIN VRB VEEA CIN IS A NONLINEAR JUNCTION CAPACITANCE VRB IS A VOLTAGE EQUAL TO THE VOLTAGE ON PIN RB VEE REFERENCE VEE RESISTOR CHAIN VEE Figure 3. Simplified Analog Input Equivalent Circuits VCC 30K 20K INPUT 65-1035-08 Figure 4. Digital Input Equivalent Circuit BITS 1/2 LSB ACCURACY Performance Curve 8 8 8 8 10 65-1035-06 15 20 25 30 PULSE WIDTH (ns at 50%) Figure 5. Variation of Accuracy as a Function of Width, "Square" Input Pulse 8 65-1035-07 PRODUCT SPECIFICATION TDC1035 Output Coding Binary Offset Two's Complement True Inverted True Inverted -2.0000V FS 7.8431mV Step -2.0000V FS 8.000mV Step MINV = 1 LINV = 1 0 0 0 1 1 0 000 0.0000V 0.0000V 00000000 11111111 10000000 01111111 001 -0.0078V -0.0080V 00000001 11111110 10000001 01111110 * * * * * * * * * * * * * * * * * * * * * 127 -0.9922V -1.0160V 01111111 10000000 11111111 00000000 128 -1.0000V -1.0240V 10000000 01111111 00000000 11111111 129 -1.0078V -1.0320V 10000001 01111110 00000001 11111110 * * * * * * * * * * * * * * * * * * * * * 254 -1.9844V -2.0240V 11111110 00000001 01111110 10000001 255 -1.9922V -2.0320V 11111111 00000000 01111111 10000000 Range Step Applications Discussion Under certain conditions, the real component of the input impedance may go negative at frequencies near 100MHz. To prevent oscillation at the input signal port, Fairchild recommends connecting the input signal to the TDC1035 via a series-connected resistor of at least 10 Ohms located close to the device. Further, if the signal bandwidth is not already limited so that the input slew rate limit is not exceeded, external circuitry is also recommended. The circuit shown in Figure 7 accomplishes both goals. VCC VCC 8101/2 1601/2 TO OUTPUT PIN OUTPUT ALL DIODES 1N3062 40pF LOAD 1 65-1035-09 Figure 6. Output Circuits 751/2 VIDEO OPERATIONAL AMPLIFIER 101/2 TDC1035 VIN 16pF 65-1035-10 Figure 7. Recommended Input Circuit 9 TDC1035 PRODUCT SPECIFICATION Mechanical Dimensions 24 Lead Ceramic DIP Symbol Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. -- .225 .014 .023 .045 .065 .008 .015 -- 1.290 .500 .610 .100 BSC .600 BSC .120 .200 .015 .075 .005 -- 90 105 Notes: Millimeters Min. Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. Max. -- 5.72 .36 .58 1.14 1.65 .20 .38 -- 32.77 12.70 15.49 2.54 BSC 15.24 BSC 3.05 5.08 .38 1.91 .13 -- 90 105 8 2, 8 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 12, 13 and 24 only. 8 4 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4 5, 9 7 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 24. 6. Applies to all four corners (leads number 1, 12, 13, and 24). 3 6 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Twenty-two spaces. D NOTE 1 E s1 e eA Q A a L b2 10 b1 c1 PRODUCT SPECIFICATION TDC1035 Mechanical Dimensions 28 Lead PLCC Inches Symbol Min. A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Max. .165 .180 .090 .120 .020 -- .013 .021 .026 .032 .485 .495 .450 .456 .300 BSC .050 BSC .042 .048 7 28 -- .004 Notes: Millimeters Min. Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 Max. 4.19 4.57 2.29 3.05 .51 -- .33 .53 .66 .81 12.32 12.57 11.43 11.58 7.62 BSC 1.27 BSC 1.07 1.22 7 28 -- 0.10 2. Corner and edge chamfer (J) = 45 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm) 3 2 E E1 D J D1 D3/E3 B1 J e A A1 A2 B -C- LEAD COPLANARITY ccc C 11 PRODUCT SPECIFICATION TDC1035 Ordering Information Product Number Temperature Range TDC1035B7C STD-TA = 0C to 70C TDC1035B7V EXT-TC = -55C to 125C TDC1035R3C TA = 0C to 70C Screening Package Package Marking Commercial 24 Lead Ceramic DIP 1035B7C MIL-STD-833 24 Lead Ceramic DIP 1035B7V Commercial 28 Lead PLCC 1035R3C LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 5/20/98 0.0m 001 Stock# DS90001035 O 1998 Fairchild Semiconductor Corporation