www.fairchildsemi.com
Features
• 8-bit resolution
• Full DC linearity for pulses—30ns wide
• Does not require analog peak-hold circuit
• Continuous peak capture between resets
• Multiple read operations between resets
• 1/2 LSB linearity
• Narrow ambiguity region around reset
• Detects pulses as small as 12ns wide
• Guaranteed monotonic
• Selectable data format
• Available in 24-pin CERDIP and 28-lead PLCC packages
• 1.0W power consumption
• Three-state registered outputs
Applications
• Radar pulse classification
• Electronic countermeasures
• Radiation measurement
• Instrumentation
Description
The TDC1035 is a unique variant of the full-parallel
(“flash”) analog-to-digital con verter , capable of capturing the
maximum peak amplitude of one or more pulses applied to
its input between asynchronous reset pulses. Multiple “peak
read” operations can be performed between resets. Peaks are
detected digitally, so operation is stable and predictable.
Packaged in a 24-pin CERDIP, the TDC1035 features lower
power consumption and smaller size than an analog peak
detector/ADC combination. All digital inputs and outputs are
TTL compatible, and all outputs are registered and
three-state.
Block Diagram
+
–Q
Q
S
0
R
+
–Q
Q
S
1
R
+
–Q
Q
S
2
R
+
–Q
Q
S
252
R
+
–Q
Q
S
253
RESET
R/2
R/2
R
R
R
R
R
CLK
MAX
VRT
VRB
VIN
REGISTER
TS0
R
+
–Q
Q
S
254
8 BIT
OUTPUT
R
65-1035-01
TDC1035
Monolithic Peak Digitizer
8-Bit, 30ns Full Response Peak Width
Rev. 1.0.0
TDC1035 PRODUCT SPECIFICATION
2
Functional Description
General Information
The TDC1035 peak detector operates on ground-referenced
negative-going signals. Within t
RP
nanoseconds after the
rising edge of the clock signal CLK, it outputs the most
negative value reached since the previous RESET pulse.
The active-HIGH RESET control is independent of CLK,
but may be connected to CLK to provide a single-control
peak detector. Multiple output cycles are permitted between
reset operations.
The TDC1035 contains parallel array of comparators, an
array of latches, and an encoder which outputs the location
of the highest-valued latch which is set. The TDC1035’s
response characteristics are determined by its comparator
array. A comparator’s response time is determined by the
degree of overdrive, since the output changes only when the
area above threshold reaches a characteristic value. There-
fore, the digitization accuracy of a pulse’s peak value
depends on the shape of the pulse.
To permit accurate, repeatable characterization, the
TDC1035 is tested with a slew-rate limited “square” pulse.
It will digitize (to its DC accuracy) the peak value of a
square pulse having a minimum duration of 30ns. The
accuracy degrades gracefully as the duration decreases from
30 down to 12ns, where it understates the applied amplitude
by 15% (see Figure 5). Production characterization of the
TDC1035 uses “square” pulses with controlled rise and
fall times of 8ns.
Performance of the TDC1035 with other pulse shapes (such
as Gaussian or bandwidth-limited square pulse) can be
estimated by applying an energy above threshold model,
with area of 120 picoVolt-seconds.
The operation of all asynchronous sequential logic circuits
involves some temporal ambiguity. The most common form
of this ambiguity , metastability , occurs in data synchronizers.
In a peak digitizer such as the TDC1035, this ambiguity
comes in the form of periods during which the accuracy of
the measurement of a pulse may be affected, or the pulse
may not even be detected. There is a 10ns (t
RP
) ambiguity
period after the falling edge of the RESET signal, during
which detection or accuracy of detection of any pulse is not
guaranteed. There is also a region of 40ns (t
PC
) before the
rising edge of the (output) clock (CLK) where a pulse may
be missed or detected inaccurately. These regions are shown
in the timing diagrams, Figure 1 and Figure 2. During the
latter period, if the input signal increases to a new peak
larger than the previously latched value, the value loaded
into the output register may be incorrect (and will most
likely be zero); nonetheless, the peak detection latches will
hold the (correct) new peak value.
As shown in Figure 3, the TDC1035’s comparator inputs
have emitter-follower buffers, which limit the permissible
input signal slew rate to 250V/
m
s. This corresponds to a
full-scale transition time of 8ns.
Power
The TDC1035 operates from two supply voltages: +5.0V
and -5.2V. The current return for the positive supply is
D
GND
, and the return for the negative (analog) supply is
A
GND
. All power and ground pins MUST be connected.
Reference
The reference for the TDC1035 is a ne gative v oltage applied
across a chain of 255 resistors. The top of this chain is
connected to the R
T
pin, and the voltage applied to the R
T
pin (V
RT
) should be within 0.1V of the analog ground. Note
that the difference between the v oltage applied to the pin and
the voltage at the reference chain is the offset specification
(E
OT
and E
OB
). The bottom of the reference resistor chain is
connected to the R
B
pin, and the voltage applied to the R
B
pin (V
RB
) should be between 1.8 and 2.2V negative with
respect to the R
T
pin for full-specification operation.
Reduced reference voltage operation is possible at reduced
accuracy (for example, for generating a nonlinear transfer
function). The R
T
–R
B
reference source should be able to
deliver at least 45mA.
Due to the variation in the reference currents with clock and
input signals, R
T
and R
B
should be connected to circuit
nodes with a low impedance to ground. F or circuits in which
the reference is not varied at a high rate, a bypass capacitor
to ground is recommended. If the reference inputs are
exercised dynamically (e.g., for AGC or nonlinear opera-
tion), a low-impedance reference source is required. The ref-
erence voltages may be varied dynamically; contact the
factory for information on limitations when the device is
used in this mode. The performance of the TDC1035 is spec-
ified with DC references of V
RT
= 0.0V and V
RB
= -2.0V.
Control
Two function control pins, MINV and LINV, are provided.
These names stand for active-LOW Most significant bit
INVert and active-LOW Least significant bits INVert,
respectiv ely These controls are for DC (i.e., steadystate), not
dynamic, use. They permit the output coding to be either
straight binary or offset two’s complement, in either true
or inverted sense, according to the Output Coding Table.
A single output state control pin, OE, is provided. The
three-state outputs may be placed in a high-impedance state
by applying a logic HIGH to the OE control pin, and enabled
by driving OE LOW.
The function control pins may be tied to V
CC
for a logic
HIGH, and D
GND
for a logic LOW; however, a 2.2 kOhm
pull-up resistor is preferred over direct connection to V
CC
.
If a pull-up resistor is not used, the absolute maximum volt-
age rating for the part becomes that of the TTL input, 5.5V,
rather than the higher value for the V
CC
terminal.
PRODUCT SPECIFICATION TDC1035
3
Command
Two pins, RESET and CLK, control the TDC1035. When
brought HIGH, the level-sensitive RESET control resets the
peak-storing latches. The edge-sensiti v e CLK control causes
the peak value to be loaded into the output register when a
rising-edge (LOW-to-HIGH) signal is applied. As noted
above, there is a data ambiguity period associated with the
operation of each of these inputs.
Analog Input
Although the TDC1035’s 255 comparators have emitter-
follower isolated inputs, the input impedance can vary up to
25 percent with the signal level, as comparator input transis-
tors switch on or off. As a result, for optimal performance,
the source impedance of the driving device must be less than
25 Ohms. The input signal will not damage the TDC1035 if
it remains in the range V
EE
–0.5V to V
AGND
+0.5V. If the
input signal stays between the V
RT
and V
RB
reference
voltages, the 8-bit digital equivalent of the most negative
voltage reached will be latched into the array of latches,
subject to the dynamic effects mentioned above. A transient
more negative than V
RB
will cause a full-scale output t
DO
after the CLK line rises.
Outputs
The outputs of the TDC1035 are TTL compatible, capable of
driving four low-power Schottky TTL (54LS/74LS) unit
loads or the equivalent. The outputs hold the previous data a
minimum time t
HO
after the rising edge of the CLK input,
and are guaranteed to have the new output value after a
maximum time t
DO
. Under light DC load conditions (such
as driving CMOS loads or base-input low-power Schottky
such as the 74L5374) 2.2k pull-up resistors to +5.0V are
recommended.
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
D1 (MSB)
D2
D3
D4
DGND
VEE
CLK
VCC
VEE
DGND
LINV
D5
MINV
OE
RB
AGND
RMID
VIN
AGND
RT
RESET
D8 (LSB)
D7
D6
65-1035-02
24 Lead Ceramic DIP
18
17
16
15
14
13
12
26
27
28
1
2
3
4
RESET
D8
D7
D6
D5
LINV
DGND
RB
OE
MINV
D1 (MSB)
D2
D3
D4
25
24
23
22
21
20
19
AGND
RMID
NC
NC
VIN
AGND
RT
5
6
7
8
9
10
11
DGND
NC
VEE
CLK
VCC
NC
VEE
65-1035-03
28 Lead PLCC
TDC1035 PRODUCT SPECIFICATION
4
Pin Definitions
Pin Name
Pin Number
Value Pin Function DescriptionCeramic DIP PLCC
Power
V
CC
8 9 +5.0V Positive Supply Voltage
V
EE
6,9 7,11 -5.2v Negative Supply Voltage
D
GND
5,10 5,12 0.0V Digital Ground
A
GND
18, 21 20, 25 0.0V Analog Ground
Reference
R
T
17 19 0.0V Reference Resistor, Top
R
MID
20 24 -1.0V Reference Resistor, Middle
R
B
22 26 -2.0V Reference Resistor, Bottom
Control
MINV 24 28 TTL (Active LOW) MSB Invert
LINV 11 13 TTL (Active LOW) LSB Invert
OE 23 27 TTL (Active LOW) Output Enable
Command
RESET 16 18 TTL (Active HIGH) Resets Peak Value to Zero
CLK 7 8 TTL (Rising Edge) Loads Output Register
Analog Input
V
IN
19 21 0.0V to -2.0V Analog Input Signal
Outputs
D
1
1 1 TTL MSB Output
D
2
2 2 TTL
D
3
3 3 TTL
D
4
4 4 TTL
D
5
12 14 TTL
D
6
13 15 TTL
D
7
14 16 TTL
D
8
15 17 TTL LSB Output
Absolute Maximum Ratings
1
(beyond which the device may be damaged)
Parameter Min. Max. Unit
Supply V oltages
V
CC
(measured to D
GND
) -0.5 +7.0 V
V
EE
(measured to D
GND
) -7.0 +0.5 V
A
GND
(measured to D
GND
) -0.5 +0.5 V
Input V oltages
RESET, CLK, OE, MINV, LINV (measured to A
GND
) -0.5 +5.5 V
V
IN
, V
RT
, V
RB
(measured to A
GND
)V
EE
– 0.5 +0.5 V
V
RT
(measured to V
RB
) -2.2 +2.2 V
PRODUCT SPECIFICATION TDC1035
5
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating
conditions. Functional operation under any of these conditions is NOT implied. Device performance is guaranteed only if
specified operating conditions are met.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as positive current flowing into the device.
Operating Conditions
Outputs
Applied voltage (measured to D
GND
)
2
-0.5 +0.5 V
Applied current (externally forced)
3,4
-1.0 6.0 mA
Short-circuit duration (single output HIGH to shorted to ground) 1 Second
Temperature
Operating Ambient -55 +125
°
C
Junction +175
°
C
Lead, soldering (10 seconds) +300
°
C
Storage -65 +150
°
C
Parameter
Temperature Range
Units
Standard Extended
Min. Nom. Max. Min. Nom. Max.
V
CC
Positive Supply Voltage 4.75 5.0 5.25 4.50 5.0 5.5 V
V
EE Negative Supply Voltage -4.90 -5.2 -5.5 -4.90 -5.2 -5.5 V
VAGND Analog Ground Voltage -0.1 0.0 0.1 -0.1 0.0 0.1 V
tPWHR Reset Minimum Pulse Width, HIGH 20 20 ns
tPWLC CLK Minimum Pulse Width, LOW 20 20 ns
tPWHC CLK Minimum Pulse Width, HIGH 20 20 ns
SRInput Signal Slew Rate 250 250 V/mS
VIL Input Voltage, Logic LOW 0.8 0.8 V
VIH Input Voltage, Logic HIGH 2.0 2.0 V
lOL Output Current, Logic LOW 4.0 4.0 mA
IOH Output Current, Logic HIGH -400 -400 mA
VRT Reterence Voltage, Top -0.1 0.0 0.1 -0.1 0.0 0.1 V
VRB Reference Voltage, Bottom -1.8 -2.0 -2.2 -1.8 -2.0 -2.2 V
VRT– Reference Voltage Span 1.8 2.0 2.2 1.8 2.0 2.2 V
VIN Input Voltage Range VRT VRB VRT VRB V
TAAmbient Temperature, Still Air 0 70 °C
TCCase Temperature -55 +125 °C
Absolute Maximum Ratings1 (continued)
(beyond which the device may be damaged)
Parameter Min. Max. Unit
TDC1035 PRODUCT SPECIFICATION
6
DC Electrical Characteristics
Note:
1. Worst case all digtal inputs and outputs LOW.
AC Electrical Characteristics
Note:
1. tRP and tPC are the guaranteed maximum lengths of the ambiguity periods.
Parameter Test Conditions
Temperature Range
Units
Standard Extended
Min. Max. Min. Max.
ICC Positive Supply Current VCC = Max, Static 35 35 mA
IEE Negative Supply Current VEE = Max, Static -160 -160 mA
IREF Reference Current VRT–VRB = Nom 35 35 mA
RREF Reference Resistance Total, RT to RB57 57 Ohms
RIN Input Equivalent Resistance
(DC) VRT, VRB = Nom, VIN = VRB 50 50 kOhms
CIN Input Capacitance, Analog VRT, VRB = Nom, VIN = VRB 50 50 pF
ICB Input Constant Bias Current VEE = Max 250 350 mA
IIL Input Current Logic LOW VCC = Max, VIL = 0.4V -500 -500 mA
IIH Input Current Logic HIGH VCC = Max, VIH = 2.4V 50 50 mA
IIM Input Current, VlN = Max VCC = Max, VIH = 5.5V 1 1 mA
IOZL Hi-Z Output Leakage Current,
Output LOW VCC = Max, VO = 0V -30 30 -30 30 mA
IOZH Hi-Z Output Leakage Current,
Output HIGH VCC = Max, VO = 5V -30 30 -30 30 mA
IOS Short-Circuit Output1VCC = Max, Output HIGH, one
output tied to DGND for 1
second.
-50 -50 mA
VOL Output Voltage, Logic LOW VCC = Max, lOL = Max 0.5 0.5 V
VOH Output Voltage, Logic HIGH VCC = Min, IOH = Max 2.4 2.4 V
CIN Input Capacitance, Digital 10 10 pF
Parameter Test Conditions
Temperature Range
Units
Standard Extended
Min. Max. Min. Max.
tPC CLK Setup Time VCC = Min, VEE = Min, Load 1 30 30 ns
tRP RESET Delay VCC = Min, VEE = Min, Load 1 5 5 ns
tDO Output Delay VCC = Min, VEE = Min, Load 1 35 35 ns
tHO Output Hold Time VCC = Min, VEE = Min, Load 1 5 5 ns
tDIS Output Disable Time VCC = Min, VEE = Min, Load 1 20 20 ns
tENA Output Enable Time VCC = Min, VEE = Min, Load 1 70 90 ns
PRODUCT SPECIFICATION TDC1035
7
Timing Diagrams
Figure 1. Timing with Separate RESET and CLK Figure 2. Timing with Common RESET and CLK
System Performance Characteristics
Parameter Test Conditions
Temperature Range
Units
Standard Extended
Min. Max. Min. Max.
ELI Linearity Error, Integral,
Independent VRT, VRB = Nom 0.2 0.2 %FS
ELD Linearity Error,
Differential VRT, VRB = Nom 0.2 0.2 %FS
CS Code Size VRT, VRB = Nom 30 170 30 170 % Nominal
tMIN Analog Input Pulse
Width Square Pulse 15% Accuracy 12 12 ns
DC Accuracy 30 30 ns
EOT Offset Error, Top VIN = VRT ±8±8mV
EOB Offset Error, Bottom VIN = VRB ±15 ±15 mV
TCO Offset Error, Temperature
Coefficent VRT, VRB, VCC,
VEE = Nom ±20 ±20 mV/°C
ANALOG
INPUT
RESET
FULL SCALE
PEAK N
PEAK
N
8ns 8ns
PEAK N-1
CLK
tRP tMIN
tPWHR
tPWHC
tHO tDO
tPC
DATA
65-1035-04
PEAK N
FULL SCALE
PEAK
N
PEAK N-1
8ns 8ns
tRP tMIN
tPWHR,
tPWHR tPWHC
tHO tDO
tPC
ANALOG
INPUT
RESET
& CLK
DATA
65-1035-05
TDC1035 PRODUCT SPECIFICATION
8
Equivalent Circuits
Figure 3. Simplified Analog Input Equivalent Circuits
Figure 4. Digital Input Equivalent Circuit
Performance Curve
Figure 5. Variation of Accuracy as a Function of Width, “Square” Input Pulse
VIN
VEE
VEE VEE
VIN
CIN
CIN IS A NONLINEAR JUNCTION CAPACITANCE
VRB IS A VOLTAGE EQUAL TO THE VOLTAGE ON PIN RB
VEEA
ICB RIN
VRB
REFERENCE
RESISTOR
CHAIN 65-1035-07
VCC
INPUT
20K30K
65-1035-08
PULSE WIDTH (ns at 50%)
BITS 1/2 LSB ACCURACY
8
8
8
810 15 20 25 30 65-1035-06
PRODUCT SPECIFICATION TDC1035
9
Output Coding
Step
Range
Binary Offset Two’s Complement
True Inverted True Inverted
-2.0000V FS
7.8431mV Step -2.0000V FS
8.000mV Step MINV = 1
LINV = 1 0
00
11
0
000 0.0000V 0.0000V 00000000 11111111 10000000 01111111
001 -0.0078V -0.0080V 00000001 11111110 10000001 01111110
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
127 -0.9922V -1.0160V 01111111 10000000 11111111 00000000
128 -1.0000V -1.0240V 10000000 01111111 00000000 11111111
129 -1.0078V -1.0320V 10000001 01111110 00000001 11111110
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
254 -1.9844V -2.0240V 11111110 00000001 01111110 10000001
255 -1.9922V -2.0320V 11111111 00000000 01111111 10000000
Applications Discussion
Under certain conditions, the real component of the input
impedance may go negati v e at frequencies near 100MHz. To
prevent oscillation at the input signal port, Fairchild recom-
mends connecting the input signal to the TDC1035 via a
series-connected resistor of at least 10 Ohms located close to
the device. Further, if the signal bandwidth is not already
limited so that the input slew rate limit is not exceeded,
external circuitry is also recommended. The circuit sho wn in
Figure 7 accomplishes both goals.
Figure 6. Output Circuits Figure 7. Recommended Input Circuit
VCC
VCC
OUTPUT 40pF ALL
DIODES
1N3062
LOAD 1
810½
160½TO
OUTPUT
PIN
65-1035-09
VIN
16pF
75½10½TDC1035
VIDEO
OPERATIONAL
AMPLIFIER 65-1035-10
TDC1035 PRODUCT SPECIFICATION
10
Mechanical Dimensions
24 Lead Ceramic DIP
NOTE 1
D
s1
b2
e
b1
E
Q
A
L
eA
c1
a
A — .225 — 5.72
Symbol Inches
Min. Max. Min. Max.
Millimeters Notes
b1 .014 .023 .36 .58
.065 1.65
b2 .045 1.14
c1 .008 .015 .20 .38
E .500 .610 12.70 15.49
e.100 BSC 2.54 BSC
L .120 .200 3.05 5.08
.015 .075 .38 1.91
.005 — .13 — 3
6
8
4
8
2, 8
4
5, 9
eA .600 BSC 15.24 BSC 7
Q
s1 90¡105¡90¡105¡
a
D — 1.290 — 32.77
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
The minimum limit for dimension "b2" may be .023 (.58mm) for leads
number 1, 12, 13 and 24 only.
Dimension "Q" shall be measured from the seating plane to the base
plane.
This dimension allows for off-center lid, meniscus and glass overrun.
The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 24.
Applies to all four corners (leads number 1, 12, 13, and 24).
"eA" shall be measured at the center of the lead bends or at the
centerline of the leads when "a" is 90¡.
All leads – Increase maximum limit by .003 (.08mm) measured at the
center of the flat, when lead finish applied.
Twenty-two spaces.
PRODUCT SPECIFICATION TDC1035
11
Mechanical Dimensions
28 Lead PLCC
D
e
E
A .165 .180 4.19 4.57
Symbol Inches
Min. Max. Min. Max.
Millimeters Notes
E1 J
D1
AA1
A2 B
B1
D3/E3
J
– C –
ccc C
LEAD COPLANARITY
A1 .090 .120 2.29 3.05
A2 .020 .51——
B .013 .021 .33 .53
D/E .485 .495 12.32 12.57
D1/E1 .450 .456 11.43 11.58
D3/E3 .300 BSC 7.62 BSC
e .050 BSC 1.27 BSC
J .042 .048 1.07 1.22 2
3
ND/NE 7 7
N28 28
ccc .004 0.10——
B1 .026 .032 .66 .81
Notes:
1.
2.
3.
All dimensions and tolerances conform to ANSI Y14.5M-1982
Corner and edge chamfer (J) = 45¡
Dimension D1 and E1 do not include mold protrusion. Allowable
protrusion is .101" (.25mm)
PRODUCT SPECIFICATION TDC1035
5/20/98 0.0m 001
Stock# DS90001035
Ó 1998 Fairchild Semiconductor Corporation
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1.Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2.A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Ordering Information
Product Number Temperature Range Screening Package Package Marking
TDC1035B7C STD–TA = 0°C to 70°C Commercial 24 Lead
Ceramic DIP 1035B7C
TDC1035B7V EXT–TC = -55°C to 125°C MIL-STD-833 24 Lead
Ceramic DIP 1035B7V
TDC1035R3C TA = 0°C to 70°C Commercial 28 Lead PLCC 1035R3C
