UC1709, UC2709, UC3709
DUAL HIGH-SPEED FET DRIVER
SLUS196B -- NOVEMBER 1996 -- REVISED MARCH 2004
1
www.ti.com
D
1.5 Amp Source/Sink Drive
D
Pin Compatible with 0026 Products
D
40 ns Rise and Fall into 1000pF
D
Low Quiescent Current
D
5 V to 40 V Operation
D
Thermal Protection
description
The UC3709 family of power drivers is an
effective low-cost solution to the problem of
providing fast turn-on and off for the
capacitive gates of power MOSFETs. Made
with a high-speed Schottky process, these
devices will provide up to 1.5 A of either
source or sink current from a totem--pole
output stage configured for minimal
cross-conduction current spike.
The UC3709 is pin compatible with the
MMH0026 or DS0026, and while the delay
times are longer, the supply current is much
less than these older devices.
With inverting logic, these units feature complete TTL compatibility at the inputs with an output stage that can
swing over 30 V. This design also includes thermal shutdown protection.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†}
}}
}
Parameter DW PACKAGE J PACKAGE L PACKAGE N PACKAGE UNIT
Supply Voltage, V
CC
40 40 40 40 V
Output Current (Source or Sink)
Steady--State........ ±500 ±500 ±500 ±500 mA
Peak Transient........ ±1.5 ±1.0 ±1.0 ±1.5 A
Capacitive Discharge Energy........ 20 15 15 20 mJ
Digital Inputs}5.5 5.5 5.5 5.5 V
Power Dissipation at T
A
=25°C 1 1 1 1 W
Power Dissipation at T
C
=25°C 3 2 2 3 W
Operating Junction Temperature Range (T
J
)--55 to 125 --55 to 125 --55 to 125 --55 to 125 °C
Storage Temperature Range --65 to 150 --65 to 150 --65 to 150 --65 to 150 °C
Lead Temperature (Soldering, 10 Seconds) 300 300 300 300 °C
†
Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice. Thesearestressratingsonly,and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡
All currents are positive into and negative out of the specified terminals. Digital drive can exceed 5.5V if input is limited to 10A. Consult the
Packaging Section of the Databook for thermal limitations and considerations of the package.
Copyright 2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
simplified schematic (only one driver shown)
5 VOLT
REGULATOR THERMAL
SENSE
6 k
5.6 V
INPUT
A OR B
INPUT
A OR B
GND
V
CC
UDG--00068
UC1709, UC2709, UC3709
DUAL HIGH-SPEED FET DRIVER
SLUS196B -- NOVEMBER 1996 -- REVISED MARCH 2004
2www.ti.com
THERMAL RESISTANCE TABLE
PACKAGE θjc(°C/W) θja(°C/W)
SOIC--16 (DW) 20
(1)
35 to 58
(3)
DIL--16 (J) 28
(2)
125 to 160
LCC--16 (L) 20
(2)
70 to 80
DIL--16 (N) 45 90
(3)
NOTES: (1) Specified thermal resistance is θjl (junction to lead)where noted.
(2) θjcdatavaluesstatedwerederivedfromMIL-STD-1835B.MIL-STD-1835Bstates,“Thebaselinevalues
shownareworstcase(mean+2s)fora60x60milmicrocircuitdevicesilicondieandapplicablefordevices
with die sizes up to 14400 square mils. For device die sizes greater than 14400 square mils use the
following values; dual-in-line, 11°C/W; flat pack, .10°C/W; pin grid array, 10°C/W”.
(3) Specifiedθja(junctiontoambient)isfordevicesmountedto5-inch
2
FR4PCboardwithoneouncecopper
wherenoted.Whenresistancerangeisgiven,lowervaluesarefor5inch
2
aluminumPCboard.TestPWB
was 0.062 inch thick and typically used 0.635-mm trace widths for power packages and 1.3-mm trace
widths for non-power packages with a 100-mil x 100-mil probe land area at the end of each trace.
1
2
3
4
8
7
6
5
N/C
INPUT A
GROUND
INPUT B
N/C
OUTPUT A
V
CC
OUTPUT B
8 PIN DIL N OR J PACKAGE
(TOP VIEW)
N/C -- No internal connection
V
CC
N/C
N/C
N/C
OUTPUT B
INPUT B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
N/C
N/C
GROUND
INPUT A
N/C
N/C
OUTPUT A
N/C
N/C
N/C
10
9
SOIC--16 (TOP VIEW)
DW PACKAGE
LCC--20 (TOP VIEW)
L PACKAGES
3
18
17
16
N/C
122019
15
14
4
5
6
7
891110 12 13
N/C
INPUT A
OUTPUT A
N/C
N/C
N/C
V
CC
N/C
N/C
N/C
N/C
GROUND
N/C
N/C
N/C
OUT PUT B
N/C
INPUT B
N/C
UC1709, UC2709, UC3709
DUAL HIGH-SPEED FET DRIVER
SLUS196B -- NOVEMBER 1996 -- REVISED MARCH 2004
3
www.ti.com
electrical characteristics over recommended operating free-air temperature range, T
A
=55°
°°
°Cto
125°
°°
°C for the UC1709, --40°
°°
°Cto85°
°°
°C for the UC2709, and 0°
°°
°Cto70°
°°
°C for the UC3709;
V
CC
=20V,T
A
=T
J.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
S
u
p
p
l
y
c
u
r
r
e
n
t
Both outputs low 10 12 mA
Supply current Both outputs high 710 mA
Logic 0 input voltage 0.8 V
Logic 1 input voltage 2.2 V
Input current V
I
=0 -- 0. 6 -- 1.0 mA
Input leakage V
I
=5V 0.05 0.1 mA
O
u
t
p
u
t
h
i
g
h
s
a
t
u
r
a
t
i
o
n
V
V
I
O
=--50mA 1.5 2.0 V
Output high saturation V
CC
-- V
O
I
O
= --500 mA 2.0 2.5 V
O
u
t
p
u
t
l
o
w
s
a
t
u
r
a
t
i
o
n
V
I
O
=50mA 0.1 0.4 V
Output low saturation V
O
I
O
= 500 mA 2.0 2.5 V
Thermal shutdown 155 mA
typical switching characteristics, V
CC
=20V,T
A
=25°
°°
°C, delays measured to 10% output change
P
A
R
A
E
T
E
R
T
E
S
T
C
O
N
D
I
T
I
O
N
S
OUTPUT C
L
=
U
N
I
T
S
P
A
R
A
METER TEST CONDITIONS 0nF 2.2 nF UNITS
Rise time delay 80 80 ns
10% to 90% rise 20 40 ns
Fall time delay 60 80 ns
10% to 90% fall 20 40 ns
VCC cross--conduction Output rise 25 ns
V
C
C
c
r
o
s
s
--
c
o
n
d
u
c
t
i
o
n
curent spike duration Output fall 0ns
NOTE: Refer to UC1705 specifications for further information.
UC1709, UC2709, UC3709
DUAL HIGH-SPEED FET DRIVER
SLUS196B -- NOVEMBER 1996 -- REVISED MARCH 2004
4www.ti.com
APPLICATION INFORMATION
D1, D2: UC3611 Schottky Diodes
Figure 1. Power bipolar drive circuit.
D1, D2: UC3611 Schottky Diodes
Figure 2. Power MOSFET drive circuit.
Figure 3. Charge pump circuits.
UC1709, UC2709, UC3709
DUAL HIGH-SPEED FET DRIVER
SLUS196B -- NOVEMBER 1996 -- REVISED MARCH 2004
5
www.ti.com
D1, D2: UC3611 Schottky Diodes
Figure 4. Transformer coupled push--pull MOSFET drive circuit.
D1, D2: UC3611 Schottky Diodes
Figure 5. Power MOSFET drive circuit using negative bias voltage
and level shifting to ground referenced PWM
UC1709, UC2709, UC3709
DUAL HIGH-SPEED FET DRIVER
SLUS196B -- NOVEMBER 1996 -- REVISED MARCH 2004
6www.ti.com
D1, D2: UC3611 Schottky Diodes
Figure 6. Transformer coupled MOSFET drive circuit.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-0151201VPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
UC1709J ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
UC1709J883B ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
UC1709L ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
UC1709L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
UC2709DW ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC2709DWG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC2709N ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
UC2709NG4 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
UC3709DW ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC3709DWG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC3709DWTR ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC3709DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC3709J ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type
UC3709N ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
UC3709NG4 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
PACKAGE OPTION ADDENDUM
www.ti.com 5-Feb-2007
Addendum-Page 1
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Feb-2007
Addendum-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE
8
4
0.015 (0,38)
Gage Plane
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
MAX
0.430 (10,92)
4040082/D 05/98
0.200 (5,08) MAX
0.125 (3,18) MIN
5
0.355 (9,02)
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.400 (10,60)
1
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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