Audio Dual Matched PNP Transistor
Data Sheet
SSM2220
Rev. C Document Feedback
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FEATURES
Low voltage noise at 100 Hz, 1 nV/√Hz maximum
High gain bandwidth: 190 MHz typical
Gain at IC = 1 mA, 165 typical
Tight gain matching: 3% maximum
Outstanding logarithmic conformance: rBE = 0.3 Ω typical
Low offset voltage: 200 μV maximum
APPLICATIONS
Microphone preamplifiers
Tape head preamplifiers
Current sources and mirrors
Low noise precision instrumentation
Voltage controlled amplifiers/multipliers
PIN CONNECTION DIAGRAM
C1
1
B
12
E
13
NC
4
C
2
8
B
2
7
E
2
6
NC
5
SSM2220
TOP VI EW
(No t t o Scal e)
03096-001
NOTES
1. NC = NO CONNECT. THI S P IN I S
NOT CONNE CTED INT E RNALL Y .
Figure 1.
GENERAL DESCRIPTION
The SSM2220 is a dual, low noise, matched PNP transistor, which
has been optimized for use in audio applications.
The ultralow input voltage noise of the SSM2220 is typically only
0.7 nV/√Hz over the entire audio bandwidth of 20 Hz to 20 kHz.
The low noise, high bandwidth (190 MHz), and offset voltage of
(200 μV maximum) make the SSM2220 an ideal choice for demand
ing, low noise preamplifier applications.
The SSM2220 also offers excellent matching of the current gain
(ΔhFE) to about 0.5%, which helps to reduce the high order ampli-
fier harmonic distortion. In addition, to ensure the long-term
stability of the matching parameters, internal protection diodes
across the base to emitter junction were used to clamp any reverse
base to emitter junction potential. This prevents a base to emitter
breakdown condition, which can result in degradation of gain and
matching performance due to excessive breakdown current.
Another feature of the SSM2220 is its very low bulk resistance
of 0.3 Ω typical, which assures accurate logarithmic conformance.
The SSM2220 is offered in 8-lead plastic dual inline (PDIP) and
8-lead standard small outline (SOIC), and its performance and
characteristics are guaranteed over the extended industrial temper-
ature range of −40°C to +85°C.
SSM2220 Data Sheet
Rev. C | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Connection Diagram ................................................................ 1
General Description ......................................................................... 1
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Typical Performance Characteristics ..............................................5
Applications Information .................................................................8
Super Low Noise Amplifier ..........................................................8
Low Noise Microphone Preamplifier .........................................9
Noise Measurement ................................................................... 10
Current Sources .......................................................................... 10
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
4/13—Re v. B to Re v. C
Updated Format .................................................................. Universal
Changes to Features Section and Figure 1 ..................................... 1
Change to Endnote 2 and Endnote 4, Table 1 ............................... 3
Changed Breakdown Voltage Parameter, Table 2
to Breakdown Voltage (Collector to Emitter), Table 2 ................ 3
Changes to Table 3 ............................................................................ 4
Changes to Figure 8 Caption, Figure 9 Caption,
and Figure 12 ..................................................................................... 6
Change to Figure 15 ......................................................................... 7
Changes to Super Low Noise Amplifier Section, Figure 16, and
Figure 17 Caption ............................................................................. 8
Change to Figure 18 ......................................................................... 9
Changes to Figure 19 and Noise Measurement Section ............ 10
Changes to Current Sources and Current
Matching Sections .......................................................................... 11
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 12
11/03—Re v. A to R ev. B
Changes to Ordering Guide ............................................................. 1
Updated Outline Dimensions .......................................................... 9
Data Sheet SSM2220
Rev. C | Page 3 of 12
SPECIFICATIONS
TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CURRENT GAIN1 hFE VCB = 0 V to 36 V
80 165 IC = 1 mA
70 150 IC = 100 μA
60 120 IC = 10 μA
Current Gain Matching2 ΔhFE 0.5 6 % IC = 100 μA, VCB = 0 V
NOISE VOLTAGE DENSITY3 en IC = 1 mA, VCB = 0 V
0.8 2 nV/√Hz fO = 10 Hz
0.7 1 nV/√Hz fO = 100 Hz
0.7 1 nV/√Hz fO = 1 kHz
0.7 1 nV/√Hz fO = 10 kHz
OFFSET VOLTAGE4 VOS 40 200 μV VCB = 0 V, IC = 100 μA
Offset Voltage Change vs. Collector Voltage ΔVOS/ΔVCB 11 200 μV IC = 100 μA, VCB1 = 0 V, VCB2 = −36 V
Offset Voltage Change vs. Collector Current ΔVOS/ΔIC 12 75 μV VCB = 0 V, IC1 = 10 μA, IC2 = 1 mA
OFFSET CURRENT IOS 6 45 nA IC = 100 μA, VCB = 0 V
COLLECTOR TO BASE LEAKAGE CURRENT ICBO 50 400 pA VCB = −36 V = VMAX
BULK RESISTANCE rBE 0.3 0.75 Ω VCB = 0 V, 10 μA ≤ IC ≤ 1 mA
COLLECTOR SATURATION VOLTAGE VCE(SAT) 0.026 0.1 V IC = 1 mA, IB = 100 μA
1 Current gain is measured at collector to base voltages (VCB) swept from 0 V to VMAX at indicated collector current. Typicals are measured at VCB = 0 V.
2 Current gain matching (ΔhFE) is defined as follows:
ΔhFE =
C
FEB
I
hI
min
))((100 ∆
3 Sample tested. Noise tested and specified as equivalent input voltage for each transistor.
4 Offset voltage is defined as follows:
VOS = VBE1 – VBE2 =
C2
C1
I
I
q
KT ln
where VOS is the differential voltage for IC1 = IC2.
ELECTRICAL CHARACTERISTICS
−40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CURRENT GAIN hFE VCB = 0 V to 36 V
60 125 IC = 1 mA
50 105 IC = 100 μA
40
90
I
C
= 10 μA
OFFSET VOLTAGE VOS 30 265 μV IC = 100 μA, VCB = 0 V
Offset Voltage Drift1 TCVOS 0.3 1.0 μV/°C IC = 100 μA, VCB = 0 V
OFFSET CURRENT IOS 10 200 nA IC = 100 μA, VCB = 0 V
BREAKDOWN VOLTAGE (COLLECTOR TO EMITTER) BVCEO 36 V
1 Guaranteed by VOS test (TCVOS = VOS/T for VOS << VBE), where T = 298K for TA = 25°C.
SSM2220 Data Sheet
Rev. C | Page 4 of 12
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Breakdown Voltage of
Collector to Base Voltage (BVCBO) 36 V
Collector to Emitter Voltage (BVCEO) 36 V
Collector to Collector Voltage (BVCC) 36 V
Emitter to Emitter Voltage (BVEE) 36 V
Current
Collector (IC) 20 mA
Emitter (I
E
)
20 mA
Temperature Range
Operating –40°C to +85°C
Storage –65°C to +150°C
Junction –65°C to +150°C
Lead Temperature (Soldering, 60 sec) +300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 4.
Package Type θJA1 θJC Unit
8-Lead PDIP 103 43 °C/W
8-Lead SOIC 158 43 °C/W
1 θJA is specified for worst-case mounting conditions; that is, θJA is specified for a
device in a socket for the PDIP package, and a device soldered to a printed
circuit board for SOIC packages.
ESD CAUTION
Data Sheet SSM2220
Rev. C | Page 5 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
0V
40nV
–40nV
1s
20mV
V
CE
= 5V
I
C
= 1mA
T
A
= 25° C
VERTICAL = 40nV/DI V
HORIZONTAL = 1s/DIV
03096-002
Figure 2. Low Frequency Noise
14
0
2
4
6
8
10
12
0.001 0.01 0.1 1
NOISE FIGURE (dB)
COLLE CTO R CURRE NT (mA)
R
S
= 1kΩ
R
S
= 10kΩ
R
S
= 100kΩ
V
CE
= 5V
f = 1kHz
03096-003
Figure 3. Noise Figure vs. Collector Current
0.5
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
10–8 10–3
10–4
10–5
10–6
10–7
LOGGING ERROR (mV)
COLLE CTO R CURRE NT (A)
TA = 25° C
VCB = 0V
03096-004
Figure 4. Emitter to Base Log Conformity
250
0
50
100
150
200
110 100 1000
TOTAL NOISE (nV Hz)
COLLE CTO R CURRE NT (µ A)
T
A
= 25° C
V
CB
= 0V
R
S
= 1kΩ
R
S
= 10kΩ
R
S
= 100kΩ
R
S
R
S
f = 1kHz
03096-005
Figure 5. Total Noise vs. Collector Current
6
5
4
3
2
1
0036912
NOISE VOL T AGE DENSITY (n V Hz)
COLLE CTO R CURRE NT (mA)
T
A
= 25° C
V
CB
= 0V
10Hz
100Hz
03096-006
Figure 6. Noise Voltage Density vs. Collector Current
1k
0.1
1
10
100
0.1 100k10k1k100101
NOISE VOL T AGE DENSITY (n V Hz)
FRE QUENCY ( Hz )
TA = 25° C
VCB = 0V
IC = 10µA
IC = 100µA
IC = 1mA
03096-007
Figure 7. Noise Voltage Density vs. Frequency
SSM2220 Data Sheet
Rev. C | Page 6 of 12
300
250
200
150
100
50
010 1000
100
CURRENT GAIN ( h
FE
)
COLLE CTO R CURRE NT (µ A)
V
CB
= 0V
+125°C
+25°C
–55°C
03096-008
Figure 8. Current Gain (hFE) vs. Collector Current
700
600
500
400
300
200
100
0
–55 –35 –15 525 45 65 85 105 125
CURRENT GAIN ( hFE)
TEMPERATURE (°C)
IC = 1mA
VCB = –36V
VCB = 0V
03096-009
Figure 9. Current Gain (hFE) vs. Temperature
1k
0.1
1
10
100
0.001 10010
10.10.01
f
T
– UNITY-GAI N BANDWI DTH PRODUCT ( M Hz )
COLLE CTO R CURRE NT (mA)
T
A
= 25° C
V
CB
= 0V
03096-010
Figure 10. Gain Bandwidth vs. Collector Current
10
0.01
0.1
1
0.01 1010.1
SATURATION VOLTAGE (V)
COLLE CTO R CURRE NT (mA)
+125°C
+25°C
–55°C
03096-011
Figure 11. Saturation Voltage vs. Collector Current
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35 1100001000
10010
BASE TO EMITTER VOLTAGE, V
BE
(V)
COLLE CTO R CURRE NT (µ A)
T
A
= 25° C
03096-012
Figure 12. Base to Emitter Voltage (VBE) vs. Collector Current
50
40
30
20
10
00–35–30–25–20–15
–10–5
CAPACI TANCE (pF )
COLLECTOR-BASE VOLTAGE (V)
T
A
= 25° C
03096-013
Figure 13. Collector to Base Capacitance vs. VCB
Data Sheet SSM2220
Rev. C | Page 7 of 12
1M
1k
10k
100k
1100010010
h
ie
– SMALL-SIGNAL INPUT RESISTANCE (Ω)
COLLE CTO R CURRE NT (µ A)
T
A
= 25° C
03096-014
Figure 14. Small Signal Input Resistance (hie) vs. Collector Current
100
0.01
0.1
1
10
1100010010
OUTPUT CONDUCT ANCE , hoe ( µm)
COLLE CTO R CURRE NT (µ A)
TA = 25° C
03096-015
Figure 15. Small Signal Output Conductance (hoe) vs. Collector Current
SSM2220 Data Sheet
Rev. C | Page 8 of 12
APPLICATIONS INFORMATION
5V
A
V
= 10
C
F
= 30pF
20µs
PULSE RESPONSE
A
V
= 1000
V
ERT
= 1nV/DIV
LOW FRE QUENCY NOI SE
10µF
AD8671
2
3
6
7
4
0.01µF
0.01µF
–15V
+15V
V
OUT
Q5 Q2Q3
Q7
Q4Q1 Q6
+ –
83Ω
1.5kΩ
0.01% 1.5kΩ
0.01%
27kΩ
–15V
RED
LED
+15V
–15V
+0.001µF
SSM 2220 P AIRS:
Q1 – Q2
Q3 – Q4
Q5 – Q6
150Ω 0.01µF
+10µF 0.001µF
03096-016
Figure 16. Super Low Noise Amplifier
SUPER LOW NOISE AMPLIFIER
The circuit in Figure 16 is a super low noise amplifier, with equiv-
alent input voltage noise of 0.32 nV/√Hz. By paralleling SSM2220
matched pairs, a reduction of the base spreading resistance by a
factor of 3 results in a further reduction of amplifier noise by a fac-
tor of √3. Additionally, the shot noise contribution is reduced by
maintaining a high collector current (2 mA/device), which reduces
the dynamic emitter resistance and decreases voltage noise. The
voltage noise is inversely proportional to the square root of the
stage current, whereas current noise increases proportionally.
Accordingly, this amplifier capitalizes on voltage noise reduction
techniques at the expense of increasing the current noise. However,
high current noise is not usually important when dealing with
low impedance sources.
This amplifier exhibits excellent full power ac performance,
0.08% THD into a 600 Ω load, making it suitable for exacting
audio applications (see Figure 17).
0.1
0.001
0.01
10
100k
10k1k100
TOTAL HARMONIC DISTORTION (%)
FRE QUENCY ( Hz )
600Ω LOAD
NO LOAD
03096-017
Figure 17. Total Harmonic Distortion vs. Frequency of Circuit in Figure 16
Data Sheet SSM2220
Rev. C | Page 9 of 12
AD8671
2
3
1
8
4
10µF
+
+
0.01µF
0.01µF
10µF
+15V
–15V
V
OUT
LED
Q1
SSM2220
Q2
2N29007A
18
36
27
R1
250Ω
V
IN
R2
27kΩ
R3
5kΩ
R4
5kΩ
R6
100Ω
R5
100Ω
C1
50pF
THD < 0.005% 20Hz TO 20kHz
0.5nV/ Hz
1/f CORNER < 1Hz
03096-018
Figure 18. Low Noise Microphone Preamplifier
LOW NOISE MICROPHONE PREAMPLIFIER
Figure 18 shows a microphone preamplifier that consists of an
SSM2220 and a low noise op amp. The input stage operates at a
relatively high quiescent current of 2 mA per side, which reduces
the SSM2220 transistor voltage noise. The 1/f corner is less than
1 Hz. Total harmonic distortion is under 0.005% for a 10 V p-p
signal from 20 Hz to 20 kHz. The preamp gain is 100, but can be
modified by varying R5 or R6 (VOUT/VIN = R5/R6 + 1). A total
input stage emitter current of 4 mA is provided by Q2. The con-
stant current in Q2 is set by using the forward voltage of a GaAsP
LED as a reference. The difference between this voltage and the
VBE of a silicon transistor is predictable and constant (to a few
percent) over a wide temperature range. The voltage difference,
approximately 1 V, is dropped across the 250 Ω resistor, which
produces a temperature stabilized emitter current.
SSM2220 Data Sheet
Rev. C | Page 10 of 12
e
n
10µF
+
0.1µF
AD8671
2
3
6
7
4
0.01µF
0.01µF
+15V
–15V
AD8671
3
2
6
7
4
0.01µF
0.01µF
+15V
–15V
1kΩ
3 6
12 7 8
SSM2220
3 6
12 7 8
SSM2220
+5V
1kΩ
500Ω
ADJUST P OT
FOR 2mA
(2V ACROSS
1kΩ RES)
SSM2220
DUT
1 8
3 6
2 7
2mA
5kΩ
1% 5kΩ
1%
10Ω
10kΩ
100Ω
2.2pF
10µF
+
0.1µF
5kΩ
–15V
SPOT NOISE FOR
EACH T RANS IST OR = e
n
10,000 × 2
03096-019
Figure 19. Voltage Noise Measurement Circuit
NOISE MEASUREMENT
All resistive components and semiconductor junctions contribute
to the system input noise. Resistive components produce Johnson
noise (en2 = 4kTBR, or en = 0.13√R nV/√Hz, where R is in kΩ). At
semiconductor junctions, shot noise is caused by current flowing
through a junction, producing voltage noise in series impedances
such as transistor collector load resistors (In = 0.556√I pA/√Hz,
where I is in μA).
Figure 19 illustrates a technique for measuring the equivalent
input noise voltage of the SSM2220. A stage current of 1 mA is
used to bias each side of the differential pair. The 5 kΩ collector
resistors noise contribution is insignificant compared to the voltage
noise of the SSM2220. Because noise in the signal path is referred
back to the input, this voltage noise is attenuated by the gain of the
circuit. Consequently, the noise contribution of the collector load
resistors is only 0.048 nV/√Hz. This is considerably less than the
typical 0.8 nV/√Hz input noise voltage of the SSM2220 transistor.
The noise contribution of the AD8671 gain stages is also negligible,
due to the gain in the signal path. The op amp stages amplify the
input referred noise of the transistors, increasing the signal strength
to allow the noise spectral density,
( )
input
n
e
× 10,000, to be meas-
ured with a spectrum analyzer. Because equal noise contributions
from each transistor in the SSM2220 are assumed, the output is
divided by √2 to determine the input noise of a single transistor.
Air currents cause small temperature changes that can appear as
low frequency noise. To eliminate this noise source, the measure-
ment circuit must be thermally isolated. Effects of extraneous noise
sources must also be eliminated by totally shielding the circuit.
SSM2220
SSM2220
+V
R
I
OUT
= I
I = +V – 2V
BE
R
Q4 Q3
Q1 Q2
03096-020
Figure 20. Cascode Current Source
CURRENT SOURCES
A fundamental requirement for accurate current mirrors and active
load stages is matched transistor components. Due to the excellent
VBE matching (the voltage difference between one VBE and another,
which is required to equalize collector current) and gain matching,
the SSM2220 can be used to implement a variety of standard cur-
rent mirrors that can source current into a load such as an amplifier
stage. The advantages of current loads in amplifiers vs. resistors
are an increase of voltage gain due to higher impedances, larger
signal range, and in many applications, a wider signal bandwidth.
Figure 20 illustrates a cascode current mirror consisting of two
SSM2220 transistor pairs.
The cascode current source has a common base transistor in series
with the output, which causes an increase in output impedance of
the current source because VCE stays relatively constant. High fre-
quency characteristics are improved due to a reduction of Miller
capacitance. The small signal output impedance can be determined
Data Sheet SSM2220
Rev. C | Page 11 of 12
by consulting Figure 15. Typical output impedance levels approach
the performance of a perfect current source.
(ro)Q3 =
MΩ1
μMho0.1
1=
Q2 and Q3 are in series and operate at the same current level;
therefore, the total output impedance is as follows:
RO = hFE × (ro)Q3 ≈ (160)(1 MΩ) = 160 MΩ
Current Matching
The objective of current source or mirror design is generation
of currents that either are matched or must maintain a constant
ratio. However, mismatch of base emitter voltages causes output
current errors. Consider the example of Figure 21.
R1 R2
R1 = R2 = R
A CLOSELY M ATCHED
TRANS IST OR PAIR
VB
–
+
IC + ΔIC
2IC – ΔIC
2
03096-021
Figure 21. Current Matching Circuit
If the resistors and transistors are equal and the collector
voltages are the same, then the collector currents match precisely.
Investigating the current matching errors resulting from a nonzero
VOS, ΔIC is defined as the current error between the two transistors.
Figure 22 describes the relationship of current matching errors
vs. offset voltage for a specified average current, IC. Note that
because the relative error between the currents is exponentially
proportional to the offset voltage, tight matching is required to
design high accuracy current sources. For example, if the offset
voltage were 5 mV at 100 μA collector current, the current match-
ing error would be 20%. Additionally, temperature effects, such
as offset drift (3 μV/°C per mV of VOS), degrade performance if
Q1 and Q2 are not well matched.
1.2
1.0
0.8
0.6
0.4
0.2
0
0.001 10
IC = 10µA IC = 100µA
IC = 1mA
10.10.01
ΔIC
IC%
VOS (mV)
SSM 2220 VOS
PERFORMANCE
R = 3kΩ
h
FE
= 200
ΔI= I
C1
– I
C2
I
C
= I
C1
+ I
C2
2
03096-022
Figure 22. Current Matching Accuracy vs. Offset Voltage
SSM2220 Data Sheet
Rev. C | Page 12 of 12
OUTLINE DIMENSIONS
COMPLIANT TO JE DE C S TANDARDS MS - 001
CONTROLLING DIMENSIONSARE IN INCHES; MILLIMET ER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OF F I NCH E QUIVALENTS FOR
REF E RE NCE ONLY AND ARE NO T APPROPRIATE FOR USE IN DESIGN.
CORNE R LEADS MAY BE CONF IG URE D AS WHO LE OR HALF L E ADS .
070606-A
0.022 ( 0.56)
0.018 ( 0.46)
0.014 ( 0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 ( 5.33)
MAX
0.150 ( 3.81)
0.130 ( 3.30)
0.115 (2.92)
0.070 ( 1.78)
0.060 ( 1.52)
0.045 ( 1.14)
8
14
5
0.280 ( 7.11)
0.250 ( 6.35)
0.240 ( 6.10)
0.100 ( 2.54)
BSC
0.400 ( 10.16)
0.365 ( 9.27)
0.355 ( 9.02)
0.060 ( 1.52)
MAX
0.430 ( 10.92)
MAX
0.014 ( 0.36)
0.010 ( 0.25)
0.008 ( 0.20)
0.325 ( 8.26)
0.310 ( 7.87)
0.300 ( 7.62)
0.195 ( 4.95)
0.130 ( 3.30)
0.115 (2.92)
0.015 ( 0.38)
GAUGE
PLANE
0.005 ( 0.13)
MIN
Figure 23. 8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 24. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
SSM2220PZ –40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
SSM2220S –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
SSM2220SZ –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
SSM2220SZ-REEL
–40°C to +85°C
8-Lead Standard Small Outline Package [SOIC_N]
R-8
1 Z = RoHS Compliant Part.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03096-0-4/13(C)
