1
INDUSTRIAL TEMPERATURE RANGE
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
JUNE 2003
2002 Integrated Device Technology, Inc. DSC 5971/10c
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ
• 1:10 fanout
• 3-level inputs for output control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
• No external RC network required for PLL loop stability
• Configurable 2.5V or 3.3V LVTTL outputs
•tPD Phase Error at 100MHz to 166MHz: ±150ps
• Jitter (peak-to-peak) at 133MHz and 166MHz: ±75ps
• Spread spectrum compatible
• Operating Frequency:
−−
−−
−Std: 25MHz to 140MHz
−−
−−
− A: 25MHz to 167MHz
• Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT5V2528 is a high performance, low-skew, low-jitter, phase-lock
loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency
and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
IDT5V2528/A
2.5V / 3.3V PHASE-LOCK
LOOP CLOCK DRIVER
ZERO DELAY BUFFER
19 Y1, VDD pin 21
PLL
3
24
17
16
26
TY0, VDDQ pin 4
13
10
20
12
Y0, VDD pin 21
6
7
5
AVDD
FBIN
CLK
G_Ctrl 28
22 FBOUT, VDD pin 21
T_Ctrl 1
MODE
SELECT
TY1, VDDQ pin 25
TY2, VDDQ pin 25
TY3, VDDQ pin 15
TY4, VDDQ pin 15
TY5, VDDQ pin 11
TY6, VDDQ pin 11
TY7, VDDQ pin 11
The IDT5V2528 inputs, PLL core, Y0, Y1, and FBOUT buffers operate from
the 3.3V VDD and AVDD power supply pins.
One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of
the ten outputs, up to seven may be configured for 2.5V or 3.3V LVTTL
outputs. The number of 2.5V outputs is controlled by 3-level input signals
G_Ctrl and T_Ctrl, and by connecting the appropriate VDDQ pins to 2.5V or
3.3V. The 3-level input signals may be hard-wired to high-mid-low levels.
Output signal duty cycles are adjusted to 50 percent, independent of the duty
cycle at CLK. The outputs can be enabled or disabled via the G_Ctrl input.
When the G_Ctrl input is mid or high, the outputs switch in phase and
frequency with CLK; when the G_Ctrl is low, all outputs (except FBOUT) are
disabled to the logic-low state.
Unlike many products containing PLLs, the IDT5V2528 does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the IDT5V2528 requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as
following any changes to the PLL reference or feedback signals. The PLL
can be bypassed for test purposes by strapping AVDD to ground.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
PIN CONFIGURATION
TSSOP
TOP VIEW
G_Ctrl
GND
TY1
VDDQ
TY2
GND
FBOUT
VDD
Y0
Y1
GND
TY3
VDDQ
TY6
T_Ctrl
GND
TY0
VDDQ
AVDD
CLK
FBIN
AGND
GND
TY7
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
TY4
VDDQ
TY5
GND
18
17
11
12
16
15
13
14
Symbol Rating Max. Unit
VDD, VDDQ, AVDD Supply Voltage Range –0.5 to +4.6 V
VI (2) Input Voltage Range –0.5 to +5.5 V
VO(2) Voltage Range applied to any –0.5 to V
output in the HIGH or LOW state VDD+0.5
IIK (VI < 0) Input Clamp Current –50 mA
IOK Output Clamp Current ±50 mA
(VO < 0 or VO > VDD)
IOContinuous Output Current ±50 mA
(VO = 0 to VDD)
VDD or G N D Continuous Current ±200 mA
TSTG Storage Temperature Range –65 to +150 °C
TJJunction Temperature +150 °C
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2 . The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Min. Typ. Max. Unit
VDD, AVDD (1) Power Supply Voltage 3 3.3 3.6 V
VDDQ (1) Power Supply Voltage 2.5V Outputs 2.3 2.5 2.7 V
3.3V Outputs 3 3.3 3.6
TAAmbient Operating Temperature –40 +25 +85 °C
RECOMMENDED OPERATING RANGE
Symbol Description Min Typ. Max. Unit
CIN Input Capacitance —5—pF
VI = VDD or GND
COOutput Capacitance —6—pF
VI = VDD or GND
CLLoad Capacitance 2.5V outputs —20 —pF
3.3V outputs —30 —
CAPACITANCE(1)
NOTE:
1. Unused inputs must be held HIGH or LOW to prevent them from floating.
NOTE:
1. All power supplies should operate in tandem. If VDD or VDDQ is at a maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
PIN DESCRIPTION
Terminal
Name No. Type Description
CLK(1) 6 I Clock input
FBIN 7 I Feedback input
G_Ctrl(2) 28 3-level 3-level input for 2.5V / 3.3V Output Select/ Output bank enable. When G_Ctrl is LOW, all outputs except FBOUT are disabled
to a logic-LOW state. When G_Ctrl is MID or HIGH, all outputs are enabled and switch at the same frequency as CLK (see
OUTPUT SELECTION table).
T_Ctrl(2) 1 3-level 3-level input for 2.5V / 3.3V Output Select (see OUTPUT SELECTION table)
FBOUT 22 O Feedback output
TY (7:0) 3, 10, 12, 13, O 2.5V or 3.3V Clock outputs. 1, 2, 3, 5, or 7 of these outputs may be selected as 2.5V outputs (see OUTPUT SELECTION table).
16, 17, 24, 26
Y (1:0) 19, 20 O 3.3V Clock Outputs
AVDD(3) 5 Power 3.3V Analog power supply. AVDD provides the power reference for the analog circuitry.
AGND 8 Ground Analog ground. AGND provides the ground reference for the analog circuitry.
VDD 21 Power 3.3V Power supply
VDDQ 4, 11, 15, 25 Power 2.5V or 3.3V Power supply for TY outputs
GND 2, 9, 14, 18 Ground Ground
23, 27
NOTES:
1 . CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time of 1ms
is required for the PLL to phase lock the feedback signal to the reference signal.
2. 3-level inputs will float to MID logic level if left unconnected.
3. AVDD can be used to bypass the PLL for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the outputs.
OUTPUT SELECTION VDDQ
G_Ctrl T_Ctrl TY(7:0) Configuration
ML TY0 (2.5V) Pin 4 (2.5V)
TY1 - TY7 (3.3V) Pins 11, 15, 25 (3.3V)
MMTY1, TY2 (2.5V) Pin 25 (2.5V)
TY0, TY3 - TY7 (3.3V) Pins 4, 11, 15 (3.3V)
MHTY0 - TY2 (2.5V) Pins 4, 25 (2.5V)
TY3 - TY7 (3.3V) Pins 11, 15 (3.3V)
HLTY0 - TY4 (2.5V) Pins 4, 15, 25 (2.5V)
TY5 - TY7 (3.3V) Pin 11 (3.3V)
HMTY1 - TY7 (2.5V) Pins 11, 15, 25 (2.5V)
TY0 (3.3V) Pin 4 (3.3V)
HHTYo - TY7 (3.3V) Pins 4, 11, 15, 25 (3.3V)
STA TIC FUNCTION TABLE (AVDD = 0V)(1)
Inputs Outputs
G_Ctrl T_Ctrl CLK TY(7:0) Y(1:0) FBOUT
LXLLLL
LXH L L H
see HHHH
OUTPUT SELECTION L L L L
table running running running running
DYNAMIC FUNCTION TABLE (AVDD = 3.3V)
Inputs Outputs
G_Ctrl T_Ctrl CLK TY(7:0) Y(1:0) FBOUT
LX L L L L
LX H L L H
see OUTPUT L L L L
SELECTION table H H H H
NOTE:
1. AVDD should be powered up along with VDD, before setting AVDD to ground, to put the
control pins in a valid state.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol Parameter Test Conditions Min. Typ.(1) Max Unit
VIK Input Clamp Voltage II = -18mA - 1.2 V
VIH Input HIGH Level CLK, FBIN 2 V
VIL Input LOW Level CLK, FBIN 0.8 V
VIHH Input HIGH Voltage Level(2) 3-Level Inputs Only VDD - 0.6 V
VIMM Input MID Voltage Level(2) 3-Level Inputs Only VDD/2 - 0.3 VDD/2 + 0.3 V
VILL Input LOW Voltage Level(2) 3-Level Inputs Only 0.6 V
VOH Output HIGH Voltage Level IOH = -100µAVDD - 0.2 V
(3.3V Outputs) IOH = -12mA 2 .4
VOH Output HIGH Voltage Level IOH = -100µAVDD - 0.1
(2.5V Outputs) IOH = -12mA 2 V
VOL Output LOW Voltage Level IOL = 100µA 0.2 V
(3.3V Outputs) IOL = 12mA 0.4
VOL Output LOW Voltage Level IOL = 100µA 0.1 V
(2.5V Outputs) IOL = 12mA 0.4
I33-Level Input DC Current VIN = VDD HIGH Level +200
(G_Ctrl, T_Ctrl) VIN = VDD/2 MID Level –50 +50 µA
VIN = GND LOW Level –200
IIInput Current VI = VDD or GND ±5 µA
NOTES:
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
2. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias floating inputs to VDD/2. If these inputs are switched, the function and timing of
the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions Typ.(1) Max Unit
IDDPD Power Down Supply Current VDD = 3.6, VDDQ = 2.7V / 3.3V, AVDD = 0V 8 40 µA
IDDA AVDD Supply Current VDD = AV DD = 3.6V, VDDQ = 2.7V / 3.3V, CLK = 0 or VDD 3.5 10 mA
IDD Dynamic Power Supply Current VDD = AVDD = 3.6V, VDDQ = 2.7V / 3.3V, CL = 0pF 500 — µA/MHz
VDD = AVDD = VDDQ = 3.6V 15 —
IDDD Dynamic Power Supply CL = 30pF, CLK = 100MHz mA
Current per Output VDD = AVDD = 3.6V, VDDQ = 2.7V 12 —
CL = 20pF, CLK = 100MHz
NOTE:
1. For nominal voltage and temperature.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INPUT TIMING REQUIREMENTS OVER OPERATING RANGE
5V2528 5V2528A
Min Max Min Max Units
fCLOCK Clock frequency 25 140 2 5 167 MHz
Input clock duty cycle 40% 60% 40% 60%
tLOCK Stabilization time(1) 11ms
NOTE:
1 .Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference
signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are
not applicable.
NOTES:
1. All parameters are measured with the following load conditions: 30pF || 500Ω for 3.3V outputs and 20pF || 500Ω for 2.5V outputs.
2. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
3. Phase error does not include jitter.
4. All skew parameters are only valid for equal loading of all outputs.
5. Measured for VDDQ = 2.3V and 3V, 2.5V and 3.3V, or 2.7V and 3.6V.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - 5V2528(1)
Symbol Parameter(2) Min. Typ. Max. Unit
tPHASE error Phase Error from Rising Edge CLK to Rising Edge FBIN (100MHz-133MHz) –150 —150 ps
tPHASE error - jitter(3) Phase Error minus Jitter from Rising Edge CLK to Rising Edge FBIN (133MHz) –50 —50 ps
tSK1(0)(4) Output Skew between 3.3V Outputs ——150 ps
tSK2(0)(4) Output Skew between 2.5V Outputs ——150 ps
tSK3(0)(4,5) Output Skew between 2.5V and 3.3V Outputs ——200 ps
tJCycle-to-Cycle Output Jitter (Peak-to-Peak) at 133MHz –75 —75 ps
Duty Cycle 45 —55 %
tROutput Rise Time for 3.3V Outputs (20% to 80%) 0.8 —2.1 ns
tFOutput Fall Time for 3.3V Outputs (20% to 80%) 0.8 —2.1 ns
tROutput Rise Time for 2.5V Outputs (20% to 80%) 0.5 —1.5 ns
tFOutput Fall Time for 2.5V Outputs (20% to 80%) 0.5 —1.5 ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - 5V2528A(1)
Symbol Parameter(2) Min. Typ. Max. Unit
tPHASE error Phase Error from Rising Edge CLK to Rising Edge FBIN (100MHz-166MHz) –150 —150 ps
tPHASE error - jitter(3) Phase Error minus Jitter from Rising Edge CLK to Rising Edge FBIN (166MHz) –50 —50 ps
tSK1(0)(4) Output Skew between 3.3V Outputs ——150 ps
tSK2(0)(4) Output Skew between 2.5V Outputs ——150 ps
tSK3(0)(4,5) Output Skew between 2.5V and 3.3V Outputs 25MHz to 133MHz ——200 ps
133MHz to 166MHz ——250
tJCycle-to-Cycle Output Jitter (Peak-to-Peak) at 166MHz –75 —75 ps
Duty Cycle 45 —55 %
tROutput Rise Time for 3.3V Outputs (20% to 80%) 0.8 —2.1 ns
tFOutput Fall Time for 3.3V Outputs (20% to 80%) 0.8 —2.1 ns
tROutput Rise Time for 2.5V Outputs (20% to 80%) 0.5 —1.5 ns
tFOutput Fall Time for 2.5V Outputs (20% to 80%) 0.5 —1.5 ns
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INDUSTRIAL TEMPERATURE RANGE
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
From Output
Under Test
500Ω
CL=30pF(2)
CLK
tPHASE ERROR
FBIN
VDDQ/2
VDDQ/2
tSK1(o)
Any Y, TY (3.3V)
Any TY (2.5V)
tSK2(o)
VDDQ/2 VDDQ/2
Any TY (2.5V)
VDDQ/2
VDDQ/2
tSK3(o)
tR
80%
20%
tF
tF
80%
20%
tR
VDD/2
VDD/2
FBOUT
or
Any Y, TY (3.3V)
From Output
Under Test
500Ω
CL=20pF(2)
Y, TY
CFFBIN
CLK
IDT5V2528/A
FBOUT
PCBTRACE
CL (2) 500Ω
on each Y,
TY output
(4) 500Ω
TEST CIRCUIT AND VOLTAGE WAVEFORMS
PHASE ERROR AND SKEW CALCULATIONS(3,4)
Test Circuit for 3.3V Outputs Test Circuit for 2.5V Outputs
NOTES:
1. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz ZO = 50Ω, tR ≤ 1.2 ns, tF ≤ 1.2 ns.
2. CL includes probe and jig capacitance.
3. The outputs are measured one at a time with one transition per measurement.
4. Phase error measurements require equal loading at outputs Y, TY, and FBOUT. CF = CL – CFBIN – CPCBtrace; CFBIN ≅ 5pF.
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INDUSTRIAL TEMPERATURE RANGE
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
ORDERING INFORMATION
IDT XXXXX Package
Device Type
5V2528
5V2528A 2.5V / 3.3V Phase-Lock Loop Clock Driver
PG Thin Shrink Small Outline Package
XX X
Process
I-40°C to +85° C ( Indus tri al)
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 logichelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 (408) 654-6459
www.idt.com
