1
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
MX25L25735E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
2
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Contents
FEATURES .................................................................................................................................................................. 5
GENERAL DESCRIPTION ......................................................................................................................................... 7
Table 1. Additional Features .............................................................................................................................. 7
PIN CONFIGURATION ................................................................................................................................................ 8
PIN DESCRIPTION ...................................................................................................................................................... 8
BLOCK DIAGRAM ....................................................................................................................................................... 9
DATA PROTECTION .................................................................................................................................................. 10
Table 2. Protected Area Sizes .......................................................................................................................... 11
Table 3. 4K-bit Secured OTP Denition ............................................................................................................ 11
Memory Organization ............................................................................................................................................... 12
Table 4. Memory Organization ........................................................................................................................ 12
DEVICE OPERATION ................................................................................................................................................ 13
Figure 1. Serial Modes Supported (for Normal Serial mode) ........................................................................... 13
HOLD FEATURES ..................................................................................................................................................... 14
Figure 2. Hold Condition Operation ................................................................................................................. 14
COMMAND DESCRIPTION ....................................................................................................................................... 15
Table 5. Command Sets ................................................................................................................................... 15
(1) Write Enable (WREN) ................................................................................................................................. 17
(2) Write Disable (WRDI) .................................................................................................................................. 17
(3) Read Identication (RDID) .......................................................................................................................... 17
(4) Read Status Register (RDSR) .................................................................................................................... 18
(5) Write Status Register (WRSR) .................................................................................................................... 19
Protection Modes ............................................................................................................................................. 19
(6) Read Data Bytes (READ) ........................................................................................................................... 20
(7) Read Data Bytes at Higher Speed (FAST_READ) ..................................................................................... 20
(8) 2 x I/O Read Mode (2READ) ...................................................................................................................... 20
(9) Dual Read Mode (DREAD) ......................................................................................................................... 20
(10) 4 x I/O Read Mode (4READ) .................................................................................................................... 21
(11) Quad Read Mode (QREAD) ...................................................................................................................... 21
(12) Sector Erase (SE) ..................................................................................................................................... 22
(13) Block Erase (BE)....................................................................................................................................... 22
(14) Block Erase (BE32K) ................................................................................................................................ 22
(15) Chip Erase (CE) ........................................................................................................................................ 23
(16) Page Program (PP)................................................................................................................................... 23
(17) 4 x I/O Page Program (4PP) ..................................................................................................................... 23
Program/Erase Flow(1) - verify by reading array data ..................................................................................... 25
Program/Erase Flow(2) - verify by reading program/erase fail ag bit ............................................................. 26
(18) Continuously program mode (CP mode) .................................................................................................. 27
(19) Deep Power-down (DP) ............................................................................................................................ 28
(20) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ............................................ 28
(21) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) .......................................... 28
Table 6. ID Denitions ..................................................................................................................................... 29
(22) Enter Secured OTP (ENSO) ..................................................................................................................... 29
(23) Exit Secured OTP (EXSO) ........................................................................................................................ 29
3
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
(24) Read Security Register (RDSCUR) .......................................................................................................... 29
Security Register Denition .............................................................................................................................. 30
(25) Write Security Register (WRSCUR) .......................................................................................................... 30
(26) Write Protection Selection (WPSEL) ......................................................................................................... 31
BP and SRWD if WPSEL=0 ............................................................................................................................. 31
The individual block lock mode is effective after setting WPSEL=1 ................................................................. 32
WPSEL Flow .................................................................................................................................................... 33
(27) Single Block Lock/Unlock Protection (SBLK/SBULK) ............................................................................... 34
Block Lock Flow ............................................................................................................................................... 34
Block Unlock Flow ............................................................................................................................................ 35
(28) Read Block Lock Status (RDBLOCK) ....................................................................................................... 36
(29) Gang Block Lock/Unlock (GBLK/GBULK)................................................................................................. 36
(30) Clear SR Fail Flags (CLSR) ...................................................................................................................... 36
(31) Enable SO to Output RY/BY# (ESRY) ...................................................................................................... 36
(32) Disable SO to Output RY/BY# (DSRY) ..................................................................................................... 36
POWER-ON STATE ................................................................................................................................................... 37
ELECTRICAL SPECIFICATIONS .............................................................................................................................. 38
ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 38
Figure 3. Maximum Negative Overshoot Waveform ........................................................................................ 38
CAPACITANCE TA = 25°C, f = 1.0 MHz ........................................................................................................... 38
Figure 4. Maximum Positive Overshoot Waveform .......................................................................................... 38
Figure 5. OUTPUT LOADING ......................................................................................................................... 39
Table 7. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) . 40
Table 8. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) 41
Timing Analysis ........................................................................................................................................................ 43
Figure 6. Serial Input Timing ............................................................................................................................ 43
Figure 7. Output Timing .................................................................................................................................... 43
Figure 8. Hold Timing ....................................................................................................................................... 44
Figure 9. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 ................................................. 44
Figure 10. Write Enable (WREN) Sequence (Command 06) ........................................................................... 45
Figure 11. Write Disable (WRDI) Sequence (Command 04) ............................................................................ 45
Figure 12. Read Identication (RDID) Sequence (Command 9F) .................................................................... 45
Figure 13. Read Status Register (RDSR) Sequence (Command 05) .............................................................. 46
Figure 14. Write Status Register (WRSR) Sequence (Command 01) ............................................................. 46
Figure 15. Read Data Bytes (READ) Sequence (Command 03) .................................................................... 47
Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B) ................................................ 47
Figure 17. 2 x I/O Read Mode Sequence (Command BB) ............................................................................... 48
Figure 18. Dual Read Mode Sequence (Command 3B)................................................................................... 48
Figure 19. 4 x I/O Read Mode Sequence (Command EB) ............................................................................... 49
Figure 20. Quad Read Mode Sequence (Command 6B) ................................................................................. 49
Figure 21. 4 x I/O Read Enhance Performance Mode Sequence (Command EB) .......................................... 50
Figure 22. Sector Erase (SE) Sequence (Command 20) ................................................................................ 50
Figure 23. Block Erase (BE/EB32K) Sequence (Command D8/52) ................................................................ 51
Figure 24. Chip Erase (CE) Sequence (Command 60 or C7) ......................................................................... 51
Figure 25. Page Program (PP) Sequence (Command 02).............................................................................. 51
Figure 26. 4 x I/O Page Program (4PP) Sequence (Command 38) ................................................................ 52
4
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Figure 27. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD) ................. 52
Figure 28. Deep Power-down (DP) Sequence (Command B9)....................................................................... 53
Figure 29. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
......................................................................................................................................................................... 53
Figure 30. Release from Deep Power-down (RDP) Sequence (Command AB) ............................................. 53
Figure 31. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF) ........ 54
Figure 32. Write Protection Selection (WPSEL) Sequence (Command 68) .................................................... 54
Figure 33. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39) ..................... 55
Figure 34. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C) ................................ 55
Figure 35. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98) ...................................... 55
Figure 36. Power-up Timing ............................................................................................................................. 56
Table 9. Power-Up Timing ................................................................................................................................ 56
INITIAL DELIVERY STATE............................................................................................................................... 56
OPERATING CONDITIONS ....................................................................................................................................... 57
Figure 37. AC Timing at Device Power-Up ....................................................................................................... 57
Figure 38. Power-Down Sequence .................................................................................................................. 58
ERASE AND PROGRAMMING PERFORMANCE .................................................................................................... 59
DATA RETENTION .................................................................................................................................................... 59
LATCH-UP CHARACTERISTICS .............................................................................................................................. 59
ORDERING INFORMATION ...................................................................................................................................... 60
PART NAME DESCRIPTION ..................................................................................................................................... 61
PACKAGE INFORMATION ........................................................................................................................................ 62
REVISION HISTORY ................................................................................................................................................. 64
5
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
256M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 268,435,456 x 1 bit structure or 134,217,728 x 2 bits (two I/O mode) structure or 67,108,864 x 4 bits (four I/O
mode) structure
• 8192 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 1024 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 512 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• 4-bytes address interface
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
VCC = 2.7~3.6V
- Normal read
- 50MHz
- Fast read
- 1 I/O: 80MHz with 8 dummy cycles
- 2 I/O: 70MHz with 4 dummy cycles
- 4 I/O: 70MHz with 6 dummy cycles
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously Program mode (automatically increase address under word program mode)
- Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.5s(typ.) /block (32K-byte per block); 0.7s(typ.) /block
(64K-byte per block); 160s(typ.) /chip
• Low Power Consumption
- Low active read current: 45mA(max.) at 80MHz, 40mA(max.) at 70MHz and 30mA(max.) at 50MHz
- Low active programming current: 25mA (max.)
- Low active erase current: 25mA (max.)
- Standby current: 200uA (max.)
- Deep power down current: 80uA (max.)
• Typical 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- BP0-BP3 block group protect
- Flexible individual block protect when OTP WPSEL=1
6
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
- Additional 4K bits secured OTP for unique identier
• Auto Erase and Auto Program Algorithms
- Automatically erases and veries data at selected sector
- Automatically programs and veries data at selected page by an internal algorithm that automatically times the
program pulse width (Any page to be programed should have page in the erased state rst.)
• Status Register Feature
• Electronic Identication
- JEDEC 1-byte Manufacturer ID and 2-byte Device ID
- RES command for 1-byte Device ID
- Both REMS, REMS2, REMS4 commands for 1-byte Manufacturer ID and 1-byte Device ID
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O mode
• HOLD#/SIO3
- HOLD# pin or serial data Input/Output for 4 x I/O mode, an internal weak pull up on the pin
• PACKAGE
- 16-pin SOP (300mil)
- 8 WSON (8x6mm)
- All Pb-free devices are RoHS Compliant
7
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Table 1. Additional Features
GENERAL DESCRIPTION
MX25L25735E is 268,435,456 bits serial Flash memory with 4-bytes address interface, which is congured
as 33,554,432 x 8 internally. When it is in two or four I/O mode, the structure becomes 134,217,728 bits x 2 or
67,108,864 bits x 4. The MX25L25735E features a serial peripheral interface and software protocol allowing op-
eration on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial
data output (SO). Serial access to the device is enabled by CS# input.
MX25L25735E, MXSMIOTM (Serial Multi I/O) ash memory, provides sequential read operation on whole chip and
multi-I/O features.
When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and
data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin,
SIO2 pin and SIO3 pin for address/dummy bits input and data Input/Output.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the
specied page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for Continuously Program mode, and erase command is executes on sector (4K-byte),
block (32K-byte/64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 200uA DC cur-
rent.
The MX25L25735E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Additional
Features
Part
Name
Protection and Security Read Performance
Flexible or Individual
block (or sector)
protection
4K-bit
secured OTP
1 I/O Read
(80 MHz)
2 I/O Read
(70 MHz)
4 I/O Read
(70 MHz)
MX25L25735E V V V V V
Additional
Features
Part
Name
Identier
RES
(command: AB hex)
REMS
(command: 90 hex)
REMS2
(command: EF hex)
REMS4
(command: DF hex)
RDID
(command: 9F hex)
MX25L25735E 18 (hex) C2 18 (hex) C2 18 (hex) C2 18 (hex) C2 20 19 (hex)
8
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
PIN CONFIGURATION
16-PIN SOP (300mil)
1
2
3
4
5
6
7
8
HOLD#/SIO3
VCC
NC
NC
NC
NC
CS#
SO/SIO1
16
15
14
13
12
11
10
9
SCLK
SI/SIO0
NC
NC
NC
NC
GND
WP#/SIO2
PIN DESCRIPTION
SYMBOL DESCRIPTION
CS# Chip Select
SI/SIO0 Serial Data Input (for 1xI/O)/ Serial Data
Input & Output (for 2xI/O or 4xI/O mode)
SO/SIO1
Serial Data Output (for 1xI/O)/Serial
Data Input & Output (for 2xI/O or 4xI/O
mode)
SCLK Clock Input
WP#/SIO2
Write protection: connect to GND or
Serial Data Input & Output (for 4xI/O
mode)
HOLD#/
SIO3
HOLD# pin or Serial Data Input & Output
(for 4xI/O mode)
VCC + 3.3V Power Supply
GND Ground
NC No Connection
8-WSON (8x6mm)
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
8
7
6
5
VCC
HOLD#/SIO3
SCLK
SI/SIO0
9
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
BLOCK DIAGRAM
Address
Generator
Memory Array
Page Buffer
Y-Decoder
X-Decoder
Data
Register
SRAM
Buffer
SI/SIO0
SCLK
SO/SIO1
Clock Generator
State
Machine
Mode
Logic
Sense
Amplifier
HV
Generator
Output
Buffer
CS#
WP#/SIO2
HOLD#/SIO3
10
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
DATA PROTECTION
MX25L25735E is designed to offer protection against accidental erasure or programming caused by spurious sys-
tem level signals that may exist during power transition. During power up the device automatically resets the state
machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents
only occurs after successful completion of specic command sequences. The device also incorporates several fea-
tures to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP, 4PP) command completion
- Continuously Program mode (CP) instruction completion
- Sector Erase (SE) command completion
- Block Erase (BE, BE32K) command completion
- Chip Erase (CE) command completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
- Write Security Register (WRSCUR) instruction completion
- Write Protection Selection (WPSEL) instruction completion
• Deep Power Down Mode: By entering deep power down mode, the ash device also is under protected from
writing all commands except Release from Deep Power Down mode command (RDP) and Read Electronic Sig-
nature command (RES).
I. Block lock protection
- The Software Protected Mode (SPM) uses (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The protected area denition is shown as table of "Protected Area Sizes", the protected areas are
more exible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "Protect-
ed Area Sizes".
- The Hardware Protected Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit.
If the system goes into four I/O mode, the feature of HPM will be disabled.
- MX25L25735E provide individual block (or sector) write protect & unprotect. User may enter the mode with
WPSEL command and conduct individual block (or sector) write protect with SBLK instruction, or SBULK for
individual block (or sector) unprotect. Under the mode, user may conduct whole chip (all blocks) protect with
GBLK instruction and unlock the whole chip with GBULK instruction.
11
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
II. Additional 4K-bit secured OTP for unique identier: to provide 4K-bit One-Time Program area for setting de-
vice unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Se-
cured OTP Denition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Denition" for secu-
rity register bit denition and table of "4K-bit Secured OTP Denition" for address range denition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Se-
cured OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Denition
Table 2. Protected Area Sizes
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0.
Address range Size Standard Factory Lock Customer Lock
xxx000~xxx00F 128-bit ESN (electrical serial number)
Determined by customer
xxx010~xxx1FF 3968-bit N/A
Status bit Protection Area
BP3 BP2 BP1 BP0 256Mb
0 0 0 0 0 (none)
0 0 0 1 1 (2 blocks, block 510th-511th)
0 0 1 0 2 (4 blocks, block 508th-511th)
0 0 1 1 3 (8 blocks, block 504th-511th)
0 1 0 0 4 (16 blocks, block 496th-511th)
0 1 0 1 5 (32 blocks, block 480th-511th)
0 1 1 0 6 (64 blocks, block 448nd-511th)
0 1 1 1 7 (128 blocks, block 384th-511th)
1 0 0 0 8 (256 blocks, block 256th-511th)
1 0 0 1 9 (512 blocks, all)
1 0 1 0 10 (512 blocks, all)
1 0 1 1 11 (512 blocks, all)
1 1 0 0 12 (512 blocks, all)
1 1 0 1 13 (512 blocks, all)
1 1 1 0 14 (512 blocks, all)
1 1 1 1 15 (512 blocks, all)
12
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Memory Organization
Table 4. Memory Organization
Block(32K-byte) Sector
8191 1FFF000h 1FFFFFFh
…
8184 1FF8000h 1FF8FFFh
8183 1FF7000h 1FF7FFFh
…
8176 1FF0000h 1FF0FFFh
8175 1FEF000h 1FEFFFFh
…
8168 1FE8000h 1FE8FFFh
8167 1FE7000h 1FE7FFFh
…
8160 1FE0000h 1FE0FFFh
8159 1FDF000h 1FDFFFFh
…
8152 1FD8000h 1FD8FFFh
8151 1FD7000h 1FD7FFFh
…
…
……………
…
……………
8144 1FD0000h 1FD0FFFh
47 002F000h 002FFFFh
…
40 0028000h 0028FFFh
39 027000h 0027FFFh
…
32 0020000h 0020FFFh
31 001F000h 001FFFFh
…
24 0018000h 0018FFFh
23 0017000h 0017FFFh
…
16 0010000h 0010FFFh
15 000F000h 000FFFFh
…
80008000h 0008FFFh
70007000h 0007FFFh
…
………………
………………
00000000h 0000FFFh
1020
1019
1018
Address Range
1023
1022
1021
individual block
lock/unlock unit:64K-byte
individual 16 sectors
lock/unlock unit:4K-byte
individual block
lock/unlock unit:64K-byte
individual block
lock/unlock unit:64K-byte
Block(64K-byte)
509
2
1
0
511
510
0
5
4
3
2
1
individual 16 sectors
lock/unlock unit:4K-byte
13
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and
data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 1.
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, DREAD, 4READ, QREAD,
RDBLOCK, RES, REMS, REMS2, and REMS4 the shifted-in instruction sequence is followed by a data-out
sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN,
WRDI, WRSR, SE, BE, BE32K, HPM, CE, PP, CP, 4PP, RDP, DP, WPSEL, SBLK, SBULK, GBLK, GBULK,
ENSO, EXSO, WRSCUR, ENPLM, EXPLM, ESRY, DSRY and CLSR the CS# must go high exactly at the byte
boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-
ed and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported (for Normal Serial mode)
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
SCLK
MSB
CPHA shift in shift out
SI
0
1
CPOL
0(Serial mode 0)
(Serial mode 3) 1
SO
SCLK
MSB
14
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
HOLD FEATURES
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start
until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Se-
rial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial
Clock being low), see Figure 2.
Figure 2. Hold Condition Operation
HOLD#
CS#
SCLK
Hold
Condition
(standard)
Hold
Condition
(non-standard)
The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care
during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of
the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
Note 1: The HOLD feature is disabled during Quad I/O mode in 16-SOP package.
15
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
COMMAND DESCRIPTION
Table 5. Command Sets
COMMAND
(byte)
WREN (write
enable)
WRDI (write
disable)
RDID (read
identication)
RDSR
(read status
register)
WRSR
(write status
register)
READ (read
data)
2READ (2
x I/O read
command)
Note1
DREAD
(1I 2O read)
Command
(hex) 06 04 9F 05 01 03 BB 3B
Input
Cycles Data(8) ADD(32) ADD(16) ADD(32)
Dummy
Cycles 4 8
Action
sets the
(WEL) write
enable latch
bit
resets the
(WEL) write
enable latch
bit
outputs JEDEC
ID: 1-byte
Manufacturer
ID & 2-byte
Device ID
to read out
the values
of the status
register
to write new
values to
the status
register
n bytes read
out until CS#
goes high
n bytes read
out by 2 x I/
O until CS#
goes high
n bytes read
out by Dual
output until
CS# goes
high
COMMAND
(byte)
FAST READ
(fast read
data)
4READ (4
x I/O read
command)
QREAD
(1I 4O read)
4PP (quad
page
program)
SE (sector
erase)
BE (block
erase 64KB)
BE 32K (block
erase 32KB)
CE (chip
erase)
Command
(hex) 0B EB 6B 38 20 D8 52 60 or C7
Input
Cycles ADD(32) ADD(8)+
indicator(2) ADD(32) ADD(8)+
Data(512) ADD(32) ADD(32) ADD(32)
Dummy
Cycles 8 4 8
Action
n bytes read
out until CS#
goes high
n bytes read
out by 4 x I/
O until CS#
goes high
n bytes read
out by Quad
output until
CS# goes
high
quad input
to program
the selected
page
to erase the
selected
sector
to erase the
selected
64KB block
to erase the
selected
32KB block
to erase
whole chip
COMMAND
(byte)
PP (Page
program)
CP
(Continuously
program
mode)
DP (Deep
power down)
RDP
(Release
from deep
power down)
RES (read
electronic ID)
REMS (read
electronic
manufacturer
& device ID)
REMS2 (read
ID for 2x I/O
mode)
REMS4 (read
ID for 4x I/O
mode)
Command
(hex) 02 AD B9 AB AB 90 EF DF
Input
Cycles
ADD(32)+
Data(2048)
ADD(32)+
Data(16) ADD(8) ADD(8) ADD(8)
Dummy
Cycles 24 16 16 16
Action
to program
the selected
page
continously
program
whole
chip, the
address is
automatically
increase
enters deep
power down
mode
release from
deep power
down mode
to read out
1-byte Device
ID
output the
Manufacturer
ID & Device
ID
output the
Manufacturer
ID & Device
ID
output the
Manufacturer
ID & device
ID
16
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Note 1: It is not recommended to adopt any other code not in the command denition table, which will potentially
enter the hidden mode.
Note 2: In individual block write protection mode, all blocks/sectors is locked as defualt.
Note 3: The number in parentheses afer "ADD" or "Data" stands for how many clock cycles it has.
For example, "Data(8)" represents there are 8 clock cycles for the data in.
COMMAND
(byte)
ENSO (enter
secured
OTP)
EXSO (exit
secured
OTP)
RDSCUR
(read security
register)
WRSCUR
(write security
register)
ESRY
(enable SO
to output RY/
BY#)
DSRY
(disable SO
to output RY/
BY#)
CLSR (Clear
SR Fail
Flags)
HPM (High
Perform-
ance Enable
Mode)
Command
(hex) B1 C1 2B 2F 70 80 30 A3
Input
Cycles
Dummy
Cycles
Action
to enter
the 4K-bit
Secured OTP
mode
to exit the 4K-
bit Secured
OTP mode
to read value
of security
register
to set the
lock-down bit
as "1" (once
lock-down,
cannot be
updated)
to enable SO
to output RY/
BY# during
CP mode
to disable SO
to output RY/
BY# during
CP mode
clear security
register bit 6
and bit 5
Quad I/O
high Perform-
ance mode
COMMAND
(byte)
WPSEL (write
protection
selection)
SBLK (single
block lock)
*Note 2
SBULK
(single block
unlock)
RDBLOCK
(block protect
read)
GBLK (gang
block lock)
GBULK (gang
block unlock)
Command
(hex) 68 36 39 3C 7E 98
Input
Cycles ADD(32) ADD(32) ADD(32)
Dummy
Cycles
Action to enter
and enable
individal
block protect
mode
individual
block (64K-
byte) or
sector (4K-
byte) write
protect
individual
block (64K-
byte) or
sector
(4K-byte)
unprotect
read
individual
block or
sector write
protect status
whole chip
write protect
whole
chip
unprotect
17
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
CP, SE, BE, BE32K, CE, WRSR, WRSCUR, WPSEL, SBLK, SBULK, GBLK and GBULK, which are intended to
change the device content, should be set every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high.
(Please refer to Figure 10)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (Please
refer to Figure 11)
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP, 4PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE, BE32K) instruction completion
- Chip Erase (CE) instruction completion
- Continuously Program mode (CP) instruction completion
- Single Block Lock/Unlock (SBLK/SBULK) instruction completion
- Gang Block Lock/Unlock (GBLK/GBULK) instruction completion
- Write Security Register (WRSCUR) instruction completion
- Write Protection Selection (WPSEL) instruction completion
(3) Read Identication (RDID)
The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the rst-byte Device ID, and the individual Device ID
of second-byte ID are listed as table of "ID Denitions". (Please refer to Table 6)
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out
on SO→ to end RDID operation can use CS# to high at any time during data out. (Please refer to Figure 12)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-
cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
18
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO (Please refer to Figure 13).
The denition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-
vice will not accept program/erase/write status register instruction. The program/erase command will be ignored and
will reset WEL bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as
dened in Table 2) of the device to against the program/erase instruction without hardware protection mode being
set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to
be executed. Those bits dene the protected area of the memory to against Page Program (PP), Sector Erase (SE),
Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be
executed).
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#,
HOLD# are enable. While QE is "1", it performs Quad I/O mode and WP#, HOLD# are disabled. In the other word, if
the system goes into four I/O mode (QE=1), the feature of HPM and HOLD# will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operat-
ed together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection
mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write
Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3,
BP2, BP1, BP0) are read only.
Status Register
Note 1: see the Table 2 "Protected Area Size" in page 11.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SRWD (status
register write
protect)
QE
(Quad
Enable)
BP3
(level of
protected
block)
BP2
(level of
protected
block)
BP1
(level of
protected
block)
BP0
(level of
protected
block)
WEL
(write enable
latch)
WIP
(write in
progress bit)
1=status
register write
disable
1= Quad
Enable
0=not Quad
Enable
(note 1) (note 1) (note 1) (note 1)
1=write
enable
0=not write
enable
1=write
operation
0=not in write
operation
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit volatile bit volatile bit
19
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-
vance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to dene the pro-
tected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad enable (QE) bit and set or
reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but
has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot be executed once the
Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→ CS# goes high. (Please refer to Figure 14)
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Protection Modes
Note: As dened by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is dened by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP3, BP2, BP1, BP0. The protected area, which is dened by BP3, BP2, BP1, BP0, is at software pro-
tected mode (SPM)
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modication.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.
If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only
can use software protected mode via BP3, BP2, BP1, BP0.
If the system goes into four I/O mode, the feature of HPM will be disabled.
Mode Status register condition WP# and SRWD bit status Memory
Software protection
mode (SPM)
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
Hardware protection
mode (HPM)
The SRWD, BP0-BP3 of
status register bits cannot be
changed
WP#=0, SRWD bit=1
The protected area
cannot
be program or erase.
20
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The rst address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low → sending READ instruction code→ 4-byte address
on SI → data out on SO → to end READ operation can use CS# to high at any time during data out. (Please refer to
Figure 15)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The rst address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low → sending FAST_READ instruction code →
4-byte address on SI → 1-dummy byte (default) address on SI → data out on SO → to end FAST_READ operation
can use CS# to high at any time during data out. (Please refer to Figure 16)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
(8) 2 x I/O Read Mode (2READ)
The 2READ instruction enables Double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-
mum frequency fT. The rst address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruc-
tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low → sending 2READ instruction → 4-byte address in-
terleave on SIO1 & SIO0 → 4-bit dummy cycle on SIO1 & SIO0 → data out interleave on SIO1 & SIO0 → to end
2READ operation can use CS# to high at any time during data out (Please refer to Figure 17 for 2 x I/O Read Mode
Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(9) Dual Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-
mum frequency fT. The rst address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruc-
21
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruc-
tion, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 4-byte address on
SI → 8-bit dummy cycle → data out interleave on SO1 & SO0 → to end DREAD operation can use CS# to high at
any time during data out (Please refer to Figure 18 for Dual Read Mode Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(10) 4 x I/O Read Mode (4READ)
The 4READ instruction enables quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,
and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The rst address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The ad-
dress counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the fol-
lowing address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low → sending 4READ instruction → 4-byte address
interleave on SIO3, SIO2, SIO1 & SIO0 → 6 dummy cycles → data out interleave on SIO3, SIO2, SIO1 & SIO0→
to end 4READ operation can use CS# to high at any time during data out (Please refer to Figure 19 for 4 x I/O
Read Mode Timing Waveform).
Another sequence of issuing 4 READ instruction especially useful in random access is : CS# goes low→ sending 4
READ instruction → 4-byte address interleave on SIO3, SIO2, SIO1 & SIO0 → performance enhance toggling bit
P[7:0]→ 4 dummy cycles → data out still CS# goes high → CS# goes low (reduce 4 Read instruction) → 4-byte ad-
dress random access address (Please refer to Figure 21 for 4x I/O Read Enhance Performance Mode timing wave-
form).
In the performance-enhancing mode (the waveform figure), P[7:4] must be toggling with P[3:0] ; likewise
P[7:0]=A5h,5Ah,F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is
no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h. These commands will reset the performance
enhance mode. And afterwards CS# is raised and then lowered, the system then will return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(11) Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status
register must be set to "1" before sending the QREAD. The address is latched on rising edge of SCLK, and data of
every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The rst
address byte can be at any location. The address is automatically increased to the next higher address after each
byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. The address counter
rolls over to 0 when the highest address has been reached. Once writing QREAD instruction, the following data out
will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 4-byte address on
SI → 8-bit dummy cycle → data out interleave on SO3, SO2, SO1 & SO0→ to end QREAD operation can use
CS# to high at any time during data out (Please refer to Figure 20 for Quad Read Mode Timing Waveform).
22
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(12) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (Table of memory organization) is a valid address for
Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte
been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 4-byte address (depending
on mode state) on SI → CS# goes high. (Please refer to Figure 22)
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
sector is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit still be reset.
(13) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE). Any address of the block (Table of memory organization) is a valid address
for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address
byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 4-byte address on SI →
CS# goes high. (Please refer to Figure 23)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit still be reset.
(14) Block Erase (BE32K)
The Block Erase (BE32) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
32K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE32). Any address of the block (Table of memory organization) is a valid ad-
dress for Block Erase (BE32) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of
address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32 instruction is: CS# goes low → sending BE32 instruction code → 4-byte address on
SI → CS# goes high. (Please refer to Figure 23)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
23
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the block is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit still be reset.
(15) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go
high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high. (Please
refer to Figure 24)
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is
protected the Chip Erase (CE) instruction will not be executed, but WEL will be reset.
(16) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device
programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed,
A7-A0 (The eight least signicant address bits) should be set to 0. If the eight least signicant address bits (A7-A0)
are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address
of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the
last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are
sent to the device, the data is programmed at the requested address of the page without effect on other address of
the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 4-byte address on SI→
at least 1-byte on data on SI→ CS# goes high. (Please refer to Figure 25)
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary (the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
(17) 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1"
before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2,
24
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
and SIO3, which can raise programer performance and and the effectiveness of application of lower clock less
than 20MHz. For system with faster clock, the Quad page program cannot provide more actual favors, because
the required internal page program time is far more than the time data ows in. Therefore, we suggest that while
executing this command (especially during sending data), user can slow the clock speed down to 20MHz below.
The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 4-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high. (Please refer to Figure 26)
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
25
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
The Program/Erase function instruction function ow is as follows:
Program/Erase Flow(1) - verify by reading array data
WREN command
Program/erase command
Write program data/address
(Write erase address)
RDSR command
Read array data
(same address of PGM/ERS)
Program/erase successfully
Yes
Yes
Program/erase fail
No
No
Start
Program/erase completed
Verify OK?
WIP=0?
Program/erase
another block?
Yes
No
RDSR command*
Yes
WREN=1? No
*
* Issue RDSR to check BP[3:0].
* If WPSEL=1, issue RDBLOCK to check the block status.
CLSR(30h) command
26
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Program/Erase Flow(2) - verify by reading program/erase fail ag bit
27
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
(18) Continuously program mode (CP mode)
The CP mode may enhance program performance by automatically increasing address to the next higher address
after each byte data has been programmed.
The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Continuously program (CP) instruction.
CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of
data is input sequentially from MSB(bit7) to LSB(bit0). The rst byte data will be programmed to the initial address
range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If
more than two bytes data are input, the additional data will be ignored and only two byte data are valid. Any byte to
be programmed should be in the erase state (FF) rst. It will not roll over during the CP mode, once the last unpro-
tected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP
mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction.
During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05
hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cy-
cle, which means the WIP bit=0.
The sequence of issuing CP instruction is : CS# goes low → sending CP instruction code → 4-byte address on SI
pin → two data bytes on SI → CS# goes high to low → sending CP instruction and then continue two data bytes
are programmed → CS# goes high to low → till last desired two data bytes are programmed → CS# goes high to
low → sending WRDI (Write Disable) instruction to end CP mode → send RDSR instruction to verify if CP mode
word program ends, or send RDSCUR to check bit4 to verify if CP mode ends. (Please refer to Figure 27 of CP
mode timing waveform)
Three methods to detect the completion of a program cycle during CP mode:
1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.
2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not.
3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a
program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is
enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indi-
cates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to
disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the
ESRY/DSRY command are not accepted unless the completion of CP mode.
If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be protected (no
change) and the WEL bit will still be reset.
28
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
(19) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-
ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac-
tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep
power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (Please
refer to Figure 28)
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Power-
down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(20) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip Se-
lect (CS#) must remain High for at least tRES2(max), as specied in Table 8. Once in the standby mode, the device
waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of
ID Denitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be
executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current pro-
gram/erase/write cycles in progress. The sequence is shown as Figure 29, 30.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at
least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and
execute instruction.
The RDP instruction is for releasing from Deep Power-down Mode.
(21) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)
The REMS, REMS2, and REMS4 instruction provides both the JEDEC assigned Manufacturer ID and the specic
Device ID.
The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "DFh" or "EFh" followed
by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the De-
vice ID are shifted out on the falling edge of SCLK with most signicant bit (MSB) rst as shown in Figure 28. The
Device ID values are listed in table of ID Denitions. If the one-byte address is initially set to 01h, then the Device
ID will be read rst and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read con-
tinuously, alternating from one to the other. The instruction is completed by driving CS# high.
29
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Table 6. ID Denitions
Command Type MX25L25735E
RDID manufacturer ID memory type memory density
C2 20 19
RES electronic ID
18
REMS/REMS2/REMS4 manufacturer ID device ID
C2 18
(22) Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit Secured OTP mode. The additional 4K-bit Secured OTP
is independent from main array, which may use to store unique serial number for system identier. After entering
the Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data.
The Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low → sending ENSO instruction to enter Secured OTP
mode → CS# goes high.
Please note that WRSR/WRSCUR/WPSEL/SBLK/GBLK/SBULK/GBULK/CE/BE/SE/BE32K commands are not ac-
ceptable during the access of secure OTP region, once Security OTP is lock down, only read related commands
are valid.
(23) Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit Secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low → sending EXSO instruction to exit Secured OTP
mode → CS# goes high.
(24) Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read at
any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low → sending RDSCUR instruction → Security Regis-
ter data out on SO → CS# goes high.
The denition of the Security Register is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory
or not. When it is "0", it indicates non-factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus-
tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured
OTP area cannot be update any more. While it is in 4K-bit Secured OTP mode, array access is not allowed.
30
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
(25) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. The WRSCUR instruction may
change the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is
set to "1", the Secured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
Security Register Denition
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
WPSEL E_FAIL P_FAIL
Continuously
Program
mode
(CP mode)
x x
LDSO
(lock-down
4K-bit Se-
cured OTP)
4K-bit
Secured OTP
0=normal
WP mode
1=individual
WP mode
(default=0)
0=normal
Erase
succeed
1=indicate
Erase failed
(default=0)
0=normal
Program
succeed
1=indicate
Program
failed
(default=0)
0=normal
Program
mode
1=CP mode
(default=0)
reserved reserved
0 = not
lockdown
1 = lock-
down
(cannot
program/
erase
OTP)
0 =
nonfactory
lock
1 = factory
lock
non-volatile
bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile
bit
non-volatile
bit
OTP Read Only Read Only Read Only Read Only Read Only OTP Read Only
Continuously Program Mode (CP mode) bit. The Continuously Program Mode bit indicates the status of CP
mode, "0" indicates not in CP mode; "1" indicates in CP mode.
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This bit will also
be set when the user attempts to program a protected main memory region or a locked OTP region. This bit can in-
dicate whether one or more of program operations fail, and can be reset by command CLSR (30h)
Erase Fail Flag bit. While a erase failure happened, the Erase Fail Flag bit would be set. This bit will also be set
when the user attempts to erase a protected main memory region or a locked OTP region. This bit can indicate
whether one or more of erase operations fail, and can be reset by command CLSR (30h)
Write Protection Select bit. The Write Protection Select bit indicates that WPSEL has been executed successfully.
Once this bit has been set (WPSEL=1), all the blocks or sectors will be write-protected after the power-on every
time. Once WPSEL has been set, it cannot be changed again, which means it's only for individual WP mode.
Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once
WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
31
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
(26) Write Protection Selection (WPSEL)
There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WPSEL=0,
ash is under BP protection mode . If WPSEL=1, ash is under individual block protection mode. The default value
of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an OTP bit. Once
WPSEL is set to 1, there is no chance to recovery WPSEL back to “0”. If the ash is put on BP mode, the indi-
vidual block protection mode is disabled. Contrarily, if ash is on the individual block protection mode, the BP mode
is disabled.
Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1, all
the blocks or sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK
and GBULK instruction. Program or erase functions can only be operated after the Unlock instruction is conducted.
BP protection mode, WPSEL=0:
ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7
of status register that can be set by WRSR command.
Individual block protection mode, WPSEL=1:
Blocks are individually protected by their own SRAM lock bits which are set to “1” after power up. SBULK and SBLK
command can set SRAM lock bit to “0” and “1”. When the system accepts and executes WPSEL instruction, the bit
7 in security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct
block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block meth-
ods.Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0.
Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual
block protect mode → CS# goes high.
WPSEL instruction function ow is as follows:
64KB
64KB
.
.
.
64KB
64KB
BP3BP2BP1BP0SRWD
WPB pin
BP and SRWD if WPSEL=0
(1) BP3~BP0 is used to dene the protection group region.
(The protected area size see Table2)
(2) “SRWD=1 and WPB=0” is used to protect BP3~BP0. In this
case, SRWD and BP3~BP0 of status register bits can not
be changed by WRSR
32
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
The individual block lock mode is effective after setting WPSEL=1
64KB
4KB
64KB
4KB
SRAM
SRAM
SRAM
4KB
4KB
SRAM
Uniform
64KB blocks
SRAM
SRAM
4KBSRAM
SBULK / SBLK / GBULK / GBLK / RDBLOCK
……
……
…
…
…
…
Bottom
4KBx16
Sectors
TOP 4KBx16
Sectors
• Power-Up: All SRAM bits=1 (all blocks are default protected).
All array cannot be programmed/erased
• SBLK/SBULK(36h/39h):
- SBLK(36h) : Set SRAM bit=1 (protect) : array can not be
programmed /erased
- SBULK(39h): Set SRAM bit=0 (unprotect): array can be
programmed /erased
- All top 4KBx16 sectors and bottom 4KBx16 sectors
and other 64KB uniform blocks can be protected and
unprotected SRAM bits individually by SBLK/SBULK
command set.
• GBLK/ GBULK(7Eh/98h):
- GBLK(7Eh):Set all SRAM bits=1,whole chip are protected
and cannot be programmed / erased.
- GBULK(98h):Set all SRAM bits=0,whole chip are
unprotected and can be programmed / erased.
- All sectors and blocks SRAM bits of whole chip can be
protected and unprotected at one time by GBLK/GBULK
command set.
• RDBLOCK(3Ch):
- use RDBLOCK mode to check the SRAM bits status after
SBULK /SBLK/GBULK/GBLK command set.
33
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
WPSEL Flow
RDSCUR(2Bh) command
RDSR command
RDSCUR(2Bh) command
WPSEL set successfully
Yes
Yes
WPSEL set fail
No
start
WPSEL=1?
WIP=0? No
WPSEL disable,
block protected by BP[3:0]
Yes
No
WPSEL=1?
WPSEL(68h) command
WPSEL enable.
Block protected by individual lock
(SBLK, SBULK, …etc).
34
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Block Lock Flow
RDSCUR(2Bh) command
Start
WREN command
SBLK command
( 36h address )
RDSR command
RDBLOCK command
( 3Ch address )
Block lock successfully
Yes
Yes
Block lock fail
No
Data = FFh ?
WIP=0?
Lock another block?
Block lock completed
No
Yes
No
No
Yes
WPSEL=1? WPSEL command
(27) Single Block Lock/Unlock Protection (SBLK/SBULK)
These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a spec-
ied block(or sector) of memory, using address bits to assign a 64Kbyte block (or 4K bytes sector) to be protected
as read only. The SBULK instruction will cancel the block (or sector) write protection state. This feature allows user
to stop protecting the entire block (or sector) through the chip unprotect command (GBULK).
The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction.
The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h) instruction →
send 4-byte address assign one block (or sector) to be protected on SI pin → CS# goes high. (Please refer to Figure
33)
The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed.
SBLK/SBULK instruction function ow is as follows:
35
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Block Unlock Flow
WREN command
RDSCUR(2Bh) command
SBULK command
( 39h address )
RDSR command
Yes
WIP=0?
Unlock another block? Yes
No
No
Yes
Unlock block completed?
start
WPSEL=1? WPSEL command
36
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
(28) Read Block Lock Status (RDBLOCK)
This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of
protection lock of a specied block(or sector), using address bits to assign a 64K bytes block (4K bytes sector) and
read protection lock status bit which the rst byte of Read-out cycle. The status bit is"1" to indicate that this block
has be protected, that user can read only but cannot write/program /erase this block. The status bit is "0" to indicate
that this block hasn't be protected, and user can read and write this block.
The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send
4-byte address to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high. (Please
refer to Figure 34)
(29) Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable
the lock protection block of the whole chip.
The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction →
CS# goes high. (Please refer to Figure 35)
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.
(30) Clear SR Fail Flags (CLSR)
The CLSR instruction is for resetting the Program/Erase Fail Flag bit of Security Register. It should be executed be-
fore program/erase another block during programming/erasing ow without read array data.
The sequence of issuing CLSR instruction is: CS# goes low → send CLSR instruction code → CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
(31) Enable SO to Output RY/BY# (ESRY)
The ESRY instruction is for outputting the ready/busy status to SO during CP mode.
The sequence of issuing ESRY instruction is: CS# goes low → sending ESRY instruction code → CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
(32) Disable SO to Output RY/BY# (DSRY)
The DSRY instruction is for resetting ESRY during CP mode. The ready/busy status will not output to SO after
DSRY issued.
The sequence of issuing DSRY instruction is: CS# goes low → send DSRY instruction code → CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
37
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
POWER-ON STATE
The device is at below states when power-up:
- Standby mode ( please note it is not Deep Power-down mode)
- Write Enable Latch (WEL) bit is reset
- 4-byte address mode
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the gure of "Power-up Timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.
(generally around 0.1uF)
38
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specication is not implied. Exposure
to absolute maximum rating conditions for extended period may affect reliability.
2. Specications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 3, 4.
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL SPECIFICATIONS
CAPACITANCE TA = 25°C, f = 1.0 MHz
Figure 3. Maximum Negative Overshoot Waveform
Vss
Vss-2.0V
20ns 20ns
20ns
Figure 4. Maximum Positive Overshoot Waveform
Vcc + 2.0V
Vcc
20ns 20ns
20ns
SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS
CIN Input Capacitance 6 pF VIN = 0V
COUT Output Capacitance 8 pF VOUT = 0V
RATING VALUE
Ambient Operating Temperature Industrial grade -40°C to 85°C
Storage Temperature -55°C to 125°C
Applied Input Voltage -0.5V to 4.6V
Applied Output Voltage -0.5V to 4.6V
VCC to Ground Potential -0.5V to 4.6V
39
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Figure 5. OUTPUT LOADING
DEVICE UNDER
TEST
DIODES=IN3064
OR EQUIVALENT
CL 6.2K ohm
2.7K ohm
+3.3V
CL=30/15pF Including jig capacitance
40
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Table 7. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V)
SYMBOL PARAMETER NOTES MIN. MAX. UNITS TEST CONDITIONS
ILI Input Load Current 1 ± 4 uA VCC = VCC Max, VIN = VCC or GND,
HOLD# = VCC
ILO Output Leakage Current 1 ± 4 uA VCC = VCC Max, VIN = VCC or GND
ISB1 VCC Standby Current 1 200 uA VIN = VCC or GND, CS# = VCC,
HOLD# = VCC
ISB2 Deep Power-down
Current 80 uA VIN = VCC or GND, CS# = VCC,
HOLD# = VCC
ICC1 VCC Read 1
45 mA f=80MHz, fQ=70MHz (4 x I/O read)
SCLK=0.1VCC/0.9VCC, SO=Open
40 mA fT=70MHz (2 x I/O read)
SCLK=0.1VCC/0.9VCC, SO=Open
30 mA f=50MHz, SCLK=0.1VCC/0.9VCC,
SO=Open
ICC2 VCC Program Current
(PP) 1 25 mA Program in Progress, CS# = VCC
ICC3 VCC Write Status
Register (WRSR) Current 40 mA Program status register in progress,
CS#=VCC
ICC4 VCC Sector Erase
Current (SE) 1 25 mA Erase in Progress, CS#=VCC
ICC5 VCC Chip Erase Current
(CE) 1 40 mA Erase in Progress, CS#=VCC
VIL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage 0.4 V IOL = 1.6mA
VOH Output High Voltage VCC-0.2 V IOH = -100uA
41
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Table 8. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V)
Symbol Alt. Parameter Min. Typ. Max. Unit
fSCLK fC
Clock Frequency for the following instructions:
FAST_READ, PP, SE, BE, CE, DP, RES, RDP, WREN,
WRDI, RDID, RDSR, WRSR
D.C. 80 MHz
fRSCLK fR Clock Frequency for READ instructions 50 MHz
fTSCLK fT Clock Frequency for 2READ/DREAD instructions 70 MHz
fQ Clock Frequency for 4READ/QREAD instructions 70 MHz
f4PP Clock Frequency for 4PP (Quad page program) 20 MHz
tCH(1) tCLH Clock High Time Fast_Read 5.5 ns
Read 9 ns
tCL(1) tCLL Clock Low Time Fast_Read 5.5 ns
Read 9 ns
tCLCH(2) Clock Rise Time (3) (peak to peak) 0.1 V/ns
tCHCL(2) Clock Fall Time (3) (peak to peak) 0.1 V/ns
tSLCH tCSS CS# Active Setup Time (relative to SCLK) 8 ns
tCHSL CS# Not Active Hold Time (relative to SCLK) 5 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH CS# Active Hold Time (relative to SCLK) 5 ns
tSHCH CS# Not Active Setup Time (relative to SCLK) 8 ns
tSHSL(3) tCSH CS# Deselect Time
Read 15 ns
Write/Erase/
Program 100 ns
tSHQZ(2) tDIS Output Disable Time 2.7V-3.6V 12 ns
3.0V-3.6V 10 ns
tCLQV tV Clock Low to Output Valid
VCC=2.7V~3.6V
Loading: 15pF 1 I/O 12 ns
2 I/O & 4 I/O 12 ns
Loading: 30pF 2 I/O & 4 I/O 15 ns
tCLQX tHO Output Hold Time 2 ns
tHLCH HOLD# Setup Time (relative to SCLK) 8 ns
tCHHH HOLD# Hold Time (relative to SCLK) 5 ns
tHHCH HOLD Setup Time (relative to SCLK) 8 ns
tCHHL HOLD Hold Time (relative to SCLK) 5 ns
tHHQX(2) tLZ HOLD to Output Low-Z 2.7V-3.6V 12 ns
3.0V-3.6V 10 ns
tHLQZ(2) tHZ HOLD# to Output High-Z 2.7V-3.6V 12 ns
3.0V-3.6V 10 ns
tWHSL(4) Write Protect Setup Time 20 ns
tSHWL(4) Write Protect Hold Time 100 ns
tDP(2) CS# High to Deep Power-down Mode 10 us
42
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Notes:
1. tCH + tCL must be greater than or equal to 1/ fC.
2. Value guaranteed by characterization, not 100% tested in production.
3.Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
Symbol Alt. Parameter Min. Typ. Max. Unit
tRES1(2) CS# High to Standby Mode without Electronic
Signature Read 100 us
tRES2(2) CS# High to Standby Mode with Electronic Signature
Read 100 us
tW Write Status Register Cycle Time 40 100 ms
tBP Byte-Program 9 300 us
tPP Page Program Cycle Time 1.4 5 ms
tSE Sector Erase Cycle Time (4KB) 60 300 ms
tBE Block Erase Cycle Time (32KB) 0.5 2 s
tBE Block Erase Cycle Time (64KB) 0.7 2 s
tCE Chip Erase Cycle Time 160 400 s
tWPS Write Protection Selection Time 1 ms
tWSR Write Security Register Time 1 ms
43
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Figure 6. Serial Input Timing
Figure 7. Output Timing
Timing Analysis
SCLK
SI
CS#
MSB
SO
tDVCH
High-Z
LSB
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
LSB
ADDR.LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
SCLK
SO
CS#
SI
44
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
tCHHL
tHLCH
tHHCH
tCHHH
tHHQXtHLQZ
SCLK
SO
CS#
HOLD#
Figure 8. Hold Timing
* SI is "don't care" during HOLD operation.
Figure 9. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
High-Z
01
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
tWHSL tSHWL
SCLK
SI
CS#
WP#
SO
45
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Figure 10. Write Enable (WREN) Sequence (Command 06)
Figure 11. Write Disable (WRDI) Sequence (Command 04)
21 34567
High-Z
0
04
SCLK
SI
CS#
SO
Command
21 34567
High-Z
0
06
Command
SCLK
SI
CS#
SO
Figure 12. Read Identication (RDID) Sequence (Command 9F)
21 345678910 11 12 13 14 150
Manufacturer Identification
High-Z
MSB
Device Identification
MSB
D7 D15 D14 D13D6 D5 D3 D3D2 D2D1 D1D0 D0D4
16 17 18 28 29 30 31
SCLK
SI
CS#
SO
9F
Command
46
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Figure 13. Read Status Register (RDSR) Sequence (Command 05)
Figure 14. Write Status Register (WRSR) Sequence (Command 01)
21 345678910 11 12 13 14 15
command
0
D7 D6 D5 D4 D3 D2 D1 D0
Status Register Out
High-Z
MSB
SCLK
SI
CS#
SO
05
21 345678910 11 12 13 14 15
Status
Register In
0
MSB
SCLK
SI
CS#
SO
01
High-Z
command
D7 D6 D5 D4 D3 D2 D1 D0
47
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Figure 15. Read Data Bytes (READ) Sequence (Command 03)
SCLK
SI
CS#
SO
Data Out 1
MSB MSB
MSB Data Out 2
03
High-Z
Command
D7
A31 A30 A29 A3 A2 A1 A0
D7D6 D5 D4 D3 D2 D1 D0
32 ADD Cycles
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
High-Z
8 Dummy Cycles
MSB
SCLK
SI
CS#
SO
0B
Command
D7 D7D6 D5 D4 D3 D2 D1 D0
Data Out 1 Data Out 2
A3 A2 A1 A0
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
32 ADD Cycles
A31 A30 A29
48
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Figure 17. 2 x I/O Read Mode Sequence (Command BB)
High Impedance
21 3456780
SCLK
SI/SIO0
SO/SIO1
CS#
9
BB(hex)
22 23 24 25 26 27 28 29 30 31 32 33
P0
P2
P1
P3
D4
D5
D2
D3
D7
D6 D6 D4
D0
D7 D5
D1
Command 16 ADD Cycle 4 dummy
cycle
A30 A28 A2 A0
A3 A1
A31 A29
Data Out
1
Data Out
2
Note:
1. SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the rst two dummy cycles. In other words, P2=P0 or P3=P1 is
necessary.
Figure 18. Dual Read Mode Sequence (Command 3B)
High Impedance
21 3456780
SCLK
SI/SIO0
SO/SIO1
CS#
938 39 40 47 48 49 51 52 5350
3B D4
D5
D2
D3
D7
D6 D6 D4
D0
D7 D5
D1
Command 32 ADD Cycle 8 dummy
cycle
A31 A30 A1 A0
Data Out
1
Data Out
2
49
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Figure 19. 4 x I/O Read Mode Sequence (Command EB)
High Impedance
21 3456780
SCLK
SI/SIO0
SO/SIO1
CS#
9 1210 11 13 14
EB P4 P0
P5 P1
P6 P2
P7 P3
15 16 17 18 19 20 21 22 23 24 25
High Impedance
WP#/SIO2
High Impedance
HOLD#/SIO3
4 dummy
cycles
Performance
Enhance
Indicator
(Note1, 2)
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
D4
D5
D6
D7
A28
A29
A30
A31
A24
A25
A26
A27
A20
A21
A22
A23
A16
A17
A18
A19
A12
A13
A14
A15
A0
A1
A2
A3
A8
A9
A10
A11
A4
A5
A6
A7
Command 8 ADD Cycles Data
Out 1
Data
Out 2
Data
Out 3
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) will result in entering the performance enhance mode.
Figure 20. Quad Read Mode Sequence (Command 6B)
High Impedance
21 3456780
SCLK
SI/SO0
SO/SO1
CS#
37
938 39 40 41 46 47 48 49 50
6B
High Impedance
WP#/SO2
High Impedance
HOLD#/SO3
8 dummy cycles
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
D4
D5
D6
D7
A31 A30 A2 A1 A0
Command 32 ADD Cycles Data
Out 1
Data
Out 2
Data
Out 3
…
…
…
50
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Figure 21. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)
High Impedance
6 7 810
SCLK
SI/SIO0
SO/SIO1
CS#
9 1210 11 13 14
EB P4 P0
P5 P1
P6 P2
P7 P3
15 16 n+1 n+9 n+11 n+15
17 18 19 20 21 22 23 24 25
High Impedance
WP#/SIO2
High Impedance
HOLD#/SIO3
4 dummy
cycles 4 dummy
cycles
Performance
enhance
indicator (Note)
P4 P0
P5 P1
P6 P2
P7 P3
Performance
enhance
indicator (Note)
Command 8 ADD Cycles 8 ADD
A20
A21
A22
A23
A16
A17
A18
A19
A12
A13
A14
A15
A8
A9
A10
A11
A4
A5
A6
A7
A0
A1
A2
A3
A28
A29
A30
A31
A24
A25
A26
A27
A28
A29
A30
A31
A0
A1
A2
A3
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
Data
Out 1
Data
Out 2
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
D4
D5
D6
D7
Data
Out 1
Data
Out 2
Data
Out 3
Cycles
Note:
1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F
2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
Figure 22. Sector Erase (SE) Sequence (Command 20)
MSB
SCLK
CS#
SI
20
Command 32 ADD Cycles
A31 A30 A2 A1 A0
…
…
0 1 2 3 4 5 6 7 8 9 37 38 39
51
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Figure 24. Chip Erase (CE) Sequence (Command 60 or C7)
21 345670
60 or C7
SCLK
SI
CS#
Command
Figure 23. Block Erase (BE/EB32K) Sequence (Command D8/52)
MSB
SCLK
CS#
SI
D8/52
Command 32 ADD Cycles
A31 A30 A2 A1 A0
0 1 2 3 4 5 6 7 8 9 37 38 39
Figure 25. Page Program (PP) Sequence (Command 02)
32 ADD Cycles Data Byte 1 Data Byte 256
2080
2081
2082
2083
2084
2085
2086
2087
MSB MSB
SCLK
CS#
SI
02
Command
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
A31 A30 A29 A3 A2 A1 A0
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
52
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Figure 26. 4 x I/O Page Program (4PP) Sequence (Command 38)
A20 A16 A12 A8 A4 A0
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
A23 A19 A15 A11 A7 A3
21 3456789
8 ADD cycles Data
Byte 1
Data
Byte 2
Data
Byte 256
0
A29 A25
A30 A26
A31 A27
A28 A24
SCLK
CS#
SI/SIO0
SO/SIO1
HOLD#/SIO3
WP#/SIO2
38
Command
10 11 12 13 14 15 16 17
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
D4 D0
D5 D1
D6 D2
D7 D3
18 19 526 527
Figure 27. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)
Note:
1. During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05
hex), and RDSCUR command (2B hex).
2. Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and CS# goes
high will return the SO pin to tri-state.
3. To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI) command (04
hex) may achieve it and then it is recommended to send RDSR command (05 hex) to verify if CP mode is ended.
CS#
SCLK
0 1 6 7 8 9
SI
Command
AD (hex)
38 39 40
S0 high impedance
41 55 56
status (Note 2)
data in
32-bit address Byte 0, Byte1
0 1
Valid Command
(Note 1)
data in
Byte n-1, Byte n
6 7 8
28 29 30 31 0
04 (hex)
32 707
05 (hex)
8
53
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Figure 28. Deep Power-down (DP) Sequence (Command B9)
21 345670tDP
Deep Power-down Mode
Stand-by Mode
SCLK
CS#
SI
B9
Command
Figure 30. Release from Deep Power-down (RDP) Sequence (Command AB)
21 345670tRES1
Stand-by Mode
Deep Power-down Mode
High-Z
SCLK
CS#
SI
SO
AB
Command
Figure 29. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
21 345678910 28 29 30 31 32 33 34 35 36 37 38
High-Z Electronic Signature Out
0
MSB
Stand-by Mode
Deep Power-down Mode
MSB
tRES2
SCLK
CS#
SI
SO
AB
Command
…
D7 D6 D5 D4 D3 D2 D1 D0
39
24 Dummy Cycles
23 22 21 3 2 1 0
54
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Notes:
1. A0=0 will output the Manufacturer ID rst and A0=1 will output Device ID rst. A1~A31 is don't care.
2. Instruction is either 90(hex) or EF(hex) or DF(hex).
Figure 31. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)
21 3456789100 32 33 34 36 37 38 39 40 41 42 43 44 45 46
Manufacturer ID
MSB
Device ID
MSB MSB
47
35
SCLK
SI
CS#
SO
90
High-Z
Command
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
2 Dummy Bytes
15 14 13 3 2 1 0 7 6 5 4 3 2 1 0
20 21 22 23 24 25 2726 28 29 30 31
ADD (1)
Figure 32. Write Protection Selection (WPSEL) Sequence (Command 68)
21 345670
68
SCLK
SI
CS#
Command
55
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Figure 33. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)
Figure 34. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)
32 ADD Cycles
MSB
SCLK
CS#
SI
36/39
Command
A31 A30 A2 A1 A0
0 1 2 3 4 5 6 7 8 9 37 38 39
High-Z
Block Protection Lock status out
32 ADD Cycles
MSB
MSB
SCLK
CS#
SI
SO
3C
Command
A31 A30 A29 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
Figure 35. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)
21 345670
7E/98
SCLK
SI
CS#
Command
56
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Figure 36. Power-up Timing
Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
Note: 1. The parameter is characterized only.
Table 9. Power-Up Timing
VCC
VCC(min)
VWI
Reset State
of the
Flash
Chip Selection is Not Allowed
Program, Erase and Write Commands are Ignored
tVSL
tPUW
time
Read Command is
allowed
Device is fully
accessible
VCC(max)
Symbol Parameter Min. Max. Unit
tVSL(1) VCC(min) to CS# low 300 us
tPUW(1) Time delay to write instruction 1 10 ms
vWI(1) Write inhibit voltage 1.5 2.5 V
57
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the gure, please refer to
"AC CHARACTERISTICS" table.
Symbol Parameter Notes Min. Max. Unit
tVR VCC Rise Time 1 20 500000 us/V
OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in Figure 37 and Figure 38 are for the supply voltages and the control signals at device power-
up and power-down. If the timing in the gures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 37. AC Timing at Device Power-Up
SCLK
SI
CS#
VCC
MSB IN
SO
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
tVR
VCC(min)
GND
58
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
Figure 38. Power-Down Sequence
CS#
SCLK
VCC
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
59
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
ERASE AND PROGRAMMING PERFORMANCE
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the rst-bus-cycle sequence for the programming com-
mand.
LATCH-UP CHARACTERISTICS
MIN. MAX.
Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax
Input Voltage with respect to GND on SO -1.0V VCC + 1.0V
Current -100mA +100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
PARAMETER TYP. (1) Max. (2) UNIT
Write Status Register Cycle Time 40 100 ms
Sector Erase Time (4KB) 60 300 ms
Block Erase Time (64KB) 0.7 2 s
Block Erase Time (32KB) 0.5 2 s
Chip Erase Time 160 400 s
Byte Program Time (via page program command) 9 300 us
Page Program Time 1.4 5 ms
Erase/Program Cycle 100,000 cycles
DATA RETENTION
PARAMETER Condition Min. Max. UNIT
Data retention 55˚C 20 years
60
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
ORDERING INFORMATION
PART NO. CLOCK
(MHz)
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (uA)
TEMPERATURE PACKAGE Remark
MX25L25735EMI-12G 80 45 200 -40°C~85°C 16-SOP
(300mil) Pb-free
MX25L25735EZNI-12G 80 45 200 -40°C~85°C 8-WSON
(8x6mm) Pb-free
61
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
PART NAME DESCRIPTION
MX 25 L M I
TEMPERATURE RANGE:
I: Industrial (-40° C to 85° C)
PACKAGE:
M: 300mil 16-SOP
DENSITY & MODE:
25735E: 256Mb Quad I/O with 4-bytes address
TYPE:
L: 3V
DEVICE:
25: Serial Flash
25735E 12 G
OPTION:
G: Pb-free
SPEED:
12: 80MHz
ZN: 8x6mm 8-WSON
62
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
PACKAGE INFORMATION
63
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
64
MX25L25735E
P/N: PM1586 REV. 1.0, JUL. 01, 2010
REVISION HISTORY
Revision No. Description Page Date
1.0 1. Removed DMC sequence description & content table P6,13,16 JUL/01/2010
2. Removed command WREN in WPSEL and WRSCUR ows P30,31,33
3. Removed "Preliminary" P5
65
Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which
the failure of a single component could cause death, personal injury, severe physical damage, or other substan-
tial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft
and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims,
injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications.
Copyright© Macronix International Co., Ltd. 2010. All Rights Reserved. Macronix, MXIC, MXIC Logo, MX Logo,
MXSMIO,
are trademarks or registered trademarks of Macronix International Co., Ltd.. The names and brands
of other companies are for identication purposes only and may be claimed as the property of the respective
companies.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MX25L25735E
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specications without notice.