© 2000 Fairchild Semiconductor Corporation DS010202 www.fairchildsemi.com
March 1989
Revised August 2000
DM93L38 8-Bit Multiple Port Register
DM93L38
8-Bit Multi ple Port Register
General Description
The DM93L38 is an 8-bit multiple port register designed for
high speed random access memory applications where the
ability to simultaneously read and write is desirable. A com-
mon use would be as a register bank in a three address
computer. Data can be written into any one of the eight bits
and read from any two of the eight bits simultaneously. The
circuit uses TTL techno logy and is compati ble with all TTL
families.
Features
■Master/slave operation permitting simultaneous write/
read without race problems
■Simultaneously read two bits and write one bit in any
one of eight bit positions
■Readily expandable to allow for larger word sizes
Ordering Code:
Logic Symbol
VCC = Pin 16
GND = Pin 8
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
DM93L38N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
A0–A2 Write Address Inpu ts
DA Data Input
B0–B2 B Read Address Inputs
C0–C2 C Read Address Inputs
CP Clock Pulse Input (Active Rising Edge)
SLE Slave Enable Input (Active LOW)
ZB B Output
ZC C Output
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DM93L38
Functional Description
The DM93L38 8-bit multiple port register can be consid-
ered a 1-bit slice of eight high speed working registers.
Data c an be writ ten in to any on e and r ead fro m any two of
the eight locations simultaneously. Master/slave operation
eliminates all r ace problems asso ciated with simultaneous
read/wr ite activity from the sam e location. When t he clock
input (CP ) is LOW data ap plied to the d ata input line (D A)
enters the selected m aster. This selec tion is accomplished
by coding the th ree write inp ut select lin es (A0–A2) ap pro-
priately. Data is stored synchronously with the rising edge
of the clock pulse.
The information for each of the two slaved (output) latches
is select ed by two sets o f read a ddress in puts (B 0–B2 and
C0–C2). The information enters the slave while the clock is
HIGH and is stored while the clock is LOW. If Slave Enable
is LOW (SLE), the slave la tches ar e continu ously enable d.
The signals are available on the output pins (ZB and ZC).
The input bit selection and the two output bit selections can
be accomplished independently or simultaneously. The
data flows into the device, is demultiplexed according to
the state of th e write addre ss lines and is clocke d into the
selected latch. The eight latches function as masters and
store the input data. Th e two ou tput latches ar e sl ave s and
hold th e data du ring the r ead oper ation. The state of e ach
slave is d etermined by the sta te of the master sel ected by
its associated set of read address inputs.
The method of parallel expansion is shown in Figure 1.
One DM 93L38 is n eeded for each bi t of the r equired wo rd
length. Th e r ead an d wr it e inp ut l in es sh ou l d be con nec ted
in common on all of the devices. This register configuration
provides two words of n-bits each at one time, where n
devices are connected in parallel.
FIGURE 1. Parallel Expansion
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DM93L38
Logic Diagram
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DM93L38
Absolute Maximum Ratings(Note 1) Note 1: The “Absolute Maximum Ratings” are thos e values bey ond which
the saf ety of the device cannot be gu aranteed. Th e device shoul d not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “R ecomm ended Oper ating Co ndition s” table will def ine the condit ions
for actu al device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Note 2: All typical s are at VCC = 5V, TA = 25°C.
Note 3: Not more tha n one out put shoul d be shorte d at a t im e, and the duration sh ould not ex c eed one s ec ond.
Note 4: ICC is measu r ed with all out puts OPE N and all input grounded.
Supply Voltage 7V
Input Voltag e 5.5 V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Symbol Parameter Min Norm Max Units
VCC Supply Voltage 4.5 5 5.5 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.7 V
IOH HIGH Level Output Current −400 µA
IOL LOW Level Output Current 4.8 mA
TAFree Air Operating Temperature −55 125 °C
tS (H) Setup Time HIGH or LOW 30 ns
tS (L) DA to CP 22
tH (H) Hold Time HIGH or LOW 0 ns
tH (L) DA to CP −4.0
tS (H) Setup Time HIGH or LOW 0 ns
tS (L) An to CP 0
tH (H) Hold Time HIGH or LOW 0 ns
tH (L) An to CP 0
tW (H) CP Pulse Width HIGH or LOW 40 ns
tW (L) 30
Symbol Parameter Conditions Min Typ Max Units
(Note 2)
VIInput Clamp Voltage VCC = Min, II = −10 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max, 2.4 V
Output Voltage VIL = Max, VIH = Min
VOL LOW Level VCC = Min IOL = Max 0.3 V
Output Voltage VIH = Min, VIL = Max
IIInput Current @ Max Input Voltage VCC = Max, VI = 5.5 V 1 mA
IIH HIGH Level Input Current VCC = Max, VI = 2.4V 50 µA
IIL LOW Level Input Current VCC = Max, VI = 0.3V −2mA
IOS Short Circuit Output Current VCC = Max (Note 3) −2.5 −25 mA
ICC Supply Current VCC = Max (Note 4) 70 mA
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DM93L38
Switching Characteristics
VCC = +5.0V, TA = +25°C
Symbol Parameter CL = 15 pF Units
Min Max
tPLH Propagation Delay 68 ns
tPHL Bn or Cn or Zn95
tPLH Propagation Delay 70 ns
tPHL DA to Zn92
tPLH Propagation Delay 65 ns
tPHL CP to Zn57
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DM93L38 8-Bit Multipl e Port Register
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syste ms are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent i n any compon ent of a lif e supp ort
device or system whose failure to perform can be rea-
sonabl y ex pect ed to ca use the fa ilu re of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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