HD6417615ARFV - Renesas Technology / Hitachi Semiconductor

Revision Date: Mar 17

2005

32 SH7615 Group

Hardware Manual

Renesas 32-Bit RISC Microcomputer

SuperH



RISC engine Family/SH7600 Series

SH7615 HD6417615

Rev. 2.00

REJ09B0157-0200O

The revision list can be viewed directly by

clicking the title page.

The revision list summarizes the locations of

revisions and additions. Details should always

be checked by referring to the relevant text.

Rev. 2.00, 03/05, page ii of xxxvii i

1. These materials are intended as a reference to assist our customers in the selection of the Renesas

Technology Corp. product best suited to the customer's application; they do not convey any license

under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or

a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-

party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or

circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and

algorithms represents information on products at the time of publication of these materials, and are

subject to change by Renesas Technology Corp. without notice due to product improvements or

other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or

an authorized Renesas Technology Corp. product distributor for the latest product information

before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising

from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corp. by various means,

including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,

diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total

system before making a final decision on the applicability of the information and products. Renesas

Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the

information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or

system that is used under circumstances in which human life is potentially at stake. Please contact

Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when

considering the use of a product contained herein for any specific purposes, such as apparatus or

systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in

whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must

be exported under a license from the Japanese government and cannot be imported into a country

other than the approved destination.

Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the

country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products

contained therein.

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and

more reliable, but there is always the possibility that trouble may occur with them. Trouble with

semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate

measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or

(iii) prevention against any malfunction or mishap.

Keep safety first in your circuit designs!

Notes regarding these materials

Rev. 2.00, 03/05, page iii of xxxviii

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are

they are used as test pins or to reduce noise. If something is connected to the NC pins, the

operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins

are in their open states, intermediate levels are induced by noise in the vicinity, a pass-

through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the

chip and a low level is input on the reset pin. During the period where the states are

undefined, the register settings and the output state of each pin are also undefined. Design

your system so that it does not malfunction because of processing while it is in this

undefined state. For those products which have a reset function, reset the LSI immediately

after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers

may have been be allocated to these addresses. Do not access these registers; the system’s

operation is not guaranteed if they are accessed.

Rev. 2.00, 03/05, page iv of xxxviii

Config uration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Config uration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the

module. However, the generic style includes the following items:

i) Feature

ii) Input/Outpu t Pin

iii) Register Description

iv) Operation

v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each

section includes notes in relation to the descriptions given, and usage notes are given, as required,

as the final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10.Main Revisions and Additions in this Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions.

This does not include all of the revised contents. For details, see the actual locations in this

manual.

11.Index

Rev. 2.00, 03/05, page v of xxxvi ii

Preface

The SH7615 RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas

Technology original RISC CPU as its core, and the peripheral functions required to configure a

system.

Target Users: This manual was written for users who will be using this LSI in the design of

application systems. Users of this manual are expected to understand the

fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of this LSI to the above users.

Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the

instruction set.

Notes on reading this manual:

• Produ ct names

The following products are covered in this manual.

Product Classifications and Abbreviations

Basic Classification Product Code

SH7615 HD6417615

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts

on the CPU, system control functions, peripheral functions, and electrical characteristics.

• In order to understand the details of the CPU's functions

Read the SH-1/SH-2/SH-DSP Software Manual.

Rev. 2.00, 03/05, page vi of xxxviii

Rules: Register name: The following notation is used for cases when the same or a

similar function, e.g. serial communication, is implemented

on more than one channel:

XXX_N (XXX is the register name and N is the channel

number)

Bit order: The MSB (most significant bit) is on the left and the LSB

(least significant bit) is on the right.

Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.

Signal notation: An overbar is added to a low-active signal:

xxxx

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.

(http://www.renesas.com/)

SH7615 manuals:

Document Title Document No .

SH7615 Hardware Manual This manual

SH-1/SH-2/SH-DSP Software Manual REJ09B0171

Users manuals for development tools:

Document Title Document No .

SuperH RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor

User's Manual REJ10B0152

SuperH RISC engine High-performance Embedded Workshop User's Manual REJ10B0025

SuperH RISC engine High-performance Embedded Workshop, Tutorial REJ10B0023

SuperH RISC engine C/C++ Compiler Package Application Note REJ05B0463

Rev. 2.00, 03/05, page vii of xxxviii

Abbreviations

ADC Analog to Digital Converter

ALU Arithmetic Logic Unit

ASE Adaptive System Evaluator

ASID Address Space Identifier

AUD Advanced User Debugger

BCD Binary Coded Decimal

bps bit per second

BSC Bus State Controller

CCN Cache memory Controller

CMT Compare Match Timer

CPG Clock Pulse Generator

CPU Central Proce ssing Uni t

DMAC Direct Memory Access Controller

etu Elementary Time Unit

FIFO First-In First-Out

Hi-Z High Impedance

H-UDI High-performance User Debugging Interface

INTC Interrupt Controller

IrDA Infrared Data Association

JTAG Joint Test Action Group

LQFP Low Profile QFP

LRU Least Recently Used

LSB Least Significant Bit

MMU Memory Management Unit

MPX Multiplex

MSB Most Significant Bit

PC Program Counter

PFC Pin Function Controller

PLL Phase Locked Loop

PWM Pulse Width Modulation

RAM Random Access Memory

RISC Reduced Instruction Set Computer

ROM Read Only Memory

RTC Real Time Clock

SCIF Serial Communication Interface with FIFO

SDRAM Synchronous DRAM

Rev. 2.00, 03/05, page viii of xxxviii

TAP Test Access Port

T.B.D To Be Determined

TLB Translation Lookaside Buffer

TMU Timer Unit

TPU Timer Pulse Unit

UART Universal Asynchronous Receiver/Transmitter

UBC User Break Controller

USB Universal Serial Bus

WDT Watchdog Timer

Rev. 2.00, 03/05, page ix of xxxviii

Main Rev isions and Additions in this Edition

Item Page Revisions (See Manual for Details)

General All BP-240A and BP-240AV packages added

1.1 Features of SuperH

Microcomputer with On-

Chip Ethernet Controller

Table 1.1 Features

7Descripti on added to the features of direct memory access

controller (DMAC)

 When synchronous DRAM is connected, single-address

transfer is available in a single clock cycle at maximum 31.25

MHz

1.2 Block Diagram

Figure 1.1 Block

Diagram of SH7615

13 Figure 1.1 amended

Internal X address bus

Internal Y address bus

16-bit internal X data bus

16-bit internal Y data bus

1.3.1 Pin Arrangement 14 Description modified

Figure 1.2 shows the pin arrangement of the HD6417615ARF

and HD6417615ARFV, and figure 1.3 shows the pin

arrangement of the HD6417615ARBP and

HD6417615ARBPV.

Rev. 2.00, 03/05, page x of xxxviii

Item Page Revisions (See Manual for Details)

1.3.1 Pin Arrangement

Figure 1.2

HD6417615ARF and

HD6417615ARFV Pin

Arrangement (FP-208C,

FP-208CV)

14 Figure 1.2 title amended, package name amended

(Before) FP-208C (Top view) → (After) FP-208C, FP-208CV

(Top view)

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

PVSS

PB10/SRXD2/TIOCA1

PB9/STCK2/TIOCB1/TCLKC

PB8/STS2/TIOCA2

PB7/STXD2/TIOCB2/TCLKD

PB6/SRCK1/SCK2

PB5/SRS1/RXD2

PB4/SRXD1/TXD2

PB3/STCK1/TIOCA0

PB2/STS1/TIOCB0

PVCC

PB1/STXD1/TIOCC0/TCLKA

PVSS

PB0/TIOCD0/TCLKB/WOL

PA13/SRCK0

PA12/SRS0

PA11/SRXD0

PA10/STCK0

PA9/STS0

PA8/STXD0

PA7/WDTOVF

PA6/FTCI

PVCC

PA5/FTI

PVSS

PA4/FTOA

CKPO/FTOB

PA2/LNKSTA

PA1/EXOUT

PA0

RX-ER

RX-DV

COL

CRS

PVSS

RX-CLK

PVCC

ERXD0

ERXD1

ERXD2

ERXD3

MDIO

MDC

PVCC

TX-CLK

PVSS

TX-EN

ETXD0

ETXD1

ETXD2

ETXD3

TX-ER

Figure 1.3

HD6417615ARBP and

HD6417615ARBPV Pin

Arrangement (BP-240A,

BP-240AV)

15 Figure 1.3 added

1.3.2 Pin Functions

Table 1.2 Pin Functions 18 to

20 Table 1.2 amended

Ethernet

controller

(EtherC)

ETXD0 to

ETXD3 Output Transmit data

0 to 3 4-bit transmit data

Serial

communi-

cation

interface with

FIFO (SCIF)

RXD1, RXD2 Input Receive data

input channel

1, 2

SCIF channel 1 and 2 receive data input

pins

Type Symbol I/O Name Function

Bus contro BUSHiZ Input Bus high

impedance

Signal used in combination with WAIT

signal to place bus and strobe signals in

the high-impedance (HiZ) state without

ending the bus cycle

1.3.3 Pin Multiplexi ng

Table 1.3 Pin

Multiplexing

22 to

27 Table 1.3 amended

The pin numbers for the BP-240A and BP-240AV packages

are added.

Rev. 2.00, 03/05, page xi of xxxviii

Item Page Revisions (See Manual for Details)

1.4 Processi ng States 29 Bus-Released State

Description added

1. In the bus-released state, the CPU releases the bus to a

device that has requested it.

2. Bus-released state duri ng manual reset signal assertion

While the manual reset signal is being asserted (

RES

low and NMI = low), no arbitration request (

BRLS

input) is

accepted. If the

BRLS

signal continues to be asserted, this

LSI remains in the bus-released state (asserts the

BGR

signal).

When the

BRLS

signal is negated in the bus-released

state during manual reset signal assertion, this LSI starts

using the bus (negates the

BGR

signal ).

2.2.5 DSP Type

Instructions and Data

Formats

Table 2.5 Destination

DSP Instructions

49 Table 2.5 amended

39 to 32 31 to 16 15 to 0

A0, A1 Data transfer MOVS.W Sign extend 16-bit data

MOVS.L 32-bit data

X0, X1, Y0,

Y1, M0, M1 Data transfer MOVX.W,

MOVY.W,

MOVS.W

16-bit data

MOVS.L 32-bit data

2.6 Usage Notes 104 to

106 3. and 4. added

3.2.3 Connecting a

Crystal Resonator

Figure 3.2 Example of

Crystal Oscillator

Connection

112 Note 1 amended

Note: 1. The CKIO pin is an output or high impedance in

clock modes 0,1, and 2, and is high impedance in clock mode

3.2.4 External Clock

Input

Figure 3.3 External Clock

Input Method

113 Description amended

The CKIO pin is an output or high impedance in clock modes

0, 1, and 2, and is high impedance in clock mode 3.

3.2.7 Notes on Board

Design 123 When Using an External Crystal Oscillator

Description added

Figure 3.5 shows an example of the oscillator circuit. This is a

sample oscillator ci rcuit and in the actual system, the values

shown in the figure are affected by the environment such as

noise, power supply characteristics, or wiring patterns. These

values cannot be guaranteed and should be used as

reference values. To determine the optimu m oscillator circuit

constants for the user system, please consult with the crystal

resonator manufacturer.

Rev. 2.00, 03/05, page xii of xxxviii

Item Page Revisions (See Manual for Details)

3.2.7 Notes on Board

Design

Figure 3.5 Points for

Attention when Using

Crystal Resonator

123 Figure 3.5 amended

Circuit constants added and crystal resonator information

added

Bypass Capacitors

Description amended

1. VSS/VCC pairs for FP-208C and FP-208CV

124 Description added

2. VSS/VCC pairs for BP-240A and BP-240AV

5.3.29 IRQ

Control/Status Register

(IRQCSR)

189 Bits 15 to 8—IRQ Sense Select Bits (IRQ31S to IRQ00S)

Bit table amended

Bits 15 to 8:

IRQn1S Bits 15 to 8:

IRQn0S Description

0 0 Low-level detection (Initial value)

1 Falling-edge dete ction

1 0 Rising-edge detection

1 Both-edge detection

7.2.1 Bus Control

Note added

Note: Data rearrangement into little-endian format requires no

extra processing time.

260 Bit 3—Endian Specification for Area 4 (A4ENDIAN)

Note: Data rearrangement into little-endian format requires no

extra processing time.

7.2.7 Individual Memory

Control Re gister (MCR) 271 • For DRAM interface

Bit table added

Bit 1: TRP1 Bit 15: TRP0 Description

0 0 1 cycle (Initial value)

1 2 cycles

1 0 Reserved (do not set)

1 Reserved (do not set)

• For synchronous DRAM interface

Bit table added

Bit 1: TRP1 Bit 15: TRP0 Description

0 0 1 cycle (Initial value)

1 2 cycles

1 0 3 cycles

1 4 cycles

274 • For synchronous DRAM interface

Bit table replaced

Rev. 2.00, 03/05, page xiii of xxxviii

Item Page Revisions (See Manual for Details)

7.5.3 Burst Reads

Figure 7.19 (a) Basic

Burst Read Timing (Auto-

Precharge) Except

tEcyc:tPcyc 1:1

Figure 7.20 (a) Burst

Read Wait Specificat ion

Timing (Auto-Precharge)

Except tEcyc:tPcyc 1:1

Figure 7.21 (a) Single

Read Timing (Auto-

Precharge) Except

tEcyc:tPcyc 1:1

Figure 7.23 (a) Basic

Burst Write Timing (Auto-

Precharge) Except

tEcyc:tPcyc 1:1

Figure 7.24 (a) Burst

Read Timing (No

Precharge) Except

tEcyc:tPcyc 1:1

Figure 7.25 (a) Burst

Read Timing (Bank

Active, Same Row

Address)

Except tEcyc:tPcyc 1:1

Figure 7.26 (a) Burst

Read Timing (Bank

Active, Different Row

Addresses)

Except tEcyc:tPcyc 1:1

297,

299,

302,

305,

308,

310,

312

Figure title am ended

7.5.11 64-Mbit

Synchronous DRAM (2

Mword × 32 Bit)

Connection

323 Synchronous DRAM Mode Settings

Description amended

Synchronous DRAM Mode Settings: To make mode settings

for the synchronous DRAM, write to address X + H'FFFF0000

or X + H'FFFF8000 from the CPU. (X represents the setting

value.) Whether to use X + H'FFFF0000 or X + H'FFFF8000

determines on the synchronous DRAM used.

Figure 7.35 128-Mbit

Synchronous DRAM (4

Mwords × 32 Bits)

Connection Example

324 • 128-Mbit Synchronous DRAM (4 Mwords × 32 Bits)

Connection Example

Figure 7.35 added

Rev. 2.00, 03/05, page xiv of xxxviii

Item Page Revisions (See Manual for Details)

7.5.11 64-Mbit

Synchronous DRAM (2

Mword × 32 Bit)

Connection

Figure 7.36 128-Mbit

Synchronous DRAM (8

Mwords × 16 Bits)

Connection Example

325 • 128-Mbit Synchronous DRAM (8 Mwords × 16 Bits)

Connection Example

Figure 7.36 added

Figure 7.37 256-Mbit

Synchronous DRAM (8

Mwords × 32 Bits)

Connection Example

326 • 256-Mbit Synchronous DRAM (8 Mwords × 32 Bits)

Connection Example

Figure 7.37 added

7.11.3 Preventing Wrong

Data Output to

Synchronous DRAM

358 Section 7.11.3 added

8.2.1 Cache Control

Regi ster (CCR)

Bit 4—Cache Purge Bit

(CP)

361 Description added

... the CP bit reverts to 0. The CP bit always reads 0. Read the

ca c h e to chec k if initia l iz a tion is c o mple te d .

9.2.1 EtherC Mode

Regi ster (ECMR) 384 Bit 1—Duplex Mode (DM)

Note added

Note: When internal loopback mode is specified (ILB = 1),

full-dupl ex transfer (DM = 1) must be used.

The duplex mode information (half-duplex or full-duplex)

detected by the PHY-LSI must be set to the DM bit. If this

setting does not match the duplex mode in the PHY-LSI, the

transfer rate may be degraded or a data collision may occur.

9.2.8 PHY Interface

Status Register (PSR) 391 Note added

Note: The LMON bit is cleared to 0 when the LNKSTA pin is

at a high level, and is set to 1 when the pin is at a low level.

9.3.1 Transmi ssion 405 Description amended

4. After waiting for the frame interval time (9.6 µs for 10Base

or 0.96 µs for 100Base), the transmitter enters the idle state,

and if there is more transmit data, continues transmitting.

9.5 Usage Notes 416 Section 9.5 added

10.2.2 E-DMAC Transmit

Request Register

(EDTRR)

422 Note added

For details on writing to the register, see section 10.4, Usage

Notes.

10.2.3 E-DMAC Receive

Request Register

(EDRRR)

423 Note added

For details on writing to the register, see section 10.4, Usage

Notes.

Rev. 2.00, 03/05, page xv of xxxviii

Item Page Revisions (See Manual for Details)

10.2.6 EtherC/E-DMAC

Status Regis ter (EESR) 426,

427 Bits 26 to 25

Description amended

Bit: 31 30 29 28 27 26 25 24

—————TABT RABT RFCOF

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R/W R/W R/W

Bits 31 to 27—Reserved: These bits are always read as 0. The write value should always read as 0.

Bit 26—Transmit abort detection (TABT): Indicates whether or not a transmit abort was detected.

Bit 26: TABT Description

0 Transmit abort not detected (Initial value)

1 Transmit abort detect ed

This bit will be set when any one or more of the following bits are set.

EESR bit 12: Illegal Transmit Frame (ITF)

EESR bit 11: Carrier Not Detected (CND)

EESR bit 10: Detect Loss of Carrier (DLC)

EESR bit 9: Delayed Collision Detect (CD)

Bit 25— Receive abort detected (RABT): Indicates whether or not a receive abort was detected.

Bit 25: RABT Description

0 Receive abort not detected (Initial value)

1 Receive abort detected

This bit will be set when any one or more of the following bits are set.

EESR bit 4: Receive Residual-Bit Frame (RRF)

EESR bit 3: Receive Too-Long Frame (RTLF)

EESR bit 2: Receive Too-Short Frame (RTSF)

EESR bit 1: PHY-LSI Receive Error (PRE)

EESR bit 0: CRC Error on Received Frame (CERF)

430 Bit 9—Delayed Collision Detect (CD)

Description amended

Bit 9—Delayed Collision Detect (CD): Indicates that a delayed collision has been detected during

frame transmission.

Bit 9: CD Description

0 Delayed Collision not detected (Initial value)

1 Delayed Collision detected (interrupt source)

10.2.8 Transmit/Receive

Status Copy Enable

437 • General description of register modified

• Bits 12 to 8, and 4 to 0 amended to reserved bits.

• Bit 7 Multicast Address Frame Receive (RMAF) Bit Copy

Enable (RMA FCE ) added.

10.2.10 Transmit FIFO

Threshold Register

(TFTR)

440,

441 Restriction added

Rev. 2.00, 03/05, page xvi of xxxviii

Item Page Revisions (See Manual for Details)

10.3.1 Descriptor List

and Data Buffers 449 Transmit Descriptor

Notes replaced

Notes: 1. The de scriptor start address must be specified to

align with an address boundary corresponding to the

descriptor length specified in the E-DMAC mode register

(EDMR).

2. The transm it buffer star t address must be specified to align

with a longword boundary. Note, however, that it must be

aligned with a 16-byte boundary when SDRAM i s connected.

Transmit Descriptor 0

(TD0) 451 Bit 27—Transmit Frame Error (TFE)

Description deleted

Indicates that one or other bit of the transmit frame status

indicated by bits 26 to 0 i s set. ...

Bits 26 to 0—Transmit Frame Status 26 to 0 (TFS26 to TFS0)

• Descriptions of TFS26 to TFS5 replaced

• Description of TFS1 am ended

Delayed Collision Detect in Transmission (corresponds to

CD bit in EESR)

Transmit Descriptor 2

(TD2) 452 Note replaced

Receive Descriptor Notes replaced

454 Bit 27—Receive Frame Error (RFE)

Description amended

... indicated by bits 26 to 0 is set. Whether or not the multicast

address frame receive information, which is part of the receive

frame status, is copied into this bit is specified by the

transmit/receive status copy enable register.

Bits 26 to 0—Receive Frame Status 26 to 0 (RFS26 to RFS0)

Description of RFS8 amended

Receive Descriptor 2

(RD2) 455 Note replaced

10.4 Usage Notes 461 Newly added

11.2.4 DMA Channel

Control Registers 0 and 1

(CHCR0, CHCR1)

Bit 4—Transfer Bus Mode

Bit (TB)

473 Description amended

When 1 (burst mode) i s set to bit TB, set 1 (edge detection) to

the DREQ select bit (DS).

11.5 Usage Notes 520 to

524 Notes 12, 13, 14, 15, and 16 added

Rev. 2.00, 03/05, page xvii of xxxviii

Item Page Revisions (See Manual for Details)

13.2.3 Reset

Control/Status Register

(RSTCSR)

553,

554 Description amended

RSTCR is initialized to H'1E by input of a reset signal from the

RES

pin, but is not initialized by the internal reset signal

generated by overflow of the WDT. It is initialized to H'1E in

standby mode, and in clock pause mode.

13.4.4 System Reset

with

WDTOVF

Figure 13.9 Example of

Circuit for System Reset

with

WDTOVF

Sign al

561 Figure 13.9 am ended

Reset input

Reset signal to

entire system

This LSI

RES

WDTOVF

13.4.6 Internal Reset by

Watchdog Timer (WDT) in

Sleep Mode

Section 13.4.6 added

14.2.6 Serial Control

Description amended

Bit 6—Receive Interrupt Enable (RIE): Enables or disables

generation of receive-FIFO-data full interrupt (RXI), receive-

error interr upt (ERI), and break interrupt (BRI) requests when,

after serial receive data is transferred from the receive shift

(SCFRDR), the number of data b y tes in SCFRDR reaches or

exceeds the receive trigger set number, and the RDF flag is

set to 1 in SC1SSR.

14.2.9 Bit Rate Register

(SCBRR)

Table 14.3 Examples of

Bit Rates and SCBRR

Settings in Asynchronous

Mode

587,

588 Table 14.3 amended

Pφ

φφ

φ (MHz)

Error

(%)

Error

(%)

2 212 0.03 3 132 0.13

2 155 0.16 3 97 –0.35

2 77 0.16 2 194 0.16

1 155 0.16 2 97 –0.35

1 77 0.16 1 194 0.16

0 155 0.16 1 97 –0.35

0770.16 0194 0.16

0 38 0.16 0 97 –0.35

019–2.34 0 48 –0.35

0 11 0.00 0 29 0.00

09 –2.34 0 23 1.73

Rev. 2.00, 03/05, page xviii of xxxviii

Item Page Revisions (See Manual for Details)

14.2.11 FIFO Data Count

Regi ster (SCFDR) 594 Description amended

SC F D R is initialize d t o H'0000 by a reset, by the module

standby function, and in standby mode.

14.3.2 Operation in

Asynchronous Mode

Transm it/Rece ive Form at

Table 14.10 Serial

Transm it/Rece ive Form ats

(Asynchronous Mode)

601 Table 14.10 amended

SCSMR Settings

Serial Transmit/Receive Format and Frame Length

CHR PE MP STOP 123456789101112

7-bit data

STOP

7-bit data

STOP

7-bit data

STOP

7-bit data

STOP

14.3.3 Multiprocessor

Communication Function

Figure 14.12 Sample

Multiprocessor Serial

Transmission Flowchart

613 Figure 14.12 amended

Read TEND bit in SC1SSR

TEND = 1? No

Yes

Figure 14.14 Sample

Multiprocessor Serial

Reception Flowchart (1)

616 Figure 14.14 (1) amended

BRK ∨ DR ∨ ER ∨ FER ∨

ORER = 1?

Read RDF flag in SC1SSR

RDF = 1?

Read receive data from SCFRDR,

and clear RDF flag to 0 in SC1SSR

This station’s ID?

Read BRK, DR, ER, and FER bits

in SC1SSR, and ORER bit in SC2SSR

BRK ∨ DR ∨ ER ∨ FER ∨

ORER = 1?

Yes

[3]

[4]

14.3.4 Operation in

Synchronous Mode 619 Description amended

In synchronous mode, the SCIF receives data in

synchronization with the rising edge of the serial clock.

Rev. 2.00, 03/05, page xix of xxxviii

Item Page Revisions (See Manual for Details)

14.5 Usage Notes 640 SCIF Initialization Flowchart and Receive-FIFO-Data-Full

Interrupt (RXI) Requests added

17.1.2 H-UDI Block

Diagram

Figure 17.1 H-UDI Block

Diagram

732 Figure 17.1 am ended

SDSR

SDIDR

SDDRH

SDDRL

Shift register

SDIR

17.1.4 Register

Configuration

Table 17.2 Register

Configuration

733 Table 17.2 amended

Initial Value*

Address

Access Size

(Bits)

Instruction register SDIR R H'E000 H'FFFFFCB0 8/16/32

Status register SDSR R/W H'0401 H'FFFFFCB2 8/16

Data register H SDDRH R/W Undefined H'FFFFFCB4 8/16/32

Data reg

ID code register

ister L S

SDIDR

DDRL R/

—

H'0101000F

ndefined H'FFFFFCB6

—

8/16

—

17.3.2 Status Register

(SDSR) 737 Bit table amended

Bit: 15 14 13 12 11 10 9 8

————————

Initial value 00000100

R/W:RRRRRRRR

17.3.6 ID Code Register

(SDIDR) 750 Description amended

The ID code register (SDIDR) is a 32-bit register. In the

IDCODE mode, SDIDR can output H'0101000F, which is a

fixed code, from TDO.

17.4.1 TAP Controller 751 Description amended

Figure 17.2 shows the internal states of TAP controller. State

transiti ons basically conform with the IEEE1149.1 standard.

Figure 17.2 TAP

Controller State

Transitions

Figure 17.2 amended

Test-logic-reset

Select-DR-scanRun-test/idle

011 1

0Select-IR-scan

Rev. 2.00, 03/05, page xx of xxxviii

Item Page Revisions (See Manual for Details)

17.5.1 Supported

Instructions 756 HIGHZ

Description amended

The instruction code is 0011.

IDCODE

Description amended

The instruction code is 1110.

17.6 Usage Notes 757 Description amended

• The registers are not initialized in standby mode. If TRST is

set to 0 in standby mode, IDCODE mode will be entered.

18.1 Overview

Table 18.1 Multiplex Pins 762 Table 18.1 amended

Function 1 [00]*Function 2 [01]*Function 3 [10]*Function 4 [11]*

Port Signal

Name I/O Related

Module Signal

Name I/O Related

Module Signal

Name I/O Related

Module Signal

Name I/O Related

Module

B PB3 I/O Port STCK1 I SIO1 TIOCA0 I/O TPU0 ———

B PB2 I/O Port STS1 I/O SIO1 TIOCB0 I/O TPU0 ———

B PB1 I/O Port STXD1 O SIO1 TIOCC0 I/O TPU0 ———

B PB0 I/O Port ———TIOCD0 I/O TPU0 WOL O EtherC

21.2 DC Characteristics

Table 21.2 DC

Characteristics

794 Table 21.2 amended

Item Symbol Min Typ Max Unit Test Conditions

Three-state

leakage

current

All I/O and output

pins (off status)

TSI

——1.0µAV

= 0.5 to

– 0.5 V

= 0.5 to

– 0.5 V

Both 3.3 V and 5 V V

– 0.7 —— VI

= –200 µA

Other output pins V

– 0.5 —— VI

= –200 µA

Output high

voltage

– 1.0 —— VI

= –1 mA

Both 3.3 V and 5 V V

——0.6 V I

= 1.6 mAOutput low

voltage Other output pins ——0.4 V I

= 1.6 mA

21.3.1 Clock Timing

Table 21.5 Clock Timing 797 Table 21.5 amended

Item Symbol Min Max Unit Figure

CKPO clock output cycle time tCKPCYC 32 1000 ns 21.4

CKPO clock output low-level pulse width tCKPOL 11 —ns

CKPO clock output high-level pulse width tCKPOH 11 —ns

CKPO clock rise time tCKPOr —5ns

CKPO clock fall time tCKPOf —5ns

Power-on oscillation stabilization time tOSC1 10 —ms 21.5

Standby recovery oscillation stabilization

time 1 tOSC2 10 —ms 21.6

Standby recovery oscillation stabilization

time 2 tOSC3 10 —ms 21.7

PLL synchronization stabilization time tPLL 1 — ms 21.8

Figure 21.3 CKIO Clock

Output Timing 798 Figure 21.3 amended

(Before) VIH → (After) VOH

Figure 21.4 CKPO Clock

Output Timing 799 Figure 21.4 added

Rev. 2.00, 03/05, page xxi of xxxviii

Item Page Revisions (See Manual for Details)

21.3.3 Bus Timing

Table 21.7 PLL-On Bus

Timing [Modes 0 and 4]

(2)

805 Conditions amended

Conditions: VCC = PLLVCC = 3.3 V ± 5%, PVCC = 5.0 V ±

5%/3.3 V ± 5%, PVCC ≥ VCC,

VSS = PVSS = PLLVSS = 0 V, Ta = –5 to +70°C,

SDRAM bus cycle

Figure 21.40 EDO Read

Cycle (TRP = 1 Cycle,

RCD = 1 Cycle, No Wait)

834 Figure 21.40 am ended

CAS ⋅

CKE

OED2

OED1

Rev. 2.00, 03/05, page xxii of xxxviii

Item Page Revisions (See Manual for Details)

21.3.3 Bus Timing

Figure 21.25

Synchronous DRAM Write

Bus Cycle (Bank Active,

Same Row Access,

Except tEcyc:tPcyc 1:1)

Figure 21.27

Synchronous DRAM

Continuous Write Cycle

(Ban k Active, Same Row

Access, Except tEcyc:tPcyc

1:1)

Figure 21.45 Interrupt

Vector Fetch Cycle

(No Wait, Except tEcyc:tPcyc

1:1)

Figure 21.46 Interrupt

Vector Fetch Cycle

(Ex ternal Wait Input,

Except tEcyc:tPcyc 1:1)

Figure 21.50 FRT

Input/Output Timing

(Except tEcyc:tPcyc 1:1)

Figure 21.52 FRT Clock

Input Timing (Except

tEcyc:tPcyc 1:1)

Figure 21.57 TPU

Input/Output Timing

(Except tEcyc:tPcyc 1:1)

Figure 21.60 Watchdo g

Timer Output Timing

(Except tEcyc:tPcyc 1:1)

Figure 21.69 I/O Port

Input/Output Timing

(Except tEcyc:tPcyc 1:1)

Figure 21.70 MII

Transmit Timing (Normal

Operation)

Figure 21.71 MII

Transmit Timing (Case of

Conflict)

819,

821,

839,

840,

843,

846,

847,

852,

854

Figure title am ended

21.3.6 Serial

Communi cation Interface

Timing

Table 21.10 Serial

Communi cation Interface

Timing

844 Table 21.10 amended

(Before) tcscyc → (After) tscyc

Rev. 2.00, 03/05, page xxiii of xxxviii

Item Page Revisions (See Manual for Details)

21.3.8 Serial I/O Timing

Table 21.13 Serial I/O

Timing

848 Table 21.13 amended

Item Symbol Min Max Unit Figure

SRCK, STCK clock input cycle time tsIcyc tPcyc or*

66.7 —ns 21.61

21.3.11 Ethernet

Control ler Tim ing

Table 21.16 Ethernet

Control ler Tim ing

853 Table 21.16 amended

Item Symbol Min Typ Max Unit Figure

TX-CLK cycle time tTcyc 40 ——ns

RX-CLK cycle time tRcyc 40 ——ns 21.71

21.3.12 STATS,

, and

BUSHiZ

Signal Timing

Table 21.17 STATS,

and

BUSHiZ

Signal

Timing

856 Table 21.17 amended

Item Symbol Min Typ Max Unit Figure

STATS1 and STATS0 output delay time t

STATd

——16 ns 21.78

Figure 21.78 STATS

Output Timing

Figure 21.79

Output

Timing

856 Figure 21.78 and Figure 21.79 am ended

(Before) G-DMAC → (After) DMAC

A.1 Addresses 859 SICTR2 amended

Bit Names

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

SIO2

H'FFFFFC24 SICTR2 —

—

———————

H'FFFFFC25 —TM SE DL TIE RIE TE RE

862 SCSMR1 amended

Bit Names

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

H'FFFF FCC0 SCSMR1 C/ACHR/ICK3 PE/ICK2 O/E/ICK1 STOP/

ICK0 MP CKS1 CKS0 SCIF1

864 EESR amended

Bit Names

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

H'FFFF FD14 EESR —————TABT RABT RFCOF E-DMAC

H'FFFF FD15 —ECI TC TDE TFUF FR RDE RFOF

H'FFFF FD16 ———ITF CND DLC CD TRO

H'FFFF FD17 RMAF ——RRF RTLF RTSF PRE CERF

TRSCER amended

Bit Names

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

H'FFFF FD1C TRSCER ————————E-DMAC

H'FFFF FD1D ————————

H'FFFF FD1E ———— — — — —

H'FFFF FD1F RMAFCE ——— — — — —

Rev. 2.00, 03/05, page xxiv of xxxviii

Item Page Revisions (See Manual for Details)

A.1 Addresses 865 EDOCR amended

Bit Names

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

H'FFFF FD30 EDOCR —————— ——E-DMAC

H'FFFF FD31 —————— ——

H'FFFF FD32 —————— ——

H'FFFF FD33 — — — — FEC AEC EDH —

869 Register names amended

H'FFFFFE71 (Before) DCDR0 → (After) DRCR0

H'FFFFFE72 (Before) DCDR1 → (After) DRCR1

872 BBRC amended

Bit Names

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

UBC

H'FFFFFF48 BBRC ——————XYEC XYSC

H'FFFFFF49 CPC1 CPC0 IDC1 IDC0 RWC1 RWC0 SZC1 SZC0

876 MCR amended

Bit Names

Address Register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

H'FFFFFFEC MCR TRP0 RCD0 TRWL0 TRAS1 TRAS0 BE RASD TRWL1 BSC

H'FFFFFFED AMX2 SZ AMX1 AMX0 RFSH RMODE TRP1 RCD1

B.1 Pin States in Reset,

Power-Down State, and

Bus-Released State

880 Table amended

Pin State

Manual Reset Power-Down State

Pin Type Pin Name

Power-

Reset

Bus

Acquired

Bus

Released

Standby

Mode

(HIZ = 0)

Standby

Mode

(HIZ = 1)

Sleep

Mode

Bus-

Released

State

EtherC ETXD3 to ETXD0

ERXD3 to ERXD0 I I I I I I I

OOO OOO O

Appendix C Product

Lineup

Table C.1 SH7615

Product Lineup

881 Table amended

Abbreviation Voltage Operating

Frequency Mark Code Package

HD6417615ARF FP-208C

HD6417615ARFV FP-208CV

HD6417615ARBP BP-240A

SH7615 V

= PLLV

= 3.3 V

= 5.0 V/3.3 V 62.5 MHz

HD6417615ARBPV BP-240AV

Appendi x D Package

Dimensions 882 Description amended

Figure D.1 shows the FP-208C and FP-208CV package

dimensions, and figure D.2 shows the BP-240A and BP-

240AV package dimensions.

Figure D.1 Package

Dimensions (FP-208C,

FP-208CV)

882 Figure D.1 replaced

Figure D.2 Package

Dimensions (BP-240A,

BP-240AV)

883 Figure D.2 added

Rev. 2.00, 03/05, page xxv of xxxviii

Contents

Se ctio n 1 Ove r v iew............................................................................................................. 1

1.1 Features of SuperH Microcomputer with On-Chip Ethernet Controller........................... 1

1.2 Block Diagram.................................................................................................................. 13

1.3 Pin Description ................................................................................................................. 14

1.3.1 Pin Arrangement.................................................................................................. 14

1.3.2 Pin Functions....................................................................................................... 16

1.3.3 Pin Multiplexi ng.................................................................................................. 22

1.4 Processing States .............................................................................................................. 28

Se ctio n 2 CPU...................................................................................................................... 33

2.1 Register Descriptions........................................................................................................33

2.1.1 General Registers................................................................................................. 33

2.1.2 Control Registers................................................................................................. 35

2.1.3 System Registers.................................................................................................. 38

2.1.4 DSP Registers...................................................................................................... 39

2.1.5 Notes on Guard Bits and Overflow Treatment .................................................... 42

2.1.6 Initial Values of Registers ................................................................................... 42

2.2 Data Formats..................................................................................................................... 43

2.2.1 Data Format in Registers ..................................................................................... 43

2.2.2 Data Formats in Memory..................................................................................... 43

2.2.3 Immediate Data Format....................................................................................... 44

2.2.4 DSP Type Data Formats...................................................................................... 44

2.2.5 DSP Type Instructions and Data Formats............................................................ 46

2.3 CPU Core Instruction Features......................................................................................... 50

2.4 Instruction Formats........................................................................................................... 54

2.4.1 CPU Instruction Addressing Modes.................................................................... 54

2.4.2 DSP Data Addressing.......................................................................................... 58

2.4.3 Instruction Formats for CPU Instructions............................................................ 64

2.4.4 Instruction Formats for DSP Instructions............................................................ 67

2.5 Instruction Set................................................................................................................... 73

2.5.1 CPU Instruction Set............................................................................................. 74

2.5.2 DS P Data Trans fer Instruc tion Set....................................................................... 89

2.5.3 DSP Operation Instruction Set............................................................................. 93

2.5.4 Various Operation Instructions............................................................................ 96

2.6 Usage Notes...................................................................................................................... 104

Section 3 Oscillator Circuits and Operating Modes.................................................. 107

3.1 Overview........................................................................................................................... 107

3.2 On-Chip Clock Pulse Generator and Operating Modes.................................................... 107

Rev. 2.00, 03/05, page xxvi of xxxviii

3.2.1 Clock Pulse Generator......................................................................................... 107

3.2.2 Clock Operating Mode Settings........................................................................... 109

3.2.3 Connecting a Crystal Resonator .......................................................................... 112

3.2.4 External Clock Input............................................................................................ 113

3.2.5 Operating Frequency Selection by Register......................................................... 114

3.2.6 Clock Modes and Frequency Ranges................................................................... 122

3.2.7 Notes on Board Design........................................................................................ 123

3.3 Bus Width of the CS0 Area .............................................................................................. 124

Section 4 Exception Handling......................................................................................... 125

4.1 Overview........................................................................................................................... 125

4.1.1 Types of Exception Handling and Priority Order................................................ 125

4.1.2 Exception Handling Operations........................................................................... 127

4.1.3 Exception Vector Table....................................................................................... 128

4.2 Resets................................................................................................................................ 131

4.2.1 Types of Resets.................................................................................................... 131

4.2.2 Power-On Reset................................................................................................... 131

4.2.3 Manual Reset....................................................................................................... 132

4.3 Address Errors.................................................................................................................. 132

4.3.1 Sources of Address Errors................................................................................... 132

4.3.2 Address Error Exception Handling...................................................................... 134

4.4 Interrupts........................................................................................................................... 135

4.4.1 Interrupt Sources.................................................................................................. 135

4.4.2 Interrupt Priori ty Lev el s....................................................................................... 136

4.4.3 Interrupt Exception Handling .............................................................................. 136

4.5 Exceptions Triggered by Instructions ............................................................................... 137

4.5.1 Instruction-Triggered Exception Types............................................................... 137

4.5.2 Trap Instructions.................................................................................................. 137

4.5.3 Illegal Slot Instructions........................................................................................ 138

4.5.4 General Illegal Instructions.................................................................................. 138

4.6 When Exception Sources Are Not Accepted.................................................................... 139

4.6.1 Immediately after a Delayed Branch Instruction................................................. 139

4.6.2 Immediately after an Interrupt-Disabled Instruction............................................ 139

4.6.3 Instructions in Repeat Loops ............................................................................... 140

4.7 Stack Status after Exception Handling.............................................................................. 141

4.8 Usage Notes...................................................................................................................... 142

4.8.1 Value of Stack Pointer (SP)................................................................................. 142

4.8.2 Value of Vector Base Register (VBR)................................................................. 142

4.8.3 Address Errors Caused by Stacking of Address Error Exception Handling........ 142

4.8.4 Manual Reset during Register Access ................................................................. 142

Se ctio n 5 I nterrupt Control le r (I NTC)........................................................................... 143

5.1 Overview........................................................................................................................... 143

Rev. 2.00, 03/05, page xxvii of xxxviii

5.1.1 Features................................................................................................................ 143

5.1.2 Block Diagram..................................................................................................... 144

5.1.3 Input/Outpu t Pins................................................................................................. 145

5.1.4 Register Configuration......................................................................................... 145

5.2 Interrupt Sources............................................................................................................... 146

5.2.1 NMI Interrupt ...................................................................................................... 147

5.2.2 User Break Interrupt............................................................................................ 147

5.2.3 H-UDI Interrupt................................................................................................... 147

5.2.4 IRL Interrupts...................................................................................................... 147

5.2.5 IRQ Interrupts...................................................................................................... 148

5.2.6 On-chi p Peripheral Module In terrup ts................................................................. 152

5.2.7 Interrupt Exception Vectors and Priority Order................................................... 152

5.3 Register Descriptions........................................................................................................ 159

5.3.1 Interrupt Priority Level Setting Register A (IPRA)............................................. 159

5.3.2 Interrupt Priority Level Setting Register B (IPRB) ............................................. 160

5.3.3 Interrupt Priority Level Setting Register C (IPRC) ............................................. 161

5.3.4 Interrupt Priority Level Setting Register D (IPRD)............................................. 162

5.3.5 Interrupt Priority Level Setting Register E (IPRE).............................................. 163

5.3.6 Vector Number Setting Register WDT (VCRWDT)........................................... 164

5.3.7 Vector Number Setting Register A (VCRA) ....................................................... 165

5.3.8 Vector Number Setting Register B (VCRB)........................................................ 165

5.3.9 Vector Number Setting Register C (VCRC)........................................................ 166

5.3.10 Vector Number Setting Register D (VCRD) ....................................................... 167

5.3.11 Vector Number Setting Register E (VCRE) ........................................................ 168

5.3.12 Vector Number Setting Register F (VCRF)......................................................... 169

5.3.13 Vector Number Setting Register G (VCRG) ....................................................... 170

5.3.14 Vector Number Setting Register H (VCRH) ....................................................... 171

5.3.15 Vector Number Setting Register I (VCRI) .......................................................... 172

5.3.16 Vector Number Setting Register J (VCRJ).......................................................... 173

5.3.17 Vector Number Setting Register K (VCRK) ....................................................... 174

5.3.18 Vector Number Setting Register L (VCRL) ........................................................ 175

5.3.19 Vector Number Setting Register M (VCRM)...................................................... 176

5.3.20 Vector Number Setting Register N (VCRN) ....................................................... 177

5.3.21 Vector Number Setting Register O (VCRO) ....................................................... 178

5.3.22 Vector Number Setting Register P (VCRP)......................................................... 179

5.3.23 Vector Number Setting Register Q (VCRQ) ....................................................... 180

5.3.24 Vector Number Setting Register R (VCRR)........................................................ 181

5.3.25 Vector Number Setting Register S (VCRS)......................................................... 182

5.3.26 Vector Number Setting Register T (VCRT) ........................................................ 183

5.3.27 Vector Number Setting Register U (VCRU) ....................................................... 184

5.3.28 Interrupt Control Register (ICR).......................................................................... 187

5.3.29 IRQ Control/Status Register (IRQCSR).............................................................. 188

5.4 Interrupt Operation ........................................................................................................... 191

Rev. 2.00, 03/05, page xxviii of xxxviii

5.4.1 Interrupt Sequence............................................................................................... 191

5.4.2 Stack State after Interrupt Exception Handling ................................................... 193

5.5 Interrupt Response Time................................................................................................... 193

5.6 Sampling of Pins

IRL3

IRL0

........................................................................................ 195

5.7 Usage Notes...................................................................................................................... 196

Section 6 User Break Controller (UBC)....................................................................... 201

6.1 Overview........................................................................................................................... 201

6.1.1 Features................................................................................................................ 201

6.1.2 Block Diagram..................................................................................................... 202

6.1.3 Register Configuration......................................................................................... 203

6.2 Register Descriptions........................................................................................................ 205

6.2.1 Break Address Register A (BARA)..................................................................... 205

6.2.2 Break Address Mask Register A (BAMRA)........................................................ 206

6.2.3 Break Bus Cycle Register A (BBRA).................................................................. 207

6.2.4 Break Address Register B (BARB) ..................................................................... 209

6.2.5 Break Address Mask Register B (BAMRB)........................................................ 210

6.2.6 Break Bus Cycle Register B (BBRB).................................................................. 211

6.2.7 Break Address Register C (BARC) ..................................................................... 213

6.2.8 Break Address Mask Register C (BAMRC)........................................................ 214

6.2.9 Break Data Register C (BDRC)........................................................................... 216

6.2.10 Break Data Mask Register C (BDMRC) ............................................................. 217

6.2.11 Break Bus Cycle Register C (BBRC).................................................................. 219

6.2.12 Break Execution Times Register C (BETRC) ..................................................... 220

6.2.13 Break Address Register D (BARD)..................................................................... 221

6.2.14 Break Address Mask Register D (BAMRD)........................................................ 222

6.2.15 Break Data Register D (BDRD).......................................................................... 224

6.2.16 Break Data Mask Register D (BDMRD)............................................................. 225

6.2.17 Break Bus Cycle Register D (BBRD).................................................................. 227

6.2.18 Break Execution Times Register D (BETRD)..................................................... 228

6.2.19 Break Control Register (BRCR).......................................................................... 229

6.2.20 Branch Flag Registers (BRFR)............................................................................ 234

6.2.21 Branch Source Registers (BRSR)........................................................................ 235

6.2.22 Branch Destination Registers (BRDR)................................................................ 236

6.3 Operation.......................................................................................................................... 237

6.3.1 User Break Operation Sequence.......................................................................... 237

6.3.2 Instruction Fetch Cycle Break............................................................................. 238

6.3.3 Data Access Cycle Break..................................................................................... 239

6.3.4 Saved Program Counter (PC) Value.................................................................... 240

6.3.5 X Memory Bus or Y Memory Bus Cycle Break.................................................. 240

6.3.6 Sequential Break.................................................................................................. 241

6.3.7 PC Traces............................................................................................................. 242

6.3.8 Examples of Use.................................................................................................. 244

Rev. 2.00, 03/05, page xxix of xxxviii

6.3.9 Usage Notes......................................................................................................... 249

Section 7 Bus State Controller (BSC)........................................................................... 251

7.1 Overview........................................................................................................................... 251

7.1.1 Features................................................................................................................ 251

7.1.2 Block Diagram..................................................................................................... 253

7.1.3 Input/Outpu t Pins................................................................................................. 254

7.1.4 Register Configuration......................................................................................... 256

7.1.5 A ddress Map........................................................................................................ 257

7.2 Register Descriptions........................................................................................................ 259

7.2.1 Bus Control Register 1 (BCR1)........................................................................... 259

7.2.2 Bus Control Register 2 (BCR2)........................................................................... 262

7.2.3 Bus Control Register 3 (BCR3)........................................................................... 263

7.2.4 Wait Control Register 1 (WCR1) ........................................................................ 265

7.2.5 Wait Control Register 2 (WCR2) ........................................................................ 267

7.2.6 Wait Control Register 3 (WCR3) ........................................................................ 269

7.2.7 Individual Memory Control Register (MCR) ...................................................... 270

7.2.8 Refresh Timer Control/Status Register (RTCSR)................................................ 276

7.2.9 Refresh Timer Counter (RTCNT)........................................................................ 277

7.2.10 Refresh Time Constant Register (RTCOR) ......................................................... 278

7.3 Access Size and Data Alignment...................................................................................... 279

7.3.1 Connection to Ordinary Devices.......................................................................... 279

7.3.2 Connection to Little-Endian Devices................................................................... 280

7.4 Accessing Ordinary Space................................................................................................ 282

7.4.1 Basic Timing........................................................................................................ 282

7.4.2 Wait State Control............................................................................................... 287

7.4.3

Assertion Period Extensi on............................................................................ 291

7.5 Synchronous DRAM Interface ......................................................................................... 292

7.5.1 Synchronous DRAM Direct Connection............................................................. 292

7.5.2 A ddress Multipl exing.......................................................................................... 294

7.5.3 Burst Reads.......................................................................................................... 296

7.5.4 Single Reads........................................................................................................ 301

7.5.5 Single Writes ....................................................................................................... 303

7.5.6 Burst Write Mode................................................................................................ 304

7.5.7 Bank Active Function.......................................................................................... 307

7.5.8 Refreshes ............................................................................................................. 317

7.5.9 Overlap Between Auto Precharge Cycle (Tap) and Next Access........................ 320

7.5.10 Power-On Sequence............................................................................................. 321

7.5.11 64-Mbit Synchronous DRAM (2 Mwords × 32 Bits) Connection....................... 323

7.6 DRAM Interface............................................................................................................... 327

7.6.1 DRAM Direct Connection................................................................................... 327

7.6.2 A ddress Multipl exing.......................................................................................... 328

7.6.3 Basic Timing........................................................................................................ 329

Rev. 2.00, 03/05, page xxx of xxxviii

7.6.4 Wait State Control............................................................................................... 330

7.6.5 Burst Access........................................................................................................ 332

7.6.6 EDO Mode........................................................................................................... 335

7.6.7 DRAM Single Transfer........................................................................................ 339

7.6.8 Refreshing............................................................................................................ 340

7.6.9 Power-On Sequence............................................................................................. 342

7.7 Burst ROM Interface ........................................................................................................ 342

7.8 Idles between Cycles ........................................................................................................ 346

7.9 Bus Arbitration ................................................................................................................. 348

7.9.1 Master Mode........................................................................................................ 352

7.10 Additional Items ............................................................................................................... 353

7.10.1 Resets................................................................................................................... 353

7.10.2 Access as Viewed from CPU, DMAC or E-DMAC............................................ 353

7.10.3 STATS1 and STATS0 Pins ................................................................................. 355

7.10.4

BUSHiZ

Specification......................................................................................... 355

7.11 Usage Notes...................................................................................................................... 356

7.11.1 Normal Space Access after Synchronous DRAM Write when Using DMAC .... 356

7.11.2 When Using Iφ:Eφ Clock Ratio of 1:1, 8-Bit Bus Width,

and External Wait Input....................................................................................... 358

7.11.3 Preventing Wrong Data Output to Synchronous DRAM..................................... 358

Se ctio n 8 Cache.................................................................................................................... 359

8.1 Introduction ...................................................................................................................... 359

8.1.1 Register Configuration......................................................................................... 360

8.2 Register Description ......................................................................................................... 360

8.2.1 Cache Control Register (CCR) ............................................................................ 360

8.3 Address Space and the Cache........................................................................................... 362

8.4 Cache Operation ............................................................................................................... 363

8.4.1 Cache Reads ........................................................................................................ 363

8.4.2 Write Access........................................................................................................ 365

8.4.3 Cache-Through Access........................................................................................ 368

8.4.4 The TAS Instruction............................................................................................ 368

8.4.5 Pseudo-LRU and Cache Replacement................................................................. 368

8.4.6 Cache Initiali zatio n.............................................................................................. 370

8.4.7 Associative Purges............................................................................................... 370

8.4.8 Cache Flushing.................................................................................................... 371

8.4.9 Data Array Access............................................................................................... 371

8.4.10 Address Array Access.......................................................................................... 372

8.5 Cache Use......................................................................................................................... 373

8.5.1 Initialization......................................................................................................... 373

8.5.2 Purge of Specific Lines........................................................................................ 374

8.5.3 Cache Data Coherency......................................................................................... 374

8.5.4 Two-Way Cache Mode........................................................................................ 375

Rev. 2.00, 03/05, page xxxi of xxxviii

8.6 Usage Notes...................................................................................................................... 376

8.6.1 Standby................................................................................................................ 376

8.6.2 Cache Control Register........................................................................................ 376

Section 9 Ethernet Controller (EtherC)......................................................................... 377

9.1 Overview........................................................................................................................... 377

9.1.1 Features................................................................................................................ 377

9.1.2 Configuration....................................................................................................... 378

9.1.3 Input/Outpu t Pins................................................................................................. 380

9.1.4 Ethernet Controller Register Configuration......................................................... 381

9.2 Register Descriptions........................................................................................................ 382

9.2.1 EtherC Mode Register (ECMR) .......................................................................... 382

9.2.2 EtherC Status Register (ECSR) ........................................................................... 385

9.2.3 EtherC Interrupt Permission Register (ECSIPR)................................................. 386

9.2.4 PHY Interface Register (PIR).............................................................................. 387

9.2.5 MAC Address High Register (MAHR) ............................................................... 388

9.2.6 MAC Address Low Register (MALR)................................................................. 389

9.2.7 Receive Frame Length Register (RFLR)............................................................. 390

9.2.8 PHY Interface Status Register (PSR) .................................................................. 391

9.2.9 Transmit Retry Over Counter Register (TROCR)............................................... 392

9.2.10 Collision Detect Counter Register (CDCR)......................................................... 393

9.2.11 Lost Carrier Counter Register (LCCR)................................................................ 394

9.2.12 Carrier Not Detect Counter Register (CNDCR).................................................. 395

9.2.13 Illegal Frame Length Counter Register (IFLCR)................................................. 396

9.2.14 CRC Error Frame Counter Register (CEFCR) .................................................... 397

9.2.15 Frame Receive Error Counter Register (FRECR )............................................... 398

9.2.16 Too-Short Frame Receive Counter Register (TSFRCR) ..................................... 399

9.2.17 Too-Long Frame Receive Counter Register (TLFRCR ) .................................... 400

9.2.18 Residual-Bit Frame Counter Register (RFCR).................................................... 401

9.2.19 Multicast Address Frame Counter Register (MAFCR) ....................................... 402

9.3 Operation.......................................................................................................................... 403

9.3.1 Transmission........................................................................................................ 403

9.3.2 Reception............................................................................................................. 405

9.3.3 MII Frame Timing............................................................................................... 407

9.3.4 Accessing MII Registers...................................................................................... 409

9.3.5 Magic Packet Detection....................................................................................... 412

9.3.6 CPU Operating Mode and Ethernet Controller Operation................................... 413

9.4 Connection to PHY-LSI.................................................................................................... 414

9.5 Usage Notes...................................................................................................................... 416

Section 10 Eth ernet Controller Di rect Memory Access Con troller

(E-DMAC)....................................................................................................... 417

10.1 Overview........................................................................................................................... 417

Rev. 2.00, 03/05, page xxxii of xxxviii

10.1.1 Features................................................................................................................ 417

10.1.2 Configuration....................................................................................................... 418

10.1.3 Descriptor Management System.......................................................................... 419

10.1.4 Register Configuration......................................................................................... 419

10.2 Register Descriptions........................................................................................................ 421

10.2.1 E-DMAC Mode Register (EDMR)...................................................................... 421

10.2.2 E-DMAC Transmit Request Register (EDTRR) ................................................. 422

10.2.3 E-DMAC Receive Request Register (EDRRR)................................................... 423

10.2.4 Transmit Descriptor List Address Register (TDLAR)......................................... 424

10.2.5 Receive Descriptor List Address Register (RDLAR).......................................... 425

10.2.6 EtherC/E-DMAC Status Register (EESR)........................................................... 426

10.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)...................... 432

10.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................ 437

10.2.9 Receive Missed-Frame Counter Register (RMFCR)........................................... 438

10.2.10 Transmit FIFO Threshold Register (TFTR) ........................................................ 439

10.2.11 FIFO Depth Register (FDR)................................................................................ 440

10.2.12 Receiver Control Register (RCR)........................................................................ 443

10.2.13 E-DMAC Operation Control Register (EDOCR)................................................ 444

10.2.14 Receiving-Buffer Write Address Register (RBWAR)......................................... 445

10.2.15 Receiving-Descriptor Fetch Address Register (RDFAR).................................... 446

10.2.16 Transmission-Buffer Read Address Register (TBRAR)...................................... 447

10.2.17 Transmission-Descriptor Fetch Address Register (TDFAR)............................... 448

10.3 Operation.......................................................................................................................... 449

10.3.1 Descriptor List and Data Buffers......................................................................... 449

10.3.2 Transmission........................................................................................................ 455

10.3.3 Reception............................................................................................................. 457

10.3.4 Multi- Buffer Fram e Transm i t/Recei v e Processi ng.............................................. 459

10.4 Usage Notes...................................................................................................................... 461

10.4.1 E-DMAC Transmit Request Register (EDTRR) and E-DMAC Receive

Request Register (EDRRR) Usage Notes............................................................ 461

Section 11 Direct Memory Access Con troller (DMAC).......................................... 463

11.1 Overview........................................................................................................................... 463

11.1.1 Features................................................................................................................ 463

11.1.2 Block Diagram..................................................................................................... 465

11.1.3 Input/Outpu t Pins................................................................................................. 466

11.1.4 Register Configuration......................................................................................... 467

11.2 Register Descriptions........................................................................................................ 468

11.2.1 DMA Source Address Registers 0 and 1 (SAR0, SAR1) .................................... 468

11.2.2 DMA Destination Address Registers 0 and 1 (DAR0, DAR1)............................ 468

11.2.3 DMA Transfer Count Registers 0 and 1 (TCR0, TCR1)..................................... 469

11.2.4 DMA Channel Control Registers 0 and 1 (CHCR0, CHCR1)............................. 470

11.2.5 DMA Vector Number Registers 0 and 1 (VCRDMA0, VCRDMA1) ................. 474

Rev. 2.00, 03/05, page xxxiii of xxxviii

11.2.6 DMA Request/Response Selection Control Registers 0 and 1

(DRCR0, DRCR1)............................................................................................... 475

11.2.7 DMA Operation Register (DMAOR) .................................................................. 477

11.3 Operation.......................................................................................................................... 479

11.3.1 DMA Transfer Flow............................................................................................ 479

11.3.2 DMA Transfer Requests...................................................................................... 481

11.3.3 Channel Prioriti es................................................................................................ 485

11.3.4 DMA Transfer Types........................................................................................... 488

11.3.5 Number of Bus Cycles......................................................................................... 498

11.3.6 DMA Transfer Request Acknowledge Signal Output Timing............................. 498

11.3.7 DREQn Pin Input Detection Timing.................................................................... 509

11.3.8 DMA Transfer End.............................................................................................. 515

11.3.9

Pin Output Timing......................................................................................... 516

11.4 Usage Examples................................................................................................................ 517

11.4.1 Example of DMA Data Transfer Between On-chip SCIF and External Memory 517

11.5 Usage Notes...................................................................................................................... 518

Section 12 16-Bit Free-Running Timer (FRT)........................................................... 525

12.1 Overview........................................................................................................................... 525

12.1.1 Features................................................................................................................ 525

12.1.2 Block Diagram..................................................................................................... 526

12.1.3 Input/Outpu t Pins................................................................................................. 527

12.1.4 Register Configuration......................................................................................... 527

12.2 Register Descriptions........................................................................................................ 528

12.2.1 Free-Running Counter (FRC).............................................................................. 528

12.2.2 Output Compare Registers A and B (OCRA and OCRB) ................................... 528

12.2.3 Input Capture Register (FICR) ............................................................................ 529

12.2.4 Timer Interrupt Enable Register (TIER).............................................................. 529

12.2.5 Free-Running Timer Control/Status Register (FTCSR) ...................................... 530

12.2.6 Timer Control Register (TCR)............................................................................. 532

12.2.7 Timer Output Compare Control Register (TOCR).............................................. 533

12.3 CPU Interface................................................................................................................... 534

12.4 Operation.......................................................................................................................... 537

12.4.1 FRC Count Timing .............................................................................................. 537

12.4.2 Output Timing for Output Compare.................................................................... 538

12.4.3 FRC Clear Timing ............................................................................................... 538

12.4.4 Input Capture Inpu t Timing................................................................................. 539

12.4.5 Input Capture Flag (ICF) Setting Timing ............................................................ 540

12.4.6 Output Compare Flag (OCFA, OCFB) Setting Timing....................................... 540

12.4.7 Timer Overflow Flag (OVF) Setting Timing....................................................... 541

12.5 Interrupt Sources............................................................................................................... 542

12.6 Example of FRT Use........................................................................................................ 542

12.7 Usage Notes...................................................................................................................... 543

Rev. 2.00, 03/05, page xxxiv o f xxxviii

12.7.1 Contention between FRC Write and Clear .......................................................... 543

12.7.2 Contention between FRC Write and Increment................................................... 544

12.7.3 Contention between OCR Write and Compare Match......................................... 545

12.7.4 Internal Clock Switching and Counter Operation................................................ 545

12.7.5 Timer Output (FTOA, FTOB) ............................................................................. 547

Section 13 Watchdog Timer (WDT).............................................................................. 549

13.1 Overview........................................................................................................................... 549

13.1.1 Features................................................................................................................ 549

13.1.2 Block Diagram..................................................................................................... 550

13.1.3 Input/Outpu t Pin.................................................................................................. 550

13.1.4 Register Configuration......................................................................................... 551

13.2 Register Descriptions........................................................................................................ 551

13.2.1 Watchdog Timer Counter (WTCNT)................................................................... 551

13.2.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 552

13.2.3 Reset Control/Status Register (RSTCSR)............................................................ 553

13.2.4 Notes on Register Access .................................................................................... 554

13.3 Operation.......................................................................................................................... 556

13.3.1 Operation in Watchdog Timer Mode................................................................... 556

13.3.2 Operation in Interval Timer Mode....................................................................... 558

13.3.3 Operation when Standby Mode is Cleared .......................................................... 558

13.3.4 Timing of Overflow Flag (OVF) Setting............................................................. 559

13.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting ............................. 559

13.4 Usage Notes...................................................................................................................... 560

13.4.1 Contention between WTCNT Write and Increment ............................................ 560

13.4.2 Changing CKS2 to CKS0 Bit Values .................................................................. 560

13.4.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 560

13.4.4 System Reset with

WDTOVF

.............................................................................. 561

13.4.5 Internal Reset in Watchdog Timer Mode............................................................. 561

13.4.6 Internal Reset by Watchdog Timer (WDT) in Sleep Mode................................. 561

Section 14 Serial Communication Interface with FIFO (SCIF)............................ 563

14.1 Overview........................................................................................................................... 563

14.1.1 Features................................................................................................................ 563

14.1.2 Block Diagrams................................................................................................... 565

14.1.3 Input/Outpu t Pins................................................................................................. 566

14.1.4 Register Configuration......................................................................................... 567

14.2 Register Descriptions........................................................................................................ 568

14.2.1 Receive Shift Register (SCRSR) ......................................................................... 568

14.2.2 Receive FIFO Data Register (SCFRDR) ............................................................. 568

14.2.3 Transmit Shift Register (SCTSR)........................................................................ 569

14.2.4 Transmit FIFO Data Register (SCFTDR)............................................................ 569

14.2.5 Serial Mode Register (SCSMR)........................................................................... 570

Rev. 2.00, 03/05, page xxxv of xxxviii

14.2.6 Serial Control Register (SCSCR)......................................................................... 573

14.2.7 Serial Status 1 Register (SC1SSR) ...................................................................... 577

14.2.8 Serial Status 2 Register (SC2SSR) ...................................................................... 582

14.2.9 Bit Rate Register (SCBRR) ................................................................................. 584

14.2.10 FIFO Control Register (SCFCR) ......................................................................... 592

14.2.11 FIFO Data Count Register (SCFDR)................................................................... 594

14.2.12 FIFO Error Register (SCFER)............................................................................. 595

14.2.13 IrDA Mode Register (SCIMR) ............................................................................ 595

14.3 Operation.......................................................................................................................... 597

14.3.1 Overview.............................................................................................................. 597

14.3.2 Operation in Asynchronous Mode....................................................................... 600

14.3.3 Multiprocessor Communication Function........................................................... 611

14.3.4 Operation in Synchronous Mode......................................................................... 619

14.3.5 Use of Transmit/Receive FIFO Buffers............................................................... 629

14.3.6 Operation in IrDA Mode ..................................................................................... 632

14.4 SCIF Interrupt Sources and the DMAC............................................................................ 635

14.5 Usage Notes...................................................................................................................... 636

Secti on 15 Serial I/O (SIO) .............................................................................................. 643

15.1 Overview........................................................................................................................... 643

15.1.1 Features................................................................................................................ 643

15.2 Register Configuration...................................................................................................... 646

15.2.1 Receive Shift Register (SIRSR)........................................................................... 647

15.2.2 Receive Data Register (SIRDR) .......................................................................... 647

15.2.3 Transmit Shift Register (SITSR) ......................................................................... 648

15.2.4 Transmit Data Register (SITDR)......................................................................... 648

15.2.5 Serial Control Register (SICTR).......................................................................... 649

15.2.6 Serial Status Register (SISTR) ............................................................................ 651

15.3 Operation.......................................................................................................................... 653

15.3.1 Input..................................................................................................................... 653

15.3.2 Output.................................................................................................................. 654

15.4 SIO Interrupt Sources and DMAC.................................................................................... 657

Section 16 16-Bit Timer Pulse Un it (TPU).................................................................. 659

16.1 Overview........................................................................................................................... 659

16.1.1 Features................................................................................................................ 659

16.1.2 Block Diagram..................................................................................................... 662

16.1.3 Input/Outpu t Pins................................................................................................. 663

16.1.4 Register Configuration......................................................................................... 664

16.2 Register Descriptions........................................................................................................ 665

16.2.1 Timer Control Register (TCR)............................................................................. 665

16.2.2 Timer Mode Register (TMDR)............................................................................ 669

16.2.3 Timer I/O Control Register (TIOR)..................................................................... 671

Rev. 2.00, 03/05, page xxxvi o f xxxviii

16.2.4 Timer Interrupt Enable Register (TIER).............................................................. 678

16.2.5 Timer Status Register (TSR)................................................................................ 680

16.2.6 Timer Counter (TCNT)........................................................................................ 683

16.2.7 Timer General Register (TGR)............................................................................ 684

16.2.8 Timer Start Register (TSTR)............................................................................... 684

16.2.9 Timer Synchro Register (TSYR)......................................................................... 685

16.3 Interface to Bus Master..................................................................................................... 686

16.3.1 16-Bit Registers................................................................................................... 686

16.3.2 8-Bit Registers..................................................................................................... 686

16.4 Operation.......................................................................................................................... 688

16.4.1 Overview.............................................................................................................. 688

16.4.2 Basic Functions.................................................................................................... 689

16.4.3 Synchronous Operation ....................................................................................... 695

16.4.4 Buffer Operation.................................................................................................. 697

16.4.5 PWM Modes........................................................................................................ 701

16.4.6 Phase Counting Mode.......................................................................................... 706

16.5 Interrupts........................................................................................................................... 711

16.5.1 Interrupt Sources and Priorities........................................................................... 711

16.5.2 DMAC Activat ion ............................................................................................... 712

16.6 Operation Timing.............................................................................................................. 713

16.6.1 Input/Outpu t Timing............................................................................................ 713

16.6.2 Interrupt Signal Timing ....................................................................................... 717

16.7 Usage Notes...................................................................................................................... 720

16.8 Usage Notes...................................................................................................................... 730

16.8.1 Clearing Flags in TSR0 to TSR2......................................................................... 730

16.8.2 DMA Transfer by TPU0...................................................................................... 730

Section 17 High-Performance User Debugging Interface (H-UD I)..................... 731

17.1 Overview........................................................................................................................... 731

17.1.1 Features................................................................................................................ 731

17.1.2 H-UDI Block Diagram......................................................................................... 732

17.1.3 Input/Outpu t Pins................................................................................................. 733

17.1.4 Register Configuration......................................................................................... 733

17.2 External Signals................................................................................................................ 734

17.2.1 Test Clock (TCK)................................................................................................ 734

17.2.2 Test Mode Select ( TMS )...................................................................................... 734

17.2.3 Test Data Input (TDI).......................................................................................... 734

17.2.4 Test Data Output (TDO)...................................................................................... 734

17.2.5 Test Reset (

TRST

)............................................................................................... 735

17.3 Register Descriptions........................................................................................................ 735

17.3.1 Instruction Register (SDIR)................................................................................. 735

17.3.2 Status Register (SDSR)........................................................................................ 737

17.3.3 Data Register (SDDR)......................................................................................... 738

Rev. 2.00, 03/05, page xxxvii of xxxviii

17.3.4 Bypass Register (SDBPR)................................................................................... 738

17.3.5 Boundary Scan Register (SDBSR) ...................................................................... 738

17.3.6 ID Code Register (SDIDR).................................................................................. 750

17.4 Operation.......................................................................................................................... 751

17.4.1 TAP Controller.................................................................................................... 751

17.4.2 H-UDI Interrupt and Serial Transfer.................................................................... 752

17.4.3 H-UDI Reset........................................................................................................ 755

17.5 Boundary Scan.................................................................................................................. 755

17.5.1 Supported Instructions......................................................................................... 755

17.5.2 Notes on Use........................................................................................................ 756

17.6 Usage Notes...................................................................................................................... 757

Section 18 Pin Function Controller (P FC)................................................................... 761

18.1 Overview........................................................................................................................... 761

18.2 Register Configuration...................................................................................................... 763

18.3 Register Descriptions........................................................................................................ 763

18.3.1 Port A Control Register (PACR) ......................................................................... 763

18.3.2 Port A I/O Register (PAIOR)............................................................................... 766

18.3.3 Port B Control Registers (PBCR, PBCR2).......................................................... 767

18.3.4 Port B I/O Register (PBIOR)............................................................................... 772

Section 19 I/O Ports............................................................................................................ 773

19.1 Overview........................................................................................................................... 773

19.2 Port A................................................................................................................................ 773

19.2.1 Register Configuration......................................................................................... 774

19.2.2 Port A Data Register (PADR).............................................................................. 774

19.3 Port B................................................................................................................................ 775

19.3.1 Register Configuration......................................................................................... 776

19.3.2 Port B Data Register (PBDR).............................................................................. 776

Section 20 Power-Down Modes...................................................................................... 779

20.1 Overview........................................................................................................................... 779

20.1.1 Power-Down Modes............................................................................................ 779

20.1.2 Register................................................................................................................ 780

20.2 Register Descriptions........................................................................................................ 781

20.2.1 Standby Control Register 1 (SBYCR1)............................................................... 781

20.2.2 Standby Control Register 2 (SBYCR2)............................................................... 783

20.3 Sleep Mode....................................................................................................................... 785

20.3.1 Transition to Sleep Mode..................................................................................... 785

20.3.2 Canceling Sleep Mode......................................................................................... 785

20.4 Standby Mode................................................................................................................... 785

20.4.1 Transition to Standby Mode ................................................................................ 785

20.4.2 Canceling Standby Mode..................................................................................... 787

Rev. 2.00, 03/05, page xxxviii of xxxviii

20.4.3 Standby Mode Cancellation by NMI Interrupt.................................................... 787

20.4.4 Clock Pause Function.......................................................................................... 788

20.4.5 Notes on Standby Mode....................................................................................... 790

20.5 Module Standby Function................................................................................................. 791

20.5.1 Transition to Module Standby Function.............................................................. 791

20.5.2 Clearing the Module Standby Function............................................................... 791

Section 21 Electrical Characteristics............................................................................. 793

21.1 Absolute Maximum Ratings............................................................................................. 793

21.2 DC Characteristics............................................................................................................ 794

21.3 AC Characteristics............................................................................................................ 796

21.3.1 Clock Timing....................................................................................................... 797

21.3.2 Control Signal Timing......................................................................................... 801

21.3.3 Bus Timing .......................................................................................................... 803

21.3.4 Direct Memory Access Controller Timing .......................................................... 841

21.3.5 Free-Running Timer Timing................................................................................ 842

21.3.6 Serial Communication Interface Timing.............................................................. 844

21.3.7 Watchdog Timer Timing ..................................................................................... 847

21.3.8 Serial I/O Timing................................................................................................. 848

21.3.9 High-Performance User Debugging Interface Timing......................................... 850

21.3.10 I/O Port Timing.................................................................................................... 851

21.3.11 Ethernet Controller Timing.................................................................................. 853

21.3.12 STATS,

, and

BUSHiZ

Signal Timing........................................................... 856

21.4 AC Characteristic Test Conditions ................................................................................... 858

Appendix A On-Ch ip Peripheral Module Registers.................................................. 859

A.1 Addresses.......................................................................................................................... 859

A ppendix B Pin S ta tes....................................................................................................... 877

B.1 Pin States in Reset, Power-Down State, and Bus-Released State..................................... 877

A ppendix C Product L i ne up............................................................................................. 881

Appendix D Package Dimensions.................................................................................. 882

Rev. 2.00, 03/05, page 1 of 884

Section 1 O verview

1.1 F eatures of Super H Microcomputer with On-Chip Ethernet

Controller

The SH7615 is a CMOS single-chip microcomputer that integrates a high-speed CPU core using

an original Renesas Technology architecture with supporting functions required for an Ethernet

system.

The CPU has a RISC (Reduced Instruction Set Computer) type instruction set. The CPU basically

operates at a rate of one instruction per cycle, offering a great improvement in instruction

execution speed. In addition, the 32-bit internal architecture provides improved data processing

power, and DSP functions have also been enhanced with the implementation of extended Harvard

architecture DSP data bus functions. With this CPU, it has become possible to assemble low-cost,

high-performance/high-functionality systems even for applications such as realtime control, which

could not previously be handled by microcomputers because of their high-speed processing

requirements. The SH7615 also includes a maximum 4-kbyte cache, for greater CPU processing

power when accessing external memory.

The SH7615 is equipped with a media access controller (MAC) conforming to the IEEE802.3u

standard, and an Ethernet controller that includes a media independent interface (MII) standard

unit, enabling 10/100 Mbps LAN connection. Supporting functions necessary for system

configuration are also provided, including RAM, timers, a serial communication interface with

FIFO (SCIF), interrupt controller (INTC), and I/O ports.

Rev. 2.00, 03/05, page 2 of 884

Table 1.1 Features

Item Specifications

CPU • Original Renesas Technology architecture

• 32-bit internal architecture

• General register machine

 Sixteen 32-bit general registers

 Six 32-bit control registers (including 3 added for DSP use)

 Ten 32-bit system registers

• RISC (Reduced Instruction Set Computer) type instruction set

 Fixed 16-bit instruction length for improved code efficiency

 Load-store architecture (basic operations are executed between

registers)

 Delayed branch instruct ions reduce pipeline disrupt ion during

branches

 C-oriented instruction set

• Instruction execution time: One instruction per cycle (16.0 ns/instruction at

62.5 MHz operation)

• Address space: Architecture supports 4 Gbytes

• On-chip mu ltiplier: Multiply operations (32 bits × 32 bits → 64 bits) and

multiply-and-accumulate operations (32 bits × 32 bits + 64 bits → 64 bits)

executed in two to four cycles

• Five-stage pipeline

Rev. 2.00, 03/05, page 3 of 884

Item Specifications

DSP • DSP engine

 Multiplier

 Arithmetic logic unit (ALU)

 Shifter

 DSP registers

• Multiplier

 16 bits × 16 bits → 32 bits

 Single-cycle multiplier

• DSP registers

 Two 40-bit data registers

 Six 32-bit data registers

 Modulo register (MOD, 32 bits) added to control registers

 Repeat counter (RC) added to status register (SR)

 Repeat start register (RS, 32 bits) and repeat end register (RE, 32 bits)

added to control registers

• DSP data bus

 Extended Harvard architecture

 Simultaneous access to two data buses and one instruction bus

• Parallel processing

 Maximum of four parallel processes

 ALU operations, multiplication, and two loads or stores

• Address processors

 Two address processors

 Address operations to access two memories

• DSP data addressing modes

 Increment and index

 Each with or without modulo addressing

• Repeat control: Zero-overhead repeat (loop) control

• Instruction set

 16-bit length (in case of load or store onl y)

 32-bit length (including ALU operations and multiplication)

 Added SuperH microcomputer instructions for accessing DSP

registers

• Fifth and last pipeline stage is DSP stage

Rev. 2.00, 03/05, page 4 of 884

Item Specifications

Cache • Mixed instruction/data type cache

• Maximum of 4 kbytes

• 4-way set-associative type

• 16-byte line length

• 64 cache tag entries

• 16-byte write-back buffer

• Selection of wr ite-through or write-back mode for data writes

• LRU replacement algorithm

• Can also be used as 2-kbyte cache and 2-kbyte RAM (2-way cache mode)

• Mixed instruction/data cache, instruction cache, or data cache mode can

be set

• 1-cycle reads, 2-cycle writes (in write-back mode)

Interrupt controller

(INTC) • 16 priority levels can be set

• On-chip supporting module interrupt vector numbers can be set

• 41 internal interrupt sources

• The E-DMAC interrupt (EINT) is input to the INTC as the OR of 22 EtherC

and E-DMAC interrupt sources (max.). Thus, from the viewpoint of the

INTC, there is one EtherC/E-DMAC interrupt source.

• Five external interrupt pins (NMI,

IRL0

IRL3

)

15 external interrupt sources (encoded input) can also be selected for pins

IRL0

IRL3

(IRL interru pts )

• IRL interrupt vector number setting can also be selected (selection of auto

vector or external vector)

• Provision for IRQ interrupt setting (low-level, rising-edge, falling-edge,

both-edge detection)

Rev. 2.00, 03/05, page 5 of 884

Item Specifications

User break

controller (UBC),

4 channels

(A, B, C, D)

• Interrupt generation based on independent or sequential conditions for

channels A, B, C, D

 Three sequential setting patterns: A → B → C → D, B → C → D,

C → D

• Settable break conditions: Address, data (channels C and D only), bus

master (CPU/DMAC), bus cycle (instruction fetch/data access), read/write,

operand cycle (byte/word/longword)

• User break interrupt generated on occurrence of break condition

• Processing can be stopped before or after instruction ex ecution in

instruction fetch cycle

• Break with specification of number of executions (channels C and D only)

Settable number of executions: max. 212 – 1 (4095)

• PC trace function

Branch source/branch destination can be traced in branch instruction fetch

(max. 8 addresses (4 pairs))

Rev. 2.00, 03/05, page 6 of 884

Item Specifications

Bus state controller

(BSC) • Address space divided into fi ve areas (CS0 to CS4, max. l inear 32 Mbytes

each)

 Memory types such as DRAM, synchronous DRAM, burst ROM, can

be specified for each area

 Two synchronous DRAM spaces (CS2, CS3); CS3 also supports

DRAM

 Bus width (8, 16, 32 bits) can be selected for each area

 Wait state insertion control for each area

 Control signal output for each area

 Endi an can be set for CS2 and CS4

• Cache

 Cache area/cache-through area selection by access address

 Selection of write-through or write-back mode

• Refresh functions

 CAS-before-RAS refreshing (auto refreshing) or self-refreshing

 Refresh interval settable by means of refresh counter and clock select

setting

 Concentrated refreshing according to refresh count setting

(1, 2, 4, 6, 8)

 Refresh request output possible (REFOUT)

• Direct DRAM i nterface

 Multiplexed row address/column address output

 Fast page mode burst transfer and continuous access when reading

 EDO mode

 TP cycle generation to secure RAS precharge time

• Direct synchronous DRAM interface

 Multiplexed row address/column address output

 Bank-active mode (valid for CS3 only)

 Selection of burst read/single write mode or burst read/burst write

mode

• Bus arbitration (

BRLS

BGR

)

• Refresh counter can be used as interval timer

 Interrupt request generated on compare match (CMI interrupt request

signal)

Rev. 2.00, 03/05, page 7 of 884

Item Specifications

Direct memory

access controller

(DMAC),

2 channels

• 4-Gbyte address space, maximum 16M (16,777,216) transfers

• Selection of 8-bit, 16-bit, 32-bit, or 16-byte transfer data length

• Parallel execution of CPU instruction processing and DMA operation

possible in case of cache hit

• Selection of dual address or single address mode

 Single address (data transfer rate of one transfer unit in one bus cycle)

 Dual address (data transfer rate of one transfer uni t in two bus cycles)

 When synchronous DRAM is connected, 16-byte continuous read →

continuous write transfer i s available (dual)

 When synchronous DRAM is connected, single-address transfer is

available in a single clock cycle at maximum 31.25 MHz

• Cycle stealing or burst transfer

• Relative channel priorities can be set (fixed mode/round robin mode)

• DMA transfer is possible for the following devices:

 External memory, on-chip memory, on-chip supporting modules

(excl uding DMAC, BSC, UBC, cache, E-DMAC, Eth erC)

• External requests, DMA transfer requests from on-chip supporting

modules, auto requests

• Interrupt request (DEIn) can be issued to CPU at end of data transfer

• DACK used for DREQ sampling (however, there i s always one overrun as

there is one acceptance before first DACK)

On-chip RAM • 4-kbyte X-RAM

• 4-kbyte Y-RAM

Ethernet controller

direct memory

access controller

(E-DMAC),

2 channels

• Transfer possible between EtherC and external memory/on-chip me mory

• 16-byte burst transfer possible

• Single address transfer

• Chain block transfer

• 32-bit transfer data width

• 4-Gbyte address space

Rev. 2.00, 03/05, page 8 of 884

Item Specifications

Ethernet controller

(EtherC) • MAC (Media Access Control) functions

 Data frame assembly/disassembly (IEEE802.3-compliant frames)

 CSMA/CD link management (collision avoidance, processing in case

of collision)

 CRC processing

 Built-in FIFOs (512 bytes each for transmission and reception)

 Supports full-duplex transmission/reception

 Transmitting and receiving short and long packets

• Compatible with MII (Media Independent Interface) standard

 Converts 8-bit stream data from MAC level to MII nibble stream (4 bits)

 Station management (STA) functions

 18 TTL-level signals

 Variable transfer rate: 10/100 Mbps

• Magic Packet™* (with WOL (Wake On LAN) output)

Serial communi-

cation interface

with FIFO (SCIF),

2 channels

• Asynchronous mode

 Data length: 7 or 8 bits

 Stop bit length: 1 or 2

 Parity: Even, odd, or none

 Receive error detection: Parity errors, framing errors, overrun errors

 Break detection

• Synchronous mode

 One serial communication format (8-bit data length)

 Receive error detection: Overrun errors

• IrDA mode (conforming to IrDA 1.0)

• Simultaneous transmission/reception (full-duplex) capability

 Half-duplex communication used for IrDA communication

• Built-in dedicated baud rate generator allows selection of bit rate

• Built-in 16-stage transmit and receive FIFOs enable high-speed,

continuous communication

• Internal or external (SCK) transmi t/receive clock source

Note: *Magic Packet is a registered trademark of Advanced Micro Devices, Inc.

Rev. 2.00, 03/05, page 9 of 884

Item Specifications

Serial communi-

cation interface

with FIFO (SCIF),

2 channels

• Four interrupt sources

 Transmi t FIFO data empty

 Break

 Receive FIFO data full

 Receive error

• Built-in modem control functions (

RTS

CTS

)

• Detection of transmit and receive FIFO register data quantity and number

of receive FIFO register transmit data errors

• Timeout error (DR) can be detected during reception

Serial I/O (SIO),

3 channels • Full-duplex operation (independent transmit and receive registers, and

independent transmit and receive clocks)

• Transmit/receive ports with double-buffer structure (enabling continuous

transmission/reception)

• Interval transfer mode and continuous transfer mode

• Choice of 8- or 16-bit data length

• Data transfer communication by means of polling or interrupts

• MSB-first transfer between SIO and data I/O

High-performance

user debugging

interface (H-UD I)

• Conforms to IEEE1149.1 standard

 Five test signals (TCK, TDI, TDO, TMS,

TRST

)

 TAP controller

 Instruction register

 Data register

 Bypass register

• Test mode that conforms to the IEEE1149.1 standard

 Standard instructions: BYPASS, SAMPLE/ PRE LOAD, and EXTEST

 Optional instructions: CLAMP, HIGHZ, and IDCODE

• H-UDI interrupt

 H-UDI interrupt request to INTC

• Reset hold

Rev. 2.00, 03/05, page 10 of 884

Item Specifications

Timer pulse unit

(TPU), 3 channels • Maximum 8-pulse input/output

• Total of eight timer general registers (TGR) (four for channel 0, two each

for channels 1 and 2)

 Waveform output by compare match: Selection of 0, 1, or togg le output

 Input capture function: Selection of rising-edge, falli ng-edge, or both-

edge detection

 Counter clear operation: Counter clearing possible by compare match

or input captur e

 Synchronous operation: Multiple timer counters (TCNT) can be written

to simultaneously; simultaneous clearing by compare match and input

capture possible; simultaneous register input/output possible by

counter synchronous operation

 PWM mode: Any PWM output duty can be set; maximum 7-phase

PWM output possible by combination wi th synchronous operation

• Buffer operation settable for channel 0

 Input capture register double-buffering possible

 Automatic rewriting of output compare register possible

• Phase counting mode settable independently for channels 1 and 2

 Two-phase encoder pulse up/down-count possible

• 13 interrupt sources

 For channel 0, four compare match/input capture dual-function

interrupts and one overflow interrupt can be requested independently

 For channels 1 and 2, two compare match/input capture dual-function

interrupts, one overflow interrupt, and one underflow interrupt can be

requested independen tly

Rev. 2.00, 03/05, page 11 of 884

Item Specifications

16-bit free-running

timer (FRT),

1 channel

• Choice of four counter input clocks

 Three internal clocks (Pφ/8, Pφ/32, Pφ/128)

 External clock (enabling external event counting)

• Two independent comparators (allowing generation of two waveform

outputs)

• Input capture (choice of rising edge or falling edge)

• Counter clear specification

 Counter value can be cleared by compare match A

• Four interrupt sources

 Two compare match sources (OCIA, OCIB)

 One input capture source (ICI)

 One overflow source (OVI)

Watchdog timer

(WDT), 1 channel • Can be switched between watchdog timer mode and interval time r mode

• Internal reset, externa l signal (

WDTOVF

), or interrupt generated on count

overflow

• Used when standby mode is cleared or the clock frequency is changed,

and in clock pause mode

• Selection of eight counter input clocks

Clock pulse

generator (CPG) • Built-in clock pulse generator

• Selection of crystal or external clock as clock source

• Built-in clock-multiplication PLL circuits

• Built-in PLL circuit for phase synchronization between external clock and

internal clock

• CPU/DSP core clock (Iφ), peripheral module clock (Pφ), and external

interface cl ock (Eφ) frequencies can be scaled independently

Rev. 2.00, 03/05, page 12 of 884

Item Specifications

System controller

(SYSC) • Selection of seven operati ng mode settings, three power-down modes

• Operating modes

 Control the method of clock generation (PLL ON/OFF) and clock

division rat io

• Power-down mode

 Sleep mode: CPU functions halted

 Standby mode: All functions halted

 Module standby function: Operation of FRT, SCIF, DMAC, UBC, DSP,

TPU, and SIO on-chip supporting modules is halted selectively

I/O ports • 29 input/output ports

Rev. 2.00, 03/05, page 13 of 884

1.2 Block Diagram

CPU

X-RAM

Y-RAM

Bus state

controller

User break

controller

Interrupt

controller

Cache

address

array/data

array

DSP

Direct

memory access

controller

Ethernet

controller

direct memory

access

controller

Ethernet

controller

External bus

interface

Cache

controller

High-

performance

user debugging

interface

Serial

I/O

Timer

pulse unit

Watchdog

timer

Clock pulse

generator

Free-running

timer

Serial

communication

interface

with FIFO

System

controller

Cache address bus

Internal X address bus

Internal Y address bus

Peripheral address bus

Internal address bus

32-bit internal data bus

32-bit cache data bus

16-bit internal X data bus

16-bit internal Y data bus

I/O ports

16-bit peripheral data bus

Figure 1.1 Block Diagram of SH7615

Rev. 2.00, 03/05, page 14 of 884

1.3 Pin Description

1.3.1 Pin Arrangement

Figure 1.2 shows the pin arrangement of the HD6417615ARF and HD6417615ARFV, and figure

1.3 shows the pin arrangement of the HD6417615ARBP and HD6417615ARBPV.

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

PB11/SRS2/CTS/STATS0

PVCC

PB12/SRCK2/RTS/STATS1

PB13/TXD1

PB14/RXD1

PB15/SCK1

VSS

BGR

VCC

BRLS

DACK0

DACK1

DREQ0

DREQ1

BUSHiZ

CS4

CS3

CS2

CS1

CS0

RD/WR

VCC

VSS

REFOUT

CKE

CAS0

CAS1

CAS2

CAS3

DQMLL/WE0

DQMLU/WE1

DQMUL/WE2

DQMUU/WE3

CAS/OE

RAS

VCC

WAIT

VSS

A24

VCC

A23

A22

A21

A20

IRL3

IRL2

IRL1

IRL0

NMI

ASEMODE*

VSS

RES

PLLVSS

PLLCAP2

PLLCAP1

PLLVCC

MD4

MD3

MD2

MD1

MD0

VCC

EXTAL

VSS

XTAL

VCC

CKIO

CKPREQ/CKM

CKPACK

VSS

IVECF

TDO

TDI

TCK

TMS

TRST

VCC

VSS

VCC

VSS

D10

D11

D12

VCC

D13

VSS

A19

A18

A17

VSS

A16

VCC

A15

A14

A13

A12

A11

A10

VSS

VCC

VSS

D31

VCC

D30

D29

D28

D27

D26

D25

VSS

D24

VCC

D23

D22

D21

D20

VSS

D19

VCC

D18

D17

D16

D15

D14

104

103

102

101

100

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

PVSS

PB10/SRXD2/TIOCA1

PB9/STCK2/TIOCB1/TCLKC

PB8/STS2/TIOCA2

PB7/STXD2/TIOCB2/TCLKD

PB6/SRCK1/SCK2

PB5/SRS1/RXD2

PB4/SRXD1/TXD2

PB3/STCK1/TIOCA0

PB2/STS1/TIOCB0

PVCC

PB1/STXD1/TIOCC0/TCLKA

PVSS

PB0/TIOCD0/TCLKB/WOL

PA13/SRCK0

PA12/SRS0

PA11/SRXD0

PA10/STCK0

PA9/STS0

PA8/STXD0

PA7/WDTOVF

PA6/FTCI

PVCC

PA5/FTI

PVSS

PA4/FTOA

CKPO/FTOB

PA2/LNKSTA

PA1/EXOUT

PA0

RX-ER

RX-DV

COL

CRS

PVSS

RX-CLK

PVCC

ERXD0

ERXD1

ERXD2

ERXD3

MDIO

MDC

PVCC

TX-CLK

PVSS

TX-EN

ETXD0

ETXD1

ETXD2

ETXD3

TX-ER

FP-208C, FP-208CV

(Top view)

Body size

Height

Pin pitch

Note: * When doing debugging using the E10A emulator, this pin is used for mode switching. It should be connected to Vss

when using the E10A emulator and connected to Vcc when using a normal user system.

28 × 28

1.7

0.5

(mm)

Figure 1.2 HD6417615ARF and HD6417615ARFV Pin Arrangement

(FP-208C, FP-208CV )

Rev. 2.00, 03/05, page 15 of 884

NC ETXD3 ETXD1 TX-EN TX-CLK MDC ERXD1 RX-CLK RX-DV PA1/

EXOUT PVCC PA9/STS0 PA12/

SRS0

PB1/

STXD1/

TIOCC0/

TCLKA

PB3/

STCK1/

TIOCA0

PB5/

SRS1/

RXD2

PB7/

STXD2/

TIOCB2/

TCLKD

PB9/

STCK2/

TIOCB1/

TCLKC NC

IRL1 IRL3 ETXD2 TX-ER ETXD0 MDIO ERXD0 PVSS RX-ER CKPO/

FTOB PA5/FTI PA8/

STXD0 PA11/

SRXD0 PVSS PB6/

SRCK1/

SCK2

PB10/

SRXD2/

TIOCA1

PB8/

STS2/

TIOCA2 PVSS PVCC

NMI IRL0 NC PVSS PVCC ERXD3 PVCC CRS PA0 PA2/

LNKSTA PA4/FTOA WDTOVF/

PA7 PA10/

STCK0

PB0/

TIOCD0/

TCLKB/

WOL PVCC PB4/

SRXD1/

TXD2

PB2/

STS1/

TIOCB0

PB12/

SRCK2/

RTS/

STATS1

PB13/

TXD1

Vss IRL2 RES NC NC ERXD2 NC COL NC NC PVSS PA6/FTCI NC PA13/

SRCK0 NC NC NC PB11/

SRS2/

CTS/

STATS0

PB15/

SCK1

PLLVSS ASEMODE NC NC NC VSS PB14/

RXD1 VSS

PLLCAP2 PLLCAP1 NC PLLVCC NC VCC VCC BGR

MD4 MD3 MD2 MD1 DREQ0 DACK1 DACK0 BRLS

MD0 VCC EXTAL VSS CS4 BUSHiZ BH DREQ1

XTAL VCC NC NC CS1 CS0 CS2 CS3

VSS CKIO CKPREQ/

CKM CKPACK NC VCC BS RD/WR

TCK TDI IVECF TDO REFOUT VSS RD CKE

D0 VCC TRST TMS CAS0 CAS1 CAS2 CAS3

D3 D2 D1 VSS DQMLL/

WE0 DQMLU/

WE1 DQMUL/

WE2 DQMUU/

WE3

VCC D6 D5 D4 NC NC CAS/OE RAS

D8 D10 D7 NC VCC WAIT VCC VSS

D9 D13 VSS NC NC VCC NC D29 NC A0 NC A4 NC A9 NC NC VSS A21 A24

D11 D12 D20 VSS D21 VCC D25 D28 D31 VSS A1 A5 VCC A10 A13 A15 VSS A23 VCC

VCC D14 D17 D15 VCC D23 VSS D27 VCC VSS A2 A6 A8 A11 A16 A19 A17 A20 A22

VSS D16 D18 D19 VSS D22 D24 D26 D30 VCC A3 A7 VSS A12 A14 VCC VSS A18 NC

X' X

12345678910111213141516171819

BP-240A, BP-240AV

Bump No. (Top View)

Figure 1.3 HD6417615ARBP and HD6417615ARBPV Pin Arrangement

(BP-240A, BP-240AV )

Rev. 2.00, 03/05, page 16 of 884

1.3.2 Pin Funct ions

Table 1.2 Pin Functions

Type Symbol I/O Name Function

Power VCC Input Power For connection to the power supply.

Connect all VCC pins to the system power

supply. The chip will not operate if there

are any open pins

VSS Input Ground For connection to ground. Connect all

VSS pins to the system ground. The chip

will not operate if there are any open pins

PVCC Input I/O circuit power Power supply for the I/O circuits

PVSS Input I/O circuit

ground Ground for the I/O circuits

Clock XTAL Output For connection to a crystal resonator

EXTAL Input

Crystal input/

output pin For connection to a crystal resonator, or

used as external clock input pin

CKIO I/O Syste m clock

input/output

Used as the external clock input or

internal clock output pin

CKPREQ

CKM Input Clock pause

request input Used as the clock pause request pin for

changing the frequency of the clock input

from the CKIO pin, or halting the clock

CKPACK

Output Clock pause

acknowledge

signal

Indicates that the chip is in the clock

pause state (standby state) internally

CKPO Output On-chip

peripheral clock

(Pφ) output

Outputs the on-ch ip peripheral clock (Pφ)

PLLCAP1 Input PLL capacitance

connection pins Connects capacitance for operation of

PLL circuit 1

PLLCAP2 Input Connects capacitance for operation of

PLL circuit 2

PLLVCC Input PLL power PLL oscillator power supply

PLLVSS Input PLL ground PLL oscillator ground

Rev. 2.00, 03/05, page 17 of 884

Type Symbol I/O Name Function

System

control

RES

Input Reset When

RES

= 0 and NMI = 1, the chip

enters the power-on reset state. When

RES

= 0 and NMI = 0, the chip enters the

manual reset state

WDTOVF

Output Watchdog

timer overflow Counter overflow signal output in

watchdog timer mode

BGR

Output Bus grant Indicates that the bus has been released

to an external device. The device that

output the

BRLS

signal recognizes that

the bus has been acquired when it

receives the

BGR

signal

BRLS

Input Bus release Driven low when an external device

requests release of the bus

Operating

mode MD0 to MD4 Input Mode setting The operating mode is specified by the

levels at these pins

Interrupts NMI Input Nonmaskable

interrupt Inputs the nonmaskable interrupt request

signal

IRL3

IRL0

Input External

interrupt

request input

0 to 3

These pins input maskabl e interrupt

request signals

IVECF

Output Interrupt

vector fetch

cycle

Indicates an external vector read cycle

Bus control

Output Bus cycle

start Signal indicating the start of a bus cycle

Asserted every data cycle in burst

transfer

CS4

CS0

Output Chip select

0 to 4 Chip select signals indicating the area

being accessed

WAIT

Input Wait Wait state request signal

Output Read Strobe signal indicating a read cycle

RAS

Output Row address

strobe DRAM/synchronous DRAM RAS signal

Rev. 2.00, 03/05, page 18 of 884

Type Symbol I/O Name Function

Bus control

CAS

Output Column

address strobe Synchronous DRAM CAS signal

Output Output enable EDO DRAM output enable signal

Used in access in RAS down mode

DQMUU/

WE3

Output Highest byte

access SRAM/synchronous DRAM highest byte

select signal

DQMUL/

WE2

Output Second byte

access SRAM/synchronous DRAM second byte

select signal

DQMLU/

WE1

Output Third byte

access SRAM/synchronous DRAM third byte

select signal

DQMLL/

WE0

Output Lowest byte

access SRAM/synchronous DRAM lo west byte

select signal

CAS3

Output Column address

strobe 3 DRAM highest byte select signal

CAS2

Output Column address

strobe 2 DRAM second byte select signal

CAS1

Output Column address

strobe 1 DRAM third byte select signal

CAS0

Output Column address

strobe 0 DRAM lowest byte select signal

CKE Output Clock enable Synchronous DRAM clock enable signal

REFOUT Output Refresh out Signal requesting refresh execution

when the bus is released

RD/

Output Read/write DRAM/synchronous DRAM write signal

BUSHiZ

Input Bus high

impedance Signal used in combination with WAIT

signal to pl ace bus and strobe signals in

the high-impedance (HiZ) state without

ending the bus cycle

Output Burst hint Asserted at the start of a DMA burst,

negated one bus cycle before the end of

the burst

STATS0,

STATS1 Output Status CPU, DMAC, and E-DMAC status

information

Rev. 2.00, 03/05, page 19 of 884

Type Symbol I/O Name Function

Bus control A24 to A0 Output Address bus Address output

D31 to D0 I/O Data bus Data input/output

H-UDI TCK Input Test clock Test clock input

TMS Input Test mode

select Test mode select input signal

TDI Input Test data input Serial data input

TDO Output Test data output Serial data output

TRST

Input Test reset Test reset input signal

ASEMODE*1Input ASE mode input ASE mode/user mode select signal

TX-CLK Input Transmitter

clock TX-EN, ETXD0 to ETXD3, TX-ER timing

reference signal

Ethernet

controller

(EtherC) RX-CLK Input Receive clock RX-DV, ERXD0 to ERXD3, RX-ER

timing reference signal

TX-EN Output Transmit enable Si gnal indicating that transmit data on

ETXD0 to ETXD3 is ready

ETXD0 to

ETXD3 Output Transmit data

0 to 3 4-bit transmi t data

TX-ER Output Transmit error Signal sending error status to another

port

RX-DV Input Receive data

enable Indicates that enable receive data on

ERXD0 to ERXD3 exist

ERXD0 to

ERXD3 Input Receive data

0 to 3 4-bit receive data

RX-ER Input Receive error Reports error state that occurred during

transfer of frame data

CRS Input Carrier sense Carrier detection notification signal

COL Input Collision Collision detection signal

MDC Output Management

data clock Reference clock signal for i nformation

transfer by MDIO

MDIO I/O Management

data input/output Bidirectional signal for exchanging

management information between STA

and PHY

Rev. 2.00, 03/05, page 20 of 884

Type Symbol I/O Name Function

LNKSTA Input Link status Link status input from PHY

EXOUT Output General-purpose

external output General-purpose external output pin

Ethernet

controller

(EtherC)

WOL Output Wake on LAN Signal indicating detection of a Magic

Packet

DACK0,

DACK1 Output DMAC

channel 0, 1

acknowledge

These pins output receiving a DMA

transfer request to an external device

Direct

memory

access

controller

(DMAC) DREQ0,

DREQ1 Input DMAC

channel 0, 1

request

Pins that input DMA transfer requests

from an external device

TXD1, TXD2 Output Transmit data

output channel

1, 2

SCIF channel 1 and 2 transmi t data

output pins

Serial

communi-

cation

interface with

FIFO (S CIF) RXD1, RXD2 Input Recei ve data

input channel

1, 2

SCIF channel 1 and 2 receive data input

pins

SCK1, SCK2 I/O Serial clock

input/output

channel 1, 2

SCIF clock input/output pins

RTS

Output Transmit

request SCIF channel 1 transmit request output

CTS

Input Transmit enable SCIF channel 1 transmit enable input pin

Timer pulse

unit (TPU) TCLKA

TCLKB

TCLKC

TCLKD

Input TPU timer clock

input A, B, C, D Pi ns that input an external clock to the

TPU counter

TIOCA0

TIOCB0

TIOCC0

TIOCD0

I/O TPU input

capture/output

compare

(channel 0)

Channel 0 input capture input/

output compare output/PWM output pins

TIOCA1

TIOCB1 I/O TPU input

capture/output

compare

(channel 1)

Channel 1 input capture input/

output compare output/PWM output pins

Rev. 2.00, 03/05, page 21 of 884

Type Symbol I/O Name Function

Timer pulse

unit (TPU) TIOCA2

TIOCB2 I/O TPU input

capture/output

compare

(channel 2)

Channel 2 input capture input/output

compare output/PWM output pins

FTCI Input Counter clock

input FRC counter clock input pin16-bit

free-running

timer (FRT) FTOA Output Output compare

A output Output compare A output pin

FTOB Output Output compare

B output Output compare B output pin

FTI Input Input capture

input Input capture input pin

Serial I/O

(SIO) SRXD0 to

SRXD2 Input Serial rece ive

data input 0 to 2 Serial receive data input ports

SRCK0 to

SRCK2 Input Serial receive

clock input 0 to 2 Serial receive clock ports

SRS0 to

SRS2 Input Serial receive

synchronization

input 0 to 2

Serial receive synchron izat ion input ports

STXD0 to

STXD2 Output Serial transmit

data 0 to 2 Serial data output ports

STCK0 to

STCK2 Input Serial transmit

clock input 0 to 2 Serial transmit clock ports

STS0 to

STS2 I/O Serial transmit

synchronization

input/output 0 to 2

Serial transmit synchronization

input/output ports

I/O ports PA0 to

PA13*2I/O General port General input/output port pins

Input or output can be specified bit by bit

PB0 to PB15 I/O General port General input/output port pins

Input or output can be specified bit by bit

Notes: 1. When carrying out debugging using the E10A emulator, this pin is used for mode

switching. It should be connected to VSS when using the E10A emulator and connected

to VCC when using a normal user system. When a boundary scan test is performed with

the H-UDI, user mode must be used. A boundary scan test cannot be performed in ASE

mode.

2. PA3 cannot be used; CKPO is valid instead.

Rev. 2.00, 03/05, page 22 of 884

1.3.3 Pin Multiplexing

Table 1.3 Pin Multiplexing (1)

BP-

240A/

FP-

208C/

CV Func tion 1 Function 2 Function 3 F unction 4 Type

F4 12 PLLVCC Clocks

E1 9 PLLVSS

F2 11 PLLCAP1

F1 10 PLLCAP2

H3 19 EXTAL

J1 21 XTAL

K2 23 CKIO

K3 24

CKPREQ

/CKM

K4 25

CKPACK

9 pins

D3 8

RES

G1 13 MD4

System

control

G2 14 MD3

G3 15 MD2

G4 16 MD1

H1 17 MD0 6 pins

C1 5 NMI Interrupts

B2 1

IRL3

D2 2

IRL2

B1 3

IRL1

C2 4

IRL0

L3 27

IVECF

6 pins

Rev. 2.00, 03/05, page 23 of 884

BP-

240A/

FP-

208C/

CV Function 1 Function 2 Function 3 Function 4 Type

K18 131

Bus control

H16 138

CS4

J19 137

CS3

J18 136

CS2

J16 135

CS1

J17 134

CS0

F19 148

BGR

G19 145

BRLS

R17 115

WAIT

L18 128

P19 117

RAS

P18 118

CAS

N19 119 DQMUU/

WE3

N18 120 DQMUL/

WE2

N17 121 DQMLU/

WE1

N16 122 DQMLL/

WE0

M19 123

CAS3

M18 124

CAS2

M17 125

CAS1

M16 126

CAS0

L19 127 CKE

L16 129 REFOUT

K19 133 RD/

H17 139

BUSHiZ

H18 140

25 pins

Rev. 2.00, 03/05, page 24 of 884

BP-

240A/

FP-

208C/

CV Function 1 Function 2 Function 3 Function 4 Type

T19 111 A24

U18 108 A23 Address

bus

V19 107 A22

T18 106 A21

V18 105 A20

V16 104 A19

W18 103 A18

V17 102 A17

V15 100 A16

U16 98 A15

W15 97 A14

U15 96 A13

W14 95 A12

V14 94 A11

U14 93 A10

T14 92 A9

V13 90 A8

W12 88 A7

V12 87 A6

U12 86 A5

T12 85 A4

W11 84 A3

V11 83 A2

U11 82 A1

T10 80 A0 25 pins

Rev. 2.00, 03/05, page 25 of 884

BP-

240A/

FP-

208C/

CV Function 1 Function 2 Function 3 Function 4 Type

U9 77 D31 Data bus

W9 75 D30

T8 74 D29

U8 73 D28

V8 72 D27

W8 71 D26

U7 70 D25

W7 68 D24

V6 65 D23

W6 64 D22

U5 63 D21

U3 62 D20

W4 59 D19

W3 57 D18

V3 56 D17

W2 55 D16

V4 54 D15

V2 53 D14

T2 51 D13

U2 49 D12

U1 48 D11

R2 47 D10

T1 46 D9

R1 44 D8

R3 43 D7

P2 41 D6

P3 40 D5

P4 39 D4

N1 38 D3

N2 37 D2

N3 36 D1

M1 34 D0 32 pins

Rev. 2.00, 03/05, page 26 of 884

BP-

240A/

FP-

208C/

CV Function 1 Function 2 Function 3 Function 4 Type

L1 30 TCK H-UDI

M4 31 TMS

L2 29 TDI

L4 28 TDO

M3 32

TRST

E2 6 ASEMODE*6 pins

A5 201 TX-CLK EtherC

A8 192 RX-CLK

A4 203 TX-EN

A2 207 ETXD3

5 V I/O

compatibility

B3 206 ETXD2

A3 205 ETXD1

B5 204 ETXD0

B4 208 TX-ER

A9 188 RX-DV

C6 197 ERXD3

D6 196 ERXD2

A7 195 ERXD1

B7 194 ERXD0

B9 187 RX-ER

C8 190 CRS

D8 189 COL

A6 199 MDC

B6 198 MDIO 18 pins

G17 143 DACK1 DMAC

G18 144 DACK0

H19 141 DREQ1

G16 142 DREQ0 4 pins

Note: *When carrying out debugging using the E10A emul ator, this pin is used for mode

switching. It should be connected to VSS when using the E10A emulator (ASE mode).

When using the chip in the normal user system, and not using the E10A emulator (user

mode), connect this pin to VCC. When a boundary scan test is performed with the H-

UDI, user mode must be used. A boundary scan test cannot be performed in ASE

mode.

Rev. 2.00, 03/05, page 27 of 884

Table 1.3 Pin Multiplexing (2)

BP-

240A/

FP-

208C/

CV Function 1

[00]*Function 2

[01]*Function 3

[10]*Function 4

[11]*Type

D19 151 PB15 SCK1 Port B

E18 152 PB14 RXD1 SCIF, SIO,

TPU

C19 153 PB13 TXD1

C18 154 PB12 SRCK2

RTS

STATS1

D18 156 PB11 SRS2

CTS

STATS0

5 V I/O

compatibility

B16 158 PB10 SRXD2 TIOCA1

A18 159 PB9 STCK2 TIOCB1/TCLKC

B17 160 PB8 STS2 TIOCA2

A17 161 PB7 STXD2 TIOCB2/TCLKD

B15 162 PB6 SRCK1 SCK2

A16 163 PB5 SRS1 RXD2

C16 164 PB4 SRXD1 TXD2

A15 165 PB3 STCK1 TIOCA0

C17 166 PB2 STS1 TIOCB0

A14 168 PB1 STXD1 TIOCC0/TCLKA

C14 170 PB0 TIOCD0/TCLKB WOL 16 pins

D14 171 PA13 SRCK0 Port A

A13 172 PA12 SRS0 SIO, FRT

B13 173 PA11 SRXD0

C13 174 PA10 STCK0

A12 175 PA9 STS0 5 V I/O

compatibility

B12 176 PA8 STXD0

C12 177

WDTOVF

PA7

D12 178 PA6 FTCI

B11 180 PA5 FTI

C11 182 PA4 FTOA

B10 183 CKPO FTOB

C10 184 PA2 LNKSTA

A10 185 PA1 EXOUT

C9 186 PA0 14 pins

Rev. 2.00, 03/05, page 28 of 884

Note: *Figures in square brackets indicate the settings of the mode bits (MD0, MD1) in the

PFC in order to select the mul tiplex functi ons in port A [0:13] and port B [0:15].

WDTOVF

: In a reset, this pin becomes an output pin.

When used for general input/output, attention must be paid to

the polarity of this pin.

1.4 Processing States

State Transitions: The CPU has five processing states: the reset state, exception handling state,

bus-released state, program execution state, and power-down state. Figure 1.4 shows the state

transitions.

RST = 0, NMI = 1

RST = 1,

NMI = 0

RST = 1,

NMI = 1

Interrupt or DMA

address error NMI interrupt

End of

exception

handling

Bus

request

Exception

Bus request

cleared

Bus request

received

Bus request

cleared

SLEEP

instruction

(SBY = 0)

SLEEP

instruction

(SBY = 1)

From any state when

RES = 0 and NMI = 1 From any state when

RES = 0 and NMI = 0

Reset states

Power-down state

Note: * clock pause function

Bus request

received

Bus request

cleared

RST = 0, NMI = 0

MSTP

bit

cleared

MSTP

bit set

Bus-released state

Exception-handling state

Manual reset statePower-on reset state

Program execution state

Sleep mode Standby mode

Module standby

SBY bit set and

CKPREQ = 0*

CKPREQ = 1*

Figure 1.4 Processing State Transitions

Rev. 2.00, 03/05, page 29 of 884

• Reset State

In this state, the CPU is reset. The reset state is entered when the

RES

pin goes low. The

power-on reset state is entered if the NMI pin is high, and the manual reset state is entered if

the NMI pin is low.

• Exception Handling State

The exception handling state is a transient state that occurs when the CPU alters the normal

programming flow dues to a reset, interrupt, or other exception handling source.

In the case of a reset, the CPU fetches the execution start address as the initial value of the

program counter (PC) from the exception vector table, and the initial value of the stack pointer

(SP), stores thes e values, b ranche s to the star t address, and beg i ns program exec ution at th at

address.

In the case of an interrupt, etc., the CPU references the SP and saves the PC and status register

(SR ) in the stack area. It fetch es the st ar t addre ss of the exce p tion serv i ce routi ne from th e

exception vector table, branches to that address, and begins program execution.

Subsequently, the processing state is the program execution state.

• Program Execution State

In the program execution state the CPU executes program instructions in normal sequence.

• Power-Down State

In the power-down state the CPU stops operating to conserve power. The power-down state is

entered by executing a SLEEP instruction. The power-down state includes two modes—sleep

mode and standby mode—and a module standby function.

• Bus-Released State

1. In the bus-released state, the CPU releases the bus to a device that has requested it.

2. Bus-released state during manual reset signal assertion

While the manual reset signal is being asserted (

RES

= low and NMI = low), no arbitration

request (

BRLS

input) is accepted. If the

BRLS

signal continues to be asserted, this LSI

remai ns in the bus-r el eas ed sta te (a sse rts the

BGR

signal).

When the

BRLS

signal is negated in the bus-released state during manual reset signal

assertion, this LSI starts using the bus (negates the

BGR

signal).

Power-Down State: In addition to the normal program execution state, another CPU processing

state called the power-down state is provided. In this state, CPU operation is halted and power

consumption is reduced. The power-down state includes two modes—sleep mode and standby

mode—and a module standby function.

Rev. 2.00, 03/05, page 30 of 884

• Sleep Mode

A transition to sleep mode is made if the SLEEP instruction is executed while the standby bit

(SBY) is cleared to 0 in standby control register 1 (SBYCR1). In sleep mode CPU operations

stop but data in the CPU’s internal registers and in on-chip cache memory and on-chip RAM is

retained. The functions of the on-chip suppo rting modules do not stop.

• Standby Mode

A transition to standby mode is made if the SLEEP instruction is executed while SBY is set to

1 in SBYCR1. In standby mode the CPU, the on-chip modules, and the oscillator all stop.

When entering standby mode, the DMAC’s DMA master enable bit should be cleared to 0.

Also, the cache should be turned off before entering this mode. The contents of the cache and

on-chip RAM are not retained in this mode.

Standby mode is exited by means of a reset or an external NMI interrupt. When standby mode

is exited, the normal program execution state is entered via the exception handling state after

the elapse of the oscillation settling time.

If a transition is made to standby mode using the clock pause function, it is possible to change

the frequency of the CKIO pin input clock, or to stop the clock itself. When SBY in SBYCR1

is set to 1 and a low level is applied to the

CKPREQ

/CKM pin, a transition is made to standby

mode and a low level is output from the

CKPACK

pin. The clock can then be stopped, or its

frequency changed.

On-chip supporting module states and pin states are the same as in the normal standby mode

entered by means of the SLEEP instruction. A transition to the program execution state is

made by applying a high level to the

CKPREQ

/CKM pin.

In this mode the oscillator is halted, greatly reducing power consumption.

• Module Standby Function

A module standby function is provided for the following on-chip supporting modules: the

direct memory access controller (DMAC), DSP, 16-bit free-running timer (FRT), serial

communication interface with FIFO (SCIF), serial I/O (SIO), user break controller (UBC), and

timer pulse unit (TPU). A module standby function is not supported for the Ethernet controller

(EtherC) or the Ethernet direct memory access controller (E-DMAC).

Setting one of module stop bits 11 to 3 and 1 (MSTP11 to MSTP3, MSTP1) to 1 in the standby

control reg i ster (SBY CR 1/2) stops the clock supply to the correspon ding on-chi p suppor ting

module. Use of this function enables power consumption to be reduced.

The module standby function is cleared by clearing the corresponding MSTP bit to 0.

DSP instructions must not be used when the DSP has been placed in the module standby state.

When using the DMAC module standby function, the direct memory access controller’s DMA

master enable bit should be cleared to 0.

Rev. 2.00, 03/05, page 31 of 884

Table 1.4 Power-Do w n State

State

Mode Entering

Conditions Clock CPU

On-chip

Supporting

Modules CPU

Registers

On-Chip

Cache or

On-Chip

RAM Exiting

Conditions

Sleep

mode Executing

SLEEP

instruction

while SBY bit

is cl eared in

SBYCR1

Operating Halted Operating Held Held 1. Interrupt

2. D M A a ddres s

error

3. Power-on re se t

4. Manual reset

Standby

mode Executing

SLEEP

instruction

while SBY

bit is set in

SBYCR1

Halted Halted Halted and

initialized*1Held Undefined 1. NMI interrupt

2. Power-on re se t

3. Manual reset

Module

standby

function

Setting

MSTP bit

corresponding

to individual

module

Operating Operating

(DSP

halted)

Clock suppl y

to specified

module

halted,

module

initialized*2

Held Held 1. Clearing MSTP

bit

2. Power-on re se t

3. Manual reset

Notes: 1. Depends on individual supporting module or pin.

2. DMAC and DSP registers and specified module interrupt vectors retain their set values.

Rev. 2.00, 03/05, page 32 of 884

Rev. 2.00, 03/05, page 33 of 884

Section 2 C PU

2.1 Register Descriptions

The register set consists of sixteen 32-bit general registers, six 32-bit control registers, and ten 32-

bit system registers.

This chip is upwardly compatible with the SH-1 and SH-2 on the object code level. For this

reason, several registers have been added to the previous SuperH microcomputer registers. The

added registers are the three control registers: repeat start register (RS), repeat end register (RE),

and modulo register (MOD), and the six system registers: DSP status register (DSR), and A0, A1,

X0, X1, Y0 and Y1 among the DSP data registers.

The general registers are used in the same manner as the SH-1 or SH-2 with regard to SuperH

microcomputer-type instructions. With regard to DSP type instructions, they are used as address

and index registers for accessing memory.

2.1.1 General Registers

There are 16 general registers (Rn) numbered R0 to R15, which are 32 bits in length. General

registers are used for data processing and address calculation.

With SuperH microcomputer type instructions, R0 is also used as an index register. Several

instructions are limited to use of R0 only. R15 is used as the hardware stack pointer (SP). Saving

and recovering the status register (SR) and program counter (PC) in exception processing is

accomplished by referencing the stack using R15.

With DSP type instructions, eight of the 16 general registers are used for the addressing of X and

Y data memory and data memory (single data) using the I bus.

R4 and R5 are used as an X address register (Ax) for X memory accesses, and R8 is used as an X

index register (Ix). R6 and R7 are used as a Y address register (Ay) for Y memory accesses, and

R9 is used as a Y index register (Iy). R2, R3, R4, and R5 are used as a single data address register

(As) for accessing single data using the I bus, and R8 is used as a single data index register (Is).

DSP type instructions can simultaneously access X and Y data memory. There are two groups of

address pointers for designating X and Y data memory addresses.

Figure 2.1 shows the general registers.

Rev. 2.00, 03/05, page 34 of 884

R2, [As]

R3, [As]

R4, [As, Ax]

R5, [As, Ax]

R6, [Ay]

R7, [Ay]

R8, [Ix, Is]

R9, [Iy]

R10

R11

R12

R13

R14

R15, SP

031

R0 also functions as an index register in the indirect indexed register

addressing mode and indirect indexed GBR addressing mode. In some

instructions, only the R0 functions as a source register or destination register.

R15 functions as a hardware stack pointer (SP) during exception processing.

Used as memory address registers, memory index registers with DSP type

instructions.

Notes: 1.

Figure 2.1 General Register Configuration

With the assembler, symbol names are used for R2, R3 ... R9. If it is wished to use a name that

makes clear the role of a register for DSP type instructions, a different register name (alias) can be

used. This is written in the following manner for the assembler.

Ix: .REG (R8)

Rev. 2.00, 03/05, page 35 of 884

The name Ix is an alias for R8. The other aliases are assigned as follows:

Ax0: .REG (R4)

Ax1: .REG (R5)

Ix: .REG (R8)

Ay0: .REG (R6)

Ay1: .REG (R7)

Iy: .REG (R9)

As0: .REG (R4) defined when an alias is required for single data transfer

As1: .REG (R5) defined when an alias is required for single data transfer

As2: .REG (R2) defined when an alias is required for single data transfer

As3: .REG (R3) defined when an alias is required for single data transfer

Is: .REG (R8) defined when an alias is required for single data transfer

2.1.2 Control Registers

The six 32-bit control registers consist of the status register (SR), repeat start register (RS), repeat

end register (RE), global base register (GBR), vector base register (VBR), and modulo register

(MOD).

The SR register indicates processing states.

The GBR register functions as a base address for the indirect GBR addressing mode, and is used

for such as on-chip peripheral module register data transfers.

The VBR register functions as the base address of the exception processing vector area (including

interrupts).

The RS and RE registers are used for program repeat (loop) control. The repeat count is

designated in the SR register repeat counter (RC), the repeat start address in the RS register, and

the repeat end address in the RE register. However, note that the address values stored in the RS

and RE registers are not necessarily always the same as the physical start and end address values

of the repeat.

The MOD register is used for modulo addressing to buffer the repeat data. The modulo addressing

designation is made by DMX or DMY, the modulo end address (ME) is designated in the upper 16

bits of the MOD register, and the modulo start address (MS) is designated in the lower 16 bits.

Note that the DMX and DMY bits cannot simultaneously designate modulo addressing. Modulo

addressing is possible with X and Y data transfer instructions (MOVX, MOVY). It is not possible

with single data transfer instructions (MOVS).

Rev. 2.00, 03/05, page 36 of 884

Figure 2.2 shows the control registers. Table 2.1 indicates the SR register bits.

STI3 I2 I1 I0 RF1 RF0QMDMXDMY00000000 RC

31 28 27 1615 12 11 10 9 8 7 4 3 2 1 0

Status register (SR)

Repeat start register (RS)

Repeat end register (RE)

Global base register (GBR)

Vector base register (VBR)

Modulo register (MOD)

ME: Modulo end address

MS: Modulo start address

016 15

GBR

VBR

ME MS

Figure 2.2 Control Register Configuration

Rev. 2.00, 03/05, page 37 of 884

Table 2.1 SR Register Bits

Bit Name (Abbreviation) Function

27 to 16 Repeat counter (RC) Designate the repeat count (2 to 4095) for repeat

(loop) control

11 Y pointer usage modulo

addressing designation

(DMY)

1: modulo addressing mode becomes valid for Y

memory address pointer, Ay (R6, R7)

10 X pointer usage modulo

addressing designation

(DMX)

1: modulo addressing mode becomes valid for X

memory address pointer, Ax (R4, R5)

9 M bit Used by the DIV0S/U, DIV1 instructions

8 Q bit Used by the DIV0S/U, DIV1 instructions

7 to 4 Interrupt request mask (I3

to I0) Indicate the receive level of an interrupt request (0 to

15)

3 to 2 Repeat flags (RF1, RF0) Used in zero overhead repeat (loop) control. Set as

below for an SETRC instruction

For 1 step repeat 00 RE — RS = –4

For 2 step repeat 01 RE — RS = –2

For 3 step repeat 11 RE — RS = 0

For 4 steps or more 10 RE — RS > 0

1 Saturation arithmetic bit

(S) Used with MAC instructions and DSP instructions

1: Designates saturation arithmetic (prevents

overflows)

0 T bit For MOVT, CMP/cond, TAS, TST, BT, BT/S, BF,

BF/S, SETT, CLRT and DT in structions,

0: represents false

1: represents true

For ADDV/ADDC, SUBV/SUBC, DIV0U/DIV0S, DIV1,

NEGC, SHAR/SHAL, SHLR/SHLL, ROTR/ROTL and

ROTCR/ROTCL instructions,

1: represents occurrence of carry, borrow, overflow or

underflow

31 to 28

15 to 12 0 bit 0: 0 is always read out; write a 0

Rev. 2.00, 03/05, page 38 of 884

There are dedicated load/store instructions for accessing the RS, RE and MOD registers. For

example, the RS register is accessed as follows.

LDC Rm,RS; Rm→RS

LDC.L @Rm+,RS; (Rm)→RS,Rm+4→Rm

STC RS,Rn; RS→Rn

STC.L RS,@-Rn; Rn-4→Rn,RS→(Rn)

The following instructions set addresses in the RS, RE registers for zero overhead repeat control:

LDRS @(disp,PC); disp×2 + PC→RS

LDRE @(disp,PC); disp×2 + PC→RE

The GBR register and VBR register are the same as the previous SuperH microprocessor registers.

An RC counter and four control bits (DMX bit, DMY bit, RF1 bit, RF0 bit) have been added to

the SR register. The RS, RE and MOD registers are new registers.

2.1.3 System Registers

System registers consist of four 32-bit registers: high and low multiply and accumulate registers

(MAC H and MACL ), the procedu re regi ster (PR), and the program coun ter (PC). The MACH and

MACL store the results of multiplication or multiply and accumulate operations*. The PR stores

the return address from the subroutine procedure. The PC indicates the address of the program in

execution; it controls the flow of the processing. The PC indicates the fourth byte after the

instruction currently being executed. These registers are the same as those in the SuperH

microprocessor.

Note: * These are used only when executing an instruction that was supported by SH-1 and

SH-2. They are not used for newly added multiplication instructions (PMULS).

MACL

MACH

31 0

Multiply and accumulate

Procedure register (PR)

Program counter (PC)

Figure 2.3 System Register Configuration

Rev. 2.00, 03/05, page 39 of 884

In addition, among the DSP unit usage registers (DSP registers) described in 2.1.4 DSP Registers,

the DSP status register (DSR) and the five registers A0, X0, X1, Y0 and Y1 of the eight data

registers are treated as system registers. Among these, the A0 is a 40-bit register, but when data is

output from the A0 register, the guard bit section (A0G) is disregarded; when data is input to the

A0 register, the MSB of the data is copied into the guard bit section (A0G).

2.1.4 DSP Registers

The DSP unit has eight data registers and one control register as its DSP registers.

The DSP data registers are comprised of the two 40-bit registers A0 and A1, and the six 32-bit

registers M0, M1, X0, X1, Y0 and Y1. The A0 and A1 registers have the 8-bit guard bits A0G and

A1G, respectively.

The DSP data registers are used for the transfer and processing of the DSP data of DSP instruction

operands. There are three types of instructions that access DSP data registers: those for DSP data

processing, and those for X or Y data transfer processing.

The control register is the 32-bit DSP status register (DSR) that represents operation results. The

DSR register has bits that represent operation results, a signed greater than bit (GT), a zero bit (Z),

a negative value bit (N), an overflow bit (V), a DSP status bit (DC: DSP condition), and a status

selection bit (CS: condition select) for controlling DC bit setting.

The DC bit represents one status flag and is very similar to the SuperH microprocessor CPU core

T bit. For conditional DSP type instructions, DSP data processing execution is controlled in

accordance with the DC bit. This control is related to execution in the DSP unit only, and only

DSP registers are updated. It bears no relation to address calculation or such SuperH

microprocessor CPU core execution instructions as load/store instructions. The control bits CS

(bits 2 to 0) designate the status for setting the DC bit.

DSP type instructions are comprised of unconditional DSP type instructions and conditional DSP

type instructions. The status and DC bits are updated in unconditional DSP type data processing,

with the exception of the PMULS, MOVX, MOVY and MOVS instructions. Conditional DSP

type instructions are executed according to the status of the DC bit, but regardless of whether or

not they are executed, the DSR register is not updated.

Figure 2.4 shows the DSP registers. The DSR register bit functions are shown in table 2.2.

Rev. 2.00, 03/05, page 40 of 884

39 32 31 0

A0G

A1G A0

DSP data registers

DSP status register (DSR)

GT Z N V CS[2:0] DC

87654321031

Figure 2.4 DSP Register Configuration

Rev. 2.00, 03/05, page 41 of 884

Table 2.2 DSR Register Bits

Bit Name (Abbreviation) Function

31 to 8 Reserved 0: These bits are always read as 0. The write value

should always be 0.

7Signed greater than bit

(GT) Indicates that the operation result is positive

(excepting 0), or that operand 1 is greater than

operand 2

1: Operation result is positive, or operand 1 is greater

6 Zero bit (Z) Indicates that the operation result is zero (0), or that

operand 1 is equal to operand 2

1: Operation result is zero (0), or equivalence

5 Negative bit (N) Indicates that the operation result is negative, or that

operand 1 is smaller than operand 2

1: Operation result is negative, or operand 1 is

smaller

4 Overflow bit (V) Indicates that the operation result has overflowed

1: Operation re sult has overflowed

3 to 1 Status selection bits (CS) Designate the mode for selecting the operation result

status set in the DC bit

Do not set either 110 or 111

000: Carry/borrow mode

001: Negative value mode

010: Zero mode

011: Overflow mode

100: Signed greater mode

101: Signed above mode

0 DSP status bit (DC) Sets the status of the operation result in the mode

designated by the CS bits

0: Designated mode status not realized (unrealized)

1: Designated mode status realized

Rev. 2.00, 03/05, page 42 of 884

2.1.5 Notes on Guard Bits and Overflow Treatment

DSP unit data operations are fundamentally performed in 32 bits, but these operations are always

executed with a 40-bit length including the 8-bit guard section. When the guard bit section does

not match the value of the 32-bit section MSB, the operation result is treated as an overflow. In

this case, the N bit indicates the correct status of the operation result regardless of the existence or

not of an overflow. This is so even if the destination operand is a 32-bit length register. The 8-bit

section guard bits are always presupposed and each status flag is updated.

When place overflows occur so that the correct result cannot be displayed even when the guard

bits are used, the N flag cannot indicate the correct status.

2.1.6 Initial Values of Registers

Table 2.3 lists the values of the registers after reset.

Table 2.3 Initial Values of Registers

Classification Register Initial Value

General registers R0 to R14 Undefined

R15 (SP) Value of the SP in the vector address table

Control registers SR Bits I3 to I0 are 1111 (H'F), the reserved bits, RC,

DMY, and DMX are 0, and other bits are undefined

Undefined

GBR Undefined

VBR H'00000000

MOD Undefined

System registers MACH, MACL, PR Undefined

PC Value of the PC in the vector address table

DSP registers A0, A0G, A1, A1G, M0,

M1, X0, X1, Y0, Y1 Undefined

DSR H'00000000

Rev. 2.00, 03/05, page 43 of 884

2.2 Data F o rmats

2.2.1 Data Format in Registe rs

longword, then loaded into the register.

31 0

Longword

Figure 2.5 Register Data Format

2.2.2 Data For mats in Memory

These formats are classified into bytes, words, and longwords.

Place byte data in any address, word data from 2n addresses, and longword data from 4n

addresses. An address error will occur if accesses are made from any other boundary. In such

cases, the access results cannot be guaranteed. In particular, the stack area referred to by the

hardware stack pointer (SP, R15) stores the program counter (PC) and status register (SR) as

longwords, so establish the hardware stack pointer so that a 4n value will always result.

To enable sharing of the processor accessing memory in little-endian mode and memory, the CS2,

4 space (area 2, 4) has a function that allows access in little-endian mode. The order of byte data

differs between little-endian mode and normal big-endian mode.

31 015

23 7

Byte Byte Byte Byte

WordWord

Address 2n

Address 4n Longword

Address m Address m + 2

Address m + 1 Address m + 3

Big endian

31 015

23 7

Byte Byte Byte Byte

WordWord Address 2n

Address 4n

Longword

Address m + 3 Address m + 1

Address m + 2 Address m

Little endian

Figure 2.6 Data Formats in Me mory

Rev. 2.00, 03/05, page 44 of 884

2.2.3 Immediate Data Format

Byte immediate data is placed in an instruction code.

With the MOV, ADD, and CMP/EQ instructions, immediate data is sign-extended and operated in

registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions

is zero-extended and handled as longword data. Consequently, AND instructions with immediate

data always clear the upper 24 bits of the destination register.

Word or longword immediate data is not located in the instruction code; it should be placed in a

memory table. Use an immediate data transfer instruction (MOV) to refer the memory table using

the PC relative addressing mode with displacement.

2.2.4 DSP Type Data Formats

This chip has three different types of data format that correspond to various instructions. These are

the fixed-point data format, the integer data forma t, and the logical data format.

The DSP type fixed-point data format has a binary point fixed between bits 31 and 30. There are

three types: with guard bits, without guard bits, and multiplication input; each with different valid

bit lengths and value ranges.

The DSP type integer data format has a binary point fixed between bits 16 and 15. There are three

types: with guard bits, without guard bits, and shift amount; each with different valid bit lengths

and value ranges. The shift amount of the arithmetic shift (PSHA) has a 7-bit range and can

express values from –64 to +63, but the actual valid values are from –32 to +32. In the same

manner, the shift amount of the logical shift has a 6-bit range, but the actual valid values are from

–16 to +16.

The DSP type logical data format does not have a decimal point.

The data format and valid data length are determined by the instructions and DSP registers.

Figure 2.7 shows the three DSP type data formats and binary point positions. The SuperH type

data format is also shown for reference.

Rev. 2.00, 03/05, page 45 of 884

(16 bits)DSP logical data

SuperH integer (word)

(Reference)

DSP integer data

DSP fixed decimal

point data

With guard bits

No guard bits

Multiplication input

With guard bits

No guard bits

Arithmetic shift (PSHA)

Logical shift (PSHL)

–2

to +2

– 2

–31

–1 to +1 – 2

–31

–1 to +1 – 2

–15

–2

to +2

–1

–2

to +2

–1

–32 to +32

–16 to +16

–2

to +2

–1

16 15

: Sign bitS : Binary decimal point

: Unrelated to processing (ignored)

Figure 2.7 DSP Type Data Formats

Rev. 2.00, 03/05, page 46 of 884

2.2.5 DSP Type Instructions and Data Formats

The DSP data format and valid data length are determined by DSP type instructions and DSP

registers. There are three types of instructions that access DSP data registers, DSP data processing,

X, Y data transfer processing, and single data transfer processing instructions.

DSP Data Processing: The guard bits (bits 39 to 32) are valid when the A0 and A1 registers are

used as source registers in DSP fixed-point data processing. When any registers other than A0, A1

(i.e., M0, M1, X0, X1, Y0, Y1 registers) are used as source registers, the sign-extended part of that

registers, the guard bits (bits 39 to 32) are valid. When any registers other than A0, A1 are used as

destination registers, bits 39 to 32 of the result data are disregarded.

Processing for DSP integer data is the same as the DSP fixed-point data processing. However, the

lower word (the lower 16 bits, bits 15 to 0) of the source register is disregarded. The lower word

of the destination register is cleared to 0.

In DSP logical data processing, the upper word (the upper 16 bits, bits 31 to 16) of the source

upper word of the destination register is valid. The lower word and the guard bits of the A0, A1

regi sters are cl ear ed to 0.

X, Y Data Transfers: The MOVX.W and MOVY.W instructions access X, Y memory via the

16-bit X, Y data buses. The data loaded into registers and data stored from registers is always the

upper word (the upper 16 bits, bits 31 to 16).

When loading, the MOVX.W instruction loads X memory, with the X0 and X1 registers as the

destination registers. The MOVY.W instruction loads Y memory, with the Y0 and Y1 registers as

the destination registers. Data is stored in the upper word of the register; the lower word is cleared

to 0.

The upper word data of the A0, A1 registers can be stored in X or Y memory with these data

transfer instructions, but storing is not possible from any other registers. The guard bits and the

lower word of the A0, A1 registers are disregarded.

Single Data Transfers: The MOVS.W and MOVS.L instructions can access any memory via the

data bus (CDB). All DSP registers are connected to the CDB bus, and they can become source or

destination registers during data transfers. The two data transfer modes are word and longword.

In word mode, data is loaded to and stored in the upper word of the DSP register, with the

exception of the A0G, A1G registers. In longword mode, data is loaded to and stored in the 32 bits

of the DSP register, with the exception of the A0G, A1G registers. The A0G, A1G registers can be

treated as independent registers during single data transfers. The load/store data length for the

A0G, A1G registers is 8 bits.

Rev. 2.00, 03/05, page 47 of 884

If DSP registers are used as source registers in word mode, when data is stored from any registers

other than A0G, A1G, the data in the upper word of the register is transferred. In the case of the

A0, A1 registers, the guard bits are disregarded. When the A0G, A1G registers are the source

registers in word mode, only 8 bits of the data are stored from the registers; the upper bits are sign-

extended.

If the DSP registers are used as destination registers in word mode, the load is to the upper word of

the register, with the exception of A0G, A1G. When data is loaded to any register other than A0G,

A1G, the lower word of the register is cleared to 0. In the case of the A0, A1 registers, the data

sign is extended and stored in the guard bits; the lower word is cleared to 0. When the A0G, A1G

registers are the destination registers in word mode, the least significant 8 bits of the data are

loaded into the registers; the A0, A1 registers are not zero cleared but retain their previous values.

If the DSP registers are used as source registers in longword mode, when data is stored from any

registers other than A0G, A1G, the 32 bits (data) of the register are transferred. When the A0, A1

registers are used as the source registers the guard bits are disregarded. When the A0G, A1G

registers are the source registers in longword mode, only 8 bits of the data are stored from the

registers; the upper bits are sign-extended.

If the DSP registers are used as destination registers in longword mode, the load is to the 32 bits of

the register, with the exception of A0G, A1G. In the case of the A0, A1 registers, the data sign is

extended and stored in the guard bits. When the A0G, A1G registers are the destination registers in

longword mode, the least significant 8 bits of the data are loaded into the registers; the A0, A1

registers are not zero cleared but retain their previous values.

Tables 2.4 and 2.5 indicate the register data formats for DSP instructions. Some registers cannot

be accessed by certain instructions. For example, the PMULS instruction can designate the A1

for details.

Figure 2.8 shows the relationship between the buses and the DSP registers during transfers.

Rev. 2.00, 03/05, page 48 of 884

Table 2.4 Source Register Data Formats for DSP Instructions

39 to 32 31 to 16 15 to 0

A0, A1 DSP

operation Fixed decimal,

PDMSB,

PSHA

40-bit data

Integer 24-bit data —

Logic, PSHL,

PMULS —16-bit data

Data

transfer MOVX.W,

MOVY.W,

MOVS.W

MOVS.L 32-bit data

A0G, A1G MOVS.W Data ——Data

transfer MOVS.L

X0, X1, Y0,

Y1, M0, M1 DSP

operation Fixed decimal,

PDMSB,

PSHA

Sign*32-bit data

Integer 16-bit data —

Logic, PSHL,

PMULS —

MOVS.W

Data

transfer MOVS.L 32-bit data

Note: *The sign is extended and stored in the ALU’s guard bits.

Rev. 2.00, 03/05, page 49 of 884

Table 2.5 Destination Register Data Formats for DSP Instructions

39 to 32 31 to 16 15 to 0

A0, A1 DSP

operation Fixed

decimal,

PSHA,

PMULS

(Sign extend) 40-bit resu lt

Integer,

PDMSB 24-bit result Clear to 0

Logic, PSHL Clear to 0 16-bit result

Data transfer MOVS.W Sign extend 16-bit data

MOVS.L 32-bit data

A0G, A1G Data transfer MOVS.W Data Not updated Not updated

MOVS.L

X0, X1, Y0,

Y1, M0, M1 DSP

operation Fixed

decimal,

PSHA,

PMULS

—32-bit result

Integer, logic,

PDMSB,

PSHL

16-bit result Clear to 0

Data transfer MOVX.W,

MOVY.W,

MOVS.W

16-bit data

MOVS.L 32-bit data

Rev. 2.00, 03/05, page 50 of 884

39 32

31 0

A0G

A1G

DSR

CDB

XDB

YDB

MOVS.W,

MOVS.L

32 bits

16 bits

32 bits

MOVX.W,

MOVY.W

MOVS.W,

MOVS.L

8 bits

[7:0]

Figure 2.8 DSP Register-Bus Relationship during Data Transfers

2.3 CPU Core Instruction Features

The CPU core instructions are RISC type. The characteristics are as follows.

16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency.

One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using

the pipeline system. One state equals 16.0 ns when operating at 62.5 MHz.

Data Length: Longword is the basic data length for all operations. Memory can be accessed in

bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and

handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-

extended for logic operations. It also is handled as longword data.

Rev. 2.00, 03/05, page 51 of 884

Table 2.6 Sign Extension of Word Data

SH7615 CPU Description Example of Conventional CPU

MOV.W @(disp,PC),R1

ADD R1,R0

........

.DATA.W H'1234

Data is sign-extended to 32

bits, and R1 becom es

H'00001234. It is next operated

upon by an ADD instruction

ADD.W #H'1234,R0

Note: @(disp, PC) accesses the immediate data.

Load-Store Architecture: Basic operations are executed between registers. For operations that

involve memory access, data is loaded to the registers and executed (load-store architecture).

However, Instructions such as AND manipulating bits, are executed directly in memory.

Delayed Branche s: Such instructions as unconditional branches are delayed branch instructions.

In the case of delayed branch instructions, the branch occurs after execution of the instruction

immediately following the delayed branch instruction (slot instruction). This reduces pipeline

disruption during branching.

The branching operation of the delayed branch occurs after execution of the slot instruction.

However, with the exception of such branch operations as register updating, execution of

instructions is performed with the order of delayed branch instruction, then delayed slot

instruction.

For example, even if the contents of a register storing a branch destination address are modified by

a delayed slot, the branch destination address will still be the contents of the register before the

modification.

Table 2.7 Delayed Branch Instruc tions

SH7615 CPU Description Example of Conventional CPU

BRA TRGET

ADD R1,R0 Executes an ADD before

branching to TRGET ADD.W R1,R0

BRA TRGET

Mul tip l ic a tio n / Mu l ti ply-Acc u mu la te Op e ra t ion: 16 × 16 → 32 multiplications execute in one

to three cycles, and 16 × 16 + 64 → 64 multiply-accumulate operations execute in two to three

cycles. 32 × 32 → 64 multipl i cations and 32 × 32 + 64 → 64 multiply-accumulate operations

execute in two to four cycles.

Rev. 2.00, 03/05, page 52 of 884

T Bit: The T bit in the status register (SR) changes according to the result of a comparison, and

conditional branches occur in accordance with its true or false status. The number of instructions

modifying the T bit is kept to a minimum to improve the processing speed.

Table 2.8 T Bit

SH7615 CPU Description Example of Conventional CPU

CMP/GE R1,R0

BT TRGET0

BF TRGET1

T bit is set when R0 ≥ R1.

The program branches to TRGET0

when R0 ≥ R1.

The program branches to TRGET1

when R0 < R1

CMP.W R1,R0

BGE TRGET0

BLT TRGET1

ADD #–1,R0

CMP/EQ #0,R0

BT TRGET

T bit is not changed by ADD. T bit

is set when R0 = 0. The program

branches when R0 = 0

SUB.W #1,R0

BEQ TRGET

Immediate Data: Byte immediate data resides in instruction code. Word or longword immediate

data is not input in instruction codes but is stored in a memory table. An immediate data transfer

instruction (MOV) accesses the memory table using the PC relative addressing mode with

displacement.

Table 2.9 Immediate Data Accessing

Classification SH7615 CPU Example of Conventional CPU

8-bit imm ediate MOV #H'12,R0 MOV .B #H'12,R0

16-bit imm ediate MOV . W @(disp,PC),R0

........

.DATA.W H'1234

MOV.W #H'1234,R0

32-bit imm ediate MOV .L @(disp,PC),R0

........

.DATA.L H'12345678

MOV.L #H'12345678,R0

Note: @(disp, PC) accesses the immediate data.

Rev. 2.00, 03/05, page 53 of 884

Absolute Address: When data is accessed by absolute address, the value already in the absolute

address is placed in the memory table. Loading the immediate data when the instruction is

executed transfers that value to the register and the data is accessed in the indirect register

addressing mode.

Table 2.10 Absolute Address Accessing

Classification SH7615 CPU Example of Conventional CPU

Absolut e address MOV.L @(disp,PC),R1

MOV.B @R1,R0

........

.DATA.L H'12345678

MOV.B @H'12345678,R0

16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the pre-

existing displacement value is placed in the memory table. Loading the immediate data when the

instruction is executed transfers that value to the register and the data is accessed in the indirect

indexed register addressing mode.

Table 2.11 Displace me nt Acce ssing

Classification SH7615 CPU Example of Conventional CPU

16-bit displacement MOV.W @(disp,PC),R0

MOV.W @(R0,R1),R2

........

.DATA.W H'1234

MOV.W @(H'1234,R1),R2

Rev. 2.00, 03/05, page 54 of 884

2.4 Instruction Formats

2.4.1 CPU Instruction Addressing Modes

The addressing modes and effective address calculation for instructions executed by the CPU core

are listed in table 2.12.

Table 2.12 CPU Instruction Addressing Modes and Effective Addresses

Addressing

Mode Instruction

Format Effective Addresses Calculation Equation

Direct register

addressing Rn The effective address is register Rn

(The operand is the contents of register Rn) —

Indirect register

addressing @Rn The effective address is the content of register

Rn Rn

Post-increment

indirect register

addressing

@Rn+ The effective address is the content of register

Rn. A constant is added to the content of Rn after

the instruction is executed. 1 is added for a byte

operation, 2 for a word operation, and 4 for a

longword operation

Rn Rn

1/2/4

Rn + 1/2/4

(After the

instruction

executes)

Byte: Rn + 1 → Rn

Word: Rn + 2 → Rn

Longword: Rn + 4

→ Rn

Pre-decrement

indirect register

addressing

@–Rn The effective address is the value obtained by

subtracting a constant from Rn. 1 is subtracted

for a byte operation, 2 for a word operation, and

4 for a longword operation

1/2/4

Rn – 1/2/4

–

Rn – 1/2/4

Byte: Rn – 1 → Rn

Word: Rn – 2 →

Longword: Rn – 4

→ Rn (Instruction

executed with Rn

after calculation)

Rev. 2.00, 03/05, page 55 of 884

Addressing

Mode Instruction

Format Effective Addresses Calculation Equation

Indirect register

addressing

with

displacement

@(disp:4,

Rn) The effective address is Rn plus a 4-bit

displacement (disp). The value of disp is zero-

extended, and remains the same for a byte

operation, is doubled for a word operation, and is

quadrupled for a longword operation

1/2/4

disp

(zero-extended)

+ disp × 1/2/4

Byte: Rn + disp

Word: Rn + disp ×

Longword: Rn +

disp × 4

Indirect index ed

addressing

@(R0, Rn) The effective address is the Rn value plus R0

Rn + R0

Indirect GBR

addressing with

displacement

@(disp:8,

GBR) The effective address is the GBR value plus an

8-bit displacement (disp). The value of disp is

zero-extended, and remains the same for a byte

operation, is doubled for a word operation, and

is quadrupled for a longword operation

GBR

1/2/4

disp

(zero-extended) GBR

+ disp × 1/2/4

Byte: GBR + disp

Word: GBR + disp

× 2

Longword: GBR +

disp × 4

Rev. 2.00, 03/05, page 56 of 884

Addressing

Mode Instruction

Format Effective Addresses Calculation Equation

Indirect

indexed GBR

addressing

@(R0,

GBR) The effective address is the GBR value plus the R0

GBR

GBR + R0

PC relative

addressing

with

displacement

@(disp:8,

PC) The effective address is the PC value plus an

8-bit displacement (disp). The value of disp is zero-

extended, is doubled for a word operation, and is

quadrupled for a longword operation. For a longword

operation, the lowest two bits of the PC value are

masked

H'FFFFFFFC +

2/4

&(for longword)

disp

(zero-extended)

PC + disp × 2

PC&H'FFFFFFFC

+ disp × 4

Word: PC + disp

× 2

Longword: PC &

H'FFFFFFFC +

disp × 4

Rev. 2.00, 03/05, page 57 of 884

Addressing

Mode Instruction

Format Effective Addresses Calculation Equation

PC relative

addressing disp:8 The effective address is the PC val ue sign-extended

with an 8-bit displacement (disp), doubled, and added

to the PC value

disp

(sign-extended) PC + disp × 2

PC + disp × 2

disp:12 The effective address is the PC value sign-extended

with a 12-bit displacement (disp), doubled, and added

to the PC value

disp

(sign-extended) PC + disp × 2

PC + disp × 2

Rn The effective address is the register PC value plus

+PC + Rn

PC + Rn

Immediate

addressing #imm:8 The 8-bit immediate data (imm) for the TST, AND,

OR, and XOR instructions are zero-extended —

#imm:8 The 8-bit immediate data (imm) for the MOV, ADD,

and CMP/EQ instructions are sign-extended —

#imm:8 The 8-bit immediate data (imm) for the TRAPA

instruct ion is zero- ex tended and is quadrup led —

Rev. 2.00, 03/05, page 58 of 884

2.4.2 DSP Data Addressing

There are two different kinds of memory accesses with DSP instructions. One type is with the X,

Y data transfer instructions (MOVX.W, MOVY.W), and the other is with the single data transfer

instructions (MOVS.W, MOVS.L). The data addressing differs between these two types of

instructions. Table 2.13 shows a summary of the data transfer instructions.

Table 2.13 Overview of Data Transfer Instructions

Classification X, Y Data Transfer Processing

(MOVX.W, MOVY.W) Single Data Transfer Processing

(MOVS.W, MOVS.L)

Address registers Ax: R4, R5; Ay: R6, R7 As: R2, R3, R4, R5

Index registers Ix: R8, Iy: R9 Is: R8

Addressing Nop/Inc(+2)/index additi on: post-

update Nop/Inc(+2,+4)/index addition: post-

update

—Dec(–2,–4): pre-update

Modulo addressing Possible Not possi ble

Data b us XDB, YDB CDB

Data length 16 bits (word) 16 bits/32 bits (word/longword)

Bus contentio n None Yes

Memory X, Y data memory All memory spaces

Source regi sters Dx, Dy: A0, A1 Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,

A0G, A1G

Destination registers Dx: X0/X1; Dy: Y0/Y1 Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,

A0G, A1G

X, Y Data Addressing: Among the DSP instructions, the MOVX.W and MOVY.W instructions

can be used to simultaneously access X, Y data memory. The DSP instructions have two address

pointers for simultaneous accessing of X, Y data memory. Only pointer addressing is possible with

DSP instructions; there is no immediate addressing. The address registers are divided into two; the

R4, R5 registers become the X memory address register (Ax), and the R6, R7 registers become the

Y memory address register (Ay). The following three types of addressing exist with X, Y data

transfer instructions.

1. Non-updated address registers: The Ax, Ay registers are address pointers. They are not

updated.

2. Add index registers: The Ax, Ay registers are address pointers. The Ix, Iy register values are

added to them, respectively, after the data transfer (post-update).

3. Increment address registers: The Ax, Ay registers are address pointers. The value +2 is added

to each of them after the data transfer (pos t-upda te).

Rev. 2.00, 03/05, page 59 of 884

Each of the address pointers has an index register. The R8 register becomes the index register (Ix)

of the X memory address register (Ax), and the R9 register becomes the index register (Iy) of the

Y memory address register (Ay).

The X, Y data transfer instructions are processed in word lengths. X, Y data memory is accessed

in 16 bits. This is why the increment processing adds 2 to the address registers. In order to

decrement, set –2 in the index register and designate add index register addressing. During X, Y

data addressing, only bits 1 to 15 of the address pointer are valid. Always write a 0 to bit 0 of the

address pointer and the index register during X, Y data addressing.

Figure 2.9 shows the X, Y data transfer addressing. When X memory and Y memory are accessed

using the X, Y bus, the upper word of Ax (R4 or R5) and Ay (R6 or R7) is ignored. The result of

@Ay+ and @Ay+Iy is stored in the lower word of Ay, and the upper word retains its original

value.

ALU AU*

R8[Ix] R4[Ax]

R5[Ax]

R9[Iy] R6[Ay]

R7[Ay]

+2 (INC) +2 (INC)

+0 (No update) +0 (No update)

Notes: All three addressing methods (increment, index register addition (Ix, Iy), and

no update) are post-updating methods. To decrement the address pointer, set

the index register to –2 or –4.

1. Adder added for DSP addressing.

Figure 2.9 X, Y Data Transfer Addressing

Rev. 2.00, 03/05, page 60 of 884

Single Data Addressing: Among the DSP instructions, the single data transfer instructions

(MOVS.W and MOVS.L) are used to either load data into DSP registers or to store it from them.

With these instructions, the registers R2 to R5 are used as address registers (As) for the single data

transfers.

The four following data addressing instructions exist for single data transfer instructions.

1. Non-updated address registers: The As registers are address pointers. They are not updated.

2. Add index registers: The As registers are address pointers. The Is register values are added to

them after the data transfer (post-update).

3. Increment address registers: The As registers are address pointers. The value +2 or +4 is added

after the data transfe r (post-upda te ).

4. Decrement add re ss reg i sters: The As regi sters ar e addr ess poi nt ers . The value –2 or –4 is added

(+2 or +4 is subtr acted ) befo re the data transfe r (pre-upda te ).

The address pointer (As) uses the R8 register as an index register (Is).

Figure 2.10 shows the single data transfer addressing.

ALU

R8[Is] R4[As]

R5[As]

+2/+4 (INC)

+0 (No update)

Note: There are four addressing methods (no update, index register addition (Is),

increment, and decrement). Index register addition and increment are

post-updating methods. Decrement is a pre-updating method.

R3[As]

R2[As]

–2/–4 (DEC)

31 0

MAB CAB

Figure 2.10 Single Data Transfer Addressing

Rev. 2.00, 03/05, page 61 of 884

Modulo Addressing: The chip has a modulo addressing mode, just as other DSPs do. Address

registers are updated in the same manner as with other modes. When the address pointer value

becomes the same as a previously established modulo end address, the address pointer becomes

the modulo start address.

Modulo addressing is valid only with X, Y data transfer instructions (MOVX.W, MOVY.W).

When the DMX bit of the SR register is set, the X address register enters modulo addressing

mode; when the DMY bit of the SR register is set, the Y address register does so. Modulo

addressing is valid only for either the X or the Y address register; it is not possible to make them

both modulo addressing mode at the same time. Therefore, do not simultaneously set the DMX

and DMY. If they happen to be set at the same time, only the DMY side is valid.

The MOD register is used to designate the start and end addresses of the modulo address area; it

stores the MS (modulo start) and ME (modulo end). An example of MOD register (MS, ME)

usage is indicated below.

MOV.L ModAddr,Rn; Rn=ModEnd, ModStart

LDC Rn,MOD; ME=ModEnd, MS=ModStart

ModAddr: .DATA.W mEnd; ModEnd

.DATA.W mStart; ModStart

ModStart: .DATA

ModEnd: .DATA

Designate the start and end addresses in MS and ME, and then set the DMX or DMY bit to 1. The

contents of the address register are compared with ME. If they match ME, the start address MS is

stored in the address register. The lower 16 bits of the address register are compared with ME. The

maximum modulo size is 64 kbytes. This is sufficient for X, Y data memory accesses. Figure 2.11

shows a block diagram of modulo addressing.

Rev. 2.00, 03/05, page 62 of 884

Instruction (MOVX/MOVY)

DMX

CONT

CMP

ALU AU

ABx ABy

R4[Ax] R6[Ay]

R5[Ax] R7[Ay]

R8[Ix] R9[Iy]

DMY

31 0 00

16 16

15 15 15

31 31

+0 +2

15 15

XAB YAB

Figure 2.11 Modulo Addressing

An example of modulo addressing is indicated below:

MS=H'E008; ME=H'E00C; R4=H'1000E008;

DMX=1; DMY=0; (sets modulo addressing for address register Ax (R4, R5))

The R4 register changes as follows due to the above settings.

R4: H'1000E008

Inc. R4: H'1000E00A

Inc. R4: H'1000E00C

Inc. R4: H'1000E008 (becomes the modulo start address because the modulo end

address occurred)

Data is placed so that the upper 16 bits of the mo dulo sta rt and end addres ses becom e iden tical .

This is so because the modulo start address replaces only the lower 15 bits of the address register,

excepting bit 0.

Note: When using add index with DSP data addressing, there are cases where the value is

exceeded without the address pointer matching the ME. In such cases, the address pointer

does not return to the modulo start address. Bit 0 is disregarded not only for modulo

addressing, but also during X, Y data addressing, so always write 0 to the 0 bits of the

address pointer, index register, MS, and ME.

Rev. 2.00, 03/05, page 63 of 884

DSP Addressing Operation: The DSP addressing operation in the item stage (EX) of the

pipeline, including modulo addressing, is indicated below.

if ( Operation is MOVX.W MOVY.W ) {

ABx=Ax; ABy=Ay;

/* memory access cycle uses ABx and ABy. The addresses to be used

have not been updated */

/* Ax is one of R4,5 */

if ( DMX==0 || DMX==1 && DMY==1 )} Ax=Ax+(+2 or R8[Ix} or +0);

/* Inc,Index,Not-Update */

else if (!not-update) Ax=modulo( Ax, (+2 or R8[Ix]) );

/* Ay is one of R6,7 */

if ( DMY==0 ) Ay=Ay+(+2 or R9[Iy] or +0; /* Inc,Index,Not-Update */

else if (! not-update) Ay=modulo( Ay, (+2 or R9[Iy]) );

}

else if ( Operation is MOVS.W or MOVS.L ) {

if ( Addressing is Nop, Inc, Add-index-reg ) {

MAB=As;

/* memory access cycle uses MAB. The address to be used has not

been updated */

/* As is one of R2–5 */

As=As+(+2 or +4 or R8[Is] or +0); /* Inc.Index,Not-Update */

else { /* Decrement, Pre-update */

/* As is one of R2–5 */

As=As+(–2 or –4);

MAB=As;

/* memory access cycle uses MAB. The address to be used has been

updated */

}

/* The value to be added to the address register depends on addressing

operations.

For example, (+2 or R8[Ix] or +0) means that

+2: if operation is increment

R8[Ix}: if operation is add-index-reg

+0: if operation is not-update

Rev. 2.00, 03/05, page 64 of 884

function modulo ( AddrReg, Index ) {

if ( AdrReg[15:0]==ME ) AdrReg[15:0]=MS;

else AdrReg=AdrReg+Index;

return AddrReg;

}

2.4.3 Instruc tion Forma ts for CPU Ins tru ctions

The instruction format of instructions executed by the CPU core and the meanings of the source

and destination operands are indicated below. The meaning of the operand depends on the

instruction code. The symbols are used as follows:

xxxx: Instruction code

mmmm: Sour ce regist e r

nnnn: Destination register

iiii: Immediate data

dddd: Displacement

Table 2.14 Instruc tion Forma ts for CPU Instru ct ions

Instruction Formats Source Operand Destination

Operand Example

0 format

xxxx xxxx xxxxxxxx

15 0

——NOP

—nnnn: Direct

n format

xxxx xxxx xxxxnnnn

15 0

Control register or

system register nnnn: Direct

Control register or

system register nnnn: Indirect pre-

decrement register STC.L SR,@-Rn

mmmm: Direct

system register LDC Rm,SRm format

xxxx

mmmm

xxxx xxxx

15 0

mmmm: Indirect post-

increment register Control register or

system register L DC.L @Rm+,SR

mmmm: Indirect

mmmm: PC relative

using Rm —BRAF Rm

Rev. 2.00, 03/05, page 65 of 884

Instruction Formats Source Operand Destination

Operand Example

nm for mat mmmm: Direct

mmmm: Direct

nnnn

xxxx xxxx

15 0

mmmm

mmmm: Indirect post-

increment register

(multiply/

accumulate)

nnnn: Indirect post-

increment register

(multiply/

accumulate)*

MACH, MACL MAC.W

@Rm+,@Rn+

mmmm: Indirect post-

increment register nnnn: Direct

mmmm: Direct

decrement register MOV.L Rm,@-Rn

mmmm: Direct

indexed register MOV.L

Rm,@(R0,Rn)

md format

xxxx dddd

15 0

mmmm

xxxx

mmmmdddd: indirect

displacement

R0 (Direct register) MOV.B

@(disp,Rm),R0

nd4 format

dddd

nnnn

xxxx

15 0

xxxx

R0 (Direct register) nnnndddd: Indirect

displacement

MOV.B

R0,@(disp,Rn)

mmmm: Direct

displacement

MOV.L

Rm,@(disp,Rn)

nmd for mat

nnnn

xxxx dddd

15 0

mmmm

mmmmdddd: Indirect

displacement

nnnn: Direct

@(disp,Rm),Rn

Rev. 2.00, 03/05, page 66 of 884

Instruction Formats Source Operand Destination

Operand Example

dddddddd: Indirect

GBR wi th

displacement

R0 (Direct register) MOV.L

@(disp,GBR),R0

d format

dddd

xxxx

15 0

xxxx dddd

R0(Direct register) dddddddd: Indirect

GBR wi th

displacement

MOV.L

R0,@(disp,GBR)

dddddddd: PC

relative with

displacement

R0 (Direct register) MOVA

@(disp,PC),R0

dddddddd: PC

relative —BF label

d12 format

dddd

xxxx

15 0

dddd dddd

dddddddddddd:

PC relative —BRA label

(label=disp+PC)

nd8 format

dddd

nnnn

xxxx

15 0

dddd

dddddddd: PC

relative with

displacement

nnnn: Direct

@(disp,PC),Rn

i format iiiiiiii:

Immediate Indirect index ed

GBR AND.B

#imm,@(R0,GBR)

iiiiiiii:

Immediate R0 (Direct register) AND #imm,R0

i i i i

xxxx

15 0

xxxx i i i i

iiiiiiii:

Immediate —TRAPA #imm

ni format

nnnn i i i i

xxxx

15 0

i i i i

iiiiiiii:

Immediate nnnn: Direct

Note: *In multiply/accumulate instructions, nnnn is the source register.

Rev. 2.00, 03/05, page 67 of 884

2.4.4 Instruc tion For mats for DS P Instru ct ions

New instructions have been added for digital signal processing. The new instructions are divided

into the two following types.

1. Memory and DSP register double, single data transfer instructions (16-bit length)

2. Parallel processing instructions processed by the DSP unit (32-bit length)

Figure 2.12 shows each of the instruction formats.

CPU core

instructions

0 0 0 0

1 1 1 0

Double data

transfer instructions

Single data

transfer instructions

Parallel processing

instructions B field

A field

1 1 1 1 0 0

1 1 1 1 0 1

1 1 1 1 1 0

031

1626 25

Figure 2.12 Instruction Formats for DSP Instructions

Double, Single Data Transfer Instructions: Table 2.15 indicates the data formats for double data

transfer instructions, and table 2.16 indicates the data formats for single data transfer instructions.

Rev. 2.00, 03/05, page 68 of 884

Table 2.15 Instruc tion Forma ts for Double Data Trans fers

Category Mnemonic 15 14 13 12 11 10 9 8

NOPX 1111000

MOVX.W @Ax,Dx

MOVX.W @Ax+,Dx

MOVX.W @Ax+Ix,Dx

X memo ry

data transfers

MOVX.W Da,@Ax

MOVX.W Da,@Ax+

MOVX.W Da,@Ax+Ix

NOPY 111100 0

MOVY.W @Ay,Dy

MOVY.W @Ay+,Dy

MOVY.W @Ay+Iy,Dy

Y memo ry

data transfers

MOVY.W Da,@Ay

MOVY.W Da,@Ay+

MOVY.W Da,@Ay+Iy

Category Mnemonic 76543210

NOPX 0000

MOVX.W @Ax,Dx

MOVX.W @Ax+,Dx

MOVX.W @Ax+Ix,Dx

Dx 0 0

X memo ry

data transfers

MOVX.W Da,@Ax

MOVX.W Da,@Ax+

MOVX.W Da,@Ax+Ix

Da 10

NOPY 00 00

MOVY.W @Ay,Dy

MOVY.W @Ay+,Dy

MOVY.W @Ay+Iy,Dy

Dy 0 0

Y memo ry

data transfers

MOVY.W Da,@Ay

MOVY.W Da,@Ay+

MOVY.W Da,@Ay+Iy

Da 1 0

Ax: 0=R4, 1=R5 Ay: 0=R6, 1=R7 Dx: 0=X0, 1=X1 Dy: 0=Y0, 1=Y1 Da: 0=A0, 1=A1

Rev. 2.00, 03/05, page 69 of 884

Table 2.16 Instructio n Forma ts for Single Data Transfe rs

Category Mnemonic 15 14 13 12 11 10 9 8

MOVS.W @–As,Ds

MOVS.W @As,Ds

MOVS.W @As+,Ds

MOVS.W @As+Is,Ds

111101 As

0: R4

1: R5

2: R2

MOVS.W Ds,@-As

MOVS.W Ds,@As

MOVS.W Ds,@As+

MOVS.W Ds,@As+Is

3: R3

MOVS.L @–As,Ds

MOVS.L @As,Ds

MOVS.L @As+,Ds

MOVS.L @As+Is,Ds

Single data

transfer

MOVS.L Ds,@-As

MOVS.L Ds,@As

MOVS.L Ds,@As+

MOVS.L Ds,@As+Is

Category Mnemonic 76543210

MOVS.W @–As,Ds

MOVS.W @As,Ds

MOVS.W @As+,Ds

MOVS.W @As+Is,Ds

Ds 0: (*)

1: (*)

2: (*)

3: (*)

MOVS.W Ds,@-As

MOVS.W Ds,@As

MOVS.W Ds,@As+

MOVS.W Ds,@As+Is

4: (*)

5: A1

6: (*)

7: A0

MOVS.L @–As,Ds

MOVS.L @As,Ds

MOVS.L @As+,Ds

MOVS.L @As+Is,Ds

8: X0

9: X1

A: Y0

B: Y1

Single data

transfer

MOVS.L Ds,@-As

MOVS.L Ds,@As

MOVS.L Ds,@As+

MOVS.L Ds,@As+Is

C: M0

D: A1G

E: M1

F: A0G

Note: *System reserved code

Rev. 2.00, 03/05, page 70 of 884

Parallel Processing Instructions: The parallel processing instructions allow for more efficient

execution of digital signal processing using the DSP unit. They are 32 bits in length, allowing

simultaneously in parallel four processes, ALU operations, multiplications or two data transfers.

The parallel processing instructions are divided into A fields and B fields. The A field defines data

transfer instructions; the B field defines ALU operation instructions and multiplication

instructions. These instructions can be defined independently, the processes can be independent,

and furthermore, they can be executed simultaneously in parallel. Table 2.17 indicates the A field

parallel data transfer instructions, and table 2.18 indicates the B field ALU operation instructions

and multiplication instructions. A fields instruction is the same as double data transfers in table

2.15.

Table 2.17 A Field Parallel Data Transfer Instructions

Category Mnemonic 31 30 29 28 27 26 25 24 23

NOPX 1111100 0

MOVX.W @Ax,Dx

MOVX.W @Ax+,Dx

MOVX.W @Ax+Ix,Dx

X memo ry

data

transfers

MOVX.W Da,@Ax

MOVX.W Da,@Ax+

MOVX.W Da,@Ax+Ix

NOPY 0

MOVY.W @Ay,Dy

MOVY.W @Ay+,Dy

MOVY.W @Ay+Iy,Dy

Y memo ry

data

transfers

MOVY.W Da,@Ay

MOVY.W Da,@Ay+

MOVY.W Da,@Ay+Iy

Rev. 2.00, 03/05, page 71 of 884

Category Mnemonic 22 21 20 19 18 17 16 15 to 0

NOPX 000

MOVX.W @Ax,Dx

MOVX.W @Ax+,Dx

MOVX.W @Ax+Ix,Dx

X memo ry

data

transfers

MOVX.W Da,@Ax

MOVX.W Da,@Ax+

MOVX.W Da,@Ax+Ix

1 0

B field

NOPY 00 00

MOVY.W @Ay,Dy

MOVY.W @Ay+,Dy

MOVY.W @Ay+Iy,Dy

Dy 0 0

Y memo ry

data

transfers

MOVY.W Da,@Ay

MOVY.W Da,@Ay+

MOVY.W Da,@Ay+Iy

Da 1 0

B field

Ax: 0=R4, 1=R5 Ay: 0=R6, 1=R7 Dx: 0=X0, 1=X1 Dy: 0=Y0, 1=Y1 Da: 0=A0, 1=A1

Rev. 2.00, 03/05, page 72 of 884

Table 2.18 B Field ALU Operation Instructions, Multiplication Instructions

Category Mnemonic 14 13 12 10 9 8 7 6 5 4 3 2 1 015 Dz000

000 –16 ≤ lmm ≤ +16

– 32 ≤ lmm ≤ +32

0Se Sf Sx SyDgDu

000

001

010

0011

1011

010 0 000 Dz

0: (*1)

1: (*1)

2: (*1)

3: (*1)

4: (*1)

5: A1

6: (*1)

7: A0

8: X0

9: X1

A: Y0

B: Y1

C: M0

D: (*1)

E: M1

F: (*1)

0010

0001

11 0011

10 01 11

1 0:X0

1:X1

2:Y0

3:A1

0:X0

1:X1

2:A0

3:A1

0:X00:Y0

1:Y1

2:X0

3:A1

0:Y0 0:M0 1:Y01:Y1 1:M1 2:A02:M0 2:A0 3:A13:M1 3:A1

010

PSHL #lmm, Dz

PSHA #lmm, Dz

PMULS Se, Sf, Dg

Reserved

PABS Sx, Dz

PRND Sx, Dz

PRND Sy, Dz

PABS Sy, Dz

Reserved

PSUBC Sx, Sy, Dz

PADDC Sx, Sy, Dz

PCMP Sx, Sy

PSUB Sx, Sy, Du

PMULS Se, Sf, Dg

PADD Sx, Sy, Du

PMULS Se, Sf, Dg

Imm. shift

Six

operand

parallel

instruction

Three

operand

instructions

31–27 25–1626

A field 11

Rev. 2.00, 03/05, page 73 of 884

Category Mnemonic 14 13 12 10 9 8 7 6 5 4 3 2 1 015

0000

10 01 11 0010

10 01 11 0001

10 01 11 0011

10 01 11 0001

10 01 11

001

if cc

0 * 00

10 01 11

Reserved

Reserved*

Reserved

(if cc) PSHL Sx, Sy, Dz

(if cc) PSHA Sx, Sy, Dz

(if cc) PSUB Sx, Sy, Dz

(if cc) PADD Sx, Sy, Dz

(if cc) PAND Sx, Sy, Dz

(if cc) PXOR Sx, Sy, Dz

(if cc) POR Sx, Sy, Dz

(if cc) PDEC Sx, Dz

(if cc) PDEC Sy, Dz

(if cc) PINC Sx, Dz

(if cc) PINC Sy, Dz

(if cc) PCLR Dz

(if cc) PDMSB Sx, Dz

(if cc) PDMSB Sy, Dz

(if cc) PNEG Sx, Dz

(if cc) PNEG Sy, Dz

(if cc) PCOPY Sx, Dz

(if cc) PCOPY Sy, Dz

(if cc) PSTS MACH, Dz

(if cc) PSTS MACL, Dz

(if cc) PLDS Dz, MACL

(if cc) PLDS Dz, MACH

Conditional

three

operand

instructions

if cc

10:DCT

11:DCF

01:

Uncon-

dition

31–27 25–1626

1 0 A field

Notes: 1. System reserved code

2. (if cc): DCT (DC bit true), DCF (DC bit false), or none (unconditional instruction)

2.5 Instruction Set

The instructions are divided into three groups: CPU instructions executed by the CPU core, DSP

data transfer instructions executed by the DSP unit, and DSP operation instructions. There are a

number of CPU instructions for supporting the DSP functions. The instruction set is explained

below in terms of each of the three groups.

Rev. 2.00, 03/05, page 74 of 884

2.5.1 CPU Instruction Set

Table 2.19 lists the CPU instructions by classification.

Table 2.19 Classification of CPU Instructions

Classification Types Operation

Code Function No. of

Instructions

Data transfer 5 MOV Data transfer, immediate data transfer, peripheral

module data transfer, structure data transfer 39

MOVA Effective address transfer

MOVT T bit transfer

SWAP Swap of upper and lower bytes

XTRCT Extraction of the middle of registers connected

21 ADD B inary addition 33Arithmetic

operations ADDC Binary addition with carry

ADDV Binary addition with overflow

CMP/cond Comparison

DIV1 Division

DIV0S Initialization of signed division

DIV0U Initialization of unsigned division

DMU LS Signed double- length m ultiplicatio n

DMULU Unsigned double-length multiplication

DT Decrement and test

EXTS Sign extension

EXTU Zero ex tension

MAC Multiply/accumulate, double-length

multiply/accumulate operation

MUL Double-length multiply operation

MULS Signed multiplication

MULU Unsigned multipli cation

NEG Negation

NEGC Negation with borrow

SUB Binary subtraction

SUBC Binary subtraction with borrow

SUBV Binary subtraction with underflow

Rev. 2.00, 03/05, page 75 of 884

Classification Types Operation

Code Function No. of

Instructions

6 AND Logical AND 14Logic

operations NOT B it in v er sion

OR Logical OR

TAS Memory test and bit set

TST Logical AND and T bit set

XOR Exclusive OR

Shift 10 ROTCL One-bit left rotation with T bit 14

ROTCR One-bit right rotation with T bit

ROTL One-bit left rotation

ROTR One-bit right rotation

SHAL One-bit arithmetic left shift

SHAR One-bit arithmetic right shift

SHLL One-bit logical left shift

SH L L n n-bit log ic al lef t shift

SHLR One-bit logical right shift

SH L R n n -bit logica l right shift

Branch 9 BF Conditional branch, conditional branch with delay

(Branch when T = 0) 11

BT Conditional branch, conditional branch with delay

(Branch when T = 1)

BRA Unconditional branch

BRAF Unconditional branch

BSR Branch to subroutine procedure

BSRF Branch to subroutine procedure

JMP Unconditi onal branch

JSR Branch to subroutine procedure

RTS Return from subroutine procedure

Rev. 2.00, 03/05, page 76 of 884

Classification Types Operation

Code Function No. of

Instructions

14 CLRMAC MAC register clear 71System

control CLRT T bit clear

LDC Load to control register

LDRE Load to repeat end register

LDRS Load to repeat start register

LDS Load to system register

NOP No operation

RTE Return from exception processing

SETRC Repeat count setting

SETT T bit set

SLEEP Shift into power-down mode

STC Storing control register data

STS Stori ng system register data

TRAP A Trap exception handling

Total:65 182

Rev. 2.00, 03/05, page 77 of 884

The instru ction code s, oper ation, and exe cution states of the CPU in struc tions ar e listed by

classification with the formats listed in below.

Instruction Instruction Code Operation Execution

Cycles T Bit

Indicated by mnemonic

Explanation of Symbols

OP.Sz SRC, DEST

OP: Operation code

Sz: Size

SRC: Source

DEST: Destination

Rm: Source register

Rn: Destination register

imm: Im mediate data

disp : Dis p l acemen t*2

Indicated in MSB ↔

LSB order

Explanation of Symbols

mmmm: Source register

nnnn: Destination register

0000: R0

0001: R1

.........

1111: R15

iiii: Immediate data

dddd: Displacement

Indicat es summary of

operation

Explanation of Symbols

→, ←: Tr a nsfer dire ctio n

(xx): Memory opera nd

M/Q/T: Flag bits in the SR

&: Log i cal AN D of eac h bi t

|: Log i cal OR of each bi t

^: Exclus i ve OR of ea c h b it

~: Logical NOT of each bit

<<n: n-bit left shift

>>n: n-bit right shift

V alue when

no wait

states are

inserted*1

Val u e of T bit

after

instruction is

executed

Ex pl anation of

Symbols

—: No chan ge

Notes: 1. Instr u ction execution cycles: The execution cycles shown in the table are minimums.

The actual number of cycles may be increased when (1) contention occurs between

instruction fetches and data access, or (2) when the destination register of the load

instruction (mem ory → register) and the register used by the next instruction are the

same.

2. Depending on the instruction’s operand size, scaling is ×1, ×2, or ×4. For details, see

the SH-1/SH-2/SH-DSP Programming Manual.

Rev. 2.00, 03/05, page 78 of 884

Table 2.20 Data Transfer Ins truc tions

Instruction Instruction Code Operation Cycles T Bit

MOV #imm,Rn 1110nnnniiiiiiii imm → Sign extension → Rn1 —

MOV.W @(disp,PC),Rn 1001nnnndddddddd (disp × 2 + PC) → Sign

extension → Rn 1 —

MOV.L @(disp,PC),Rn 1101nnnndddddddd (disp × 4 + PC) → Rn 1 —

MOV Rm,Rn 0110nnnnmmmm0011 Rm → Rn 1 —

MOV.B Rm,@Rn 0010nnnnmmmm0000 Rm → (Rn) 1 —

MOV.W Rm,@Rn 0010nnnnmmmm0001 Rm → (Rn) 1 —

MOV.L Rm,@Rn 0010nnnnmmmm0010 Rm → (Rn) 1 —

MOV.B @Rm,Rn 0110nnnnmmmm0000 (Rm) → Sign extension →

Rn 1 —

MOV.W @Rm,Rn 0110nnnnmmmm0001 (Rm) → Sign extension →

Rn 1 —

MOV.L @Rm,Rn 0110nnnnmmmm0010 (Rm) → Rn 1 —

MOV.B Rm,@–Rn 0010nnnnmmmm0100 Rn–1 → Rn, Rm → (Rn) 1 —

MOV.W Rm,@–Rn 0010nnnnmmmm0101 Rn–2 → Rn, Rm → (Rn) 1 —

MOV.L Rm,@–Rn 0010nnnnmmmm0110 Rn–4 → Rn, Rm → (Rn) 1 —

MOV.B @Rm+,Rn 0110nnnnmmmm0100 (Rm) → Sign extension →

Rn,Rm + 1 → Rm 1 —

MOV.W @Rm+,Rn 0110nnnnmmmm0101 (Rm) → Sign extension →

Rn,Rm + 2 → Rm 1 —

MOV.L @Rm+,Rn 0110nnnnmmmm0110 (Rm) → Rn,Rm + 4 → Rm 1 —

MOV.B R0,@(disp,Rn) 10000000nnnndddd R0 → (disp + Rn) 1 —

MOV.W R0,@(disp,Rn) 10000001nnnndddd R0 → (disp × 2 + Rn) 1 —

MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd Rm → (disp × 4 + Rn) 1 —

MOV.B @(disp,Rm),R0 10000100mmmmdddd (disp + Rm) → Sign

extension → R0 1 —

MOV.W @(disp,Rm),R0 10000101mmmmdddd (disp × 2 + Rm) → Sign

extension → R0 1 —

MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd (disp × 4 + Rm) → Rn 1 —

MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 Rm → (R0 + Rn) 1 —

MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm → (R0 + Rn) 1 —

MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm → (R0 + Rn) 1 —

MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 (R0 + Rm) → Sign

extension → Rn 1 —

MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm) → Sign

extension → Rn 1 —

Rev. 2.00, 03/05, page 79 of 884

Instruction Instruction Code Operation Cycles T Bit

MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm) → Rn 1 —

MOV.B R0,@(disp,GBR) 11000000dddddddd R0 → (di sp + GBR) 1 —

MOV.W R0,@(disp,GBR) 11000001dddddddd R0 → (disp × 2 + GBR) 1 —

MOV.L R0,@(disp,GBR) 11000010dddddddd R0 → (disp × 4 + GBR) 1 —

MOV.B @(disp,GBR),R0 11000100dddddddd (disp + GBR) → Sign

extension → R0 1 —

MOV.W @(disp,GBR),R0 11000101dddddddd (disp × 2 + GBR) → Sign

extension → R0 1 —

MOV.L @(disp,GBR),R0 11000110dddddddd (disp × 4 + GBR) → R0 1 —

MOVA @(disp,PC),R0 11000111dddddddd disp × 4 + PC → R0 1 —

MOVT Rn 0000nnnn00101001 T → Rn 1 —

SWAP.B Rm,Rn 0110nnnnmmmm1000 Rm → Swap the bottom

two bytes → Rn 1 —

SWAP.W Rm,Rn 0110nnnnmmmm1001 Rm → Swap upper and

lower word s → Rn 1 —

XTRCT Rm,Rn 0010nnnnmmmm1101 Rm: Middle 32 bits of Rn →

Rn 1 —

Rev. 2.00, 03/05, page 80 of 884

Table 2.21 Arithmet ic Instruc tions

Instruction Instruction Code Operation Cycles T Bit

ADD Rm,Rn 0011nnnnmmmm1100 Rn + Rm → Rn 1 —

ADD #imm,Rn 0111nnnniiiiiiii Rn + imm → Rn 1 —

ADDC Rm,Rn 0011nnnnmmmm1110 Rn + Rm + T → Rn,

Carry → T 1 Carry

ADDV Rm,Rn 0011nnnnmmmm1111 Rn + Rm → Rn,

Overflow → T 1 Overflow

CMP/EQ #imm,R0 10001000iiiiiiii If R0 = imm, 1 → T 1 Comparison

result

CMP/EQ Rm,Rn 0011nnnnmmmm0000 If Rn = Rm, 1 → T1 Comparison

result

CMP/HS Rm,Rn 0011nnnnmmmm0010 If Rn ≥ Rm with unsigned

data, 1 → T 1Comparison

result

CMP/GE Rm,Rn 0011nnnnmmmm0011 If Rn ≥ Rm with signed

data, 1 → T 1 Comparison

result

CMP/HI Rm,Rn 0011nnnnmmmm0110 If Rn > Rm with unsigned

data, 1 → T 1 Comparison

result

CMP/GT Rm,Rn 0011nnnnmmmm0111 If Rn > Rm with signed

data, 1 → T 1 Comparison

result

CMP/PL Rn 0100nnnn00010101 If Rn > 0, 1 → T 1 Comparison

result

CMP/PZ Rn 0100nnnn00010001 If Rn ≥ 0, 1 → T1Comparison

result

CMP/STR Rm,Rn 0010nnnnmmmm1100 If Rn and Rm contain

an identical byte,

1 → T

1Comparison

result

DIV1 Rm,Rn 0011nnnnmmmm0100 Single-step division

(Rn/Rm) 1Calculation

result

DIV0S Rm,Rn 0010nnnnmmmm0111 MSB of Rn → Q, MSB

of Rm → M, M ^ Q → T 1Calculation

result

DIV0U 0000000000011001 0 → M/Q/T 1 0

DMULS.L Rm,Rn 0011nnnnmmmm1101 Signed operation of Rn ×

Rm → MACH, M ACL

32 × 32 → 64 bits

2 to 4*—

DMULU.L Rm,Rn 0011nnnnmmmm0101 Unsigned operation of

Rn × Rm → MACH,

MACL 32 × 32 →

64 bits

2 to 4*—

Rev. 2.00, 03/05, page 81 of 884

Instruction Instruction Code Operation Cycles T Bit

DT Rn 0100nnnn00010000 Rn – 1 → Rn, when Rn

is 0, 1 → T

When Rn is nonzero,

0 → T

1 Comparison

result

EXTS.B Rm,Rn 0110nnnnmmmm1110 A byte in Rm is sign-

extended → Rn 1 —

EXTS.W Rm,Rn 0110nnnnmmmm1111 A word in Rm is sign-

extended → Rn 1 —

EXTU.B Rm,Rn 0110nnnnmmmm1100 A byte in Rm i s zero-

extended → Rn 1 —

EXTU.W Rm,Rn 0110nnnnmmmm1101 A word in Rm is zero-

extended → Rn 1 —

MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 Signed operation of

(Rn) × (Rm) + MAC →

MAC 32 × 32 + 64 →

64 bits

3/(2 to 4)*—

MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of

(Rn) × (Rm) + MAC →

MAC 16 × 16 + 64 →

64 bits

3/(2)*—

MUL.L Rm,Rn 0000nnnnmmmm0111 Rn × Rm → MACL,

32 × 32 → 32 bits 2 to 4*—

MULS.W Rm,Rn 0010nnnnmmmm1111 Signed operation of

Rn × Rm → MAC 16 ×

16 → 32 bi ts

1 to 3*—

MULU.W Rm,Rn 0010nnnnmmmm1110 Unsigned operation of

Rn × Rm → MAC 16 ×

16 → 32 bi ts

1 to 3*—

NEG Rm,Rn 0110nnnnmmmm1011 0–Rm → Rn 1 —

NEGC Rm,Rn 0110nnnnmmmm1010 0–Rm–T → Rn,

Borrow → T 1 Borrow

SUB Rm,Rn 0011nnnnmmmm1000 Rn–Rm → Rn 1 —

SUBC Rm,Rn 0011nnnnmmmm1010 Rn–Rm–T → Rn,

Borrow → T 1 Borrow

SUBV Rm,Rn 0011nnnnmmmm1011 Rn–Rm → Rn,

Underflow → T 1 Underflow

Note: *The normal number of execution cycles. The number in parentheses is the number of

execution cycles in the case of contention with preceding or following instructions.

Rev. 2.00, 03/05, page 82 of 884

Table 2.22 Logic Opera tion In struct ion s

Instruction Instruction Code Operation Cycles T Bit

AND Rm,Rn 0010nnnnmmmm1001 Rn & R m → Rn 1 —

AND #imm,R0 11001001iiiiiiii R0 & imm → R0 1 —

AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm →

(R0 + GBR) 3 —

NOT Rm,Rn 0110nnnnmmmm0111 ~Rm → Rn 1 —

OR Rm,Rn 0010nnnnmmmm1011 Rn | Rm → Rn 1 —

OR #imm,R0 11001011iiiiiiii R0 | imm → R0 1 —

OR.B #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm →

(R0 + GBR) 3 —

TAS.B @Rn 0100nnnn00011011 If (Rn) is 0, 1 → T,

1 → MSB of (Rn) 4Test

result

TST Rm,Rn 0010nnnnmmmm1000 Rn & Rm, if the result

is 0, 1 → T 1Test

result

TST #imm,R0 11001000iiiiiiii R0 & imm, if the result

is 0, 1 → T 1Test

result

TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm,

if the result is 0, 1 → T 3Test

result

XOR Rm,Rn 0010nnnnmmmm1010 Rn ^ Rm → Rn 1 —

XOR #imm,R0 11001010iiiiiiii R0 ^ imm → R0 1 —

XOR.B #imm,@(R0,GBR) 11001110iiiiiiii (R0 + GBR) ^ imm →

(R0 + GBR) 3 —

Rev. 2.00, 03/05, page 83 of 884

Table 2.23 Shift Instruc tions

Instruction Instruction Code Operation Cycles T Bit

ROTL Rn 0100nnnn00000100 T ← Rn ← MSB 1 MSB

ROTR Rn 0100nnnn00000101 LSB → Rn → T1LSB

ROTCL Rn 0100nnnn00100100 T ← Rn ← T1MSB

ROTCR Rn 0100nnnn00100101 T → Rn → T1LSB

SHAL Rn 0100nnnn00100000 T ← Rn ← 01MSB

SHAR Rn 0100nnnn00100001 MSB → Rn → T1LSB

SHLL Rn 0100nnnn00000000 T ← Rn ← 01MSB

SHLR Rn 0100nnnn00000001 0 → Rn → T1LSB

SHLL2 Rn 0100nnnn00001000 Rn<<2 → Rn 1 —

SHLR2 Rn 0100nnnn00001001 Rn>>2 → Rn 1 —

SHLL8 Rn 0100nnnn00011000 Rn<<8 → Rn 1 —

SHLR8 Rn 0100nnnn00011001 Rn>>8 → Rn 1 —

SHLL16 Rn 0100nnnn00101000 Rn<<16 → Rn 1 —

SHLR16 Rn 0100nnnn00101001 Rn>>16 → Rn 1 —

Rev. 2.00, 03/05, page 84 of 884

Table 2.24 Branch Instructions

Instruction Instruction Code Operation Cycles T Bit

BF label 10001011dddddddd If T = 0, disp × 2 + PC → PC,

if T = 1, nop 3/1*—

BF/S label 10001111dddddddd Delayed branch, if T = 0,

disp × 2 + PC → PC, i f T = 1, nop 2/1*—

BT label 10001001dddddddd If T = 1, disp × 2 + PC → PC,

if T = 0, nop 3/1*—

BT/S label 10001101dddddddd Delayed branch,

if T = 1, disp × 2 + PC → PC,

if T = 0, nop

2/1*—

BRA label 1010dddddddddddd Delayed branch,

disp × 2 + PC → PC 2 —

BRAF Rm 0000mmmm00100011 Delayed branch, Rm + PC → PC 2 —

BSR label 1011dddddddddddd Delayed branch, PC → PR,

disp × 2 + PC → PC 2 —

BSRF Rm 0000mmmm00000011 Delayed branch,

PC → PR, R m + PC → PC 2 —

JMP @Rm 0100mmmm00101011 Delayed branch, Rm → PC 2 —

JSR @Rm 0100mmmm00001011 Delayed branch,

PC → PR, Rm → PC 2 —

RTS 0000000000001011 Delayed branch, PR → PC 2 —

Note: *One state when it does not branch.

Rev. 2.00, 03/05, page 85 of 884

Table 2.25 System Control Instru ct ions

Instruction Instruction Code Operation Cycles T Bit

CLRMAC 0000000000101000 0 → MACH, MACL 1 —

CLRT 0000000000001000 0 → T10

LDC Rm,SR 0100mmmm00001110 Rm → SR 1 LSB

LDC Rm,GBR 0100mmmm00011110 Rm → GBR 1 —

LDC Rm,VBR 0100mmmm00101110 Rm → VBR 1 —

LDC Rm,MOD 0100mmmm01011110 Rm → MOD 1 —

LDC Rm,RE 0100mmmm01111110 Rm → RE 1 —

LDC Rm,RS 0100mmmm01101110 Rm → RS 1 —

LDC.L @Rm+,SR 0100mmmm00000111 (Rm) → SR, Rm + 4 → Rm 3 LSB

LDC.L @Rm+,GBR 0100mmmm00010111 (Rm) → GBR, Rm + 4 → Rm 3 —

LDC.L @Rm+,VBR 0100mmmm00100111 (Rm) → VBR, Rm + 4 → Rm 3 —

LDC.L @Rm+,MOD 0100mmmm01010111 (Rm) → MOD, Rm + 4 → Rm 3 —

LDC.L @Rm+,RE 0100mmmm01110111 (Rm) → RE, Rm + 4 → Rm 3 —

LDC.L @Rm+,RS 0100mmmm01100111 (Rm) → RS, Rm + 4 → Rm 3 —

LDRE @(disp,PC) 10001110dddddddd disp × 2 + PC → RE 1 —

LDRS @(disp,PC) 10001100dddddddd disp × 2 + PC → RS 1 —

LDS Rm,MACH 0100mmmm00001010 Rm → MACH 1 —

LDS Rm,MACL 0100mmmm00011010 Rm → MACL 1 —

LDS Rm,PR 0100mmmm00101010 Rm → PR 1 —

LDS Rm,DSR 0100mmmm01101010 Rm → DSR 1 —

LDS Rm,A0 0100mmmm01111010 Rm → A0 1 —

LDS Rm,X0 0100mmmm10001010 Rm → X0 1 —

LDS Rm,X1 0100mmmm10011010 Rm → X1 1 —

LDS Rm,Y0 0100mmmm10101010 Rm → Y0 1 —

LDS Rm,Y1 0100mmmm10111010 Rm → Y1 1 —

LDS.L @Rm+,MACH 0100mmmm00000110 (Rm) → MACH,

Rm + 4 → Rm 1 —

LDS.L @Rm+,MACL 0100mmmm00010110 (Rm) → MACL ,

Rm + 4 → Rm 1 —

LDS.L @Rm+,PR 0100mmmm00100110 (Rm) → PR, Rm + 4 → Rm 1 —

LDS.L @Rm+,DSR 0100mmmm01100110 (Rm) → DSR, Rm + 4 → Rm 1 —

LDS.L @Rm+,A0 0100mmmm01110110 (Rm) → A0, Rm + 4 → Rm 1 —

LDS.L @Rm+,X0 0100mmmm10000110 (Rm) → X0, Rm + 4 → Rm 1 —

Rev. 2.00, 03/05, page 86 of 884

Instruction Instruction Code Operation Cycles T Bit

LDS.L @Rm+,X1 0100mmmm10010110 (Rm) → X1, Rm + 4 → Rm 1 —

LDS.L @Rm+,Y0 0100mmmm10100110 (Rm) → Y0, Rm + 4 → Rm 1 —

LDS.L @Rm+,Y1 0100mmmm10110110 (Rm) → Y1, Rm + 4 → Rm 1 —

NOP 0000000000001001 No operation 1 —

RTE 0000000000101011 Delayed branch,

stack area → PC/SR 4LSB

SETRC Rm 0100mmmm00010100 RE–RS operation result

(repeat status) → RF1, RF0

Rm[11:0] → RC (SR[27:16])

1 —

SETRC #imm 10000010iiiiiiii RE–RS operation result

(repeat status) → RF1, RF0

imm → RC (SR[23:16]),

0 → SR[27:24]

SETT 0000000000011000 1 → T11

SLEEP 0000000000011011 Sleep 3*—

STC SR,Rn 0000nnnn00000010 SR → Rn 1 —

STC GBR,Rn 0000nnnn00010010 GBR → Rn 1 —

STC VBR,Rn 0000nnnn00100010 VBR → Rn 1 —

STC MOD,Rn 0000nnnn01010010 MOD → Rn 1 —

STC RE,Rn 0000nnnn01110010 RE → Rn 1 —

STC RS,Rn 0000nnnn01100010 RS → Rn 1 —

STC.L SR,@–Rn 0100nnnn00000011 Rn–4 → Rn, SR → (Rn) 2 —

STC.L GBR,@–Rn 0100nnnn00010011 Rn–4 → Rn, GBR → (Rn) 2 —

STC.L VBR,@–Rn 0100nnnn00100011 Rn–4 → Rn, VBR → (Rn) 2 —

STC.L MOD,@–Rn 0100nnnn01010011 Rn–4 → Rn, MOD → (Rn) 2 —

STC.L RE,@–Rn 0100nnnn01110011 Rn–4 → Rn, RE → (Rn) 2 —

STC.L RS,@–Rn 0100nnnn01100011 Rn–4 → Rn, RS → (Rn) 2 —

STS MACH,Rn 0000nnnn00001010 MACH → Rn 1 —

STS MACL,Rn 0000nnnn00011010 MACL → Rn 1 —

STS PR,Rn 0000nnnn00101010 PR → Rn 1 —

STS DSR,Rn 0000nnnn01101010 DSR → Rn 1 —

STS A0,Rn 0000nnnn01111010 A0 → Rn 1 —

STS X0,Rn 0000nnnn10001010 X0 → Rn 1 —

STS X1,Rn 0000nnnn10011010 X1 → Rn 1 —

STS Y0,Rn 0000nnnn10101010 Y0 → Rn 1 —

STS Y1,Rn 0000nnnn10111010 Y1 → Rn 1 —

Rev. 2.00, 03/05, page 87 of 884

Instruction Instruction Code Operation Cycles T Bit

STS.L MACH,@–Rn 0100nnnn00000010 Rn–4 → Rn, MACH → (Rn) 1 —

STS.L MACL,@–Rn 0100nnnn00010010 Rn–4 → Rn, MACL → (Rn) 1 —

STS.L PR,@–Rn 0100nnnn00100010 Rn–4 → Rn, PR → (Rn) 1 —

STS.L DSR,@–Rn 0100nnnn01100010 Rn–4 → Rn, DSR → (Rn) 1 —

STS.L A0,@–Rn 0100nnnn01110010 Rn–4 → Rn, A0 → (Rn) 1 —

STS.L X0,@–Rn 0100nnnn10000010 Rn–4 → Rn, X0 → (Rn) 1 —

STS.L X1,@–Rn 0100nnnn10010010 Rn–4 → Rn, X1 → (Rn) 1 —

STS.L Y0,@–Rn 0100nnnn10100010 Rn–4 → Rn, Y0 → (Rn) 1 —

STS.L Y1,@–Rn 0100nnnn10110010 Rn–4 → Rn, Y1 → (Rn) 1 —

TRAPA #imm 11000011iiiiiiii PC/SR → stack area, (imm × 4

+ VBR) → PC 8 —

Note: *The number of execution cycles before the chip enters sleep mode.

Precautions Concerning the Number of Instruction Execution Cycles: The execution cycles

listed in the tables are minimum values. In practice, the number of execution cycles increases

under such conditions as 1) when the instruction fetch is in contention with a data access, 2) when

the destination register of a load instruction (memory → register) is the same as the register used

by the next instruction, 3) when the branch destination address of a branch instruction is a 4n + 2

address.

CPU Instructions That Support DSP Functions: A number of system control instructions have

been added to the CPU core instructions to support DSP functions. The RS, RE and MOD

registers have been added to support repeat control and modulo addressing, and the repeat counter

(RC) has been added to the status register (SR). The LDC and STC instructions have been added

in order to access the aforementioned. The LDS and STS instructions have been added in order to

access the DSP registers DSR, A0, X0, X1, Y0 and Y1.

The SETRC instruction has been added to set the repeat counter (RC, bits 27 to 16) and repeat

flags (RF1, RF0, bits 3 and 2) of the SR register. When the SETRC instruction operand is

immediate, the 8-bit immediate data is stored in bits 23 to 16 of the SR register and bits 27 to 24

are cleared to 0. When the operand is a register, bits 11 to 0 (12 bits) of the register are stored in

bits 27 to 16 of the SR register. Additionally, the status of 1 instruction repeat (00), 2 instruction

repeat (01), 3 instruction repeat (11) or 4 instruction or greater repeat (10) is set from the RS and

RE set values.

In addition to the LDC instruction, the LDRS and LDRE instructions have been added for

establishing the repeat start and repeat end addresses in the RS and RE registers.

The added instructions are listed in table 2.26.

Rev. 2.00, 03/05, page 88 of 884

Table 2.26 Added CPU Instructions

Instruction Code Operation Cycles T Bit

LDC Rm,MOD 0100mmmm01011110 Rm→MOD 1 —

LDC Rm,RE 0100mmmm01111110 Rm→RE 1 —

LDC Rm,RS 0100mmmm01101110 Rm→RS 1 —

LDC.L @Rm+,MOD 0100mmmm01010111 (Rm)→MOD,Rm+4→Rm 3 —

LDC.L @Rm+,RE 0100mmmm01110111 (Rm)→RE,Rm+4→Rm 3 —

LDC.L @Rm+,RS 0100mmmm01100111 (Rm)→RS,Rm+4→Rm 3 —

STC MOD,Rn 0000nnnn01010010 MOD→Rn 1 —

STC RE,Rn 0000nnnn01110010 RE→Rn 1 —

STC RS,Rn 0000nnnn01100010 RS→Rn 1 —

STC.L MOD,@-Rn 0100nnnn01010011 Rn–4→Rn,MOD→(Rn) 2 —

STC.L RE,@-Rn 0100nnnn01110011 Rn–4→Rn,RE→(Rn) 2 —

STC.L RS,@-Rn 0100nnnn01100011 Rn–4→Rn,RS→(Rn) 2 —

LDS Rm,DSR 0100mmmm01101010 Rm→DSR 1 —

LDS.L @Rm+,DSR 0100mmmm01100110 (Rm)→DSR,Rm+4→Rm 1 —

LDS Rm,A0 0100mmmm01111010 Rm→A0 1 —

LDS.L @Rm+,A0 0100mmmm01110110 (Rm)→A0,Rm+4→Rm 1 —

LDS Rm,X0 0100mmmm10001010 Rm→X0 1 —

LDS.L @Rm+,X0 0100mmmm10000110 (Rm)→X0,Rm+4→Rm 1 —

LDS Rm,X1 0100mmmm10011010 Rm→X1 1 —

LDS.L @Rm+,X1 0100mmmm10010110 (Rm)→X1,Rm+4→Rm 1 —

LDS Rm,Y0 0100mmmm10101010 Rm→Y0 1 —

LDS.L @Rm+,Y0 0100mmmm10100110 (Rm)→Y0,Rm+4→Rm 1 —

LDS Rm,Y1 0100mmmm10111010 Rm→Y1 1 —

LDS.L @Rm+,Y1 0100mmmm10110110 (Rm)→Y1,Rm+4→Rm 1 —

STS DSR,Rn 0000nnnn01101010 DSR→Rn 1 —

STS.L DSR,@-Rn 0100nnnn01100010 Rn–4→Rn,DSR→(Rn) 1 —

STS A0,Rn 0000nnnn01111010 A0→Rn 1 —

STS.L A0,@-Rn 0100nnnn01110010 Rn–4→Rn,A0→(Rn) 1 —

STS X0,Rn 0000nnnn10001010 X0→Rn 1 —

STS.L X0,@-Rn 0100nnnn10000010 Rn–4→Rn,X0→(Rn) 1 —

STS X1,Rn 0000nnnn10011010 X1→Rn 1 —

Rev. 2.00, 03/05, page 89 of 884

Instruction Code Operation Cycles T Bit

STS.L X1,@-Rn 0100nnnn10010010 Rn–4→Rn,X1→(Rn) 1 —

STS Y0,Rn 0000nnnn10101010 Y0→Rn 1 —

STS.L Y0,@-Rn 0100nnnn10100010 Rn–4→Rn,Y0→(Rn) 1 —

STS Y1,Rn 0000nnnn10111010 Y1→Rn 1 —

STS.L Y1,@-Rn 0100nnnn10110010 Rn–4→Rn,Y1→(Rn) 1 —

SETRC Rm 0100mmmm00010100 Rm[11:0]→RC (SR[27:16]) 1 —

SETRC #imm 10000010iiiiiiii imm→RC(SR[23:16]),

0→SR[27:24] 1 —

LDRS @(disp,PC) 10001100dddddddd disp × 2+PC→RS 1 —

LDRE @(disp,PC) 10001110dddddddd disp × 2+PC→RE 1 —

2.5.2 DSP Data Transfer Instruction Set

Table 2.27 lists the DSP data transfer instructions by classification.

Table 2.27 Classification of DSP Data Transfer Instructions

Classification Types Operation

Code Function No. of

Instructions

4 NOPX X memory no operation 14

MOVX X memory data transfer

Double data

transfer

instructions NOPY Y memory no operation

MOVY Y memory data transfer

Single data

transfer

instructions

1 MOVS Single data transfer 16

Total: 5 Total: 30

The data transfer instructions are divided into two groups, double data transfers and single data

transfers. Double data transfers can be combined with DSP operation instructions to perform DSP

parallel processing. The parallel processing instructions are 32 bits in length, and the double data

transfer instructions are incorporated into their A fields. Double data transfers that are not parallel

processing instructions are 16 bits in length, as are the single data transfer instructions.

The X memory and Y memory can be accessed simultaneously in parallel in double data transfers.

One instruction each is designated from among the X and Y memory data accesses. The Ax

pointer is used to access X memory; the Ay pointer is used to access Y memory. Double data

transfers can only access X, Y memory.

Rev. 2.00, 03/05, page 90 of 884

Single data transfers can be accessed from any area. Single data transfers use the Ax pointer and

two other pointers as an As pointer.

Table 2.28 Double Data Transfer Instructions (X Memory Data)

Instruction Operation Code Cycles DC Bit

NOPX No Operation 1111000*0*0*00** 1 —

MOVX.W @Ax,Dx (Ax)→MSW of Dx,0→LSW of Dx 111100A*D*0*01** 1 —

MOVX.W @Ax+,Dx (Ax)→MSW of Dx,0→LSW of Dx,

Ax+2→Ax 111100A*D*0*10** 1 —

MOVX.W @Ax+Ix,Dx (Ax)→MSW of Dx,0→LSW of Dx,

Ax+Ix→Ax 111100A*D*0*11** 1 —

MOVX.W Da,@Ax MSW of D a→(Ax) 111100A*D*1*01** 1 —

MOVX.W Da,@Ax+ MSW of Da →(Ax),Ax+2→Ax 111100A*D*1*10** 1 —

MOVX.W Da,@Ax+Ix MSW of Da→(Ax),Ax+Ix→Ax 111100A*D*1*11** 1 —

Table 2.29 Double Data Transfer Instructions (Y Memory Data)

Instruction Operation Code Cycles DC Bit

NOPY No Operation 111100*0*0*0**00 1 —

MOVY.W @Ay,Dy (Ay)→MSW of Dy,0→LSW of Dy 111100*A*D*0**01 1 —

MOVY.W @Ay+,Dy (Ay)→MSW of Dy,0→LSW of Dy,

Ay+2→Ay 111100*A*D*0**10 1 —

MOVY.W @Ay+Iy,Dy (Ay)→MSW of Dy,0→LSW of Dy,

Ay+Iy→Ay 111100*A*D*0**11 1 —

MOVY.W Da,@Ay MSW of D a→(Ay) 111100*A*D*1**01 1 —

MOVY.W Da,@Ay+ MSW of Da →(Ay),Ay+2→Ay 111100*A*D*1**10 1 —

MOVY.W Da,@Ay+Iy MSW of Da→(Ay),Ay+Iy→Ay 111100*A*D*1**11 1 —

Rev. 2.00, 03/05, page 91 of 884

Table 2.30 Single Data Transfer Instructions

Instruction Operation Code Cycles DC Bit

MOVS.W @-As,Ds As–2→As,(As)→MSW of

Ds,0→LSW of Ds 111101AADDDD0000 1 —

MOVS.W @As,Ds (As)→MSW of Ds,0→LSW of

Ds 111101AADDDD0100 1 —

MOVS.W @As+,Ds (As)→MSW of Ds,0→LSW of

Ds, As+2→As 111101AADDDD1000 1 —

MOVS.W @As+Ix,Ds (As)→MSW of Ds,0→LSW of

Ds, As+Ix→As 111101AADDDD1100 1 —

MOVS.W Ds,@-As As–2→As,MSW of Ds→(As)*111101AADDDD0001 1 —

MOVS.W Ds,@As MSW of Ds→(As)*111101AADDDD0101 1 —

MOVS.W Ds,@As+ MSW of Ds→(As)*,As+2→As 111101AADDDD1001 1 —

MOVS.W Ds,@As+Is MSW of Ds→(As)*,As+Is→As 111101AADDDD1101 1 —

MOVS.L @-As,Ds As–4→As,(As)→Ds 111101AADDDD0010 1 —

MOVS.L @As,Ds (As)→Ds 111101AADDDD0110 1 —

MOVS.L @As+,Ds (As)→Ds,As+4→As 111101AADDDD1010 1 —

MOVS.L @As+Is,Ds (As)→Ds,As+Is→As 111101AADDDD1110 1 —

MOVS.L Ds,@-As As–4→As,Ds→(As)*111101AADDDD0011 1 —

MOVS.L Ds,@As Ds→(As)*111101AADDDD0111 1 —

MOVS.L Ds,@As+ Ds→(As)*,As+4→As 111101AADDDD1011 1 —

MOVS.L Ds,@As+Is Ds→(As)*,As+Is→As 111101AADDDD1111 1 —

Note: *When guard bit registers A0G and A1G are specified for the source operand Ds, data is

sign-extended before being transferred.

Rev. 2.00, 03/05, page 92 of 884

Table 2.31 shows the correspondence between the DSP data transfer operands and registers. CPU

core registers are used as pointer addresses indicating memory addresses.

Table 2.31 Correspondence between DSP Data Transfer Operands and Registers

SH (CPU Core) Registers

Oper-

and R0 R1 R2

(As2) R3

(As3)

(Ax0)

(As0)

(Ax1)

(As0) R6

(Ay0) R7

(Ay1)

(Ix)

(Is) R9

(Iy)

Ax ——— — Yes Yes ————

Ix (Is) ————————Yes —

Dx ——————————

Ay ——————Yes Yes ——

Iy —————————Yes

Dy ——————————

Da ——————————

As ——Yes Yes Yes Yes ————

Ds ——————————

DSP Registers

Oper-

andX0X1Y0Y1M0M1A0A1A0GA1G

Ax ——————————

Ix (Is) ——————————

Dx Yes Yes ————————

Ay ——————————

Iy ——————————

Dy ——Yes Yes ——————

Da ——————Yes Yes ——

As ——————————

Ds Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Note: Yes indicates that the register can be set.

Rev. 2.00, 03/05, page 93 of 884

2.5.3 DSP Operation Instruction Set

DSP operation instructions are digital signal processing instructions processed by the DSP unit.

These instructions use 32-bit instruction codes, and multiple instructions are executed in parallel.

The instruction codes are divided into an A field and a B field; parallel data transfer instructions

are designated in the A field, and single or double data operation instructions are designated in the

B field. Instructions can be independently designated and execution can also be carried out

independently. A parallel data transfer instruction designated in the A field is exactly the same as a

double data transfer instruction.

The B field data operation instructions are divided into three groups: double data operation

instructions, conditional single data operation instructions, and unconditional single data operation

instructions. Table 2.32 lists the instruction formats of the DSP operation instructions. Each of the

operands can be independently selected from the DSP registers. Table 2.33 shows the

correspondence between the DSP operation instruction operands and registers.

Table 2.32 DSP Operation Instruct ion Formats

Classification Instruction Forms Instruction

Double data operat ion instructions

(6 operands) ALUop. Sx, Sy, Du

MLTop. Se, Sf, Dg

PADD PMULS,

PSUB PMULS

Conditional single data

operatio n instructi ons 3 operands ALUop. Sx, Sy, Dz

DCT ALUop. Sx, Sy, Dz

DCF ALUop. Sx, Sy, Dz

PADD, PAND, POR,

PSHA, PSHL, PSUB,

PXOR

2 operands ALUop. Sx, Dz

DCT ALUop. Sx, Dz

DCF ALUop. Sx, Dz

ALUop. Sy, Dz

DCT ALUop. Sy, Dz

DCF ALUop. Sy, Dz

PCOPY, PDEC,

PDMSB, PINC,

PLDS, PSTS, PNEG

1 operand ALUop. Dz

DCT ALUop. Dz

DCF ALUop. Dz

PCLR, PSHA #imm,

PSHL #imm

Unconditional single data

operatio n instructi ons 3 operands ALUop. Sx, Sy, Du

MLTop. Se, Sf, Dg

PADDC, PSUBC,

PMULS

2 operands ALUop. Sx, Dz

ALUop. Sy, Dz

ALUop. Sx, Sy

PCMP, PABS, PRND

1 operand ALUop. Dz PSHA #imm,

PSHL #imm

Rev. 2.00, 03/05, page 94 of 884

Table 2.33 Correspondence between DSP Instruction Operands and Registers

ALU and BPU Instructions Multiplication Instructions

A0 Yes —Yes Yes ——Yes

A1 Yes —Yes Yes Yes Yes Yes

M0 —Yes Yes — ——Yes

M1 —Yes Yes — ——Yes

X0 Yes —Yes Yes Yes Yes —

X1 Yes —Yes —Yes ——

Y0 —Yes Yes Yes Yes Yes —

Y1 —Yes Yes ——Yes —

When writing parallel instructions, write the B field instructions first, then write the A field

instructions:

PADD A0,M0,A0 PMULS X0,Y0,M0 MOVX.W @R4+,X0 MOVY.W @R6+,Y0[;]

DCF PINC X1,A1 MOVX.W A0,@R5+R8 MOVY.W @R7+,Y0[;]

PCMP X1,M0 MOVX.W @R4+R8 [NOPY][;]

Text in bra ckets ([]) can be omitted. The no operation instructions NOPX and NOPY can be

omitted. Semicolons (;) are used to demarcate instruction lines, but can be omitted. If semicolons

are used, the space after the semicolon can be used for comments.

The individual status codes (DC, N, Z, V, GT) of the DSR register are always updated by

unconditional ALU operation instructions and shift operation instructions. Conditional instructions

do not update the status codes, even if the conditions have been met. Multiplication instructions

also do not update the status codes. DC bit definitions are determined by the specifications of the

CS bits in the DSR register.

Table 2.34 lists the DSP operation instructions by classification.

Rev. 2.00, 03/05, page 95 of 884

Table 2.34 Classification of DSP Instructions

Classification Instruction

Types Operation

Code Function No. of

Instructions

11 PABS Absolute value

operation 28

ALU fixed decimal

point operation

instructions PADD Addition

PADD

PMULS Addition and signed

multiplication

PADDC Addition with carry

PCLR Clear

PCMP Compare

PCOPY Copy

PNEG Invert sign

PSUB Subtraction

PSUB

PMULS Subtraction and

signed multiplication

PSUBC Subtraction with

borrow

2 PDEC Decrement 12ALU integer operation

instructions PINC Increment

MSB detection

instruction 1 PDMSB MSB detection 6

ALU

arithmetic

operation

Rounding operation

instruction 1 PRND Rounding 2

3 PAND Logical AND 9ALU logical operation instructions

POR Logical OR

PXOR Logical exclusive OR

Fixed decimal point multiplication

instruction 1 PMULS Signed multiplication 1

Shift Arithmetic shift

operatio n instructi on 1 PSHA Arithmetic shift 4

Logical shift operation

instruction 1 PSHL Logical shift 4

System control instructions 2 PLDS System register load 12

PSTS Store from system

Total 23 Total 78

Rev. 2.00, 03/05, page 96 of 884

2.5.4 Various Oper at ion Instruc tions

ALU Arithmetic Operation Instructions: Tables 2.35 to 2.44 list various operation instructions.

Table 2.35 ALU Fixed Point Operation Instruc tions

Instruction Operation Code Cycles DC Bit

PABS Sx,Dz If Sx≥0,Sx→Dz

If Sx<0,0– Sx→Dz

111110**********

10001000xx00zzzz

1 Update

PABS Sy,Dz If Sy≥0,Sy→Dz

If Sy<0,0–Sy→Dz

111110**********

1010100000yyzzzz

1 Update

PADD Sx,Sy,Dz Sx+Sy→Dz 111110**********

10110001xxyyzzzz

1 Update

DCT PADD Sx,Sy,Dz if DC=1,Sx+Sy→Dz if 0,nop 111110**********

10110010xxyyzzzz

1 —

DCF PADD Sx,Sy,Dz if DC=0,Sx+Sy→Dz if 1,nop 111110**********

10110011xxyyzzzz

1 —

PADD Sx,Sy,Du

PMULS Se,Sf,Dg

Sx+Sy→Du

MSW of Se × MSW of

Sf→Dg

111110**********

0111eeffxxyygguu

1 Update

PADDC Sx,Sy,Dz Sx+Sy+DC→Dz 111110**********

10110000xxyyzzzz

1 Update

PCLR Dz H'00000000→Dz 111110**********

100011010000zzzz

1 Update

DCT PCLR Dz if DC=1,H'00000000→Dz

if 0,nop

111110**********

100011100000zzzz

1 —

DCF PCLR Dz if DC=0,H'00000000→Dz

if 1,nop

111110**********

100011110000zzzz

1 —

PCMP Sx,Sy Sx–Sy 111110**********

10000100xxyy0000

1 Update

PCOPY Sx,Dz Sx→Dz 111110**********

11011001xx00zzzz

1 Update

PCOPY Sy,Dz Sy→Dz 111110**********

1111100100yyzzzz

1 Update

DCT PCOPY Sx,Dz if DC=1,Sx→Dz if 0,nop 111110**********

11011010xx00zzzz

1 —

Rev. 2.00, 03/05, page 97 of 884

Instruction Operation Code Cycles DC Bit

DCT PCOPY Sy,Dz if DC=1,Sy→Dz if 0,nop 111110**********

1111101000yyzzzz

1 —

DCF PCOPY Sx,Dz if DC=0,Sx→Dz if 1,nop 111110**********

11011011xx00zzzz

1 —

DCF PCOPY Sy,Dz if DC=0,Sy→Dz if 1,nop 111110**********

1111101100yyzzzz

1 —

PNEG Sx,Dz 0–Sx→Dz 111110**********

11001001xx00zzzz

1 Update

PNEG Sy,Dz 0–Sy→Dz 111110**********

1110100100yyzzzz

1 Update

DCT PNEG Sx,Dz if DC=1,0–Sx→Dz

if 0,nop

111110**********

11001010xx00zzzz

1 —

DCT PNEG Sy,Dz if DC=1,0–Sy→Dz

if 0,nop

111110**********

1110101000yyzzzz

1 —

DCF PNEG Sx,Dz if DC=0,0–Sx→Dz

if 1,nop

111110**********

11001011xx00zzzz

1 —

DCF PNEG Sy,Dz if DC=0,0–Sy→Dz

if 1,nop

111110**********

1110101100yyzzzz

1 —

PSUB Sx,Sy,Dz Sx–Sy→Dz 111110**********

10100001xxyyzzzz

1 Update

DCT PSUB Sx,Sy,Dz if DC=1,Sx–Sy→Dz if 0,nop 111110**********

10100010xxyyzzzz

1 —

DCF PSUB Sx,Sy,Dz if DC=0,Sx–Sy→Dz if 1,nop 111110**********

10100011xxyyzzzz

1 —

PSUB Sx,Sy,Du

PMULS Se,Sf,Dg

Sx–Sy→Du

MSW of Se × MSW of Sf→Dg

111110**********

0110eeffxxyygguu

1 Update

PSUBC Sx,Sy,Dz Sx–Sy–DC→Dz 111110**********

10100000xxyyzzzz

1 Update

Rev. 2.00, 03/05, page 98 of 884

Table 2.36 ALU Integer Ope ra tion Instru ct ion s

Instruction Operation Code Cycles DC Bit

PDEC Sx,Dz MSW of Sx – 1 → MSW of Dz,

clear LSW of Dz 111110**********

10001001xx00zzzz

1 Update

PDEC Sy,Dz MSW of Sy – 1 → MSW of Dz,

clear LSW of Dz 111110**********

1010100100yyzzzz

1 Update

DCT PDEC Sx,Dz If DC=1, MSW of Sx – 1 →

MSW of Dz, clear LSW of Dz;

if 0, nop

111110**********

10001010xx00zzzz

1 —

DCT PDEC Sy,Dz If DC=1, MSW of Sy – 1 →

MSW of Dz, clear LSW of Dz;

if 0, nop

111110**********

1010101000yyzzzz

1 —

DCF PDEC Sx,Dz If DC=0, MSW of Sx – 1 →

MSW of Dz, clear LSW of Dz;

if 1, nop

111110**********

10001011xx00zzzz

1 —

DCF PDEC Sy,Dz If DC=0, MSW of Sy – 1 →

MSW of Dz, clear LSW of Dz;

if 1, nop

111110**********

1010101100yyzzzz

1 —

PINC Sx,Dz MSW of Sx + 1 → MSW of Dz,

clear LSW of Dz 111110**********

10011001xx00zzzz

1 Update

PINC Sy,Dz MSW of Sy + 1 → MSW of Dz,

clear LSW of Dz 111110**********

1011100100yyzzzz

1 Update

DCT PINC Sx,Dz If DC=1, MSW of Sx + 1 →

MSW of Dz, clear LSW of Dz;

if 0, nop

111110**********

10011010xx00zzzz

1 —

DCT PINC Sy,Dz If DC=1, MSW of Sy + 1 →

MSW of Dz, clear LSW of Dz;

if 0, nop

111110**********

1011101000yyzzzz

1 —

DCF PINC Sx,Dz If DC=0, MSW of Sx + 1 →

MSW of Dz, clear LSW of Dz;

if 1, nop

111110**********

10011011xx00zzzz

1 —

DCF PINC Sy,Dz If DC=0, MSW of Sy + 1 →

MSW of Dz, clear LSW of Dz;

if 1, nop

111110**********

1011101100yyzzzz

1 —

Rev. 2.00, 03/05, page 99 of 884

Table 2.37 MSB Detection Instructions

Instruction Operation Code Cycles DC Bit

PDMSB Sx,Dz Sx data MSB position → MSW

of Dz, clear LSW of Dz 111110**********

10011101xx00zzzz

1 Update

PDMSB Sy,Dz Sy data MSB position → MSW

of Dz, clear LSW of Dz 111110**********

1011110100yyzzzz

1 Update

DCT PDMSB Sx,Dz If DC=1, Sx data MSB position

→ MSW of Dz, clear LSW of

Dz; if 0, nop

111110**********

10011110xx00zzzz

1 —

DCT PDMSB Sy,Dz If DC=1, Sy data MSB position

→ MSW of Dz, clear LSW of

Dz; if 0, nop

111110**********

1011111000yyzzzz

1 —

DCF PDMSB Sx,Dz If DC=0, Sx data MSB position

→ MSW of Dz, clear LSW of

Dz; if 1, nop

111110**********

10011111xx00zzzz

1 —

DCF PDMSB Sy,Dz If DC=0, Sy data MSB position

→ MSW of Dz, clear LSW of

Dz; if 1, nop

111110**********

1011111100yyzzzz

1 —

Table 2.38 Rounding Opera tion Instruct ions

Instruction Operation Code Cycles DC Bit

PRND Sx,Dz Sx+H'00008000→Dz

clear LSW of Dz

111110**********

10011000xx00zzzz

1 Update

PRND Sy,Dz Sy+H'00008000→Dz

clear LSW of Dz

111110**********

1011100000yyzzzz

1 Update

Rev. 2.00, 03/05, page 100 of 884

Table 2.39 ALU Logical Operat ion Instru ct ions

Instruction Operation Code Cycles DC Bit

PAND Sx,Sy,Dz Sx & Sy → Dz, clear LSW of

Dz 111110**********

10010101xxyyzzzz

1 Update

DCT PAND Sx,Sy,Dz If DC=1, Sx & Sy → Dz,

clear LSW of Dz; if 0, nop 111110**********

10010110xxyyzzzz

1 —

DCF PAND Sx,Sy,Dz If DC=0, Sx & Sy → Dz,

clear LSW of Dz; if 1, nop 111110**********

10010111xxyyzzzz

1 —

POR Sx,Sy,Dz Sx | Sy → Dz, clear LSW of

Dz 111110**********

10110101xxyyzzzz

1 Update

DCT POR Sx,Sy,Dz If DC=1, Sx | Sy → Dz, clear

LSW of Dz; if 0, nop 111110**********

10110110xxyyzzzz

1 —

DCF POR Sx,Sy,Dz If DC=0, Sx | Sy → Dz, clear

LSW of Dz; if 1, nop 111110**********

10110111xxyyzzzz

1 —

PXOR Sx,Sy,Dz Sx ^ Sy → Dz, clear LSW of

Dz 111110**********

10100101xxyyzzzz

1 Update

DCT PXOR Sx,Sy,Dz If DC=1, Sx ^ Sy → Dz,

clear LSW of Dz; if 0, nop 111110**********

10100110xxyyzzzz

1 —

DCF PXOR Sx,Sy,Dz If DC=0, Sx ^ Sy → Dz,

clear LSW of Dz; if 1, nop 111110**********

10100111xxyyzzzz

1 —

Table 2.40 Fixed Point Multipl icatio n Instru ction s

Instruction Operation Code Cycles DC Bit

PMULS Se,Sf,Dg MSW of Se × MSW of

Sf→Dg 111110**********

0100eeff0000gg00

1 —

Rev. 2.00, 03/05, page 101 of 884

Table 2.41 Arithmetic Shift Operation Ins tructions

Instruction Operation Code Cycles DC Bit

PSHA Sx,Sy,Dz if Sy≥0,Sx<<Sy→Dz

if Sy<0,Sx>>Sy→Dz

111110**********

10010001xxyyzzzz

1 Update

DCT PSHA Sx,Sy,Dz if DC=1 & Sy≥0,Sx<<Sy→Dz

if DC=1 & Sy<0,Sx>> Sy→Dz

if DC=0,nop

111110**********

10010010xxyyzzzz

1 —

DCF PSHA Sx,Sy,Dz if DC=0 & Sy≥0,Sx<<Sy→Dz

if DC=0 & Sy<0,Sx>> Sy→Dz

if DC=1,nop

111110**********

10010011xxyyzzzz

1 —

PSHA #imm,Dz if im m≥0,Dz<<imm→Dz

if imm<0,Dz >>imm →Dz

111110**********

00010iiiiiiizzzz

1 Update

Table 2.42 Logical Shift Operation Ins truct ions

Instruction Operation Code Cycles DC Bit

PSHL Sx,Sy,Dz if Sy≥0,Sx<<Sy→Dz, clear

LSW of Dz

if Sy<0,Sx>>Sy→Dz, clear

LSW of Dz

111110**********

10000001xxyyzzzz

1 Update

DCT PSHL Sx,Sy,Dz if DC=1 &

Sy≥0,Sx<<Sy→Dz, clear

LSW of Dz

if DC=1 &

Sy<0,Sx>>Sy→Dz, clear

LSW of Dz

if DC=0,nop

111110**********

10000010xxyyzzzz

1 —

DCF PSHL Sx,Sy,Dz if DC=0 &

Sy≥0,Sx<<Sy→Dz, clear

LSW of Dz

if DC=0 &

Sy<0,Sx>>Sy→Dz, clear

LSW of Dz

if DC=1,nop

111110**********

10000011xxyyzzzz

1 —

PSHL #imm,Dz if im m≥0,Dz<<imm→Dz,

clear LSW of Dz

if imm<0,Dz >>imm →Dz,

clear LSW of Dz

111110**********

00000iiiiiiizzzz

1 Update

Rev. 2.00, 03/05, page 102 of 884

Table 2.43 System Control Instru ct ions

Instruction Operation Code Cycles DC Bit

PLDS Dz,MACH Dz→MACH 111110**********

111011010000zzzz

1 —

PLDS Dz,MACL Dz→MACL 111110**********

111111010000zzzz

1 —

DCT PLDS Dz,MACH if DC=1,Dz→MACH

if 0,nop

111110**********

111011100000zzzz

1 —

DCT PLDS Dz,MACL if DC=1,Dz→MACL

if 0,nop

111110**********

111111100000zzzz

1 —

DCF PLDS Dz,MACH if DC=0,Dz→MACH

if 1,nop

111110**********

111011110000zzzz

1 —

DCF PLDS Dz,MACL if DC=0,Dz→MACL

if 1,nop

111110**********

111111110000zzzz

1 —

PSTS MACH,Dz MACH→Dz 111110**********

110011010000zzzz

1 —

PSTS MACL,Dz MACL→Dz 111110**********

110111010000zzzz

1 —

DCT PSTS MACH,Dz if DC=1,MACH→Dz

if 0,nop

111110**********

110011100000zzzz

1 —

DCT PSTS MACL,Dz if DC=1,MACL→Dz

if 0,nop

111110**********

110111100000zzzz

1 —

DCF PSTS MACH,Dz if DC=0,MACH→Dz

if 1,nop

111110**********

110011110000zzzz

1 —

DCF PSTS MACL,Dz if DC=0,MACL→Dz

if 1,nop

111110**********

110111110000zzzz

1 —

Rev. 2.00, 03/05, page 103 of 884

When there are no data transfer instructions being processed simultaneously in parallel with DSP

operation instructions, it is possible to either write NOPX and NOPY instructions or to omit the

instructi on s. The ins tructi on code s are the same reg ardl ess of whet her th e NO PX and NO PY

instructions are written or omitted. Table 2.44 gives some examples of NOPX and NOPY

instruction codes.

Table 2.44 NOPX and NOPY Instruction Codes

Instruction Code

PADD X0, Y0, A0 MOVX.W @R4+, X0 MOVY.W @R6+R9, Y0 1111100000001011

1011000100000111

PADD X0, Y0, A0 NOPX MOVY.W @R6+R9, Y0 1111100000000011

1011000100000111

PADD X0, Y0, A0 NOPX NOPY 1111100000000000

1011000100000111

PADD X0, Y0, A0 NOPX 1111100000000000

1011000100000111

PADD X0, Y0, A0 1111100000000000

1011000100000111

MOVX.W @R4+, X0 MOVY.W @R6+R9, Y0 1111000000001011

MOVX.W @R4+, X0 NOPY 1111000000001000

MOVS.W @R4+, X0 1111010010001000

NOPX MOVY.W @R6+R9, Y0 1111000000000011

MOVY.W @R6+R9, Y0 1111000000000011

NOPX NOPY 1111000000000000

NOP 0000000000001001

Rev. 2.00, 03/05, page 104 of 884

2.6 Usage Notes

1. When DSP instructions are not used, execute the dummy instruction as follows to decrease

operation cur rent.

This dummy instruction is executed in initial program.

PCLR A0 ; Clear the A0 register.

PSHA #5, A0 ; 5 bit shift to left.

2. When the S bit of SR is changed after the DSP instructions are executed, pipeline is not

executed exactly.

Execute the processing as described in either A or B below.

A. After the DSP instructions are executed, don’t change the S bit of SR register.

B. Insert the NOP instruction before the LDC Rn, SR instruction.

Example:

PSHA #1,A0

PINC X0,A0 MOVX.W A1,@R5

NOP

LDC R0,SR

3. When a double-length multiply instruction (MUL.L, DMULU.L, or DMULS.L) or a double-

length multiply-and-accumulate instruction (MAC.L) is executed in combination with a DSP

operation instruction, a malfunction may occur. See the following conditions and

countermeasures.

Conditions:

When the following A and B conditions are both satisfied, the instruction shown in item b in B

below may be executed incorrectly.

A. An instruction in the on-chip memory or the cache is executed.

B. The following instructions are executed in the order of a, b, and c.

a. Double-length multiply instruction (MUL.L, DMULU.L, or DMULS.L) or double-

length multiply-and-accumulate instruction (MAC.L)

b. DSP operation instruction other than PMULS, PSTS, and PLDS

Note: The following instructions are DSP operation instructions other than PMULS,

PSTS, and PLDS:

PABS, PADD, PADDC, PAND, PCLR, PCMP, PCOPY, PDEC, PDMSB,

PI N C , PN E G, POR, PRN D, PS H A, PS HL, PS U B , PS U BC, an d PX O R

c. PMULS, PSTS, or PLDS

Rev. 2.00, 03/05, page 105 of 884

Execution of instruction a in B above takes several cycles. If instruction c, which uses the same

resource as instruction a, is issued during execution of instruction a, instruction c is made wait

until the current operation is completed.

Instruction b has no relationship with instruction a and is started without waiting instruction a.

However, its execution may be affected by the control for keeping instruction c in the wait

state and may generate an incorrect result.

If instructions a and c are executed in sequence without instruction b between them, execution

will be completed corrected.

Countermeasures:

This problem is avoided by any of the following countermeasures.

A. Do not execute the instruction sequence shown in B above.

B. Replace instructions b and c above if the program code includes the instruction sequence

shown in B above and replacing instructions b and c does not affect the execution results.

C. Insert one or more NOP instructions or instructions that are not related to the multiplier

between instructions a and b if the program code includes the instruction sequence shown

in B above and replacing instructions b and c does affect the execution results.

Supplementary information:

This usage note is also applicable when a delayed branch instruction comes immediately

before instruction a in B above, the a instruction is placed in the delay slot, and instructions b

and c in B are executed in sequence at the branch destination.

4. This section presents examples of and methods for preventing the instruction execution stall

phenomenon due to multiplier contention caused by multiply and multiply-and-accumulate

instructions.

If the SR (status register) S bit (saturated arithmetic bit) is changed immediately after a

multiply or multiply-and-accumulate instruction in the state where multiplier contention has

occurred due to multiply and/or multiply-and-accumulate instructions and instruction

execution has stalled, the instruction execution order will be reversed. As a result, the

instruction that should have been executed before the S bit was changed will be executed after

the S bit has changed. This can result in an incorrect arithmetic result being produced.

Instructions affected by S bit modification:

Multiply-and-accumulate instructions: MAC.W and MAC.L

Conditions:

The following shows an example of error conditions.

A. Multiply instruction and multiply-and-accumulate instruction

a. DMULU.L R4,R10 MUL.L, DMULS.L, DMULU.L, or MAC.L can be instruction

Rev. 2.00, 03/05, page 106 of 884

b. MAC.L @R5+, @R5+ MAC.W and MAC.L can be instruction b. Multiplier access

conflict occurs and execution stall cycle may be produced.

c. LDC R0,SR Changes the saturation arithmetic mode.

Multiplier access conflict occurs between instructions a (DMULU.L) and b (MAC.L), and

execution of instruction b (MAC.L) is stalled. S bit modification (instruction c) is executed

immediately before the MAC.L instruction (b) in the CPU due to the pipeline operation.

Consequently, the sequence of instruction execution b and c is reversed and the MAC.L

operation result becomes an incorrect value.

Countermeasures:

This problem is avoided by any of the following countermeasures.

A. Do not access SR immediately after the multiply-and-accumulate instruction.

B. Insert a NOP instruction before the LDC Rn,SR instruction.

C. Prevent multiplier access conflict (not to produce stall cycles).

Rev. 2.00, 03/05, page 107 of 884

Section 3 Oscillator Ci rcuits and Operating Modes

3.1 Overview

Operation of the on-chip clock pulse generator, and CS0 area bus width specification, are

controlled by the operating mode pins. A crystal resonator or external clock can be selected as the

clock source.

3.2 On-Chip Clock Pulse Generator and Operating Modes

3.2.1 Clock Pulse Genera tor

A block diagram of the on-chip clock pulse generator circuit is shown in figure 3.1.

CAP1

CKIO

MD2

MD0

MD1

CKPACK*

Oscillator

On/Off

PLL circuit 1

PLL circuit 2

×1, ×2, ×4

CAP2

EXTAL

XTAL

CKPREQ/CKM

Clock mode control circuit

DIVP

1/1

1/2

1/4

Note:

See section 20.4.4, Clock Pause Function.

Eφ

External interface

clock

Iφ

CPU/DSP core

clock

Pφ

Peripheral module

clock

The relationship between the

internal clock frequencies is:

Iφ ≥ Eφ ≥ Pφ.

Maximum frequencies are:

Iφ, Eφ ≤ 62.5 MHz, Pφ ≤ 31.25 MHz.

DIVE

1/1

1/2

1/4

DIVM

1/1

1/2

1/4

φ system clock

Figure 3.1 Block Diagram of Clock Pulse Generator Circuit

Rev. 2.00, 03/05, page 108 of 884

Pin Configuration: Table 3.1 lists the functions relating to the pins relating to the oscillator

circuit.

Table 3.1 Pin Configura tion

Pin Name I/O Function

CKIO I/O External clock input pin or internal clock output pin

XTAL Output Connects to the crystal resonator

EXTAL Input Connects to the crystal resonator or to the external clock input when

using PLL circuit 2

CAP1 Input Connects to capaci tance for operating PLL circuit 1

CAP2 Input Connects to capaci tance for operating PLL circuit 2

MD0 Input The level applied to these pins specifi es the clock mode

MD1 Input

MD2 Input

CKPREQ

/CKM Input Used as the clock pause request pin, or specifies operation of the

crystal resonator

CKPACK

Output Clock pause function

PLL Circuit 1: PLL circuit 1 eliminates phase differences between external clocks and clocks

supplied internally within the chip. In high-speed operation, the phase difference between the

reference clocks and operating clocks in the chip directly affects the interface margin with

peripheral devices. On-chip PLL circuit 1 is provided to eliminate this effect.

PLL Circuit 2: PLL circuit 2 either leaves unchanged, doubles, or quadruples the frequency of

clocks provided from the crystal resonator or the EXTAL pin external clock input for the chip

operating frequency. The freque ncy modifi catio n regist er set s the clock frequency multi pli cation

factor.

Rev. 2.00, 03/05, page 109 of 884

3.2.2 Clock Operating Mode Settings

Table 3.2 lists the functions and operation of clock modes 0 to 6.

Table 3.2 Operating Mod es

Clock Mode Function/Operation Clock Source

0 PLL circuits 1 and 2 operate. A clock is output with the same

phase (with the same frequency as Eφ) as the internal clocks

(Iφ, Eφ, Pφ) from the CKIO pin

PLL circuits 1 and 2 can be switched between the operating

and halted states by means of control bits in the frequency

modification register (FMR). The CKIO pin can also be placed

in the high-impedance state

Normall y, mode 0 should be used.

Crystal resonator/

external clock input

1 PLL circuits 1 and 2 operate. A clock (with the same

frequency as Eφ) 1/4 φ cycle in advance of the chip's i nternal

system clock φ is output from the CKIO pin.

PLL circuits 1 and 2 can be switched between the operating

and halted states by means of control bits in the frequency

modification register (FMR). The CKIO pin can also be placed

in the high-impedance state. However, clock phase shifting is

not performed when PLL circuit 1 is halted.

Normall y, mode 0 should be used.

2 Only PLL circuit 2 operates. The clock from PLL circuit 2 is

output from the CKIO pin (having the same frequency as the

Eφ). As PLL circuit 1 does not operate, phases are not

matched in this mode

PLL circuit 2 can be switched between the operating and

halted states by means of a control bit in the frequency

modification register (FMR). The CKIO pin can also be placed

in the high-impedance state

3 Only PLL circuit 2 operates. The CKIO pin is high-impedance

PLL circuit 2 can be switched between the operating and

halted states by means of a control bit in the frequency

m odification register (FMR)

4 Only PLL circuit 1 operates. Operate PLL circuit 1 when

operating with synchronization of the phases of the clock

input from the CKIO pin and the internal clocks (Iφ, Eφ, Pφ).

PLL circuit 2 does not operate in this mode

PLL circuit 1 can be switched between the operating and

halted states by means of a control bit in the frequency

m odification register (FMR)

External clock input

Rev. 2.00, 03/05, page 110 of 884

Clock Mode Function/Operation Clock Source

5 Only PLL circuit 1 operates. Operate PLL circuit 1 when

operating with a 1/4 φ cyc le lag of the clock input from the

CKIO pin and the internal clocks (Iφ, Eφ, Pφ) with respect to

system clock φ. PLL circuit 2 does not operate in this mode

PLL circuit 1 can be switched between the operating and

halted states by means of control bits in the frequency

modification register (FMR). However, clock phase shifting is

not performed when PLL circuit 1 is halted.

Normall y, mode 4 should be used.

External clock input

6 PLL circuits 1 and 2 do not operate. Set this mode when a

clock having a frequency equal to that of clocks the clock

input from the CKIO pin is used

The internal clock frequency can be changed in each clock mode (see section 3.2.5, Operating

Frequency Selection by Register).

In clock modes 4 to 6, the frequency of the clock input from the CKIO pin can be changed, or the

clock can be stopped (see section 20.4.4, Clock Pause Function).

Table 3.3 lists the relationship between pins MD2 to MD0 and the clock operating mode. Do not

switch the MD2 to MD0 pins while they are operating. Switching will cause operating errors.

Rev. 2.00, 03/05, page 111 of 884

Table 3.3 Clock Mode Pin Settings and States

Clock

Mode MD2 MD1 MD0

CKPREQ

CKM EXTAL XTAL CKIO

0 0 0 0 0 Clock in put Op en

1Crystal

oscillation Crystal

oscillation

Output/high

impedance

1 0 0 1 0 Clock in put Op en

1 Crystal

oscillation Crystal

oscillation

Output/high

impedance

2 0 1 0 0 Clock in put Op en

1Crystal

oscillation Crystal

oscillation

Output/high

impedance

3 0 1 1 0 Clock in put Op en

1 Crystal

oscillation Crystal

oscillation

High

impedance

4100*Open Open Clock input

5 1 0 1 Open Open Clock input

6 1 1 0 Open Open Clock input

Notes: Do not use in combi nations other than those listed.

*In clock modes 4, 5, and 6,

CKPREQ

/CKM functions as the clock pause request pin.

Rev. 2.00, 03/05, page 112 of 884

3.2.3 Connecting a Crystal Resonator

Connecting a Crystal Resonator: Figure 3.2 shows an example of crystal resonator connection.

The values of damping resistance R and load capacitance CL1 and CL2 should be decided after

investigating the components in collaboration with the manufacturer of the crystal oscillator to be

used. The crystal resonator should be an AT-cut parallel-oscillator type. Place the crystal resonator

and its load capacitors as close as possible to the XTAL and EXTAL pins.

Other signal lines should be routed away from the oscillator circuit to prevent induction from

interfering with correct oscillation.

High level

Notes: 1. The CKIO pin is an output or high impedance in clock modes 0, 1, and 2,

and is high impedance in clock mode 3.

2. The values for CL1, CL2, and the damping resistance should be determined after

consultation with the crystal resonator manufacturer.

CL1

CKPREQ/CKM

CKIO

EXTAL

XTAL

Output or high

impedance

CL2

Figure 3.2 Example of Crystal Oscillator Connection

Rev. 2.00, 03/05, page 113 of 884

3.2.4 External Clock Input

An external clock is input from the EXTAL pin or the CKIO pin, depending on the clock mode.

Clock Input from EXTAL Pin: This method can be used in clock modes 0, 1, 2, and 3.

CKPREQ/CKM

CKIO

EXTAL

XTAL

Output or

high-impedance

The CKIO pin is an output or

high impedance in clock modes

0, 1, and 2, and is high impedance

in clock mode 3.

Open

External Clock Input

Ground level

Figure 3.3 External Clock Input Method

Clock Input from CKIO Pin: This method can be used in clock modes 4, 5, and 6.

CKPREQ/CKM

CKIO

EXTAL

XTAL Open

External Clock Input

Open

The CKPREQ/CKM pin is the clock

pause request input pin.

Figure 3.4 External Clock Input Method

Rev. 2.00, 03/05, page 114 of 884

3.2.5 Operating Frequency Selection by Register

Using the frequency modification register (FMR), it is possible to specify the operating frequency

division ratio for the internal clocks (Iφ, Eφ, Pφ). The internal clock frequency is determined under

the control of PLL circuits 1 and 2 and dividers DIVM, DIVE, and DIVP.

Frequen cy Modif icati on Reg ister ( FMR ): The frequency modification register is initialized only

by a power-on reset via the

RES

pin, and not by an internal reset resulting from WDT overflow.

Its initial value depends on the settings of pins MD2 to MD0. Table 3.4 shows the relationship

between the MD2 to MD0 pin combinations and the initial value of the frequency modification

Table 3.4 Relationship between Clock Mode Pin Settings and Initial Value of Frequency

Modification Register

Cloc k Mo de MD2 MD1 MD0 Initia l Va lue

Mode 0 0 0 0 H'00

Mode 1 0 0 1

Mode 2 0 1 0 H'40

Mode 3 0 1 1 H'60

Mode 4 1 0 0 H'A6

Mode 5 1 0 1

Mode 6 1 1 0 H'E0

The register configuration is shown in table 3.5.

Table 3.5 Register Configurat ion

Name Abbreviation R/W Initial Value Address

Frequency modification register FMR R/W See table 3.4*H'FFFFFE90

Note: *The initial value depends on the clock mode.

Rev. 2.00, 03/05, page 115 of 884

Bit:76543210

PLL2ST PLL1ST CKIOST — FR3 FR2 FR1 FR0

Initial value: — — — 0 0 — — 0

R/W: R/W R/W R/W R R/W R/W R/W R/W

Bit 7—PLL2ST: Switching is possible in modes 0 to 3. In modes 4 to 6, PLL circuit 2 cannot be

used. In these modes, this bi t alw ay s reads 1.

Bit 7: PLL2ST Description

0 PLL circuit 2 used

1 PLL circuit 2 not used

Bit 6—PLL1ST: Switching is possible in modes 0, 1, 4, and 5. In modes 2, 3, and 6, PLL circuit 1

cannot be used. In these modes, this bit always reads 1.

Bit 6: PLL1ST Description

0 PLL circuit 1 is used

1 PLL circuit 1 is not used

Bit 5—CKIOST: Setting is possible in modes 0 to 3. In modes 4 to 6, the CKIO pin is an input

pin. In these modes, this bit always reads 1.

Bit 5: CKIOST Description

0 The CKIO pin outputs Eφ

1 The CKIO pin is in the high-impedance state (Do not place CKIO in the high-

impedance state when PLL circuit 1 is operating)

Bit 4—Reserved: This bit is always read as 0. The write value should always be 0.

Bits 3 to 0—FR3 to FR0: The internal clock frequency and CKIO output frequency (modes 0 to 2)

can be set by frequency setting bits FR3 to FR0. The values that can be set in bits FR3 to FR0

depend on the mode and whether PLL circuit 1 and PLL circuit 2 are operating or halted. The

following tables show the values that can be set in FR3 to FR0, and the internal clock and CKIO

output frequency ratios, taking the external input clock frequency as 1.

Rev. 2.00, 03/05, page 116 of 884

• Modes 0 and 1

PLL circuits 1 and 2 operating

EXTAL input or crystal resonator used

FR3 FR2 FR1 FR0 φ

φφ

φIφ

φφ

φEφ

φφ

φPφ

φφ

φCKIO

0000×4×1×1×1Eφ

0100×4×2×1×1Eφ

0101×4×2×2×1Eφ

0110×4×2×2×2Eφ

1000×4×4×1×1Eφ

1001×4×4×2×1Eφ

1010×4×4×2×2Eφ

1100×4×4×4×1Eφ

1110×4×4×4×2Eφ

Note: Do not use combinations other than those shown above.

• Modes 0 to 3

PLL circuit 1 halted, PLL circuit 2 operating

EXTAL input or crystal resonator used

FR3 FR2 FR1 FR0 φ

φφ

φIφ

φφ

φEφ

φφ

φPφ

φφ

φCKIO

0000×1×1×1×1Eφ

0101×2×2×2×1Eφ

0110×2×2×2×2Eφ

1100×4×4×4×1Eφ

1110×4×4×4×2Eφ

Note: Do not use combinations other than those shown above.

Rev. 2.00, 03/05, page 117 of 884

• Modes 0 and 1

PLL circuit 1 operating, PLL circuit 2 halted

EXTAL input or crystal resonator used

FR3 FR2 FR1 FR0 φ

φφ

φIφ

φφ

φEφ

φφ

φPφ

φφ

φCKIO

0000×4×1×1×1Eφ

0100×4×2×1×1Eφ

1000×4×4×1×1Eφ

Note: Do not use combinations other than those shown above.

• Modes 4 and 5

PLL circuit 1 operating, PLL circuit 2 halted

CKIO input

FR3 FR2 FR1 FR0 φ

φφ

φIφ

φφ

φEφ

φφ

φPφ

φφ

φCKIO

0101×2×1×1×1/2 Eφ

0110×2×1×1×1Eφ

1001×2×2×1×1/2 Eφ

1010×2×2×1×1Eφ

Note: Do not use combinations other than those shown above.

Rev. 2.00, 03/05, page 118 of 884

• Modes 0 to 6

PLL circuits 1 and 2 halted

EXTAL input or crystal resonator used (modes 0 to 3)

CKIO input (modes 4 to 6)

FR3 FR2 FR1 FR0 φ

φφ

φIφ

φφ

φEφ

φφ

φPφ

φφ

φCKIO

0000×1×1/4 ×1/4 ×1/4 ×1

0100×1×1/2 ×1/4 ×1/4 ×1

0101×1×1/2 ×1/2 ×1/4 ×1

0110×1×1/2 ×1/2 ×1/2 ×1

1000×1×1×1/4 ×1/4 ×1

1001×1×1×1/2 ×1/4 ×1

1010×1×1×1/2 ×1/2 ×1

1100×1×1×1×1/4 ×1

1110×1×1×1×1/2 ×1

1111×1×1×1×1×1

Note: Do not use combinations other than those shown above.

Frequency Change: When PLL circuit 1 or PLL circuit 2 becomes operational after modifying

the frequency modification register (including modification the frequency modification register in

the operating state), access the frequency modification register using the following procedure, and

noting the cautions listed below.

Frequency change procedure

• Set the on-chip watchdog timer (WDT) overflow time to secure the PLL circuit oscillation

settling time (CKS2 to CKS0 bits in WTCSR).

• Clear the WT/

and TME bit to 0 in WTCSR.

• Perform a read anywhere in an external memory area 0 to 4 cache-through area.

• Change the frequency modification register to the target frequency, or change the

operating/halted state of the PLL circuits 1 and 2 (the clocks will stop temporarily inside the

chip).

• The oscillation circuits operate, and the clock is supplied to the WDT. This clock increments

the WDT.

• On WDT overflow, supply of a clock with the frequency set in frequency setting bits FR3 to

FR0 begins. In this case, the OVF bit in WTSCR and the WOVF bit in RSTCSR are not set, an

interval timer interrupt (ITI) is not requested, and the

WDTOVF

signal is not asserted.

Sample code for changing the frequency is shown below.

Rev. 2.00, 03/05, page 119 of 884

;SH7615 freque ncy change

;

FMR .equ h'fffffe90

WTCSR .equ h'fffffe80

RSTCSR .equ h'fffffe83

PACR .equ h'fffffc80

XRAM .equ h'1000e000

.export _init_FMR

_init_FMR:

mov.l #XRAM,r1

mov.l r1,r5

mov.l #FREQUENCY,r2

mov.l #FREQUENCY_END,r3

program_move:

mov.w @r2,r0

mov.w r0,@r1

add #2,r1

add #2,r2

cmp/eq r2,r3

bf program_move

nop

mov.l #PACR,r1

mov.w #h'0008,r0

mov.w r0,@r1

MOV.L #WTCSR,R1

MOV.W #H'A51F,R2

MOV.L #H'26200000,R3

MOV.L #FMR,R4

Rev. 2.00, 03/05, page 120 of 884

jmp @r5

nop

clock4_err:

bra clock4_err

nop

;

;Main port ion of freque ncy change code.

;First copy this to XRAM and then run it in XRAM.

FREQUENCY:

; <Watchdo g t imer cont ro l and status regist er set ting>

; Cle ar TME bit.

; Clock input to WTCNT is φ/16384

; (Overflow frequency = 262.144 ms)

MOV.W R2,@R1

; <Exter nal cache t hrough area read>

; Cache through area of external member space 3: H'26200000

MOV.L @R3,R0

; <Frequency change register sett ing >

; PLL circu it 1 → D isabled.

; PLL circu it 2 → Enabled.

; Iφ (×4) = 62.5 MHz, Eφ (×4) = 62.5 MHz,

; Pφ (×2) = 31.25 MHz, CKIO (E φ) = 62.5 MHz,

; MOV #H'4E,R0

; PLL cir cuits 1 and 2 → Enabled.

; Iφ (×4) = 62.5 MHz, Eφ (×2) = 31.25 MHz,

; Pφ (×2 ) = 31.25 MHz, CKI O ( E φ) = 31.25 MHz,

MOV #H'0A,R0

Rev. 2.00, 03/05, page 121 of 884

; PLL cir cuits 1 and 2 → Enabled.

; Iφ (×4) = 62.5 MHz, Eφ (×1) = 15.625 MHz,

; Pφ (×1) = 15.625 MHz, CKIO (E φ) = 15.625 MHz,

; MOV #H'08,R0

MOV.B R0,@R4

rts

nop

FREQUENCY_END:

NOP

.END

Cautions

• The read from the external memory space 0–4 cache-through area and the write to the

frequency modification register should be performed in on-chip X/Y memory. After reading

from the external memory space 0–4 cache-through area, do not perform any write operations

in external memory spaces 0–4 until the write to the frequency modification register.

• When the write access to the frequency modification register is executed, the WDT starts

automatically.

• Do not turn off the CKIO output when PLL circuit 1 is in the operating state.

• The CKIO output will be unstable until the PLL circuit stabilizes.

• When a frequency is modified, halt the on-chip DMAC (E-DMAC and DMAC) operation

before the frequency modification.

If PLL circuit 1 or PLL circuit 2 does not become operational after modifying the frequency

modification register (including modification in the operating state), it means that the above

procedure or cautions have not been properly observed. In this case, the WDT will not operate

even though the frequency modification register is modified.

Rev. 2.00, 03/05, page 122 of 884

3.2.6 Clock Modes and Freq uency Ranges

The following table shows the operating modes and the associated frequency ranges for input

clocks.

Clock Input PLL Circuit Internal Clock*2,*3

Mode Pin

Input

Frequency

Range (MHz) PLL1 PLL2 Iφ

φφ

(MHZ)Eφ

φφ

(MHZ)Pφ

φφ

(MHZ)

CKIO

Output

(MHz)

0, 1 EXTAL or crystal

resonator*18–15.625 On On 8–

62.5 8–

31.25 8–62.5

Off On 8–

62.5 8–

31.25 8–62.5

On Off 8–

62.5 8–

15.625 8–

15.625 8–15.625

1–31.25 Off Off 1–

31.25 1–

31.25 1–31.25

2 8–15.625 Off On 8–

62.5 8–

31.25 8–62.5

1–31.25 Off 1–

31.25 1–

31.25 1–31.25

3 8–15.625 On 8–

62.5 8–

31.25 —

1–31.25 Off 1–

31.25 1–

31.25

4, 5 CKIO 16–31.25 On Off 16–

62.5 16–

31.25 16–

31.25 —

1–31.25 Off 1–

31.25 1–

31.25

6 1–31.25 Off 1–

31.25 1–

31.25

Notes: 1. When a crystal resonator is used, set the frequency in the range of 8 to 15.625 MHz.

2. Set the frequency modification regi ster so that the frequency of all internal clocks is 1

MHz or higher.

3. Use internal clock frequencies such that I φ ≥ Eφ ≥ Pφ.

Rev. 2.00, 03/05, page 123 of 884

3.2.7 Notes on Board Design

When Using an External Crystal Oscillator: Place the crystal resonator, capacitors CL1 and

CL2, and damping resistor R close to the EXTAL and XTAL pins. To prevent induction from

interfering with correct oscillation, use a common grounding point for the capacitors connected to

the resonator, and do not locate a wiring pattern near these components.

Figure 3.5 shows an example of the oscillator circuit. This is a sample oscillator circuit and in the

actual system, the values shown in the figure are affected by the environment such as noise, power

supply characteristics, or wiring patterns. These values cannot be guaranteed and should be used

as reference values. To determine the optimum oscillator circuit constants for the user system,

please consult with the crystal resonator manufacturer.

Note: The values for CL1, CL2, and the damping resistance should be determined after

consultation with the crystal resonator manufacturer.

XTALEXTAL

CL2CL1

Avoid crossing

signal lines CL1, CL2 = 20 to 22 pF

R = 0 Ω

Oscillation frequency:

15.625 MHz

Crystal resonator:

HC-49/u manufactured by

KYUSHU DENTSU CO., LTD.

Figure 3.5 Points for Attention when Using Crystal Resonator

Bypass Capacitors: As far as possible, insert a laminated ceramic capacitor of 0.01 to 0.1 µF as a

bypass capacitor for each VSS/VCC pair. Mount the by pass cap aci to rs as close as possi ble to the

LSI power supply pins, and use components with a frequency characteristic suitable for the LSI

operating frequency, as well as a suitable capacitance value.

1. VSS/VCC pairs for FP-208C and FP-208CV

a. PLL system: 9-12

b. 3 V digital system: 20-18, 26-22, 35-33, 45-42, 52-50, 60-58, 61-67, 69-66, 78-76,

79-81, 91-89, 101-99, 112-109, 113-110, 114-116, 130-132, 149-146,

150-147

c. 5 V digital system: 157-155, 169-167, 181-179, 191-193, 202-200

Rev. 2.00, 03/05, page 124 of 884

2. VSS/VCC pairs for BP-240A and BP-240AV

a. PLL system: E1, F1, F2, F4

b. 3 V digital system: H4-H2, K1-J2, N4-M2, T3-P1, W1-V1, V5-U4, W5-U6, V7-T6,

V10-V9, U10-W10, W13-U13, W17-W16, T17-U19, R19-R18,

U17-R16, L17-K17, E17-F17, F18-E19

c. 5 V digital system: B18-B19, B14-C15, D11-A11, B8-C7, C4-C5

When Using a PLL Oscillator Circuit: Keep the wiring short from the PLL VCC and VSS

connection pa ttern to the pow er supply pins, and make the pattern wi dth large, to minimize the

inductance component. Ground the oscillation stabilization capacitors C1 and C2 to VSS (PLL1)

and VSS (PLL2), respectively. Place C1 and C2 close to the CAP1 and CAP2 pins and do not

locate a wiring pattern in the vicinity.

CAP1

(PLL) V

C1 = 470 pF

C2 = 470 pF

CAP2

(PLL)

Avoid crossing

signal lines Power supply

Reference values

Figure 3.6 Points for Attention when Using PLL Oscillator Circuit

3.3 Bus Width of the CS0 Ar ea

Pins MD3 and MD4 are used to specify the bus width of the CS0 area. The pin combination and

functions are listed in table 3.6. Do not switch the MD4 and MD3 pins while they are operating.

Switching them will cause operating errors.

Table 3.6 Bus Width of the CS0 Area

MD4 MD3 Function

0 0 8-bit bus width selected

0 1 16-bit bus width selected

1 0 32-bit bus width selected

1 1 Setting prohibi ted

Rev. 2.00, 03/05, page 125 of 884

Section 4 E xception H andling

4.1 Overview

4.1.1 Types of Exception Handling and Priority Order

Exception handling is initiated by four sources: resets, address errors, interrupts, and instructions

(table 4.1). When several exception sources occur simultaneously, they are accepted and processed

according to the priority order shown in table 4.1.

Rev. 2.00, 03/05, page 126 of 884

Table 4.1 Types of Exception Handling and Priority Order

Exception Source Priority

Reset Power-on reset High

Manual reset

CPU address errorAddress

error DMA address error (DMAC and E-DMAC)

Interrupt NMI

User break

High-performance user debugging interface (H-UDI)

External interrupts (IRL1 to IRL15, IRQ0 to IRQ3 (set with

IRL3

IRL2

IRL1

IRL0

pins))

On-chip peripheral modules Direct memory access controller (DMAC)

Watchdog timer (WDT)

Compare match interrupt (part of the bus

state controller)

Ethernet controller (EtherC) and Ethernet

controller direct me mory access controller

(E-DMAC)

16-bit free-running timer (FRT)

Serial communication interface with FIFO

(SCIF)

16-bit timer pulse unit (TPU)

Serial I/O (SIO)

Instructions Trap instruction (TRAPA)

General illegal instructions (undefined code)

Illegal slot instructions (undefined code placed directly following a delayed

branch instruction*1 or i nstructions that r ewrite the PC*2)Low

Notes : 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF

2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RT E, BT, BF, TRAPA,

BF/S, BT/S, BSRF, BRAF

Rev. 2.00, 03/05, page 127 of 884

4.1.2 Exception Handl ing Opera tio ns

Exception handling sources are detected, and exception handling started, according to the timing

shown in table 4.2.

Table 4.2 Timing of Exception Source Detection and Start of Exception Handling

Exception Source Timing of Source Detection and Start of Handling

Reset Power-on reset Starts when the NMI pin is high and the

RES

pin changes from

low to hi gh

Manual reset Starts when the NMI pin is low and the

RES

pin changes from

low to hi gh

Address error Detected when instruction i s decoded and starts when the

previous executing instruction finishes executing

Interrupts Detected when instruction is decoded and starts when the

previous executing instruction finishes executing

Instructions Tr ap instruction Starts fr om the execution of a TRAPA instruction

General illegal

instructions Starts from the decoding of undefined code anytime except after

a delayed branch instruction (delay slot)

Illegal slot

instructions Starts from the decoding of undefined code pl aced directly

following a delayed branch instruction (delay slot) or of an

instruction that rewrites the PC

When exception handling starts, the CPU operates as follows:

1. Exception handling triggered by reset

The initial values of the program counter (PC) and stack pointer (SP) are fetched from the

exception vector table (PC and SP are respectively addresses H'00000000 and H'00000004 for

a power-on reset and addresses H'00000008 and H'0000000C addresses for a manual reset).

See section 4.1.3, Exception Vector Table, for more information. 0 is then written to the vector

base register (VBR) and 1111 is written to the interrupt mask bits (I3 to I0) of the status

vector table.

2. Exception handling triggered by address errors, interrupts, and instructions

SR and PC are saved to the stack address indicated by R15. For interrupt exception handling,

the interrupt priority level is written to the SR’s interrupt mask bits (I3 to I0). For address error

and instruction exception handling, the I3 to I0 bits are not affected. The start address is then

fetched from the exception vector table and the program begins running from that address.

Rev. 2.00, 03/05, page 128 of 884

4.1.3 Exception Vector Table

Before exception handling begins, the exception vector table must be written in memory. The

exception vector table stores the start addresses of exception service routines. (The reset exception

table holds the initial values of PC and SP.)

All exception sources are given different vector numbers and vector table address offsets, from

which the vector table addresses are calculated. In exception handling, the start address of the

exception service routine is fetched from the exception vector table as indicated by the vector table

address.

Table 4.3 lists the vector numbers and vector table address offsets. Table 4.4 shows vector table

address calculations.

Table 4.3 (a) Exception Vector Table

Exception Source Vector

Number Vector Table A ddr ess

Offset Vector Address

Power-on reset PC 0 H'00000000–H'00000003 Vector number × 4

SP 1 H'00000004–H'00000007

Manual reset PC 2 H'00000008–H'0000000B

SP 3 H'0000000C–H'0000000F

General illegal instruct ion 4 H'00000010–H' 00000 013

(Reserved by system) 5 H'00000014–H'00000017

VBR + (vector

number × 4)

Slot illegal instruction 6 H'00000018–H' 00000 01B

(Reserved by system) 7 H'0000001C–H'0000001F

8 H'00000020–H'00000023

CPU address error 9 H'00000024–H'00000027

DMA address error (DMAC and

E-DMAC) 10*5H'00000028–H'0000002B

Interrupt NMI 11 H'0000002C–H'0000002F

User break 12 H'00000030–H'00000033

H-UDI 13 H'00000034–H'00000037

(Reserved by system) 14

H'00000038–H'0000003B

H'0000007C–H'0000007F

Trap instruction (user vector) 32

H'00000080–H'00000083

H'000000FC–H'000000FF

Rev. 2.00, 03/05, page 129 of 884

Table 4.3 (b) Exception Processing Vector Table (IRQ Mode)

Exception Source Vector

Number Vector Table A ddr ess

Offset Vector Addresses

Interrupt IRQ0 64*2H'00000100–H'00000103

IRQ1 65*2H'00000104–H'00000107

IRQ2 66*2H'00000108–H'0000010B

IRQ3 67*2H'0000010C–H'0000010F

On-chip

peripheral

module*3

0*4

127*4

H'00000000–H'00000003

H'000001FC–H'000001FF

Table 4.3 (c) Exception Processing Vector Table (IRL Mode)

Exception Source Vector

Number Vector Table A ddr ess

Offset Vector Addresses

Interrupt IRL1*164*2H'00000100–H'00000103

IRL2*165*2H'00000104–H'00000107 VBR + (vector

number × 4)

IRL3*1

IRL4*166*2H'00000108–H'0000010B

IRL5*1

IRL6*167*2H'0000010C–H'0000010F

IRL7*1

IRL8*168*2H'00000110–H'00000113

IRL9*1

IRL10*169*2H'00000114–H'00000117

IRL11*1

IRL12*170*2H'00000118–H'0000011B

IRL13*1

IRL14*171*2H'0000011C–H'0000011F

IRL15*1

On-chip

peripheral

module*3

0*4

127*4

H'00000000–H'00000003

H'000001FC–H'000001FF

Notes: 1. When 1110 is input to the

IRL3

IRL2

IRL1

, and

IRL0

pins, an IRL1 interrupt results.

When 0000 is input, an IRL15 interrupt results.

2. External vector number fetches can be performed wi thout using the auto-vector

numbers in this table.

Rev. 2.00, 03/05, page 130 of 884

3. The vector numbers and vector table address offsets for each on-chip peripheral

module interrupt are given table 5.4, Interrupt Excepti on Vectors and Priorities, in

section 5, Interrupt Controller.

4. Vector numbers are set in the on-chip vector number register. See section 5.3, Register

Descriptions, in section 5, Interrupt Controller, and section 11, Direct Memory Access

Controller, for more information.

5. The same vector number, 10, is generated for a DMAC DMA address error and an E-

DMAC DMA address error. (See table 4.3 (a).)

Both the address error flag (AE) in the DMAC’s DMA operation register (DMAOR) and

the address error control bit (AEC) in the E-DMAC’s E-DMAC operation control register

(EDOCR) must therefore be read in the exception service routine to determine which

DMA address error has occurred.

Table 4.4 Calculating Exception Vector Table Addresses

Exception Source Vector T able Address Calculation

Power-on reset

Manual reset (Vector table address) = (vector table address offset)

= (vector number) × 4

Other exception handling (Vector table address) = VBR + (vector table address offset)

= VBR + (vector number) × 4

Note: VBR: Vector base register

Vector table address offset: See table 4.3.

Vector number: See table 4.3.

Rev. 2.00, 03/05, page 131 of 884

4.2 Resets

4.2.1 Types of Resets

Resets have the highest priority of any exception source. There are two types of resets: manual

resets and power-on resets. As table 4.5 shows, both types of resets initialize the internal status of

the CPU. In power-on resets, all registers of the on-chip peripheral modules are initialized; in

manual resets, registers of all on-chip peripheral modules except the bus state controller (BSC),

user break controller (UBC), pin function controller (PFC), and frequency modification register

(FMR) are initialized. (Use the power-on reset when turning the power on.)

Table 4.5 Types of Resets

Conditions for

Transition to Reset Status Internal Status

Type NMI Pin

RES

Pin CPU On-Chip Peripheral Modules

Power-on reset High Low Initialized Initialized

Manual reset Low Low Initialized Ini tialized except for BSC, UBC,

PFC, and frequency modification

4.2.2 Power-On Reset

When the NMI pin is high and the

RES

pin is driven low, the device performs a power-on reset.

For a reliable reset, the

RES

pin should be kept low for at least the duration of the oscillation

settling time (when the PLL circuit is halted) or for 20tpcyc (when the PLL circuit is running).

During a power-on reset, the CPU’s internal state and all on-chip peripheral module registers are

initialized. See Appendix B, Pin States, for the state of individual pins in the power-on reset state.

In a power-on reset, power-on reset exception handling starts when the NMI pin is kept high and

the

RES

pin is first driven low for a set period of time and then returned to high. The CPU will

then operate as follows:

1. The initial value (execution start address) of the program counter (PC) is fetched from the

exception vector table.

2. The initial value of the stack pointer (SP) is fetched from the exception vector table.

3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)

of the status register (SR) are set to H'F (1111).

4. The values fetched from the exception vector table are set in the program counter (PC) and

stack pointer (SP), and the program begi ns executing .

Rev. 2.00, 03/05, page 132 of 884

4.2.3 Manual Reset

When the NMI pin is low and the

RES

pin is driven low, the device executes a manual reset. For a

reliable reset, the

RES

pin should be kept low for at least 20 clock cycles. During a manual reset,

the CPU’s internal state is initialized. All on-chip peripheral module registers are initialized,

except for the bus state controller (BSC), user break controller (UBC), and pin function controller

(PFC) registers, and the frequency modification register (FMR). When the chip enters the manual

reset state in the middle of a bus cycle, manual reset exception handling does not start until the bus

cycle has ended. Thus, manual resets do not abort bus cycles. See appendix B, Pin States, for the

state of individual pins in the manual reset state.

In a manual reset, manual reset exception handling starts when the NMI pin is kept low and the

RES

pin is first kept low for a set period of time and then returned to high. The CPU will then

operate in the same way as for a power-on reset.

4.3 Address Errors

4.3.1 Sources of Address Errors

Address errors occur when instructions are fetched or data read or written, as shown in table 4.6.

Rev. 2.00, 03/05, page 133 of 884

Table 4.6 Bus Cycles and Address Errors

Bus Cycle

Type Bus

Master Bus Cycle Description Address Errors

CPU Instruction fetched from even address None (normal)

Instruction

fetch Instruction fetched from odd address Address error

occurs

Instruction fetched from other than on-chip peripheral

module space None (normal)

Instruction fetched from on-chip peripheral module

space Address error

occurs

Word data accessed from even address None (normal)Data

read/write CPU or

DMAC,

E-DMAC Word data accessed from odd address Address error

occurs

Longword data accessed from a longword boundary None (normal)

Longword data accessed from other than a longword

boundary Address error

occurs

Access of cache purge space, address array read/write

space, on-chip peripheral module space, or

synchronous DRAM mode setting space by PC-relative

addressing

Address error

occurs

Access of cache purge space, address array read/write

space, data array read/write space, on-chip peripheral

module space, or synchronous DRAM mode setting

space by a TAS.B instruction

Address error

occurs

Byte, word, or longword data accessed in on-chip

peripheral module space at addresses H'FFFFFC00 to

H'FFFFFCFF

None (normal)

Longword data accessed in on-chip periphera l module

space at addresses H'FFFFFE00 to H'FFFFFEFF Address error

occurs

Word or byte data accessed in on-chip peripheral

module space at addresses H'FFFFFE00 to

H'FFFFFEFF

None (normal)

Byte data accessed in on-chip peripheral module space

at addresses H'FFFF0000 to H'FFFFF0FF or

H'FFFFFF00 to H'FFFFFFFF

Address error

occurs

Wor d or longw ord data accessed in on-chip peripheral

module space at addresses H'FFFF0000 to

H' FFFFF0FF or H'FFFFFF00 to H 'FFFFFFFF

None (normal)

Notes: 1. Address errors do not occur during the synchronous DRAM mode register write cycle.

2. 16-byte DMAC transfers use longword accesses.

Rev. 2.00, 03/05, page 134 of 884

4.3.2 Address Error Exception Handling

When an address error occurs, address error exception handling begins after the end of the bus

cycle in which the error occurred and completion of the executing instruction. The CPU operates

as follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the last instruction executed .

3. The exception service routine start address is fetched from the exception vector table entry that

corresponds to the address error that occurred, and the program starts executing from that

address . The jump that occu rs is not a del ay ed branch.

Note: The same vector number, 10, is generated for a DMAC DMA address error and an E-

DMA C DMA address erro r. (See table 4.3 (a).)

Both the address error flag (AE) in the DMAC’s DMA operation register (DMAOR) and

the address error control bit (AEC) in the E-DMAC’s E-DMAC operation control register

(EDOCR) must therefore be read in the exception service routine to determine which

DMA address error has occurred.

Rev. 2.00, 03/05, page 135 of 884

4.4 Interrupts

4.4.1 Interrupt Sources

Table 4.7 shows the sources that initiate interrupt exception handling. These are divided into NMI,

user breaks, H-UDI, IRL, IRQ, and on-chip peripheral modules.

Table 4.7 Types of Interrupt Sources

Type Request Source Number of Sources

NMI NMI pin (external input) 1

User break User break controller (UBC) 1

H-UDI High-performance user debugging interface

(H-UDI) 1

IRL IRL1 to IRL15 (external input) 15

IRQ IRQ0 to IRQ3 (external input) 4

On-chip peripheral module Direct memory access controller (DMAC) 2

Ethernet controller (EtherC) and Ethernet

controller direct me mory access controller

(E-DMAC)

16-bit free-running timer (FRT) 3

Watchdog timer (WDT) 1

Bus state controller (BSC) 1

Serial I/O (SIO) 4

Serial communication interface with FIFO

(SCIF) 4

16-bit timer pulse unit (TPU) 13

Each interrupt source is allocated a different vector number and vector table address offset. See

table 5.4, Interrupt Exception Vectors and Priority Order, in section 5, Interrupt Controller, for

more information.

Rev. 2.00, 03/05, page 136 of 884

4.4.2 Interrup t Priority Levels

The interrupt priority order is predetermined. When multiple interrupts occur simultaneously, the

interrup t control ler (IN TC) dete rmi nes their rela tiv e priorities and beg i ns excep tion handl ing

accordingly.

The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest

and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is

always accepted. The user break interrupt priority level is 15 and IRL interrupts have priorities of

1 to 15. On-chip peripheral module interrupt priority levels can be set freely using the INTC’s

interrupt priority level setting registers A to E (IPRA to IPRE) as shown in table 4.8. The priority

levels that can be set are 0 to 15. Level 16 cannot be set. For more information on IPRA to IPRE,

see sections 5.3.1, Interrupt Priority Level Setting Register A (IPRA), to 5.3.5, Interrupt Priority

Level Setting Register E (IPRE).

Table 4.8 Interrup t Prior ity Order

Type Priority Level Comment

NMI 16 Fixed priority level. Cannot be masked

User break 15 Fixed priority level

H-UDI 15 Fixed priority level

IRL 1 to 15 Set with

IRL3

IRL0

pins

IRQ 0 to 15 Set with interrupt pr iority level setting register C

(IPRC)

On-chip peripheral module 0 to 15 Set with interrupt priority level setting registers A, B,

D, and E (IPRA, IPRB, IPRD, IPRE)

4.4.3 Interrupt Exception Handling

When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI

is always accepted, but other interrupts are only accepted if they have a priority level higher than

the priority level set in the interrupt mask bits (I3 to I0) of the status register (SR).

When an interrupt is accepted, exception handling begins. In interrupt exception handling, the

CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted

interrupt is written to SR bits I3 to I0. For NMI, however, the priority level is 16, but the value set

in I3 to I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from

the exception vector table for the accepted interrupt, that address is jumped to and execution

begins. For more information about interrupt exception handling, see section 5.4, Interrupt

Operation.

Rev. 2.00, 03/05, page 137 of 884

4.5 Excepti on s Tr ig gered by Instruct i ons

4.5.1 Instruction-Triggered Exception Types

Exception handling can be triggered by a trap instruction, general illegal instruction or illegal slot

instruction, as shown in table 4.9.

Table 4.9 Types of Exceptions Triggered by Instructions

Type Source Instruction Comment

Tra p instru c tion TRA PA —

Illegal slot

instruction Undefined code placed

imm ediately after a delayed

branch instruction (delay slot)

and instructions that rewrite the

Delayed branch instructions: JMP, JSR,

BRA, BSR, RT S, RTE, BF/S, BT /S, BSRF,

BRAF

Instructions that rewrite the PC: JMP, JSR,

BRA, BSR, RTS, RTE, BT, BF , TRAPA,

BF/S, BT/S, BSRF, BRAF

General illegal

instruction Undefined code anywhere

besides in a delay slot —

4.5.2 Trap Instructions

When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU

operates as follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the TRAPA instruction.

3. The exception service routine start address is fetched from the exception vector table entry that

corresponds to the vector number specified by the TRAPA instruction. That address is jumped

to and the program starts executing. The jump that occurs is not a delayed branch.

Rev. 2.00, 03/05, page 138 of 884

4.5.3 Illegal Slot Instructions

An instruction placed immediately after a delayed branch instruction is said to be placed in a delay

slot. If the instruction placed in the delay slot is undefined code, illegal slot exception handling

begins when the undefined code is decoded. Illegal slot exception handling is also started when an

instruction that rewrites the program counter (PC) is placed in a delay slot. The exception handling

starts when the instruction is decoded. The CPU handles an illegal slot instruction as follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the

delayed branch instruction immediately before the undefined code or the instruction that

rew rites the PC.

3. The exception service routine start address is fetched from the exception vector table entry that

corresponds to the exception that occurred. That address is jumped to and the program starts

executing. The jump that occurs is not a delayed branch.

4.5.4 General Illegal Instructions

When undefined code placed anywhere other than immediately after a delayed branch instruction

(i.e., in a delay slot) is decoded, general illegal instruction exception handling starts. The CPU

handles general illegal instructions in the same way as illegal slot instructions. Unlike processing

of illegal slot instructions, however, the program counter value saved is the start address of the

undefined code.

Rev. 2.00, 03/05, page 139 of 884

4.6 When Exception Sources Are Not Accepted

When an address error or interrupt is generated after a delayed branch instruction or interrupt-

disabled instruction, it is sometimes not immediately accepted but is stored instead, as described in

table 4.10. When this happens, it will be accepted when an instruction for which exception

acceptance is possible is decoded.

Table 4.10 Exception Source Generation Immediately after a Delayed Branch Instruction

or Interrupt-Disabled Instruction

Exception Source

Point of Occurrence Address Error Interrupt

Immediately after a delayed br anch instruction*1Not accepted Not accepted

Immediately after an interrupt-disabled instruction*2Accepted Not accepted

A repeat loop comprising up to three instructions (instruction

fetch cycle not generated)

First instruction or last three instructions in a repeat loop

containing four or more instructions

Not accepted Not accepted

Fourth from la st instruction in a repeat loop containing four or

more instructions Accepted Not accepted

Notes : 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF

2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L

4.6.1 Immediately after a Delayed Branch Instruction

When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded,

neither address errors nor interrupts are accepted. The delayed branch instruction and the

instruction located immediately after it (delay slot) are always executed consecutively, so no

exception handling occurs between the two.

4.6.2 Immediately after an Interrupt-Disabled Instruction

When an instruction immediately following an interrupt-disabled instruction is decoded, interrupts

are not accep ted. Addr ess er ro rs are acc ep ted.

Rev. 2.00, 03/05, page 140 of 884

4.6.3 Instructions in Repeat Loops

If a repeat loop comprises up to three instructions, neither exceptions nor interrupts are accepted.

If a repeat loop contains four or more instructions, neither exceptions nor interrupts are accepted

during the execution cycle of the first instruction or the last three instructions. If a repeat loop

contains four or more instructions, address errors only are accepted during the execution cycle of

the fourth from last instruction. For more information, see the SH-1/SH-2/SH-DSP Programming

Manual.

A. All interrupts and address errors are accepted.

B. Address errors only are accepted.

C. No interrupts or address errors are accepted.

When RC ≥ 1

When RC = 0

All interrupts and address errors are accepted.

(1) One instruction ←

←

instr0

instr1

instr2

Start (End):

(4) Four or more instructions

←

A or C (on return from instr n)

←

instr0

instr1

instr n-3

instr n-2

instr n-1

instr n

instr n+1

Start:

End:

(2) Two instructions

←

instr0

instr1

instr2

instr3

Start:

End:

(3) Three instructions

←

instr0

instr1

instr2

instr3

instr4

Start:

End:

Figure 4.1 Interrupt Acceptance Restrictions in Repeat Mode

Rev. 2.00, 03/05, page 141 of 884

4.7 Stack Status after Exception Handling

The status of the stack after exception handling ends is as shown in table 4.11.

Table 4.11 Stack Status after Excep tion Handlin g

Type Stack Status

Address error SP →Address of instruct ion after ex ecuted instructio n 32 bits

SR 32 bits

Tra p instru c tion SP →Address of instruction after TRAPA instruction 32 bits

SR 32 bits

General illegal instruct ion SP →Start address of illegal instruction 32 bits

SR 32 bits

Interrupt SP →Address of instruct ion after executed instruc tion 32 bits

SR 32 bits

Illegal slot instruction SP →Jump destination address of delayed branch instruction 32 bits

SR 32 bits

Rev. 2.00, 03/05, page 142 of 884

4.8 Usage Notes

4.8.1 Value of Stack Pointer (SP)

The value of the stack pointer must always be a multiple of four, otherwise an address error will

occur when the stack is accessed during exception handling.

4.8.2 Value of Vector Base Register (VBR)

The value of the vector base register must always be a multiple of four, otherwise an address error

will occur when the vector table is accessed during exception handling.

4.8.3 Address Errors Caused by Stacking of Address Error Exception Handling

If the stack pointer value is not a multiple of four, an address error will occur during stacking of

the exception handling (interrupts, etc.). Address error exception handling will begin after the

original exception handling ends, but address errors will continue to occur. To ensure that address

error exception handling does not go into an endless loop, no address errors are accepted at that

point. This allows program control to be shifted to the address error exception service routine and

enables error handling to be carried out.

When an address error occurs during exception handling stacking, the stacking bus cycle (write) is

executed. In stacking of the status register (SR) and program counter (PC), the SP is decremented

by 4 for both, so the value of SP will not be a multiple of four after the stacking either. The

address value output during stacking is the SP value, so the address where the error occurred is

itself output. This means that the write data stacked will be undefined.

4.8.4 Manual Reset during Register Access

Do not initiate a manual reset during access of a bus state controller (BSC), user break controller

(UBC), or pin function controller (PFC) register, or the frequency modification register (FMR),

otherwise a write error may result.

Rev. 2.00, 03/05, page 143 of 884

Section 5 Interrupt Co ntroller (INTC)

5.1 Overview

The interrupt controller (INTC) ascertains the priority order of interrupt sources and controls

interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt

which allow the user to set the order of priority in which interrupt requests are handled.

5.1.1 Features

The INTC has the following features:

• Sixteen interrupt priority levels can be set

By setting the five interrupt priority registers, the priorities of on-chip peripheral module

interrupts can be selected at 16 levels for different request sources.

• Vector numbers for on-chip peripheral module interrupt can be set

By setting the 24 vector number setting registers, the vector numbers of on-chip peripheral

module interrupts can be set to values from 0 to 127 for different request sources.

• The IRL interrupt vector number setting method can be selected: Either of two modes can be

selected by a register setting: auto-vector mode in which vector numbers are determined

internally, and external vector mode in which vector numbers are set externally.

• IRQ interrupt settings can be made (low level, rising-, falling-, or both-edge detection)

Rev. 2.00, 03/05, page 144 of 884

5.1.2 Block Diagram

Figure 5.1 shows a block diagram of the INTC.

CPU

Interrupt request

Com-

parator

Priority

decision

logic

(Interrupt request)

ICR

IRQCSR IPRA–IPRE

VCRWDT, VCRA–VCRU

Module bus Bus

interface

Internal bus

I3 I2 I1 I0

INTC

NMI

IR3–IR0

A3–A0

IVECF

D7–D0

UBC

H-UDI

DMAC

FRT

WDT

REF

SCIF

TPU

SIO

E-DMAC

Input/

output

control

Vector

number Vector

number DMAC

Peripheral bus

VCRWDT

IPR

UBC: User break controller

H-UDI: High-performance user debugging interface

DMAC: Direct memory access controller

FRT: 16-bit free-running timer

WDT: Watchdog timer

REF: Refresh request within bus state controller

SCIF: Serial communication interface with FIFO

TPU: 16-bit timer pulse unit

SIO: Serial I/O

E-DMAC: Ethernet controller direct memory

access controller

EtherC: Ethernet controller

ICR: Interrupt control register

IRQCSR: IRQ control/status register

IPRA–IPRE: Interrupt priority level setting

registers A–E

VCRWDT: Vector number setting register WDT

VCRA–VCRU: Vector number setting registers A–U

SR: Status re

ister

(Including EtherC

interrupt)

Figure 5.1 INTC Block Diagram

Rev. 2.00, 03/05, page 145 of 884

5.1.3 Input/Output Pins

Table 5.1 shows the INTC pin configuration.

Table 5.1 Pin Configura tion

Name Abbreviation I/O Function

Nonmaskable interrupt input pin NMI Input Input of nonmaskable interrupt request

signal

Level request interrup t input pins

IRL3

IRL0

Input Input of maskable interrupt request

signals

Interrupt acceptance level output

pins A3 to A0 Output In external vector mode, output an

interrupt level signal when an IRL/IRQ

interrupt is accepted

External vector fetch pi n

IVECF

Output Indicates external vector read cycle

External vector number input pins D7 to D0 Input Input external vector number

5.1.4 Register Configuration

The INTC has the 31 registers shown in table 5.2. These registers perform various INTC functions

including setting interrupt priority, and controlling external interrupt input signal detection.

Table 5.2 Register Configurat ion

Name Abbr. R/W Initial

Value Address Access

Size

Interrupt priority register setting register A IPRA R/W H'0000 H'FFFFFEE2 8, 16

Interrupt priority register setting register B IPRB R/W H'0000 H'FFFFFE60 8, 16

Interrupt priority register setting register C IPRC R/W H'0000 H'FFFFFEE6 8, 16

Interrupt priority register setting register D IPRD R/W H'0000 H'FFFFFE40 8, 16

Interrupt priority register setting register E IPRE R/W H'0000 H'FFFFFEC0 8, 16

Vector number setting register A VCRA R/W H'0000 H'FFFFFE62 8, 16

Vector number setting register B*3VCRB R/W H'0000 H'FFFFFE64 8, 16

Vector number setting register C VCRC R/W H'0000 H'FFFFFE66 8, 16

Vector number setting register D VCRD R/W H'0000 H'FFFFFE68 8, 16

Vector number setting register E VCRE R/W H'0000 H'FFFFFE42 8, 16

Vector number setting register F VCRF R/W H'0000 H'FFFFFE44 8, 16

Vector number setting register G VCRG R/W H'0000 H'FFFFFE46 8, 16

Rev. 2.00, 03/05, page 146 of 884

Name Abbr. R/W Initial

Value Address Access

Size

Vector number setting register H VCRH R/W H'0000 H'FFFFFE48 8, 16

Vector number setting register I VCRI R/W H'0000 H'FFFFFE4A 8, 16

Vector number setting register J VCRJ R/W H'0000 H'FFFFFE4C 8, 16

Vector number setting register K VCRK R/W H'0000 H'FFFFFE4E 8, 16

Vector number setting register L VCRL R/W H'0000 H'FFFFFE 50 8, 16

Vector number setting register M VCRM R/W H'0000 H'FFFFFE52 8, 16

Vector number setting register N VCRN R/W H'0000 H'FFFFFE54 8, 16

Vector number setting register O VCRO R/W H'0000 H'FFFFFE56 8, 16

Vector number setting register P VCRP R/W H'0000 H'FFFFFEC2 8, 16

Vector number setting register Q VCRQ R/W H'0000 H'FFFFFEC4 8, 16

Vector number setting register R VCRR R/W H'0000 H'FFFFFEC6 8, 16

Vector number setting register S VCRS R/W H'0000 H'FFFFFEC8 8, 16

Vector number setting register T VCRT R/W H'0000 H'FFFFFECA 8, 16

Vector number setting register U VCRU R/W H'0000 H'FFFFFECC 8, 16

Vector number setting register WDT VCRWDT R/W H'0000 H'FFFFFEE4 8, 16

Vector number setting register DMA0*4VCRDMA0 R/W Undefined H'FFFFFFA0 32

Vector number setting register DMA1*4VCRDMA1 R/W Undefined H'FFFFFFA8 32

Interrupt control register ICR R/W H'8000/

H'0000*1H'FFFFFEE0 8, 16

IRQ control/status register IRQCSR R/W *2H'FFFFFEE8 8, 16

Notes: 1. The value when the NMI pin is high is H'8000; when the NMI pin is low, it is H'0000.

2. When pins

IRL3

IRL0

are high, bits 7 to 4 in IRQCSR are set to 1. When pins

IRL3

IRL0

are low, bits 7 to 4 in IRQCSR are cleared to 0. The initial value of bits other than

7 to 4 is 0.

3. In the SH7615, VCRB is a reserved register and must not be accessed.

4. See section 11, Direct Memory Access Controller (DMAC), for more information on

VCRDMA0, and VCRDMA1.

5.2 Interrupt Source s

There are five types of interrupt sources: NMI, user breaks, H-UDI, IRL/IRQ and on-chip

peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the

lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it.

Rev. 2.00, 03/05, page 147 of 884

5.2.1 NMI Interrupt

The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by

edge. Use the NMI edge select bit (NMIE) in the interrupt control register (ICR) to select either

the rising or falling edge. NMI interrupt exception handling sets the interrupt mask level bits (I3 to

I0) in the status register (SR) to level 15.

5.2.2 User Break Interrupt

A user break interrupt has priority level 15 and occurs when the break condition set in the user

break controller (UBC) is satisfied. User break interrupt exception handling sets the interrupt mask

level bits (I3 to I0) in the status register (SR) to level 15. For more information about the user

break interrupt, see section 6, User Break Controller.

5.2.3 H-UDI Interrupt

The H-UDI interrupt has a priority level of 15, and is generated when an H-UDI interrupt

instruction is serially input. H-UDI interrupt exception processing sets the interrupt mask bits (I3

to I0) in the status register (SR) to level 15. See section 17, High-Performance User Debugging

Interface (H-UDI), for details of the H-UDI interrupt.

5.2.4 IRL Interrupts

IRL interrupts are requested by input from pins

IRL3

IRL0

. Fifteen interrupts, IRL15 to IRL1,

can be input externally via pins

IRL3

IRL0

. The priority levels of interrupts IRL15 to IRL0 are

15 to 1, respectively, and their vector numbers are 71 to 64. Set the vector numbers with the

interrupt vector mode select (VECMD) bit of the interrupt control register (ICR) to enable external

input. External input of vector numbers consists of vector numbers 0 to 127 from the external

vector input pins (D7 to D0). When an external vector is used, 0 is input to D7. Internal vectors

are called auto-vectors and vectors input externally are called external vectors. Table 5.3 lists IRL

priority levels and auto vector numbers.

When an IRL interrupt is accepted in external vector mode, the IRL interrupt level is output from

the interrupt acceptance level output pins (A3 to A0). The external vector fetch pin (

IVECF

) is

also asserted. The external vector number is read from pins D7 to D0 at this time.

IRL interrupt exception processing sets the interrupt mask level bits (I3 to I0) in the status register

(SR) to the priority level value of the IRL interrupt that was accepted.

Rev. 2.00, 03/05, page 148 of 884

5.2.5 IRQ Interrupts

An IRQ interrupt is requested when the external interrupt vector mode select bit (EXIMD) of the

interrupt control register (ICR) is set to 1. An IRQ interrupt corresponds to input at one of pins

IRL3

IRL0

. Low-level sensing or rising/falling/both-edge sensing can be selected

independently for each pin by the IRQ sense select bits (IRQ31S to IRQ00S) in the IRQ

control/status register (IRQCSR), and a priority level of 0 to 15 can be selected independently for

each pin by means of interrupt priority register C (IPRC). Set the interrupt vector mode select bit

(VECMD) of the interrupt control register (ICR) to enable external input of vector numbers.

External vector numbers are 0 to 127, and are input to the external vector input pins (D7 to D0)

during the interrupt vector fetch bus cycle. When an external vector is used, 0 is input to D7.

When an IRQ interrupt is accepted in external vector mode, the IRQ interrupt priority level is

output from the interrupt acceptance level output pins (A3 to A0). The external vector fetch signal

(

IVECF

) is also asserted . The ex ternal vecto r numb er is read from si g nal s D7 to D0 at this tim e.

IRQ interrupt exception processing sets the interrupt mask bits (I3 to I0) in the status register (SR)

to the priority level value of the IRQ interrupt that was accepted.

Table 5.3 IRL Interrupt Priority Levels and Auto-Vector Numbers

IRL3 IRL2 IRL1 IRL0

Priority

Level Vector

Number

00001571

114

101370

112

1001169

110

10968

1000767

10566

100365

10164

Rev. 2.00, 03/05, page 149 of 884

An example of connections for external vector mode interrupts is shown in figure 5.2, and an

example of connections for auto-vector mode interrupts in figure 5.3.

Chip

Priority

encoder

Interrupt

requests

Vector number

generator

circuit

4IRL0–IRL3

IRL0–IRL3

D0–D7

A0–A3

IVECF

D0–D7

Figure 5.2 Example of Connections for External Vector Mode Interrupts

Chip

Priority

encoder

Interrupt

requests

4IRL0–IRL3

IRL0–IRL3

Figure 5.3 Example of Connections for Auto-Vector Mode Interrupts

Figures 5.4 to 5.7 show the interrupt vector fetch cycle for the external vector mode. During this

cycle,

CS0

CS4

stay high. A24 to A4 output undefined values. The

WAIT

pin is sampled, but

programmable waits are not valid.

Rev. 2.00, 03/05, page 150 of 884

CKIO

CS0–CS4

A3–A0

IVECF

RD/WR

D7–D0

T2T3T4

Vector number input

High

Accepted interrupt level

Figure 5.4 External Vector Fetch (Iφ

φφ

φ:Eφ

φφ

φ = 1:1)

CKIO

CS0–CS4

A3–A0

IVECF

RD/WR

D7–D0

High

Vector number input

Accepted interrupt level

Figure 5.5 External Vector Fetch (Iφ

φφ

φ:Eφ

φφ

φ ≠

≠≠

≠ 1:1)

Rev. 2.00, 03/05, page 151 of 884

CKIO

CS0–CS4

A3–A0

IVECF

RD/WR

D7–D0

WAIT

Tw T

Vector number input

Accepted interrupt level

High

Figure 5.6 External Vector Fetch (Iφ

φφ

φ:Eφ

φφ

φ = 1:1 (

WAIT

Input))

CKIO

S0–CS4

A3–A0

IVECF

RD/WR

D7–D0

WAIT

Accepted interrupt level

High

Vector number input

Figure 5.7 External Vector Fetch (Iφ

φφ

φ:Eφ

φφ

φ ≠

≠≠

≠ 1:1 (

WAIT

Input))

Rev. 2.00, 03/05, page 152 of 884

5.2.6 On-chip Periph era l Module Inte rrup ts

On-chip peripheral module interrupts are interrupts generated by the following nine on-chip

peripheral modules:

• Direct memory access controller (DMAC)

• Bus state controller (BSC)

• Watchdog timer (WDT)

• 16-bit free-running timer (FRT)

• Ethernet controller direct memory access controller (E-DMAC) (Including EtherC interrupt)

• 16-bit timer pulse unit (TPU)

• Serial communication interface with FIFO (SCIF)

• Serial I/O (SIO)

A different interrupt vector is assigned to each interrupt source, so the exception service routine

does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be

assigned to individual on-chip peripheral modules in interrupt priority registers A, B, D, and E

(IPRA, IPRB, IPRD, IPRE). On-chip peripheral module interrupt exception handling sets the

interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the on-

chip peripheral module interrupt that was accepted.

5.2.7 Interrupt Exception Vectors and Priority Order

Table 5.4 lists interrupt sources and their vector numbers, vector table address offsets and interrupt

priorities.

Each interrupt source is allocated a different vector number and vector table address offset. Vector

table addresses are calculated from vector numbers and vector table address offsets. In interrupt

exception handling, the exception service routine start address is fetched from the vector table

entry indicated by the vector table address. See table 4.4, Calculating Exception Vector Table

Addresses, in section 4, Exception Handling, for more information on this calculation.

IRL interrupts IRL15 to IRL1 have interrupt priority levels of 15 to 1, respectively. IRQ interrupt

and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each

module by setting interrupt priority registers A to E (IPRA to IPRE). The ranking of interrupt

sources for IPRA to IPRE, however, must be the order listed under Priority within IPR Setting

Unit in table 5.4 and cannot be changed. A reset assigns priority level 0 to on-chip peripheral

module interrupts. If the same priority level is assigned to two or more interrupt sources and

interrupts from those sources occur simultaneously, their priority order is the default priority order

indicated at the right in table 5.4.

Rev. 2.00, 03/05, page 153 of 884

Table 5.4 (a) Interrupt Exception Vectors and Priority Order (IRL Mode)

Vectors

Interrupt Source Vector

No.

Vector

Table

Address

Interrupt

Priority

Order

(Initial

Value) IPR (Bit

Numbers)

Priority

within

IPR

Setting

Unit VCR (Bit

Numbers) Default

Priority

NMI 11 16 ——— High

User break 12 15 ———

H-UDI 13

VBR +

(vector No.

× 4) 15 ———

IRL15*471*115 ———

IRL14*414 ———

IRL13*470*113 ———

IRL12*412 ———

IRL11*469*111 ———

IRL10*410 ———

IRL9*468*19———

IRL8*48———

IRL7*467*17———

IRL6*46———

IRL5*466*15———

IRL4*44———

IRL3*465*13———

IRL2*42———

IRL1*464*11———

DMAC0 Transfer

end 0–127*215–0 (0) IPRA

(11–8) High

Low

VCRDMA0

(6–0)

DMAC1 Transfer

end 0–127*215–0 (0) High

Low

VCRDMA1

(6–0)

Low

Rev. 2.00, 03/05, page 154 of 884

Vectors

Interrupt Source Vector

No.

Vector

Table

Address

Interrupt

Priority

Order

(Initial

Value) IPR (Bit

Numbers)

Priority

within

IPR

Setting

Unit VCR (Bit

Numbers) Default

Priority

WDT ITI 0–127*2VBR +

(vector No.

× 4)

15–0 (0) IPRA

(7–4) High

Low

VCRWDT

(14–8) High

REF*3CMI 0–127*215–0 (0) High

Low

VCRWDT

(6–0)

E-DMAC EINT*60–127*215–0 (0) High VCRA (14–8)

Reserved VCRB (14–0)*5

IPRB

(15–12)

Low

FRT ICI 0–127*215–0 (0) High VCRC (14–8)

OCI 0–127*2VCRC (6–0)

OVI 0–127*2

IPRB

(11–8)

Low VCRD (14–8)

TPU0 TGI0A 0–127*215–0 (0) High VCRE (14–8)

TGI0B 0–127*2VCRE (6–0)

TGI0C 0–127*2VCRF ( 14–8)

TGI0D 0–127*2VCRF ( 6–0)

TCI0V 0–127*2

IPRD

(15–12)

Low VCRG (14–8)

TPU1 TGI1A 0–127*215–0 (0) High VCRH ( 14–8)

TGI1B 0–127*2VCRH (6–0)

TCI1V 0–127*2VCRI (14 –8)

TCI1U 0–127*2

IPRD

(11–8)

Low VCRI (6–0)

TPU2 TGI2A 0–127*215–0 (0) High VCRJ (14–8)

TGI2B 0–127*2VCRJ (6–0)

TCI2V 0–127*2VCRK (14–8)

TCI2U 0–127*2

IPRD

(7–4)

Low VCRK (6–0) Low

Rev. 2.00, 03/05, page 155 of 884

Vectors

Interrupt Source Vector

No.

Vector

Table

Address

Interrupt

Priority

Order

(Initial

Value) IPR (Bit

Numbers)

Priority

within

IPR

Setting

Unit VCR (Bit

Numbers) Default

Priority

SCIF1 ERI1 0–127*215–0 (0) High VCRL (14–8) High

RXI1 0–127*2VCRL (6–0)

BRI1 0–127*2

VBR +

(vector No.

× 4) VCRM (14–8)

TXI1 0–127*2

IPRD

(3–0)

Low VCRM (6–0)

SCIF2 ERI2 0–127*215–0 (0) High VCRN (14–8)

RXI2 0–127*2VCRN (6–0)

BRI2 0–127*2VCRO (1 4 –8)

TXI2 0–127*2

IPRE

(15–12)

Low VCRO (6–0)

SIO0 RERI0 0–127*215–0 (0) High VCRP (14–8)

TERI0 0–127*2VCRP (6–0)

RDFI0 0–127*2VCRQ (14 –8)

TDEI0 0–127*2

IPRE

(11–8)

Low VCRQ (6–0)

SIO1 RERI1 0–127*215–0 (0) High VCRR (14–8)

TERI1 0–127*2VCRR (6–0)

RDFI1 0–127*2VCRS (14–8)

TDEI1 0–127*2

IPRE

(7–4)

Low VCRS (6–0)

SIO2 RERI2 0–127*215–0 (0) High VCRT (14–8)

TERI2 0–127*2VCRT (6–0)

RDFI2 0–127*2VCRU (14–8)

TDEI2 0–127*2

IPRE

(3–0)

Low VCRU (6 –0)

Reserved 128–255 ————— Low

Notes: 1. An external vector number fetch can be performed without using the auto-vector

numbers shown in this table. The external vector numbers are 0 to 127.

2. Vector numbers are set in the on-chip vector number register.

3. REF is the refresh control unit within the bus state controller.

4. Set to IRL1 to IRL15 or IRQ0 to IRQ3 by the EXIMD bit in ICR.

5. In the SH7615, VCRB is a reserved register and must not be accessed.

6. The E-DMAC interrupt (EINT) is the OR of those of the 19 interrupt sources i n the

EtherC/E-DMAC status r egister (EESR) th at are enabled by the EtherC/E-DMAC sta tus

interrupt permission regis ter (EESIPR). As t he three status bit s in the EtherC status

input to the INTC as the OR of a maximum of 22 interrupt sources.

Rev. 2.00, 03/05, page 156 of 884

Table 5.4 (b) Interrupt Exception Vectors and Priority Order (IRQ Mode)

Vectors

Interrupt Source Vector

No.

Vector

Table

Address

Interrupt

Priority

Order

(Initial

Value) IPR (Bit

Numbers)

Priority

within

IPR

Setting

Unit VCR (Bit

Numbers) Default

Priority

NMI 11 16 ——— High

User break 12 15 ———

H-UDI 13

VBR +

(vector No.

× 4) 15 ———

IRQ0*464*115–0 (0) IPRC

(15–12) ——

IRQ1*465*115–0 (0) IPRC

(11–8) ——

IRQ2*466*115–0 (0) IPRC

(7–4) ——

IRQ3*467*115–0 (0) IPRC

(3–0) ——

DMAC0 Transfer

end 0–127*215–0 (0) IPRA

(11–8) High

Low

VCRDMA0

(6–0)

DMAC1 Transfer

end 0–127*215–0 (0) High

Low

VCRDMA1

(6–0)

WDT ITI 0–127*215–0 (0) IPRA

(7–4) High

Low

VCRWDT

(14–8)

REF*3CMI 0–127*215–0 (0) High

Low

VCRWDT

(6–0)

Low

Rev. 2.00, 03/05, page 157 of 884

Vectors

Interrupt Source Vector

No.

Vector

Table

Address

Interrupt

Priority

Order

(Initial

Value) IPR (Bit

Numbers)

Priority

within

IPR

Setting

Unit VCR (Bit

Numbers) Default

Priority

E-DMAC EINT*60–127*215–0 (0) High VCRA (14–8) High

Reserved

VBR +

(vector No.

× 4)

IPRB

(15–12)

Low VCRB

(14–0)*5

FRT ICI 0–127*215–0 (0) High VCRC (14–8)

OCIA/B 0–127*2VCRC (6–0)

OVI 0–127*2

IPRB

(11–8)

Low VCRD (14–8)

TPU0 TGI0A 0–127*215–0 (0) High VCRE (14–8)

TGI0B 0–127*2VCRE (6–0)

TGI0C 0–127*2VCRF ( 14–8)

TGI0D 0–127*2VCRF ( 6–0)

TCI0V 0–127*2

IPRD

(15–12)

Low VCRG (14–8)

TPU1 TGI1A 0–127*215–0 (0) High VCRH (14–8)

TGI1B 0–127*2VCRH (6–0)

TCI1V 0–127*2VCRI (14 –8)

TCI1U 0–127*2

IPRD

(11–8)

Low VCRI (6–0)

TPU2 TGI2A 0–127*215–0 (0) High VCRJ (14–8)

TGI2B 0–127*2VCRJ (6–0)

TCI2V 0–127*2VCRK (14–8)

TCI2U 0–127*2

IPRD

(7–4)

Low VCRK (6–0)

SCIF1 ERI1 0–127*215–0 (0) High VCRL (14–8)

RXI1 0–127*2VCRL (6–0)

BRI1 0–127*2VCRM (14–8)

TXI1 0–127*2

IPRD

(3–0)

Low VCRM (6–0)

SCIF2 ERI2 0–127*215–0 (0) Hig h VCRN (14–8)

RXI2 0–127*2VCRN (6–0)

BRI2 0–127*2VCRO (1 4 –8)

TXI2 0–127*2

IPRE

(15–12)

Low VCRO (6–0) Low

Rev. 2.00, 03/05, page 158 of 884

Vectors

Interrupt Source Vector

No.

Vector

Table

Address

Interrupt

Priority

Order

(Initial

Value) IPR (Bit

Numbers)

Priority

within

IPR

Setting

Unit VCR (Bit

Numbers) Default

Priority

SIO0 RERI0 0–127*215–0 (0) High VCRP (14–8) High

TERI0 0–127*2VCRP (6–0)

RDFI0 0–127*2

VBR +

(vector No.

× 4) VCRQ (14–8)

TDEI0 0–127*2

IPRE

(11–8)

Low VCRQ (6–0)

SIO1 RERI1 0–127*215–0 (0) High VCRR (14–8)

TERI1 0–127*2VCRR (6–0)

RDFI1 0–127*2VCRS (14–8)

TDEI1 0–127*2

IPRE

(7–4)

Low VCRS (6–0)

SIO2 RERI2 0–127*215–0 (0) High VCRT (14–8)

TERI2 0–127*2VCRT (6–0)

RDFI2 0–127*2VCRU (14–8)

TDEI2 0–127*2

IPRE

(3–0)

Low VCRU (6–0)

Reserved 128–255 ————— Low

Notes: 1. An external vector number fetch can be performed without using the auto- vector