PSoC(R) 4: PSoC 4100 Family Datasheet (R) Programmable System-on-Chip (PSoC ) General Description PSoC(R) 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system controllers with an ARM(R) CortexTM-M0 CPU. It combines programmable and re-configurable analog and digital blocks with flexible automatic routing. The PSoC 4100 product family, based on this platform, is a combination of a microcontroller with digital programmable logic, high-performance analog-to-digital conversion, opamps with Comparator mode, and standard communication and timing peripherals. The PSoC 4100 products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital sub-systems allow flexibility and in-field tuning of the design. Features 32-bit MCU Sub-system Serial Communication 24 MHz ARM Cortex-M0 CPU with single-cycle multiply Up to 32 kB of flash with Read Accelerator Up to 4 kB of SRAM Two independent run-time reconfigurable Serial Communication Blocks (SCBs) with re-configurable I2C, SPI, or UART functionality Timing and Pulse-Width Modulation Programmable Analog Four 16-bit Timer/Counter Pulse-Width Modulator (TCPWM) blocks Center-aligned, Edge, and Pseudo-random modes Comparator-based triggering of Kill signals for motor drive and other high reliability digital logic applications Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator modes and ADC input buffering capability 12-bit 806 Ksps SAR ADC with differential and single-ended modes and Channel Sequencer with signal averaging Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin Up to 36 Programmable GPIO Two low-power comparators that operate in Deep Sleep 44-pin TQFP, 40-pin QFN, and 28-pin SSOP packages. Any GPIO Pin can be Capsense, LCD, Analog, or Digital Drive modes, strengths, and slew rates are programmable Low Power 1.71 to 5.5 V operation 20 nA Stop Mode with GPIO pin wakeup Hibernate and Deep Sleep modes allow wakeup-time versus power trade-offs PSoC Creator Design Environment Integrated Development Environment provides schematic design entry and build (with analog and digital automatic routing) Applications Programming Interface (API Component) for all fixed-function and programmable peripherals Capacitive Sensing Cypress Capacitive Sigma-Delta (CSD) provides best-in-class SNR (>5:1) and water tolerance Cypress supplied software component makes capacitive sensing design easy Industry Standard Tool Compatibility Automatic hardware tuning (SmartSenseTM) Segment LCD Drive LCD drive supported on all pins (common or segment) Operates in Deep Sleep mode with 4 bits per pin memory Cypress Semiconductor Corporation Document Number: 001-87220 Rev. *B * 198 Champion Court After schematic entry, development can be done with ARM-based industry-standard development tools * San Jose, CA 95134-1709 * 408-943-2600 Revised August 29, 2013 PSoC(R) 4: PSoC 4100 Family Datasheet Contents Block Diagram .................................................................. 3 Functional Definition........................................................ 4 CPU and Memory Subsystem ............................................ 4 System Resources ............................................................. 4 Analog Blocks..................................................................... 5 Fixed Function Digital ......................................................... 6 GPIO .................................................................................. 6 Special Function Peripherals.............................................. 7 Pinouts .............................................................................. 8 Power............................................................................... 11 Unregulated External Supply............................................ 11 Regulated External Supply ............................................... 11 Development Support .................................................... 12 Documentation ................................................................. 12 Online ............................................................................... 12 Tools ................................................................................ 12 Electrical Specifications ................................................ 13 Absolute Maximum Ratings.............................................. 13 Document Number: 001-87220 Rev. *B Device Level Specifications.............................................. 13 Analog Peripherals ........................................................... 17 Digital Peripherals ............................................................ 21 Memory............................................................................. 24 System Resources ........................................................... 24 Ordering Information...................................................... 27 Part Numbering Conventions ........................................... 28 Packaging........................................................................ 29 Acronyms ........................................................................ 32 Document Conventions ................................................. 34 Units of Measure .............................................................. 34 Sales, Solutions, and Legal Information ...................... 35 Worldwide Sales and Design Support .............................. 35 Products ........................................................................... 35 PSoC(R) Solutions.............................................................. 35 Cypress Developer Community........................................ 35 Technical Support............................................................. 35 Page 2 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Figure 1. Block Diagram CPU Subsystem PSoC 4100 SW D 32-bit AH B-Lite Cortex M0 24 M Hz FLASH Up to 32 kB SR AM U p to 4 kB RO M 4 kB FAST M U L N VIC , IR Q M X R ead Accelerator SR AM C ontroller R O M C ontroller System R esources x1 SM X CTBm 2x O pAm p x1 2x LP Comparator SAR ADC (12-bit) LCD Program m able Analog 2x SCB-I2C/SPI/UART Test D FT Logic D FT Analog Peripheral Interconnect (M M IO ) PC LK Capsense R eset R eset C ontrol XR ES Peripherals 4x TCPWM C lock C lock C ontrol WDT IM O ILO System Interconnect (Single Layer AHB ) IOSS GPIO (5x ports) Pow er Sleep C ontrol W IC PO R LVD R EF BO D PW R SYS N VLatches Port Interface & D igital System Interconnect (DSI) High Speed I/O M atrix Pow er M odes Active/Sleep D eep Sleep H ibernate 36x G PIO s IO Subsystem PSoC 4100 devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. security not possible with multi-chip application solutions or with microcontrollers. The ARM Serial_Wire Debug (SWD) interface supports all programming and debug features of the device. The debug circuits are enabled by default and can only be disabled in firmware. If not enabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging. Complete debug-on-chip functionality enables full device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The PSoC Creator Integrated Development Environment (IDE) provides fully integrated programming and debug support for PSoC 4100 devices. The SWD interface is fully compatible with industry standard third party tools. With the ability to disable debug features, with very robust flash protection, and by allowing customer-proprietary functionality to be implemented in on-chip programmable blocks, the PSoC 4100 family provides a level of Document Number: 001-87220 Rev. *B Additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. Because all programming, debug, and test interfaces are disabled when maximum device security is enabled, PSoC 4100 with device security enabled may not be returned for failure analysis. This is a trade-off the PSoC 4100 allows the customer to make. Page 3 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Functional Definition CPU and Memory Subsystem CPU The Cortex-M0 CPU in the PSoC 4100 is part of the 32-bit MCU subsystem, which is optimized for low power operation with extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. This enables fully compatible binary upward migration of the code to higher performance processors such as the Cortex-M3 and M4, thus enabling upward compatibility. The Cypress implementation includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt controller (NVIC) block with 32 interrupt inputs and also includes a Wakeup Interrupt Controller (WIC), which can wake the processor up from Deep Sleep mode allowing power to be switched off to the main processor when the chip is in Deep Sleep mode. The Cortex-M0 CPU provides a Non-Maskable Interrupt input (NMI), which is made available to the user when it is not in use for system functions requested by the user. The CPU also includes a debug interface, the Serial Wire Debug (SWD) interface, which is a 2-wire form of JTAG; the debug configuration used for PSoC 4100 has four break-point (address) comparators and two watchpoint (data) comparators. Clock System The PSoC 4100 clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching. In addition, the clock system ensures that no metastable conditions occur. The clock system for the PSoC 4100 consists of the IMO and the ILO internal oscillators and provision for an external clock. Figure 2. PSoC 4100 MCU Clocking Architecture IMO HFCLK EXTCLK ILO LFCLK HFCLK Prescaler SYSCLK Flash The PSoC 4100 has a flash module with a flash accelerator tightly coupled to the CPU to improve average access times from the flash block. The flash block is designed to deliver 0 wait-state (WS) access time at 24 MHz. Part of the flash module can be used to emulate EEPROM operation if required. SRAM SRAM memory is retained during Hibernate. SROM A supervisory ROM that contains boot and configuration routines is provided. System Resources Power System The power system is described in detail in the section Power on page 11. It provides assurance that voltage levels are as required for each respective mode and either delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function or generate resets (Brown-Out Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). The PSoC 4100 operates with a single external supply over the range of 1.71 to 5.5 V and has five different power modes, transitions between which are managed by the power system. The PSoC 4100 provides Sleep, Deep Sleep, Hibernate, and Stop low-power modes. UDB Dividers UDBn Analog Divider SAR clock Peripheral Dividers PERXYZ_CLK The HFCLK signal can be divided down (see PSoC 4100 MCU Clocking Architecture) to generate synchronous clocks for the analog and digital peripherals. There are a total of 12 clock dividers for the PSoC 4100, each with 16-bit divide capability. The analog clock leads the digital clocks to allow analog events to occur before digital clock-related noise is generated. The 16-bit capability allows a lot of flexibility in generating fine-grained frequency values and is fully supported in PSoC Creator. IMO Clock Source The IMO is the primary source of internal clocking in the PSoC 4100. It is trimmed during testing to achieve the specified accuracy. Trim values are stored in nonvolatile latches (NVL). Additional trim settings from flash can be used to compensate for changes. The IMO default frequency is 24 MHz and it can be adjusted between 3 to 24 MHz in steps of 1 MHz. IMO Tolerance with Cypress-provided calibration settings is 2%. ILO Clock Source The ILO is a very low power oscillator, which is primarily used to generate clocks for peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Cypress provides a software component, which does the calibration. Document Number: 001-87220 Rev. *B Page 4 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Watchdog Timer A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the timeout occurs. The watchdog reset is recorded in the Reset Cause register. Reset The PSoC 4100 can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset and allows software to determine the cause of the Reset. An XRES pin is reserved for external reset to avoid complications with configuration and multiple pin functions during power-on or reconfiguration. The XRES pin has an internal pull-up resistor that is always enabled. Voltage Reference The PSoC 4100 reference system generates all internally required references. A 1% voltage reference spec is provided for the 12-bit ADC. To allow better signal to noise ratios (SNR) and better absolute accuracy, it is possible to bypass the internal reference using a GPIO pin or to use an external reference for the SAR. Analog Blocks 12-bit SAR ADC ences: VDD, VDD/2, and VREF (nominally 1.024 V) as well as an external reference through a GPIO pin. The Sample-and-Hold (S/H) aperture is programmable allowing the gain bandwidth requirements of the amplifier driving the SAR inputs, which determine its settling time, to be relaxed if required. System performance will be 65 dB for true 12-bit precision providing appropriate references are used and system noise levels permit. To improve performance in noisy conditions, it is possible to provide an external bypass (through a fixed pin location) for the internal reference amplifier. The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through selected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, aggregate sampling bandwidth is equal to 806 Ksps whether it is for a single channel or distributed over several channels). The sequencer switching is effected through a state machine or through firmware driven switching. A feature provided by the sequencer is buffering of each channel to reduce CPU interrupt service requirements. To accommodate signals with varying source impedance and frequency, it is possible to have different sample times programmable for each channel. Also, signal range specification through a pair of range registers (low and high range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed and the CPU to read the values and check for out-of-range values in software. The SAR is able to digitize the output of the on-board temperature sensor for calibration and other temperature-dependent functions. The SAR is not available in Deep Sleep and Hibernate modes as it requires a high-speed clock (up to 18 MHz). The SAR operating range is 1.71 to 5.5 V. The 12-bit 806 KSample/second SAR ADC can operate at a maximum clock rate of 14.5 MHz and requires a minimum of 18 clocks at that frequency to do a 12-bit conversion. The block functionality is augmented for the user by adding a reference buffer to it (trimmable to 1%) and by providing the choice (for the PSoC 4100 case) of three internal voltage refer- Figure 3. SAR ADC System Diagram AHB System Bus and Programmable Logic Interconnect SAR Sequencer vminus vplus Data and Status Flags POS SARADC NEG P7 Port 2 (8 inputs) SARMUX P0 Sequencing and Control External Reference and Bypass (optional) Reference Selection VDD/2 VDDD VREF Inputs from other Ports Two Opamps (CTBm Block) Temperature Sensor The PSoC 4100 has two opamps with Comparator modes which allow most common analog functions to be performed on-chip eliminating external components; PGAs, Voltage Buffers, Filters, Trans-Impedance Amplifiers, and other functions can be realized with external passives saving power, cost, and space. The on-chip opamps are designed with enough bandwidth to drive the Sample-and-Hold circuit of the ADC without requiring external buffering. The PSoC 4100 has one on-chip temperature sensor This consists of a diode, which is biased by a current source that can be disabled to save power. The temperature sensor is connected to the ADC, which digitizes the reading and produces a temperature value using Cypress supplied software that includes calibration and linearization. Document Number: 001-87220 Rev. *B Page 5 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Low-power Comparators The PSoC 4100 has a pair of low-power comparators, which can also operate in the Deep Sleep and Hibernate modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode (Hibernate) where the system wake-up circuit is activated by a comparator switch event. Fast-mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8 mA IOL with a VOL maximum of 0.6 V. Fast-mode and Fast-mode Plus specify minimum Fall times, which are not met with the GPIO cell; Slow strong mode can help meet this spec depending on the Bus Load. Fixed Function Digital Timer/Counter/PWM Block The Timer/Counter/PWM block consists of four 16-bit counters with user-programmable period length. There is a Capture register to record the count value at the time of an event (which may be an I/O event), a period register which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals which are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow use as deadband programmable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor drive systems when an overcurrent state is indicated and the PWMs driving the FETs need to be shut off immediately with no time for software intervention. Serial Communication Blocks (SCB) The PSoC 4100 has two SCBs, which can each implement an I2C, UART, or SPI interface. I2C Mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of multimaster arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EzI2C that creates a mailbox address range in the memory of the PSoC 4100 and effectively reduces I2C communication to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the CPU not having read data on time. The FIFO mode is available in all channels and is very useful in the absence of DMA. When the SCB is an I2C Master, it interposes an IDLE state between NACK and Repeated Start; the I2C spec defines Bus free as following a Stop condition so other Active Masters do not intervene but a Master that has just become activated may start an Arbitration cycle. When the SCB is in I2C Slave mode, and Address Match on External Clock is enabled (EC_AM = 1) along with operation in the internally clocked mode (EC_OP = 0), then its I2C address must be even. UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated. SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (essentially adds a start pulse used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO and also supports an EzSPI mode in which data interchange is reduced to reading and writing an array in memory. GPIO The PSoC 4100 has 36 GPIOs. The GPIO block implements the following: Eight drive strength modes: Analog input mode (input and output buffers disabled) Input only Weak pull-up with strong pull-down Strong pull-up with weak pull-down Open drain with strong pull-down Open drain with strong pull-up Strong pull-up with strong pull-down Weak pull-up with weak pull-down Input threshold select (CMOS or LVTTL). The PSoC 4100 is not completely compliant with the I2C spec in the following respects: Individual control of input and output buffer enabling/disabling in addition to the drive strength modes. GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I2C system. Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode and Hibernate modes). Selectable slew rates for dV/dt related noise control to improve EMI. The I2C peripheral is compatible with the I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. Document Number: 001-87220 Rev. *B Page 6 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet The pins are organized in logical entities called ports, which are 8-bit in width. During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Pin locations for fixed-function peripherals are also fixed to reduce internal multiplexing complexity. Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it (5 for PSoC 4100 since it has 4.5 ports). Special Function Peripherals LCD Segment Drive The PSoC 4100 has an LCD controller which can drive up to four commons and up to 32 segments. It uses full digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods used are referred to as digital correlation and PWM. Digital correlation pertains to modulating the frequency and levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or to keep Document Number: 001-87220 Rev. *B the RMS signal zero. This method is good for STN displays but may result in reduced contrast with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but can result in better results when driving TN displays. LCD operation is supported during Deep Sleep refreshing a small display buffer (4 bits; 1 32-bit register per port). CapSense CapSense is supported on all pins in the PSoC 4100 through a CapSense Sigma-Delta (CSD) block that can be connected to any pin through an analog mux bus that any GPIO pin can be connected to via an Analog switch. CapSense function can thus be provided on any pin or group of pins in a system under software control. A component is provided for the CapSense block to make it easy for the user. Shield voltage can be driven on another Mux Bus to provide water tolerance capability. Water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. The CapSense block has two IDACs which can be used for general purposes if CapSense is not being used.(both IDACs are available in that case) or if CapSense is used without water tolerance (one IDAC is available). Page 7 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Pinouts The following is the pin-list for the PSoC 4100. Port 2 comprises of the high-speed Analog inputs for the SAR Mux. P1.7 is the optional external input and bypass for the SAR reference. Ports 3 and 4 contain the Digital Communication channels. All pins support CSD Capsense and Analog Mux Bus connections. Pins Name 44-TQFP Type Pin VSSD Power 1(DN) 40-QFN Name Pin 28-SSOP Name Pin Name Alternate Functions for Pins Analog Alt 1 Alt 2 Alt 3 Alt 4 Pin Description VSS DN - DN - - - - - - Digital Ground P2.0 GPIO 2 P2.0 1 P2.0 - - sarmux.0 - - - - Port 2 Pin 0: gpio, lcd, csd, sarmux P2.1 GPIO 3 P2.1 2 P2.1 - - sarmux.1 - - - - Port 2 Pin 1: gpio, lcd, csd, sarmux P2.2 GPIO 4 P2.2 3 P2.2 5 P2.2 sarmux.2 - - - - Port 2 Pin 2: gpio, lcd, csd, sarmux P2.3 GPIO 5 P2.3 4 P2.3 6 P2.3 sarmux.3 - - - - Port 2 Pin 3: gpio, lcd, csd, sarmux P2.4 GPIO 6 P2.4 5 P2.4 7 P2.4 sarmux.4 tcpwm0_p[1] - - - Port 2 Pin 4: gpio, lcd, csd, sarmux, pwm P2.5 GPIO 7 P2.5 6 P2.5 8 P2.5 sarmux.5 tcpwm0_n[1] - - - Port 2 Pin 5: gpio, lcd, csd, sarmux, pwm P2.6 GPIO 8 P2.6 7 P2.6 9 P2.6 sarmux.6 tcpwm1_p[1] - - - Port 2 Pin 6: gpio, lcd, csd, sarmux, pwm P2.7 GPIO 9 P2.7 8 P2.7 10 P2.7 sarmux.7 tcpwm1_n[1] - - - Port 2 Pin 7: gpio, lcd, csd, sarmux, pwm - - 10(D N) VSS 9(D N) VSS - - - - - - - Package pin to lead frame paddle downbond P3.0 GPIO 11 P3.0 10 P3.0 11 P3.0 - tcpwm0_p[0] scb1_uart_rx[ 0] scb1_i2c_scl[0] scb1_spi_mosi[0] Port 3 Pin 0: gpio, lcd, csd, pwm, scb1 P3.1 GPIO 12 P3.1 11 P3.1 12 P3.1 - tcpwm0_n[0] scb1_uart_tx[0 scb1_i2c_sda[0] ] scb1_spi_miso[0] Port 3 Pin 1: gpio, lcd, csd, pwm, scb1 P3.2 GPIO 13 P3.2 12 P3.2 13 P3.2 - tcpwm1_p[0] - swd_io P3.3 GPIO 14 P3.3 13 P3.3 14 P3.3 - tcpwm1_n[0] - swd_clk P3.4 GPIO 15 P3.4 14 P3.4 - - - tcpwm2_p[0] - - scb1_spi_ssel_1 Port 3 Pin 4: gpio, lcd, csd, pwm, scb1 P3.5 GPIO 16 P3.5 15 P3.5 - - - tcpwm2_n[0] - - scb1_spi_ssel_2 Port 3 Pin 5: gpio, lcd, csd, pwm, scb1 P3.6 GPIO 17 P3.6 16 P3.6 - - - tcpwm3_p[0] - scb1_spi_ssel_3 Port 3 Pin 6: gpio, lcd, csd, pwm, scb1 P3.7 GPIO 18 P3.7 17 P3.7 - - - tcpwm3_n[0] - - Port 3 Pin 7: gpio, lcd, csd, pwm VDDD Power 19 VDD D - - - - - - - - - Digital Supply, 1.8 - 5.5 V scb1_spi_clk[0] Port 3 Pin 2: gpio, lcd, csd, pwm, scb1, swd scb1_spi_ssel_0[0 Port 3 Pin 3: gpio, lcd, ] csd, pwm, scb1, swd P4.0 GPIO 20 P4.0 18 P4.0 15 P4.0 - - scb0_uart_rx scb0_i2c_scl scb0_spi_mosi Port 4 Pin 0: gpio, lcd, csd, scb0 P4.1 GPIO 21 P4.1 19 P4.1 16 P4.1 - - scb0_uart_tx scb0_i2c_sda scb0_spi_miso Port 4 Pin 1: gpio, lcd, csd, scb0 P4.2 GPIO 22 P4.2 20 P4.2 17 P4.2 csd_c_mo d - - - scb0_spi_clk Port 4 Pin 2: gpio, lcd, csd, scb0 P4.3 GPIO 23 P4.3 21 P4.3 18 P4.3 csd_c_sh_ tank - - - scb0_spi_ssel_0 Port 4 Pin 3: gpio, lcd, csd, scb0 P0.0 GPIO 24 P0.0 22 P0.0 19 P0.0 comp1_inp - - - scb0_spi_ssel_1 Port 0 Pin 0: gpio, lcd, csd, scb0, comp P0.1 GPIO 25 P0.1 23 P0.1 20 P0.1 comp1_inn - - - scb0_spi_ssel_2 Port 0 Pin 1: gpio, lcd, csd, scb0, comp P0.2 GPIO 26 P0.2 24 P0.2 21 P0.2 comp2_inp - - - scb0_spi_ssel_3 Port 0 Pin 2: gpio, lcd, csd, scb0, comp P0.3 GPIO 27 P0.3 25 P0.3 22 P0.3 comp2_inn - - - - Port 0 Pin 3: gpio, lcd, csd, comp P0.4 GPIO 28 P0.4 26 P0.4 - - - - scb1_uart_rx[ 1] scb1_i2c_scl[1] scb1_spi_mosi[1] Port 0 Pin 4: gpio, lcd, csd, scb1 P0.5 GPIO 29 P0.5 27 P0.5 - - - - scb1_uart_tx[1 scb1_i2c_sda[1] ] scb1_spi_miso[1] Port 0 Pin 5: gpio, lcd, csd, scb1 P0.6 GPIO 30 P0.6 28 P0.6 23 P0.6 - ext_clk - - P0.7 GPIO 31 P0.7 29 P0.7 24 P0.7 - - - wakeup Document Number: 001-87220 Rev. *B scb1_spi_clk[1] Port 0 Pin 6: gpio, lcd, csd, scb1, ext_clk scb1_spi_ssel_0[1 Port 0 Pin 7: gpio, lcd, ] csd, scb1, wakeup Page 8 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Pins Name Type 44-TQFP 40-QFN Pin Name Pin Name 28-SSOP Pin Name Alternate Functions for Pins Analog Alt 1 Alt 2 Alt 3 Alt 4 Pin Description XRES XRES 32 XRES 30 XRES 25 XRES - - - - - Chip reset, active low VCCD Power 33 VCC D 31 VCCD 26 VCCD - - - - - Regulated supply, connect to 1 F cap or 1.8 V VDDD Power 34 VDD D 32 VDDD 27 VDD - - - - - Digital Supply, 1.8 - 5.5 V VDDA Power 35 VDD A 33 VDDA 27 VDD - - - - - Analog Supply, 1.8 - 5.5 V, equal to VDDD VSSA Power 36 VSSA 34 VSSA 28(D N) VSS - - - - - Analog Ground P1.0 GPIO 37 P1.0 35 P1.0 1 P1.0 ctb.oa0.inp tcpwm2_p[1] - - - Port 1 Pin 0: gpio, lcd, csd, ctb, pwm P1.1 GPIO 38 P1.1 36 P1.1 2 P1.1 ctb.oa0.in m tcpwm2_n[1] - - - Port 1 Pin 1: gpio, lcd, csd, ctb, pwm P1.2 GPIO 39 P1.2 37 P1.2 3 P1.2 ctb.oa0.out tcpwm3_p[1] - - - Port 1 Pin 2: gpio, lcd, csd, ctb, pwm P1.3 GPIO 40 P1.3 38 P1.3 - - ctb.oa1.out tcpwm3_n[1] - - - Port 1 Pin 3: gpio, lcd, csd, ctb, pwm P1.4 GPIO 41 P1.4 39 P1.4 - - ctb.oa1.in m - - - - Port 1 Pin 4: gpio, lcd, csd, ctb P1.5 GPIO 42 P1.5 - - - - ctb.oa1.inp - - - - Port 1 Pin 5: gpio, lcd, csd, ctb P1.6 GPIO 43 P1.6 - - - - ctb.oa0.inp _alt - - - - Port 1 Pin 6: gpio, lcd, csd P1.7 GPIO 44 P1.7 40 P1.7 4 P1.7 ctb.oa1.inp _alt ext_vref - - - - Port 1 Pin 7: gpio, lcd, csd, ext_ref Descriptions of the Pin functions are as follows: VDDD: Power supply for both analog and digital sections (where there is no VDDA pin). VDDA: Analog VDD pin where package pins allow; shorted to VDDD otherwise. VSSA: Analog ground pin where package pins allow; shorted to VSS otherwise VSS: Ground pin. VCCD: Regulated Digital supply (1.8 V 5%). Port Pins can all be used as LCD Commons, LCD Segment drivers, or CSD sense and shield pins can be connected to AMUXBUS A or B or can all be used as GPIO pins that can be driven by firmware or DSI signals. The following packages are supported: 44-pin TQFP, 40-pin QFN, and 28-pin SSOP. Document Number: 001-87220 Rev. *B Page 9 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet 36 VSSA 35 VD DA 34 VD DD ( GPIO)P1[3] ( GPIO)P1[2] ( GPIO)P1[1] ( GPIO)P1[0] 40 39 38 37 (GPIO)P1[7] 44 1 2 3 4 5 6 33 32 31 30 29 TQFP 28 27 26 25 24 23 VCCD XRES (GPIO) P0[7] (GPIO) (GPIO) (GPIO) (GPIO) (GPIO) (GPIO) (GPIO) (GPIO) P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] P4[3] (GPIO) P4[0] (GPIO) P4[1] (GPIO) P4[2] (GPIO) P3[6] (GPIO) P3[7] VDD D (GPIO) P3[5] (GPIO) P3[2] (GPIO) P3[3] (GPIO) P3[4] (GPIO) P3[1] 16 17 18 19 20 21 22 (Top View) 7 8 9 10 11 12 13 14 15 VSS ( GPIO) P2[ 0] ) ( GPIO P2[1] (GPIO) P2[2] (GPIO) P2[3] (GPIO) P2[4] (GPIO) P2[5] (GPIO) P2[6] (GPIO) P2[7] VSS ( GPIO) P3[0] 43 ( GPIO)P1[6] 42 ( GPIO)P1[5] 41 ( GPIO)P1[4] Figure 4. 44-pin TQFP Part Pinout ( GPIO) P2[0] (GPIO) P2[1] (GPIO) P2[2] (GPIO) P2[3] (GPIO) P2[4] (GPIO) P2[5] 1 2 3 4 5 6 (GPIO) P2[6] (GPIO) P2[7] Vss (GPIO) P3[0] 7 8 9 VDDD VCCD 33 32 31 (GPIO)P1[0] VSSA VDDA (GPIO)P1[3] (GPIO)P1[2] (GPIO)P1[1] (GPIO)P1[4] 39 38 37 36 35 34 (GPIO)P1[7] 40 Figure 5. 40-Pin QFN Pinout 30 29 28 27 QFN 26 25 24 23 22 21 (Top View) 15 16 17 18 19 20 (GPIO) P3[5] (GPIO) P3[6] (GPIO) P3[7] (GPIO) P4[0] (GPIO) P4[1] (GPIO) P4[2] (GPIO) P3[4] 12 13 14 (GPIO) P3[2] (GPIO) P3[3] 11 (GPIO) P3[1] 10 XRES (GPIO) P0[7] (GPIO) P0[6] (GPIO) P0[5] (GPIO) P0[4] (GPIO) (GPIO) (GPIO) ( GPIO) P0[3] P0[2] P0[1] P0[0] ( GPIO) P4[3] Figure 6. 28-Pin SSOP Pinout ( GPIO) P1[0] ( GPIO) P1[1] ( GPIO) P1[2] (GPIO) P1[7] (GPIO) P2[2] (GPIO) P2[3] (GPIO) P2[4] (GPIO) P2[5] (GPIO) P2[6] ( GPIO) P2[7 ] (GPIO) P3[0] ( GPIO) P3[1] ( GPIO) P3[2] ( GPIO) P3[3] Document Number: 001-87220 Rev. *B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP (Top View) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS VDDD VCCD XRES ( GPIO) P0[7] (GPIO) P0[6] (GPIO) P0[3] (GPIO) P0[2] (GPIO) P0[1] ( GPIO) P0[0] ( GPIO) P4[3] (GPIO) P4[2] (GPIO) P4[1] (GPIO) P4[0] Page 10 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Power VDDA-VSSA VCCD-VSS VREF-VSSA (optional) Figure 8. 40-pin QFN Example 0.1 F C4 VSS (GPIO)P1[3] (GPIO)P1[2] (GPIO)P1[1] (GPIO)P1[0] (GPIO)P1[4] VSSA VDDA VDDD VCCD QFN VSS 0.1 F C4 C3 1F (GPIO)P1[7] (GPIO)P1[6] (GPIO)P1[5] (GPIO)P1[4] (GPIO)P1[3] (GPIO)P1[2] (GPIO)P1[1] (GPIO)P1[0] VSS 44 43 42 41 40 39 38 37 VSSA 36 VDDA 35 VDDD 34 12 13 14 15 16 17 18 19 VDDD 20 21 22 ( Top View) C2 0.1 F 19 20 VSS (GPIO) P4[1] (GPIO) P4[2] 16 17 18 XRES (GPIO) P0[7] (GPIO) P0[6] (GPIO) P0[5] (GPIO) P0[4] (GPIO) P0[3] (GPIO) P0[2] (GPIO) P0[1] (GPIO) P0[0] (GPIO) P4[3] VSS 0.1 F C2 C1 1F VSS (GPIO )P1[0] (GPIO)P1[1] (GPIO )P1[2] ( GPIO) P1[7] ( GPIO) P2[2] (GPIO ) P2[3] (GPIO ) P2[4] (GPIO ) P2[5] (GPIO) P2[6] (GPIO) P2[7] ( GPIO) P3[0] (GPIO )P3[1] (GPIO )P3[2] (GPIO )P3[3] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP ( Top View) VSS 28 VDDD27 VCCD26 25 24 23 22 21 20 19 18 17 16 15 XRES ( GPIO) P0[7] ( GPIO) P0[6] ( GPIO) P0[3] ( GPIO) P0[2] ( GPIO) P0[1] ( GPIO) P0[0] ( GPIO) P4[3] ( GPIO)P4[2] ( GPIO)P4[1] ( GPIO)P4[0] C3 1F VSS VSS 33 32 31 30 29 28 27 26 25 24 23 VCCD XRES ( GPIO) P0[7] ( GPIO) P0[6] ( GPIO) P0[5] ( GPIO) P0[4] ( GPIO) P0[3] ( GPIO) P0[2] ( GPIO) P0[1] ( GPIO) P0[0] ( GPIO) P4[3] (GPIO) P4[0] (GPIO) P4[1] (GPIO) P4[2] VSS TQFP (GPIO) P3[2] (GPIO) P3[3] (GPIO) P3[4] (GPIO) P3[5] (GPIO) P3[6] (GPIO) P3[7] ( GPIO) P3[0] 1 VSS 2 3 4 5 6 7 8 9 10 VSS 11 (GPIO) P3[1] ( GPIO)P2[0] ( GPIO)P2[1] ( GPIO) P2[2] ( GPIO) P2[3] ( GPIO) P2[4] ( GPIO) P2[5] ( GPIO) P2[6] ( GPIO) P2[7] 1 F C 1 C5 1 F 30 29 28 27 26 25 24 23 22 21 Figure 9. 28-SSOP Example An example of a bypass scheme for the 44-TQFP package follows. Figure 7. 44-TQFP Package Example (GPIO) P4[0] (GPIO) P3[3] (GPIO) P3[4] VSS 15 (Top View) 11 12 13 14 (GPIO) P3[0] 1 2 3 4 5 6 7 8 9 VSS 10 (GPIO) P3[5] (GPIO) P3[6] (GPIO) P3[7] (GPIO) P2[0] (GPIO) P2[1] (GPIO) P2[2] (GPIO) P2[3] (GPIO) P2[4] (GPIO) P2[5] (GPIO) P2[6] (GPIO) P2[7] (GPIO)P1[7] VSS 39 38 37 36 35 34 33 32 31 In this mode, the PSoC 4100 is powered by an External Power Supply that can be anywhere in the range of 1.8 to 5.5 V. This range is also designed for battery-powered operation, for instance, the chip can be powered from a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the PSoC 4100 supplies the internal logic and the VCCD output of the PSoC 4100 must be bypassed to ground via an external Capacitor (in the range of 1 to 1.6 F; X5R ceramic or better). C2 0.1 F 1F C1 C3 1F VSS 40 Unregulated External Supply VDDA and VDDD must be shorted together; the grounds, VSSA and VSS must also be shorted together. Bypass capacitors must be used from VDDD to ground, typical practice for systems in this frequency range is to use a capacitor in the 1 F range in parallel with a smaller capacitor (0.1 F for example). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the Bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. Bypass Capacitors 0.1 F ceramic at each pin (C2, C6) plus bulk capacitor 1 to 10 F (C1). 0.1 F ceramic at pin (C4). Additional 1 F to 10 F (C3) bulk capacitor 1 F ceramic capacitor at the VCCD pin (C5) The internal bandgap may be bypassed with a 1 F to 10 F capacitor. (GPIO) P3[2] The PSoC 4100 family allows two distinct modes of power supply operation: Unregulated External Supply, and Regulated External Supply modes. Power Supply VDDD-VSS (GPIO) P3[1] The following power system diagram shows the minimum set of power supply pins as implemented for the PSoC 4100. The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog circuits run directly from the VDDA input. There are separate regulators for the Deep Sleep and Hibernate (lowered power supply and retention) modes. There is a separate low-noise regulator for the bandgap. The supply voltage range is 1.71 to 5.5 V with all functions and circuits operating over that range. C5 1 F VSS Regulated External Supply In this mode, the PSoC 4100 is powered by an external power supply that must be within the range of 1.71 to 1.89 V (1.8 5%); note that this range needs to include power supply ripple too. In this mode, VCCD, VDDA, and VDDD pins are all shorted together and bypassed. The internal regulator is disabled in firmware. C6 0.1F VSS Document Number: 001-87220 Rev. *B Page 11 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Development Support The PSoC 4100 family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit www.cypress.com/go/psoc4 to find out more. Documentation A suite of documentation supports the PSoC 4100 family to ensure that you can find answers to your questions quickly. This section contains a list of some of the key documents. Software User Guide: A step-by-step guide for using PSoC Creator. The software user guide shows you how the PSoC Creator build process works in detail, how to use source control with PSoC Creator, and much more. Component Datasheets: The flexibility of PSoC allows the creation of new peripherals (components) long after the device has gone into production. Component data sheets provide all of the information needed to select and use a particular component, including a functional description, API documentation, example code, and AC/DC specifications. Technical Reference Manual: The Technical Reference Manual (TRM) contains all the technical detail you need to use a PSoC device, including a complete description of all PSoC registers. The TRM is available in the Documentation section at www.cypress.com/psoc4. Online In addition to print documentation, the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world, 24 hours a day, 7 days a week. Tools With industry standard cores, programming, and debugging interfaces, the PSoC 4100 family is part of a development tool ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use PSoC Creator IDE, supported third party compilers, programmers, debuggers, and development kits. Application Notes: PSoC application notes discuss a particular application of PSoC in depth; examples include brushless DC motor control and on-chip filtering. Application notes often include example projects in addition to the application note document. Document Number: 001-87220 Rev. *B Page 12 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Electrical Specifications Absolute Maximum Ratings Table 1. Absolute Maximum Ratings[1] Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID1 VDDD_ABS Digital supply relative to Vssd -0.5 - 6 V Absolute max SID2 VCCD_ABS Direct digital core voltage input relative to Vssd -0.5 - 1.95 V Absolute max SID3 VGPIO_ABS GPIO voltage -0.5 - VDD+0.5 V Absolute max SID4 IGPIO_ABS Maximum current per GPIO -25 - 25 mA Absolute max SID5 IGPIO_injection GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS -0.5 - 0.5 mA Absolute max, current injected per pin BID44 ESD_HBM Electrostatic discharge human body model 2200 - - V BID45 ESD_CDM Electrostatic discharge charged device model 500 - - V BID46 LU Pin current for Latch-up -200 - 200 mA Device-Level Specifications All specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Table 2. DC Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID53 VDDD Power supply input voltage 1.8 - 5.5 V With regulator enabled SID255 VDDD Power supply input voltage unregulated 1.71 1.8 1.89 V Internally unregulated supply SID54 VCCD Output voltage (for core logic) - 1.8 - V SID55 CEFC External regulator voltage bypass 1 1.3 1.6 F X5R ceramic or better SID56 CEXC Power supply decoupling capacitor - 1 - F X5R ceramic or better - - 2.8 mA Active Mode, VDDD = 1.71 to 5.5 V. Typical values measured at VDD = 3.3 V. SID9 IDD5 Execute from Flash; CPU at 6 MHz SID10 IDD6 Execute from Flash; CPU at 6 MHz - 2.2 - mA SID12 IDD8 Execute from Flash; CPU at 12 MHz - - 4.2 mA SID13 IDD9 Execute from Flash; CPU at 12 MHz - 3.7 - mA T = 25 C SID16 IDD11 Execute from Flash; CPU at 24 MHz - 6.7 - mA T = 25 C SID17 IDD12 Execute from Flash; CPU at 24 MHz - - 7.2 mA - 1.3 1.8 mA T = 25 C Sleep Mode, VDDD = 1.7 to 5.5 V SID25 IDD20 I2C wakeup, WDT, and comparators on. 6 MHz Note 1. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150 C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Document Number: 001-87220 Rev. *B Page 13 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Table 2. DC Specifications (continued) Spec ID# Parameter SID25A IDD20A Description Min Typ Max Units I2C wakeup, WDT, and comparators on. 12 MHz - 1.7 2.2 mA Details/ Conditions Deep Sleep Mode, VDDD = 1.8 to 3.6 V (Regulator on) SID31 IDD26 I2C wakeup and WDT on - 1.3 - A T = 25 C, 3.6 V SID32 IDD27 I2C wakeup and WDT on - - 50 A T = 85 C - 15 - A T = 25 C, 5.5 V Deep Sleep Mode, VDDD = 3.6 to 5.5 V SID34 IDD29 I2C wakeup and WDT on Deep Sleep Mode, VDDD = 1.71 to 1.89 V (Regulator bypassed) SID37 SID38 IDD32 I2C wakeup and WDT on - 1.7 - A T = 25 C IDD33 I2C - - 440 A T = 85 C wakeup and WDT on Hibernate Mode, VDDD = 1.8 to 3.6 V (Regulator on; Guaranteed by Characterization) SID40 IDD35 GPIO and reset active - 150 - nA T = 25 C, 3.6 V SID41 IDD36 GPIO and reset active - - 1 A T = 85 C - 150 - nA T = 25 C, 5.5 V Hibernate Mode, VDDD = 3.6 to 5.5 V (Guaranteed by Characterization) SID43 IDD38 GPIO and reset active Hibernate Mode, VDDD = 1.71 to 1.89 V (Regulator bypassed; Guaranteed by Characterization) SID46 IDD41 GPIO and reset active - 150 - nA T = 25 C SID47 IDD42 GPIO and reset active - - 1 A T = 85 C Stop Mode (Guaranteed by Characterization) SID304 IDD43A Stop Mode current; VDD = 3.6 V - 20 80 nA IDD_XR Supply current while XRES asserted - 2 5 mA XRES Current SID307 Table 3. AC Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions DC - 24 MHz 1.71 VDD 5.5 SID48 FCPU CPU frequency SID49 TSLEEP Wakeup from sleep mode - 0 - s Guaranteed by characterization SID50 TDEEPSLEEP Wakeup from Deep Sleep mode - - 25 s 24 MHz IMO. Guaranteed by characterization SID51 THIBERNATE Wakeup from Hibernate and Stop modes - - 2 ms Guaranteed by characterization SID52 TRESETWIDTH External reset pulse width 1 - - s Guaranteed by characterization Document Number: 001-87220 Rev. *B Page 14 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet GPIO Table 4. GPIO DC Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID57 VIH[2] Input voltage high threshold 0.7 x VDDD - - V CMOS Input SID58 VIL Input voltage low threshold - - 0.3 x VDDD V CMOS Input SID241 VIH[2] LVTTL input, VDDD < 2.7 V 0.7x VDDD - - V SID242 VIL LVTTL input, VDDD < 2.7 V - - 0.3 x VDDD V SID243 VIH[2] LVTTL input, VDDD 2.7 V 2.0 - - V SID244 VIL LVTTL input, VDDD 2.7 V - - 0.8 V SID59 VOH Output voltage high level VDDD -0.6 - - V IOH = 4 mA at 3 V VDDD SID60 VOH Output voltage high level VDDD -0.5 - - V IOH = 1 mA at 1.8 V VDDD SID61 VOL Output voltage low level - - 0.6 V IOL = 4 mA at 1.8 V VDDD SID62 VOL Output voltage low level - - 0.6 V IOL = 8 mA at 3 V VDDD SID62A VOL Output voltage low level - - 0.4 V IOL = 3 mA at 3 V VDDD SID63 RPULLUP Pull-up resistor 3.5 5.6 8.5 k SID64 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 k SID65 IIL Input leakage current (absolute value) - - 2 nA SID65A IIL_CTBM Input leakage current (absolute value) for CTBM pins - - 4 nA 25 C, VDDD = 3.0 V SID66 CIN Input capacitance - - 7 pF SID67 VHYSTTL Input hysteresis LVTTL 25 40 - mV VDDD 2.7 V. Guaranteed by characterization SID68 VHYSCMOS Input hysteresis CMOS 0.05 x VDDD - - mV Guaranteed by characterization SID69 IDIODE Current through protection diode to VDD/Vss - - 100 A Guaranteed by characterization SID69A ITOT_GPIO Maximum Total Source or Sink Chip Current - - 200 mA Guaranteed by characterization Note 2. VIH must not exceed VDDD + 0.2 V. Document Number: 001-87220 Rev. *B Page 15 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Table 5. GPIO AC Specifications (Guaranteed by Characterization) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID70 TRISEF Rise time in fast strong mode 2 - 12 ns 3.3 V VDDD, Cload = 25 pF SID71 TFALLF Fall time in fast strong mode 2 - 12 ns 3.3 V VDDD, Cload = 25 pF SID72 TRISES Rise time in slow strong mode 10 - 60 3.3 V VDDD, Cload = 25 pF SID73 TFALLS Fall time in slow strong mode 10 - 60 3.3 V VDDD, Cload = 25 pF SID74 FGPIOUT1 GPIO Fout;3.3 V VDDD 5.5 V. Fast strong mode. - - 24 MHz 90/10%, 25 pF load, 60/40 duty cycle SID75 FGPIOUT2 GPIO Fout;1.7 V VDDD 3.3 V. Fast strong mode. - - 16.7 MHz 90/10%, 25 pF load, 60/40 duty cycle SID76 FGPIOUT3 GPIO Fout;3.3 V VDDD 5.5 V. Slow strong mode. - - 7 MHz 90/10%, 25 pF load, 60/40 duty cycle SID245 FGPIOUT4 GPIO Fout;1.7 V VDDD 3.3 V. Slow strong mode. - - 3.5 MHz 90/10%, 25 pF load, 60/40 duty cycle SID246 FGPIOIN GPIO input operating frequency; 1.71 V VDDD 5.5 V - - 24 MHz 90/10% VIO Min Typ Max Units XRES Table 6. XRES DC Specifications Spec ID# Parameter Description Details/ Conditions SID77 VIH Input voltage high threshold 0.7 x VDDD - - V CMOS Input SID78 VIL Input voltage low threshold - - 0.3 x VDDD V CMOS Input SID79 RPULLUP Pull-up resistor 3.5 5.6 8.5 k SID80 CIN Input capacitance - 3 - pF SID81 VHYSXRES Input voltage hysteresis - 100 - mV Guaranteed by characterization SID82 IDIODE Current through protection diode to VDDD/VSS - - 100 A Guaranteed by characterization Min 1 Typ - Max - Units s Table 7. XRES AC Specifications Spec ID# SID83 Parameter TRESETWIDTH Description Reset pulse width Document Number: 001-87220 Rev. *B Details/ Conditions Guaranteed by characterization Page 16 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Analog Peripherals Opamp Table 8. Opamp Specifications (Guaranteed by Characterization) Spec ID# Parameter Description Min Typ Max Units IDD Opamp block current. No load. - - - - SID269 IDD_HI Power = high - 1000 1300 A SID270 IDD_MED Power = medium - 320 500 A SID271 IDD_LOW Power = low - 250 350 A GBW Load = 20 pF, 0.1 mA. VDDA = 2.7 V - - - - SID272 GBW_HI Power = high 6 - - MHz SID273 GBW_MED Power = medium 4 - - MHz SID274 GBW_LO Power = low - 1 - MHz IOUT_MAX VDDA 2.7 V, 500 mV from rail - - - - SID275 IOUT_MAX_HI Power = high 10 - - mA SID276 IOUT_MAX_MID Power = medium 10 - - mA SID277 IOUT_MAX_LO Power = low - 5 - mA IOUT VDDA = 1.71 V, 500 mV from rail - - - - SID278 IOUT_MAX_HI Power = high 4 - - mA SID279 IOUT_MAX_MID Power = medium 4 - - mA SID280 IOUT_MAX_LO Power = low - 2 - mA Details/ Conditions SID281 VIN Charge pump on, VDDA 2.7 V -0.05 - VDDA - 0.2 V SID282 VCM Charge pump on, VDDA 2.7 V -0.05 - VDDA - 0.2 V VOUT VDDA 2.7 V - - - SID283 VOUT_1 Power = high, Iload=10 mA 0.5 - VDDA - 0.5 V SID284 VOUT_2 Power = high, Iload=1 mA 0.2 - VDDA - 0.2 V SID285 VOUT_3 Power = medium, Iload=1 mA 0.2 - VDDA - 0.2 V SID286 VOUT_4 Power = low, Iload=0.1mA 0.2 - VDDA - 0.2 V SID288 VOS_TR Offset voltage, trimmed 1 0.5 1 mV High mode SID288A VOS_TR Offset voltage, trimmed - 1 - mV Medium mode SID288B VOS_TR Offset voltage, trimmed - 2 - mV Low mode SID290 VOS_DR_TR Offset voltage drift, trimmed -10 3 10 V/C High mode SID290A VOS_DR_TR Offset voltage drift, trimmed - 10 - V/C Medium mode SID290B VOS_DR_TR Offset voltage drift, trimmed - 10 - V/C Low mode SID291 CMRR DC 70 80 - dB VDDD = 3.6 V PSRR At 1 kHz, 100 mV ripple 70 85 - dB VDDD = 3.6 V - - - - - 94 - Vrms SID292 Noise SID293 VN1 Input referred, 1 Hz - 1GHz, power = high SID294 VN2 Input referred, 1 kHz, power = high - 72 - nV/rtHz SID295 VN3 Input referred, 10kHz, power = high - 28 - nV/rtHz SID296 VN4 Input referred, 100kHz, power = high - 15 - nV/rtHz SID297 Cload Stable up to maximum load. Performance specs at 50 pF. - - 125 pF Document Number: 001-87220 Rev. *B Page 17 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Table 8. Opamp Specifications (Guaranteed by Characterization) (continued) Spec ID# Parameter Description Min Typ Max Units SID298 Slew_rate Cload = 50 pF, Power = High, VDDA 2.7 V 6 - - V/sec SID299 T_op_wake From disable to enable, no external RC dominating - 300 - sec Comp_mode Comparator mode; 50 mV drive, Trise = Tfall (approx.) - - - SID300 TPD1 Response time; power = high - 150 - nsec SID301 TPD2 Response time; power = medium - 400 - nsec SID302 TPD3 Response time; power = low - 2000 - nsec SID303 Vhyst_op Hysteresis - 10 - mV Min Typ Max Units Details/ Conditions Comparator Table 9. Comparator DC Specifications Spec ID# Parameter Description Details/ Conditions SID85 VOFFSET2 Input offset voltage - - 4 mV SID85A VOFFSET3 Input offset voltage. Ultra low-power mode. - 12 - mV SID86 VHYST Hysteresis when enabled - 10 35 mV Guaranteed by characterization SID87 VICM1 Input common mode voltage in normal mode 0 - VDDD - 0.1 V Modes 1 and 2. Guaranteed by characterization SID247 VICM2 Input common mode voltage in low power mode 0 - VDDD V Guaranteed by characterization SID247A VICM2 Input common mode voltage in ultra low power mode 0 - VDDD - 1.15 V Guaranteed by characterization SID88 CMRR Common mode rejection ratio 50 - - dB VDDD 2.7 V. Guaranteed by characterization SID88A CMRR Common mode rejection ratio 42 - - dB VDDD < 2.7 V. Guaranteed by characterization SID89 ICMP1 Block current, normal mode - - 280 A Guaranteed by characterization SID248 ICMP2 Block current, low power mode - - 50 A Guaranteed by characterization SID259 ICMP3 Block current, ultra low power mode - - 6 A Guaranteed by characterization SID90 ZCMP DC input impedance of comparator 35 - - M Guaranteed by characterization Typ Max Table 10. Comparator AC Specifications (Guaranteed by Characterization) Spec ID# Parameter Description Min Units Details/Conditions SID91 TRESP1 Response time, normal mode - - 38 ns 50 mV overdrive SID258 TRESP2 Response time, low power mode - - 70 ns 50 mV overdrive Document Number: 001-87220 Rev. *B Page 18 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Table 10. Comparator AC Specifications (Guaranteed by Characterization) (continued) SID92 TRESP3 Response time, ultra low power mode Document Number: 001-87220 Rev. *B - - 2.3 s 200 mV overdrive Page 19 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Temperature Sensor Table 11. Temperature Sensor Specifications Spec ID# SID93 Parameter TSENSACC Description Temperature sensor accuracy Min Typ Max Units Details/Conditions -5 1 +5 C -40 to +85 C Min Typ Max Units - - 12 bits SAR ADC Table 12. SAR ADC DC Specifications Spec ID# Parameter Description Resolution Details/Conditions SID94 A_RES SID95 A_CHNIS_S Number of channels - single ended - - 8 8 full speed SID96 A-CHNKS_D Number of channels - differential - - 4 Diff inputs use neighboring I/O SID97 A-MONO Monotonicity - - - Yes. Based on characterization SID98 A_GAINERR Gain error - - 0.1 % SID99 A_OFFSET Input offset voltage - - 2 mV SID100 A_ISAR Current consumption - - 1 mA SID101 A_VINS Input voltage range - single ended VSS - VDDA V Based on device characterization SID102 A_VIND Input voltage range - differential VSS - VDDA V Based on device characterization SID103 A_INRES Input resistance - - 2.2 K Based on device characterization SID104 A_INCAP Input capacitance - - 10 pF Based on device characterization With external reference. Guaranteed by characterization Measured with 1-V VREF. Guaranteed by characterization Table 13. SAR ADC AC Specifications (Guaranteed by Characterization) Spec ID# SID106 Parameter A_PSRR Description Power supply rejection ratio Min 70 Typ - Max - Units dB SID107 A_CMRR Common mode rejection ratio 66 - - dB SID108 A_SAMP_1 - - 1 Msps SID108A A_SAMP_2 - - 500 Ksps SID108B A_SAMP_3 - - 100 Ksps SID109 A_SNDR 65 - - dB SID111 A_INL Sample rate with external reference bypass cap Sample rate with no bypass cap. Reference = VDD Sample rate with no bypass cap. Internal reference Signal-to-noise and distortion ratio (SINAD) Integral non linearity -1.7 - +2 LSB Document Number: 001-87220 Rev. *B Details/Conditions Measured at 1 V FIN = 10 kHz VDD = 1.71 to 5.5, 806 Ksps, Vref = 1 to 5.5. Page 20 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Table 13. SAR ADC AC Specifications (Guaranteed by Characterization) (continued) Spec ID# SID111A Parameter A_INL Description Integral non linearity Min -1.5 Typ - Max +1.7 Units LSB SID111B A_INL Integral non linearity -1.5 - +1.7 LSB SID112 A_DNL Differential non linearity -1 - +2.2 LSB SID112A A_DNL Differential non linearity -1 - +2 LSB SID112B A_DNL Differential non linearity -1 - +2.2 LSB SID113 A_THD Total harmonic distortion - - -65 dB Typ Max Units Details/Conditions VDDD = 1.71 to 3.6, 806 Ksps, Vref = 1.71 to VDDD. VDDD = 1.71 to 5.5, 500 Ksps, Vref = 1 to 5.5. VDDD = 1.71 to 5.5, 806 Ksps, Vref = 1 to 5.5. VDDD = 1.71 to 3.6, 806 Ksps, Vref = 1.71 to VDDD. VDDD = 1.71 to 5.5, 500 Ksps, Vref = 1 to 5.5. FIN = 10 kHz. CSD Table 14. CSD Block Specification Spec ID# Parameter Description Min Details/ Conditions CSD Specification SID308 VCSD Voltage range of operation 1.71 - 5.5 V SID309 IDAC1 DNL for 8-bit resolution -1 - 1 LSB SID310 IDAC1 INL for 8-bit resolution -3 - 3 LSB SID311 IDAC2 DNL for 7-bit resolution -1 - 1 LSB SID312 IDAC2 INL for 7-bit resolution -3 - 3 LSB SID313 SNR Ratio of counts of finger to noise. Guaranteed by characterization 5 - - Ratio SID314 IDAC1_CRT1 Output current of Idac1 (8-bits) in High range - 612 - A SID314A IDAC1_CRT2 Output current of Idac1(8-bits) in Low range - 306 - A SID315 IDAC2_CRT1 Output current of Idac2 (7-bits) in High range - 304.8 - A SID315A IDAC2_CRT2 Output current of Idac2 (7-bits) in Low range - 152.4 - A Document Number: 001-87220 Rev. *B Capacitance range of 9 to 35 pF, 0.1 pF sensitivity Page 21 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Digital Peripherals The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timer Table 15. Timer DC Specifications (Guaranteed by Characterization) Spec ID SID115 Parameter ITIM1 Description Block current consumption at 3 MHz Min - Typ - Max 19 Units Details/Conditions A 16-bit timer SID116 ITIM2 Block current consumption at 12 MHz - - 66 A Min - Typ - Max 24 Units MHz 16-bit timer Table 16. Timer AC Specifications (Guaranteed by Characterization) Spec ID SID118 Parameter TTIMFREQ Description Operating frequency SID119 TCAPWINT Capture pulse width (internal) 42 - - ns SID120 TCAPWEXT Capture pulse width (external) 42 - - ns SID121 TTIMRES Timer resolution 21 - - ns SID122 TTENWIDINT Enable pulse width (internal) 42 - - ns SID123 TTENWIDEXT Enable pulse width (external) 42 - - ns SID124 TTIMRESWINT Reset pulse width (internal) 42 - - ns SID125 TTIMRESEXT Reset pulse width (external) 42 - - ns Details/Conditions Counter Table 17. Counter DC Specifications (Guaranteed by Characterization) Spec ID SID126 Parameter ICTR1 Description Block current consumption at 3 MHz Min - Typ - Max 19 Units Details/Conditions A 16-bit Counter SID127 ICTR2 Block current consumption at 12 MHz - - 66 A Typ - Max 24 Units MHz 16-bit Counter Table 18. Counter AC Specifications (Guaranteed by Characterization) Spec ID SID129 Parameter TCTRFREQ Description Operating frequency Min - SID130 TCTRPWINT Capture pulse width (internal) 42 - - ns SID131 TCTRPWEXT Capture pulse width (external) 42 - - ns SID132 TCTRES Counter Resolution 21 - - ns SID133 TCENWIDINT Enable pulse width (internal) 42 - - ns SID134 TCENWIDEXT Enable pulse width (external) 42 - - ns SID135 TCTRRESWINT Reset pulse width (internal) 42 - - ns SID136 TCTRRESWEXT Reset pulse width (external) 42 - - ns Details/Conditions Pulse Width Modulation (PWM) Table 19. PWM DC Specifications (Guaranteed by Characterization) Min Typ Max Units SID137 Spec ID IPWM1 Parameter Block current consumption at 3 MHz Description - - 19 A 16-bit PWM Details/Conditions SID138 IPWM2 Block current consumption at 12 MHz - - 66 A 16-bit PWM Min Typ Max Units Table 20. PWM AC Specifications (Guaranteed by Characterization) Spec ID Parameter Description SID140 TPWMFREQ Operating frequency - - 24 MHz SID141 TPWMPWINT Pulse width (internal) 42 - - ns Document Number: 001-87220 Rev. *B Details/Conditions Page 22 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Table 20. PWM AC Specifications (Guaranteed by Characterization) (continued) Spec ID Parameter Description Min Typ Max Units SID142 TPWMEXT Pulse width (external) 42 - - ns SID143 TPWMKILLINT Kill pulse width (internal) 42 - - ns SID144 TPWMKILLEXT Kill pulse width (external) 42 - - ns SID145 TPWMEINT Enable pulse width (internal) 42 - - ns SID146 TPWMENEXT Enable pulse width (external) 42 - - ns SID147 TPWMRESWINT Reset pulse width (internal) 42 - - ns SID148 TPWMRESWEXT Reset pulse width (external) 42 - - ns Details/Conditions I2C Table 21. Fixed I2C DC Specifications (Guaranteed by Characterization) Spec ID SID149 SID150 Parameter II2C1 Description Block current consumption at 100 kHz Min - Typ - Max 10.5 Units A II2C2 Block current consumption at 400 kHz - - 135 A SID151 II2C3 Block current consumption at 1 Mbps - - 310 A SID152 II2C4 I2C enabled in Deep Sleep mode - - 1.4 A Min Typ Max Units - - 1 Mbps Details/Conditions Table 22. Fixed I2C AC Specifications (Guaranteed by Characterization) Spec ID SID153 Parameter FI2C1 Description Bit rate Details/Conditions LCD Direct Drive Table 23. LCD Direct Drive DC Specifications (Guaranteed by Characterization) Spec ID SID154 Parameter ILCDLOW Description Operating current in low power mode SID155 CLCDCAP SID156 LCDOFFSET SID157 ILCDOP1 SID158 ILCDOP2 Min - Typ 5 Max - Units Details/Conditions A 16 x 4 small segment disp. at 50 Hz pF Guaranteed by Design LCD capacitance per segment/common driver Long-term segment offset - 500 5000 - 20 - mV PWM Mode current. 5-V bias. 24-MHz IMO. 25 C PWM Mode current. 3.3-V bias. 24-MHz IMO. 25 C - 0.6 - mA - 0.5 - mA Max 150 Units Hz 32 x 4 segments. 50 Hz 32 x 4 segments. 50 Hz Table 24. LCD Direct Drive AC Specifications (Guaranteed by Characterization) Spec ID SID159 Parameter FLCD Description LCD frame rate Min 10 Typ 50 Details/Conditions Table 25. Fixed UART DC Specifications (Guaranteed by Characterization) Min Typ Max Units SID160 Spec ID IUART1 Parameter Block current consumption at 100 Kbits/sec Description - - 9 A SID161 IUART2 Block current consumption at 1000 Kbits/sec - - 312 A Document Number: 001-87220 Rev. *B Details/Conditions Page 23 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Table 26. Fixed UART AC Specifications (Guaranteed by Characterization) Spec ID SID162 Parameter FUART Description Bit rate Min Typ Max Units - - 1 Mbps SPI Specifications Table 27. Fixed SPI DC Specifications (Guaranteed by Characterization) Min Typ Max Units SID163 Spec ID ISPI1 Parameter Block current consumption at 1 Mbits/sec Description - - 360 A SID164 ISPI2 Block current consumption at 4 Mbits/sec - - 560 A SID165 ISPI3 Block current consumption at 8 Mbits/sec - - 600 A Min Typ Max Units - - 4 MHz Min Typ Max Units Table 28. Fixed SPI AC Specifications (Guaranteed by Characterization) Spec ID SID166 Parameter FSPI Description SPI operating frequency (master; 6X oversampling) Table 29. Fixed SPI Master mode AC Specifications (Guaranteed by Characterization) Spec ID Parameter Description SID167 TDMO MOSI valid after Sclock driving edge - - 15 ns SID168 TDSI MISO valid before Sclock capturing edge. Full clock, late MISO Sampling used 20 - - ns SID169 THMO Previous MOSI data hold time with respect to capturing edge at Slave 0 - - ns Min Typ Table 30. Fixed SPI Slave mode AC Specifications (Guaranteed by Characterization) Spec ID Parameter Description Max Units SID170 TDMI MOSI valid before Sclock capturing edge 40 - - ns SID171 TDSO MISO valid after Sclock driving edge - - 42 + 3 x FCPU ns SID171A TDSO_ext MISO valid after Sclock driving edge in Ext. Clock mode - - 48 ns SID172 THSO Previous MISO data hold time 0 - - ns SID172A TSSELSCK SSEL Valid to first SCK Valid edge 100 - - ns Document Number: 001-87220 Rev. *B Page 24 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Memory Table 31. Flash DC Specifications Spec ID SID173 Parameter Description VPE Erase and program voltage Min Typ Max Units 1.71 - 5.5 V Details/Conditions Table 32. Flash AC Specifications Spec ID Parameter SID174 TROWWRITE[3] SID175 TROWERASE[3] SID176 TROWPROGRAM SID178 TBULKERASE[3] [3] [3] Description Min Typ Max Units Details/Conditions Row (block) write time (erase and program) - - 20 ms Row (block) = 128 bytes Row erase time - - 13 ms Row program time after erase - - 7 ms Bulk erase time (32 KB) - - 35 ms Total device program time - - 7 100 K - - cycles Guaranteed by characterization SID180 TDEVPROG SID181 FEND Flash endurance SID182 FRET Flash retention. TA 55 C, 100 K P/E cycles 20 - - years Guaranteed by characterization Flash retention. TA 85 C, 10 K P/E cycles 10 - - years Guaranteed by characterization SID182A seconds Guaranteed by characterization System Resources Power-on-Reset (POR) with Brown Out Table 33. Imprecise Power On Reset (PRES) Min Typ Max Units Details/Conditions SID185 Spec ID VRISEIPOR Parameter Rising trip voltage Description 0.80 - 1.45 V Guaranteed by characterization SID186 VFALLIPOR Falling trip voltage 0.75 - 1.4 V Guaranteed by characterization SID187 VIPORHYST Hysteresis 15 - 200 mV Guaranteed by characterization Table 34. Precise Power On Reset (POR) Min Typ Max Units Details/Conditions SID190 Spec ID VFALLPPOR Parameter BOD trip voltage in active and sleep modes Description 1.64 - - V Guaranteed by characterization SID192 VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 - - V Guaranteed by characterization Note 3. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 001-87220 Rev. *B Page 25 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Voltage Monitors Table 35. Voltage Monitors DC Specifications Spec ID SID195 Parameter VLVI1 Description LVI_A/D_SEL[3:0] = 0000b Min 1.71 Typ 1.75 Max 1.79 Units V Details/Conditions SID196 VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V SID197 VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V SID198 VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V SID199 VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V SID200 VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V SID201 VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V SID202 VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V SID203 VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V SID204 VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V SID205 VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V SID206 VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V SID207 VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V SID208 VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V SID209 VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V SID210 VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V SID211 LVI_IDD Block current - - 100 A Min Typ Max Units - - 1 s Min Typ Max Units Details/Conditions Guaranteed by characterization Table 36. Voltage Monitors AC Specifications Spec ID SID212 Parameter TMONTRIP Description Voltage monitor trip time Details/Conditions Guaranteed by characterization SWD Interface Table 37. SWD Interface Specifications Spec ID Parameter Description SID213 F_SWDCLK1 3.3 V VDD 5.5 V - - 14 MHz SWDCLK 1/3 CPU clock frequency SID214 F_SWDCLK2 1.71 V VDD 3.3 V - - 7 MHz SWDCLK 1/3 CPU clock frequency SID215 T_SWDI_SETUP T = 1/f SWDCLK 0.25*T - - ns Guaranteed by characterization SID216 T_SWDI_HOLD 0.25*T - - ns Guaranteed by characterization SID217 T_SWDO_VALID T = 1/f SWDCLK - - 0.5*T ns Guaranteed by characterization SID217A T_SWDO_HOLD T = 1/f SWDCLK 1 - - ns Guaranteed by characterization T = 1/f SWDCLK Document Number: 001-87220 Rev. *B Page 26 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Internal Main Oscillator Table 38. IMO DC Specifications (Guaranteed by Design) Spec ID Parameter Description Min Typ Max Units SID219 IIMO2 IMO operating current at 24 MHz - - 325 A SID220 IIMO3 IMO operating current at 12 MHz - - 225 A SID221 IIMO4 IMO operating current at 6 MHz - - 180 A SID222 IIMO5 IMO operating current at 3 MHz - - 150 A Min Typ Max Units - 2 % Details/Conditions Table 39. IMO AC Specifications Spec ID Parameter Description SID223 FIMOTOL1 Frequency variation from 3 to 24 MHz - SID226 TSTARTIMO IMO startup time - - 12 s SID227 TJITRMSIMO1 RMS Jitter at 3 MHz - 156 - ps SID228 TJITRMSIMO2 RMS Jitter at 24 MHz - 145 - ps Min - Typ 0.3 Max 1.05 Units A - 2 15 nA Min - Typ - Max 2 Units ms Details/Conditions With API-called calibration Internal Low-Speed Oscillator Table 40. ILO DC Specifications (Guaranteed by Design) Spec ID SID231 Parameter IILO1 Description ILO operating current at 32 kHz SID233 IILOLEAK ILO leakage current Details/Conditions Guaranteed by Characterization Guaranteed by Design Table 41. ILO AC Specifications Spec ID SID234 Parameter TSTARTILO1 Description ILO startup time SID236 TILODUTY ILO duty cycle 40 50 60 % SID237 FILOTRIM1 32 kHz trimmed frequency 15 32 50 kHz Details/Conditions Guaranteed by characterization Guaranteed by characterization 60% with trim. Table 42. External Clock Specifications Spec ID SID305 Parameter ExtClkFreq Description External Clock input Frequency Min 0 Typ - Max 24 Units MHz SID306 ExtClkDuty Duty cycle; Measured at VDD/2 45 - 55 % Min 0 Typ - Max - Units Details/Conditions Guaranteed by characterization Guaranteed by characterization Table 43. Block Specs Spec ID SID257 Parameter TWS24* Description Number of wait states at 24 MHz SID260 VREFSAR Trimmed internal reference to SAR -1 - +1 SID262 TCLKSWITCH Clock switching from clk1 to clk2 in clk1 periods 3 - 4 Details/Conditions CPU execution from Flash. Guaranteed by characterization % Percentage of Vbg (1.024 V). Guaranteed by characterization Periods Guaranteed by design * Tws24 is guaranteed by Design Document Number: 001-87220 Rev. *B Page 27 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Ordering Information The PSoC 4100 part numbers and features are listed in the following table. Table 44. PSoC 4100 Family Ordering Information Op-amp (CTBm) CapSense Direct LCD Drive 12-bit SAR ADC LP Comparators TCPWM Blocks SCB Blocks GPIO 28-SSOP 40-QFN 44-TQFP 24 16 4 1 - - 806 Ksps 2 4 2 24 - - 0410 CY8C4124PVI-442 24 16 4 1 806 Ksps 2 4 2 24 - - 0411 CY8C4124LQI-443 24 16 4 2 806 Ksps 2 4 2 34 - - 0416 CY8C4124AXI-443 24 16 4 2 806 Ksps 2 4 2 36 - - 041A CY8C4125AXI-473 24 32 4 2 - - 806 Ksps 2 4 2 36 - - 041b CY8C4125PVI-482 24 32 4 1 806 Ksps 2 4 2 24 - - 0412 CY8C4125LQI-483 24 32 4 2 806 Ksps 2 4 2 34 - - 0417 CY8C4125AXI-483 24 32 4 2 806 Ksps 2 4 2 36 - - 041C Document Number: 001-87220 Rev. *B Silicon ID SRAM (KB) CY8C4124PVI-432 MPN Flash (KB) Package Max CPU Speed (MHz) 4100 Family Features Page 28 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Part Numbering Conventions PSoC 4 devices follow the part numbering convention described in the following table. All fields are single-character alphanumeric (0, 1, 2, ..., 9, A,B, ..., Z) unless stated otherwise. The part numbers are of the form CY8C4ABCDEF-XYZ where the fields are defined as follows. Example CY8C 4 A B C D E F - X Y Z Cypress Prefix 4 : PSoC 4 Architecture 1 : 4100Family Family within Architecture 2 : 24 MHz Speed Grade 5 : 32 KB Flash Capacity AX: TQFP Package Code I : Industrial Temperature Range Attributes Set The Field Values are listed in the following table. Field CY8C Description Values Meaning Cypress Prefix 4 Architecture 4 PSoC 4 A Family within architecture 1 4100 Family 2 4200 Family B C DE CPU Speed Flash Capacity Package Code 2 24 MHz 4 48 MHz 4 16 KB 5 32 KB AX TQFP LQ QFN PV F XYZ Temperature Range Attributes Code Document Number: 001-87220 Rev. *B I 000-999 SSOP Industrial Code of feature set in specific family Page 29 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Packaging Table 45. Package Characteristics Parameter Description Conditions Min Typ Max Units TA Operating ambient temperature -40 25.00 85 C TJ Operating junction temperature -40 - 100 C TJA Package JA (28-pin SSOP) - 66.58 - C/Watt TJA Package JA (40-pin QFN) - 15.34 - C/Watt TJA Package JA (44-pin TQFP) - 57.16 - C/Watt TJC Package JC (28-pin SSOP) - 26.28 - C/Watt TJC Package JC (40-pin QFN) - 2.50 - C/Watt TJC Package JC (44-pin TQFP) - 17.47 - C/Watt Table 46. Solder Reflow Peak Temperature Package Maximum Peak Temperature 28-pin SSOP 260 C 30 seconds 40-pin QFN 260 C 30 seconds 44-pin TQFP 260 C 30 seconds Maximum Time at Peak Temperature Table 47. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 28-pin SSOP MSL 3 40-pin QFN MSL 3 44-pin TQFP MSL 3 Figure 10. 28-pin (210-mil) SSOP Package Outline 51-85079 *E Document Number: 001-87220 Rev. *B Page 30 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Figure 11. 40-pin QFN Package Outline 001-80659 ** The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floating and not connected to any other signal. Figure 12. 44-pin TQFP Package Outline 51-85064 *E Document Number: 001-87220 Rev. *B Page 31 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Acronyms Table 48. Acronyms Used in this Document Acronym Description Table 48. Acronyms Used in this Document (continued) Acronym Description ETM embedded trace macrocell FIR finite impulse response, see also IIR FPB flash patch and breakpoint FS full-speed GPIO general-purpose input/output, applies to a PSoC pin arithmetic logic unit HVI high-voltage interrupt, see also LVI, LVD analog multiplexer bus IC integrated circuit API application programming interface IDAC current DAC, see also DAC, VDAC APSR application program status register IDE integrated development environment ARM(R) advanced RISC machine, a CPU architecture I ATM automatic thump mode BW bandwidth CAN Controller Area Network, a communications protocol abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus ALU AMUXBUS 2C, or IIC Inter-Integrated Circuit, a communications protocol IIR infinite impulse response, see also FIR ILO internal low-speed oscillator, see also IMO IMO internal main oscillator, see also ILO integral nonlinearity, see also DNL CMRR common-mode rejection ratio INL CPU central processing unit I/O input/output, see also GPIO, DIO, SIO, USBIO CRC cyclic redundancy check, an error-checking protocol IPOR initial power-on reset IPSR interrupt program status register DAC digital-to-analog converter, see also IDAC, VDAC IRQ interrupt request DFB digital filter block ITM instrumentation trace macrocell DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. LCD liquid crystal display DMIPS Dhrystone million instructions per second LIN Local Interconnect Network, a communications protocol. DMA direct memory access, see also TD LR link register DNL differential nonlinearity, see also INL LUT lookup table DNU do not use LVD low-voltage detect, see also LVI DR port write data registers LVI low-voltage interrupt, see also HVI DSI digital system interconnect LVTTL low-voltage transistor-transistor logic DWT data watchpoint and trace MAC multiply-accumulate ECC error correcting code MCU microcontroller unit ECO external crystal oscillator MISO master-in slave-out EEPROM electrically erasable programmable read-only memory NC no connect EMI electromagnetic interference NMI nonmaskable interrupt EMIF external memory interface NRZ non-return-to-zero EOC end of conversion NVIC nested vectored interrupt controller EOF end of frame NVL nonvolatile latch, see also WOL EPSR execution program status register ESD electrostatic discharge Document Number: 001-87220 Rev. *B opamp operational amplifier PAL programmable array logic, see also PLD Page 32 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Table 48. Acronyms Used in this Document (continued) Acronym Description Table 48. Acronyms Used in this Document (continued) Acronym Description PC program counter SWV single-wire viewer PCB printed circuit board TD transaction descriptor, see also DMA PGA programmable gain amplifier THD total harmonic distortion PHUB peripheral hub TIA transimpedance amplifier PHY physical layer TRM technical reference manual PICU port interrupt control unit TTL transistor-transistor logic PLA programmable logic array TX transmit PLD programmable logic device, see also PAL UART PLL phase-locked loop Universal Asynchronous Transmitter Receiver, a communications protocol PMDD package material declaration data sheet UDB universal digital block POR power-on reset PRES precise power-on reset PRS pseudo random sequence PS port read data register PSoC(R) Programmable System-on-ChipTM PSRR power supply rejection ratio PWM pulse-width modulator RAM random-access memory RISC reduced-instruction-set computing RMS root-mean-square RTC real-time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC/CT switched capacitor/continuous time SCL I2C serial clock SDA I2C serial data S/H sample and hold SINAD signal to noise and distortion ratio SIO special input/output, GPIO with advanced features. See GPIO. SOC start of conversion SOF start of frame SPI Serial Peripheral Interface, a communications protocol SR slew rate SRAM static random access memory SRES software reset SWD serial wire debug, a test protocol Document Number: 001-87220 Rev. *B USB Universal Serial Bus USBIO USB input/output, PSoC pins used to connect to a USB port VDAC voltage DAC, see also DAC, IDAC WDT watchdog timer WOL write once latch, see also NVL WRES watchdog timer reset XRES external reset I/O pin XTAL crystal Page 33 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Document Conventions Units of Measure Table 49. Units of Measure Symbol Unit of Measure C degrees Celsius dB decibel fF femto farad Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohour kHz kilohertz k kilo ohm Ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz M mega-ohm Msps megasamples per second A microampere F microfarad H microhenry s microsecond V microvolt W microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt ohm pF picofarad ppm parts per million ps picosecond s second sps samples per second sqrtHz square root of hertz V volt Document Number: 001-87220 Rev. *B Page 34 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Revision History Description Title: PSoC(R) 4: PSoC 4100 Family Datasheet Programmable System-on-Chip (PSoC(R)) Document Number:001-87220 Orig. of Submission Revision ECN Description of Change Change Date *B 4108562 WKA 08/29/2013 Added clarifying note about the XRES pin in the Reset section. Added a link reference to the PSoC 4 TRM. Updated the footnote in Absolute Maximum Ratings. Updated Sleep Mode IDD specs in DC Specifications. Updated Comparator DC Specifications Updated SAR ADC AC Specifications (Guaranteed by Characterization) Updated LCD Direct Drive DC Specifications (Guaranteed by Characterization) Updated the number of GPIOs in Ordering Information. Document Number: 001-87220 Rev. *B Page 35 of 36 PSoC(R) 4: PSoC 4100 Family Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-87220 Rev. *B Revised August 29, 2013 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 36 of 36