UT5S4ACS283/UTS4ACTS283 Radiation-Hardened 4-Bit Binary Full Adders FEATURES 1.2, radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Flexible package - 16-pin DIP - 16-lead flatpack DESCRIPTION The UTS4ACS283 and the UT54ACTS283 are 4-bit binary adders. The adders perform addition of two 4-bit binary words. The sum () outputs are provided for each bit and the resultant carry (C4) is obtained as the fifth bit. The adders feature full internal look-ahead across all four bits for fast carry generation. The devices are characterized over full military temperature range of -55C to +125C. Available QML Q or V processes LOGIC SYMBOL = (5) Al 0 aad te A3 (4) a 2) I, oe B1 o 0 (13) pe (2) (10) ps 15) a 3 =A B4 3 (9) co Ie3 cor Ca Note: 1. These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 16-Pin DIP Top View 2 1 16 [77 Voo B2]2 15|_) es a2[j3 14] as uO4 23) ao 127 aa a1(J Ww) Bs co 7? wf) x Vsg (] 9] ca 16-Lead Flatpack Top View 1 2 3 4 5 6 7 8 16 15 14 13 12 Ww 10 9 QMERURES 175 Rad-Hard MSI LogicUT54ACS283/UTS4ACTS283 FUNCTION TABLE INPUT OUTPUT When CO =L x1 r2 L L L L L L L H L L H L L L H L L L H L L H L L H L L L H L H H L L L H L H H L L L H L L H L H H L H L H L H H L L L H L H H L H H L L L H H H H L L L H H L H L L L H L H L H H L H L L H H H L L L H L H L H H H L L L H H H L H L L H H L H L L H H L L H H L H H L H H H L H L H H L H H H H L H L H H H H H H L H H H H H H = high level, L = low level Note: Input conditions at Al, A2, B1, BZ, and CO are used to determine outputs Z1 and 2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs 3, 4, and C4. Rad-Hard MSI Logic 176UTS4ACS283/UTS4ACTS283 LOGIC DIAGRAM 177 Rad-Hard MSI LogicRADIATION HARDNESS SPECIFICATIONS 3 UTS5S4ACS283/UTS4ACTS283 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU & SEL Threshold 7 80 MeV-cm?/mg Neutron Fluence 1.0E14 nfcm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS Vpp Supply voltage -0.3 to 7.0 Vv Vio Voltage any pin -.3 Vpp +.3 Vv Tstg Storage Temperature range -65 to +150 C Ty Maximum junction temperature +175 c TLs Lead temperature (soldering 5 seconds) +300 i Bic Thermal resistance junction to case 20 CIW j DC input current +10 mA Pp Maximum power dissipation 1 WwW Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS Vpp Supply voltage 4.50 5.5 Vv VIN Input voltage any pin 0 to Vpp v Tc Temperature range -55 to + 125 C Rad-Hard MSI Logic 178UTS4ACS283/UTS4ACTS283 DC ELECTRICAL CHARACTERISTICS (Vpp = 5.0V 10%; Vsg = OV , -55C < Te < +125C) SYMBOL PARAMETER CONDITION MIN MAX UNIT Vit Low-level input voltage ! ACTS 0.8 Vv ACS 3pp Vin High-level input voltage I ACTS 5Vpp Vv ACS Vpp Tw Input leakage current ACTS/ACS Vin = Vpp or Vgs5 -1 1 pA Vou Low-level output voltage 3 ACTS lo, = 8.0mA 0.40 v ACS Io, = 100pA 0.25 Vou High-level output voltage 3 ACTS lon =-8.0mA TVpp v ACS Joy = -100HA Vpp - 0.25 los Short-circuit output current 24 ACTS/ACS Vo= Vpp and Ves -200 200 mA Protal Power dissipation 8 Cy = 50pF 19 mW/ MHz Ippa Quiescent Supply Current Vopp = 5.5V 10 PA Cn Input capacitance > f = 1MHz @ 0V 15 pF Cour Output capacitance 5 f = IMHz @ 0V 15 pF Notes: L. Functional tests are conducted in accordance with MIi,-STD-883 with the following input test conditions: Vjjq = Vig{min) + 20%, - 0%; Vip = Vip (max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to Vj;,(min) and Vj, (max). 2. Supplied as a design limit but not guaranteed or tested, 3. Per MIL-M-38510, for current density $ 5.0E5 amps/cm/, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF MHz. 4, Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and Vgg at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50m V, 7. All specifications valid for radiation dose < 1 E6 rads(Si). 8. Power does not include power contribution of any TTL output sink custent. 9, Power dissipation specified per switching outpul. 179 Rad-Hard MSI LogicAC ELECTRICAL CHARACTERISTICS 2 (Vpp =5.0V +10%; Vss = 0V 1 5C < Te <+125C) UTS4ACS283/UT54ACTS283 SYMBOL PARAMETER MINIMUM MAXIMUM UNIT beLy Propagation delay CO to En 2 16 ns tpHL Propagation delay CO to In 2 19 ns tery Propagation delay CO to C4 2 16 ns tpHt Propagation delay CO to C4 2 17 ns tPLH Propagation delay An, Bn to C4 2 16 ns tpyy. Propagation delay An, Bn to C4 2 15 ns tpLy Propagation delay An, Bn to In 2 14 ns tpo. Propagation delay An, Bn to Zn 2 16 ns Notes: 1. Maximum allowable relative shift equals SOmV. 2. All specifications valid for radiation dose < 1E6 rads(Si). Rad-Hard MSI Logic 180