XRT8000 Clock Synchronizer/Adapter for Communications September 2006 FEATURES D Cascadable D Clock Adaptation for Most Popular Telecommunication Frequencies D No External Components Needed D Wide Input Frequency Range D Lock Detect Indication Pin D Programmable Output Frequencies APPLICATIONS D Less than 0.05UI Wide Band Output Jitter D DSU's, CSU's and Access Equipment D Low Power Operation (5V and 3.3V) D ISDN Terminals D Maximum Lock Time of 45mS D Concentrators and Multiplexers GENERAL DESCRIPTION The XRT8000 is a dual phase-locked loop chip that generates two simultaneous, very low jitter, output clocks for synchronization applications in wide area networking systems. The outputs are phase locked to the input signal. The chip has four basic modes of operation; referred to as master (FORWARD, REVERSE) and slave (FORWARD, REVERSE) modes (See Figure 1). In the FORWARD mode it accepts up to 16th harmonic of either 1.544MHz or 2.048MHz as input reference and generates 1.2kHz and multiples of 2.4kHz, 56kHz or 64kHz. In the REVERSE mode an input clock of 56kHz or 64kHz is used to generate 1.544MHz or 2.048MHz output clocks. The SLAVE (FORWARD, REVERSE) modes generate the same output frequencies as the MASTER (FORWARD/ REVERSE MODES) except that the input frequency (FIN) is 8kHz. An optional divide by eight can be enabled at each of the outputs. The input and output frequency selection can be done through a serial microprocessor interface. The XRT8000 is available in either 18 pin SOIC package or 18 pin plastic DIP. ORDERING INFORMATION Part No. Package Operating Temperature Range XRT8000IP 18 Lead 300 Mil PDIP -40C to +85C XRT8000ID 18 Lead 300 Mil JEDEC SOIC -40C to +85C XRT8000 CLK2 n x 1.544{T1} n x 2.048{E1} 1 <= n <= 16 FIN CLK1 XRT8000 K x 56kHz K x 64kHz 1.2kHz 2.4 x K to 43.2kHz CLK2 1 <= K <= 32 A 1 <= K <= 18 56kHz 64kHz FIN CLK1 XRT8000 B T1 (1.544) or E1 (2.048) SYNC SYNC 8kHz MASTER FORWARD MASTER REVERSE CLK2 8kHz FIN CLK1 A/ B SYNC SLAVE FORWARD/REVERSE Figure 1. System Diagram Rev.1.11 E1999--2006 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 z www.exar.com XRT8000 BLOCK DIAGRAM Analog PhaseLocked Loop Post Divider Feedback Divider M Q2 Q Div. By 8 Driver DIV/8_EN PLL 2 Lock Detector M2 CLK2 LOCKDET SYNC Input Divider FIN P Analog PhaseLocked Loop Post Divider Q Div. By 8 Driver VCC R 100K Feedback Divider M R 100K PLL 1 M2 Q2 SCLK CSB SDI SDO Serial Interface DIV/8_EN Mode and Frequency Select Control MSB Figure 2. Block Diagram Rev. 1.11 2 CLK1 XRT8000 PIN CONFIGURATION SDO SYNC FIN GND GND CLK1 VCC MSB GND 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 SCLK CSB SDI VCC GND CLK2 VCC LOCKDET VCC SDO SYNC FIN GND GND CLK1 VCC MSB GND 18 Lead PDIP (0.300") 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 SCLK CSB SDI VCC GND CLK2 VCC LOCKDET VCC 18 Lead SOIC (Jedec, 0.300") PIN DESCRIPTION Symbol Pin# Type SDO 1 O Serial Data Output (Microprocessor Serial Interface). Data output from the command registers. SYNC 2 O An 8kHz Signal SubDivided From FIN. This output can be threestated via CR5. SYNC can be used to synchronize other XRT8000 which are configured in slave modes. FIN 3 I Reference Frequency Input. GND 4 Digital Ground. GND 5 Digital Ground. CLK1 6 VCC 7 MSB 8 GND 9 Analog Ground. VCC 10 Analog Positive Supply. LOCKDET 11 VCC 12 CLK2 13 GND 14 Digital Ground. VCC 15 Digital Positive Power Supply. SDI 16 I Serial Data Input (Microprocessor Serial Interface) Data input to the command registers. CSB 17 I Chip Select Not (Microprocessor Serial Interface) . When this input is low the data in and out will be shifted in the appropriate registers. Internal pull up (100K). SCLK 18 I Serial Clock Input (Microprocessor Serial Interface) . This clock will serve as a reference to the data streams to SDI and SDO (the positive edge of SCLK is used to latch the data). O Description Clock 1. Output of the phase-locked loop 1. Digital Positive Power Supply. I O Master/Slave Mode Select Input. If this input is high, then the MASTER mode is selected. If this input is low, then the SLAVE mode is enabled. This pin is internally pulled up via 100KW resistor. Lock Detect. This output is high when both phase-locked loops are in lock and will go low if either one of the phase locked loops loses lock. Digital Positive Power Supply. O Clock 2. Output of the phase-locked loop 2. Rev. 1.11 3 XRT8000 DC ELECTRICAL CHARACTERISTICS (Except Serial Interface) Operating Temperature: -40_C to 85_C Test Conditions: TA = 25_C, VCC = 5.0V 5% Unless Otherwise Specified Symbol VIL VIH VOL VOH VOL VOH IIL IIH IIL IIH ICC RIN Parameter Input low level Input high level Output low level (CLK1,CLK2) Output high level (CLK1,CLK2) Output low level (LOCKDET,SYNC) Output high level (LOCKDET,SYNC) Input low current (CSB,MSB) Input high current (CSB,MSB) Input low current (except CSB,MSB) Input high current (except CSB,MSB) Operating current Input pull-up resistance (CSB,MSB) Min Typ Max 0.8 Unit V V V V V V mA mA mA mA mA KW 2.0 0.4 2.4 0.4 2.4 -150 10 -10 20 100 50 10 35 150 Conditions IOL = -6.0 mA IOH = 6.0 mA IOL = -3.0 mA IOH = 3.0 mA VIN = VCC VIN = VCC No load. Clock = 2.1 MHz AC ELECTRICAL CHARACTERISTICS (See Figure 3) Spec.3 T3 T61 Parameter Input frequency Minimum input signal high to low duration Output frequency Duty cycle CLK1, CLK2 T74 T74 T74 T74 T74 T8 T9 Jitter added 8KHz-40KHz Jitter added 10Hz-40KHz Broad Band-jitter Jitter added 20Hz-100KHz Jitter added 18kHz-100KHz Capture time Clock output rise time 0.025 0.025 0.05 1.5 0.2 T10 Clock output fall time T112 Duty cycle SYNC Symbol T1 T2 T14 Delay time between the rising edge of SYNC and the rising edge of CLK1 or CLK2 Min 0.008 12 Typ 1.2 47.5 50 0.007 0.022 0.03 0.05 0.01 40 T-20 T Max 32.7 Unit MHz ns 2.1 52.5 KHz % 0.02 0.05 0.07 0.03 40 10 UI UI UI UI UI ms ns 10 ns 60 % 30pF load. Measured at 20/80 % 30pF load. Measured at 20/80 % VCC/2 switch point ns (in master forward mode). 30pF load. See table 12 for values of T T+20 Conditions VCC/2 switch point. 30pF load. Output =1.544MHz Output =1.544MHz Output =1.544MHz Output =2.048MHz Output =2.048MHz Notes: T4 1 3 4 T 12 T6 = ( T4 + T5 ) 2 T11 = ( T 12 + T 13 ) Specifications from AT&T Publication 62411 and ITU-T Recommendations G-823 (for 1.544MHz and 2.048MHz, respectively). T7 is guaranteed by characterization, not tested. Specifications are subject to change without notice. Rev. 1.11 4 XRT8000 DC ELECTRICAL CHARACTERISTICS (Except Serial Interface) Operating Temperature: -40_C to 85_C Test Conditions: TA = 25_C, VCC = 3.3V 5% Unless Otherwise Specified Symbol Parameter VIL Input low level VIH Input high level Min Typ Max Unit 0.8 V 2.0 VOL Output low level (CLK1,CLK2) VOH Output high level (CLK1,CLK2) VOL Output low level (LOCKDET,SYNC) VOH Output high level (LOCKDET,SYNC) V 0.4 2.4 0.4 2.4 V IOL = -3 mA V IOH = 3 mA V IOL = -2.5 mA V IOH = 2.5 mA IIL Input low current (CSB,MSB) -150 mA IIH Input high current (CSB,MSB) 10 mA IIL Input low current (except CSB,MSB) -10 IIH Input high current (except CSB,MSB) ICC Operating current RIN Input pull-up resistance (CSB,MSB) Conditions VIN = VCC mA 50 10 mA VIN = VCC 11 30 mA No load. Clock = 2.1 MHz 100 150 KW Typ Max Unit 32.7 MHz AC ELECTRICAL CHARACTERISTICS (See Figure 3) Symbol Parameter T1 Input frequency T2 Minimum input signal high to low duration Spec.3 Min 0.008 12 T3 Output frequency 1.2 T61 Duty cycle CLK1, CLK2 47.5 T74 Jitter added 8KHz-40KHz T74 T74 T74 T74 T8 T9 Conditions ns 2.1 KHz 50 52.5 % VCC/2 switch point. 30pF load. 0.025 0.01 0.02 UI Output =1.544MHz Jitter added 10Hz-40KHz 0.025 0.030 UI Output =1.544MHz Broad Band 0.05 0.035 0.05 UI Output =1.544MHz Jitter added 20Hz-100KHz 1.5 0.045 0.07 UI Output =2.048MHz Jitter added 18kHz-100KHz 0.2 0.010 0.03 UI Output =2.048MHz Capture time 40 ms Clock output rise time 14 ns 30pF load. Measured at 20/80 % T10 Clock output fall time 14 ns 30pF load. Measured at 20/80 % T112 Duty cycle SYNC 60 % VCC/2 switch point 40 (in master forward mode). 30pF load. T14 Delay time between SYNC and CLK1 or CLK2 T-20 T T+20 ns See table 12 for values of T Notes: T4 1 3 4 T 12 T6 = ( T 4 + T 5 ) 2 T11 = ( T 12 + T 13 ) Specifications from AT&T Publication 62411 and ITUT Rcommendations G-823 (for 1.544MHz and 2.048MHz, respectively) T7 is guaranteed by characterization, not tested. Specifications are subject to change without notice. Rev. 1.11 5 XRT8000 AC ELECTRICAL CHARACTERISTICS (See Figure 5). Symbol Parameter Min. Typ. Max. Unit Conditions AC Electrical Characteristics (See Figure 5) T21 CSB to SCLK Setup Time 50 ns T22 SCLK to CSB Hold Time 20 ns T23 SDI to SCLK Setup Time 50 ns T24 SCLK to SDI Hold Time 50 ns T25 SCLK Low Time 240 ns T26 SCLK High Time 240 ns T27 SCLK Period 500 ns T28 SCLK to CSB Hold Time 50 ns T29 CSB Inactive Time 250 ns T30 SCLK to SDO Valid 200 ns T31 SCLK to SDOx Delay 100 ns T32 SCLK Edge or CSB Edge to SDO HZ T33 Rise/Fall Time SDO Output 100 ns 40 ns Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Operating Temperature . . . . . . . . . . . . 40C to +85C Storage Temperature . . . . . . . . . . . . . 40C to +150C Package Dissipation . . . . . . . . . . . . . . . . . . . . 500mW Voltage at Any Pin . . . . . . . . . GND0.3V to Vcc +0.3V T2 T1 T2 FIN T3 T4 CLK1 or CLK2 T9 T14 T5 T10 T7 T12 SYNC Figure 3. Clocks Timing Rev. 1.11 6 T13 XRT8000 SYSTEM DESCRIPTION On power up the clock outputs of XRT8000 will be tri-stated. This means that no clocks will be seen at the outputs and lock detect output will be low. After power up the XRT8000 needs to be initialized. Therefore a serial interface is provided to load the internal registers. These registers will define the modes of operation, the output frequencies and enabling the clock outputs. D 2.048 MHz Master/Forward Mode of Operation D 1.544 MHz/8 = 193 kHz at the FIN input. From this input signal, the XRT8000 device will synthesize any of the following clock signal frequencies. At the CLK1 and/or CLK2 output pins: D 1.544 MHz D 2.048 MHz/8 = 256 kHz When the XRT8000 device is operating in the "Master/Forward" Mode, it will receive either an "n x 2.048 MHz" or "n x 1.544 MHz" clock signal at the FIN input (pin3); where "n" can range from 1 to 16. From this input signal, the XRT8000 device will internally divide and synthesize the following signals. At the SYNC output pin: D 8 kHz The user can configure the XRT8000 device to generate these clock frequencies by writing the appropriate values into the Command Registers (CR1, CR2, CR3, CR4 and CR5), via the Microprocessor Serial Interface. At the CLK1 and/or CLK2 output pins: D k x 56 kHz Note: in the REVERSE mode the contents of CR3 and CR4 has to be all one's. D k x 64 kHz D (k x 56 kHz)/8 Slave (Forward, Reverse) Mode of Operation D (k x 64 kHz)/8 where k can range from 1 to 32. To activate the slave modes of operations the input MSB must be tied low. In these modes an 8kHz signal must be applied to the FIN input in order to obtain output frequencies at T1 or E1 rates. The output frequencies can be selected via the serial interface in a similar fashion as described in the master forward and reverse modes. At the SYNC Output pin: D 8kHz The user selects and configures the XRT8000 device to generate these clock frequencies by writing the appropriate values into the Command Registers (CR1, CR2, CR3, CR4 and CR5), via the Microprocessor Serial Interface. The Lock Detect Output Pin If both PLL's are enabled and in locked state then LOCKDET will be active. If one PLL loses lock then LOCKDET will be false. If only one PLL is enabled then only the active PLL will control the state of LOCKDET. Reverse Mode of Operation When the XRT8000 device is operating in the "Reverse" Mode, it will receive either a 56 kHz or 64 kHz clock signal Rev. 1.11 7 XRT8000 The Command Registers via the Microprocessor Serial Interface. Between the MSB input pin and the Command Registers, the user can configure the XRT8000 device into any of the operating modes that have been described in this data sheet. The user can access these Command Registers Table 1 presents the Address Location and Format for each of the Command Registers, within the XRT8000 device. AD2~0 Register D4 D3 D2 D1 D0 000 CR1 IOC4 IOC3 IOC2 IOC1 PL1EN 001 CR2 M4 M3 M2 M1 PL2EN 010 CR3 SEL14 SEL13 SEL12 SEL11 SEL10 011 CR4 SEL24 SEL23 SEL22 SEL21 SEL10 100 CR5 SYNCEN CLK1EN CLK2EN PL2/8 PL1/8 101 CR6 Reserved Reserved Reserved Reserved Reserved 110 CR7 Reserved Reserved Reserved Reserved Reserved 111 CR8 Reserved Reserved Reserved Reserved Reserved Table 1. Control Registers The next few pages describe the role/functionality of each bit-field within the Command Registers. Rev. 1.11 8 XRT8000 CR1 Register (Power On State = "00000") 56kHz or 64kHz clocks, this notation is extended to 1,544kHz and 2,048kHz frequencies in the following table (Table 2). D0 (PL1EN): Enable control for PLL1. If PL1EN = "1", then PLL1 is enabled. Otherwise, if PL1EN = "0", then PLL1 is disabled. Note: The value of "K" for PLL1 and PLL2 are independent of each other. D1~D4 (IOC1~IOC4): Table 2 These four bit-fields function as the control bits for PLL1 and PLL2 operation modes. These bits select FORWARD, REVERSE, DATA, Kx56 or Kx64 clock rates. Multiplier "K" in Kx56 and Kx64 refers to harmonics of Table 2 creates the values of D1 through D4 within the CRI command register to the operating mode of the XRT8000 device. IOC4 IOC3 IOC2 IOC1 Input Freq. [kHz] PLL1 Output [kHz] PLL2 Output [kHz] Mode 0 0 0 0 nx1544 Kx56 Kx56 Forward 0 0 0 1 nx1544 Kx56 Kx64 Forward 0 0 1 0 nx1544 Kx64 Kx64 Forward 0 0 1 1 nx1544 Kx56 DATA Forward 0 1 0 0 nx1544 Kx64 DATA Forward 0 1 0 1 nx1544 DATA DATA Forward 0 1 1 0 56 1544 1544 Reverse 0 1 1 1 8K 1544 2048 Reverse 1 0 0 0 nx2048 Kx56 Kx56 Forward 1 0 0 1 nx2048 Kx56 Kx64 Forward 1 0 1 0 nx2048 Kx64 Kx64 Forward 1 0 1 1 nx2048 Kx56 DATA Forward 1 1 0 0 nx2048 Kx64 DATA Forward 1 1 0 1 nx2048 DATA DATA Forward 1 1 1 0 8 1544 2048 Reverse 1 1 1 1 64 2048 2048 Reverse Table 2. Operation Mode/Output Clock Frequency Select Options Via the D1 Through D4 Bits within the CRI Register Note: 1 The values of "n" are selected via the M1 through M4 bits, within the CR2 Register (see Table 3). 2 The values of "k" are selected via the Sel14 through SelP bits within the CR3 Register (see Table 4). Rev. 1.11 9 XRT8000 CR2 Register (Power On State = "00000") D0 (PL2EN): Enable control for PLL2. If PL2EN = "1", then PLL2 is enabled. Otherwise, if PL2EN = "0", PLL2 is disabled. D1~D4 (M1~M4): Control bits for prescaler divider. These bits will set the divide ratio of the prescaler such that in MASTER/ FORWARD or REVERSE modes the output of this block is always at 8kHz. The settings for M4~M1 bits is based on the input frequency and the mode of operation (which is determined by the state of IOC4~IOC1 bits) is provided in Table 3. M4 M3 M2 M1 Mode Input Freq.[kHz] 0 0 0 0 Forward 1x(1544 or 2048) 0 0 0 1 Forward 2x(1544 or 2048) 0 0 1 0 Forward 3x(1544 or 2048) 0 0 1 1 Forward 4x(1544 or 2048) 0 1 0 0 Forward 5x(1544 or 2048) 0 1 0 1 Forward 6x(1544 or 2048) 0 1 1 0 Forward 7x(1544 or 2048) 0 1 1 1 Forward 8x(1544 or 2048) 1 0 0 0 Forward 9x(1544 or 2048) 1 0 0 1 Forward 10x(1544 or 2048) 1 0 1 0 Forward 11x(1544 or 2048) 1 0 1 1 Forward 12x(1544 or 2048) 1 1 0 0 Forward 13x(1544 or 2048) 1 1 0 1 Forward 14x(1544 or 2048) 1 1 1 0 Forward 15x(1544 or 2048) 1 1 1 1 Forward 16x(1544 or 2048) x x x x Reverse 56 x x x x Reverse 64 Note: This table applies to MASTER (FORWARD, REVERSE) mode only Table 3. CR2 Register Rev. 1.11 10 XRT8000 CR3 Register (Power On State = "00000") 2.) The delay time between the rising edge of the sync output signal (Pin 2) and the rising edge of the CLK1 or CLI 2 output signals (See Table 6). SEL14~SEL10: These bits control two parameters: 1.) The frequency multiplier "K" for the PLL1, after selecting Kx56, Kx64 or DATA mode through register CR1 (1 < K < 32), and Table 4 provides the settings for SEL14~10 bits to generate harmonic of 56kHz, 64kHz or 1.2kHz at the output of PLL1. PLL1 Output Frequency (kHz) SEL14~SEL10 K factor Kx56 MODE Kx64 MODE DATA MODE 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 56 112 168 224 280 336 392 448 504 560 616 672 728 784 840 896 952 1008 1064 1120 1176 1232 1288 1344 1400 1456 1512 1568 1624 1680 1736 1792 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 1088 1152 1216 1280 1344 1408 1472 1536 1600 1664 1728 1792 1856 1920 1984 2048 1.2 2.4 4.8 7.2 9.6 12 14.4 16.8 19.2 21.6 24 26.4 28.8 31.2 33.6 36 38.4 40.8 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 Note: This table applies to forward or slave modes only Table 4. CR3 Register Rev. 1.11 11 XRT8000 CR4 Register (Power On State = "00000") Table 5 provides the settings for SEL24~20 bits to generate harmonic of 56kHz, 64kHz or 1.2kHz at the output of PLL2. SEL24~SEL20: These bits control the frequency multiplier "K" for the PLL2, after selecting Kx56, Kx64 or DATA mode through register CR1 (1 < K < 32). PLL2 Output Frequency (kHz) SEL24~SEL20 K factor Kx56 MODE Kx64 MODE DATA MODE 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 56 112 168 224 280 336 392 448 504 560 616 672 728 784 840 896 952 1008 1064 1120 1176 1232 1288 1344 1400 1456 1512 1568 1624 1680 1736 1792 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 1088 1152 1216 1280 1344 1408 1472 1536 1600 1664 1728 1792 1856 1920 1984 2048 1.2 2.4 4.8 7.2 9.6 12 14.4 16.8 19.2 21.6 24 26.4 28.8 31.2 33.6 36 38.4 40.8 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 Note: This table applies to forward or slave forward mode only Table 5. CR4 Register Rev. 1.11 12 XRT8000 Table 6 presents information on the delay between the rising edge of SYNC and the CLK1 or CLKL output signals. It is important to note that this delay behaves as a function of the settings within the CR3 register. T values (nS) SEL14~SEL10 K Kx56 MODE Kx64 MODE 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 372 372 372 372 446 372 319 279 496 446 406 372 343 319 298 279 525 496 470 446 425 406 388 372 357 343 331 319 308 298 288 279 326 326 326 326 391 326 279 244 434 301 355 326 301 279 260 244 460 434 411 391 372 355 340 326 312 301 289 279 279 260 252 244 Notes: 1 This table does not apply to the data mode or to Kx56 mode with the divide by eight enabled. 2 This table does not apply when the XRT8000 device is operating in the REVERSE Mode. Table 6. Delay Time Between SYNC and CLK1 or CLK2 Rev. 1.11 13 XRT8000 CR5 Register (Power On State = "00000") D0 : ( PL1/8) : D3 : ( CLK1EN) , PLL1: Select the divider by 8 for PLL1, PL1/8 = "1" CLK1 output frequency is divided by 8. PL1/8 = "0" CLK1 output frequency is as per table 4. Output enable bit, CLK1EN = "1" CLK1 output is enabled. CLK1EN = "0" CLK1 output is Tri State D. D1 : ( PL2/8) : D4 : ( SYNCEN) , 8kHz SYNC enable bit: Select the divider by 8 for PLL2, PL2/8 = "1" CLK2 output frequency is divided by 8. PL2/8 = "0" CLK2 output frequency is as per table 5. SYNCEN = "1" SYNC output is enabled. SYNCEN = "0" SYNC output is Tri State D. D2 : ( CLK2EN) , PLL2: CR6 to CR7 Register Output enable bit, CLK2EN = "1" CLK2 output is enabled. CLK2EN = "0" CLK2 output is Tri State D. Register reserved for future use. CSB 1 SCLK 2 3 4 5 6 7 8 9 10 11 Address SDI R/W A0 A1 A2 A3 12 13 14 15 16 Data In A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 D5 D6 D7 Data Out HiZ SDO D0 D1 D2 D3 D4 Figure 4. Serial Processor Interface Data Structure Note: A3, A4 and A5 always Low. A6 Do not care. R/W bit = 1 for a read operation 2 for a write operation D5, D6 and D7 always Low CSB SCLK SDI SDO SERIAL INTERFACE The serial interface is a simple four wire interface that is compatible with many of the microcontrollers available in the market. This interface consists of the following signals: Rev. 1.11 14 Chip Select (Active Low) Serial Clock Input Serial Data Input Serial Data Output HiZ XRT8000 Using the Serial Interface Read Operation The following instructions, for using the serial interface, are best understood by referring to the diagram in Figure 4. Once the last address bit (A2) has been clocked into the SDI input, the read operation will proceed through an idle period, lasting four SCLK periods. On the falling edge of SCLK Cycle "8" (See Figure 4) the serial output signal (SDO) becomes active. At this point the user can begin reading the data contents of the addressed command register (at Address A2, A1, A0) via the SDO pin. The SDO pin will output this five bit data word (D0 through D4) in ascending order, with the LSB first, on the rising edges of the SCLK pin. In order to use the serial interface the user must first provide a clock signal to the SCLK input pin. Afterwards, the user will initiates a "Read" or "Write" operation by asserting the active low Chip Select Input pin (CSB). It is important to note that the user assert CSB low coincident with the falling edge of SCLK. Once the CSB input has been asserted the type of operation and the target register address must be provided by the user. The user will provide this information to the serial interface by writing four serial bits of data to the SDI input. Note: Each of these bits will be "clocked" into the SDI input, on the rising edge of SCLK. These four bits are identified and described below. Write Operation Once the last address bit (A2) has been clocked into the SDI input, the write operation will proceed through an idle period, lasting four SCLK periods. Prior to the rising edge of SCLK Cycle #9 (See Figure 4) the user must begin to apply the eight-bit data word, that he/she wishes to write to the serial input interface onto the SDI input pin. The microprocessor serial interface will catch the value on the SDI pin on the rising edge of the SCLK. The user must apply this word (D0 through D7), serially, in ascending order with the LSB first. Bit 1: The R/W (Read/Write) Bit This bit will be clocked into the SDI input, on the first rising edge of SCLK (after CSB has been asserted). This bit indicates whether the current operation is a read or a write operation. A "1" in this bit will cause a "Read" operation; whereas a "0" in this bit will cause a "Write" operation. Simplified Interface Option The user can simplify the design of the circuitry connecting to the serial interface by tying both the SDO and SDI pins together, and reading data from and/or writing data to this "combined" signal. This simplification is possible because only one of these signals are active at any given time. The inactive signal will be tri-stated. Notes: Bits 2 through 4: The three (3) bit address value (A0, A1, A2) These next three rising edges of the SCLK signal will clock in the 3-bit address value for this particular read (or write) operation. This address selects the command register within XRT8000 device that the user will either be reading data from, or writing data to. The user must supply the address bits to the SDI input pin, in ascending order with the LSB first. (A3 to A5 must be low A6 is a "don't care"). 1. Prior to reading data from (or writing data to) the Serial Interface, the user is not required to provide a clock signal at the SCLK. However, shortly before performing any read or write operations with the Serial Interface, the user must supply the clock signal to the SCLK input pin. 2. Each Read or Write operation, with the Serial Interface, will require 16 SCLK periods, as depicted in Figure 4. 3. Upon completion of a Read or Write cycle, the user must negate CSB for at least 250ns (see timing parameter T29 in the AC Characteristics), before asserting it again for the next Read or Write operation. Once the "Read/Write" and Address bits have been written, the subsequent action depends upon whether the current operation is a "Read" or "Write" operation. Rev. 1.11 15 XRT8000 T29 CSB SCLK T22 T25 T21 T23 SDI T27 T28 T26 T24 W/R A0 CSB SCLK T30 SDO SDI Hz SDI[D7] T31 SDOD0 T32 T33 SDOD1 SDOD7 Hz Figure 5. Serial Interface Timing Rev. 1.11 16 Hz XRT8000 CONFIGURATION DIAGRAMS The following six figures depict all of the configuration possibilities for the XRT8000. The table in the left (FIN) lists different possibilities for reference clock input, while the table in the right lists all the possibilities for two output clocks. k n x T1 or n x E1 (1<=n<=16) n Reference Freq. (kHz) n x T1 n x E1 1 2 1,544 3,088 2,048 4,096 3 4,632 6,144 4 6,176 8,192 5 7,720 10,240 6 9,264 12,288 7 10,808 14,336 8 12,352 16,384 9 13,896 18,432 10 15,440 20,480 11 16,984 22,528 12 18,528 24,576 13 20,072 26,624 14 21,616 28,672 15 23,160 30,720 16 24,704 32,768 XRT8000 FIN CLK1 k x DS0 (1<=k<=32) CLK2 SYNC 8 kHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 6. Master Forward Mode Rev. 1.11 17 Output Frequencies (kHz) (k x 56) (k x 56)/8 56 112 168 224 280 336 392 448 504 560 616 672 728 784 840 896 952 1,008 1,064 1,120 1,176 1,232 1,288 1,344 1,400 1,456 1,512 1,568 1,624 1,680 1,736 1,792 7 14 21 28 35 42 49 56 63 70 77 84 91 98 105 112 119 126 133 140 147 154 161 168 175 182 189 196 203 210 217 224 (k x 64) (k x 64)/8 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1,024 1,088 1,152 1,216 1,280 1,344 1,408 1,472 1,536 1,600 1,664 1,728 1,792 1,856 1,920 1,984 2,048 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256 XRT8000 Output Frequencies (Hz) XRT8000 n x T1 n x E1 (1<=n<=16) k FIN (k x 2400) (k x 2400)/8 0.5 1,200 150 1 2,400 300 2 4,800 600 3 7,200 900 4 9,600 1,200 5 12,000 1,500 6 14,400 1,800 7 16,800 2,100 8 19,200 2,400 9 21,600 2,700 10 24,000 3,000 11 26,400 3,300 12 28,800 3,600 13 31,200 3,900 14 33,600 4,200 Reference Freq.n (kHz) x T1 n x T1 or n x E1 1 1,544 2,048 2 3,088 4,096 3 4,632 6,144 4 6,176 8,192 5 7,720 10,240 6 9,264 12,288 7 10,808 14,336 8 12,352 16,384 9 13,896 18,432 10 15,440 20,480 15 36,000 4,500 11 16,984 22,528 16 38,400 4,800 12 18,528 24,576 17 40,800 5,100 13 20,072 26,624 18 43,200 5,400 14 21,616 28,672 15 23,160 30,720 16 24,704 32,768 n CLK1 k x 2.4 kHz (1<=k<=18) CLK2 SYNC 8 kHz Figure 7. Master Forward Mode (Cont'd) Rev. 1.11 18 XRT8000 64 kHz or 56 kHz XRT8000 FIN Output CLK1 T1, T1/8 or E1, E1/8 CLK2 SYNC Freq. kHz kHz 1544 193 2048 256 8 kHz Figure 8. Master Reverse Mode k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 XRT8000 8 kHz FIN CLK1 k x DS0 (1<=k<=32) CLK2 SYNC 8 kHz (k x 56)/8 56 112 168 224 280 336 392 448 504 560 616 672 728 784 840 896 952 1,008 1,064 1,120 1,176 1,232 1,288 1,344 1,400 1,456 1,512 1,568 1,624 1,680 1,736 1,792 Figure 9. Slave Forward Mode Rev. 1.11 19 Output Frequencies (kHz) (k x 56)/8 (k x 64) (k x 64)/8 7 64 8 14 128 16 21 192 24 28 256 32 35 320 40 42 384 48 49 448 56 56 512 64 63 576 72 70 640 80 77 704 88 84 768 96 91 832 104 98 896 112 105 960 120 112 1,024 128 119 1,088 136 126 1,152 144 133 1,216 152 140 1,280 160 147 1,344 168 154 1,408 176 161 1,472 184 168 1,536 192 175 1,600 200 182 1,664 208 189 1,728 216 196 1,792 224 203 1,856 232 210 1,920 240 217 1,984 248 224 2,048 256 XRT8000 k Output Frequencies (Hz) (k x 2400) 1,200 150 2,400 300 2 4,800 600 0.50 1 8 kHz (k x 2400)/8 3 7,200 900 XRT8000 4 9,600 1,200 FIN 5 12,000 1,500 6 14,400 1,800 7 16,800 2,100 8 19,200 2,400 9 21,600 2,700 10 24,000 3,000 11 26,400 3,300 12 28,800 3,600 13 31,200 3,900 14 33,600 4,200 15 36,000 4,500 16 38,400 4,800 17 40,800 5,100 18 43,200 5,400 CLK1 k x 2.4 kHz (1<=k<=18) CLK2 SYNC 8 kHz Figure 10. Slave Forward Mode (Cont'd) Rev. 1.11 20 XRT8000 XRT8000 8 kHz FIN Output CLK1 T1, T1/8 or E1, E1/8 CLK2 SYNC Freq. kHz kHz 1544 193 2048 256 8 kHz Figure 11. Slave Reverse Mode (Cont'd) Board Layout Considerations The CLK1 and CLK 2 outputs are surrounded with supply pins (GND(514),Vcc(712). It is recommended to decouple these supplies with a 0.1uF very close to the pins. The positive supply (7,12,15) and ground pins (4,5,14) can all be connected to the Digital Supply and Ground. Supply if possible. If there is no Analog Supply, then connect these pins as close as possible to the supply source. If the layout is done with separate layers for the supplies, cut an island under the XTT8000 such that no current flows under the circuit. It has been observed that coupling can occur because heavy digital currents are flowing under the locations of the XRT8000. The internal VCO has its proper supply's pins (GND 9, Vcc 10) these supply pins have to be decoupled by a 0.1uF capacitor and should be connected to an Analog Rev. 1.11 21 XRT8000 18 LEAD PLASTIC DUALINLINE (300 MIL PDIP) Rev. 1.00 18 10 1 9 E1 E D Seating Plane A2 A L a A1 B e INCHES SYMBOL eA eB B1 MILLIMETERS MIN MAX MIN MAX A 0.145 0.210 3.68 5.33 A1 0.015 0.070 0.38 1.78 A2 0.115 0.195 2.92 4.95 B 0.014 0.024 0.36 0.56 B1 0.030 0.070 0.76 1.78 C 0.008 0.014 0.20 0.38 D 0.845 0.925 21.46 23.50 E 0.300 0.325 7.62 8.26 E1 0.240 0.280 6.10 7.11 e 0.100 BSC 2.54 BSC eA 0.300 BSC 7.62 BSC eB 0.310 0.430 7.87 10.92 L 0.115 0.160 2.92 4.06 a 0 15 0 15 Note: The control dimension is the inch column Rev. 1.11 22 C XRT8000 18 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) Rev. 1.00 D 18 10 H E 1 9 C A Seating Plane e B a A1 L INCHES SYMBOL A MILLIMETERS MIN MAX MIN 0.093 0.104 2.35 MAX 2.65 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.447 0.463 11.35 11.75 E 0.291 0.299 7.40 7.60 e 0.050 BSC 1.27 BSC H 0.394 0.419 10.00 10.65 L 0.016 0.050 0.40 1.27 a 0 8 0 8 Note: The control dimension is the millimeter column Rev. 1.11 23 XRT8000 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1999--2006 EXAR Corporation Datasheet September 2006 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.11 24 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Exar: XRT8000ID-F XRT8000IDTR-F XRT8000ES