September2006
XRT8000
Clock Synchronizer/Adapterfor
Communications
Rev.1.11
E1999--2006EXAR Corporation,48720 KatoRoad,Fremont, CA94538 z(510)668-7000 zFAX (510)668-7017 zwww.exar.com
FEATURES
DClock Adaptation forMostPopular
Telecommunication Frequencies
DWide InputFrequency Range
DProgrammableOutputFrequencies
DLess than 0.05UIWide Band OutputJitter
DLowPowerOperation (5Vand 3.3V)
DMaximumLock Time of45mS
DCascadable
DNoExternalComponentsNeeded
DLock Detect Indication Pin
APPLICATIONS
DDSU’s,CSU’sand Access Equipment
DISDN Terminals
DConcentratorsand Multiplexers
GENERALDESCRIPTION
The XRT8000 isa dualphase-locked loop chipthat
generatestwosimultaneous,verylowjitter,outputclocks
forsynchronization applicationsinwide area networking
systems.The outputsare phaselocked tothe input
signal.The chip hasfourbasicmodesofoperation;
referred to asmaster (FORWARD,REVERSE)and slave
(FORWARD,REVERSE)modes(See Figure 1). Inthe
FORWARD mode itacceptsup to 16th harmonicofeither
1.544MHzor2.048MHzasinputreference and generates
1.2kHzand multiplesof2.4kHz,56kHzor64kHz. Inthe
REVERSEmode an inputclock of56kHzor64kHzisused
to generate 1.544MHzor2.048MHzoutputclocks.The
SLAVE (FORWARD,REVERSE)modesgeneratethe
same output frequenciesasthe MASTER(FORWARD/
REVERSE MODES)except that the input frequency (FIN)
is8kHz.An optionaldivide byeightcan be enabled at
each of the outputs.
The inputand output frequency selection can be done
through a serialmicroprocessorinterface.The XRT8000
isavailablein either18 pinSOICpackage or18 pin plastic
DIP.
ORDERINGINFORMATION
PartNo.Package
Operating Temperature
Range
XRT8000IP18 Lead 300 Mil PDIP-40°Cto+85°C
XRT8000ID18 Lead 300 Mil JEDECSOIC-40°Cto+85°C
nx1.544{T1}
nx2.048{E1}
1<= n<= 16
Kx56kHz
Kx64kHz
1.2kHz
2.4xK
to
43.2kHz
1<= K<= 32
MASTERFORWARD
T1(1.544)
E1(2.048)
56kHz
64kHz
MASTER REVERSE
8kHz
B
A/B
A
Figure 1.SystemDiagram
1<= K<= 18
XRT8000 XRT8000 XRT8000
FINFINFIN
CLK2CLK2CLK2
CLK1CLK1CLK1
SYNC 8kHzSLAVE
FORWARD/REVERSE
or
SYNC SYNC
XRT8000
2
Rev.1.11
BLOCK DIAGRAM
Analog
PhaseLocked
Loop
Post
Divider
Div.
By
8Driver
Feedback
Divider
Lock
Detector
M2
MQ2
Q
CLK2
DIV/8_EN
PLL 2
FIN
VCC
R
100K
R
100K
SCLK
CSB
SDI
SDO
MSB
Serial
InterfaceMode and Frequency SelectControl
Input
DividerAnalog
PhaseLocked
Loop
Feedback
Divider
Post
Divider
Div.
By
8Driver
M
Q
M2Q2
LOCKDET
SYNC
P
PLL 1
CLK1
Figure 2.Block Diagram
DIV/8_EN
XRT8000
3
Rev.1.11
PIN CONFIGURATION
SCLK
CSB
SDI
VCC
GND
CLK2
VCC
LOCKDET
SDO
SYNC
FIN
GND
GND
CLK1
VCC
MSB
VCC
GND
18 LeadPDIP(0.300”)
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
18 LeadSOIC(Jedec,0.300”)
SCLK
CSB
SDI
VCC
GND
CLK2
VCC
LOCKDET
SDO
SYNC
FIN
GND
GND
CLK1
VCC
MSB
VCC
GND
181
109
2
3
4
5
6
7
15
14
13
12
11
17
16
8
PIN DESCRIPTION
SymbolPin#TypeDescription
SDO1OSerialDataOutput (MicroprocessorSerial Interface).Data output fromthe command reg-
isters.
SYNC 2OAn8kHzSignalSubDivided FromFIN.Thisoutputcan be threestated viaCR5.SYNC can
be used tosynchronize otherXRT8000 which areconfigured inslavemodes.
FIN3IReference Frequency Input.
GND 4DigitalGround.
GND 5DigitalGround.
CLK1 6 OClock 1.Outputof the phase-locked loop 1.
VCC 7DigitalPositive PowerSupply.
MSB 8IMaster/Slave ModeSelectInput.If thisinputishigh, then the MASTERmode is selected. If
thisinputislow, then the SLAVE mode isenabled.Thispinisinternallypulled up via 100KW
resistor.
GND 9Analog Ground.
VCC 10 Analog Positive Supply.
LOCKDET11 OLock Detect.Thisoutputishigh when both phase-locked loopsareinlock and will go lowif
eitherone of the phaselocked loopsloseslock.
VCC 12 DigitalPositive PowerSupply.
CLK2 13 OClock 2.Outputof the phase-locked loop 2.
GND 14 DigitalGround.
VCC 15 DigitalPositive PowerSupply.
SDI16 ISerialDataInput (MicroprocessorSerial Interface)Datainput tothe command registers.
CSB 17 IChipSelectNot (MicroprocessorSerial Interface).When thisinputislowthe datain and
outwill be shifted inthe appropriateregisters. Internalpull up (100K).
SCLK18 ISerialClock Input (MicroprocessorSerial Interface).This clock will serve asareference
tothe datastreamstoSDIand SDO(the positive edge ofSCLKisused tolatchthe data).
XRT8000
4
Rev.1.11
DC ELECTRICALCHARACTERISTICS(ExceptSerial Interface)Operating Temperature: -40_Cto85_C
TestConditions:TA=25_C,VCC =5.0V±5%Unless Otherwise Specified
SymbolParameterMin TypMax UnitConditions
VILInputlowlevel0.8V
VIHInputhigh level2.0V
VOLOutputlowlevel(CLK1,CLK2)0.4VIOL=-6.0mA
VOHOutputhigh level(CLK1,CLK2)2.4VIOH=6.0mA
VOLOutputlowlevel(LOCKDET,SYNC)0.4VIOL=-3.0mA
VOHOutputhigh level(LOCKDET,SYNC)2.4VIOH=3.0mA
IILInputlowcurrent(CSB,MSB) -150 mA
IIHInputhigh current(CSB,MSB)10 mA VIN=VCC
IILInputlowcurrent(exceptCSB,MSB) -10 mA
IIHInputhigh current(exceptCSB,MSB)10 mA VIN=VCC
ICC Operating current20 35 mANoload.Clock =2.1MHz
RINInputpull-up resistance(CSB,MSB)50 100 150 KW
AC ELECTRICALCHARACTERISTICS(See Figure 3)
SymbolParameterSpec.3Min TypMax UnitConditions
T1Input frequency 0.008 32.7MHz
T2Minimuminputsignalhigh to
lowduration 12 ns
T3Output frequency 1.2 2.1KHz
T61Duty cycleCLK1,CLK2 47.5 50 52.5%VCC/2switch point. 30pF
load.
T74Jitteradded 8KHz-40KHz0.025 0.007 0.02 UIOutput=1.544MHz
T74Jitteradded 10Hz-40KHz0.025 0.022 UIOutput=1.544MHz
T74Broad Band-jitter0.05 0.03 0.05 UIOutput=1.544MHz
T74Jitteradded 20Hz-100KHz1.5 0.05 0.07 UIOutput=2.048MHz
T74Jitteradded 18kHz-100KHz0.2 0.01 0.03 UIOutput=2.048MHz
T8Capturetime 40 ms
T9Clock outputrisetime 10 ns30pFload.Measured at
20/80 %
T10 Clock output fall time 10 ns30pFload.Measured at
20/80 %
T112Duty cycleSYNC 40 60 %VCC/2switch point
(inmasterforwardmode).
30pFload.
T14 Delaytime between the rising
edge ofSYNC and the rising
edge ofCLK1 orCLK2
T-20 T T+20 nsSee table 12 forvaluesofT
Notes:
1T6=
(
)
T
T
T
4
4
5
+
2T11 =()
T
T T
12
12 13
+
3SpecificationsfromAT&TPublication 62411 and ITU-TRecommendationsG-823 (for1.544MHzand 2.048MHz,respectively).
4T7isguaranteed by characterization,not tested.
Specificationsaresubject tochange withoutnotice.
XRT8000
5
Rev.1.11
DC ELECTRICALCHARACTERISTICS(ExceptSerial Interface)Operating Temperature: -40_Cto85_C
TestConditions:TA=25_C,VCC =3.3V±5%Unless Otherwise Specified
SymbolParameterMin TypMax UnitConditions
VILInputlowlevel0.8V
VIHInputhigh level2.0V
VOLOutputlowlevel(CLK1,CLK2)0.4VIOL=-3mA
VOHOutputhigh level(CLK1,CLK2)2.4VIOH=3mA
VOLOutputlowlevel(LOCKDET,SYNC)0.4VIOL=-2.5mA
VOHOutputhigh level(LOCKDET,SYNC)2.4VIOH=2.5mA
IILInputlowcurrent(CSB,MSB) -150 mA
IIHInputhigh current(CSB,MSB)10 mA VIN=VCC
IILInputlowcurrent(exceptCSB,MSB) -10 mA
IIHInputhigh current(exceptCSB,MSB)10 mA VIN=VCC
ICC Operating current11 30 mANoload.Clock =2.1MHz
RINInputpull-up resistance(CSB,MSB)50 100 150 KW
AC ELECTRICALCHARACTERISTICS(See Figure 3)
SymbolParameterSpec.3Min TypMax UnitConditions
T1Input frequency 0.008 32.7MHz
T2Minimuminputsignalhigh to
lowduration 12 ns
T3Output frequency 1.2 2.1KHz
T61Duty cycleCLK1,CLK2 47.5 50 52.5%VCC/2switch point. 30pF
load.
T74Jitteradded 8KHz-40KHz0.025 0.01 0.02 UIOutput=1.544MHz
T74Jitteradded 10Hz-40KHz0.025 0.030 UIOutput=1.544MHz
T74Broad Band 0.05 0.035 0.05 UIOutput=1.544MHz
T74Jitteradded 20Hz-100KHz1.5 0.045 0.07 UIOutput=2.048MHz
T74Jitteradded 18kHz-100KHz0.2 0.010 0.03 UIOutput=2.048MHz
T8Capturetime 40 ms
T9Clock outputrisetime 14 ns30pFload.Measured at
20/80 %
T10 Clock output fall time 14 ns30pFload.Measured at
20/80 %
T112Duty cycleSYNC 40 60 %VCC/2switch point
(inmasterforwardmode).
30pFload.
T14 Delaytime between SYNC
and CLK1 orCLK2T-20 T T+20 nsSee table 12 forvaluesofT
Notes:
1T6=()
T
T T
4
45
+2T11 =()
T
T T
12
12 13+
3SpecificationsfromAT&TPublication 62411 and ITUTRcommendationsG-823 (for1.544MHzand 2.048MHz,respectively)
4T7isguaranteed by characterization,not tested.
Specificationsaresubject tochange withoutnotice.
XRT8000
6
Rev.1.11
AC ELECTRICALCHARACTERISTICS(See Figure 5).
SymbolParameterMin.Typ.Max.UnitConditions
AC ElectricalCharacteristics (See Figure 5)
T21 CSB toSCLK Setup Time 50 ns
T22 SCLKtoCSB HoldTime 20 ns
T23 SDI toSCLK Setup Time 50 ns
T24 SCLKtoSDIHoldTime 50 ns
T25 SCLKLowTime 240 ns
T26 SCLKHigh Time 240 ns
T27 SCLK Period 500 ns
T28 SCLKtoCSB HoldTime 50 ns
T29 CSB InactiveTime 250 ns
T30 SCLKtoSDOValid 200 ns
T31 SCLKtoSDOxDelay100 ns
T32 SCLK Edge orCSB Edge to
SDOHZ
100 ns
T33 Rise/Fall TimeSDO Output40 ns
Specifications are subject tochangewithoutnotice
ABSOLUTEMAXIMUMRATINGS
SupplyRange 7V...............................
Voltage atAnyPinGND0.3VtoVcc +0.3V.........
Operating Temperature 40°Cto+85°C............
Storage Temperature 40°Cto+150°C.............
Package Dissipation 500mW....................
FIN
CLK1 orCLK2
SYNC
T1
T3
T4T5
T9T10 T12 T7T13
Figure 3.Clocks Timing
T2T2
T14
XRT8000
7
Rev.1.11
SYSTEMDESCRIPTION
On powerup the clock outputsofXRT8000 will be
tri-stated.Thismeansthatno clocks will be seen at the
outputsand lock detectoutputwill be low.Afterpowerup
the XRT8000 needstobeinitialized.Thereforeaserial
interfaceisprovided toload the internalregisters.These
registerswill define the modesofoperation, the output
frequenciesand enabling the clock outputs.
Master/ForwardModeofOperation
When the XRT8000 deviceisoperating inthe
“Master/Forward”Mode,itwill receive eitheran
“nx2.048 MHz”or “nx1.544 MHz”clock signalat the
FINinput(pin3);where“n”can range from1to 16.From
thisinputsignal, the XRT8000 devicewill internallydivide
and synthesizethe following signals.
At theCLK1 and/orCLK2outputpins:
Dkx56 kHz
Dkx64 kHz
D(kx56 kHz)/8
D(kx64 kHz)/8
wherek can range from1to 32.
At theSYNC Outputpin:
D8kHz
The userselectsand configuresthe XRT8000 deviceto
generatetheseclock frequenciesbywriting the
appropriatevaluesintothe Command Registers(CR1,
CR2,CR3,CR4 and CR5),viathe MicroprocessorSerial
Interface.
Reverse ModeofOperation
When the XRT8000 deviceisoperating inthe “Reverse”
Mode,itwill receive eithera 56 kHzor64 kHz clock signal
at the FINinput. Fromthisinputsignal, the XRT8000
devicewill synthesize anyof the following clock signal
frequencies.
At the CLK1 and/orCLK2 outputpins:
D1.544 MHz
D2.048 MHz
D1.544 MHz/8=193 kHz
D2.048 MHz/8=256 kHz
At theSYNC outputpin:
D8kHz
The usercan configurethe XRT8000 deviceto generate
theseclock frequenciesbywriting the appropriatevalues
intothe Command Registers(CR1,CR2,CR3,CR4 and
CR5),viathe MicroprocessorSerialInterface.
Note:inthe REVERSE mode the contentsofCR3 and
CR4 hasto be all one’s.
Slave (Forward,Reverse)ModeofOperation
To activatethe slavemodesofoperationsthe inputMSB
mustbe tied low. Inthesemodesan 8kHz signalmustbe
applied tothe FINinputin orderto obtain output
frequenciesatT1orE1rates.The output frequencies can
be selected viathe serial interfacein a similarfashion as
described inthe masterforward and reversemodes.
TheLock DetectOutputPin
If bothPLL’sare enabled and inlocked statethen
LOCKDETwill be active. If one PLL loseslock then
LOCKDETwill be false. If onlyone PLL isenabled then
onlythe activePLL will controlthe state ofLOCKDET.
XRT8000
8
Rev.1.11
TheCommand Registers
Between the MSB inputpin and the Command Registers,
the usercan configurethe XRT8000 deviceinto anyof the
operating modesthathave been described inthisdata
sheet. The usercan access theseCommand Registers
viathe MicroprocessorSerialInterface.
Table 1 presentsthe Address Location and Format for
each of the Command Registers,withinthe XRT8000
device.
AD2~0RegisterD4D3D2D1D0
000 CR1IOC4IOC3IOC2IOC1PL1EN
001 CR2M4M3M2M1PL2EN
010 CR3SEL14 SEL13 SEL12 SEL11 SEL10
011 CR4SEL24 SEL23 SEL22 SEL21 SEL10
100 CR5SYNCEN CLK1EN CLK2ENPL2/8PL1/8
101 CR6Reserved Reserved Reserved Reserved Reserved
110 CR7Reserved Reserved Reserved Reserved Reserved
111 CR8Reserved Reserved Reserved Reserved Reserved
Table 1.ControlRegisters
The next fewpagesdescribe the role/functionalityofeach bit-fieldwithinthe Command Registers.
XRT8000
9
Rev.1.11
CR1Register(PowerOnState=“00000”)
D0(PL1EN):
EnablecontrolforPLL1. If PL1EN=“1”, then PLL1 is
enabled.Otherwise,ifPL1EN=“0”, then PLL1 is
disabled.
D1~D4(IOC1~IOC4):
Thesefourbit-fieldsfunction asthe controlbitsforPLL1
and PLL2 operation modes.These bits select
FORWARD,REVERSE,DATA,Kx56 orKx64 clock rates.
Multiplier “K”inKx56 and Kx64 refersto harmonics of
56kHzor64kHz clocks, thisnotation isextended to
1,544kHzand 2,048kHzfrequenciesinthe following
table(Table 2).
Note:The value of“K”forPLL1 and PLL2 areindependentof
each other.
Table 2
Table 2 createsthe valuesofD1through D4withinthe
CRIcommand registertothe operating mode of the
XRT8000 device.
IOC4IOC3IOC2IOC1InputFreq.
[kHz]PLL1Output
[kHz]PLL2Output
[kHz]Mode
0 0 0 0 nx1544 Kx56 Kx56 Forward
0 0 0 1 nx1544 Kx56 Kx64 Forward
0 0 1 0 nx1544 Kx64 Kx64 Forward
0 0 1 1 nx1544 Kx56 DATAForward
0 1 0 0 nx1544 Kx64 DATAForward
0 1 0 1 nx1544 DATADATAForward
0 1 1 0 56 1544 1544 Reverse
0 1 1 1 8K1544 2048 Reverse
1 0 0 0 nx2048 Kx56 Kx56 Forward
1 0 0 1 nx2048 Kx56 Kx64 Forward
1 0 1 0 nx2048 Kx64 Kx64 Forward
1 0 1 1 nx2048 Kx56 DATAForward
1 1 0 0 nx2048 Kx64 DATAForward
1 1 0 1 nx2048 DATADATAForward
1 1 1 0 8 1544 2048 Reverse
1 1 1 1 64 2048 2048 Reverse
Table 2.Operation Mode/OutputClock Frequency SelectOptions
ViatheD1Through D4BitswithintheCRIRegister
Note:
1The valuesof“n”areselected viathe M1through M4 bits,withinthe CR2Register (see Table 3).
2The valuesof“k”areselected viathe Sel14 through SelPbitswithinthe CR3Register (see Table 4).
XRT8000
10
Rev.1.11
CR2Register(PowerOnState=“00000”)
D0(PL2EN):
EnablecontrolforPLL2. If PL2EN=“1”, then PLL2 is
enabled.Otherwise,ifPL2EN=“0”,PLL2 isdisabled.
D1~D4(M1~M4):
Controlbitsforprescalerdivider.These bitswill set the
divide ratio of the prescalersuchthatinMASTER/
FORWARD orREVERSE modesthe outputof thisblock
isalways at8kHz.The settingsforM4~M1 bitsisbased
on the input frequency and the mode ofoperation (which
isdetermined bythe state of IOC4~IOC1 bits)isprovided
inTable 3.
M4M3M2M1ModeInputFreq.[kHz]
0 0 0 0 Forward 1x(1544 or2048)
0 0 0 1 Forward 2x(1544 or2048)
0 0 1 0 Forward 3x(1544 or2048)
0 0 1 1 Forward 4x(1544 or2048)
0 1 0 0 Forward 5x(1544 or2048)
0 1 0 1 Forward 6x(1544 or2048)
0 1 1 0 Forward 7x(1544 or2048)
0 1 1 1 Forward 8x(1544 or2048)
1 0 0 0 Forward 9x(1544 or2048)
1 0 0 1 Forward 10x(1544 or2048)
1 0 1 0 Forward 11x(1544 or2048)
1 0 1 1 Forward 12x(1544 or2048)
1 1 0 0 Forward 13x(1544 or2048)
1 1 0 1 Forward 14x(1544 or2048)
1 1 1 0 Forward 15x(1544 or2048)
1 1 1 1 Forward 16x(1544 or2048)
xxxx Reverse 56
xxxx Reverse 64
Note:
Thistable appliestoMASTER(FORWARD,REVERSE)mode only
Table 3.CR2Register
XRT8000
11
Rev.1.11
CR3Register(PowerOnState=“00000”)
SEL14~SEL10:
These bits controltwo parameters:
1.)The frequency multiplier “K”forthe PLL1,after
selecting Kx56,Kx64 orDATAmode through registerCR1
(1<K<32),and
2.)The delaytime between the rising edge of the sync
outputsignal(Pin 2)and the rising edge of the CLK1 or
CLI2 outputsignals(See Table 6).
Table 4 providesthe settingsforSEL14~10 bitsto
generate harmonicof56kHz,64kHzor1.2kHzat the
outputofPLL1.
PLL1OutputFrequency (kHz)
SEL14~SEL10 KfactorKx56 MODEKx64 MODEDATAMODE
00000 1 56 64 1.2
00001 2 112 128 2.4
00010 3 168 192 4.8
00011 4 224 256 7.2
00100 5 280 320 9.6
00101 6 336 384 12
00110 7 392 448 14.4
00111 8 448 512 16.8
01000 9 504 576 19.2
01001 10 560 640 21.6
01010 11 616 704 24
01011 12 672 768 26.4
01100 13 728 832 28.8
01101 14 784 896 31.2
01110 15 840 960 33.6
01111 16 896 1024 36
10000 17 952 1088 38.4
10001 18 1008 1152 40.8
10010 19 1064 1216 43.2
10011 20 1120 1280 43.2
10100 21 1176 1344 43.2
10101 22 1232 1408 43.2
10110 23 1288 1472 43.2
10111 24 1344 1536 43.2
11000 25 1400 1600 43.2
11001 26 1456 1664 43.2
11010 27 1512 1728 43.2
11011 28 1568 1792 43.2
11100 29 1624 1856 43.2
11101 30 1680 1920 43.2
11110 31 1736 1984 43.2
11111 32 1792 2048 43.2
Note:
Thistable appliestoforward orslavemodesonly
Table 4.CR3Register
XRT8000
12
Rev.1.11
CR4Register(PowerOnState=“00000”)
SEL24~SEL20:
These bits controlthe frequency multiplier “K”forthe
PLL2,afterselecting Kx56,Kx64 orDATAmode through
registerCR1(1<K<32).
Table 5 providesthe settingsforSEL24~20 bitsto
generate harmonicof56kHz,64kHzor1.2kHzat the
outputofPLL2.
PLL2OutputFrequency (kHz)
SEL24~SEL20 KfactorKx56 MODEKx64 MODEDATAMODE
00000 1 56 64 1.2
00001 2 112 128 2.4
00010 3 168 192 4.8
00011 4 224 256 7.2
00100 5 280 320 9.6
00101 6 336 384 12
00110 7 392 448 14.4
00111 8 448 512 16.8
01000 9 504 576 19.2
01001 10 560 640 21.6
01010 11 616 704 24
01011 12 672 768 26.4
01100 13 728 832 28.8
01101 14 784 896 31.2
01110 15 840 960 33.6
01111 16 896 1024 36
10000 17 952 1088 38.4
10001 18 1008 1152 40.8
10010 19 1064 1216 43.2
10011 20 1120 1280 43.2
10100 21 1176 1344 43.2
10101 22 1232 1408 43.2
10110 23 1288 1472 43.2
10111 24 1344 1536 43.2
11000 25 1400 1600 43.2
11001 26 1456 1664 43.2
11010 27 1512 1728 43.2
11011 28 1568 1792 43.2
11100 29 1624 1856 43.2
11101 30 1680 1920 43.2
11110 31 1736 1984 43.2
11111 32 1792 2048 43.2
Note:
Thistable appliestoforward orslaveforwardmode only
Table 5.CR4Register
XRT8000
13
Rev.1.11
Table 6 presentsinformation on the delaybetween the rising edge ofSYNC and the CLK1 orCLKL outputsignals. It is
important to notethat thisdelaybehavesasafunction of the settingswithinthe CR3register.
Tvalues (nS)
SEL14~SEL10 K Kx56 MODEKx64 MODE
00000 1 372 326
00001 2 372 326
00010 3 372 326
00011 4 372 326
00100 5 446 391
00101 6 372 326
00110 7 319 279
00111 8 279 244
01000 9 496 434
01001 10 446 301
01010 11 406 355
01011 12 372 326
01100 13 343 301
01101 14 319 279
01110 15 298 260
01111 16 279 244
10000 17 525 460
10001 18 496 434
10010 19 470 411
10011 20 446 391
10100 21 425 372
10101 22 406 355
10110 23 388 340
10111 24 372 326
11000 25 357 312
11001 26 343 301
11010 27 331 289
11011 28 319 279
11100 29 308 279
11101 30 298 260
11110 31 288 252
11111 32 279 244
Notes:
1Thistable doesnotapplytothe datamode ortoKx56 mode
withthe divide byeightenabled.
2Thistable doesnotapplywhen the XRT8000 deviceis
operating inthe REVERSE Mode.
Table 6.Delay TimeBetweenSYNC and CLK1orCLK2
XRT8000
14
Rev.1.11
CR5Register(PowerOnState=“00000”)
D0:(PL1/8):
Select the dividerby8forPLL1,
PL1/8=“1”CLK1 output frequency isdivided by8.
PL1/8=“0”CLK1 output frequency isaspertable 4.
D1:(PL2/8):
Select the dividerby8forPLL2,
PL2/8=“1”CLK2 output frequency isdivided by8.
PL2/8=“0”CLK2 output frequency isaspertable 5.
D2:(CLK2EN),PLL2:
Outputenable bit,
CLK2EN=“1”CLK2 outputisenabled.
CLK2EN=“0”CLK2 outputisTriStateD.
D3:(CLK1EN),PLL1:
Outputenable bit,
CLK1EN=“1”CLK1 outputisenabled.
CLK1EN=“0”CLK1 outputisTriStateD.
D4:(SYNCEN),8kHzSYNC enable bit:
SYNCEN=“1”SYNC outputisenabled.
SYNCEN=“0”SYNC outputisTriStateD.
CR6toCR7Register
Register reserved forfuture use.
Address DataIn
DataOut
R/WA0A1A2A3A4A5A6D0D1D2D3D4D5D6D7
D0D1D2D3D4D5D6D7
HiZHiZ
SDO
SDI
SCLK
CSB
Figure 4.SerialProcessorInterface DataStructure
Note:
A3,A4 and A5 always Low.
A6Do notcare.
R/Wbit=1foraread operation
2forawrite operation
D5,D6 and D7 always Low
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SERIALINTERFACE
The serial interfaceisasimplefourwireinterfacethatis
compatiblewithmanyof the microcontrollersavailablein
the market. Thisinterfaceconsistsof the following
signals:
CSB ChipSelect(Active Low)
SCLK SerialClock Input
SDISerialDataInput
SDOSerialDataOutput
XRT8000
15
Rev.1.11
Using theSerial Interface
The following instructions, forusing the serial interface,
are bestunderstood byreferring tothe diagramin
Figure 4.
In orderto usethe serial interfacethe usermust first
provideaclock signaltothe SCLKinputpin.Afterwards,
the userwill initiatesa“Read”or “Write”operation by
asserting the activelow ChipSelect Inputpin(CSB). It is
important to notethat the userassertCSB lowcoincident
withthe falling edge ofSCLK.
Oncethe CSB inputhasbeen asserted the type of
operation and the targetregisteraddress mustbe
provided bythe user.The userwill provide this
information tothe serial interface bywriting fourserialbits
ofdatatothe SDIinput. Note:Each of these bitswill be
“clocked”intothe SDIinput, on the rising edge ofSCLK.
Thesefourbitsareidentified and described below.
Bit1:The R/W(Read/Write)Bit
Thisbitwill be clocked intothe SDIinput, on the firstrising
edge ofSCLK(afterCSB hasbeen asserted).Thisbit
indicateswhetherthe currentoperation isaread orawrite
operation.A“1”inthisbitwill cause a “Read”operation;
whereasa“0”inthisbitwill causea“Write”operation.
Bits2through 4:The three (3)bitaddress value (A0,
A1,A2)
These next three rising edgesof the SCLKsignalwill
clock inthe 3-bitaddress value forthisparticular read (or
write)operation.Thisaddress selectsthe command
registerwithinXRT8000 devicethat the userwill eitherbe
reading datafrom,orwriting datato.The usermust
supplythe address bitstothe SDIinputpin,in ascending
orderwiththe LSB first. (A3toA5mustbe lowA6isa
“don’tcare”).
Oncethe “Read/Write”and Address bitshave been
written, the subsequentaction dependsupon whetherthe
currentoperation isa“Read”or “Write”operation.
ReadOperation
Oncethe lastaddress bit(A2)hasbeen clocked intothe
SDIinput, the read operation will proceed through an idle
period,lasting fourSCLKperiods.Onthe falling edge of
SCLKCycle“8” (See Figure 4)the serialoutputsignal
(SDO)becomesactive.At thispoint the usercan begin
reading the datacontentsof the addressed command
register (atAddress A2,A1,A0)viathe SDOpin.The
SDOpinwill output thisfive bitdataword(D0through D4)
in ascending order,withthe LSB first, on the rising edges
of the SCLKpin.
WriteOperation
Oncethe lastaddress bit(A2)hasbeen clocked intothe
SDIinput, the write operation will proceed through an idle
period,lasting fourSCLKperiods.Priortothe rising edge
ofSCLKCycle #9 (See Figure 4)the usermustbeginto
applythe eight-bitdataword, thathe/she wishestowrite
tothe serial inputinterface ontothe SDIinputpin.The
microprocessorserial interfacewill catchthe value on the
SDIpinonthe rising edge of the SCLK.The usermust
applythisword(D0through D7),serially,in ascending
orderwiththe LSB first.
SimplifiedInterface Option
The usercan simplifythe design of the circuitry
connecting tothe serial interface bytying boththe SDO
and SDIpinstogether,and reading datafromand/or
writing datatothis“combined”signal.This simplification
ispossible because onlyone of thesesignalsare active at
anygiven time.The inactivesignalwill be tri-stated.
Notes:
1.Priortoreading datafrom(orwriting datato)the SerialInter-
face, the userisnotrequired to provideaclock signalat the
SCLK.However,shortlybefore performing anyread orwrite
operationswiththe SerialInterface,the usermustsupplythe
clock signaltothe SCLKinputpin.
2.EachRead orWrite operation,withthe SerialInterface,will
require16SCLKperiods,asdepicted inFigure 4.
3.Upon completion ofaRead orWritecycle, the usermustne-
gateCSB foratleast250ns(see timing parameterT29 inthe
AC Characteristics),before asserting itagainforthe next
Read orWrite operation.
XRT8000
16
Rev.1.11
CSB
SCLK
SDI
CSB
SCLK
SDO
SDI
Hz
SDI[D7]
T30 T31 T33 T32
Hz
SDOD0SDOD1SDOD7
W/RA0
T23
T22
T24
T26
T27
T25
T28
T29
Figure 5.Serial Interface Timing
Hz
T21
XRT8000
17
Rev.1.11
CONFIGURATION DIAGRAMS
The following sixfiguresdepictall of the configuration
possibilitiesforthe XRT8000.The tableinthe left (FIN)
listsdifferentpossibilitiesfor referenceclock input, while
the tableinthe rightlistsall the possibilitiesfortwo output
clocks.
nxT1
or
nxE1
(1<=n<=16)
kOutputFrequencies (kHz)
(k x 56) (k x 56)/8(k x 64) (k x 64)/8
1 56 7 64 8
2 112 14 128 16
3 168 21 192 24
4 224 28 256 32
5 280 35 320 40
6 336 42 384 48
7 392 49 448 56
8 448 56 512 64
9 504 63 576 72
10 560 70 640 80
11 616 77 704 88
12 672 84 768 96
13 728 91 832 104
14 784 98 896 112
15 840 105 960 120
16 896 112 1,024 128
17 952 119 1,088 136
18 1,008 126 1,152 144
19 1,064 133 1,216 152
20 1,120 140 1,280 160
21 1,176 147 1,344 168
22 1,232 154 1,408 176
23 1,288 161 1,472 184
24 1,344 168 1,536 192
25 1,400 175 1,600 200
26 1,456 182 1,664 208
27 1,512 189 1,728 216
28 1,568 196 1,792 224
29 1,624 203 1,856 232
30 1,680 210 1,920 240
31 1,736 217 1,984 248
32 1,792 224 2,048 256
SYNC 8kHz
k x DS0
(1<=k<=32)
FIN
XRT8000
CLK1
CLK2
Reference Freq.(kHz)
nxT1nxE1
1 1,544 2,048
2 3,088 4,096
3 4,632 6,144
4 6,176 8,192
5 7,720 10,240
6 9,264 12,288
7 10,808 14,336
8 12,352 16,384
9 13,896 18,432
10 15,440 20,480
11 16,984 22,528
12 18,528 24,576
13 20,072 26,624
14 21,616 28,672
15 23,160 30,720
16 24,704 32,768
Figure 6.MasterForwardMode
n
XRT8000
18
Rev.1.11
nxT1
or
nxE1
(1<=n<=16)
nReference Freq.(kHz)
nxT1nxE1
1 1,544 2,048
2 3,088 4,096
3 4,632 6,144
4 6,176 8,192
5 7,720 10,240
6 9,264 12,288
7 10,808 14,336
8 12,352 16,384
9 13,896 18,432
10 15,440 20,480
11 16,984 22,528
12 18,528 24,576
13 20,072 26,624
14 21,616 28,672
15 23,160 30,720
16 24,704 32,768
k
OutputFrequencies (Hz)
(k x 2400) (k x 2400)/8
0.5 1,200 150
1 2,400 300
2 4,800 600
3 7,200 900
4 9,600 1,200
5 12,000 1,500
6 14,400 1,800
7 16,800 2,100
8 19,200 2,400
9 21,600 2,700
10 24,000 3,000
11 26,400 3,300
12 28,800 3,600
13 31,200 3,900
14 33,600 4,200
15 36,000 4,500
16 38,400 4,800
17 40,800 5,100
18 43,200 5,400
SYNC 8kHz
k x 2.4kHz
(1<=k<=18)
FIN
XRT8000
CLK1
CLK2
Figure 7.MasterForwardMode(Cont’d)
nxT1
XRT8000
19
Rev.1.11
64 kHz
or
56 kHz
SYNC 8kHz
FIN
XRT8000
CLK1
CLK2
T1,T1/8
or
E1,E1/8
Figure 8.MasterReverse Mode
OutputFreq.
kHzkHz
1544 193
2048 256
kOutputFrequencies (kHz)
(k x 56)/8(k x 64) (k x 64)/8
1 56 7 64 8
2 112 14 128 16
3 168 21 192 24
4 224 28 256 32
5 280 35 320 40
6 336 42 384 48
7 392 49 448 56
8 448 56 512 64
9 504 63 576 72
10 560 70 640 80
11 616 77 704 88
12 672 84 768 96
13 728 91 832 104
14 784 98 896 112
15 840 105 960 120
16 896 112 1,024 128
17 952 119 1,088 136
18 1,008 126 1,152 144
19 1,064 133 1,216 152
20 1,120 140 1,280 160
21 1,176 147 1,344 168
22 1,232 154 1,408 176
23 1,288 161 1,472 184
24 1,344 168 1,536 192
25 1,400 175 1,600 200
26 1,456 182 1,664 208
27 1,512 189 1,728 216
28 1,568 196 1,792 224
29 1,624 203 1,856 232
30 1,680 210 1,920 240
31 1,736 217 1,984 248
32 1,792 224 2,048 256
SYNC 8kHz
kxDS0
(1<=k<=32)
FIN
XRT8000
CLK1
CLK2
8kHz
Figure 9.Slave ForwardMode
(k x 56)/8
XRT8000
20
Rev.1.11
8kHz
kOutputFrequencies (Hz)
(k x 2400)
1,200 150
1 2,400 300
2 4,800 600
3 7,200 900
4 9,600 1,200
5 12,000 1,500
6 14,400 1,800
7 16,800 2,100
8 19,200 2,400
9 21,600 2,700
10 24,000 3,000
11 26,400 3,300
12 28,800 3,600
13 31,200 3,900
14 33,600 4,200
15 36,000 4,500
16 38,400 4,800
17 40,800 5,100
18 43,200 5,400
SYNC 8kHz
k x 2.4kHz
(1<=k<=18)
FIN
XRT8000
CLK1
CLK2
Figure 10.Slave ForwardMode(Cont’d)
(k x 2400)/8
0.50
XRT8000
21
Rev.1.11
SYNC 8kHz
FIN
XRT8000
CLK1
CLK2
T1,T1/8
or
E1,E1/8
8kHz
Figure 11.Slave Reverse Mode(Cont’d)
OutputFreq.
kHzkHz
1544 193
2048 256
Board LayoutConsiderations
The CLK1 and CLK2 outputsaresurrounded withsupply
pins(GND(514),Vcc(712). It isrecommended to
decouplethesesupplieswith a 0.1uFvery closetothe
pins.The positivesupply(7,12,15)and ground pins
(4,5,14)can all be connected tothe DigitalSupplyand
Ground.
The internalVCOhasitspropersupply’spins(GND 9,
Vcc 10)thesesupplypinshaveto be decoupled bya
0.1uFcapacitorand should be connected toanAnalog
Supplyifpossible. If thereisno Analog Supply, then
connect these pinsas close aspossibletothe supply
source.
If the layoutisdone withseparatelayersforthe supplies,
cutan island underthe XTT8000 suchthatno current
flowsunderthe circuit. It hasbeen observed thatcoupling
can occurbecause heavy digitalcurrentsareflowing
underthe locationsof the XRT8000.
XRT8000
22
Rev.1.11
18 LEAD PLASTIC DUALINLINE
(300 MILPDIP)
Rev.1.00
18
1
10
9
D
eB1
A1
E1
C
E
A2
L
B
Seating
Plane
SYMBOLMINMAXMINMAX
INCHES
A0.145 0.210 3.68 5.33
A10.015 0.070 0.38 1.78
A2 0.115 0.195 2.92 4.95
B0.014 0.024 0.36 0.56
B10.030 0.070 0.76 1.78
C0.008 0.014 0.20 0.38
D0.845 0.925 21.46 23.50
E0.300 0.325 7.62 8.26
E10.240 0.280 6.10 7.11
e 0.100 BSC2.54 BSC
eA0.300 BSC7.62 BSC
eB0.310 0.430 7.87 10.92
L 0.115 0.160 2.92 4.06
a0°15°0°15°
MILLIMETERS
a
A
Note:The controldimension isthe inchcolumn
eB
eA
XRT8000
23
Rev.1.11
SYMBOLMINMAXMINMAX
A0.093 0.104 2.35 2.65
A10.004 0.012 0.10 0.30
B0.013 0.020 0.33 0.51
C0.009 0.013 0.23 0.32
D0.447 0.463 11.35 11.75
E0.291 0.299 7.40 7.60
e 0.050 BSC1.27 BSC
H0.394 0.419 10.00 10.65
L 0.016 0.050 0.40 1.27
a0°8°0°8°
INCHES MILLIMETERS
18 LEAD SMALL OUTLINE
(300 MILJEDECSOIC)
Rev.1.00
e
18 10
9
D
EH
B
A
L
C
A1
Seating
Planea
Note:The controldimension isthe millimetercolumn
1
XRT8000
24
Rev.1.11
NOTICE
EXAR Corporation reservesthe right tomakechangestothe products contained inthispublication in ordertoim-
prove design,performance or reliability.EXAR Corporation assumesno responsibilityforthe use ofany circuitsde-
scribed herein,conveys no license underanypatentorother right, and makesno representation that the circuitsare
free ofpatentinfringement. Chartsand schedules contained herein are onlyforillustration purposesand may vary
depending upon a user’s specificapplication.Whilethe information inthispublication hasbeen carefully checked;
no responsibility,however,isassumed forinaccuracies.
EXAR Corporation doesnotrecommend the use ofanyofitsproductsinlifesupportapplicationswherethe failure or
malfunction of the productcan reasonablybe expected tocausefailure of the lifesupportsystemortosignificantly
affectits safetyoreffectiveness.Productsare notauthorized foruseinsuch applicationsunless EXAR Corporation
receives,inwriting,assurancestoits satisfaction that: (a)the risk ofinjuryordamage hasbeen minimized;(b)the
userassumesall suchrisks;(c)potential liabilityofEXAR Corporation isadequatelyprotected underthe circum-
stances.
Copyright1999--2006 EXAR Corporation
DatasheetSeptember2006
Reproduction,in partorwhole,without the priorwritten consentofEXAR Corporation isprohibited.
