INTEGRATED CIRCUITS DATA SHEET 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1998 Jun 17 2002 Jun 18 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A FEATURES DESCRIPTION * 5 V tolerant inputs for interfacing with 5 V logic The 74LVC74A is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. * Wide supply voltage range from 1.2 to 3.6 V * CMOS low power consumption The 74LVC74A is a dual positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs. * Direct interface with TTL levels * Inputs accept voltages up to 5.5 V * Complies with JEDEC standard no. 8-1A * Specified from -40 to +85 C and -40 to +125 C. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH PARAMETER CONDITIONS UNIT propagation delay nCP to nQ, nQ CL = 50 pF; VCC = 3.3 V 2.5 ns nSD to nQ, nQ CL = 50 pF; VCC = 3.3 V 2.5 ns nRD to nQ, nQ CL = 50 pF; VCC = 3.3 V 2.5 ns CL = 50 pF; VCC = 3.3 V 250 MHz 4.0 pF VCC = 3.3 V; notes 1 and 2 15 pF fmax maximum clock frequency CI input capacitance CPD power dissipation capacitance per gate Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC. 2002 Jun 18 TYPICAL 2 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74LVC74AD -40 to +125 C 14 SO plastic SOT108-1 74LVC74ADB -40 to +125 C 14 SSOP plastic SOT337-1 74LVC74APW -40 to +125 C 14 TSSOP plastic SOT402-1 PINNING FUNCTION TABLES Table 1 See note 1. INPUT OUTPUT nSD nRD nCP nD nQ nQ L H X X H L H L X X L H L L X X H H Table 2 See note 1. INPUT OUTPUT PIN SYMBOL DESCRIPTION 1 1RD asynchronous reset-direct input (active LOW) 2 1D data inputs 3 1CP clock input (LOW-to-HIGH, edge-triggered) 4 1SD asynchronous set-direct input (active LOW) 5 1Q true flip-flop outputs 6 1Q complement flip-flop outputs nSD nRD nCP nD nQn+1 nQn+1 7 GND H H L L H 8 2Q complement flip-flop outputs L 9 2Q true flip-flop outputs 10 2SD asynchronous set-direct input (active LOW) 11 2CP clock input (LOW-to-HIGH, edge-triggered) X = don't care; 12 2D data inputs = LOW-to-HIGH CP transition; 13 2RD Qn+1 = state after the next LOW-to-HIGH CP transition. asynchronous reset-direct input (active LOW) 14 VCC supply voltage H H H H Note to Tables 1 and 2 1. H = HIGH voltage level; L = LOW voltage level; 2002 Jun 18 3 ground (0 V) Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger handbook, halfpage 1RD 1 14 VCC 1D 2 13 2RD 1CP 3 12 2D 1SD 4 1Q 5 10 2SD 1Q 6 9 GND 7 8 2Q 4 10 handbook, halfpage 1SD 2SD SD 1Q 1D Q D 2D 2Q 1CP CP 2CP FF 1Q Q 2Q RD 2 12 3 11 11 2CP 74 74LVC74A 2Q 1 13 Fig.1 Pin configuration. MNA418 Fig.2 Logic diagram. handbook, halfpage 4 2 4 3 2 1 S 3 5 11 12 13 1D 1CP SD Q D Q 5 1Q 6 RD 6 R 10 S 1Q CP FF 1 10 1SD C1 1D 6 8 1RD 2RD MNA417 handbook, halfpage 5 9 1RD 2SD 9 C1 1D 12 8 R 11 2D 2CP SD Q D 9 CP FF MNA419 2Q Q 2Q 8 RD 13 Fig.3 IEC logic symbol. 2002 Jun 18 2RD MNA420 Fig.4 Functional diagram. 4 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A handbook, full pagewidth Q C C C C C C D Q C C RD SD CP MNA421 C C Fig.5 Logic diagram (one flip-flop). 2002 Jun 18 5 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER supply voltage CONDITIONS MIN. MAX. UNIT for maximum speed performance 2.7 3.6 V for low-voltage applications 1.2 3.6 V VI input voltage 0 5.5 V VO output voltage 0 VCC V Tamb ambient temperature -40 +125 C tr, tf input rise and fall times VCC = 1.2 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER VCC supply voltage CONDITIONS MIN. MAX. UNIT -0.5 +6.5 V IIK input diode current VI < 0 - -50 mA VI input voltage note 1 -0.5 +6.5 V IOK output diode current VO > VCC or VO < 0 - 50 mA VO output voltage note 1 -0.5 VCC + 0.5 V IO output source or sink current VO = 0 to VCC - 50 mA IGND, ICC VCC or GND current - 100 mA Tstg storage temperature -65 +150 C Ptot power dissipation per package SO above 70 C derate linearly with 8 mW/K - 500 mW SSOP and TSSOP above 60 C derate linearly with 5.5 mW/K - 500 mW Note 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2002 Jun 18 6 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A DC CHARACTERISTICS Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS Tamb (C) -40 to +85 SYMBOL PARAMETER OTHER VIH VIL VOH VOL HIGH-level input voltage VCC (V) MIN. -40 to +125 TYP.(1) MAX. MIN. UNIT MAX. 1.2 VCC - - VCC - V 2.7 to 3.6 2.0 - - 2.0 - V 1.2 - - 0 - 0 V 2.7 to 3.6 - - 0.8 - 0.8 V 2.7 to 3.6 VCC - 0.2 - - VCC - 0.3 - V VI = VIH or VIL; IO = -12 mA 2.7 VCC - 0.5 - - VCC - 0.65 - V VI = VIH or VIL; IO = -18 mA 3.0 VCC - 0.6 - - VCC - 0.75 - V VI = VIH or VIL; IO = -24 mA 3.0 VCC - 0.8 - - VCC - 1.0 - V 2.7 to 3.6 - - 0.2 - 0.3 V VI = VIH or VIL; IO = 12 mA 2.7 - - 0.4 - 0.6 V VI = VIH or VIL; IO = 24 mA 3.0 - - 0.55 - 0.8 V VI = 5.5 V or GND 3.6 - 0.1 5 - 20 A LOW-level input voltage HIGH-level VI = VIH or VIL; output voltage IO = -100 A LOW-level VI = VIH or VIL; output voltage IO = 100 A ILI input leakage current ICC quiescent VI = VCC or GND; supply current IO = 0 3.6 - 0.1 10 - 40 A ICC additional VI = VCC - 0.6V; quiescent IO = 0 supply current per input pin 2.7 to 3.6 - 5 500 - 5000 A Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 2002 Jun 18 7 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A AC CHARACTERISTICS GND = 0 V; tr = tf 2.5 ns. Tamb (C) SYMBOL PARAMETER -40 to +85 WAVEFORMS MIN. TYP. MAX. -40 to +125 MIN. UNIT MAX. VCC = 1.2 V tPHL/tPLH propagation delay nCP to nQ, nQ see Figs 6 and 8 - 15 - - - ns propagation delay nSD to nQ, nQ see Figs 7 and 8 - 15 - - - ns propagation delay nRD to nQ, nQ see Figs 7 and 8 - 15 - - - ns see Figs 6 and 8 1.0 2.7 6.0 1.0 7.5 ns VCC = 2.7 V tPHL/tPLH propagation delay nCP to nQ, nQ propagation delay nSD to nQ, nQ see Figs 7 and 8 1.0 3.2 6.4 1.0 8.0 ns propagation delay nRD to nQ, nQ see Figs 7 and 8 1.0 3.2 6.4 1.0 8.0 ns clock pulse width HIGH or LOW see Figs 6 and 8 3.3 - - 4.5 - ns set or reset pulse width LOW see Figs 7 and 8 3.3 - - 4.5 - ns trem removal time set or reset see Figs 7 and 8 1.5 - - 1.5 - ns tsu set-up time nD to nCP see Figs 6 and 8 2.2 - - 2.2 - ns th hold time nD to nCP see Figs 6 and 8 1.0 - - 1.0 - ns fmax maximum clock pulse frequency see Figs 6 and 8 83 - - 66 - MHz see Figs 6 and 8 1.0 2.5 5.2 1.0 6.5 ns tW VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH tW propagation delay nCP to nQ, nQ propagation delay nSD to nQ, nQ see Figs 7 and 8 1.0 2.5 5.4 1.0 7.0 ns propagation delay nRD to nQ, nQ see Figs 7 and 8 1.0 2.5 5.4 1.0 7.0 ns clock pulse width HIGH or LOW see Figs 6 and 8 3.3 1.3 - 4.5 - ns set or reset pulse width LOW see Figs 7 and 8 3.3 1.7 - 4.5 - ns trem removal time set or reset see Figs 7 and 8 1.0 -3.0 - 1.0 - ns tsu set-up time nD to nCP see Figs 6 and 8 2.0 0.8 - 2.0 - ns th hold time nD to nCP see Figs 6 and 8 0.0 -0.7 - 0.0 - ns fmax maximum clock pulse frequency see Figs 6 and 8 150 250 - 120 - MHz tsk(0) skew note 2 - - 1.0 - 1.5 ns Notes 1. Typical values are measured at VCC = 3.3 V. 2. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 2002 Jun 18 8 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A AC WAVEFORMS VI handbook, full pagewidth VM nD input GND th th t su t su 1/fmax VI VM nCP input GND tW t PHL t PLH VOH VM nQ output VOL VOH nQ output VM VOL t PLH t PHL MNA422 VM = 1.5 V at VCC 2.7 V; VM = 0.5VCC at VCC < 2.7 V; VOL and VOH are typical output voltage drop that occur with the output load. Fig.6 The clock input (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the nCP to nD hold times, the output transition times and the maximum clock pulse frequency. 2002 Jun 18 9 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A VI handbook, full pagewidth VM nCP input GND t rem VI VM nSD input GND tW tW VI VM nRD input GND t PHL t PLH VOH nQ output VM VOL VOH VM nQ output VOL MNA423 t PHL t PLH VM = 1.5 V at VCC 2.7 V; VM = 0.5VCC at VCC < 2.7 V; VOL and VOH are typical output voltage drop that occur with the output load. Fig.7 The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD to nCP removal time. 2002 Jun 18 10 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger S1 handbook, full pagewidth VCC VI PULSE GENERATOR RL 500 VO 74LVC74A 2 x VCC open GND D.U.T. CL 50 pF RT RL 500 MNA368 VCC VI tPLH/tPHL 1.2 V VCC open 2.7 V 2.7 V open 3.0 to 3.6 V 2.7 V open Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.8 Load circuitry for switching times. 2002 Jun 18 11 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp 1 L 7 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.244 0.039 0.050 0.041 0.228 0.016 0.010 0.057 inches 0.069 0.004 0.049 0.028 0.024 0.01 0.01 0.028 0.004 0.012 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 2002 Jun 18 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 12 o 8 0o Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 2002 Jun 18 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 96-01-18 99-12-27 MO-150 13 o Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index Lp L 1 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 2002 Jun 18 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-04-04 99-12-27 MO-153 14 o Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger SOLDERING 74LVC74A If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. To overcome these problems the double-wave soldering method was specifically developed. 2002 Jun 18 15 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable(3) HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not PLCC(4), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(2) suitable suitable suitable not recommended(4)(5) suitable not recommended(6) suitable Notes 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 Jun 18 16 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74A DATA SHEET STATUS DATA SHEET STATUS(1) PRODUCT STATUS(2) DEFINITIONS Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2002 Jun 18 17 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger NOTES 2002 Jun 18 18 74LVC74A Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger NOTES 2002 Jun 18 19 74LVC74A Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA74 (c) Koninklijke Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613508/03/pp20 Date of release: 2002 Jun 18 Document order number: 9397 750 09838