DATA SH EET
Product specification
Supersedes data of 1998 Jun 17 2002 Jun 18
INTEGRATED CIRCUITS
74LVC74A
Dual D-type flip-flop with set and
reset; positive-edge trigger
2002 Jun 18 2
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
FEATURES
•5 V tolerant inputs for interfacing with 5 V logic
•Wide supply voltage range from 1.2 to 3.6 V
•CMOS low power consumption
•Direct interface with TTL levels
•Inputs accept voltages up to 5.5 V
•Complies with JEDEC standard no. 8-1A
•Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74LVC74A is a high-performance, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The 74LVC74A is a dual positive edge triggered D-type
flip-flop with individual data (D) inputs, clock (CP) inputs,
set (SD) and (RD) inputs, and complementary Q and Q
outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition, for predictable operation.
Schmitt-trigger action at all inputs makes the circuit highly
tolerant to slower input rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f≤2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL×VCC2×fo) = sum of the outputs.
2. The condition is VI= GND to VCC.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH propagation delay
nCP to nQ, nQC
L
= 50 pF; VCC = 3.3 V 2.5 ns
nSDto nQ, nQC
L
= 50 pF; VCC = 3.3 V 2.5 ns
nRDto nQ, nQC
L
= 50 pF; VCC = 3.3 V 2.5 ns
fmax maximum clock frequency CL= 50 pF; VCC = 3.3 V 250 MHz
CIinput capacitance 4.0 pF
CPD power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 15 pF
2002 Jun 18 3
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
ORDERING INFORMATION
TYPE NUMBER PACKAGE
TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE
74LVC74AD −40 to +125 °C 14 SO plastic SOT108-1
74LVC74ADB −40 to +125 °C 14 SSOP plastic SOT337-1
74LVC74APW −40 to +125 °C 14 TSSOP plastic SOT402-1
FUNCTION TABLES
Table 1 See note 1.
Table 2 See note 1.
Note to Tables 1 and 2
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑= LOW-to-HIGH CP transition;
Qn+1 = state after the next LOW-to-HIGH CP
transition.
PINNING
INPUT OUTPUT
nSDnRDnCP nD nQ nQ
LHXXHL
HLXXLH
LLXXHH
INPUT OUTPUT
nSDnRDnCP nD nQn+1 nQn+1
HH↑LLH
HH↑HHL
PIN SYMBOL DESCRIPTION
11
R
D
asynchronous reset-direct input
(active LOW)
2 1D data inputs
3 1CP clock input (LOW-to-HIGH,
edge-triggered)
41
S
D
asynchronous set-direct input
(active LOW)
5 1Q true flip-flop outputs
61
Q complement flip-flop outputs
7 GND ground (0 V)
82
Q complement flip-flop outputs
9 2Q true flip-flop outputs
10 2SDasynchronous set-direct input
(active LOW)
11 2CP clock input (LOW-to-HIGH,
edge-triggered)
12 2D data inputs
13 2RDasynchronous reset-direct input
(active LOW)
14 VCC supply voltage
2002 Jun 18 4
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
Fig.1 Pin configuration.
handbook, halfpage
MNA417
74
1
2
3
4
5
6
78
14
13
12
11
10
9
1RD
1D
1CP
1SD
1Q
1Q
GND 2Q
2Q
2SD
2CP
2D
2RD
VCC
Fig.2 Logic diagram.
MNA418
handbook, halfpage
RD
FF
SD
410
Q1Q
2Q
1Q
2Q
5
9
2
12
3
11 6
8
Q
1SD
CP
2CP
1CP
2D
1D D
2SD
113
1RD2RD
Fig.3 IEC logic symbol.
handbook, halfpage
MNA419
6
3
2C1
4S
1D
1R
5
8
11
12 C1
10 S
1D
13 R
9
Fig.4 Functional diagram.
handbook, halfpage
RD
FF
SD
4
Q1Q
1Q
5
2
3
6
Q
1SD
CP
1CP
1D D
11RD
MNA420
RD
FF
SD
10
Q2Q
2Q
9
12
11
8
Q
2SD
CP
2CP
2D D
13 2RD
2002 Jun 18 5
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
Fig.5 Logic diagram (one flip-flop).
handbook, full pagewidth
MNA421
SD
CP
RD
D
C
C
Q
C
C
C
C
C
C
Q
C
C
2002 Jun 18 6
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage for maximum speed performance 2.7 3.6 V
for low-voltage applications 1.2 3.6 V
VIinput voltage 0 5.5 V
VOoutput voltage 0 VCC V
Tamb ambient temperature −40 +125 °C
tr,t
finput rise and fall times VCC = 1.2 to 2.7 V 0 20 ns/V
VCC = 2.7 to 3.6 V 0 10 ns/V
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5 V
IIK input diode current VI<0 −−50 mA
VIinput voltage note 1 −0.5 +6.5 V
IOK output diode current VO>V
CC or VO<0 −±50 mA
VOoutput voltage note 1 −0.5 VCC + 0.5 V
IOoutput source or sink current VO=0toV
CC −±50 mA
IGND, ICC VCC or GND current −±100 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation per package
SO above 70 °C derate linearly with
8 mW/K −500 mW
SSOP and TSSOP above 60 °C derate linearly with
5.5 mW/K −500 mW
2002 Jun 18 7
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground=0V).
Note
1. All typical values are measured at VCC = 3.3 V and Tamb =25°C.
SYMBOL PARAMETER
TEST CONDITIONS Tamb (°C)
UNIT
OTHER VCC (V) −40 to +85 −40 to +125
MIN. TYP.(1) MAX. MIN. MAX.
VIH HIGH-level
input voltage 1.2 VCC −−V
CC −V
2.7 to 3.6 2.0 −−2.0 −V
VIL LOW-level
input voltage 1.2 −−0−0V
2.7 to 3.6 −−0.8 −0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL;
IO=−100 µA2.7 to 3.6 VCC −0.2 −−V
CC −0.3 −V
VI=V
IH or VIL;
IO=−12 mA 2.7 VCC −0.5 −−V
CC −0.65 −V
VI=V
IH or VIL;
IO=−18 mA 3.0 VCC −0.6 −−V
CC −0.75 −V
VI=V
IH or VIL;
IO=−24 mA 3.0 VCC −0.8 −−V
CC −1.0 −V
VOL LOW-level
output voltage VI=V
IH or VIL;
IO= 100 µA2.7 to 3.6 −−0.2 −0.3 V
VI=V
IH or VIL;
IO=12mA 2.7 −−0.4 −0.6 V
VI=V
IH or VIL;
IO=24mA 3.0 −−0.55 −0.8 V
ILI input leakage
current VI= 5.5 Vor GND 3.6 −±0.1 ±5−±20 µA
ICC quiescent
supply current VI=V
CC or GND;
IO=0 3.6 −0.1 10 −40 µA
∆ICC additional
quiescent
supplycurrent
per input pin
VI=V
CC −0.6V;
IO=0 2.7 to 3.6 −5 500 −5000 µA
2002 Jun 18 8
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
AC CHARACTERISTICS
GND = 0 V; tr=t
f≤2.5 ns.
Notes
1. Typical values are measured at VCC = 3.3 V.
2. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
SYMBOL PARAMETER WAVEFORMS
Tamb (°C)
UNIT−40 to +85 −40 to +125
MIN. TYP. MAX. MIN. MAX.
VCC = 1.2 V
tPHL/tPLH propagation delay nCP to nQ, nQ see Figs 6 and 8 −15 −−−ns
propagation delay nSDto nQ, nQ see Figs 7 and 8 −15 −−−ns
propagation delay nRDto nQ, nQ see Figs 7 and 8 −15 −−−ns
VCC = 2.7 V
tPHL/tPLH propagation delay nCP to nQ, nQ see Figs 6 and 8 1.0 2.7 6.0 1.0 7.5 ns
propagation delay nSDto nQ, nQ see Figs 7 and 8 1.0 3.2 6.4 1.0 8.0 ns
propagation delay nRDto nQ, nQ see Figs 7 and 8 1.0 3.2 6.4 1.0 8.0 ns
tWclock pulse width HIGH or LOW see Figs 6 and 8 3.3 −−4.5 −ns
set or reset pulse width LOW see Figs 7 and 8 3.3 −−4.5 −ns
trem removal time set or reset see Figs 7 and 8 1.5 −−1.5 −ns
tsu set-up time nD to nCP see Figs 6 and 8 2.2 −−2.2 −ns
thhold time nD to nCP see Figs 6 and 8 1.0 −−1.0 −ns
fmax maximum clock pulse frequency see Figs 6 and 8 83 −−66 −MHz
VCC = 3.0 to 3.6 V; note 1
tPHL/tPLH propagation delay nCP to nQ, nQ see Figs 6 and 8 1.0 2.5 5.2 1.0 6.5 ns
propagation delay nSDto nQ, nQ see Figs 7 and 8 1.0 2.5 5.4 1.0 7.0 ns
propagation delay nRDto nQ, nQ see Figs 7 and 8 1.0 2.5 5.4 1.0 7.0 ns
tWclock pulse width HIGH or LOW see Figs 6 and 8 3.3 1.3 −4.5 −ns
set or reset pulse width LOW see Figs 7 and 8 3.3 1.7 −4.5 −ns
trem removal time set or reset see Figs 7 and 8 1.0 −3.0 −1.0 −ns
tsu set-up time nD to nCP see Figs 6 and 8 2.0 0.8 −2.0 −ns
thhold time nD to nCP see Figs 6 and 8 0.0 −0.7 −0.0 −ns
fmax maximum clock pulse frequency see Figs 6 and 8 150 250 −120 −MHz
tsk(0) skew note 2 −− 1.0 −1.5 ns
2002 Jun 18 9
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
AC WAVEFORMS
handbook, full pagewidth
MNA422
th
tsu
th
tPHL
tPHL
tW
tPLH
tPLH
tsu
1/fmax
VM
VM
VM
VM
VI
GND
VI
GND
nCP input
nD input
VOH
VOL
nQ output
VOH
VOL
nQ output
Fig.6 The clock input (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up,
the nCP to nD hold times, the output transition times and the maximum clock pulse frequency.
VM= 1.5 V at VCC ≥2.7 V;
VM= 0.5VCC at VCC < 2.7 V;
VOL and VOH are typical output voltage drop that occur with the output load.
2002 Jun 18 10
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
handbook, full pagewidth
MNA423
trem
tPHL
tPHL
tW
tPLH
tPLH
VM
VM
VM
tW
VM
VM
VI
GND
VI
GND
nSD input
VI
GND
nRD input
nCP input
VOH
VOL
nQ output
VOH
VOL
nQ output
Fig.7 The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths
and the nRDto nCP removal time.
VM= 1.5 V at VCC ≥2.7 V;
VM= 0.5VCC at VCC < 2.7 V;
VOL and VOH are typical output voltage drop that occur with the output load.
2002 Jun 18 11
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
handbook, full pagewidth
open
GND
50 pF
2 × VCC
VCC
VIVO
MNA368
D.U.T.
CL
RT
RL
500 Ω
RL
500 Ω
PULSE
GENERATOR
S1
Fig.8 Load circuitry for switching times.
VCC VItPLH/tPHL
1.2 V VCC open
2.7 V 2.7 V open
3.0 to 3.6 V 2.7 V open
Definitions for test circuits:
RL= Load resistor.
CL= Load capacitance including jig and probe capacitance.
RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.
2002 Jun 18 12
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
PACKAGE OUTLINES
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.050
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
97-05-22
99-12-27
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
2002 Jun 18 13
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25 0.2
7.9
7.6 1.03
0.63 0.9
0.7 1.4
0.9 8
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT337-1 96-01-18
99-12-27
(1)
w
M
b
p
D
H
E
E
Z
e
c
v
M
A
X
A
y
17
14 8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
A
max.
2.0
2002 Jun 18 14
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21.0
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 95-04-04
99-12-27
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.10
pin 1 index
2002 Jun 18 15
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
SOLDERING
Introduction to soldering surface mount packages
Thistextgivesaverybriefinsighttoacomplextechnology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certainsurfacemountICs,butitisnotsuitable for finepitch
SMDs. In these situations reflow soldering is
recommended.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuit board by screen printing,stencillingor
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Wave soldering
Conventional single wave soldering is not recommended
forsurface mount devices (SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackages with leadsonfoursides,thefootprint must
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2002 Jun 18 16
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. Formoredetailedinformationon the BGA packages refertothe
“(LF)BGAApplicationNote
”(AN01026);orderacopy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE(1) SOLDERING METHOD
WAVE REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,
HVSON, SMS not suitable(3) suitable
PLCC(4), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(4)(5) suitable
SSOP, TSSOP, VSO not recommended(6) suitable
2002 Jun 18 17
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DATA SHEET STATUS(1) PRODUCT
STATUS(2) DEFINITIONS
Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseoratanyotherconditionsabovethosegiveninthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentation orwarrantythatsuch applicationswillbe
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorselling theseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuse of anyoftheseproducts,conveysno licence ortitle
under any patent, copyright, or mask work right to these
products,andmakesnorepresentationsor warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
2002 Jun 18 18
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
NOTES
2002 Jun 18 19
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset; positive-edge
trigger 74LVC74A
NOTES
© Koninklijke Philips Electronics N.V. 2002 SCA74
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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
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Printed in The Netherlands 613508/03/pp20 Date of release: 2002 Jun 18 Document order number: 9397 750 09838
