REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD9854
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
CMOS 300 MSPS Quadrature
Complete-DDS
FUNCTIONAL BLOCK DIAGRAM
DIGITAL MULTIPLIERS
SYSTEM
CLOCK
DAC R
SET
INV.
SINC
FILTER
FREQUENCY
ACCUMULATOR
ACC 1
I/O PORT BUFFERS
COMPARATOR
PROGRAMMING REGISTERS
4–20
REF CLK
MULTI-
PLIER
DIFF/SINGLE
SELECT
REFERENCE
CLOCK IN
FSK/BPSK/HOLD
DATA IN
BIDIRECTIONAL
INTERNAL/EXTERNAL
I/O UPDATE
CLOCK
READ WRITE SERIAL/
PARALLEL
SELECT
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT
PARALLEL
LOAD
MASTER
RESET
+V
S
GND
CLOCK
OUT
ANALOG
IN
SHAPED
ON/OFF
KEYING
ANALOG
OUT
ANALOG
OUT
INTERNAL
PROGRAMMABLE
UPDATE CLOCK
PHASE-TO-
AMPLITUDE
CONVERTER
12-BIT
"Q" DAC OR
CONTROL
DAC
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
DQ
CK 2
INT
EXT
SYSTEM
CLOCK
REF
CLK
BUFFER
SYSTEM
CLOCK
MUX
DELTA
FREQUENCY
RATE TIMER
SYSTEM
CLOCK
DELTA
FREQUENCY
WORD
FREQUENCY
TUNING
WORD 1
FREQUENCY
TUNING
WORD 2
1ST 14-BIT PHASE/
OFFSET WORD
2ND 14-BIT PHASE/
OFFSET WORD
I AND Q 12-BIT
AM MODULATION
12-BIT DC
CONTROL
MUX
SYSTEM CLOCK
PHASE
ACCUMULATOR
ACC 2
DDS CORE
12-BIT "I"
DAC
INV.
SINC
FILTER
I
Q
MUX MUX
MUX MUX
MUX MUX
SYSTEM
CLOCK
SYSTEM
CLOCK
48 48 48 14 14 12 12
BUS
12
12
12
12
12
12
14
17
174848
48
AD9854
FEATURES
300 MHz Internal Clock Rate
FSK, BPSK, PSK, CHIRP, AM Operation
Dual Integrated 12-Bit D/A Converters
Ultrahigh-Speed Comparator, 3 ps RMS Jitter
Excellent Dynamic Performance: 80 dB SFDR @ 100 MHz
(1 MHz) AOUT
4 to 20 Programmable Reference Clock Multiplier
Dual 48-Bit Programmable Frequency Registers
Dual 14-Bit Programmable Phase Offset Registers
12-Bit Amplitude Modulation and Programmable
Shaped On/Off Keying Function
Single Pin FSK and BPSK Data Interface
PSK Capability Via I/O Interface
Linear or Nonlinear FM Chirp Functions with Single
Pin Frequency “Hold” Function
Frequency-Ramped FSK
<25 ps RMS Total Jitter in Clock Generator Mode
Automatic Bidirectional Frequency Sweeping
SIN(x)/x Correction
Simplified Control Interface
10 MHz Serial, 2-Wire or 3-Wire SPI-Compatible or
100 MHz Parallel 8-Bit Programming
3.3 V Single Supply
Multiple Power-Down Functions
Single-Ended or Differential Input Reference Clock
Small 80-Lead LQFP Packaging
APPLICATIONS
Agile, Quadrature L.O. Frequency Synthesis
Programmable Clock Generator
FM Chirp Source for Radar and Scanning Systems
Test and Measurement Equipment
Commercial and Amateur RF Exciter
GENERAL DESCRIPTION
The AD9854 digital synthesizer is a highly integrated device
that uses advanced DDS technology, coupled with two internal
high-speed, high-performance quadrature D/A converters to
form a digitally-programmable I and Q synthesizer function. When
referenced to an accurate clock source, the AD9854 generates
highly stable, frequency-phase-amplitude-programmable sine
and cosine outputs that can be used as an agile L.O. in com-
munications, radar, and many other applications. The AD9854’s
innovative high-speed DDS core provides 48-bit frequency
resolution (1 microHertz tuning resolution with 300 MHz
SYSCLK). Phase truncation to 17 bits assures excellent SFDR.
The AD9854’s circuit architecture allows the generation of
(continued on page 15)
REV. A
AD9854
–2–
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . . 5
Test Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 5
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . 6–7
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TYPICAL APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . 13
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DESCRIPTION OF AD9854 MODES OF OPERATION . . 15
Single-Tone (Mode 000) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Unramped FSK (Mode 001) . . . . . . . . . . . . . . . . . . . . . . 16
Ramped FSK (Mode 010) . . . . . . . . . . . . . . . . . . . . . . . . 16
Chirp (Mode 011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Basic FM Chirp Programming Steps . . . . . . . . . . . . . . . . 20
BPSK (Mode 100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
USING THE AD9854 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Internal and External Update Clock . . . . . . . . . . . . . . . . . 22
Shaped On/Off Keying . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I and Q DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Control DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Inverse SINC Function . . . . . . . . . . . . . . . . . . . . . . . . . . 24
REFCLK Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PROGRAMMING THE AD9854 . . . . . . . . . . . . . . . . . . . 25
Parallel I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Serial Port I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . 27
GENERAL OPERATION OF THE
SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Instruction Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Serial Interface Port Pin Description . . . . . . . . . . . . . . . . 28
Notes on Serial Port Operation . . . . . . . . . . . . . . . . . . . . 28
MSB/LSB TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Control Register Description . . . . . . . . . . . . . . . . . . . . . . 29
POWER DISSIPATION AND
THERMAL CONSIDERATIONS . . . . . . . . . . . . . . . . . 30
THERMAL IMPEDANCE . . . . . . . . . . . . . . . . . . . . . . . . . 31
JUNCTION TEMPERATURE CONSIDERATIONS . . . . 31
EVALUATION OF OPERATING CONDITIONS . . . . . . 32
THERMALLY ENHANCED PACKAGE
MOUNTING GUIDELINES . . . . . . . . . . . . . . . . . . . . 32
EVALUATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . 33
OPERATING INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . 33
Attach REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Low-Pass Filter Testing . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Observing the Unfiltered I
OUT1
and the
Unfiltered I
OUT2
DAC Signals . . . . . . . . . . . . . . . . . . . . . 34
Observing the Filtered I
OUT1
and the Filtered I
OUT2
. . . . 34
Observing the Filtered I
OUT
and the Filtered I
OUTB
. . . . . 34
Connecting the High-Speed Comparator in a
Single-Ended Configuration . . . . . . . . . . . . . . . . . . . . . . . 35
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 42
REV. A –3–
AD9854
(VS = 3.3 V 5%, RSET = 3.9 k external reference clock frequency = 30 MHz with
REFCLK Multiplier enabled at 10 for AD9854ASQ, external reference clock frequency = 20 MHz with REFCLK Multiplier
enabled at 10 for AD9854AST unless otherwise noted.)
Test AD9854ASQ AD9854AST
Parameter Temp Level Min Typ Max Min Typ Max Unit
REF CLOCK INPUT CHARACTERISTICS
1
Internal System Clock Frequency Range FULL VI 5 300 5 200 MHz
External REF Clock Frequency Range
REFCLK Multiplier Enabled FULL VI 5 75 5 50 MHz
REFCLK Multiplier Disabled FULL VI 5 300 5 200 MHz
Duty Cycle 25°CIV 455055 455055 %
Input Capacitance 25°CIV 3 3 pF
Input Impedance 25°C IV 100 100 kΩ
Differential Mode Common-Mode Voltage Range
Minimum Signal Amplitude 25°C IV 800 800 mV p-p
Common-Mode Range 25°C IV 1.6 1.75 1.9 1.6 1.75 1.9 V
V
IH
(Single-Ended Mode) 25°C IV 2.3 2.3 V
V
IL
(Single-Ended Mode) 25°CIV 1 1 V
DAC STATIC OUTPUT CHARACTERISTICS
Output Update Speed FULL I 300 200 MSPS
Resolution 25°C IV 12 12 Bits
I and Q Full-Scale Output Current 25°C IV 5 10 20 5 10 20 mA
I and Q DAC DC Gain Imbalance
2
25°C I –0.5 +0.15 +0.5 –0.5 +0.15 +0.5 dB
Gain Error 25°C I –6 +2.25 –6 +2.25 % FS
Output Offset 25°CI 2 2 µA
Differential Nonlinearity 25°C I 0.3 1.25 0.3 1.25 LSB
Integral Nonlinearity 25°C I 0.6 1.66 0.6 1.66 LSB
Output Impedance 25°C IV 100 100 kΩ
Voltage Compliance Range 25°C I –0.5 +1.0 –0.5 +1.0 V
DAC DYNAMIC OUTPUT CHARACTERISTICS
I and Q DAC Quad. Phase Error 25°C IV 0.2 1 0.2 1 Degrees
DAC Wideband SFDR
1 MHz to 20 MHz A
OUT
25°C V 58 58 dBc
20 MHz to 40 MHz A
OUT
25°C V 56 56 dBc
40 MHz to 60 MHz A
OUT
25°C V 52 52 dBc
60 MHz to 80 MHz A
OUT
25°C V 48 48 dBc
80 MHz to 100 MHz A
OUT
25°C V 48 48 dBc
100 MHz to 120 MHz A
OUT
25°C V 48 dBc
DAC Narrowband SFDR
10 MHz A
OUT
(±1 MHz) 25°C V 83 83 dBc
10 MHz A
OUT
(±250 kHz) 25°C V 83 83 dBc
10 MHz A
OUT
(±50 kHz) 25°C V 91 91 dBc
41 MHz A
OUT
(±1 MHz) 25°C V 82 82 dBc
41 MHz A
OUT
(±250 kHz) 25°C V 84 84 dBc
41 MHz A
OUT
(±50 kHz) 25°C V 89 89 dBc
119 MHz A
OUT
(±1 MHz) 25°C V 71 dBc
119 MHz A
OUT
(±250 kHz) 25°C V 77 dBc
119 MHz A
OUT
(±50 kHz) 25°C V 83 dBc
Residual Phase Noise
(A
OUT
= 5 MHz, Ext. CLK = 30 MHz,
REFCLK Multiplier Engaged at 10×)
1 kHz Offset 25°C V 140 140 dBc/Hz
10 kHz Offset 25°C V 138 138 dBc/Hz
100 kHz Offset 25°C V 142 142 dBc/Hz
(A
OUT
= 5 MHz, Ext. CLK = 300 MHz,
REFCLK Multiplier Bypassed)
1 kHz Offset 25°C V 142 142 dBc/Hz
10 kHz Offset 25°C V 148 148 dBc/Hz
100 kHz Offset 25°C V 152 152 dBc/Hz
Pipeline Delays
Phase Accumulator and DDS Core 25°C IV 30 30 SysClk Cycles
Inverse Sinc Filter 25°C IV 12 12 SysClk Cycles
Digital Multiplier 25°C IV 11 11 SysClk Cycles
SPECIFICATIONS
REV. A
–4–
AD9854–SPECIFICATIONS
Test AD9854ASQ AD9854AST
Parameter Temp Level Min Typ Max Min Typ Max Unit
MASTER RESET DURATION 25°C IV 10 10 SysClk Cycles
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance 25°CV 3 3 pF
Input Resistance 25°C IV 500 500 kΩ
Input Current 25°CI ±1±5±1±5µA
Hysteresis 25°C IV 10 20 10 20 mV p-p
COMPARATOR OUTPUT CHARACTERISTICS
Logic “1” Voltage, High Z Load FULL VI 3.1 3.1 V
Logic “0” Voltage, High Z Load FULL VI 0.16 0.16 V
Output Power, 50 Ω Load, 120 MHz Toggle Rate 25°C I 9 11 9 11 dBm
Propagation Delay 25°CIV 3 3 ns
Output Duty Cycle Error
3
25°CI –10 ±1 +10 –10 ±1 +10 %
Rise/Fall Time, 5 pF Load 25°CV 2 2 ns
Toggle Rate, High Z Load 25°C IV 300 350 300 350 MHz
Toggle Rate, 50 Ω Load 25°C IV 375 400 375 400 MHz
Output Cycle-to-Cycle Jitter
4
25°C IV 4.0 4.0 ps rms
COMPARATOR NARROWBAND SFDR
4
10 MHz (±1 MHz) 25°C V 84 84 dBc
10 MHz (±250 kHz) 25°C V 84 84 dBc
10 MHz (±50 kHz) 25°C V 92 92 dBc
41 MHz (±1 MHz) 25°C V 76 76 dBc
41 MHz (±250 kHz) 25°C V 82 82 dBc
41 MHz (±50 kHz) 25°C V 89 89 dBc
119 MHz (±1 MHz) 25°C V 73 dBc
119 MHz (±250 kHz) 25°C V 73 dBc
119 MHz (±50 kHz) 25°C V 83 dBc
CLOCK GENERATOR OUTPUT JITTER
5
5 MHz A
OUT
25°C V 23 23 ps rms
40 MHz A
OUT
25°C V 12 12 ps rms
100 MHz A
OUT
25°C V 7 7 ps rms
PARALLEL I/O TIMING CHARACTERISTICS
T
ASU
(Address Setup Time to WR Signal Active) FULL IV 8.0 7.5 8.0 7.5 ns
T
ADHW
(Address Hold Time to WR Signal Inactive) FULL IV 0 0 ns
T
DSU
(Data Setup Time to WR Signal Active) FULL IV 3.0 1.6 3.0 1.6 ns
T
DHD
(Data Hold Time to WR Signal Inactive) FULL IV 0 0 ns
T
WRLOW
(WR Signal Minimum Low Time) FULL IV 2.5 1.8 2.5 1.8 ns
T
WRHIGH
(WR Signal Minimum High Time) FULL IV 7 7 ns
T
WR
(WR Signal Minimum Period) FULL IV 10.5 10.5 ns
T
ADV
(Address to Data Valid Time) FULL V 15 15 15 15 ns
T
ADHR
(Address Hold Time to RD Signal Inactive) FULL IV 5 5 ns
T
RDLOV
(RD Low-to-Output Valid) FULL IV 15 15 ns
T
RDHOZ
(RD High-to-Data Three-State) FULL IV 10 10 ns
SERIAL I/O TIMING CHARACTERISTICS
T
PRE
(CS Setup Time) FULL IV 30 30 ns
T
SCLK
(Period of Serial Data Clock) FULL IV 100 100 ns
T
DSU
(Serial Data Setup Time) FULL IV 30 30 ns
T
SCLKPWH
(Serial Data Clock Pulsewidth High) FULL IV 40 40 ns
T
SCLKPWL
(Serial Data Clock Pulsewidth Low) FULL IV 40 40 ns
T
DHLD
(Serial Data Hold Time) FULL IV 0 0 ns
T
DV
(Data Valid Time) FULL V 30 30 ns
CMOS LOGIC INPUTS
Logic “1” Voltage 25°C I 2.2 2.2 V
Logic “0” Voltage 25°C I 0.8 0.8 V
Logic “1” Current 25°CIV ±5±12 µA
Logic “0” Current 25°CIV ±5±12 µA
Input Capacitance 25°CV 3 3 pF
REV. A –5–
AD9854
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9854 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Test AD9854ASQ AD9854AST
Parameter Temp Level Min Typ Max Min Typ Max Unit
POWER SUPPLY
6
+V
S
Current
7
25°C I 1050 1210 755 865 mA
+V
S
Current
8
25°C I 710 816 515 585 mA
+V
S
Current
9
25°C I 600 685 435 495 mA
P
DISS7
25°C I 3.475 4.190 2.490 3.000 W
P
DISS8
25°C I 2.345 2.825 1.700 2.025 W
P
DISS9
25°C I 1.975 2.375 1.435 1.715 W
P
DISS
Power-Down Mode 25°CI 1 50 1 50 mW
NOTES
1
The reference clock inputs are configured to accept a 1 V p-p (minimum) dc offset sine wave centered at one-half the applied V
DD
or a 3 V TTL-level pulse input.
2
The I and Q gain imbalance is digitally adjustable to less than 0.01 dB.
3
Change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold.
4
Represents comparator’s inherent cycle-to-cycle jitter contribution. Input signal is a 1 V, 40 MHz square wave. Measurement device Wavecrest DTS – 2075.
5
Comparator input originates from analog output section via external 7-pole elliptic LPF. Single-ended input, 0.5 V p-p. Comparator output terminated in 50 Ω.
6
Simultaneous operation at the maximum ambient temperature of 85°C and the maximum internal clock frequency of 200 MHz for the 80-lead LQFP, or 300 MHz
for the thermally-enhanced 80-lead LQFP may cause the maximum die junction temperature of 150 °C to be exceeded. Refer to the section titled Power Dissipation
and Thermal Considerations for derating and thermal management information.
7
All functions engaged.
8
All functions except inverse sinc engaged.
9
All functions except inverse sinc and digital multipliers engaged.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level
I – 100% Production Tested.
III – Sample Tested Only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – Devices are 100% production tested at 25°C and
guaranteed by design and characterization testing
for industrial operating temperature range.
ABSOLUTE MAXIMUM RATINGS*
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +V
S
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Maximum Clock Frequency (ASQ) . . . . . . . . . . . . . 300 MHz
Maximum Clock Frequency (AST) . . . . . . . . . . . . . 200 MHz
θ
JA
(ASQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16°C/W
θ
JA
(AST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38°C/W
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect device
reliability.
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9854ASQ –40°C to +85°C Thermally-Enhanced 80-Lead LQFP SQ-80
AD9854AST –40°C to +85°C 80-Lead LQFP ST-80
AD9854/PCB 0°C to 70°C Evaluation Board
REV. A
AD9854
–6–
PIN FUNCTION DESCRIPTIONS
Pin
No. Pin Name Function
1–8 D7–D0 Eight-Bit Bidirectional Parallel Programming Data Inputs. Used only in parallel programming mode.
9, 10, 23, DVDD Connections for the Digital Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
24, 25, 73, and DGND.
74, 79, 80
11, 12, 26, DGND Connections for Digital Circuitry Ground Return. Same potential as AGND.
27, 28, 72,
75, 76, 77,
78
13, 35, 57, NC No Internal Connection.
58, 63
14–19 A5–A0 Six-Bit Parallel Address Inputs for Program Registers. Used only in parallel programming mode. A0, A1,
and A2 have a second function when the serial programming mode is selected. See immediately below.
(17) A2/IO RESET Allows a RESET of the serial communications bus that is unresponsive due to improper program-
ming protocol. Resetting the serial bus in this manner does not affect previous programming nor
does it invoke the “default” programming values seen in the Table IV. Active HIGH.
(18) A1/SDO Unidirectional Serial Data Output for Use in 3-Wire Serial Communication Mode.
(19) A0/SDIO Bidirectional Serial Data Input/Output for Use in 2-Wire Serial Communication Mode.
20 I/O UD CLK Bidirectional Frequency Update Signal. Direction is selected in control register. If selected as an input,
a rising edge will transfer the contents of the programming registers to the internal works of the IC for
processing. If I/O UD is selected as an output, an output pulse (low to high) of eight system clock cycle
duration indicates that an internal frequency update has occurred.
21 WRB/SCLK Write Parallel Data to Programming Registers. Shared function with SCLK. Serial clock signal
associated with the serial programming bus. Data is registered on the rising edge. This pin is shared with
WRB when the parallel mode is selected.
22 RDB/CSB Read Parallel Data from Programming Registers. Shared function with CSB. Chip-select signal
associated with the serial programming bus. Active LOW. This pin is shared with RDB when
the parallel mode is selected.
29 FSK/BPSK/ Multifunction Pin According to the Mode of Operation Selected in the Programming Control Register.
HOLD If in the FSK mode logic low selects F1, logic high selects F2. If in the BPSK mode, logic low selects
Phase 1, logic high selects Phase 2. If in the Chirp mode, logic high engages the HOLD function
causing the frequency accumulator to halt at its current location. To resume or commence Chirp,
logic low is asserted.
30 SHAPED Must First Be Selected in the Programming Control Register to Function. A logic high will cause the
KEYING I and Q DAC outputs to ramp-up from zero-scale to full-scale amplitude at a preprogrammed rate.
Logic low causes the full-scale output to ramp-down to zero-scale at the preprogrammed rate.
31, 32, 37, AVDD Connections for the Analog Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
38, 44, 50, and DGND
54, 60, 65
33, 34, 39, AGND Connections for Analog Circuitry Ground Return. Same potential as DGND.
40, 41, 45,
46, 47, 53,
59, 62, 66,
67
36 VOUT Internal High-Speed Comparator’s Noninverted Output Pin. Designed to drive 10 dBm to 50 Ω load
as well as standard CMOS logic levels.
42 VINP Voltage Input Positive. The internal high-speed comparator’s noninverting input.
43 VINN Voltage Input Negative. The internal high-speed comparator’s inverting input.
48 IOUT1 Unipolar Current Output of the I or Cosine DAC.
49 IOUT1B Complementary Unipolar Current Output of the I or Cosine DAC.
51 IOUT2B Complementary Unipolar Current Output of the Q or Sine DAC.
52 IOUT2 Unipolar Current Output of the Q or Sine DAC. This DAC can be programmed to accept
external 12-bit data in lieu of internal sine data. This allows the AD9854 to emulate the AD9852
control DAC function.
REV. A
AD9854
–7–
Pin
No. Pin Name Function
55 DACBP Common Bypass Capacitor Connection for Both I and Q DACs. A 0.01 µF chip cap from this pin to
AVDD improves harmonic distortion and SFDR slightly. No connect is permissible (slight SFDR
degradation).
56 DAC R
SET
Common Connection for Both I and Q DACs to Set the Full-Scale Output Current. R
SET
= 39.9/I
OUT
.
Normal R
SET
range
is from 8 kΩ (5 mA) to 2 kΩ (20 mA).
61 PLL FILTER This pin provides the connection for the external zero compensation network of the REFCLK
Multiplier’s PLL loop filter. The zero compensation network consists of a 1.3 kΩ resistor in series
with a 0.01 µF capacitor. The other side of the network should be connected to AVDD as close as
possible to Pin 60. For optimum phase noise performance, the REFCLK Multiplier can be bypassed
by setting the “Bypass PLL” bit in control register 1E.
64 DIFF CLK Differential REFCLK Enable. A high level of this pin enables the differential clock inputs, REFCLK
ENABLE and REFCLKB (Pins 69 and 68 respectively). The minimum differential signal amplitude required is
800 mV p-p. The centerpoint or common-mode range of the differential signal ranges from 1.6 V
to 1.9 V.
68 REFCLKB The Complementary (180 Degrees Out-of-Phase) Differential Clock Signal. User should tie this pin
high or low when single-ended clock mode is selected. Same signal levels as REFCLK.
69 REFCLK Single-Ended Reference Clock Input or One of Two Differential Clock Signals. Normal 3.3 V CMOS
logic levels or 1 V p-p sine wave centered about 1.6 V.
70 S/P SELECT Selects Between Serial Programming Mode (Logic LOW) and Parallel Programming Mode
(Logic High).
71 MASTER Initializes the serial/parallel programming bus to prepare for user programming; sets programming
RESET registers to a “do-nothing” state defined by the default values seen in the Table V. Active on logic
high. Asserting MASTER RESET is essential for proper operation upon power-up.
REV. A
AD9854
–8–
PIN CONFIGURATION
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD9854
80-LEAD LQFP 14 14 1.4
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
D7
D6
D5
D4
D3
D2
D1
D0
DVDD
DVDD
DGND
DGND
NC
A5
A4
A3
A2/IO RESET
A1/SDO
A0/SDIO
I/O UD CLK
WRB/SCLK
RDB/CSB
DVDD
DVDD
DVDD
DGND
DGND
DGND
FSK/BPSK/HOLD
SHAPED KEYING
AVDD
AVDD
AGND
AGND
NC
VOUT
AVDD
AVDD
AGND
AGND
AGND
VINP
VINN
AVDD
AGND
AGND
AGND
IOUT1
IOUT1B
AVDD
IOUT2B
IOUT2
AGND
AVDD
DACBP
DAC R
SET
NC
NC
AGND
AVDD
PLL FILTER
AGND
NC
DIFF CLK ENABLE
AVDD
AGND
AGND
REFCLKB
REFCLK
S/P SELECT
MASTER RESET
DGND
DVDD
DVDD
DGND
DGND
DGND
DGND
DVDD
DVDD
NC = NO CONNECT
Figure 1. Equivalent Input and Output Circuits
V
DD
I
OUT
I
OUTB
a. DAC Outputs
DIGITAL
OUT
V
DD
b. Comparator Output
V
DD
VINP/
VINN
c. Comparator Input
V
DD
DIGITAL
IN
d. Digital Input
REV. A
AD9854
–9–
Figures 2–7 indicate the wideband harmonic distortion performance of the AD9854 from 19.1 MHz to 119.1 MHz Fundamental
Output, Reference Clock = 30 MHz, REFCLK Multiplier = 10. Each graph plotted from 0 MHz to 150 MHz (Nyquist).
0
START 0Hz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
15MHz/ STOP 150MHz
Figure 2. Wideband SFDR, 19.1 MHz
0
START 0Hz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
15MHz/ STOP 150MHz
Figure 3. Wideband SFDR, 39.1 MHz
0
START 0Hz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
15MHz/ STOP 150MHz
Figure 4. Wideband SFDR, 59.1 MHz
0
START 0Hz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
15MHz/ STOP 150MHz
Figure 5. Wideband SFDR, 79.1 MHz
0
START 0Hz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
15MHz/ STOP 150MHz
Figure 6. Wideband SFDR, 99.1 MHz
0
START 0Hz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
15MHz/ STOP 150MHz
Figure 7. Wideband SFDR, 119.1 MHz
REV. A
AD9854
–10–
Figures 8–11 show the trade-off in elevated noise floor, increased phase noise, and discrete spurious energy when the internal
REFCLK Multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown.
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
100kHz/ SPAN 1MHz
Figure 8. Narrowband SFDR, 39.1 MHz, 1 MHz BW,
300 MHz REFCLK with REFCLK Multiply Bypassed
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/ SPAN 50kHz
Figure 9. Narrowband SFDR, 39.1 MHz, 50 kHz BW,
300 MHz REFCLK with REFCLK Multiplier Bypassed
Compare the noise floor of Figures 9 and 11 to Figures 12 and 13. The improvement seen in Figures 9 and 11 is a direct result
of sampling the fundamental at a higher rate. Sampling at a higher rate spreads the quantization noise of the DAC over a wider
bandwidth, which effectively lowers the noise floor.
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/ SPAN 50kHz
Figure 12. Narrowband SFDR, 39.1 MHz, 50 kHz BW,
100 MHz REFCLK with REFCLK Multiplier Bypassed
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
100kHz/ SPAN 1MHz
Figure 10. Narrowband SFDR, 39.1 MHz, 1 MHz BW,
30 MHz REFCLK with REFCLK Multiply = 10
×
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/ SPAN 50kHz
Figure 11. Narrowband SFDR, 39.1 MHz, 50 kHz BW,
30 MHz REFCLK with REFCLK Multiplier = 10
×
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/ SPAN 50kHz
Figure 13. Narrowband SFDR, 39.1 MHz, 50 kHz BW,
10 MHz REFCLK with REFCLK Multiplier = 10
×
REV. A
AD9854
–11–
Figure 14 represents a tuning word that accentuates the inherent errors due to phase truncation and phase-to-amplitude conversion
in the DDS. Figure 15 is essentially the same output frequency (a few tuning codes over), but it displays much fewer spurs on the output.
0
CENTER 112.499MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
50kHz/ SPAN 500kHz
Figure 14. 112.499 MHz with multiple high energy spurs
close around the fundamental. REFCLK is 300 MHz.
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/ SPAN 50kHz
Figure 16. Narrowband SFDR, 39.1 MHz, 50 kHz BW,
200 MHz REFCLK with REFCLK Multiplier Bypassed
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/ SPAN 50kHz
Figure 17. Narrowband SFDR, 39.1 MHz, 50 kHz BW,
20 MHz REFCLK with REFCLK Multiplier = 10
×
Figures 16 and 17 show the narrowband performance of the AD9854 when operating with a 20 MHz reference clock and the
REFCLK Multiplier enabled at 10× vs. a 200 MHz reference clock with REFCLK Multiplier bypassed.
FREQUENCY – Hz
–110
100
PHASE NOISE – dBc/Hz
–115
–120
–125
–130
–135
–140
–145
–150
–155
1k 10k 100k
AOUT
80MHz
AOUT
5MHz
Figure 18a. Residual Phase Noise, 300 MHz REFCLK with
REFCLK Multiplier Bypassed
FREQUENCY – Hz
–110
100
PHASE NOISE – dBc/Hz
–115
–120
–125
–130
–135
–140
–145
–150
–155
1k 10k 100k
AOUT
80MHz
AOUT
5MHz
Figure 18b. Residual Phase Noise, 30 MHz REFCLK with
REFCLK Multiplier = 10
×
0
CENTER 112.469MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
50kHz/ SPAN 500kHz
Figure 15. A slight change in tuning word yields dramati-
cally better results. 112.469 MHz with all spurs shifted
out-of-band. REFCLK is 300 MHz.
REV. A
AD9854
–12–
DAC CURRENT – mA
55
0
SFDR – dBc
54
53
52
51
50
49
48 510152025
Figure 19. SFDR vs. DAC Current, 59.1 A
OUT
, 300 MHz
REFCLK with REFCLK Multiplier Bypassed
FREQUENCY – MHz
620
0
SUPPLY CURRENT – mA
615
610
605
600
595
590 20 40 60 80 100 120 140
Figure 20. Supply Current vs. Output Frequency; Variation
Is Minimal as a Percentage and Heavily Dependent on
Tuning Word
RISE TIME
1.04ns
500ps/DIV 232mV/DIV 50 INPUT
JITTER
[10.6ps RMS]
–33ps 0ps +33ps
Figure 21. Typical Comparator Output Jitter, 40 MHz A
OUT
,
300 MHz REFCLK with REFCLK Multiplier Bypassed
REF1 RISE
1.174ns
C1 FALL
1.286ns
CH1 500mVM 500
p
s CH1 980mV
Figure 22. Comparator Rise/Fall Times
FREQUENCY – MHz
1200
0
AMPLITUDE – mV p-p
1000
800
600
400
200
0100 200 300 400 500
MINIMUM COMPARATOR
INPUT DRIVE
V
CM
= 0.5V
Figure 23. Comparator Toggle Voltage Requirement
REV. A
AD9854
–13–
50
BANDPASS
FILTER
50
IOUT
AD9854
FUNDAMENTAL
FC – FO
IMAGE
FCLK
FC + FO
IMAGE
BANDPASS
FILTER
FC + FO
IMAGE
AD9854
SPECTRUM
FINAL OUTPUT
SPECTRUM
AMPLIFIER
Figure 26. Using an Aliased Image to Generate a High
Frequency
LPF
REFCLK
RF/IF
INPUT
I BASEBAND
COS
LPF
LPF
AD9854
Q BASEBANDLPF
CHANNEL
SELECT
FILTERS
SIN
a. Quadrature Downconversion
LPF
REFCLK
COS
LPF
AD9854
SIN
RF OUTPUT
I BASEBAND
Q BASEBAND
b. Direct Conversion Quadrature Upconverter
Figure 24. Quadrature Up/Down Conversion Applications for the AD9854
I
Q
Rx
RF IN
DUAL
8-/10-BIT
ADC
DIGITAL
DEMODULATOR
Rx BASEBAND
DIGITAL DATA
OUT
8
8
I/Q MIXER
AND
LOW-PASS
FILTER
VCA
ADC ENCODE
ADC CLOCK FREQUENCY
LOCKED TO Tx CHIP/
SYMBOL/PN RATE
REFERENCE
CLOCK
48
CHIP/SYMBOL/PN
RATE DATA
AD9854
CLOCK
GENERATOR
AGC
Figure 25. Chip Rate Generator in Spread Spectrum Application
TYPICAL APPLICATIONS
VCO
LOOP
FILTER
PHASE
COMPARATOR
REFERENCE
CLOCK
FILTER
AD9854
DDS
TUNING
WORD
REF CLK IN
RF
FREQUENCY
OUT
DAC OUT
PROGRAMMABLE
"DIVIDE-BY-N" FUNCTION
(WHERE N = 248/TUNING WORD)
Figure 27. Programmable “Fractional Divide-by-N”
Synthesizer
REV. A
AD9854
–14–
REFERENCE
CLOCK
50
1:1 TRANSFORMER
I.E, MINI-CIRCUITS T1–1T
FILTER
50
DIFFERENTIAL
TRANSFORMER-COUPLED
OUTPUT
AD9854
DDS
IOUT
IOUT
Figure 29a. Differential Output Connection for Reduction of Common-Mode Signals
CLOCK OUT = 200MHz
LPF SIN
LPF
AD9854
COS
REFERENCE
CLOCK
COMPARATORS
A
OUT
= 100MHz
Figure 29b. Clock Frequency Doubler
PROCESSOR/
CONTROLLER
FPGA, ETC.
R
SET
8-BIT PARALLEL OR
SERIAL PROGRAMMING
DATA AND CONTROL
SIGNALS
AD9854
+
CMOS LOGIC "CLOCK" OUT
REFERENCE
CLOCK
300MHz MAX DIRECT
MODE OR 15 TO 75MHz
MAX IN THE 4–20
CLOCK
MULTIPLIER MODE
2k
"I" DAC
1
2
NOTES:
I
OUT
= APPROX 20mA MAX WHEN R
SET
= 2k
SWITCH POSTION 1 PROVIDES COMPLEMENTARY
SINUSOIDAL SIGNALS TO THE COMPARATOR
TO PRODUCE A FIXED 50% DUTY CYCLE FROM
THE COMPARATOR.
SWITCH POSTION 2 PROVIDES THE SAME DUTY CYCLE
USING QUADRATURE SINUSOIDAL SIGNALS TO THE
COMPARATOR OR A DC THRESHOLD VOLTAGE TO
ALLOW SETTING OF THE COMPARATOR DUTY CYCLE
(DEPENDS ON THE "Q" DAC's CONFIGURATION)
"Q" DAC OR
"CONTROL
DAC"
LOW-PASS
FILTER
LOW-PASS
FILTER
Figure 30. Frequency Agile Clock Generator Applications for the AD9854
TUNING
WORD
VCO
LOOP
FILTER
PHASE
COMPARATOR
REF
CLOCK RF
FREQUENCY
OUT
FILTER
AD9854
DDS
DIVIDE-BY-N
Figure 28a. Agile High-Frequency Synthesizer
PHASE
SPLITTER
0.8 TO
2.5 GHz
AD9854
QUADRATURE
DDS
DDS – LO LO DDS
+ LO
36dB
TYPICAL
SSB
REJECTION 50
V
OUT
AD8346 QUADRATURE
MODULATOR
90
COSINE (DC TO 70MHz)
SINE (DC TO 70MHz)
NOTES:
FLIP DDS QUADRATURE SIGNALS TO SELECT ALTERNATE SIDEBAND. ADJUST DDS
SINE OR COSINE SIGNAL AMPLITUDE FOR GREATEST SIDEBAND SUPPRESSION.
DDS DAC OUTPUTS MUST BE LOW-PASS FILTERED PRIOR TO USE WITH THE AD8346.
(
NOTE: REFER TO THE TECHNICAL NOTE AT WEBSITE
[
WWW.ANALOG.COM/DDS
])
LO
LO
0
Figure 28b. Single-Sideband Upconversion
REV. A
AD9854
–15–
(continued from page 1)
simultaneous quadrature output signals at frequencies up to
150 MHz, which can be digitally tuned at a rate of up to 100
million new frequencies per second. The (externally filtered) sine
wave output can be converted to a square wave by the internal
comparator for agile clock generator applications. The device pro-
vides two 14-bit phase registers and a single pin for BPSK
operation. For higher order PSK operation, the user may use the
I/O Interface for phase changes. The 12-bit I and Q DACs,
coupled with the innovative DDS architecture, provide excel-
lent wide-band and narrow-band output SFDR. The Q-DAC
can also be configured as a user-programmable control DAC
if the quadrature function is not desired. When configured with
the comparator, the 12-bit control DAC facilitates static duty cycle
control in the high-speed clock generator applications. Two 12-
bit digital multipliers permit programmable amplitude modulation,
shaped on/off keying and precise amplitude control of the quadra-
ture output. Chirp functionality is also included which facilitates
wide bandwidth frequency sweeping applications. The AD9854’s
programmable 4×–20× REFCLK multiplier circuit generates
the 300 MHz system clock internally from a lower frequency exter-
nal reference clock. This saves the user the expense and difficulty
of implementing a 300 MHz system clock source. Direct 300 MHz
clocking is also accommodated with either single- ended or differ-
ential inputs. Single-pin conventional FSK and the enhanced
spectral qualities of “ramped” FSK are supported. The AD9854
uses advanced 0.35 micron CMOS technology to provide this
high level of functionality on a single 3.3 V supply.
The AD9854 is available in a space-saving 80-lead LQFP
surface mount package and a thermally-enhanced 80-lead LQFP
package. The AD9854 is pin-for-pin compatible with the AD9852
single-tone synthesizer. It is specified to operate over the extended
industrial temperature range of –40°C to +85°C.
OVERVIEW
The AD9854 quadrature output digital synthesizer is a highly
flexible device that will address a wide range of applications.
The device consists of an NCO with 48-bit phase accumulator,
programmable reference clock multiplier, inverse sinc filters,
digital multipliers, two 12-bit/300 MHz DACs, high-speed
analog comparator, and interface logic. This highly integrated
device can be configured to serve as a synthesized LO, agile clock
generator, and FSK/BPSK modulator. The theory of operation of
the functional blocks of the device, and a technical description
of the signal flow through a DDS device, can be found in a
tutorial from Analog Devices called “A Technical Tutorial on
Digital Signal Synthesis.” This tutorial is available on CD-ROM
and information on obtaining it can be found at the Analog
Devices DDS website at www.analog.com/dds. The tutorial
also provides basic applications information for a variety of
digital synthesis implementations. The DDS background subject
matter is not covered in this data sheet; the functions and features
of the AD9854 will be individually discussed herein.
DESCRIPTION OF AD9854 MODES OF OPERATION
There are five programmable modes of operation of the AD9854.
Selecting a mode requires that three bits in the Control Register
(parallel address 1F hex) be programmed as follows in Table I.
Table I. Mode Selection Table
Mode 2 Mode 1 Mode 0 Result
0 0 0 SINGLE-TONE
0 0 1 FSK
0 1 0 RAMPED FSK
0 1 1 CHIRP
1 0 0 BPSK
In each mode, engaging certain functions may not be permitted.
Shown in Table II is a listing of some important functions and
their availability for each mode.
Single-Tone (Mode 000)
This is the default mode when master reset is asserted. It may also
be accessed by being user-programmed into the control register.
The Phase Accumulator, responsible for generating an output
frequency, is presented with a 48-bit value from Frequency Tuning
Word 1 registers whose default values are zero. Default values from
the remaining applicable registers will further define the single-tone
output signal qualities.
The default values after a master reset configure the device with an
output signal of 0 Hertz, 0 phase. Upon power-up and reset
the output from both I and Q DACs will be a dc value equal to the
midscale output current. This is the default mode amplitude
setting of zero. Refer to the digital multiplier section for further
explanation of the output amplitude control. It will be neces-
sary to program all or some of the 28 program registers to realize a
user-defined output signal.
Figure 31 graphically shows the transition from the default con-
dition (0 Hz) to a user defined output frequency (F1).
000 (SINGLE TONE)
MODE
F1
TW1
000 (DEFAULT)
0
F1
0
FREQUENCY
MASTER RESET
Figure 31. Default State to User-Defined Output Transition
REV. A
AD9854
–16–
Table II. Function Availability vs. Mode of Operation
Single-Pin Single-Pin Phase Amplitude Inverse Frequency Frequency Automatic
Phase Phase FSK/BPSK Shaped- Offset or Control or SINC Tuning Tuning Frequency
Mode Adjust 1 Adjust 2 or HOLD Keying Modulation Modulation Filter Word 1 Word 2 Sweep
Single-Tone ✓XX ✓✓ ✓ ✓✓XX
FSK ✓X✓✓ ✓ ✓ ✓✓✓X
Ramped FSK ✓X✓✓ ✓ ✓ ✓✓✓✓
CHIRP ✓X✓✓ ✓ ✓ ✓✓X✓
BPSK ✓✓✓ ✓ X✓✓✓XX
As with all Analog Devices DDSs, the value of the frequency
tuning word is determined using the following equation:
FTW = (Desired Output Frequency × 2
N
)/SYSCLK.
Where N is the phase accumulator resolution (48 bits in this
instance), frequency is expressed in Hertz, and the FTW, Fre-
quency Tuning Word, is a decimal number. Once a decimal
number has been calculated, it must be rounded to an integer
and then converted to binary format—a series of 48 binary-
weighted 1s or 0s. The fundamental sine wave DAC output
frequency range is from dc to 1/2 SYSCLK.
Changes in frequency are phase-continuous, which means that the
first sampled phase value of the new frequency will be referenced in
time from the last sampled phase value of the previous frequency.
The I and Q DACs of the AD9854 are always 90 degrees out-
of-phase. The 14-bit phase registers (discussed elsewhere in this
data sheet) do not independently adjust the phase of each DAC
output. Instead, both DAC’s are affected equally by a change in
phase offset.
The single-tone mode allows the user to control the following
signal qualities:
• Output Frequency to 48-Bit Accuracy
• Output Amplitude to 12-Bit Accuracy
– Fixed, User-Defined, Amplitude Control
– Variable, Programmable Amplitude Control
– Automatic, Programmable, Single-Pin-Controlled, “Shaped
On/Off Keying”
• Output Phase to 14-Bit Accuracy
Furthermore, all of these qualities can be changed or modulated
via the 8-bit parallel programming port at a 100 MHz parallel-byte
rate, or at a 10 MHz serial rate. Incorporating this attribute will
permit FM, AM, PM, FSK, PSK, ASK operation in the single-
tone mode.
Unramped FSK (Mode 001)
When selected, the output frequency of the DDS is a function
of the values loaded into Frequency Tuning Word registers 1
and 2 and the logic level of Pin 29 (FSK/BPSK/HOLD). A logic
low on Pin 29 chooses F1 (frequency tuning word 1, parallel
address 4–9 hex) and a logic high chooses F2 (frequency tuning
word 2, parallel register address A–F hex). Changes in frequency
are phase-continuous and are internally coincident with the
FSK data pin (29); however, there is deterministic pipeline delay
between the FSK data signal and the DAC Output. (Please
refer to pipeline delays in specification table.)
The unramped FSK mode, Figure 32, is representative of
traditional FSK, RTTY (Radio Teletype) or TTY (Teletype)
transmission of digital data. FSK is a very reliable means of
digital communication; however, it makes inefficient use of the
bandwidth in the RF Spectrum. Ramped FSK in Figure 33 is a
method of conserving the bandwidth.
Ramped FSK (Mode 010)
A method of FSK whereby changes from F1 to F2 are not
instantaneous but, instead, are accomplished in a frequency
sweep or “ramped” fashion. The “ramped” notation implies
that the sweep is linear. While linear sweeping or frequency
ramping is easily and automatically accomplished, it is only one
of many possibilities. Other frequency transition schemes may
F1
F2
0
FREQUENCY
MODE
TW1
TW2
FSK DATA (PIN 29)
001 (FSK NO RAMP)
F1
F2
000 (DEFAULT)
0
0
I/O UPDATE CLK
Figure 32. Traditional FSK Mode
REV. A
AD9854
–17–
be implemented by changing the ramp rate and ramp step size
“on-the-fly,” in piecewise fashion.
Frequency ramping, whether linear or nonlinear, necessitates
that many intermediate frequencies between F1 and F2 will be
output in addition to the primary F1 and F2 frequencies. Figures
33 and 34 graphically depict the frequency versus time charac-
teristics of a linear ramped FSK signal.
NOTE: In ramped FSK mode, the Delta Frequency (DFW)
is required to be programmed as a positive two’s comple-
ment value. Another requirement is that the lowest
frequency (F1) be programmed in the Frequency Tun-
ing Word 1 register.
The purpose of ramped FSK is to provide better bandwidth
containment than traditional FSK by replacing the instantaneous
frequency changes with more gradual, user-defined frequency
changes. The dwell time at F1 and F2 can be equal to or much
greater than the time spent at each intermediate frequency. The
I/O UPDATE CLK
F1
F2
0
FREQUENCY
MODE
TW1
TW2
010 (RAMPED FSK)
F1
F2
000 (DEFAULT)
0
0
REQUIRES A POSITIVE TWO'S COMPLEMENT VALUE
RAMP RATE
DFW
FSK DATA (PIN 29)
Figure 33. Ramped FSK Mode
F1
F2
0
FREQUENCY
MODE
TW1
TW2
FSK DATA
010 (RAMPED FSK)
F1
F2
000 (DEFAULT)
0
0
I/O UPDATE
CLOCK
Figure 34. Ramped FSK Mode
user controls the dwell time at F1 and F2, the number of inter-
mediate frequencies and time spent at each frequency. Unlike
unramped FSK, ramped FSK requires the lowest frequency to be
loaded into F1 registers and the highest frequency into F2 registers.
Several registers must be programmed to instruct the DDS
regarding the resolution of intermediate frequency steps (48
bits) and the time spent at each step (20 bits). Furthermore, the
CLR ACC1 bit in the control register should be toggled (low-high-
low) prior to operation to assure that the frequency accumulator
is starting from an “all zeros” output condition. For piecewise,
nonlinear frequency transitions, it is necessary to reprogram the
registers while the frequency transition is in progress to affect the
desired response.
Parallel register addresses 1A–1C hex comprise the 20-bit “Ramp
Rate Clock” registers. This is a countdown counter that outputs
a single pulse whenever the count reaches zero. The counter
is activated any time a logic level change occurs on FSK input
REV. A
AD9854
–18–
Pin 29. This counter is run at the System Clock Rate, 300 MHz
maximum. The time period between each output pulse is given as
(N+1) × (SYSTEM CLOCK PERIOD)
where N is the 20-bit ramp rate clock value programmed by the
user. Allowable range of N is from 1 to (2
20
–1). The output of
this counter clocks the 48-bit Frequency Accumulator shown
below in Figure 35. The Ramp Rate Clock determines the amount
of time spent at each intermediate frequency between F1 and F2.
The counter stops automatically when the destination frequency
is achieved. The “dwell time” spent at F1 and F2 is determined
by the duration that the FSK input, Pin 29, is held high or low
after the destination frequency has been reached.
FREQUENCY
TUNING
WORD 2
FREQUENCY
TUNING
WORD 1
20-BIT
RAMP RATE
CLOCK
48-BIT DELTA-
FREQUENCY
WORD (TWO'S
COMPLEMENT)
FREQUENCY
ACCUMULATOR
PHASE
ACCUMULATOR
INSTANTANEOUS
PHASE OUT
ADDER
FSK (PIN 29)
SYSTEM
CLOCK
Figure 35. Block Diagram of Ramped FSK Function
Parallel register addresses 10–15 hex comprise the 48-bit, two’s
complement, “Delta Frequency Word” registers. This 48-bit
word is accumulated (added to the accumulator’s output) every
time it receives a clock pulse from the ramp rate counter. The
output of this accumulator is then added to or subtracted from
the F1 or F2 frequency word, which is then fed to the input of the
48-bit Phase Accumulator that forms the numerical phase steps
for the sine and cosine wave outputs. In this fashion, the output
frequency is ramped up and down in frequency, according to
the logic-state of Pin 29. The rate at which this happens is a
function of the 20-bit ramp rate clock. Once the destination
frequency is achieved, the ramp rate clock is stopped, which halts
the frequency accumulation process.
Generally speaking, the Delta Frequency Word will be a much
smaller value compared to that of the F1 or F2 tuning word.
For example, if F1 and F2 are 1 kHz apart at 13 MHz, the
Delta Frequency Word might be only 25 Hz.
F1
F2
0
FREQUENCY
MODE
TW1
TW2
FSK DATA
TRIANGLE
BIT
010 (RAMPED FSK)
F1
F2
I/O UPDATE
CLOCK
Figure 36. Effect of Triangle Bit in Ramped FSK Mode
Figure 37 shows that premature toggling causes the ramp to
immediately reverse itself and proceed at the same rate and resolu-
tion back to originating frequency.
The control register contains a Triangle bit at parallel register
address 1F hex. Setting this bit high in Mode 010 causes an
automatic ramp-up and ramp-down between F1 and F2 to occur
without having to toggle Pin 29 as shown in Figure 36. In fact, the
logic state of Pin 29 has no effect once the Triangle bit is set high.
This function uses the ramp-rate clock time period and the
F1
F2
0
FREQUENCY
MODE
TW1
TW2
FSK DATA
F1
F2
000 (DEFAULT)
0
0
010 (RAMPED FSK)
I/O UPDATE
CLOCK
Figure 37. Effect of Premature Ramped FSK Data
REV. A
AD9854
–19–
delta-frequency-word step size to form a continuously sweeping
linear ramp from F1 to F2 and back to F1 with equal dwell times
at every frequency. Using this function, one can automatically
sweep between any two frequencies from dc to Nyquist.
In the Ramped FSK mode, with the triangle bit set high, an
automatic frequency sweep will begin at either F1 or F2,
according to the logic level on Pin 29 (FSK input pin) when the
triangle bit’s rising edge occurs as shown in Figure 38. If the
FSK data bit had been high instead of low, F2, rather than F1,
would have been chosen as the start frequency.
Additional flexibility in the ramped FSK mode is provided in
the ability to respond to changes in the 48-bit delta frequency
word and/or the 20-bit ramp-rate counter on-the-fly during the
F2
F1
0
FREQUENCY
MODE
TW1
TW2
FSK DATA
TRIANGLE BIT
000 (DEFAULT)
0
0
010 (RAMPED FSK)
F1
F2
Figure 38. Automatic Linear Ramping Using the
Triangle Bit
ramping from F1 to F2 or vice versa. To create these nonlinear
frequency changes it is necessary to combine several linear ramps,
in a piecewise fashion, with differing slopes. This is done by
programming and executing a linear ramp at some rate or “slope”
and then altering the slope (by changing the ramp rate clock or
delta frequency word or both). Changes in slope are made as often
as needed to form the desired nonlinear frequency sweep response
before the destination frequency has been reached. These piecewise
changes can be precisely timed using the 32-bit Internal Update
Clock (see detailed description of Update Clock in this data
sheet).
Nonlinear ramped FSK will have the appearance of a chirp
function that is graphically illustrated in Figure 39. The major
difference between a ramped FSK function and a chirp function
is that FSK is limited to operation between F1 and F2. Chirp
operation has no F2 limit frequency.
Two additional control bits are available in the ramped FSK mode
that allow even more options. CLR ACC1, register address 1F hex,
will, if set high, clear the 48-bit frequency accumulator (ACC1)
output with a retriggerable one-shot pulse of one system clock
duration. If the CLR ACC1 bit is left high, a one-shot pulse will
be delivered on the rising edge of every Update Clock. The effect
is to interrupt the current ramp, reset the frequency back to the
start point, F1 or F2, and then continue to ramp up (or down)
at the previous rate. This will occur even when a static F1 or F2
destination frequency has been achieved.
Next, CLR ACC2 control bit (register address 1F hex) is avail-
able to clear both the frequency accumulator (ACC1) and the phase
accumulator (ACC2). When this bit is set high, the output of the
phase accumulator will result in 0 Hz output from the DDS. As
long as this bit is set high, the frequency and phase accumulators
will be cleared, resulting in 0 Hz output. To return to previous
DDS operation, CLR ACC2 must be set to logic low.
Chirp (Mode 011)
This mode is also known as pulsed FM. Most chirp systems use
a linear FM sweep pattern, but the AD9854 supports nonlinear
patterns, as well. In radar applications, use of chirp or pulsed
FM allows operators to significantly reduce the output power
needed to achieve the same result as a single-frequency radar
system would produce. Figure 39 represents a very low-resolution
nonlinear chirp meant to demonstrate the different “slopes” that
are created by varying the time steps (ramp rate) and frequency
steps (delta frequency word).
The AD9854 permits precise, internally generated linear or exter-
nally programmed nonlinear pulsed or continuous FM over the
complete frequency range, duration, frequency resolution
and sweep direction(s). These are all user programmable. A block
diagram of the FM chirp components is shown in Figure 40.
F1
0
FREQUENCY
010 (RAMPED FSK)
F1
000 (DEFAULT)
0
MODE
TW1
DFW
RAMP RATE
I/O UPDATE
CLOCK
Figure 39. Example of a Nonlinear Chirp
REV. A
AD9854
–20–
20-BIT
RAMP RATE
CLOCK
48-BIT DELTA-
FREQUENCY
WORD (TWO'S
COMPLEMENT)
FREQUENCY
ACCUMULATOR
PHASE
ACCUMULATOR
OUT
ADDER
SYSTEM
CLOCK
CLR ACC2
CLR ACC1
FREQUENCY
TUNING
WORD 1
HOLD
Figure 40. FM Chirp Components
Basic FM Chirp Programming Steps
1. Program a start frequency into Frequency Tuning Word 1
(parallel register addresses 4–9 hex) hereafter called FTW1.
2. Program the frequency step resolution into the 48-bit, two’s
complement, Delta Frequency Word (parallel register addresses
10–15 hex).
3. Program the rate of change (time at each frequency) into the
20-bit Ramp Rate Clock (parallel register addresses 1A–1C
hex).
4. When programming is complete, an I/O update pulse at Pin
20 will engage the program commands.
The necessity for a two’s complement Delta Frequency Word is
to define the direction in which the FM chirp will move. If the
48-bit delta frequency word is negative (MSB is high) then the
incremental frequency changes will be in a negative direction
from FTW1. If the 48-bit word is positive (MSB is low) then
the incremental frequency changes will be in a positive direction.
It is important to note that FTW1 is only a starting point for
FM chirp. There is no built-in restraint requiring a return to
FTW1. Once the FM chirp has begun it is free to move (under
program control) within the Nyquist bandwidth (dc to 1/2 system
I/O UPDATE
CLOCK
F1
0
FREQUENCY
MODE
FTW1
DFW
F1
000 (DEFAULT)
0
RAMP RATE RAMP RATE
011 (CHIRP)
DELTA FREQUENCY WORD
CLR ACC1
Figure 41. Effect of CLR ACC1 in FM Chirp Mode
clock). Instant return to FTW1 is easily achieved, though, and this
option is explained in the next few paragraphs.
Two control bits are available in the FM Chirp mode that will
allow the return to the beginning frequency, FTW1, or to 0 Hz.
First, when the CLR ACC1 bit (register address 1F hex) is set
high, the 48-bit frequency accumulator (ACC1) output is cleared with
a retriggerable one-shot pulse of one system clock duration.
The 48-bit Delta Frequency Word input to the accumulator is
unaffected by CLR ACC1 bit. If the CLR ACC1 bit is held high, a
one-shot pulse will be delivered to the Frequency Accumulator
(ACC1) on every rising edge of the I/O Update Clock. The effect
is to interrupt the current chirp, reset the frequency back to FTW1,
and continue the chirp at the previously programmed rate and
direction. Clearing the output of the Frequency Accumulator
in the chirp mode is illustrated in Figure 41. Shown in the diagram
is the I/O Update Clock, which is either user-supplied or internally
generated. A discussion of I/O Update is presented elsewhere
in this data sheet.
Next, CLR ACC2 control bit (register address 1F hex) is available
to clear both the frequency accumulator (ACC1) and the phase
accumulator (ACC2). When this bit is set high, the output of the
phase accumulator will result in 0 Hz output from the DDS. As
long as this bit is set high, the frequency and phase accumulators
will be cleared, resulting in 0 Hz output. To return to previous
DDS operation, CLR ACC2 must be set to logic low. This bit is
useful in generating pulsed FM.
Figure 42 graphically illustrates the effect of CLR ACC2 bit upon
the DDS output frequency. Note that reprogramming the registers
while the CLR ACC2 bit is high allows a new FTW1 frequency
and slope to be loaded.
Another function that is available only in the chirp mode is the
HOLD pin, Pin 29. This function will stop the clock signal to the
ramp rate counter, thereby halting any further clocking pulses to
the frequency accumulator, ACC1. The effect is to halt the
chirp at the frequency existing just before HOLD was pulled
high. When the HOLD pin is returned low, the clocks are resumed
and chirp continues. During a hold condition, the user may
change the programming registers; however, the ramp rate counter
REV. A
AD9854
–21–
CLR ACC2
F1
0
FREQUENCY
MODE
TW1
DPW
000 (DEFAULT)
0
RAMP RATE
011 (CHIRP)
I/O UPDATE
CLOCK
Figure 42. Effect of CLR ACC2 in FM Chirp Mode
HOLD
F1
0
FREQUENCY
MODE
TW1
DFW
000 (DEFAULT)
0
RAMP RATE
011 (CHIRP)
F1
DELTA FREQUENCY WORD
RAMP RATE
I/O UPDATE
CLOCK
Figure 43. Illustration of HOLD Function
must resume operation at its previous rate until a count of zero is
obtained before a new ramp rate count can be loaded. Figure 43
illustrates the effect of the hold function on the DDS output
frequency.
The 32-bit automatic I/O Update counter may be used to con-
struct complex chirp or ramped FSK sequences. Since this internal
counter is synchronized with the AD9854 System Clock, it allows
precisely timed program changes to be invoked. In this manner,
the user is only required to reprogram the desired registers before
the automatic I/O Update Clock is generated.
In the chirp mode, the destination frequency is not directly
specified. If the user fails to control the chirp, the DDS will natu-
rally confine itself to the frequency range between dc and Nyquist.
Unless terminated by the user, the chirp will continue until power
is removed.
When the chirp destination frequency is reached there are several
possible outcomes:
1. Stop at the destination frequency using the HOLD pin, or by
loading all zeros into the Delta Frequency Word registers of
the frequency accumulator (ACC1).
2. Use the HOLD pin function to stop the chirp, then ramp-down
the output amplitude using the digital multiplier stages and
the Shaped Keying pin, Pin 30, or via program register control
(addresses 21–24 hex).
3. Abruptly terminate the transmission using the CLR ACC2 bit.
4. Continue chirp by reversing direction and returning to the
previous, or another, destination frequency in a linear or user-
directed manner. If this involves going down in frequency, a
negative 48-bit Delta Frequency Word (the MSB is set to “1”)
must be loaded into registers 10–15 hex. Any decreasing
REV. A
AD9854
–22–
BPSK DATA
360
0
PHASE
MODE
FTW1
PHASE ADJUST 1
000 (DEFAULT)
0
PHASE ADJUST 2
100 (BPSK)
F1
270 DEGREES
90 DEGREES
I/O UPDATE
CLOCK
Figure 44. BPSK Mode
frequency step of the Delta Frequency Word requires the
MSB to be set to logic high.
5. Continue chirp by immediately returning to the beginning
frequency (F1) in a sawtooth fashion and repeat the previ-
ous chirp process. This is where CLR ACC1 control bit is used.
An automatic, repeating chirp can be set up using the 32-bit
Update Clock to issue CLR ACC1 command at precise time
intervals. Adjusting the timing intervals or changing the Delta
Frequency Word will change the chirp range. It is incumbent
upon the user to balance the chirp duration and frequency
resolution to achieve the proper frequency range.
BPSK (Mode 100)
Binary, biphase or bipolar phase shift keying is a means to rapidly
select between two preprogrammed 14-bit output phase offsets
that will identically affect both the I and Q outputs of the AD9854.
The logic-state of Pin 29, BPSK pin, controls the selection of
Phase Adjust register number 1 or 2. When low, Pin 29 selects
Phase Adjust register 1; when high, Phase Adjust register 2 is
selected. Figure 44 illustrates phase changes made to four cycles
of an output carrier.
Basic BPSK programming steps:
1. Program a carrier frequency into Frequency Tuning Word 1.
2. Program appropriate 14-bit phase words in Phase Adjust
registers 1 and 2.
3. Attach BPSK data source to Pin 29.
4. Activate I/O Update Clock when ready.
NOTE: If higher order PSK modulation is desired, the user should
select the Single Tone mode and program Phase Adjust register 1
using the serial or high-speed parallel programming bus.
USING THE AD9854
Internal and External Update Clock
This function is comprised of a bidirectional I/O pin, Pin 20, and a
programmable 32-bit down-counter. In order for programming
changes to be transferred from the I/O Buffer registers to the active
core of the DDS, a clock signal (low to high edge) must be externally
supplied to Pin 20 or internally generated by the 32-bit Update Clock.
When the user provides an external Update Clock, it is internally
synchronized with the system clock to prevent partial transfer
of program register information due to violation of data setup
or hold times. This mode gives the user complete control of
when updated program information becomes effective. The
default mode for Update Clock is internal (Int Update Clk control
register bit is logic high). To switch to External Update Clock
mode, the Int Update Clk register bit must be set to logic low.
The internal update mode generates automatic, periodic update
pulses with the time period set by the user.
An internally generated Update Clock can be established by
programming the 32-bit Update Clock registers (address 16–19
hex) and setting the Int Update Clk (address 1F hex) control
register bit to logic high. The update clock down-counter function
operates at 1/2 the rate of the system clock (150 MHz maximum)
and counts down from a 32-bit binary value (programmed by
the user). When the count reaches 0, an automatic I/O Update of
the DDS output or functions is generated. The update clock is
internally and externally routed on Pin 20 to allow users to syn-
chronize programming of update information with the update
clock rate. The time period between update pulses is given as:
(N+1) × (SYSTEM CLOCK PERIOD × 2)
where N is the 32-bit value programmed by the user. Allow-
able range of N is from 1 to (2
32
–1). The internally generated
update pulse output on Pin 20 has a fixed high time of eight system
clock cycles.
Programming the Update Clock register for values less than five
will cause the I/O UD pin to remain high. The update clock func-
tionality still works, its just that the user cannot use the signal as
an indication that data is transferring. This is an affect of the
minimum high pulse time when I/O UD is an output.
Shaped On/Off Keying
This feature allows the user to control the amplitude vs. time slope
of the I and Q DAC output signals. This function is used in “burst
transmissions” of digital data to reduce the adverse spectral impact
of short, abrupt bursts of data. Users must first enable the digi-
tal multipliers by setting the OSK EN bit (control register address
20 hex) to logic high in the control register.
REV. A
AD9854
–23–
Otherwise, if the OSK EN bit is set low, the digital multipliers
responsible for amplitude-control are bypassed and the I and Q
DAC outputs are set to full-scale amplitude. In addition to set-
ting the OSK EN bit, a second control bit, OSK INT (also at
address 20 hex), must be set to logic high. Logic high selects the
linear internal control of the output ramp-up or ramp-down
function. A logic low in the OSK INT bit switches control of
the digital multipliers to user programmable 12-bit registers
allowing users to dynamically shape the amplitude transition in
practically any fashion. These 12-bit registers, labeled “Output
Shape Key I and Output Shape Key Q,” are located at addresses
21 through 24 hex in Table IV. The maximum output amplitude is
a function of the R
SET
resistor and is not programmable when
OSK INT is enabled.
ABRUPT ON/OFF KEYING
SHAPED ON/OFF KEYING
ZERO
SCALE
ZERO
SCALE
FULL
SCALE
FULL
SCALE
Figure 45. Shaped On/Off Keying
The transition time from zero-scale to full-scale must also be
programmed. The transition time is a function of two fixed ele-
ments and one variable. The variable element is the programmable
8-bit RAMP RATE COUNTER. This is a down-counter that is
clocked at the system clock rate (300 MHz max) and generates one
pulse whenever the counter reaches zero. This pulse is routed to
a 12-bit counter that increments with each pulse received. The
outputs of the 12-bit counter are connected to the 12-bit digital
multiplier. When the digital multiplier has a value of all zeros at
its inputs, the input signal is multiplied by zero, producing zero-
scale. When the multiplier has a value of all ones, the input signal
is multiplied by a value of 4095/4096, producing nearly full-
scale. There are 4094 remaining fractional multiplier values
that will produce output amplitudes scaled according to their
binary values.
12-BIT DIGITAL
MULTIPLIER
12 12
(BYPASS MULTIPLIER)
OSK EN = 0
OSK EN = 1
OSK EN = 0
OSK EN = 1
12
12
DIGITAL
SIGNAL IN
USER-PROGRAMMABLE
12-BIT Q-CHANNEL
MULTIPLIER
"OUTPUT SHAPE
KEY Q MULT"
REGISTER
12 OSK INT = 1
OSK INT = 0
18-BIT RAMP
RATE
COUNTER
SYSTEM
CLOCK
SHAPED ON/OFF
KEYING PIN
SINE DAC
12-BIT
UP/DOWN
COUNTER
DDS DIGITAL
OUTPUT
Figure 46. Block diagram of Q-pathway of the digital multiplier section responsible for Shaped Keying function.
The two fixed elements of the transition time are the period of
the system clock (which drives the Ramp Rate Counter) and the
number of amplitude steps (4096). To give an example, assume
that the System Clock of the AD9854 is 100 MHz (10 ns period).
If the Ramp Rate Counter is programmed for a minimum count of
three, it will take two system clock periods (one rising edge
loads the count-down value, the next edge decrements the counter
from three to two). If the count down value is less than three, the
Ramp Rate Counter will stall and, therefore, produce a con-
stant scaling value to the digital multipliers. This stall condition
may have application to the user. The relationship of the 8-bit
count-down value to the time period between output pulses is
given as:
(N+1) × SYSTEM CLOCK PERIOD,
where N is the 8-bit count-down value. It will take 4096 of these
pulses to advance the 12-bit up-counter from zero-scale to full-
scale. Therefore, the minimum shaped keying ramp time for a
100 MHz system clock is 4096 × 4 × 10 ns = approximately 164 µs.
The maximum ramp time will be 4096 × 256 × 10 ns = approxi-
mately 10.5 ms.
Finally, changing the logic state of Pin 30, “shaped keying” will
automatically perform the programmed output envelope functions
when OSK INT is high. A logic high on Pin 30 causes the out-
puts to linearly ramp up to full-scale amplitude and hold until
the logic level is changed to low, causing the outputs to ramp
down to zero-scale.
I and Q DACs
The sine and cosine outputs of the DDS drive the Q and I DACs,
respectively (300 MSPS maximum). Their maximum output
amplitudes are set by the DAC R
SET
resistor at Pin 56. These are
current-out DACs with a full-scale maximum output of 20 mA;
however, a nominal 10 mA output current provides best spurious-
free dynamic range (SFDR) performance. The value of R
SET
= 39.93/I
OUT
, where I
OUT
is in amps. DAC output compliance
specification limits the maximum voltage developed at the out-
puts to –0.5 V to +1 V. Voltages developed beyond this limitation
will cause excessive DAC distortion and possibly permanent
damage. The user must choose a proper load impedance to limit
the output voltage swing to the compliance limits. Both DAC
outputs should be terminated equally for best SFDR, especially
at higher output frequencies where harmonic distortion errors
are more prominent.
REV. A
AD9854
–24–
Both DACs are preceded by inverse SIN(x)/x filters (a.k.a. inverse
sinc filters) that precompensate for DAC output amplitude varia-
tions over frequency to achieve flat amplitude response from dc
to Nyquist. Both DACs can be powered down by setting the
DAC PD bit high (address 1D of control register) when not
needed. I-DAC outputs are designated as IOUT1 and IOUT1B,
Pins 48 and 49 respectively. Q-DAC outputs are designated
as IOUT2 and IOUT2B, Pins 52 and 51 respectively.
Control DAC
The 12-bit Q DAC can be reconfigured to perform as a “control”
or auxiliary DAC. The control DAC output can provide dc
control levels to external circuitry, generate ac signals, or enable
duty cycle control of the on-board comparator. When the SRC
Q DAC bit in the control register (parallel address 1F hex) is
set high, the Q DAC inputs are switched from internal 12-bit Q
data source (default setting) to external 12-bit, two’s-complement
data, supplied by the user. Data is channeled through the serial
or parallel interface to the 12-bit Q DAC register (address 26 and
27 hex) at a maximum 100 MHz data rate. This DAC is clocked
at the system clock, 300 MSPS (maximum), and has the same
maximum output current capability as that of the I DAC. The
single R
SET
resistor on the AD9854 sets the full-scale output
current for both DACs. The control DAC can be separately
powered down for power conservation when not needed by set-
ting the Q DAC POWER-DOWN bit high (address 1D hex).
Control DAC outputs are designated as IOUT2 and IOUT2B
(Pins 52 and 51 respectively).
FREQUENCY NORMALIZED TO SAMPLE RATE
4.0
00.1
–0.5
0
dB
3.5
3.0
2.5
2.0
1.5
1.0
0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0 0.2 0.3 0.4 0.5
SYSTEM
ISF
SINC
Figure 47. Inverse SINC Filter Response
Inverse SINC Function
This filter precompensates input data to both DACs for the
SIN(x)/x roll-off characteristic inherent in the DAC’s output
spectrum. This allows wide bandwidth signals (such as QPSK)
to be output from the DACs without appreciable amplitude varia-
tions as a function of frequency. The inverse SINC function may
be bypassed to significantly reduce power consumption, espe-
cially at higher clock speeds. When the Q DAC is configured
as a “control” DAC, the inverse SINC function does not apply.
Inverse SINC is engaged by default and is bypassed by bringing
the “Bypass Inv SINC” bit high in control register 20 (hex) in
Table IV.
REFCLK Multiplier
This is a programmable PLL-based reference clock multiplier
that allows the user to select an integer clock multiplying value
over the range of 4× to 20×. Use of this function allows users to
input as little as 15 MHz at the REFCLK input to produce a
300 MHz internal system clock. Five bits in control register 1E
hex set the multiplier value as follows in Table III.
The REFCLK Multiplier function can be bypassed to allow direct
clocking of the AD9854 from an external clock source. The
system clock for the AD9854 is either the output of the REFCLK
Multiplier (if it is engaged) or the REFCLK inputs. REFCLK
may be either a single-ended or differential input by setting Pin
64, DIFF CLK ENABLE, low or high respectively.
PLL Range Bit
The PLL Range Bit selects the frequency range of the REFCLK
Multiplier PLL. For operation from 200 MHz to 300 MHz
(internal system clock rate) the PLL Range Bit should be set to
Logic 1. For operation below 200 MHz, the PLL Range Bit
should be set to Logic 0. The PLL Range Bit adjusts the PLL
loop parameters for optimized phase noise performance within
each range.
Pin 61, PLL FILTER
This pin provides the connection for the external zero compen-
sation network of the PLL loop filter. The zero compensation
network consists of a 1.3 kΩ resistor in series with a 0.01 µF
capacitor. The other side of the network should be connected to
as close as possible to Pin 60, AVDD. For optimum phase noise
performance the clock multiplier can be bypassed by setting the
“Bypass PLL” bit in control register address 1E.
Differential REFCLK Enable
A high level on this pin enables the differential clock Inputs,
REFCLK and REFCLKB (Pins 69 and 68 respectively). The
minimum differential signal amplitude required is 800 mV p-p.
The centerpoint or common-mode range of the differential sig-
nal can range from 1.6 V to 1.9 V.
When Pin 64 (DIFF CLK ENABLE) is tied low, REFCLK
(Pin 69) is the only active clock input. This is referred to as
the single-ended mode. In this mode, Pin 68 (REFCLKB) should
be tied low or high, but not left floating.
High-Speed Comparator—optimized for high speed, >300 MHz
toggle rate, low jitter, sensitive input, built-in hysteresis and
an output level of 1 V p-p minimum into 50 Ω or CMOS logic
levels into high impedance loads. The comparator can be sepa-
rately powered down to conserve power. This comparator is used
in “clock generator” applications to square up the filtered sine
wave generated by the DDS.
Power-Down—Several individual stages may be powered down
to reduce power consumption via the programming registers
while still maintaining functionality of desired stages. These
stages are identified in the Register Layout table, address 1D hex.
Power-down is achieved by setting the specified bits to logic high.
A logic low indicates that the stages are powered up.
Furthermore, and perhaps most significantly, the Inverse Sinc
filters and the Digital Multiplier stages, can be bypassed to achieve
significant power reduction through programming of the control
registers in address 20 hex. Again, logic high will cause the stage to
be bypassed. Of particular importance is the Inverse Sinc filter
as this stage consumes a significant amount of power.
A full power-down occurs when all four PD Bits in control
register 1D hex are set to logic high. This reduces power
consumption to approximately 10 mW (3 mA).
REV. A
AD9854
–25–
PROGRAMMING THE AD9854
The AD9854 Register Layout, shown in Table IV, contains
the information that programs the chip for the desired function-
ality. While many applications will require very little programming
to configure the AD9854, some will make use of all twelve acces-
sible register banks. The AD9854 supports an 8-bit parallel I/O
operation or an SPI-compatible serial I/O operation. All acces-
sible registers can be written and read back in either I/O operating
mode.
S/P SELECT, Pin 70, is used to configure the I/O mode. Systems
that use the parallel I/O mode must connect the S/P SELECT
pin to V
DD
. Systems that operate in the serial I/O mode must tie
the S/P SELECT pin to GND.
Table III. REFCLK Multiplier Control Register Values
Multiplier Value Ref Mult Bit 4 Ref Mult Bit 3 Ref Mult Bit 2 Ref Mult Bit 1 Ref Mult Bit 0
400100
500101
600110
700111
801000
901001
10 0 1 0 1 0
11 0 1 0 1 1
12 0 1 1 0 0
13 0 1 1 0 1
14 0 1 1 1 0
15 0 1 1 1 1
16 1 0 0 0 0
17 1 0 0 0 1
18 1 0 0 1 0
19 1 0 0 1 1
20 1 0 1 0 0
Regardless of mode, the I/O port data is written to a buffer
memory that does NOT affect operation of the part until the
contents of the buffer memory are transferred to the register
banks. This transfer of information occurs synchronously to the
system clock and occurs in one of two ways:
1. Internally controlled at a rate programmable by the user or,
2. Externally controlled by the user. I/O operations can occur in
the absence of REFCLK but the data cannot be moved from
the buffer memory to the register bank without REFCLK.
See the Update Clock Operation section of this document
for details.
A<5:0>
D<7:0>
RD
A1
D1
A2
D2
A3
D3
TRDHOZ TRDLOV
TAHD TADV
SPECIFICATION VALUE DESCRIPTION
TADV
TAHD
TRDLOV
TRDHOZ
15ns
5ns
15ns
10ns
ADDRESS TO DATA VALID TIME (MAXIMUM)
ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM)
RD LOW TO OUTPUT VALID (MAXIMUM)
RD HIGH TO DATA THREE-STATE (MAXIMUM)
Figure 48. Parallel Port Read Timing Diagram
REV. A
AD9854
–26–
Table IV. Register Layout. Shaded Sections Comprise the Control Register
Parallel Serial
Address Address AD9854 Register Layout
Default
Hex Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value
00 0 Phase Adjust Register #1 <13:8> (Bits 15, 14 don’t care) Phase 1 00h
01 Phase Adjust Register #1 <7:0> 00h
02 1 Phase Adjust Register #2 <13:8:> (Bits 15, 14 don’t care) Phase 2 00h
03 Phase Adjust Register #2 <7:0> 00h
04 2 Frequency Tuning Word 1 <47:40> Frequency 1 00h
05 Frequency Tuning Word 1 <39:32> 00h
06 Frequency Tuning Word 1 <31:24> 00h
07 Frequency Tuning Word 1 <23:16> 00h
08 Frequency Tuning Word 1 <15:8> 00h
09 Frequency Tuning Word 1 <7:0> 00h
0A 3 Frequency Tuning Word 2 <47:40> Frequency 2 00h
0B Frequency Tuning Word 2 <39:32> 00h
0C Frequency Tuning Word 2 <31:24> 00h
0D Frequency Tuning Word 2 <23:16> 00h
0E Frequency Tuning Word 2 <15:8> 00h
0F Frequency Tuning Word 2 <7:0> 00h
10 4 Delta Frequency Word <47:40> 00h
11 Delta Frequency Word <39:32> 00h
12 Delta Frequency Word <31:24> 00h
13 Delta Frequency Word <23:16> 00h
14 Delta Frequency Word <15:8> 00h
15 Delta Frequency Word <7:0> 00h
16 5 Update Clock <31:24> 00h
17 Update Clock <23:16> 00h
18 Update Clock <15:8> 00h
19 Update Clock <7:0> 40h
1A 6 Ramp Rate Clock <19:16> (Bits 23, 22, 21, 20 don’t care) 00h
1B Ramp Rate Clock <15:8> 00h
1C Ramp Rate Clock <7:0> 00h
7 Don’t Don’t Don’t Comp PD Reserved, QDAC PD DAC PD DIG PD 10h
1D Care Care Care Always
CR [31] Low
1E Don’t PLL Bypass Ref Mult 4 Ref Mult 3 Ref Mult 2 Ref Mult 1 Ref Mult 0 64h
Care Range PLL
1F CLR CLR Triangle SRC Mode 2 Mode 1 Mode 0 INT/EXT 01h
ACC 1 ACC 2 QDAC Update Clk
Don’t Bypass OSK EN OSK INT Don’t Don’t LSB First SDO 20h
Care Inv Care Care Active
20 Sinc CR [0]
21 8 Output Shape Key I Mult <11:8> (Bits 15, 14, 13, 12 don’t care) 00h
22 Output Shape Key I Mult <7:0> 00h
23 9 Output Shape Key Q Mult <11:8> (Bits 15, 14, 13, 12 don’t care) 00h
24 Output Shape Key Q Mult <7:0> 00h
25 A Output Shape Key Ramp Rate <7:0> 80h
26 B QDAC <11:8> (Bits 15, 14, 13, 12 don’t care) 00h
27 QDAC <7:0> (Data is required to be in two’s complement format) 00h
REV. A
AD9854
–27–
D<7:0>
WR
D1 D2 D3
SPECIFICATION VALUE DESCRIPTION
TASU
TDSU
TADH
TDHD
8.0ns
3.0ns
ADDRESS SETUP TIME TO WR SIGNAL ACTIVE
DATA SETUP TIME TO WR SIGNAL ACTIVE
0ns
0ns
ADDRESS HOLD TIME TO WR SIGNAL INACTIVE
DATA HOLD TIME TO WR SIGNAL INACTIVE
TWRLOW
TWRHIGH
TWR
2.5ns WR SIGNAL MINIMUM LOW TIME
7ns
10.5ns
WR SIGNAL MINIMUM HIGH TIME
WR SIGNAL MINIMUM PERIOD
A<5:0> A1 A2 A3
TASU TAHD
TWRHIGH TWRLOW TDHD
TDSU
TWR
Figure 49. Parallel Port Write Timing Diagram
Master RESET—logic high active, must be held high for a
minimum of 10 system clock cycles. This causes the communi-
cations bus to be initialized and loads default values listed in the
Table IV.
Parallel I/O Operation
With the S/P SELECT pin tied high, the parallel I/O mode is
active. The I/O port is compatible with industry standard DSPs
and microcontrollers. Six address bits, eight bidirectional data
bits and separate write/read control inputs make up the I/O
port pins.
Parallel I/O operation allows write access to each byte of any
register in a single I/O operation at 100 MHz. Read back capability
for each register is included to ease designing with the AD9854.
Reads are not guaranteed at 100 MHz as they are intended for
software debug only.
Parallel I/O operation timing diagrams are shown in the Figures
48 and 49.
Serial Port I/O Operation
With the S/P SELECT pin tied low, the serial I/O mode is active.
The AD9854 serial port is a flexible, synchronous, serial com-
munications port allowing easy interface to many industry-standard
microcontrollers and microprocessors. The serial I/O is compat-
ible with most synchronous transfer formats, including both the
Motorola 6905/11 SPI and Intel 8051 SSR protocols. The inter-
face allows read/write access to all twelve registers that configure
the AD9854 and can be configured as a single pin I/O (SDIO)
or two unidirectional pins for in/out (SDIO/SDO). Data transfers
are supported in most significant bit (MSB) first format or least
significant bit (LSB) first format at up to 10 MHz.
When configured for serial I/O operation, most pins from the
AD9854 parallel port are inactive; some are used for the serial
I/O. Table V describes pin requirements for serial I/O.
Note: When operating in the serial I/O mode, it is best to use the
external update mode to avoid an update CLK during serial com-
munication cycle. Such an occurrence could cause incorrect
programming due to partial data transfer. To exit the default
internal update mode, at power up, before starting the REFCLK
signal program the device for external update operation. Starting
the REFCLK will cause this information to transfer to the register
bank, putting the device in external update mode.
Table V. Serial I/O Pin Requirements
Pin Pin
Number Name Serial I/O Description
1, 2, 3, 4, D[7:0] The parallel data pins are not active, tie
5, 6, 7, 8 to VDD or GND.
14, 15, 16 A[5:3] The parallel address Pins A5, A4, A3
are not active, tie to VDD or GND.
17 A2 IO RESET
18 A1 SDO
19 A0 SDIO
20 I/O UD Update Clock. Same functionality for
CLOCK Serial Mode as Parallel Mode.
21 WRB SCLK
22 RDB CSB—Chip Select
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a serial communication cycle with the
AD9854. Phase 1 is the instruction cycle, which is the writing
of an instruction byte into the AD9854, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9854 serial port controller with information regarding the data
transfer cycle, which is Phase 2 of the communication cycle. The
Phase 1 instruction byte defines whether the upcoming data trans-
fer is read or write, and the register address to be acted upon.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9854. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9854
and the system controller. The number of data bytes transferred
in Phase 2 of the communication cycle is a function of the regis-
ter address. The AD9854 internal serial I/O controller expects
every byte of the register being accessed to be transferred. Table
VI describes how many bytes must be transferred.
REV. A
AD9854
–28–
Table VI. Register Address vs. Data Bytes Transferred
Serial Number
Register of Bytes
Address Register Name Transferred
0 Phase Offset Tuning Word Register #1 2 Bytes
1 Phase Offset Tuning Word Register #2 2 Bytes
2 Frequency Tuning Word #1 6 Bytes
3 Frequency Tuning Word #2 6 Bytes
4 Delta Frequency Register 6 Bytes
5 Update Clock Rate Register 4 Bytes
6 Ramp Rate Clock Register 3 Bytes
7 Control Register 4 bytes
8 I Path Digital Multiplier Register 2 Bytes
9 Q Path Digital Multiplier Register 2 Bytes
A Shaped On/Off Keying Ramp Rate Register 2 Bytes
B Q DAC Register 2 Bytes
At the completion of any communication cycle, the AD9854
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. In
addition, an active high input on the IO RESET pin immediately
terminates the current communication cycle. After IO RESET
returns low, the AD9854 serial port controller requires the next
eight rising SCLK edges to be the instruction byte of the next
communication cycle.
All data input to the AD9854 is registered on the rising edge of
SCLK. All data is driven out of the AD9854 on the falling edge
of SCLK.
Figures 50 and 51 are useful in understanding the general opera-
tion of the AD9854 Serial Port.
INSTRUCTION
CYCLE
DATA TRANSFER
INSTRUCTION
BYTE DATA BYTE 1 DATA BYTE 2 DATA BYTE 3
SDIO
CS
Figure 50. Using SDIO as a Read/ Write Transfer
INSTRUCTION
CYCLE DATA TRANSFER
INSTRUCTION
BYTE
SDIO
CS
DATA TRANSFER
DATA BYTE 1 DATA BYTE 2 DATA BYTE 3
SDO
Figure 51. Using SDIO as an Input, SDO as an Output
Instruction Byte
The instruction byte contains the following information.
Table VII. Instruction Byte Information
MSBD6 D5D4 D3 D2D1LSB
R/WXXXA3A2A1A0
R/W—Bit 7 of the instruction byte determines whether a read or
write data transfer will occur following the instruction byte.
Logic high indicates read operation. Logic zero indicates a write
operation.
Bits 6, 5, and 4 of the instruction byte are dummy bits (don’t
care).
A3, A2, A1, A0—Bits 3, 2, 1, 0 of the instruction byte determine
which register is accessed during the data transfer portion of the
communications cycle. See Table VI for register address details.
Serial Interface Port Pin Description
SCLK
Serial Clock (Pin 21). The serial clock pin is used to synchronize
data to and from the AD9854 and to run the internal state
machines. SCLK maximum frequency is 10 MHz.
CS
Chip Select (Pin 22). Active low input that allows more than
one device on the same serial communications lines. The SDO
and SDIO pins will go to a high impedance state when this
input is high. If driven high during any communications cycle,
that cycle is suspended until CS is reactivated low. Chip Select
can be tied low in systems that maintain control of SCLK.
SDIO
Serial Data I/O (Pin 19). Data is always written into the AD9854
on this pin. However, this pin can be used as a bidirectional
data line. The configuration of this pin is controlled by Bit 0 of
register address 20h. The default is logic zero, which configures
the SDIO pin as bidirectional.
SDO
Serial Data Out (Pin 18). Data is read from this pin for proto-
cols that use separate lines for transmitting and receiving data.
In the case where the AD9854 operates in a single bidirectional
I/O mode, this pin does not output data and is set to a high
impedance state.
IO RESET
Synchronize I/O Port (Pin 17). Synchronizes the I/O port state
machines without affecting the contents of the addressable regis-
ters. An active high input on IO RESET pin causes the current
communication cycle to terminate. After IO RESET returns low
(Logic 0) another communication cycle may begin, starting with
the instruction byte.
Notes on Serial Port Operation
The AD9854 serial port configuration bits reside in Bits 1 and 0
of register address 20h. It is important to note that the configura-
tion changes immediately upon a valid I/O update. For multibyte
transfers, writing this register may occur during the middle of a
communication cycle. Care must be taken to compensate for
this new configuration for the remainder of the current commu-
nication cycle.
The system must maintain synchronization with the AD9854 or
the internal control logic will not be able to recognize further
instructions. For example, if the system sends the instruction to
write a 2-byte register, then pulses the SCLK pin for a 3-byte
register (24 additional SCLK rising edges), communication
synchronization is lost. In this case, the first 16 SCLK rising edges
after the instruction cycle will properly write the first two data
bytes into the AD9854, but the next eight rising SCLK edges
are interpreted as the next instruction byte, NOT the final byte
of the previous communication cycle.
REV. A
AD9854
–29–
In the case where synchronization is lost between the system and
the AD9854, the IO RESET pin provides a means to reestablish
synchronization without reinitializing the entire chip. Asserting
the IO RESET pin (active high) resets the AD9854 serial port state
machine, terminating the current IO operation and putting the
device into a state in which the next eight SCLK rising edges
are understood to be an instruction byte. The SYNC IO pin
must be deasserted (low) before the next instruction byte write can
begin. Any information that had been written to the AD9854
registers during a valid communication cycle prior to loss of
synchronization will remain intact.
CS
SCLK
SDIO
TPRE
TDSU TSCLKPWH TSCLKPWL
TSCLK
TDHLD
2ND BIT1ST BIT
SYMBOL MIN DEFINITION
CS SETUP TIME
PERIOD OF SERIAL DATA CLOCK
SERIAL DATA SETUP TIME
SERIAL DATA CLOCK PULSEWIDTH HIGH
SERIAL DATA CLOCK PULSEWIDTH LOW
SERIAL DATA HOLD TIME
TPRE
TSCLK
TDSU
TSCLKPWH
TSCLKPWL
TDHLD
30ns
100ns
30ns
40ns
40ns
0ns
Figure 52. Timing Diagram for Data Write to AD9854
T
DV
1ST BIT 2ND BIT
SDIO
SDO
SCLK
CS
SYMBOL MAX DEFINITION
T
DV
30ns DATA VALID TIME
Figure 53. Timing Diagram for Read from AD9854
MSB/LSB TRANSFERS
The AD9854 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by Bit 1 of serial register bank 20h.
When this bit is set active high, the AD9854 serial port is in LSB
first format. This bit defaults low, to the MSB first format. The
instruction byte must be written in the format indicated by Bit 1
of serial register bank 20h. That is, if the AD9854 is in LSB first
mode, the instruction byte must be written from least significant
bit to most significant bit.
Control Register Description
The Control Register is located in the shaded portion of the
Table IV at address 1D through 20 hex. It is composed of 32
bits. Bit 31 is located at the top left position and Bit 0 is located
in the lower right position of the shaded table portion. The reg-
ister has been subdivided below to make it easier to locate the
text associated with specific control categories.
CR[31:29] are open.
CR[28] is the comparator power-down bit. When set (Logic 1),
this signal indicates to the comparator that a power-down mode
is active. This bit is an output of the digital section and is an
input to the analog section.
CR[27] must always be written to logic zero. Writing this bit to
Logic 1 causes the AD9854 to stop working until a master
reset is applied.
CR[26] is the Q DAC power-down bit. When set (Logic 1), this
signal indicates to the Q DAC that a power-down mode is active.
CR[25] is the full DAC power-down bit. When set (Logic 1),
this signal indicates to both the I and Q DACs as well as the refer-
ence that a power-down mode is active.
CR[24] is the digital power-down bit. When set (Logic 1), this
signal indicates to the digital section that a power-down mode is
active. Within the digital section, the clocks will be forced to dc,
effectively powering down the digital section. The PLL will
still accept the REFCLK signal and continue to output the higher
frequency.
CR[23] is reserved. Write to zero.
CR[22] is the PLL range bit. The PLL range bit controls the
VCO gain. The power-up state of the PLL range bit is Logic 1,
higher gain for frequencies above 200 MHz.
CR[21] is the bypass PLL bit, active high. When active, the PLL
is powered down and the REFCLK input is used to drive the
system clock signal. The power-up state of the bypass PLL bit is
Logic 1, PLL bypassed.
CR[20:16] bits are the PLL multiplier factor. These bits are the
REFCLK multiplication factor unless the bypass PLL bit is set.
The PLL multiplier valid range is from 4 to 20, inclusive.
CR[15] is the clear accumulator 1 bit. This bit has a one-shot
type function. When written active, Logic 1, a clear accumulator 1
signal is sent to the DDS logic, resetting the accumulator value to
zero. The bit is then automatically reset, but the buffer memory
is not reset. This bit allows the user to easily create a sawtooth
frequency sweep pattern with minimal user intervention.
This bit is intended for chirp mode only, but its function is still
retained in other modes.
CR[14] is the clear accumulator bit. This bit, active high, holds
both the accumulator 1 and accumulator 2 values at zero for as
long as the bit is active. This allows the DDS phase to be initial-
ized via the I/O port.
CR[13] is the triangle bit. When this bit is set, the AD9854 will
automatically perform a continuous frequency sweep from F1 to
F2 frequencies and back. The effect is a triangular frequency
sweep. When this bit is set, the operating mode must be set to
ramped FSK.
CR[12] is the source Q DAC bit. When set high, the Q path
DAC accepts data from the Q DAC Register.
CR[11:9] are the three bits that describe the five operating modes
of the AD9854:
0h = Single-Tone Mode
1h = FSK Mode
2h = Ramped FSK mode
3h = Chirp Mode
4h = BPSK Mode
REV. A
AD9854
–30–
SDIO D
7
I
7
SCLK
CS
INSTRUCTION CYCLE DATA TRANSFER CYCLE
I
6
I
5
I
4
I
3
I
0
I
2
I
1
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Figure 54. Serial Port Write Timing–Clock Stall Low
SDIO
D
O 7
D
O 6
D
O 5
D
O 4
D
O 3
D
O 2
D
O 1
D
O 0
SCLK
CS
INSTRUCTION CYCLE
DON'T CARE
SDO
DATA TRANSFER CYCLE
I
7
I
6
I
5
I
4
I
3
I
0
I
2
I
1
Figure 55. Three-Wire Serial Port Read Timing–Clock Stall Low
D7D6D5D4D3D2D1D0
SDIO
SCLK
CS
INSTRUCTION CYCLE DATA TRANSFER CYCLE
I7I6I5I4I3I0
I2I1
Figure 56. Serial Port Write Timing–Clock Stall High
I7I6I5I4I3I0
I2I1
SDIO
SCLK
CS
INSTRUCTION CYCLE DATA TRANSFER CYCLE
DO 7 DO 6 DO 5 DO 4 DO 3 DO 2 DO 1 DO 0
Figure 57. Two-Wire Serial Port Read Timing–Clock Stall High
CR[8] is the internal update active bit. When this bit is set to
Logic 1, the I/O UD pin is an output and the AD9854 generates
the I/O UD signal. When Logic 0, external I/O UD functionality
is performed, the I/O UD pin is configured as an input.
CR[7] is reserved. Write to zero.
CR[6] is the inverse sinc filter BYPASS bit. When set, the data
from the DDS block goes directly to the output shaped-keying
logic and the clock to the inverse sinc filter is stopped. Default is
clear, filter enabled.
CR[5] is the shaped keying enable bit. When set the output
ramping function is enabled and is performed in accordance with
the CR[4] bit requirements.
CR[4] is the internal/external output shaped-keying control
bit. When set to Logic 1, the shaped-keying factor will be inter-
nally generated and applied to both the I and Q paths. When
cleared (default), the output shaped-keying function is externally
controlled by the user and the shaped-keying factor is the I and
Q output shaped-keying factor register value. The two registers
that are the shaped-keying factors also default low such that the
output is off at power-up and until the device is programmed by
the user.
CR[3:2] are reserved. Write to zero.
CR[1] is the serial port MSB/LSB first bit. Defaults low, MSB
first.
CR[0] is the serial port SDO active bit. Defaults low, inactive.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The AD9854 is a multifunctional, very high-speed device that
targets a wide variety of synthesizer and agile clock applications.
The set of numerous innovative features contained in the device
each consume incremental power. If enabled in combination,
the safe thermal operating conditions of the device may be
exceeded. Careful analysis and consideration of power dissipa-
tion and thermal management is a critical element in the successful
application of the AD9854 device.
The AD9854 device is specified to operate within the industrial
temperature range of –40°C to +85°C. This specification is
conditional, however, such that the absolute maximum junction
temperature of 150°C is not exceeded. At high operating tempera-
tures, extreme care must be taken in the operation of the device
REV. A
AD9854
–31–
to avoid exceeding the junction temperature which results in a
potentially damaging thermal condition.
Many variables contribute to the operating junction tempera-
ture within the device, including:
1. Package Style
2. Selected Mode of Operation
3. Internal System Clock Speed
4. Supply Voltage
5. Ambient Temperature.
The combination of these variables determines the junction
temperature within the AD9854 device for a given set of operating
conditions.
The AD9854 device is available in two package styles: a thermally-
enhanced surface-mount package with an exposed heat sink,
and a nonthermally-enhanced surface-mount package. The
thermal impedance of these packages is 16°C/W and 38°C/W
respectively, measured under still-air conditions.
THERMAL IMPEDANCE
The thermal impedance of a package can be thought of as a
thermal resistor that exists between the semiconductor surface
and the ambient air. The thermal impedance of a package is
determined by package material and its physical dimensions. The
dissipation of the heat from the package is directly dependent upon
the ambient air conditions and the physical connection made
between the IC package and the PCB. Adequate dissipation of
power from the AD9854 relies upon all power and ground pins
of the device being soldered directly to a copper plane on a PCB.
In addition, the thermally-enhanced package of the AD9854ASQ
contains a heat sink on the bottom of the package that must be
soldered to a ground pad on the PCB surface. This pad must be
connected to a large copper plane which, for convenience, may be
ground plane. Sockets for either package style of the AD9854
device are not recommended.
JUNCTION TEMPERATURE CONSIDERATIONS
The power dissipation (P
DISS
) of the AD9854 device in a given
application is determined by many operating conditions. Some
of the conditions have a direct relationship with P
DISS
, such as
supply voltage and clock speed, but others are less deterministic.
The total power dissipation within the device, and its effect
on the junction temperature, must be considered when using the
device. The junction temperature of the device is given by:
Junction Temperature = (Thermal Impedance ×
Power Consumption) + Ambient Temperature
Given that the junction temperature should never exceed 150°C
for the AD9854, and that the ambient temperature can be 85°C,
the maximum power consumption for the AD9854AST is 1.7 W
and the AD9854ASQ (thermally-enhanced package) is 4.1 W.
Factors affecting the power dissipation are:
Supply Voltage—this obviously affects power dissipation and
junction temperature since P
DISS
equals V × I. Users should design
for 3.3 V nominal; however, the device is guaranteed to meet
specifications, over the full temperature range and over the sup-
ply voltage range of 3.135 V to 3.465 V.
Clock Speed—this directly and linearly influences the total
power dissipation of the device, and, therefore, junction tem-
perature. As a rule, the user should always select the lowest
internal clock speed possible to support a given application, to
minimize power dissipation. Normally the usable frequency out-
put bandwidth from a DDS is limited to 40% of the clock rate
to keep reasonable requirements on the output low-pass filter.
For the typical DDS application, the system clock frequency
should be 2.5 times the highest desired output frequency.
Mode of Operation—the selected mode of operation for the
AD9854 has a great influence on total power consumption. The
AD9854 offers many features and modes, each of which imposes
an additional power requirement. The collection of features
contained in the AD9854 target a wide variety of applications
and the device was designed under the assumption that only a
few features would be enabled for any given application. In fact,
the user must understand that enabling multiple features at higher
clock speeds may cause the maximum junction temperature of
the die to be exceeded. This can severely limit the long-term
reliability of the device. Figures 58a and 58b provide a summary
of the power requirements associated with the individual fea-
tures of the AD9854. These charts should be used as a guide
in determining the optimum application of the AD9854 for
reliable operation.
As can be seen in Figure 58b, the Inverse Sinc filter function
requires a significant amount of power. As an alternate approach
to maintaining flatness across the output bandwidth, the digital
multiplier function may be used to adjust the output signal level,
at a dramatic savings in power consumption. Careful planning and
management in the use of the feature set will minimize power dis-
sipation and avoid exceeding junction temperature requirements
within the IC.
FREQUENCY – MHz
1400
20
SUPPLY CURRENT – mA
1200
1000
800
600
400
200
060 100 140 180 220 260 300
ALL CIRCUITS ENABLED
BASIC CONFIGURATION
Figure 58a. Current Consumption vs. Clock Frequency
Figure 58a shows the supply current consumed by the AD9854
over a range of frequencies for two possible configurations: all
circuits enabled means the output scaling multipliers, the inverse
sinc filter, the Q DAC, and the on-board comparator are all
enabled. Basic configuration means the output scaling multipliers,
the inverse sinc filter, the Q DAC, and the on-board comparator
are all disabled.
REV. A
AD9854
–32–
FREQUENCY – MHz
20 60 100 140 180 220 260 300
450
SUPPLY CURRENT – mA
400
350
300
250
200
150
0
100
50
Q DAC
500
INVERSE SINC FILTER
OUTPUT SCALING
MULTIPLIERS
COMPARATOR
Figure 58b. Current Consumption by Function vs. Clock
Frequency
Figure 58b shows the approximate current consumed by each of
four functions.
EVALUATION OF OPERATING CONDITIONS
The first step in applying the AD9854 is to select the internal
clock frequency. Clock frequency selections above 200 MHz
will require the thermally-enhanced package (AD9854ASQ);
clock frequency selections of 200 MHz and below may allow
the use of the standard plastic surface-mount package, but more
information will be needed to make that determination.
The second step is to determine the maximum required operating
temperature for the AD9854 in the given application. Subtract
this value from 150°C, which is the maximum junction tem-
perature allowed for the AD9854. For the extended industrial
temperature range, the maximum operating temperature is 85°C,
which results in a difference of 65°C. This is the maximum
temperature gradient that the device may experience due to
power dissipation.
The third step is to divide this maximum temperature gradient
by the thermal impedance, to arrive at the maximum power dis-
sipation allowed for the application. For the example so far, 65°C
divided by both versions of the AD9854 package’s thermal imped-
ances of 38°C/W and 16°C/W, yields a total power dissipation
limit of 1.7 W and 4.1 W (respectively). This means that for a
3.3 V nominal power supply voltage, the current consumed by the
device under full operating conditions must not exceed 515 mA
in the standard plastic package and 1242 mA in the thermally-
enhanced package. The total set of enabled functions and
operating conditions of the AD9854 application must support
these current consumption limits.
Figures 58a and Figure 58b may be used to determine the
suitability of a given AD9854 application vs. power dissipation
requirements. These graphs assume that the AD9854 device will
be soldered to a multilayer PCB per the recommended best
manufacturing practices and procedures for the given package
type. This ensures that the specified thermal impedance spec-
ifications will be achieved.
THERMALLY ENHANCED PACKAGE MOUNTING
GUIDELINES
The following are general recommendations for mounting the
thermally enhanced exposed heat sink package (AD9854ASQ)
to printed circuit boards. The exceptional thermal characteristics of
this package depend entirely upon proper mechanical attachment.
Figure 59 depicts the package from the bottom and shows the
dimensions of the exposed heat sink. A solid conduit of solder
needs to be established between this pad and the surface of
the PCB.
C
O
U
N
T
R
Y
14mm10mm
Figure 59.
Figure 60 depicts a general PCB land pattern for such an exposed
heat sink device. Note that this pattern is for a 64-lead device, not
an 80-lead, but the relative shapes and dimensions still apply.
In this land pattern, a solid copper plane exists inside of the
individual lands for device leads. Note also that the solder mask
opening is conservatively dimensioned to avoid any assembly
problems.
SOLDER MASK
OPENING
THERMAL LAND
Figure 60.
The thermal land itself must be able to distribute heat to an even
larger copper plane such as an internal ground plane. Vias must be
uniformly provided over the entire thermal pad to connect to this
internal plane. A proposed via pattern is shown in Figure 61. Via
holes should be small (12 mils, 0.3 mm) such that they can be
plated and plugged. These will provide the mechanical conduit
for heat transfer.
REV. A
AD9854
–33–
Figure 61.
Finally, a proposed stencil design is shown in Figure 62 for screen
solder placement. Note that if vias are not plugged, wicking will
occur, which will displace solder away from the exposed heat sink,
and the necessary mechanical bond will not be established.
Figure 62.
EVALUATION BOARD
An evaluation board is available that supports the AD9854 DDS
devices. This evaluation board consists of a PCB, software, and
documentation to facilitate bench analysis of the performance of
the AD9854 device. It is recommended that users of the AD9854
familiarize themselves with the operation and performance
capabilities of the device with the evaluation board. The evaluation
board should also be used as a PCB reference design to ensure
optimum dynamic performance from the device.
OPERATING INSTRUCTIONS
To assist in proper placement of the pin-header shorting-jumpers,
the instructions will refer to direction (left, right, top, bottom)
as well as header pins to be shorted. Pin #1 for each 3-pin header
has been marked on the PCB corresponding with the schematic
diagram. When following these instructions, position the PCB
so that the text can be read from left to right. The board is
shipped with the pin headers configuring the board as follows:
1. REFCLK for the AD9854 is configured as differential. The
differential clock signals are provided by the 100LVEL16
differential receiver.
2. Input clock for the 100LVEL16 is single-ended via J5. This
signal may be 3.3 V CMOS or a 2 V p-p sine wave capable of
driving 50 Ω (R8).
3. Both DAC outputs from the AD9854 are routed through
the two 120 MHz elliptical LP filters and their outputs con-
nected to J3 (Q) and J4 (I).
4. The board is set up for software control via the printer port
connector.
5. Configured for AD9854 operation.
Load the software from the CD onto the host PC’s hard disk.
Only Windows 9x and NT operating systems are supported.
Connect a printer cable from the PC to the AD9854 Evaluation
Board printer port connector labeled “J11.”
Attach power wires to connector labeled “TB1” using the screw-
down terminals. This is a plastic connector that press-fits over a
4-pin header soldered to the board. Table VIII below shows
connections to each pin. DUT = “device under test.”
Table VIII. Power Requirements for DUT Pins
AVDD 3.3 V DVDD 3.3 V VCC 3.3 V Ground
for All DUT for All DUT for All Other —for All
Analog Pins Digital Pins Devices Devices
Attach REFCLK
There are three possibilities to choose from:
1. On-Board (But Optional) Crystal Clock Oscillator, Y1.
Insert an appropriate 3.3 V CMOS clock oscillator. See that
the shorting jumper at W5 is located on Pins 1 and 2 (the left
two pins). This routes the single-ended oscillator output to a
very high speed “Differential Receiver” (the MC100LVEL16),
where the signal is transformed to a differential PECL output.
To route the differential output signals to AD9854, two more
switches must be configured. W9 must have a shorting jumper
on Pins 2 and 3 (the right two pins). To engage the differen-
tial clocking mode of the AD9854 W3, Pins 2 and 3 (the right
two pins) must be connected with a shorting jumper.
2. External Differential Clock Input, J5.
This is actually just another single-ended input that will be
routed to the MC100LVEL16 for conversion to differential
PECL output. This is accomplished by attaching a 2 V p-p
clock or sine wave source to J5. Note that this is a 50 Ω
impedance point set by R8. The input signal will be ac-coupled
and then biased to the center switching threshold of the
MC100LVEL16. Position the shorting jumper of W5 to Pins
2 and 3 (the right two pins) to route the signal at J5 to the
differential receiver IC. To route the differential output signals
to AD9854, two more switches must be configured. W9 must
have a shorting jumper on Pins 2 and 3 (the right two pins).
To engage the differential clocking mode of the AD9854
W3, Pins 2 and 3 (the right two pins) must be connected
with a shorting jumper.
REV. A
AD9854
–34–
3. External Single-Ended Clock Input, J7.
This mode bypasses the MC100LVEL16 and directly drives
the AD9854 with a user-supplied reference clock. Attach a
50 Ω, 2 V p-p sine source that is dc offset to 1.65 V, or a 50 Ω
CMOS-level clock source to J7. Remove the shorting jumper
from W5 altogether to make certain that the device (U3) is not
Toggling or Self-Oscillating. Set the shorting jumper at W9
to Pins 1 and 2 (the left two pins) to route the REFCLK signal
from J7 to Pin 69 of the AD9854. Finally, set the shorting
jumper at W3 to Pins 1 and 2 (the left two pins) to place the
AD9854 in the single-ended clock mode.
Regardless of the origination, the signals arriving at the AD9854
are called the Reference Clock. If the on-chip REFCLK Multiplier
is engaged, this signal is the reference clock for the REFCLK
Multiplier and the REFCLK Multiplier output becomes the
SYSTEM CLOCK. If the REFCLK Multiplier is bypassed, the
reference clock supplied is directly operating the AD9854 and
is, therefore, the system clock.
Three-state control or switch headers W11, W12, W14, and
W15 must be shorted to allow the provided software to control
the AD9854 evaluation board via the printer port connector J11.
If programming of the AD9854 is not to be provided by the host
PC via the ADI software, then headers W11, W12, W14, and W15
should be opened (shorting jumpers removed). This effectively
detaches the PC interface and allows the 40-pin header, J10, to
assume control without bus contention. Input signals on J10 going
to the AD9854 should be 3.3 V CMOS logic levels.
Low-Pass Filter Testing
The purpose of 2-pin headers W7 and W10 (associated with J1
and J2) are to allow the two 50 Ω, 120 MHz filters to be tested
during PCB assembly without interference from other circuitry
attached to the filter inputs. Normally, a shorting jumper will be
attached to each header to allow the DAC signals to be routed to the
filters. If the user wishes to test the filters, the shorting jumpers
at W7 and W10 should be removed and 50 Ω test signals applied
at J1 and J2 inputs to the 50 Ω elliptic filters. User should refer
to Figure 63 and the following sections to properly position the
remaining shorting jumpers.
Observing the Unfiltered I
OUT1
and the Unfiltered I
OUT2
DAC
Signals
This allows the user to observe the unfiltered DAC outputs at J2
(the “I” signal) and J1 (the “Q” signal). The procedure below sim-
ply routes the two 50 Ω terminated analog DAC outputs to the
BNC connectors and disconnects any other circuitry. The “raw”
DAC outputs will be a series of quantized (stepped) output levels.
The default 10 mA output current will develop a 0.5 V p-p signal
across the on-board 50 Ω termination. When connected to an
external 50 Ω input, the DAC will therefore develop 0.25 V p-p due to
the double termination.
1. Install shorting jumpers at W7 and W10.
2. Remove shorting jumper at W16.
3. Remove shorting jumper from 3-pin header W1.
4. Install shorting jumper on Pins 1 and 2 (bottom two pins) of
3-pin header W4.
Observing the Filtered I
OUT1
and the Filtered I
OUT2
This allows viewer to observe the filtered I and Q DAC outputs
at J4 (the “I” signal) and J3 (the “Q” signal). This places the
50 Ω (input and output Z) low-pass filters in the I and Q DAC
pathways to remove images and aliased harmonics and other
spurious signals above the dc to approximately 120 MHz band-
pass. These signals will appear as nearly pure sine waves and
exactly 90 degrees out-of-phase with each other. These filters
are designed with the assumption that the system clock speed is
at or near maximum (300 MHz). If the system clock utilized is
much less than 300 MHz, for example 200 MHz, unwanted DAC
products other than the fundamental signal will be passed by the
low-pass filters.
1. Install shorting jumpers at W7 and W10.
2. Install shorting jumper at W16.
3. Install shorting jumper on Pins 1 and 2 (bottom two pins) of
3-pin header W1.
4. Install shorting jumper on Pins 1 and 2 (bottom two pins) of
3-pin header W4.
5. Install shorting jumper on Pins 1 and 2 (top two pins) of 3-
pin header W2 and W8.
Observing the Filtered I
OUT
and the Filtered I
OUTB
This allows the user to observe only the filtered “I” DAC out-
puts at J4 (the “true” signal) and J3 (the “complementary” signal).
This places the 120 MHz low pass filters in the true and comple-
mentary output paths of the I DAC to remove images and aliased
harmonics and other spurious signals above approximately
120 MHz. These signals will appear as nearly pure sine waves
and exactly 180 degrees out-of-phase with each other. Again, if
the system clock used is much less than 300 MHz, for example
200 MHz, then unwanted DAC products other than the funda-
mental signal will be passed by the low-pass filters.
1. Install shorting jumpers at W7 and W10.
2. Install shorting jumper at W16.
3. Install shorting jumper on Pins 2 and 3 (top two pins) of 3-
pin header W1.
4. Install shorting jumper on Pins 2 and 3 (top two pins) of 3-
pin header W4.
5. Install shorting jumper on Pins 1 and 2 (top two pins) of 3-
pin header W2 and W8.
To connect the high-speed comparator to the DAC output signals
choose either the quadrature (90⬚) filtered output configuration
or the complementary (180⬚) filtered output configuration as
outlined above. Follow Steps 1 through 4 above, for the desired
filtered configuration. Step 5 below will reroute the filtered sig-
nals away from their connectors (J3 and J4) and connect them to
the 100 Ω configured comparator inputs. This configures the
comparator for differential input without control of the comparator
output duty cycle. The comparator output duty cycle should
be approximately 50% in this configuration.
5. Install shorting jumper on Pins 2 and 3 (bottom two pins) of
3-pin header W2 and W8.
User may elect to change the R
SET
resistor, R2 from 3.9 kΩ to
2 kΩ to get a more robust signal at the comparator inputs. This
will decrease jitter and extend comparator operating range. This
can be accomplished by soldering a second 3.9 kΩ chip resistor
in parallel with the 3.9 kΩ resistor already on board.
REV. A
AD9854
–35–
Connecting the High-Speed Comparator in a Single-Ended
Configuration
This will allow duty cycle or pulse width control and requires that a
dc threshold voltage be present at one of the comparator inputs.
This voltage may be supplied using the “Q DAC” by configuring it
as a control DAC in software or by removing the shorting jumper
at 2-pin header W6. A 12-bit, two’s-complement value is written
to the Q DAC register that will set the I
OUT2
output to a static
dc level. Allowable hexadecimal values are 7FF (maximum) to
800 (minimum) with all 0s being midscale. The I
OUT1
channel
will continue to output a filtered sine wave programmed by the
user. These two signals are routed to the comparator inputs
using W2 and W8 3-pin header switches. The configuration
described above entitled “Observing the Filtered I
OUT
and the
Filtered I
OUTB
” must be used. Follow Steps 1 through 4 and
then the following Step 5:
5. Install shorting jumper on Pins 2 and 3 (bottom two pins) of
3-pin header W2 and W8.
User should elect to change the R
SET
resistor from 3900 Ω to
1950 Ω to get a more robust signal at the comparator inputs.
This will decrease jitter and extend comparator operating range.
User can accomplish this by soldering a second 3.9 kΩ chip
resistor in parallel with the provided R2.
The control software for the AD9854/PCB evaluation board is
provided on a CD. This brief set of instructions should be used
in conjunction with the AD9854/PCB evaluation board sche-
matic. Several numerical entries, such as frequency and phase
information, require that the ENTER key by pressed to register
that information.
1. Select the proper printer port. Click the “Parallel Port” selec-
tion in the menu bar. Select the port that matches your PC.
If unknown, experiment by performing the following on the
selected port. With the part powered up, properly clocked and
connected to the PC, select a port and go to the “Mode and
Frequency” menu and click the “Reset DUT and Initialize
Registers” button. Then go to the “Clock and Amplitude”
menu. Once there, click the box next to “Bypass Inverse Sinc
Filter” . . . a check mark will appear in the box . . . next click
the button “Send Control Info to DUT.” If the proper port
has been selected, the supply current going to the AD9854/
PCB evaluation board should drop by approximately 1/3 when
the inverse sinc filters are bypassed. Conversely, the supply
current will increase approximately 1/3 when the inverse sinc
filters are engaged.
2. Normal operation of the AD9854/PCB evaluation board begins
with a master reset. Many of the default register values after
reset are depicted in the software “control panel.” The reset
command sets the DDS output amplitude to minimum and
0 Hz, 0 phase-offset as well as other states listed in the AD9854
Register Layout table in the data sheet.
3. The next programming block should be the “Reference Clock
and Multiplier” since this information is used to determine
the proper 48-bit frequency tuning words that will be entered
and calculated later.
4. The output amplitude defaults to the 12-bit straight binary
multiplier values of the I and Q multiplier registers of 000hex
and no output should be seen from the DACs. User should
now set both multiplier amplitudes in the Output Amplitude
window to a substantial value, such as FFFhex. You may
bypass the digital multiplier by clicking the box “Output
Amplitude is always Full-Scale” but experience has shown
that doing so does not result in best SFDR. It is interesting
to note that best SFDR, as much as 11 dB better, is obtained
by routing the signal through the digital multiplier and “backing
off” on the multiplier amplitude. For instance, FC0 hex
produces less spurious signal amplitude than FFF hex. It
is a repeatable phenomenon that should be investigated and
exploited for maximum SFDR (spurious-free dynamic range).
5. Refer to this data sheet and evaluation board schematic to
understand all the functions of the AD9854 available to the
user and to gain an understanding of what the software is
doing in response to programming commands.
Applications assistance is available for the AD9854, the
AD9854/PCB evaluation board, and all other Analog Devices
products. Please call 1/800-ANALOGD.
REV. A
AD9854
–36–
D7
D6
D5
D4
D3
D2
D1
D0
DVDD1
DVDD2
DGND1
DGND2
NC
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
UPDCLK
80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
12
17
18
20
19
U1
AD9854
PLLVDD
PLLGND
NC4
NC3
RSET
DACBYPASS
AVDD2
AGND2
IOUT2
IOUT2B
AVDO
IOUT1B
IOUT1
AGND
GND2
COMPVDD
VINB
VIN
GND
COMPGND
PLLFLT
GND3
NC5
DIFFCLKEN
CLKVDD
CLKGND
GND4
REFCLKB
REFCLK
SPSELECT
MRESET
OPTGND
DVDD6
DVDD7
DGND6
DGND7
DGND8
DGND9
DVDD8
DVDD9
COUTGND2
COUTGND
COUTVDD2
COUTVDD
VOUT
NC2
DACDGND2
DACDGND
DACDVDD2
DACDVDD
OUTRAMP
FSK/BPSK/HOLD
DGND5
DGND4
DVDD5
DVDD4
DVDD3
RD
DGND3
WR
J6
J8
J16
J17
J18
J19
J20
J21
J22
J24
J23
J14
J13
J12
J11
GND
J15
AVDD
GND
TB1
DVDD
AVDD
VCC
1
2
3
4GND
W6
R2 3.9k
R20 3.9k
AVDD
AVDD
C45 0.1F
R1
51J4
W7
W1
1
GND
GND
GND
GND
AVDD
AVDD
R3 24
W10 W16
J5
D7
D6
D5
D4
D3
D2
D1
D0
DVDD
DVDD
GND
GND
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
UDCLK
J26
J1
WR
RD
DVDD
DVDD
DVDD
DRAMP
AVDD
AVDD
AVDD
AVDD
AVDD
GND
DVDD
AVDD
GND
DVDD
W3
R4
1.3kC1
0.01F
GND
GND
CLK8
CLK
PMODE
RESET
GND
GND
DVDD
GND
J25
GND R13
50C2
0.01F
OUT GND
NC3.3V
MC100LVEL16
L5
68nH
VEE
VBB
VCC
U3
Y2
D
D
Q
Q
DVDD
1
23
4
2
3
7
8
C25
10F
C24
0.1F
C44
0.1F
C27
0.1F
C8
0.1F
C22
0.1F
C23
0.1F
+
GND
DVDD
C21
10F
C20
0.1F
C14
0.1F
C17
0.1F
C16
0.1F
C18
0.1F
C19
0.1F
VCC
+
GND
C28
0.1F
C26
0.1F
C6
10F
C7
0.1F
C12
0.1F
C10
0.1F
C11
0.1F
C9
0.1F
C29
0.1F
AVDD
+
GND
C13
0.1F
W5
W18
W19
W20
J10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
UDCLK
WR
RD
PMODE
ORAMP
RESET
D7
D6
D5
D4
D3
D2
D0
D1
120 MHz LOW-PASS FILTER
120 MHz LOW-PASS FILTER
W4
R5
51
W17
R8
2k
1DVDD
R11
50R12
50
R19
0
R14
0
CLKB
CLK
J2
J3
GND
GND
C37
27pF
C38
47pF
C39
39pF
C40
22pF
W8
1
L1
68nH
L6
82nH
C41
2.2pF
C42
12pF
C43
8.2pF
J7
GND
C31
22pF
C30
39pF
C5
47pF
C4
27pF
L4
82nH
L2
68nH
C32
2.2pF
C33
12pF
C34
8.2pF GND
J6
W2
1
GND
GND
1
R7
24
R6
50
GND
GND
FDATA
543
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND GND GND
GNDGNDGNDGND
GND
GND
GND
NC = NO CONNECT
L3
68nH
R8
100
GND
R10
100
GND
Figure 63a. Evaluation Board Schematic
REV. A
AD9854
–37–
9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
8D
1D
GND: 10
11
1EN
74HC574
C1
VCC: 20
D0
D1
D2
D3
D4
D5
D6
D7
U8
1
3
5
9
11
13
7
74HC14
14
VCC GND
2
4
6
8
10
12
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
GND
VCC
U5
4
6
8
3
5
9
2
7
1
U11
36PINCONN
GND:[19:30]
11
13
10
12
14
A0
C0
A1
A2
A3
A4
A5
A6
A7
B6
B7
B5
B4
C1
C2
B3
C3
U6
U7
VCC
R15
10k
R16
10k
R17
10k
VCC
VCC
GND: 10
11
1EN
74HC574
C1
VCC: 20
ADDR5
ADDR4
ADDR3
ADDR2
U9
VCC
GND: 10
11
1EN
C1
74HC574
VCC: 20
WR
RD
RESET
UDCLK
PMODE
ORAMP
FDATA
U4
74HC14
GND
1G
1A
1Y
2G
2A
2Y
VCC
4G
4A
4Y
3G
3A
3Y
U2
GND
1
2
3
4
5
6
7
13
12
11
10
9
8
14 VCC
VCC
U10
W11
ADDR1
ADDR0 W14
W12
W13
W9
VCC
R18
10k
GND
W15
VCC RP1
10k
1
3
5
9
2
4
6
8
10
7
1
3
5
9
11
13
7
74HC14
14
VCC GND
2
4
6
8
10
12
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
GND
VCC
1
3
5
9
11
13
7
74HC14
14
VCC GND
2
4
6
8
10
12
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
GND
VCC
1
3
5
9
11
13
7
74HC14
14
VCC GND
2
4
6
8
10
12
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
GND
VCC
9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
8D
1D 9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
8D
1D
31
32
36
VCC
VCC
VCC
Figure 63b. Evaluation Board Schematic
REV. A
AD9854
–38–
AD9852/54 Customer Evaluation Board
(AD9852 PCB > U1 = AD9852ASQ, AD9854 PCB > U1 = AD9854ASQ)
# Quantity REFDES Device Package Value Mfg. Part No.
1 3 C1, C2, C45 CAP 0805 0.01 µF
2 21 C7, C8, C9, C10, C11, CAP 0603 0.1 µF
C12, C13, C14, C16, C17,
C18, C19, C20, C22, C23,
C24, C26, C27, C28, C29,
C44
3 2 C4, C37 CAP 1206 27 pF
4 2 C5, C38 CAP 1206 47 pF
5 3 C6, C21, C25 BCAPT TAJD 10 µF
6 2 C30, C39 CAP 1206 39 pF
7 2 C31, C40 CAP 1206 22 pF
8 2 C32, C41 CAP 1206 2.2 pF
9 2 C33, C42 CAP 1206 12 pF
10 2 C34, C43 CAP 1206 8.2 pF
11 9 J1, J2, J3, J4, J5, J6, J7 SMB STR-PC MNT
J25, J26
12 16 J8, J9, J11, J12, J13, J14, W-HOLE
J15, J16, J17, J18, J19, J20,
J21, J22, J23, J24
13 1 J10 DUAL ROW 40 PINS SAMTEC
HEADER TSW-120-23-L-D
14 4 L1, L2, L3, L5 IND-COIL 1008CS 68 nH COILCRAFT
1008CS-680XGBB
15 2 L4, L6 IND-COIL 1008CS 82 nH COILCRAFT
1008CS-820XGBB
16 2 R1, R5 RES 1206 51 Ω(49.9 Ω, 1%)
17 2 R2, R20 RES 1206 3900 Ω
18 2 R3, R7 RES 1206 24 Ω(24.9 Ω, 1%)
19 1 R4 RES 1206 1300 Ω
20 4 R6, R11, R12, R13 RES 1206 50 Ω(49.9 Ω, 1%)
21 1 R8 RES 1206 2000 Ω
22 2 R9, R10 RES 1206 100 Ω
23 4 R15, R16, R17, R18 RES 1206 10 kΩ
24 1 RP1 RES NETWORK SIP-10P 10 kΩBourns
4610X-101-103
25 1 TB1 TERMINAL 4-POSITION WIELAND
BLOCK & PINS 25.602.2453.0 Block
Z5.530.3425.0 Pins
26 1 U1 AD9852 or 80 LQFP AD9852ASQ or
AD9854 AD9854ASQ
27 1 U2 74HC125 14 SO1C SN74HC125D
28 1 U3 MC100LVEL16D 8 SO1C MC100LVEL16D
29 4 U4, U5, U6, U7 74HC14 14 SO1C SN74HC14D
30 3 U8, U9, U10 74HC574 20 SO1C SN74HC574DW
31 1 J11 36 PIN AMP 552742-1
CONNECTOR
32 6 W1, W2, W3, W4, W8, W17 3-PIN JUMPER SAMTEC
33 10 W6, W7, W9, W10, W11, 2-PIN JUMPER SAMTEC
W12, W13, W14, W15, W16
34 2 SELF-TAPPING 4–40, PHILIPS,
SCREW ROUND HEAD
35 4 RUBBER SQUARE 3M
BUMPER BLACK SJ-5018SPBL
36 1 AD9852/54 PCB GSO2669 REV. E
37 2 R14, R19 Zero Ω JUMPER 1206 Zero ⍀
38 4 Pin Socket AMP 5-330808-6
39 1 Y1 XTAL COSC Optional
REV. A
AD9854
–39–
Figure 64. Assembly Drawing
Figure 65. Top Routing Layer, Layer 1
REV. A
AD9854
–40–
Figure 66. Power Plane Layer, Layer 2
Figure 67. Ground Plane Layer, Layer 3
REV. A
AD9854
–41–
Figure 68. Bottom Routing Layer, Layer 4
REV. A
AD9854
–42–
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
80-Lead LQFP_ED
(SQ-80)
61
60
1
80
20 41
21 40
TOP VIEW
(PINS DOWN)
PIN 1
0.630 (16.00) BSC SQ
0.551 (14.00) BSC SQ
1
20
21
41
40
60
80
61
BOTTOM VIEW
THERMAL
SLUG
0.394 (10.00)
REF SQ
SEATING
PLANE
0.063 (1.60)
MAX
0.004 (0.10)
MAX
COPLANARITY
0.006 (0.15)
0.002 (0.05)
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
0.0256 (0.65)
BSC
7
3.5
0
0.008 (0.20)
0.004 (0.09)
0.015 (0.38)
0.013 (0.32)
0.009 (0.22)
0.057 (1.45)
0.055 (1.40)
0.053 (1.35)
CONTROLLING DIMENSIONS IN MILLIMETERS.
CENTER FIGURES ARE NOMINAL UNLESS OTHERWISE NOTED.
80-Lead LQFP
(ST-80)
61
60
1
80
20 41
21 40
TOP VIEW
(PINS DOWN)
PIN 1
0.630 (16.00) BSC SQ
0.551 (14.00) BSC SQ
SEATING
PLANE
0.063 (1.60)
MAX
0.004 (0.10)
MAX
COPLANARITY
0.006 (0.15)
0.002 (0.05)
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
0.0256 (0.65)
BSC
7
3.5
0
0.008 (0.20)
0.004 (0.09)
0.015 (0.38)
0.013 (0.32)
0.009 (0.22)
0.057 (1.45)
0.055 (1.40)
0.053 (1.35)
CONTROLLING DIMENSIONS IN MILLIMETERS.
CENTER FIGURES ARE NOMINAL UNLESS OTHERWISE NOTED.
C00636–0–9/00 (rev. A)
PRINTED IN U.S.A.
