Z9960 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer Features * * * * * * * * * * * * * Table 1. Frequency Table[1] 2.5V or 3.3V operation Output frequency up to 200 MHz Supports PowerPC, and Pentium(R) processors 21 clock outputs: drive up to 42 clock lines LVPECL or LVCMOS/LVTTL clock input Output-to-output Sskew < 150 ps Split 2.5V/3.3V outputs Spread spectrum compatible Glitch-free output clocks transitioning Output disable control Pin-compatible with MPC9600 Industrial temperature range: -40C to +85C 48-pin LQFP package S E L A 0 1 QA VCO/2 VCO/4 QC VCO/2 VCO/4 FB_OUT VCO/8 VCO/12 VSS FB_IN QA0 QA1 VDDA QA2 QA3 VSSA QA4 QA5 QA6 VDDA Pin Configuration AVDD A 0 1 QB VCO/2 VCO/4 S E L C 0 1 Note: 1. Input frequency range: 16 MHz to 33 MHz (FB_SEL = 1), or 25 MHz to 50 MHz (FB_SEL = 0). Block Diagram REF_SEL TCLK PECL_CLK PECL_CLK# S E L B 0 1 F B _ S E L 0 1 PLL 0 REF FB 1 /2 /4 /8 /12 0 1 DQ 0 1 48 47 46 45 44 43 42 41 40 39 38 37 2 3 FB_IN SELA 4 5 B 0 1 DQ 6 0 1 2 3 SELB 4 5 C 0 1 DQ 6 0 1 2 3 SELC 1 2 3 4 5 6 7 8 9 10 11 12 VSS TCLK PECL_CLK PECL_CLK# VDD REF_SEL FB_SEL AVDD SELA SELB SELC VSSC Z9960 36 35 34 33 32 31 30 29 28 27 26 25 VSSA FB_OUT QB0 QB1 VDDB QB2 QB3 VSSB QB4 QB5 QB6 VDDB 13 14 15 16 17 18 19 20 21 22 23 24 VDDC OE# QC6 QC5 VSSC QC4 QC3 VDDC QC2 QC1 QC0 VSSB 4 5 6 OE# FB 0 1 DQ FB_OUT FB_SEL Cypress Semiconductor Corporation Document #: 38-07087 Rev. *B * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised December 21, 2002 Z9960 Pin Definitions Pin Name Pin No. Pin Type PECL_CLK 3 I, PD PECL Clock Input. PECL_CLK# 4 I, PU PECL Clock Input. TCLK 2 I, PD External Reference/Test Clock Input. QA(6:0) 38, 39, 40, 42, 43, 45, 46 O VDDA Clock Outputs. See Table 1 for frequency selections. QB(6:0) 26, 27, 28, 30, 31, 33, 34 O VDDB Clock Outputs. See Table 1 for frequency selections. QC(6:0) 15, 16, 18, 19, 21, 22, 23 O VDDC Clock Outputs. See Table 1 for frequency selections. FB_OUT 35 O VDD Feedback Clock Output. Connect to FB_IN for normal operation. The divider ratio for this output is set by FB_SEL; see Table 1. A bypass delay capacitor at this output will control Input Reference/ Output Banks phase relationships. SELA 9 I, PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:6) outputs. See Table 1. SELB 10 I, PU Frequency Select Inputs. These inputs select the divider ratio at QB(0:6) outputs. See Table 1. SELC 11 I, PU Frequency Select Inputs. These inputs select the divider ratio at QC(0:6) outputs. See Table 1. FB_SEL 7 I, PU Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output. See Table 1. FB_IN 47 I, PD Feedback Clock Input. Connect to FB_OUT for accessing the PLL. REF_SEL 6 I, PU Reference Select Input. When high, the PECL clock is selected. And when low, TCLK is the reference clock. OE# 14 I, PD Output Enable Input. When asserted low, enables all of the outputs. When pulled high, disables to high impedance all of the outputs except FB_OUT. VDDA 37, 44 Power Supply for Bank A Clock Buffers VDDB 25, 32 Power Supply for Bank B Clock Buffers VDDC 13, 20 Power Supply for Bank C Clock Buffers VDD 5 Power Supply for Core AVDD 8 Power Supply for PLL. When AVDD is set low, PLL is bypassed. VSSA 36, 41 Common Ground for Bank A VSSB 24, 29 Common Ground for Bank B VSSC 12, 17 Common Ground for Bank C VSS 1, 48 Common Ground Pin Description A bypass capacitor (0.1F) should be placed as close as possible to each positive power pin (< 0.2"). If these bypass capacitors are not close to the pins, their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces. Document #: 38-07087 Rev. *B Page 2 of 7 Z9960 Function Table Control Pin REF_SEL 0 1 TCLK PECL_CLK AVDD PLL Bypass, Outputs Controlled by OE# PLL Power OE# Outputs Enabled Outputs Disabled (except FB_OUT) SELA Output Bank A at VCO/2 Output Bank A at VCO/4 SELB Output Bank B at VCO/2 Output Bank B at VCO/4 SELC Output Bank C at VCO/2 Output Bank C at VCO/4 FB_SEL Feedback Output at VCO/8 Feedback Output at VCO/12 Overview The Z9960 has an integrated PLL that provides low skew and low jitter clock outputs for high-performance microprocessors. Three independent banks of seven outputs as well as an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 400 MHz. This allows a wide range of output frequencies up to 200 MHz. The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by FB_SEL select inputs; refer to Table 1. The VCO frequency is then divided down to provide the required output frequencies. Zero Delay Buffer When used as a zero delay buffer the Z9960 will likely be in a nested clock tree application. For these applications the Z9960 offers a low-voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far-superior skew performance. The Z9960 then can lock onto the LVPECL reference and translate with near zero delay to low skew outputs. works to align the output edge, with the input reference edge thus producing a near-zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Because the static phase offset is a function of the reference clock, the Tpd of the Z9960 is a function of the configuration used. Absolute Maximum Ratings[2] Input Voltage Relative to VSS: .............................. VSS - 0.3V Input Voltage Relative to VDD: ..............................VDD + 0.3V Storage Temperature:................................. -65C to + 150C Operating Temperature: ............................... -40C to + 85C Maximum ESD Protection ............................................... 2kV Maximum Power Supply:................................................ 5.5V Maximum Input Current: ................................................. 20mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range VSS < (VIN or VOUT) < VDD. Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). By using one of the outputs as a feedback to the PLL, the propagation delay through the device is eliminated. The PLL Note: 2. The voltage on any input or I/O or pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Document #: 38-07087 Rev. *B Page 3 of 7 Z9960 DC Electrical Characteristics VDD = 2.5V 5%, TA = -40C to +85C Parameter Description Test Condition Min. Typ. Max. Unit VSS - 0.7 V VIL[3] Input Low Voltage VIH[3] Input High Voltage 1.7 - VDD V Peak-to-Peak Input Voltage PECL_CLK 500 - 1000 mV VDD -1.4 - VDD -0.6 V -120 A 120 A 0.6 V VPP VCMR[4] Common Mode Range PECL_CLK IIL[5] Input Low Current (@ VIL = VSS) [5] Input High Current (@ VIH = VDD) IIH VOL[6] Output Low Voltage VOH[6] IOL = 15 mA Output High Voltage IOH = -15 mA 1.8 IDD Quiescent Supply Current VDD and AVDD - 10 13 mA V CIN Input Pin Capacitance - 4 - pF Min. Typ. Max. Unit DC Electrical Characteristics VDD = 3.3V +5%, TA = -40C to +85C Parameter Description Test Condition [3] Input Low Voltage VSS - 0.8 V VIH[3] Input High Voltage 2.0 - VDD V Peak-to-Peak Input Voltage PECL_CLK 500 - 1000 mV VDD -1.4 - VDD -0.6 V -120 A VIL VPP VCMR[4] Common Mode Range PECL_CLK IIL[5] Input Low Current (@ VIL = VSS) IIH[5] Input High Current (@ VIH = VDD) VOL[6] Output Low Voltage [6] IOL = 24 mA 120 A 0.55 V Output High Voltage IOH = -24 mA 2.4 IDD Quiescent Supply Current VDD and AVDD - 15 20 mA CIN Input Pin Capacitance - 4 - pF VOH V Notes: 3. The LVCMOS inputs threshold is at 30% of VDD. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when HIGH input is within the VCMR range and the input lies within the VPP specification. 5. Inputs have pull-up/pull-down resistors that affect input current . 6. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines. Document #: 38-07087 Rev. *B Page 4 of 7 Z9960 AC Electrical Characteristics VDD = 2.5V 5% or 3.3V 5%, TA = -40C to +85C[7] Symbol Fref Parameter Reference Input Frequency FrefDC Fvco Tlock Tr / Tf Reference Input Duty Cycle PLL VCO Lock Range Maximum PLL lock Time Output Clocks Rise / Fall Time[8],[9] Fout Maximum Output Frequency Test Condition FB_SEL = 1 FB_SEL = 0 0.55V to 2.0V, VDD = 3.3V 0.5V to 1.8V, VDD = 2.5V Q (/2) Q (/4) FoutDC Output Duty Cycle[8],[9] tpZL, tpZH Output Enable Time[8] (all outputs) tpLZ, tpHZ Output Disable Time[8] (all outputs) TCCJ Cycle to Cycle Jitter[8],[9] Tskew Any Output to Any Output Skew[8],[9] Min. 16 25 25 200 Typ. 0.1 Max. 33 50 75 400 10 1.0 100 50 45 2 200 100 55 10 MHz 8 ns 50 2 +/- 100 Same frequency Different frequency Banks at different voltages Tskew Bank to Bank Skew Tskew(pp) Part to Part Skew[10] Tpd Phase ErTCLK or ror[8],[9] PECL_CLK to FB_IN VDD = 3.3V VDD = 2.5V 0 25 100 125 150 300 400 450 200 225 Unit MHz % MHz ms ns % ns ps ps ps ps ps Note: 7. Parameters are guaranteed by design and characterization. Not 100% tested in production. 8. Outputs loaded with 30pF each. 9. 50 transmission line terminated into VDD/2. 10. Part to Part skew at a given temperature and voltage Ordering Information Package Name Ordering Code Z9960AL 48 LQFP Package Type Industrial, -40C to +85C The ordering part number is formed by a combination of device number, device revision, package style, and screening, as shown below. Example: Cypress Z9960AL Date Code, Lot # Z9960AL Package L = LQFP Revision Device Number Document #: 38-07087 Rev. *B Page 5 of 7 Z9960 Package Diagram D D1 10 A1 A2 A L Symbol A A1 A2 48 Pin LQFP Outline Dimensions Inches Millimeters Min. Nom. Max. Min. Nom. Max. 0.063 1.60 0.002 0.006 0.05 0.15 0.053 0.057 1.35 1.45 e D D1 b e L b 0.007 0.354 0.276 0.011 0.02 BSC 0.018 0.030 0.17 9.00 7.00 0.27 0.50 BSC 0.45 0.75 PowerPC is a trademark of IBM(R). Pentium(R) is a trademark of Intel Corporation. All product or company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07087 Rev. *B Page 6 of 7 (c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Z9960 Document Title: Z9960 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer Document Number: 38-07087 Rev. ECN No. Issue Date Orig. of Change ** 107123 06/06/01 IKA Convert from IMI to Cypress *A 108715 11/07/01 NDP Updated AVDD Pin Functionality. *B 122772 12/21/02 RBI Add power up requirements to maximum ratings information Document #: 38-07087 Rev. *B Description of Change Page 7 of 7