2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buff er
Z9960
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07087 Rev. *B Revised December 21, 2002
Features
• 2.5V or 3.3V operation
• Output frequency up to 200 MHz
•Supports PowerPC, and Pentium® processors
•21 clock outputs: drive up to 42 clock lines
•LVPECL or LVCMOS/LVTTL clock input
•Output-to-output Sskew < 150 ps
•Split 2.5V/3.3V outputs
•Spread spec trum com patib le
•Glitch-free output clocks transitioning
•Output disable control
•Pin-com pati ble wit h MPC9 60 0
•Industrial temperature range: –40°C to +85°C
•48-pin LQFP package
Table 1. Frequency Table[1]
S
E
L
AQA
S
E
L
BQB
S
E
L
CQC
F
B
_
S
E
LFB_OUT
0 VCO/2 0 VCO/2 0 VCO/2 0 VCO/8
1 VCO/4 1 VCO/4 1 VCO/4 1 VCO/12
Note:
1. Input frequency range: 16 MHz to 33 MHz (FB_SEL = 1), or 25 MHz to 50
MHz (FB_SEL = 0).
/2
/4
/8
/12
REF_SEL
TCLK
PECL_CLK
PECL_CLK#
FB_IN
SELA
SELB
SELC
FB_SEL
OE#
FB_OUT
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
D Q
D Q
D Q
D Q
0
1
0
1
0
1
0
1
FB
C
B
A
0
1REF
FB
0
1
AVDD
PLL
Block Diagram Pin Configuration
Z9960
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
VSS
TCLK
PECL_CLK
PECL_CLK#
VDD
REF_SEL
FB_SEL
AVDD
SELA
SELB
SELC
VSSC
VDDC
OE#
QC6
QC5
VSSC
QC4
QC3
VDDC
QC2
QC1
QC0
VSSB
VSS
FB_IN
QA0
QA1
VDDA
QA2
QA3
VSSA
QA4
QA5
QA6
VDDA
VSSA
FB_OUT
QB0
QB1
VDDB
QB2
QB3
VSSB
QB4
QB5
QB6
VDDB
Z9960
Document #: 38-07087 Rev. *B Page 2 of 7
A bypass capacitor (0.1µF) should be placed as close as
pos sible to each po siti ve powe r pin (< 0.2”). If these bypass
capacitors are not close to the pins, their high-frequency
filter ing ch aracte ristic will be c ance lled by the le ad indu ctanc e
of the traces.
Pin Definitions
Pin Name Pin No. Pin
Type Pin Description
PECL_CLK 3 I, PD PECL Clock Input.
PECL_CLK# 4 I, PU PECL Clock Input.
TCLK 2 I, PD External Reference/Test Clock In put.
QA(6:0) 38, 39, 40,
42, 43, 45, 46 O
VDDA Clock Outputs. See Table 1 for frequency selections.
QB(6:0) 26, 27, 28,
30, 31, 33, 34 O
VDDB Clock Outputs. See Table 1 for frequency selections.
QC(6:0) 15, 16, 18,
19, 21, 22, 23 O
VDDC Clock Outputs. See Table 1 for frequency selections.
FB_OUT 35 O
VDD Feedback Clock Output. Connect to FB_IN for no rmal operation. The divider
ratio for this output is set by FB_SEL; see Table 1. A bypass delay capacitor
at this outp ut wil l control Input Refere nce/ Ou tput Banks ph ase relatio nship s.
SELA 9 I, PU Frequency Sele ct Inputs. These inputs select the divider rat io at QA(0:6)
outputs. See Table 1.
SELB 10 I, PU Frequency Select Inputs. These inputs select the divider rat io at QB(0:6)
outputs. See Table 1.
SELC 11 I, PU Frequency Sele ct Inputs. These i nputs select the divider ratio at QC(0:6)
outputs. See Table 1.
FB_SEL 7 I, PU Feedback Select Inputs. These inputs select the divide ratio at FB_OUT
output. See Table 1.
FB_IN 47 I, PD Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
REF_SEL 6 I, PU Reference Select Input. When high, the PECL clock is selected. And when
low, TCLK is the reference clock.
OE# 14 I, PD Output Enable Input. When asserted low, enables all of the outputs. When
pulled high, disables to high impedance all of the outputs except FB_OUT.
VDDA 37, 44 Power Supply for Bank A Clock Buffers
VDDB 25, 32 Power Supply for Bank B Clock Buffers
VDDC 13, 20 Power Supply for Bank C Clock Buffers
VDD 5 Pow er Supply for Core
AVDD 8Power Supply for PLL. When AVDD is set low, PLL is bypassed.
VSSA 36, 41 Common Ground for Bank A
VSSB 24, 29 Common Ground for Bank B
VSSC 12, 17 Common Ground for Bank C
VSS 1, 48 Common Ground
Z9960
Document #: 38-07087 Rev. *B Page 3 of 7
Overview
The Z9960 has an integrated PLL th at p r ov ide s low s k ew an d
low jitt er clock outputs for high-perform ance microp rocessors.
Three independent banks of seven outputs as well as an
independent PLL feedback output, FB_OUT, provide excep-
tional flexibility for possible output configurations. The PLL is
ensured stable operation given that the VCO is configured to
run between 200 MHz to 400 MHz. This allows a wide range
of output frequencies up to 200 MHz.
The phas e detec tor com pares the in put refere nce cl ock to th e
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OU T. The inte rnal VCO is running at mult iples of the input
reference clock set by FB_SEL select inputs; refer to Table 1.
The VCO frequency is then divided down to provide the
required output frequencies.
Zero Delay Buffer
When used as a z ero d elay buf f er the Z99 60 w il l li ke ly be i n a
nested clock tree application. For these applications the
Z9960 offers a low-voltage PECL clock input as a PLL
referenc e. This allo ws the us er to use LVPECL as the primary
clock distribution device to take advantage of its far-superior
skew performance. The Z9960 then can lock onto the LVPECL
reference and translate with near zero delay to low skew
outputs.
By using one of the outputs as a feedback to the PLL, the
propagation delay through the device is eliminated. The PLL
works to align the output edge, with the input reference edge
thus producing a near-zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between the inputs and outputs. Because the static
phase of fset is a func tion of the referen ce clock, the Tpd of th e
Z9960 is a function of the configuration used.
Absolute Maximum Ratings[2]
Input Voltage Relative to VSS:..............................VSS – 0.3V
Input Voltage Relative to VDD:..............................VDD + 0.3V
Stora ge Tempe ratu re:.................... ...... ...... .-65°C to + 150°C
Operating Temperature: ............................... -40°C to + 85°C
Maximum ESD Protection............................................... 2kV
Maximum Power Supply:................................................5.5V
Maximum Input Current: .................................................± 20mA
This device contains circuitry to protect the inputs against
damage due to high st atic vo ltages or elec tric fie lds; ho wever,
precautions should be taken to avoid application of any
voltage higher than the maximum rated vol tages to this c ircuit.
For proper operation, VIN and VOUT should be constrained to
the range VSS < (VIN or VOUT) < VDD.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
Note:
2. The voltage on any input or I/O or pin cannot exceed the power pin during
power-up. Power supply sequencing is NOT required.
Function Table
Control Pin 0 1
REF_SEL TCLK PECL_CLK
AVDD PLL Bypass, Out puts Cont roll ed by OE # PLL Power
OE# Outputs Enabled Outputs Disabled (except FB_OUT)
SELA Output Bank A at VCO/2 Output Bank A at VCO/4
SELB Output Bank B at VCO/2 Output Bank B at VCO/4
SELC Output Bank C at VCO/2 Output Bank C at VCO/4
FB_SEL Feedback Output at VCO/8 Feedback Output at VCO/12
Z9960
Document #: 38-07087 Rev. *B Page 4 of 7
DC Electrical Characteristics VDD = 2.5V ±5%, TA = –40°C to +85°C
Parameter Description Test Condition Min. Typ. Max. Unit
VIL[3] Input Low Voltage VSS -0.7V
VIH[3] Input High Voltage 1.7 - VDD V
VPP Peak-to-Peak Input Voltage
PECL_CLK 500 - 1000 mV
VCMR[4] Common Mode Range
PECL_CLK VDD –1.4 - VDD –0.6 V
IIL[5] Input Low Current (@ V IL = VSS)–120 µA
IIH[5] Input High Current (@ VIH = VDD) 120 µA
VOL[6] Output Low Voltage IOL = 15 mA 0.6 V
VOH[6] Output High Voltage IOH = –15 mA 1.8 V
IDD Quiesce nt Supp ly Current VDD and AVDD -1013mA
CIN Input Pin Capacitance - 4 - pF
Notes:
3. The LVCMOS input s threshold is at 30% of VDD.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when HIGH input is within the VCMR range
and the input lies within the VPP specification.
5. Inputs have pull-up/pull-down resistors that affect input current .
6. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
DC Electrical Characteristics VDD = 3.3V +5%, TA = –40°C to +85°C
Parameter Description Test Condition Min. Typ. Max. Unit
VIL[3] Input Low Voltage VSS -0.8V
VIH[3] Input High Voltage 2.0 - VDD V
VPP Peak-to-Peak Input Voltage
PECL_CLK 500 - 1000 mV
VCMR[4] Common Mode Range PECL_CLK VDD –1.4 - VDD –0.6 V
IIL[5] Input Low Current (@ VIL = VSS)–120 µA
IIH[5] Input High Current (@ VIH = VDD) 120 µA
VOL[6] Output Low Voltage IOL = 24 mA 0.55 V
VOH[6] Output High Voltage IOH = –24 mA 2.4 V
IDD Quiescent Supply Current VDD and AVDD -1520mA
CIN Input Pin Capa cit anc e - 4 - pF
Z9960
Document #: 38-07087 Rev. *B Page 5 of 7
AC Electrical Characteristics VDD = 2.5V ±5% or 3.3V ±5%, TA = –40°C to +85°C[7]
Symbol Parameter Test Condition Min. Typ. Max. Unit
Fref Reference Input Frequency FB_SEL = 1 16 33 MHz
FB_SEL = 0 25 50
FrefDC Reference Input Duty Cycle 25 75 %
Fvco PLL VCO Lock Range 200 400 MHz
Tlock Maximum PLL lock Time 10 ms
Tr / Tf Output Clocks Rise / Fall
Time[8],[9] 0.55V to 2.0V, VDD = 3.3V 0.1 1.0 ns
0.5V to 1.8V, VDD = 2.5V
Fout Maximum Output Frequency Q (÷2) 100 200 MHz
Q (÷4) 50 100
FoutDC Output Duty Cycle[8],[9] 45 50 55 %
tpZL, tpZH Output Enable Time[8] (all out-
puts) 210ns
tpLZ, tpHZ Output Disable Time[8] (all out-
puts) 28ns
TCCJ Cycle to Cycle Jitter[8],[9] +/- 100 ps
Tskew Any Output to Any Output
Skew[8],[9] Same frequency 150 ps
Different frequency 300
Tskew Bank to Bank Skew Banks at different voltages 400 ps
Tskew(pp) Part to Part Skew[10] 450 ps
Tpd Phase Er-
ror[8],[9] TCLK or
PECL_CLK to
FB_IN
VDD = 3.3V 0 100 200 ps
VDD = 2.5V 25 125 225
Note:
7. Parameters are guaranteed by design and characterization. Not 100% tested in production.
8. Outputs loaded with 30pF each.
9. 50Ω transmission line terminated into VDD/2.
10. Part to Part skew at a given temperature and voltage
Ordering Information
Ordering Code Package
Name Package Type
Z9960AL 48 LQFP Industrial, -40°C to +85°C
The ordering part number is formed by a combination
of device number, device revision, package style,
and screening, as shown below.
Example: Cypress
Z9960AL
Date Code, Lot #
Z9960AL
Package
L = LQFP
Revision
Device Nu mber
Z9960
Document #: 38-07087 Rev. *B Page 6 of 7
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Semi conductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
PowerPC i s a trad emark of IBM ®. Pentium ® is a trademark of Int el Corporati on. All produc t or company na mes mentio ned in this
document are the trademarks of their respective holders.
Package Diagram
D
D1
A2
b
e
10°
A
L
A1
48 Pin LQFP Outline Dimensions
Inches Millimeters
Symbol Min. Nom. Max. Min. Nom. Max.
A - - 0.063 - - 1.60
A10.002 - 0.006 0.05 - 0.15
A2 0.053 - 0.057 1.35 - 1.45
D-0.354--9.00-
D1- 0.276 - - 7.00 -
b 0.007 - 0.011 0.17 - 0.27
e 0.02 BSC 0.50 BSC
L 0.018 - 0.030 0.45 - 0.75
Z9960
Document #: 38-07087 Rev. *B Page 7 of 7
Document Title: Z9960 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer
Document Number: 38-07087
Rev. ECN No. Issue
Date Orig. of
Change Description of Change
** 107123 06/06/01 IKA Convert from IMI to Cypress
*A 108715 11/07/01 NDP Updated AVDD Pin Functionality.
*B 122772 12/21/0 2 RB I Add power up require me nts to maxim um ratings informa tio n
