PRELIMINARY
18-Mbit (512K x 36/1Mbit x 18)
Pipelined Register-Register Late Write
CY7C1330AV25
CY7C1332AV25
Cypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600
Document No: 001-07844 Rev . *A Revised September 20, 2006
Features
Fast clock speed: 250, 200 MHz
Fast access time: 2.0, 2.25 ns
Synchronous Pipelined Operation with Self-timed Late
Write
Internally synchronized registered outpu ts eliminate
the need to control OE
2.5V core supply voltage
1.4–1.9V VDDQ supply with VREF of 0.68–0.95V
Wide range HSTL I/O Levels
Single Differential HSTL clock Input K and K
•Single WE (READ/WRITE) control pin
Individual byte write (BWS[a:d]) con tr ol (m ay be tied
LOW)
Common I/O
Asynchronous Output Enable Input
Programmable Imp edance Output Drivers
JTAG boundary sca n for BGA packaging version
Available in a 119-b all BGA package (CY7C1330AV25
and CY7C1332AV 25)
Configuration
CY7C1330AV25 – 512K x 36
CY7C1332AV25 – 1M x 18
Functional Description
The CY7C1330AV25 and CY7C1332AV25 are high perfor-
mance, Synchronous Pipelined SRAMs designed with late
write operation. These SRAMs can achieve speeds up to 250
MHz. Each memory cell consists of six transistors.
Late write feature avoids an idle cycle required during the
turnaround of the bus from a read to a write.
All synchronous inputs are gated b y registers controlled by a
positive-edge-triggered Clock Input (K). The synchronous
inputs include all addresses (A), all data inputs (DQ[a:d]), Chip
Enable (CE), Byte Write Selects (BWS[a:d]), and read-write
control (WE). Read or Write Operations can be initiated with
the chip enable pin (CE). This signal allows the user to
select/deselect the device when desire d.
Power down feature is accomplished by pulling the
Synchronous signal ZZ HIGH.
Output Enable (OE) is an asynchronous input signal. OE can
be used to disable the outputs at any given ti me.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operati on.
K,K
A
x
WE
BWS
x
CE
OE
512Kx36
Logic Block Diagram
DQ
x
Data-In REG.
Q
D
CE
CONTROL
and WRITE
LOGIC
ZZ
1Mx18
OUTOUT
REGISTERS
and LOGIC
512Kx36
1Mx18
AXDQXBWSX
X = 18:0
X = 19:0 X = a, b
X = a, b, c, d
X = a, b
X = a, b, c, d
Clock
Buffer
MEMORY
ARRAY
(2stage)
PRELIMINARY CY7C1330AV25
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 2 of 19
Selection Guide
CY7C1330AV25-250
CY7C1332AV25-250 CY7C1330AV25-200
CY7C1332AV25- 200 Unit
Maximum Access T i me 2.0 2.25 ns
Maximum Operating Current 600 550 mA
Maximum CMOS Standby Current 280 260 mA
Pin Configurations
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DQa
VDDQ
NC
NC
DQc
DQd
DQc
DQd
AA AANC VDDQ
AA
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
A
DQc
DQc
DQd
DQd
TMS
VDD
A
NC
DQd
A
A
NC A A NC
VDD AANC
VSS VSS
ZQ DQbDQb
DQb
DQa
DQb
DQb
DQa
DQa
NCTDI TDO VDDQ
TCK
VSS
VSS
VSS
VREF
VSS
VSS
VSS
VSS
M1
CE VSS
OE VSS VDDQ
BWScNC VSS
NC VDDQ
VDD VREF VDD
VSS
K
KBWSa
WE VSS VDDQ
VSS
ZZ
NC
NC
A
A
A0
A1 VSS
VDD M2
CY7C1330AV25 (512K x 36)
DQcDQb
A
DQcDQb
DQc
DQcDQc
DQbDQb
DQaDQa
DQa
DQa
DQa
DQdDQd
DQd
DQd
BWSd
119
-
B
a
ll
BGA
(14
x
22
x
2
.
4
mm
)
BWSb
CY7C13 32 AV 2 5 (1 M x 18 )
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DQa
VDDQ
NC
NC
DQb
DQb
DQb
DQb
AA AANC VDDQ
AA
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
A
DQb
DQb
DQb
DQb
TMS
VDD
A
A
DQb
A
A
NC A A NC
VDD AANC
VSS VSS
ZQ DQaDQa
DQa
DQa
DQa
DQa
DQa
DQa
NCTDI TDO VDDQ
TCK
VSS
VSS
VSS
VREF
VSS
VSS
VSS
VSS
M1
CE VSS
OE VSS VDDQ
BWSbNC VSS
NC VDDQ
VDD VREF VDD
VSS
K
KBWSa
WE VSS VDDQ
VSS
ZZ
NCA
A
A0
A1 VSS
VDD M2
NC NC
NC A
NC NC
NC
NC NC NC NC
NC NC
NC
NC
NC
NC NC
NC NC
NC
NC
PRELIMINARY CY7C1330AV25
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 3 of 19
Pin Definitions
Name I/O Type Description
A Input-
Synchronous Address Inputs used to select one of the address locations. Sampled at the rising
edge of the K.
BWSa
BWSb
BWSc
BWSd
Input-
Synchronous Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWSa controls DQa, BWSb controls DQb,
BWSc controls DQc, BWSd controls DQd.
WE Input-
Synchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to initiate a write sequence and high to initiate a read sequence.
K,K Input-
Differential Clock Clock Inputs. Used to capture all synchronous inputs to the device.
CE Input-
Synchronous Chip Enable Input, active LOW. Sampled on the rising edge of CLK. Used to
select/deselect the device.
OE Input-
Asynchronous Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state and when the device has been
deselected.
DQa
DQb
DQc
DQd
I/O-
Synchronous Bidirectional Data I /O lines. As input s, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A[x:0] during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE and the internal control logic. When OE is
asserted LOW , the pins can behave as outputs. When HIGH, DQa–DQd are placed in
a tri-state condition. The outputs are automatically tri-stated during the data portion of
a write sequence, during the first clock when emerging fro m a deselected state, and
when the device is deselected, regardless of the state of OE. DQ a,b,c,d are 9 bits wide
M1, M2Read Protocol Mode
Pins Mode control pins, used to set the proper read protocol. For specified device
operation, M1 must be connected to VSS, and M2 must be connected to VDD or VDDQ.
These mode pins must be set at power-up and cannot be changed during device
operation.
ZZ Input-
Asynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved.
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to
the system data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where
RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to VDDQ, which enables the minimum impedance mode. This pin
cannot be connected directly to GND or left unconnected.
VDD Power Supply Power supply inputs to the core of the device. For this device, the VDD is 2.5V.
VDDQ I/O Power Supply Power supply for the I/O circuitry. For this device, the VDDQ is 1.5V.
VREF Input-
Reference Voltage Reference Voltage Input. S tatic input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
VSS Ground Ground for the device. Should be connected to ground of the system.
TDO JTAG serial output
Synchronous Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
TDI JTAG serial input
Synchronous Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
TMS Test Mode Select
Synchronous This pin controls the Test Access Port state machine. Sampled on the rising edge
of TCK.
TCK JTAG serial clock Serial clock to the JTAG circuit.
NC No connects.
PRELIMINARY CY7C1330AV25
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 4 of 19
Introduction
Functional Overview
The CY7C1330AV25 and CY7C1332AV25 are synchronous-
pipelined Late Write SRAMs running at speeds up to 250 MHz.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 2.0 ns
(250-MHz device).
Accesses can be initiated by asserting Chip Enable (CE) on
the rising edge of the clock. The address presented to the
device will be latched on this edge of the clock. The access
can either be a read or write operation, depending on the
status of the Write Enable (WE). BWS[d:a] can be used to
conduct individual byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed late
write circuitry.
All operations (Reads, Writes, and Deselects) are pipelined.
Pipelined Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) Chip Enable (CE) is asserted active
and (2) the Write Enable input signal (WE) is asserted HIGH.
The address presented to the address inputs is latched into
the Address Register and presente d to the me mory core and
control logic. The contro l logic determines th at a read a ccess
is in progress and allows the req uested data to propagate to
the input of the output register. At the rising edge of the next
clock the requested data is allowed to p ropagate through the
output register and on to the d ata bus within 2.0 ns (250-MHz
device) provided OE is active LOW. After the first clock of the
read access the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. During the second
clock, a subsequent operation (Read/Write/Deselect) can be
initiated. Deselecting the device is also pipelined. Therefore,
when the SRAM is deselected at clock rise by one of the chip
enable signals, i ts output will tri-state following the next clo ck
rise.
Bypass Read Operation
Bypass read operation occurs when the last write operation is
followed by a read operation where write and read addresses
are identical. The data outputs are provided from the data in
registers rather than the memory array. This operation occurs
on a byte to byte basis. If only one byte is written during a write
operation and a read operation is performed on the same
address; then a partial bypass read operation is performed
since the new byte data will be from the datain registers while
the remainin g bytes are from the memory array.
Late Write Acces s es
The Late Write feature allows for the write data to be presented
one cycle later after the access is started. This feature elimi-
nates one bus-turnaround cycle which is necessary when
going from a read to a write in an ordinary pipelined
Synchronous Burst SRAM.
Write access is initiated when the following conditions are
satisfied at clock rise: (1) CE is asserted active and (2) the
write signal WE is asserted LOW. The address presented to
Ax is loaded into th e Address Register. The write signals are
latched into the Control Logi c block.
The data lines are automatically tri-stated regardless of the
state of the OE input signal when a write is detected. This
allows the external log ic to present the data on DQ and DQP
(DQ[a:b] for CY7C1332AV25 and DQ[a:d] for CY7C1330AV25).
In addition, the address for the subsequent access
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ (or a subset
for byte write operations, see Write Cycle Description table for
details) inputs is latched into the device and the write is
complete.
The data written during the Write operation is controlled by
BWS (BWS[a:d] for CY7C1330AV25 and BWS[a:b] for
CY7C1332AV25) signals. The CY7C1330AV25 and
CY7C1332A V25 provide byte write capability that is described
in the Write Cycle Description table. Asserting the Write
Enable input (WE) with th e selected Byte Write Select (BWS )
input will selective ly write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
Synchronous self-timed write mechan ism has been provided
to simplify the write operations. Byte write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write opera-
tions.
Because the CY7C1330AV25/CY7C1332AV25 is a common
I/O device, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQ inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQ is
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Power-up/Power-down Supply Voltage Sequencing
The power-up and power-down supply voltage application
recommendations are as follows:
Power-up: VSS, VDD, VDDQ, VREF, VIN.
Power-down: VIN, VREF, VDDQ, VDD, VSS.
VDDQ can be applied/removed simultaneously with VDD as
long as VDDQ doe s not exceed VDD by more than 0.5V.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±10% is between 175 and 350, with
VDDQ=1.5V. The output impedance is adjusted every 1024
cycles to adjust for drifts in supply voltage and temper-
ature.The output buffers can also be programmed in a
minimum impedance configuration by connecting ZQ to VDD.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. T wo
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
PRELIMINARY CY7C1330AV25
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 5 of 19
guaranteed. The d evice must be deselecte d prior to entering
the “sleep” mode. CE must remain inactive for the duration of
tZZREC after the ZZ input returns LOW.
Cycle Description Truth Table[1, 2, 3, 4, 5]
Operation Address Used CE WE BWSxCLK ZZ Comments
Deselected External 1 X X L-H 0 I/Os tri-state following next recognized clock.
Begin Read External 0 1 X L-H 0 Address latched. Data driven out on the next rising edge of the clock.
Begin Write External 0 0 Valid L-H 0 Address latched, data presented to the SRAM on the next rising
edge of the clock.
Sleep Mode - X X X X 1 Power down mode.
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
IDDZZ Snooze mode standby current ZZ > VIH 128 mA
tZZS Device operation to ZZ ZZ > VIH 2tCYC ns
tZZREC ZZ recovery time ZZ < VIL 2tCYC ns
Write Cycle Descriptions[1, 2]
Function (CY7C1330AV25) WE BWdBWcBWbBWa
Read 1 X X X X
Wr i te Byte 0 – D Qa01110
Wr i te Byte 1 – D Qb01101
Write Bytes 1, 0 0 1 1 0 0
Wr i te Byte 2 – D Qc01011
Write Bytes 2, 0 0 1 0 1 0
Write Bytes 2, 1 0 1 0 0 1
Write Bytes 2, 1, 0 0 1 0 0 0
Wr i te Byte 3 – D Qd00111
Write Bytes 3, 0 0 0 1 1 0
Write Bytes 3, 1 0 0 1 0 1
Write Bytes 3, 1, 0 0 0 1 0 0
Write Bytes 3, 2 0 0 0 1 1
Write Bytes 3, 2, 0 0 0 0 1 0
Write Bytes 3, 2, 1 0 0 0 0 1
Write All Bytes 0 0 0 0 0
Abort Write All Bytes 0 1 1 1 1
Write Cycle Descriptions[1, 2]
Function (CY7C1332AV25) WE BWbBWa
Read 1 X X
Wr i te Byte 0 – D Qa 010
Wr i te Byte 1 – D Qb 001
Write All Bytes 0 0 0
Abort Write All Bytes 0 1 1
Notes:
1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW . BWSx = 0 sig nifies at least one Byt e W rite Select is a ctive, BWSx = Valid signifies that the desired byte write
selects are asserted, see Write Cycle Description table f or details.
2. Write is defined by WE and BWSx. See Write Cycle Description table for details.
3. The DQ pins are controlled by the current cycle and the OE signal.
4. Device will power-up deselected and the I/Os in a tri-st ate condition, regardless of OE.
5. OE assumed LOW.
PRELIMINARY CY7C1330AV25
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 6 of 19
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This port operates in accor-
dance with IEEE Standard 1 149.1-1900 but does not have the
set of functions require d for full 1149.1 complian ce. The TAP
operates using JEDEC standard 1.8V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the T AP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected i f the TAP is n ot used. The pin is
pulled up internally, resu lting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loa ded into th e TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internall y pulled up and can
be unconnected if the TAP is un used i n an appli cation. T DI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Registers
Registers are connected betwe en the TDI and TD O pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only on e register can be selected at a time thro ugh
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Da ta is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed betw een the
TDI and TDO pins as shown in T AP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level seri al test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is mo ved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update -IR state.
PRELIMINARY CY7C1330AV25
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 7 of 19
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the T AP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the T AP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during th e Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable st ate). This will not harm
the device, but there is no guarante e as to the value that will
be captured. Repeatable results may not be possible.
To guarante e th at the boun dary scan register will capture the
correct value of a signal, the SRAM signa l must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). T he SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
PRELIMINARY CY7C1330AV25
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 8 of 19
Note:
6. The 0/1 next to each state re presents the value at TMS at the rising edge of TCK.
TAP Controller State Diagram[6]
TEST-LOGIC
RESET
TEST-LOGIC/
IDLE SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
01
1
0
1
0
1
0
0
0
1
1
1
0
10
10
0
0
1
0
1
1
0
1
0
0
1
1
0
PRELIMINARY CY7C1330AV25
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 9 of 19
TAP Controller Block Diagram
TAP Electrical Characteristics Over the Operating Range[7, 8, 9]
Parameter Description Test Conditions Min. Max. Unit
VOH1 Output HIGH Voltage IOH =2.0 mA 1.7 V
VOH2 Output HIGH Voltage IOH =100 µA2.1 V
VOL1 Output LOW Voltage IOL = 2.0 mA 0.7 V
VOL2 Output LOW Voltage IOL = 100 µA0.2V
VIH Input HIGH Voltage 1.7 VDD + 0.3 V
VIL Input LOW Voltage –0.3 0.7 V
IXInput and Output Load Current GND VI VDD –5 5 µA
TAP AC Switching Characteristics Over the Operating Range [10, 11]
Parameter Description Min. Max. Unit
tTCYC TCK Clock Cycle Time 50 ns
tTF TCK Clock Frequency 20 MHz
tTH TCK Clock HIGH 20 ns
tTL TCK Clock LOW 20 ns
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise 5 ns
tTDIS TDI Set-up to TCK Clock Rise 5 ns
tCS Capture Set-up to TCK Rise 5 ns
Hold Times
tTMSH TMS Hold after TCK Clock Rise 5 ns
tTDIH TDI Hold after Clock Rise 5 ns
Notes:
7. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
8. Input waveform should have a slew rate of > 1 V/ns.
9. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
10.tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test condit i ons. tR/tF = 1 ns.
0
012..
29
3031
Boundary Scan Register
Identification Register
012..
.
.106
012
Instruction Register
Bypass Register
Selection
Circuitry Selection
Circuitry
TAP Controller
TDI TDO
TCK
TMS
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CY7C1332AV25
Document No: 001-07844 Rev. *A Page 10 of 19
tCH Capture Hold after Clock Rise 5 ns
Output Times
tTDOV TCK Clock LOW to TDO Valid 10 ns
tTDOX TCK Clock LOW to TDO Invalid 0 ns
TAP Timing and Test Conditions[11]
TAP AC Switching Characteristics Over the Operating Range (continued)[10, 11]
Parameter Description Min. Max. Unit
(a)
TDO
CL= 20 pF
Z0= 50
GND
1.25V
50
2.5V
0V
ALL INPUT PULSES
1.25V
Test Clock
Test Mode Select
TCK
TMS
Test Data-In
TDI
Test Data-Out
tTCYC
tTMSH
tTL
tTH
tTMSS
tTDIS tTDIH
tTDOV tTDOX
TDO
Identification Register Definitions
Instruction Field Value DescriptionCY7C1330AV25 CY7C1332AV25
Revision Number (31:29) 000 000 Version number.
Cypress Device ID (28:12) 01011110101100101 01011110101010101 Defines the type of SRAM.
Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor.
ID Register Presence (0) 1 1 Indicates the presence of an ID register.
PRELIMINARY CY7C1330AV25
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 11 of 19
Scan Register Sizes
Register Name Bit Size—CY7C1330AV25 Bit Size—CY7C1332AV25
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary Scan 70 51
Instruction Codes
Instruction Code Description
EXTEST 000 Captures the Input/Output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operati on does not affect SRAM operation.
SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register betwe en
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Doe s not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
Boundary Scan Order (1 Mbit x 18)
Bit # Bump ID Bit # Bump ID Bit # Bump ID
15R 187E 351H
26T 196D 363G
34P 206A 374D
46R 216C 384E
55T 225C 394G
67T 235A 404H
77P 246B 414M
86N 255B 422K
96L 263B 431L
10 7K 27 2B 44 2M
11 5L 28 3A 45 1N
12 4L 29 3C 46 2P
13 4K 30 2C 47 3T
14 4F 31 2A 48 2R
15 6H 32 1D 49 4N
16 7G 33 2E 50 2T
17 6F 34 2G 51 3R
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CY7C1332AV25
Document No: 001-07844 Rev. *A Page 12 of 19
Boundary Scan Order (512K x 36)
Bit # Bump ID Bit # Bump ID Bit # Bump ID
15R 256F 492H
24P 267E 501H
34T 276E 513G
46R 287D 524D
55T 296D 534E
67T 306A 544G
76P 316C 554H
87P 325C 564M
96N 335A 57 3L
10 7N 34 6B 58 1K
11 6M 35 5B 59 2K
12 6L 36 3B 60 1L
13 7L 37 2B 61 2L
14 6K 38 3A 62 2M
15 7K 39 3C 63 1N
16 5L 40 2C 64 2N
17 4L 41 2A 65 1P
18 4K 42 2D 66 2P
19 4F 43 1D 67 3T
20 5G 44 2E 68 2R
21 7H 45 1E 69 4N
22 6H 46 2F 70 3R
23 7G 47 2G
24 6G 48 1G
PRELIMINARY CY7C1330AV25
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 13 of 19
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied........................................... –55°C to +125°°C
Supply Voltage on VDD Relative to GND........–0.5V to +2.9V
Supply Voltage on VDDQ Relative to GND. .....–0.5V to +VDD
DC Voltage Applied to Outputs
in High-Z S tate[7]................................. –0.5V to VDDQ + 0.5V
DC Input Voltage[7] .............. ... ...............–0.5V to V DD + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage...........................................> 1500V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range Ambient
Temperature VDD VDDQ
Com’l 0°C to +70°C 2.37V to 2.63V 1.4V to 1.9V
Electrical Characteristics Over the Operating Range
DC Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
VDD Power Supply Voltage 2.37 2.63 V
VDDQ I/O Supply Voltage 1.4 1.9 V
VOH1 Output HIGH Voltage[12] Programmable Impedance Mode[14] VDDQ/2 VDD V
VOL1 Output LOW Voltage[13] Programmable Impedance Mode[14] VSS VDDQ/2 V
VOH2 Output HIGH Voltage IOH = –0.1 mA, Minimum Impedance Mode[15] VDDQ – 0.2 VDDQ V
VOL2 Output LOW Voltage IOL = 0.1 mA, Minimum Impedance Mode[15] VSS 0.2 V
VOH3 Output HIGH Voltage IOH = –6.0 mA, Minimum Impedance Mode[15] VDDQ – 0.4 VDDQ V
VOL3 Output LOW Voltage IOL = 6.0 mA, Minimum Impedance Mode[15] VSS 0.4 V
VIH Input HIGH Voltage VREF + 0.1 VDDQ + 0.3 V
VIL Input LOW Voltage[7] –0.3 VREF – 0.1 V
IXInput Leakage Current GND VI VDDQ –1 1 mA
IOZ Output Leakage Current GND VI VDDQ, Output Disabled –1 1 mA
VREF Input Reference Voltage Typical value = 0.75V 0.68 0.95 V
VIN–CLK Clock Input Reference
Voltage –0.3 VDDQ + 0.3 V
VDIF–CLK Clock Input Differential
Voltage 0.1 VDDQ + 0.3 V
VCM–CLK Clock Common Mode
Voltage Typical Value =0.75V 0.55 0.95 V
IDD VDD Operating Supply VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC 250 MHz 600 mA
200 MHz 550 mA
ISB1 Automatic CE
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN > VIH or VIN < VIL
f = fMAX = 1/tCYC
250 MHz 280 mA
200 MHz 260 mA
AC Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
VIH Input HIGH Voltage VREF + 0.2 V
VIL Input LOW Voltage VREF – 0.2 V
Notes:
12.IOH = (VDDQ/2)/(RQ/5)+15% for 175 < RQ < 350.
13.IOL = (VDDQ/2)/(RQ/5)+15% for 175 < RQ < 350.
14.Programmable Impedance Output Buffer Mode. The ZQ pin is connected to VSS through RQ.
15.Minimum Impedance Output Buffer Mode: The ZQ pin is connected directly to VSS or VDD.
16.TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
PRELIMINARY CY7C1330AV25
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 14 of 19
AC Test Loads and Waveforms
Notes:
17.Tested initially and after any design or process change that may affect these parameters.
18.Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
Capacitance[17]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 2.5V
VDDQ = 1.5V
5pF
CCLK Clock Input Capacitance 6 pF
CI/O Input/Output Capacitance 7 pF
Thermal Resistance[17]
Parameter Description Test Conditions BGA Typ. Unit
ΘJA Thermal Resistance
(Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit board 19.7 °C/W
ΘJC Thermal Resistance
(Junction to Case) 6.0 °C/W
1.25V
0.25V
R = 50
5pF
ALL INPUT PULSES
Device RL= 50
Z0= 50
VREF = 0.75V
VREF = 0.75V
[18]
0.75V
Under
Test
0.75V
Device
Under
Test
OUTPUT
0.75V
VREF
VREF
OUTPUT
ZQ
ZQ
(a)
Slew Rate = 2 V/ns
RQ =
250
(b)
RQ =
250
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CY7C1332AV25
Document No: 001-07844 Rev. *A Page 15 of 19
Switching Characteristics[18, 19, 20, 21]
Parameter Description
250 200
UnitMin. Max. Min. Max.
tPower VCC (typical) to the First Access Read or Write[22] 11ms
Clock
tCYC Clock Cycle Time 4.0 5.0 ns
FMAX Maximum Operating Frequency 250 200 MHz
tCH Clock HIGH 1.5 1.5 ns
tCL Clock LOW 1.5 1.5 ns
Output Times
tCO Data Output Valid After CLK Rise 2.0 2.25 ns
tEOV OE LOW to Output Valid[17, 19, 21] 2.0 2.25 ns
tDOH Data Output Hold After CLK Rise 0.5 0.5 ns
tCHZ Clock to High-Z[17, 18, 19, 20, 21] 2.0 2.25 ns
tCLZ Clock to Low-Z[17, 18, 19, 20, 21] 0.5 0.5 ns
tEOHZ OE HIGH to Output High-Z[18, 19, 21] 2.0 2.25 ns
tEOLZ OE LOW to Output Low-Z[18, 19, 21] 0.5 0.5 ns
Set-Up Times
tAS Address Set-Up Before CLK Rise 0.3 0.3 ns
tDS Data Input Set-Up Before CLK Rise 0.3 0.3 ns
tWES WE, BWSx Set-Up Before CLK Rise 0.3 0.3 ns
tCES Chip Select Set-Up 0.3 0.3 ns
Hold Times
tAH Address Hold After CLK Rise 0.6 0.6 ns
tDH Data Input Hold After CLK Rise 0.6 0.6 ns
tWEH WE, BWx Hold After CLK Rise 0.6 0.6 ns
tCEH Chip Select Hold After CLK Rise 0.6 0.6 ns
Notes:
19.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
20.At any given voltage and temperature, tEOHZ is less than t EOLZ and tCHZ is less than tCLZ to el iminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imp ly a bu s co ntention condition, but r efl ect parameters gu aran tee d over worst ca se user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21.This parameter is sampled and not 100% tested.
22.This part has a volt age reg ulator that steps do wn the volt age interna lly; tPower i s the time power ne eds to be suppl ied above VDD minimum initially be fore a read
or write operation can be initiated.
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CY7C1332AV25
Document No: 001-07844 Rev. *A Page 16 of 19
Switching Waveforms
READ/WRITE/DESELECT Sequence (OE Controlled)[23, 24, 25, 26]
Notes:
23.The combination of WE and BWSx (x = a, b, c, d for x36 and x = a, b for x18) define a write cycle (see Write Cycle Description table).
24.All chip enables need to be active in order to select the device. Any chip enable can deselect the device.
25.RAx stands for Read Address X, WAx Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X.
26.CE held LOW.
K
ADDRESS
WE
Data
In/Out
tCYC
tCH tCL
RA1
tAH
tAS
tWEStWEH
tCO
Q1
= DON’T CARE = UNDEFINED
Out D2
In
READ
WRITE
READ
DESELECT
WRITE
READ
READ
WRITE
WRITE
DESELECT
WA2 WA5 RA6
tCLZ tDOH
Q3
Out
tCHZ
Device
originally
deselected
D7
In
tDOH
Q6
Out
tDS tDH
RA3
D5
In
WA7 WA8
D8
In
OE/ tEOHZ tEOLZ
tEOV tEOHZ
tDS
tDH
BWSx
tWEStWEH
DESELECT
PRELIMINARY CY7C1330AV25
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 17 of 19
READ/WRITE/DESELECT Sequence (CE Controlled)
Switching Waveforms (continued)
CLK
CE
tCYC
tCH tCL
tCES tCEH
= DON’T CARE = UNDEFINED
READ
WRITE
READ
DESELECT
WRITE
Deselect
READ
WRITE
WRITE
DESELECT
ADDRESS
WE
Data
In/Out
RA1
tAH
tAS
tWEStWEH
tCO
Q1
Out D2
In
WA2 WA5 RA6
tCLZ tDOH
Q3
Out
tCHZ
Device
originally
deselected
D7
In
tDOH
Q6
Out
tDS tDH
RA3
D5
In
WA7 WA8
D8
In
BWSx
tWEStWEH
DESELECT
PRELIMINARY
CY7C1330AV25
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 18 of 19
© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change without notice. Cypress S em icon duct or Corpo ration assu mes no resp onsib ility for th e us e
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypres s. Furthermore, Cypress does no t authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypre ss
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All product and company names mentioned in this document are trademarks of their respective ho lders.
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
250 CY7C1330AV25-250BGC
CY7C1332AV25-250BGC 51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm) Commercial
CY7C1330AV25-250BGXC
CY7C1332AV25-250BGXC 51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
200 CY7C1330AV25-200BGC
CY7C1332AV25-200BGC 51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1330AV25-200BGXC
CY7C1332AV25-200BGXC 51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
Package Diagram
51-85115-*B
119-ball PBGA (14 x 22 x 2.4 mm) (51-85115)
PRELIMINARY CY7C1330AV25
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 19 of 19
Document History Page
Document Title: CY7C1330AV25/CY7C1332AV25 18-Mbit (512K x 36/1Mbit x 18)
Pipelined Register-Register Late Write SRAM
Document Number: 001-07844
REV. ECN No. Issue Date Orig. of
Change Description of Change
** 469811 See ECN NXR New data sheet
*A 503690 See ECN VKN Minor change: Moved data sheet to web