100307DMQB. - NATIONAL SEMICONDUCTOR

100307

OBSOLETE

October 19, 2009

Low Power Quint Exclusive OR/NOR Gate

General Description

The 100307 is monolithic quint exclusive-OR/NOR gate. The

Function output is the wire-OR of all five exclusive-OR out-

puts. All inputs have 50 kΩ pull-down resistors.

Features

■Low Power Operation

■2000V ESD protection

■Pin/function compatible with 100107

■Voltage compensated operating range = −4.2V to −5.7V

■Available to industrial grade temperature range

■Available to Standard Microcircuit Drawing

(SMD) 5962-9459001

Logic Symbol

10030501

Logic Equation

F = (D1a + D2a) + (D 1b + D2b) + (D1c + D2c) + (D1d + D2d) +

(D1e + D 2e).

Pin Names Description

Dna–Dne Data Inputs

F Function Output

Oa–OeData Outputs

Oa–OeComplementary

Data Outputs

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100307 Low Power Quint Exclusive OR/NOR Gate

Connection Diagrams

24-Pin DIP

10030502

24-Pin Quad Cerpak

10030503

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100307

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Above which the useful life may be impaired. (Note 1)

Storage Temperature (TSTG)−65°C to +150°C

Maximum Junction Temperature (TJ)

Ceramic +175°C

Plastic +150°C

VEE Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltage (DC) VEE to +0.5V

Output Current (DC Output HIGH) −50 mA

ESD (Note 2)≥2000V

Recommended Operating

Conditions

Case Temperature (TC)

Military −55°C to +125°C

Supply Voltage (VEE)−5.7V to −4.2V

Note 1: Absolute maximum ratings are those values beyond which the

device may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Military Version

DC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55°C to +125°C

Symbol Parameter Min Max Units TCConditions Notes

VOH Output HIGH Voltage −1025 −870 mV 0°C to

+125°C

−1085 −870 mV −55°C VIN = VIH (Max) Loading with 1, 2, 3

VOL Output LOW Voltage −1830 −1620 mV 0°C to or VIL (Min) 50Ω to −2.0V

+125°C

−1830 −1555 mV −55°C

VOHC Output HIGH Voltage −1035 mV 0°C to

+125°C

−1085 mV −55°C VIN = VIH (Min) Loading with 1, 2, 3

VOLC Output LOW Voltage −1610 mV 0°C to or VIL (Max) 50Ω0 to −2.0V

+125°C

−1555 mV −55°C

VIH Input HIGH Voltage −1165 −870 mV −55°C Guaranteed HIGH Signal 1, 2, 3, 4

+125°C for All Inputs

VIL Input LOW Voltage −1830 −1475 mV −55°C to Guaranteed LOW Signal 1, 2, 3,4

+125°C for All Inputs

IIL Input LOW Current 0.50 μA−55°C to VEE = −4.2V 1, 2, 3

+125°C VIN = VIL (Min)

IIH Input High Current

D2a–D2e 250 μA0°C to

D1a–D1e 350 +125°C VEE = −5.7V 1, 2, 3

D2a–D2e 350 μA−55°C VIN = VIH (Max)

D1a–D1e 500

IEE Power Supply Current −75 −25 mA −55°C to Inputs Open 1, 2, 3

+125°C

Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55°C), then testing

immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be

considered a worst case condition at cold temperatures.

Note 4: Screen tested 100% on each device at −55°C, +25°C, and +125°C, Subgroups 1, 2 3, 7, and 8.

Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at −55°C, +25°C, and +125°C, Subgroups A1, 2, 3, 7, and 8.

Note 6: Guaranteed by applying specified input condition and testing VOH/VOL.

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100307

AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

Symbol Parameter TC = −55°C TC = +25°C TC = +125°C Units Conditions Notes

Min Max Min Max Min Max

tPLH Propagation Delay 0.30 2.10 0.40 1.90 0.40 2.40 ns

tPHL D2a–D2e to O, O

tPLH Propagation Delay 0.30 1.90 0.40 1.80 0.40 2.20 ns 1, 2, 3

tPHL D1a–D1e to O, O Figures 1, 2

tPLH Propagation Delay 0.80 2.90 0.90 2.80 0.90 3.40 ns

tPHL Data to F

tTLH Transition Time 0.20 1.70 0.30 1.60 0.20 1.70 ns 4

tTHL 20% to 80%, 80% to 20%

Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55°C), then testing

immediately after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures.

Note 8: Screen tested 100% on each device at +25°C temperature only, Subgroup A9.

Note 9: Sample tested (Method 5005, Table I) on each mfg. lot at +25°C, Subgroup A9, and at +125°C and −55°C temperatures, Subgroups A10 and A11.

Note 10: Not tested at +25°C, +125°C, and −55°C temperature (design characterization data).

Test Circuitry

10030505

Notes:

VCC, VCCA = +2V, VEE = −2.5V

L1 and L2 = equal length 50Ω impedance lines

RT = 50Ω terminator internal to scope

Decoupling 0.1 μF from GND to VCC and VEE

All unused outputs are loaded with 50Ω to GND

CL = Fixture and stray capacitance ≤ 3 pF

FIGURE 1. AC Test Circuit

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100307

Switching Waveforms

10030506

FIGURE 2. Propagation Delay and Transition Times

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100307

Physical Dimensions inches (millimeters) unless otherwise noted

24-Pin Ceramic Dual-In-Line Package (D)

NS Package Number J24E

24-Pin Quad Cerpak (F)

NS Package Number W24B

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100307

Notes

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100307

Notes

100307 Low Power Quint Exclusive OR/NOR Gate

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