3222/3223-DB1 - Silicon Labs

IA3222/3223-EVB

IA3222/3223 DEMO BOARD AND CPLD INTERPOSER USER’S GUIDE

Description

The IA3222/3223 Demo Board is a typical application

circuit that exhibits all the features of the IA3222/3223

chipset. The chipset can be programmed by software to

pass PTT certification worldwide. The integrated V.92

DAA offers an easy-to-use analog interface with an

internal or external dc reference for seamless

interfacing to a variety of systems. It allows easy

building-block integration where audio codecs are either

separate or integrated into DSPs. It is also ideal for non-

modem systems requiring isolated DAAs, such as alarm

systems, VoIP, and PBX FXO interfaces.

The CPLD interposer allows stand-alone evaluation of

the chipset. This simple circuit takes the place of a

microcontroller that would normally send off-hook

commands and other settings to the IA3223's serial

port. Instead of having to program a microcontroller, the

user may control the IA3223's registers using manual

switches.

Features

Programmable worldwide telecom compliance with

one hardware build

V.92 (56 kbps) performance

Virtually unlimited high-voltage insulation

Highly-competitive BOM cost

Lowest pin count (26) chipset

High common-mode RF immunity without costly

filtering

Continuous dc and audio snooping with >5 M Tip

to Ring

Parallel pick-up, line-in-use, ring, and "911" detection

–86 dBm receiver noise floor

+3 dBm transmit power

Micropower line-side device powered from line

120 dB Caller ID common-mode rejection

IA3222/3223-EVB

2 Preliminary Rev. 0.1

1. IA3222/3223 Demo Board Photographs

Figure 1. IA3222/3223 Demo Board

Figure 2. CPLD Interposer

IA3222/3223-EVB

Preliminary Rev. 0.1 3

Figure 3. Demo Board and Interposer

IA3222/3223-EVB

4 Preliminary Rev. 0.1

2. Getting Started

The Interposer Board's simplified silkscreen is shown in Figure 4. Refer to the schematic for connector pinouts.

Figure 4. Interposer Board Simplified Silkscreen

The board must be powered using 3.3 V through J3 according to the polarity indicated on the silkscreen. The DAA

Demo Board must be plugged into connector J2 on the Interposer as shown in Figure 3. The DAA Modem Side is

powered via the Interposer.

Table 1 lists the DAA registers, which can be programmed via DIP switch banks on the Interposer Board. A

complete description of these registers can be found in the IA3222/3223 data sheet.

In order to program the DAA, the corresponding DIP switches must be set to the desired state; then, switch SW5

must be set to the momentary "write" position. Every push of SW5 makes the CPLD write all the DAA's read/write

registers based on the current state of the DIP switches.

The line-status register and the ECHO bit in the Line-Side LSB register are read-only. If switch SW4 is set to "read,"

those read-only bits are monitored continuously and updated onto the LEDs. An LED turned on means a high

state.

Table 1. DAA Registers

A2 A1 A0 Register D3 D2 D1 D0

0 0 0 Control OFH LSR SGAIN PWD

0 0 1 Line Side programming LP5 LP4 LP3 LP2

0 1 0 Line Side programming LP1 LP0 ECHO REVID

0 1 1 Thresholds LTH1 LTH0 RTH1 RTH0

1 0 0 Line status (read only) RNG/PPU LIU/LDN LSTAT LP

1 0 1 Dividers Reserved F2 F1 F0

1 1 X Reserved Reserved Reserved Reserved Reserved

J4

IA3222/3223-EVB

Preliminary Rev. 0.1 5

2.1. J1 Connector Pinout for the IA3222/3223 Demo Board

The ExtClk input can be used in order to synchronize the IA3222/3223 internal codecs with an external codec. This

helps prevent aliasing. Otherwise, the ExtClk input can be left open (there is an internal pull-down). The internal

oscillator must then be selected. Refer to the data sheet for internal or external clock register settings.

2.1.1. Jumper Setting

A single jumper is available on the IA3222/3223 Demo Board. When it is open, the state of the hook switch is

controlled by the serial port. When it is closed, the DAA goes off-hook regardless of the programmed hook-switch

state. If the Interposer is used, the jumper is not needed to go off-hook.

2.2. Automatic Operation

In order to evaluate the IA3222/3223 DAA chipset as a replacement of a DAA product with a static hook control

wire, the CPLD can recognize an active-high or active-low host command and produce the equivalent serial

command to the IA3223. The host command signal is to be connected on the Interposer board at the net named

tri_in, which is the common between R38 and R39. The leftmost switch of the SW1 bank (OFH) should be set to

the polarity of the hook command that corresponds to the off-hook state. If the off-hook command is active high,

OFH should be set to 1, and if the off-hook command is active low, OFH should be set to 0. At every transition of

the hook command (tri_in signal), all the IA3223 registers are loaded based on the state of the DIP switches and of

the hook command signal.

Manual operation is still possible with the hook command signal connected, but the meaning of the OFH DIP switch

differs between automatic and manual operation. When a transition of tri_in is detected, OFH indicates the polarity

of the off-hook command. When the write switch (SW5) is pushed momentarily, the state of OFH is copied to

IA3223 register 0, where a high level means off-hook, and a low level means on-hook.

Table 2. J1 Connector Pin Descriptions*

Pin # Name Type Description

1, 2 Extclk Input Optional external clock input for codec

3, 4 SClk input Serial data clock input from interposer board

5, 6 CS Input Chip select from interposer board

7, 8 SDIN Input Serial data input from interposer board

9, 10 VDD Power Power supply 3.3 V from interposer board

11, 12 TX Input Transmit analog input

13, 14 ACREF Input/Output Analog ac reference

15, 16 LINESTATUS Output Line status

17, 18 SDOUT Output Serial data output (register read)

19, 20 RX Output Receive analog output

21 GND Power Chassis ground

22 GND Power Signal and system ground

*Note: See the IA3222/3223 data sheet for more information about differential or single-ended analog interfacing.

IA3222/3223-EVB

6 Preliminary Rev. 0.1

3. Demo Board Schematics

Cext1

ACRef

AVDD

Cext2

LGNDOFHK

SDin

Rx

Tx

SClk

LIU/LDN

RNG/PPU

ExtClk

LineStatus

CS-

LP

SDout

TIP

RING

CS-

ExtClk

Rx

SDout

SClk

SDin

LineStatus

SClk

Rx

CS-

ACRef

LineStatus

ExtClk

Tx

ACRef

SDin

Tx

SDout

Vdd

Vdd Vdd

Vdd

R2

47k 0603

R2

47k 0603

U1

IA3222B

U1

IA3222B

HOOK 1

ACIN 8

HCAP

5

ICT

2

ICG

4

ICR

3

VDD 10

GND

9

CX 7

CX1 6

C6

Disk capacitors

C6

Disk capacitors

Q3

MMBTA42

Q3

MMBTA42

C733nF 100V 1206 C733nF 100V 1206

C10

2.7nF 100V 0805

C10

2.7nF 100V 0805

C16

2.2µF 6.3V 0603

C16

2.2µF 6.3V 0603

RV1

P3100SB

RV1

P3100SB

C14

4.7nF 100V 0805

C14

4.7nF 100V 0805

Q2

MMBTA42

Q2

MMBTA42

Q6

MMBTA06

Q6

MMBTA06

C17

470 pF HV

C17

470 pF HV

R15

20 1% 1206

R15

20 1% 1206

C8

Disk capacitors

C8

Disk capacitors

R14

4.7k 1/4W 1206

R14

4.7k 1/4W 1206 R6

3.3 0603

R6

3.3 0603

R8

4.7 1W t/h metal oxide

R8

4.7 1W t/h metal oxide

+

C2

10µF 4V A

+

C2

10µF 4V A

R1

5.6M 1% 1206

R1

5.6M 1% 1206

C5

1nF 100V 0603

C5

1nF 100V 0603

BR1

S1ZB60

BR1

S1ZB60

4

2

3

1

J2

RJ jack dual

J2

RJ jack dual

1

2

3

4

R17

120k 1% 0805

R17

120k 1% 0805

C9

Disk capacitors

C9

Disk capacitors

R5

3.3 0603

R5

3.3 0603

U2

IA3223A

U2

IA3223A

Din

4

ICT 20

Vss 19

TxIn

6ICG 16

CS

3SCLK

2

ICR 18

Cext2 13

Cext1 14

RxOut

7

Dout

5

LineStat

1

ExtClk

8

ACRef 15

Vdd 17

RNG/PPU

9

LIU/LDN

10 LP 11

OFHK 12

C11

330nF 10V 0603

C11

330nF 10V 0603

R12

120k 1% 0805

R12

120k 1% 0805

C4

22nF 200V 0805

C4

22nF 200V 0805

JUMPERJUMPER

1 2

J1

HEADER 11X2

J1

HEADER 11X2

2

4

6

8

10

12

14

16

18

20

22

1

3

5

7

9

11

13

15

17

19

21

R10

220 1206

R10

220 1206 C1

6.8nF 200V 0805

C1

6.8nF 200V 0805

Q1

MMBTA92

Q1

MMBTA92

C3

100nF 16V 0603

C3

100nF 16V 0603

R13

10k 0805

R13

10k 0805

R18

4.7k 0603

R18

4.7k 0603

C18

470 pF HV

C18

470 pF HV

R16

5.6M 1% 1206

R16

5.6M 1% 1206

R7

3.3 0603

R7

3.3 0603

C15

100nF 16V 0603

C15

100nF 16V 0603

R9

680 1206

R9

680 1206

C12

10nF 16V 0603

C12

10nF 16V 0603

FB1

Ferrite 0603

FB1

Ferrite 0603

C13

220nF 16V 0603

C13

220nF 16V 0603

Q4

MMBTA42

Q4

MMBTA42

Figure 5. Demo Board Schematic

IA3222/3223-EVB

Preliminary Rev. 0.1 7

reg1-2

reg1-0

Echo

LPol

LStat

Ring

write

reg3-3

reg5-3

read_b

reg0-1

reg5-1

reg0-0

write_b

res-reg-3

reg5-2

reg2-0

res-reg-2

reg1-3

reg1-1

reg2-3

reg2-2

reg2-1

reg3-2

reg3-1

reg3-0

reg5-0

res-reg-1

res-reg-0

read

SDin SDin

SDout

CS-CS-

SClkSClk

SDout

CLK_1M

TDO

TCK

TDO

TMS

TDI

tri_in

LIU

reg0-2

reg0-3

RSTB

+3.3V +3.3V +3.3V +3.3V +3.3V+3.3V +3.3V+3.3V

+3.3V

+3.3V+3.3V

+3.3V

+3.3V+3.3V

+3.3V+3.3V +3.3V+3.3V

+3.3V

+3.3V+3.3V

+3.3V +3.3V +3.3V +3.3V +3.3V

+3.3V

+3.3V+3.3V+3.3V

+3.3V +3.3V

+3.3V

D4

LED

D4

LED

J3

HEADER 2

J3

HEADER 2

1

2

R36

47k 0603

R36

47k 0603

R21

47k 0603

R21

47k 0603

R29

47k 0603

R29

47k 0603

SW5

SW SPDT momentary

SW5

SW SPDT momentary

R9

47k 0603

R9

47k 0603

R1

1k 0603

R1

1k 0603

C7

0.1µF 0603

C7

0.1µF 0603

EPM3128ATC100-4

U1

EPM3128ATC100-4

U1

VccIO 3

GNDINT

38

VccINT

39

TDI 4

NC 5

I/O LAB A 6

NC 7

I/O LAB A 8

I/O LAB A 9

I/O LAB A 10

GNDIO 11

I/O LAB A 12

I/O LAB A 13

I/O LAB A 14

I/O LAB A 92

I/O LAB A 93

I/O LAB A 94

GNDIO 95

I/O LAB A 96

I/O LAB A 97

I/O LAB A 98

I/O LAB A 99

I/O LAB A 100

TMS 15

I/O LAB B 16

I/O LAB B 17

VccIO 18

I/O LAB B 19

I/O LAB B 20

I/O LAB B 21

NC 22

I/O LAB B 23

NC 24

I/O LAB B 25

GNDIO

26

NC

27

NC

28

I/O LAB B

29

I/O LAB B

30

I/O LAB B

31

I/O LAB B

32

GNDIO

33

VccIO

34

I/O LAB B

35

I/O LAB B

36

I/O LAB B

37

I/O LAB C

40

I/O LAB C

41

I/O LAB C

42

GNDIO

43

I/O LAB C

44

I/O LAB C

45

I/O LAB C

46

I/O LAB C

47

I/O LAB C

48

NC

49

NC

50

VccIO

51

I/O LAB C

52

GNDIO

53

I/O LAB C

54

NC

55

I/O LAB C

56

I/O LAB C

57

I/O LAB C

58

GNDIO

59

I/O LAB C

60

I/O LAB C

61

TCK

62

I/O LAB D

63

I/O LAB D

64

GNDIO

65

VccIO

66

I/O LAB D

67

I/O LAB D

68

I/O LAB D

69

NC

70

I/O LAB D

71

NC

72

TDO

73

GNDIO

74

I/O LAB D

75

I/O LAB D 76

NC 77

GNDIO 78

I/O LAB D 79

I/O LAB D 80

I/O LAB D 81

VccIO 82

I/O LAB D 83

I/O LAB D 84

I/O LAB D 85

NC 1

NC 2

GNDINT 86

I/GCK1 87

I/OE1 88

I/GC 89

I/OE2/GCK2 90

VccINT 91

C3

0.1µF 0603

C3

0.1µF 0603

R26

47k 0603

R26

47k 0603

R16

47k 0603

R16

47k 0603

C2

0.1µF 0603

C2

0.1µF 0603

R7

47k 0603

R7

47k 0603

D5

LED

D5

LED

R4

47k 0603

R4

47k 0603

J1

HEADER 5X2

J1

HEADER 5X2

2

4

6

8

10

1

3

5

7

9

R12

1k 0603

R12

1k 0603

R33

68 0603

R33

68 0603

R40

470k

R40

470k

R34

68 0603

R34

68 0603

C5

0.1µF 0603

C5

0.1µF 0603

R25

47k 0603

R25

47k 0603

R20

47k 0603

R20

47k 0603

D1

LED

D1

LED

SW3

SW DIP-8

SW3

SW DIP-8

R38

47k 0603

R38

47k 0603

R19

47k 0603

R19

47k 0603

R15

47k 0603

R15

47k 0603

R10

47k 0603

R10

47k 0603

R14

47k 0603

R14

47k 0603

D2

LED

D2

LED

C1

10µF A

C1

10µF A

Y1

OSC14

Y1

OSC14

VCC 14

OUT

8

GND 7

J2

HEADER 11X2

J2

HEADER 11X2

2

4

6

8

10

12

14

16

18

20

22

1

3

5

7

9

11

13

15

17

19

21

R24

47k 0603

R24

47k 0603

R39

n/p 0603

R39

n/p 0603

C4

0.1µF 0603

C4

0.1µF 0603

R13

47k 0603

R13

47k 0603

R11

47k 0603

R11

47k 0603

R35

68 0603

R35

68 0603

R30

47k 0603

R30

47k 0603

R31

68 0603

R31

68 0603

R5

47k 0603

R5

47k 0603

R18

47k 0603

R18

47k 0603

R28

47k 0603

R28

47k 0603

R2

1k 0603

R2

1k 0603

C6

0.1µF 0603

C6

0.1µF 0603

D3

LED

D3

LED

R37

47k 0603

R37

47k 0603

SW4

SW SPDT

SW4

SW SPDT

R32

68 0603

R32

68 0603

R27

47k 0603

R27

47k 0603

R23

47k 0603

R23

47k 0603

R17

47k 0603

R17

47k 0603

SW1

SW DIP-8

SW1

SW DIP-8

R8

47k 0603

R8

47k 0603

SW2

SW DIP-8

SW2

SW DIP-8

R22

47k 0603

R22

47k 0603

R6

47k 0603

R6

47k 0603

R3

1k 0603

R3

1k 0603

Figure 6. Interposer Board Schematic

IA3222/3223-EVB

8 Preliminary Rev. 0.1

4. Demo Board Bill of Materials

Table 3. Demo Board Bill of Materials

Quantity Reference Description

1BR1 S1ZB60

1 C1 6.8 nF 200 V 0805

1 C2 10µF 4V A

2 C3, C15 100 nF 16 V 0603

1 C4 22nF 200V 0805

1 C5 1 nF 100 V 0603

1 C7 33nF 100V 1206

1 C10 2.7 nF 100 V 0805

1 C11 330 nF 10 V 0603

1 C12 10 nF 16 V 0603

1 C13 220 nF 16 V 0603

1 C14 4.7 nF 100 V 0805

1 C16 2.2 µF 6.3 V 0603

2 C17, C18 470 pF HV

1 FB1 Ferrite 0603 600Ω

1Q1 MMBTA92

3 Q2, Q3, Q4 MMBTA42

1Q6 MMBTA06

1 RV1 P3100SB

2 R1, R16 5.6 M 1% 1206

1R2 47k 0603

3 R5, R6, R7 3.3  0603

1R84.7 through hole metal oxide

1 R9 680 1206

1 R10 220 1206

2 R12, R17 120 k 1% 0805

1 R13 10 k 0805

1 R14 4.7 k 1206

1 R15 20  1% 1206

1 R18 4.7 k 0603

1 U1 IA3222B

1 U2 IA3223A

IA3222/3223-EVB

Preliminary Rev. 0.1 9

5. Interposer Bill of Materials

Table 4. Interposer Bill of Materials

Quantity Reference Description

1C1 10µF A

6 C2,C3,C4,C5,C6,C7 0.1 µF 0603

5 D1,D2,D3,D4,D5 LED green

4 R1,R2,R3,R12 1 k 0603

29 R4–11, R13–30, R36–38 47 k 0603

5 R31, R32, R33, R34, R35 68 0603

1 R39 N/P 0603

1R40 470k

3 SW1, SW2, SW3 SW DIP-8

1 SW4 SW SPDT

1 SW5 SW SPDT momentary

1 U1 EPM3128ATC100-10

1 Y1 1 MHz DIP14 oscillator

IA3222/3223-EVB

10 Preliminary Rev. 0.1

6. Interposer Board CPLD Pin Assignment

Pin name : Pin # : Type

---------------------------

reg_0[3] : 19 : input

reg_0[2] : 20 : input

reg_0[1] : 21 : input

reg_0[0] : 23 : input

reg_1[3] : 25 : input

reg_1[2] : 29 : input

reg_1[1] : 30 : input

reg_1[0] : 31 : input

reg_2[3] : 32 : input

reg_2[2] : 35 : input

reg_2[1] : 36 : input

reg_2[0] : 37 : input

reg_3[3] : 40 : input

reg_3[2] : 41 : input

reg_3[1] : 42 : input

reg_3[0] : 44 : input

reg_5[3] : 45 : input

reg_5[2] : 46 : input

reg_5[1] : 47 : input

reg_5[0] : 48 : input

read : 60 : input

read_b : 61 : input

write : 63 : input

write_b : 64 : input

ring : 67 : output

liu : 68 : output

lstat : 69 : output

lp : 71 : output

echo : 75 : output

offhook : 76 : input

clk1m : 87 : input

rstb : 89 : input

dout : 93 : input

din : 98 : output

csb : 99 : output

sclk : 100 : output

IA3222/3223-EVB

Preliminary Rev. 0.1 11

7. Interposer Board CPLD Verilog Code

/*********************************************/

/* */

/* weikang on 04/04/2006 */

/* modified on 06/12/2006 */

/* */

/* sclk = 1MHz */

/* */

/* simulator for p502 spi interface */

/* */

/* 1) change tri_in --> offhook */

/* 2) add offhook pin */

/* when offhook goes high/low-->reg0[3]= */

/* (offhook&reg0[3]) | (~offhook&~reg0[3]) */

/* and generate write pulse */

/* */

/*********************************************/

`timescale 1ns/10ps

module p502_spi_model_new_712(rstb, clk1m, dout,

reg_0, reg_1, reg_2, reg_3, reg_5,

write, write_b, read, read_b,

offhook,

echo, ring, liu, lstat, lp,

sclk, din, csb);

/************** input and output ***************/

input rstb;

input dout;

input clk1m;

input [3:0] reg_0, reg_1, reg_2, reg_3, reg_5;

input write, write_b;

input read, read_b;

input offhook;

output echo;

output ring, liu, lstat, lp;

output sclk, din, csb;

reg echo;

reg ring, liu, lstat, lp;

IA3222/3223-EVB

12 Preliminary Rev. 0.1

/**************** p502_spi_model debouncing circuit **************/

// add on 07-12-06

reg d0_offhook;

reg d1_offhook;

reg d2_offhook, d3_offhook, d4_offhook, d5_offhook;

reg d6_offhook, d7_offhook, d8_offhook, d9_offhook;

wire offhook_wr = (d0_offhook & ~d1_offhook) | (~d0_offhook & d1_offhook);

// wire reg_0_sel = d2_offhook | d3_offhook | d4_offhook | d5_offhook |

// d6_offhook | d7_offhook | d8_offhook | d9_offhook;

wire total_offhk = d2_offhook | d3_offhook | d4_offhook | d5_offhook |

d6_offhook | d7_offhook | d8_offhook | d9_offhook |

offhook;

reg reg_0_sel;

reg sync_w, sync_w_b;

reg sync_r, sync_r_b;

wire q_w;

wire wrenb = ~(q_w & sync_w);

assign q_w = ~(sync_w_b & wrenb);

// wire wren = ~ wrenb;

wire wren = ~ wrenb | offhook_wr;

wire q_r;

wire rdenb = ~(q_r & sync_r);

assign q_r = ~(sync_r_b & rdenb);

wire rden = ~ rdenb;

reg wk_wr;

reg clk;

always @(posedge clk1m or negedge rstb)

if (rstb==0) clk <= 1'b0;

else clk <= ~clk;

always @(negedge clk or negedge rstb)

if (rstb==0)

begin

sync_w <= 0;

sync_w_b <= 1;

sync_r <= 0;

sync_r_b <= 1;

end

else

begin

sync_w <= write;

sync_w_b <= write_b;

IA3222/3223-EVB

Preliminary Rev. 0.1 13

sync_r <= read;

sync_r_b <= read_b;

end

/**************** p502_spi_model register **************/

reg [7:0] read_cnt;

reg [2:0] bit_cnt;

reg [2:0] cnt, sync_cnt, s_sync_cnt;

wire t_sync_cnt = (sync_cnt==3'b101);

reg r_sync;

reg wr;

reg t_csb;

wire tri_in = ~rstb;

wire csb = (tri_in==1) ? 1'bZ : t_csb;

reg t_wk_read;

reg wk_read;

reg cnt_q0, cnt_q1, cnt_q2, cnt_q3;

wire clk_16 = cnt_q3;

wire clearb = rstb & ~(r_sync);

wire readen = (read_cnt==8'h02) | (read_cnt==8'h04);

wire tmp_csb = ~(wk_wr & ~clk_16) & ~(wk_read & ~clk_16 & readen);

wire bit_rstb = rstb & ~t_csb;

reg [7:0] data;

wire [7:0] r_data= (read_cnt==8'h02) ? 8'b10100000 : (read_cnt==8'h04) ?

8'b11000000 : 8'b0;

wire [2:0] downcnt = {~bit_cnt[2],~bit_cnt[1],~bit_cnt[0]};

wire tmp_din = (wk_wr==1) ? data[downcnt] : (wk_read==1) ? r_data[downcnt]

: 1'b0;

reg wk2_csb;

wire din = (tri_in==1) ? 1'bZ : tmp_din & ~wk2_csb & ~t_csb;

wire sclk = (tri_in==1) ? 1'bZ : (csb==1) ? 1'b1 : clk;

wire cnt_clearb = rstb & wk_read;

/*********************** add new function 07-12-2006 *********************/

always @(posedge clk_16 or negedge rstb)

if (rstb==0)

begin

d2_offhook <= 0;

d3_offhook <= 0;

d4_offhook <= 0;

d5_offhook <= 0;

d6_offhook <= 0;

d7_offhook <= 0;

d8_offhook <= 0;

d9_offhook <= 0;

end

IA3222/3223-EVB

14 Preliminary Rev. 0.1

else

begin

d2_offhook <= offhook;

d3_offhook <= d2_offhook;

d4_offhook <= d3_offhook;

d5_offhook <= d4_offhook;

d6_offhook <= d5_offhook;

d7_offhook <= d6_offhook;

d8_offhook <= d7_offhook;

d9_offhook <= d8_offhook;

end

always @(posedge clk or negedge rstb)

if (rstb==0)

begin

d0_offhook <= 0;

d1_offhook <= 0;

end

else

begin

d0_offhook <= offhook;

d1_offhook <= d0_offhook;

end

reg w0_offhook, w1_offhook;

wire offhook_rstb = rstb & wrenb;

wire offhook_clk = (w0_offhook & ~w1_offhook) | (~w0_offhook & w1_offhook);

always @(negedge clk or negedge rstb)

if (rstb==0)

begin

w0_offhook <= 0;

w1_offhook <= 0;

end

else

begin

w0_offhook <= total_offhk;

w1_offhook <= w0_offhook;

end

always @(posedge offhook_clk or negedge offhook_rstb)

if (offhook_rstb==0) reg_0_sel <= 0;

else reg_0_sel <= ~reg_0_sel;

/**************** **************/

always @(posedge clk or negedge rstb)

IA3222/3223-EVB

Preliminary Rev. 0.1 15

if (rstb==0) cnt_q0 <= 0;

else cnt_q0 <= ~cnt_q0;

always @(negedge cnt_q0 or negedge rstb)

if (rstb==0) cnt_q1 <= 0;

else cnt_q1 <= ~cnt_q1;

always @(negedge cnt_q1 or negedge rstb)

if (rstb==0) cnt_q2 <= 0;

else cnt_q2 <= ~cnt_q2;

always @(negedge cnt_q2 or negedge rstb)

if (rstb==0) cnt_q3 <= 0;

else cnt_q3 <= ~cnt_q3;

always @(posedge wren or negedge clearb)

if (clearb==0) wr <= 1'b0;

else wr <= 1'b1;

always @(posedge clk_16 or negedge clearb)

if (clearb==0) wk_wr <= 1'b0;

else wk_wr <= wr;

always @(posedge clk_16 or negedge clearb)

if (clearb==0) cnt <= 3'b0;

else if (wk_wr==1) cnt <= cnt + 1;

always @(negedge clk1m or negedge rstb)

if (rstb==0) s_sync_cnt <= 3'b0;

else s_sync_cnt <= cnt;

always @(negedge clk or negedge rstb)

if (rstb==0) sync_cnt <= 3'b0;

else sync_cnt <= s_sync_cnt;

always @(negedge clk or negedge rstb)

if (rstb==0) r_sync <= 1'b0;

else r_sync <= t_sync_cnt;

always @(negedge clk or negedge bit_rstb)

if (bit_rstb==0) bit_cnt <= 3'b111;

else if (t_csb==0 & (wk_wr==1 | wk_read==1)) bit_cnt <= bit_cnt + 1;

// add on 07-12-06

wire t_offhook = (reg_0[3] & offhook) | (~reg_0[3] & ~offhook);

wire [3:0] t_reg_0 = (reg_0_sel==1) ? {t_offhook,reg_0[2:0]} : reg_0;

always @(t_reg_0 or reg_1 or reg_2 or reg_3 or reg_5 or wk_wr or sync_cnt)

case (sync_cnt)

IA3222/3223-EVB

16 Preliminary Rev. 0.1

3'b000 : data = {4'b0000,t_reg_0};

3'b001 : data = {4'b0001,reg_1};

3'b010 : data = {4'b0010,reg_2};

3'b011 : data = {4'b0011,reg_3};

3'b100 : data = {4'b0101,reg_5};

default: data = 8'b00000000;

endcase

always @(posedge clk_16 or negedge rstb)

if (rstb==0) t_wk_read <= 1'b0;

else t_wk_read <= rden;

always @(negedge clk or negedge rstb)

if (rstb==0) wk_read <= 1'b0;

else wk_read <= t_wk_read;

always @(posedge clk_16 or negedge cnt_clearb)

if (cnt_clearb==0) read_cnt <= 8'b0;

else read_cnt <= read_cnt + 1;

always @(negedge clk1m or negedge rstb)

if (rstb==0) t_csb <= 1;

else t_csb <= tmp_csb;

always @(negedge clk1m or negedge rstb)

if (rstb==0) wk2_csb <= 1;

else wk2_csb <=t_csb;

always @(posedge clk or negedge rstb)

begin

if (rstb==0)

begin

echo <=0;

ring <=0;

liu <=0;

lstat<=0;

lp <=0;

end

else if (wk_read==1 & t_csb==0)

begin

if (read_cnt==8'h02 & bit_cnt==3'b110)

echo <= dout;

else if (read_cnt==8'h04 & bit_cnt==3'b100)

ring <= dout;

else if (read_cnt==8'h04 & bit_cnt==3'b101)

liu <= dout;

else if (read_cnt==8'h04 & bit_cnt==3'b110)

lstat <= dout;

IA3222/3223-EVB

Preliminary Rev. 0.1 17

else if (read_cnt==8'h04 & bit_cnt==3'b111)

lp <= dout;

end

/*********************** add new function *********************/

reg offhk;

always @(posedge wk_wr or negedge rstb)

if (rstb==0) offhk <= 0;

else offhk <= t_reg_0[3];

/*********************** call modules *********************/

endmodule

IA3222/3223-EVB

18 Preliminary Rev. 0.1

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