SSM3J46CTB
2015-11-26
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T OSHIB A Field-Ef fect T ra nsistor Silicon P-Channel MOS Type (U-MOS VI)
SSM3J46CTB
○ Power Management Switch Applications
• 1.5 V drive
• Low ON-resistance: RDS(ON) = 250 mΩ (max) (@VGS = -1.5 V)
RDS(ON) = 178 mΩ (max) (@VGS = -1.8 V)
RDS(ON) = 133 mΩ (max) (@VGS = -2.5 V)
RDS(ON) = 103 mΩ (max) (@VGS = -4.5 V)
Absolute Maximum Ratings (Ta = 25°C)
Characteristic Symbol Rating Unit
Drain-Source voltage V
DSS
-20 V
Gate-Source voltage VGSS
± 8 V
Drain current DC ID
-2.0 A
Pulse IDP
-4.0
Power dissipation P
D
(Note 1
)
1000 mW
Channel temperature Tch 150 °C
Storage temperature range Tstg −55 to 150 °C
Note: Using continuously under heavy loads (e.g. the application of high
temperature/current/voltage and the significant change in
temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e.
operating temperature/current/voltage, etc.) are within the
absolute maximum ratings.
Please design the appropriate reliability upon reviewing the
Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and
individual reliability data (i.e. reliability test report and estimated failure rate, etc).
Note 1: Mounted on a FR4 board.
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2)
Marking (top view) Pin Condition (top view ) Equivalent Circuit
Unit
: mm
1. Gate
2. Source
3. Drain
CST3B
JEDEC ―
JEITA ―
TOSHIBA 2-1T1A
Weight: 1.5 mg (typ.)
S V
1
2
3
1
2
3
1. Gate
2. Source
3. Drain
*Electrodes: on the bottom
Polarity mark
(on the top)
Start of commercial production
2010-02
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Electrical Characteristics (Ta = 25°C)
Characteristic Symbol Test Conditions Min Typ. Max Unit
Drain-Source breakdown voltage V
(BR) DSS
I
D
= −1 mA, V
GS
= 0 V −20 ― ― V
V
(BR) DSX
I
D
= −1 mA, V
GS
= 5 V (Note 3) −15 ― ― V
Drain cut-off current IDSS VDS = −20 V, VGS = 0 V ― ― −1 μA
Gate leakage current
IGSS VGS = ±8 V, VDS = 0 V ― ― ±1 μA
Gate threshold volt age
V
th
V
DS
= −3 V, I
D
= −1 mA −0.3 ― −1.0 V
Forward transfer admitt ance |Y
fs
| V
DS
= −3 V, I
D
= −1.0 A (Note 2) ― 5.2 ― S
Drain–sourc e ON-resistance RDS (ON)
ID = -1.5 A, VGS = −4.5 V (Note 2) ― 88.5
103
mΩ
ID = -1.0 A, VGS = −2.5 V (Note 2) ― 107.5
133
I
D
= -0.5 A, V
GS
= −1.8 V (Note 2) ―
130
178
I
D
= -0.25 A, V
GS
= −1.5 V (Note 2) ― 151 250
Input capacitance
Ciss VDS = −10 V, VGS = 0 V
f = 1 MHz
― 290 ―
pF
Output capacitance
Coss ― 44 ―
Reverse transfer capacitance Crss ― 32 ―
Switching time Turn-on time t
on
VDD = −10 V, ID = −0.5 A
VGS = 0 to −2.5 V, RG = 4.7 Ω
― 13.4 ― ns
Turn-off time toff ―
46.2 ―
Total Gate Charge
Qg VDD = −10 V, ID = −2.0 A,
VGS = − 4.5 V
― 4.7 ―
nC
Gate-Source Charge Q
gs1
― 0.4 ―
Gate-Drain Charge Q
gd
―
1.0 ―
Drain-Source forward voltage VDSF ID = 2.0 A, VGS = 0 V (Note 2) ―
0.9 1.2 V
Note2: Pulse test
Note3: If a forward bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the
drain-source breakdown voltage is lowered in this mode.
Switching Time Test Circuit
(a) Test Circuit (b) VIN
Notice on Usage
Vth can be expressed as the voltage between gate and source when the low operating current value is ID = -1 mA for
this product. For normal switching operat ion , VGS (on) requires a higher voltage than Vth and VGS (off) requires a lower
voltage than Vth. (The relationship can be established as follows: VGS (o ff) < Vth < VGS (on).)
Take this into consideration when using the device.
Handling Preca ution
When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that
come into direct contact with devices should be made of antistatic materials.
V
DD
= -10 V
R
G = 4.7 Ω
Duty
≤ 1%
V
IN: tr, tf < 5 ns
Common Source
Ta
= 25°C
IN
0
−2.5V
10 μs
VDD
OUT
RG
RL
ton
10%
90%
−2.5 V
0 V
90%
10%
toff
tr
tf
VDS (ON)
VDD
(c) V
OUT
SSM3J46CTB
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-4.0
R
DS (ON)
– I
D
Drain current I
D
(A)
Drain–sourc e ON-resistance
R
DS (ON)
(mΩ)
0 -1.0
-2.0
0
-3.0
300
100
VGS = -4.5 V
-1.5 V
-2.5 V
-1.8 V
Common Source
Ta = 25°C
Pulse test
Ambient temperature Ta (°C)
R
DS (ON)
– Ta
Drain–sourc e ON-resistance
R
DS (ON)
(mΩ)
0
−50 0 50 150 100
300
100
Common Source
Pulse test
I
D
= -1.5 A / V
GS
= -4.5 V
-
0.25 A / -1.5 V
-
1.0 A / -2.5 V
-0.5 A / -1.8 V
Ambient temperature Ta (°C)
V
th
– Ta
Gate threshold voltage V
th
(V)
-1.0
0
−50 0 150
-0.5
50 100
Common Source
VDS = -3 V
ID = -1 mA
Drain–source ON-resistance
R
DS (ON)
(mΩ)
0 -2 -4
-6
Gate–source voltage V
GS
(V)
0
RDS (ON) – VGS
-8
200
-25 °C
25 °C
300
ID = -1.5 A
Common Source
Pulse test
Ta = 100 °C
Gate–source voltage V
GS
(V)
ID – VGS
Drain current ID
(A)
-10
0
-0.1
-1
-0.001
-0.01
-0.0001
-1.5
-1.0
Common Source
VDS = -3 V
Pulse test
-25 °C
Ta = 100 °C
25 °C
-0.5
Drain–sourc e voltage V
DS
(V)
I
D
– V
DS
Drain current I
D (A)
0
-2
0 -0.2
-0.4 -0.6 -1
-1
-0.8
-3
-4
Common Source
Ta = 25 °C
Pulse test
-1.8 V
VGS = -1.5 V
-2.5 V
-5
-4.5 V
200
200
100
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Drain current I
D
(A)
Forward transf er admittance |Y
fs
| (S)
|Yfs| – ID
0.1
-10
1
10
-0.1 -1
3
0.3
-
0.01
Common Source
VDS = -3 V
Ta = 25°C
Pulse test
Drain reverse current I
DR
(A)
Drain–sourc e voltage V
DS
(V)
I
DR
– V
DS
10
0
0.1
1
0.001
0.01
0.2 0.6
0.4 1.0 0.8 1.2
-25 °C
Ta =100 °C
25 °C
Common Source
VGS = 0 V
Pulse test
G
D
S
IDR
Drain current I
D
(A)
Switching time t (ns)
t – I
D
1
-0.001
1000
-0.1
10000
-1 -10
100
tf
Common Source
VDD = -10 V
VGS = 0 to -2.5 V
Ta = 25 °C
RG = 4.7 Ω
10
-0.01
toff
tr
ton
Total Gate Charge Qg (nC)
Dynamic Input Characteristic
Gate–source voltage V
GS
(V)
0
0 4 8
-4
-8
10
-6
-2
2 6
VDD = -16 V
VDD = -10 V
Common Source
ID = -2.0 A
Ta = 25°C
Drain-sourc e voltage V
DS
(V)
C – V
DS
Capacitance C (pF)
10
-0.1
-1
-10
-100
100
1000
300
30
Common Source
Ta = 25 °C
f = 1 MHz
VGS = 0 V
Ciss
Coss
Crss
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a
b
Ambient temperature Ta (°C)
PD – Ta
Power dissipation P
D
(mW)
1000
0
200
120 100 140
400
800
160
1200
80 60 40 20 0
-20
-40
a
b
a: Mounted on FR4 board
(25.4 mm × 25.4 mm × 1.6 mm , C u Pad : 645 mm2)
b: Mounted on FR4 board
(25.4 mm × 25.4 mm × 1.6 mm , C u Pad : 0. 58 mm2)
Pulse width t
w
(s)
Rth – tw
Transient thermal impedance Rth (°C/W )
0.001
1000
0.01
0.1 1 100
10
100
1000
1
10
Single pulse
a. Mounted on FR4 board
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2)
b. Mounted on FR4 board
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 0.58 mm2
)
600
SSM3J46CTB
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RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collect i vely "Product " ) without not ice.
• This document and any information herein may not be reproduced without pri or written permission from TOSHIBA. Even with
TOSHIBA's written permission, reproduct i on is permiss i bl e only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliabil ity, Product can malfunction or fail. Customers are
responsibl e for compl ying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimi ze risk and avoid situations in which a malfunction or fai l ure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corrupti on. Before c ust om ers use the Product, create designs including the
Product, or incorporat e the Product into thei r own applicati ons, c ustomers must also refer to and comply with (a) the l atest ver sions of
all relevant TOSHIBA informati on, includi ng without limi tation, this document, the specif ications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook " and (b) the
instruct i ons for the applicati on with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, includi ng but not limit ed to (a) determini ng the appropriateness of the use of this Product in suc h
design or applications; (b) evaluat ing and determ i ni ng the applic ability of any inform ation contained in this document, or in charts,
diagrams, programs, al gorithms , sample application circuits, or any other referenced documents; and (c) validating all operating
parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILI TY FOR CUSTOMERS' PRODUCT DESIGN OR
APPLICATIONS.
• PRODUCT IS NEI THE R INTENDE D NO R WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
EXTRAORDINARILY HIGH LEVELS OF QU ALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHI CH
MAY CAUSE LOSS OF HUMAN LIFE, BO DILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT
("UNINTENDED USE"). E xcept for s peci fic applic at i ons as expressl y stated in this document, Unintended Use i ncludes, without
limitation, equipment used in nuclear fac ilities, equi pment used in the aerospace industry, medical equipm ent, equipment us ed for
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including without limi tation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIAB IL ITY FOR DAMAGES OR LOSSES
OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICAB LE LAWS AND REGULATIONS.