LTC2756
1
2756f
Typical applicaTion
FeaTures
applicaTions
DescripTion
Serial 18-Bit SoftSpan
IOUT DAC
The LTC
®
2756 is an 18-bit multiplying serial-input, cur-
rent-output digital-to-analog converter. LTC2756A provides
full 18-bit performance—INL and DNL of ±1LSB maxi-
mum—over temperature without any adjustments. 18-bit
monotonicity is guaranteed in all performance grades. This
SoftSpan™ DAC operates from a single 3V to 5V supply
and offers six output ranges (up to ±10V) that can be
programmed through the 3-wire SPI serial interface or
pin-strapped for operation in a single range.
Any on-chip register (including DAC output-range set-
tings) can be read for verification in just one instruction
cycle; and if you change register content, the altered
register will be automatically read back during the next
instruction cycle.
Voltage-controlled offset and gain adjustments are also
provided; and the power-on reset circuit and CLR pin both
reset the DAC output to 0V regardless of output range.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation and SoftSpan is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
18-Bit Voltage Output DAC with Software-Selectable Ranges
n Maximum 18-Bit INL Error: ±1 LSB Over Temperature
n Program or Pin-Strap Six Output Ranges:
0V to 5V, 0V to 10V, –2.5V to 7.5V, ±2.5V, ±5V, ±10V
n Guaranteed Monotonic Over Temperature
n Glitch Impulse 0.4nV•s (3V), 2nV•s (5V)
n 18-Bit Settling Time: 2.1µs
n 2.7V to 5.5V Single Supply Operation
n Reference Current Constant for All Codes
n Voltage-Controlled Offset and Gain Trims
n Serial Interface with Readback of All Registers
n Clear and Power-On-Reset to 0V Regardless of
Output Range
n 28-Pin SSOP Package
n Instrumentation
n Medical Devices
n Automatic Test Equipment
n Process Control and Industrial Automation
LTC2756 Integral Nonlinearity
150pF
+
–
LT1012
–
+
LT1468
18-BIT DAC WITH SPAN SELECT
LTC2756
VOSADJ
RCOM
RIN ROFS
REF
5V
REF RFB
IOUT1
VOUT
IOUT2
GND
VDD
GND
GAIN
ADJUST
GEADJ
27pF
0.1µF
5V
4
2756 TA01a
SPI WITH
READBACK
OFFSET
ADJUST
CODE
0 65536
–1.0
INL (LSB)
–0.8
–0.6
–0.4
–0.2
0.6
0.4
0.2
0
0.8
1.0
131072 196608 262143
2756 TA01b
0V TO 10V RANGE
LTC2756
2
2756f
absoluTe MaxiMuM raTings
IOUT1, IOUT2 to GND................................................±0.3V
RIN, RCOM, REF, RFB, ROFS, VOSADJ,
GEADJ to GND ......................................................... ±18V
VDD to GND ..................................................–0.3V to 7V
Digital Inputs to GND ................................... –0.3V to 7V
Digital Outputs to GND .... –0.3V to VDD+0.3V (Max 7V)
Operating Temperature Range
LTC2756C ................................................ 0°C to 70°C
LTC2756I .............................................–40°C to 85°C
Maximum Junction Temperature .......................... 150°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................... 300°C
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2756BCG#PBF LTC2756BCG#TRPBF LTC2756G 28-Lead Plastic SSOP 0°C to 70°C
LTC2756BIG#PBF LTC2756BIG#TRPBF LTC2756G 28-Lead Plastic SSOP –40°C to 85°C
LTC2756ACG#PBF LTC2756ACG#TRPBF LTC2756G 28-Lead Plastic SSOP 0°C to 70°C
LTC2756AIG#PBF LTC2756AIG#TRPBF LTC2756G 28-Lead Plastic SSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
pin conFiguraTion
(Notes 1, 2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ROFS
REF
RCOM
GEADJ
RIN
GND
IOUT2
GND
CS/LD
SDI
SCK
SRO
GND
VDD
RFB
RFB
IOUT1
VOSADJ
GND
LDAC
S2
S1
S0
M-SPAN
RFLAG
CLR
GND
GND
TJMAX = 150°C, θJA = 95°C/W
LTC2756
3
2756f
elecTrical characTerisTics
VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes the
specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS
LTC2756B LTC2756A
UNITSMIN TYP MAX MIN TYP MAX
Static Performance
Resolution l18 18 Bits
Monotonicity l18 18 Bits
DNL Differential Nonlinearity l±1 ±0.25 ±1 LSB
INL Integral Nonlinearity l±2 ±0.5 ±1 LSB
GE Gain Error All Output Ranges l±40 ±5 ±28 LSB
Gain Error Temperature Coefficient ∆Gain/∆Temp ±0.25 ±0.25 ppm/°C
BZE Bipolar Zero Error All Bipolar Ranges l±24 ±2.5 ±16 LSB
Bipolar Zero Temperature Coefficient ±0.15 ±0.15 ppm/°C
Unipolar Zero-Scale Error Unipolar Ranges (Note 3) l±0.03 ±3.2 ±0.03 ±3.2 LSB
PSR Power Supply Rejection VDD = 5V, ±10%
VDD = 3V, ±10%
l
l
±1.6
±4
±0.05
±0.2
±0.8
±2
LSB/V
LSB/V
ILKG IOUT1 Leakage Current TA = 25°C
TMIN to TMAX
l
±0.05 ±2
±5
±0.05 ±2
±5
nA
nA
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Analog Pins
Reference Inverting Resistors (Note 4) l16 20 kΩ
RREF DAC Input Resistance (Notes 5, 6) l8 10 kΩ
RFB Feedback Resistors (Note 6) l8 10 kΩ
ROFS Bipolar Offset Resistors (Note 6) l16 20 kΩ
RVOSADJ Offset Adjust Resistors l1024 1280 kΩ
RGEADJ Gain Adjust Resistors l2048 2560 kΩ
CIOUT1 Output Capacitance Full-Scale
Zero-Scale
90
40
pF
Dynamic Performance
Output Settling Time Span Code = 0000, 10V Step. To ±0.0004% FS
(Note 7)
2.1 μs
Glitch Impulse VDD = 5V (Note 8)
VDD = 3V (Note 8)
2
0.4
nV•s
nV•s
Digital-to-Analog Glitch Impulse VDD = 5V (Note 9)
VDD = 3V (Note 9)
2.6
0.6
nV•s
nV•s
Reference Multiplying BW 0V to 5V Range,
Code = Full Scale, –3dB Bandwidth
1 MHz
Multiplying Feedthrough Error 0V to 5V Range, VREF = ±10V, 10kHz
Sine Wave
0.4 mV
THD Total Harmonic Distortion (Note 10) Multiplying –108 dB
Output Noise Voltage Density (Note 11) at IOUT1 13 nV/√Hz
VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes specifications that apply over the full operating temperature range,
otherwise specifications are at TA = 25°C.
LTC2756
4
2756f
TiMing characTerisTics
The l denotes specifications that apply over the full operating temperature range,
otherwise specifications are at TA = 25°C.
elecTrical characTerisTics
VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes the
specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
VDD Supply Voltage l2.7 5.5 V
IDD Supply Current, VDD Digital Inputs = 0V or VDD l0.5 1 μA
Digital Inputs
VIH Digital Input High Voltage 3.3V ≤ VDD ≤ 5.5V
2.7V ≤ VDD < 3.3V
l
l
2.4
2
V
V
VIL Digital Input Low Voltage 4.5V < VDD ≤ 5.5V
2.7V ≤ VDD ≤ 4.5V
l
l
0.8
0.6
V
V
Hysteresis Voltage 0.1 V
IIN Digital Input Current VIN = GND to VDD l±1 µA
CIN Digital Input Capacitance VIN = 0V (Note 12) l6 pF
Digital Outputs
VOH IOH = 200µA 2.7V ≤ VDD ≤ 5.5V lVDD – 0.4 V
VOL IOL = 200µA 2.7V ≤ VDD ≤ 5.5V l0.4 V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD = 4.5V to 5.5V
t1SDI Valid to SCK Set-Up l7 ns
t2SDI Valid to SCK Hold l7 ns
t3SCK High Time l11 ns
t4SCK Low Time l11 ns
t5CS/LD Pulse Width l9 ns
t6LSB SCK High to CS/LD High l4 ns
t7CS/LD Low to SCK Positive Edge l4 ns
t8CS/LD High to SCK Positive Edge l4 ns
t9SRO Propagation Delay CLOAD = 10pF l18 ns
t10 CLR Pulse Width Low l36 ns
t11 LDAC Pulse Width Low l15 ns
t12 CLR Low to RFLAG Low CLOAD = 10pF (Note 12) l50 ns
t13 CS/LD High to RFLAG High CLOAD = 10pF (Note 12) l40 ns
SCK Frequency 50% Duty Cycle (Note 13) l40 MHz
VDD = 2.7V to 3.3V
t1SDI Valid to SCK Set-Up l9 ns
t2SDI Valid to SCK Hold l9 ns
t3SCK High Time l15 ns
t4SCK Low Time l15 ns
t5CS/LD Pulse Width l12 ns
t6LSB SCK High to CS/LD High l5 ns
LTC2756
5
2756f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: Calculation from feedback resistance and IOUT1 leakage current
specifications; not production tested. In most applications, unipolar zero-
scale error is dominated by contributions from the output amplifier.
Note 4: Input resistors measured from RIN to RCOM; feedback resistors
measured from RCOM to REF.
Note 5: DAC input resistance is independent of code.
Note 6: Parallel combination of the resistances from the specified pin to
IOUT1 and from the specified pin to IOUT2.
Note 7: Using LT1468 with CFEEDBACK = 27pF. A ±0.0004% settling time
of 1.8µs can be achieved by optimizing the time constant on an individual
basis. See Application Note 120, 1ppm Settling Time Measurement for a
Monolithic 18-Bit DAC.
TiMing characTerisTics
The l denotes specifications that apply over the full operating temperature range,
otherwise specifications are at TA = 25°C.
Note 8: Measured at the major carry transition, 0V to 5V range. Output
amplifier: LT1468; CFB = 50pF.
Note 9: Full-scale transition; REF = 0V.
Note 10: REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output
amplifier = LT1468.
Note 11: Calculation from Vn = √4kTRB, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (Ω), T = temperature (°K), and B =
bandwidth (Hz). 0V to 5V Range; zero-, mid-, or full-scale.
Note 12: Guaranteed by design; not production tested.
Note 13: When using SRO, maximum SCK frequency fMAX is limited by
SRO propagation delay t9 as follows:
fMAX =1
2 t9+tS
( )
, where tS is the setup time of the receiving device.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t7CS/LD Low to SCK Positive Edge l5 ns
t8CS/LD High to SCK Positive Edge l5 ns
t9SRO Propagation Delay CLOAD = 10pF l26 ns
t10 CLR Pulse Width Low l60 ns
t11 LDAC Pulse Width Low l20 ns
t12 CLR Low to RFLAG Low CLOAD = 10pF (Note 12) l70 ns
t13 CS/LD High to RFLAG high CLOAD = 10pF (Note 12) l60 ns
SCK Frequency 50% Duty Cycle (Note 13) l25 MHz
LTC2756
6
2756f
INL vs Temperature
DNL vs Temperature
Gain Error vs Temperature
Bipolar Zero Error
vs Temperature
INL vs Reference Voltage
DNL vs Reference Voltage
Typical perForMance characTerisTics
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
VDD = 5V, V(RIN) = 5V, TA = 25°C, unless otherwise noted.
INL vs Output Range
CODE
0 65536
–1.0
INL (LSB)
–0.8
–0.6
–0.4
–0.2
0.6
0.4
0.2
0
0.8
1.0
131072 196608 262143
2756 G01
0V TO 10V RANGE
CODE
0 65536
–1.0
DNL (LSB)
–0.8
–0.6
–0.4
–0.2
0.6
0.4
0.2
0
0.8
1.0
131072 196608 262143
2756 G02
0V TO 10V RANGE
OUTPUT RANGE
–2.5V
TO
2.5V
–2.5V
TO
7.5V
–1.0
INL (LSB)
–0.8
–0.6
–0.4
–0.2
0.4
0.2
0
0.6
0.8
1.0
0V
TO
5V
–5V
TO
5V
–10V
TO
10V
0V
TO
10V
2756 G03
TEMPERATURE (°C)
–40 –20
–1.0
INL (LSB)
–0.8
–0.6
–0.4
–0.2
0.4
0.2
0
0.6
0.8
1.0
0 20 806040 85
2756 G04
+INL
–INL
0V TO 10V RANGE
TEMPERATURE (°C)
–40 –20
–1.0
DNL (LSB)
–0.8
–0.6
–0.4
–0.2
0.4
0.2
0
0.6
0.8
1.0
0 20 806040 85
2756 G05
+DNL
–DNL
0V TO 10V RANGE
TEMPERATURE (°C)
–40 –20
0
GE (LSB)
4
8
12
20
16
24
28
32
0 20 806040 85
2756 G06
±0.25ppm/°C TYP ±2.5V
±5V
±10V
0V TO 5V
0V TO 10V
–2.5V TO 7.5V
TEMPERATURE (°C)
–40 –20
–16
BZE (LSB)
–12
–8
–4
4
0
8
12
16
0 20 806040 85
2756 G07
±5V
±10V
±2.5V
–2.5V TO 7.5V
±0.15ppm/°C TYP
V(RIN) (V)
–10 –2–6 –4
–1.0
INL (LSB)
–0.8
–0.6
–0.2
–0.4
0.4
0.2
0
0.6
0.8
1.0
0 2 864 10
2756 G08
–8
+INL
–INL
+INL
–INL
±5V RANGE
V(RIN) (V)
–10 –2–6 –4
–1.0
DNL (LSB)
–0.8
–0.6
–0.2
–0.4
0.4
0.2
0
0.6
0.8
1.0
0 2 864 10
2756 G09
–8
+DNL
–DNL
+DNL
–DNL
±5V RANGE
LTC2756
7
2756f
Typical perForMance characTerisTics
Settling Full-Scale Step
INL vs VDD
DNL vs VDD
Logic Threshold
vs Supply Voltage
Supply Current
vs Logic Input Voltage
Supply Current
vs Update Frequency
Mid-Scale Glitch (VDD = 3V)
DIGITAL INPUT VOLTAGE (V)
0
SUPPLY CURRENT (mA)
3
4
5
4
2756 G16
2
1
01235
VDD = 5V
CLR, LDAC, SDI, SCK,
CS/LD TIED TOGETHER
VDD = 3V
VDD (V)
2.5
0.5
LOGIC THRESHOLD (V)
0.75
1
1.25
1.5
2
33.5 4 4.5 5 5.5
1.75
2756 G17
RISING
FALLING
SCK FREQUENCY (Hz)
1
0.0001
SUPPLY CURRENT (mA)
0.001
0.01
0.1
1
10
100
VDD = 5V
100 10k 1M 100M
2756 G18
VDD = 3V
ALTERNATING ZERO-SCALE
AND FULL-SCALE
500ns/DIV
CS/LD
5V/DIV
GATED
SETTLING
WAVEFORM
100µV/DIV
(AVERAGED)
2756 G13
LT1468 AMP; CFEEDBACK = 20pF
0V TO 10V STEP
VREF = –10V; SPAN CODE = 0000
tSETTLE = 1.8µs to 0.0004% (18 BITS)
VDD = 5V, V(RIN) = 5V, TA = 25°C, unless otherwise noted.
Mid-Scale Glitch (VDD = 5V)
Multiplying Frequency Response
vs Digital Code
ALL BITS ON
ALL BITS OFF
FREQUENCY (Hz)
100 1k 10k
–140
ATTENUATION (dB)
–100
–120
–60
–80
–40
–20
0
1M100k 10M
2756 G12
0V TO 5V OUTPUT RANGE
LT1468 OUTPUT AMPLIFIER
CFEEDBACK = 15pF
ALL BITS OFF
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VDD (V)
2.5 3.5 4
–1.0
INL (LSB)
–0.8
–0.6
–0.2
–0.4
0.4
0.2
0
0.6
0.8
1.0
54.5 5.5
2756 G10
3
+INL
–INL
0V TO 10V RANGE
VDD (V)
2.5 3.5 4
–1.0
DNL (LSB)
–0.8
–0.6
–0.2
–0.4
0.4
0.2
0
0.6
0.8
1.0
54.5 5.5
2756 G11
3
+DNL
–DNL
0V TO 10V RANGE
500ns/DIV
CS/LD
5V/DIV
VOUT
5mV/DIV
(AVERAGED)
2756 G14
0V TO 5V RANGE
LT1468 OUTPUT AMPLIFIER
CFEEDBACK = 50pF
RISING MAJOR CARRY TRANSITION.
FALLING TRANSITION IS SIMILAR OR BETTER.
0.4nV•s TYP
500ns/DIV
CS/LD
5V/DIV
VOUT
5mV/DIV
(AVERAGED)
2756 G15
0V TO 5V RANGE
LT1468 OUTPUT AMPLIFIER
CFEEDBACK = 50pF
RISING MAJOR CARRY TRANSITION.
FALLING TRANSITION IS SIMILAR OR BETTER.
2nV•s TYP
LTC2756
8
2756f
pin FuncTions
ROFS (Pin 1): Bipolar Offset Resistor. This pin provides the
translation of the output voltage range for bipolar spans.
Accepts up to ±15V; for normal operation tie to the positive
reference voltage at RIN (Pin 5).
REF (Pin 2): DAC Reference Input, and Feedback Resistor
for the Reference Inverting Amplifier. The external reference
inverting amplifier sees as its load the 10k DAC reference
input resistance in parallel with the 20k feedback resis-
tor. For normal operation tie this pin to the output of the
reference inverting amplifier (see the Typical Applications
section). Typically 5V; accepts up to ±15V.
RCOM (Pin 3): Virtual Ground Point for the On-Chip Refer-
ence Inverting Resistors. These precision-matched 20k
resistors are included on the chip to facilitate generation
of the negative reference voltage needed to produce a
positive output polarity. They are connected internally from
RIN to RCOM and from RCOM to REF (see Block Diagram).
For normal operation tie RCOM to the negative input of
the external reference inverting amplifier (see the Typical
Applications section).
GEADJA (Pin 4): Gain Adjust Pin. This control pin can be
used to null gain error or to compensate for reference
errors. Nominal adjustment range is ±2048 LSB for a
voltage input range of ±VRIN (i.e., ±5V for a 5V reference
input). Tie to ground if not used.
RIN (Pin 5): Input Resistor for Reference Inverting Ampli-
fier. The 20k input resistor is connected internally from
RIN to RCOM. For normal operation tie RIN to the external
reference voltage (see the Typical Applications section).
Typically 5V; accepts up to ±15V.
GND (Pins 6, 8, 13, 15, 16, 24): Ground; tie to ground.
IOUT2 (Pin 7): Current Output Complement. Tie to ground
via a clean, low-impedance path.
CS/LD (Pin 9): Synchronous Chip Select and Load Input
Pin. A logic low on this pin enables SDI, SCK and SRO
(Pins 10, 11 and 12) for input and output of serial data.
SDI (Pin 10): Serial Data Input. Data is clocked in on the
rising edge of the serial clock (SCK, Pin 11) when CS/LD
(Pin 9) is low.
SCK (Pin 11): Serial Clock.
SRO (Pin 12): Serial Readback Output. Data is clocked out
on the falling edge of SCK. Readback data begins clock-
ing out after the first byte is clocked in. SRO is an active
output only when the chip is selected (i.e., when CS/LD is
low). Otherwise SRO presents a high-impedance output
in order to allow other parts to control the bus.
VDD (Pin 14): Positive Supply Input; 2.7V ≤ VDD ≤ 5.5V.
Bypass with a 0.1μF low-ESR capacitor to ground.
CLR (Pin 17): Asynchronous Clear Input. When this pin
is low, all DAC registers (both code and span) are cleared
to zero. The DAC output is cleared to zero volts.
RFLAG (Pin 18): Reset Flag Output. An active low output
is asserted when there is a power-on reset or a clear event.
Returns high when an Update command is executed.
M-SPAN (Pin 19): Manual Span Control Pin. M-SPAN is
used in conjunction with pins S0, S1 and S2 (Pins 20, 21
and 22) to configure the DAC for operation in a single,
fixed output range.
To configure the part for manual-span use, tie M-SPAN
directly to VDD. The active output range is then set via
hardware pin strapping of pins S2, S1 and S0 (rather than
through the SPI port); and Write and Update commands
have no effect on the active output span.
To configure the part for SoftSpan use, tie M-SPAN directly
to GND. The output ranges are then individually control-
lable through the SPI port; and pins S2, S1 and S0 have
no effect.
See Manual Span Configuration in the Operation section.
M-SPAN must be connected either directly to GND
(SoftSpan configuration) or to VDD (manual-span con-
figuration).
LTC2756
9
2756f
pin FuncTions
S0 (Pin 20): Span Bit 0 Input. In Manual Span mode
(M-SPAN tied to VDD), pins S0, S1 and S2 are pin-strapped
to select a single fixed output range. These pins must be
tied to either GND or VDD even if they are unused.
S1 (Pin 21): Span Bit 1 Input. In Manual Span mode
(M-SPAN tied to VDD), pins S0, S1 and S2 are pin-strapped
to select a single fixed output range. These pins must be
tied to either GND or VDD even if they are unused.
S2 (Pin 22): Span Bit 2 Input. In Manual Span mode
(M-SPAN tied to VDD), pins S0, S1 and S2 are pin-strapped
to select a single fixed output range. These pins must be
tied to either GND or VDD even if they are unused.
LDAC (Pin 23): Asynchronous DAC Load Input. When LDAC
is logic low, the DAC is updated (CS/LD must be high).
VOSADJ (Pin 25): Offset Adjust Pin. This control pin
can be used to null unipolar offset or bipolar zero error.
The offset-voltage delta is inverted and attenuated such
that a 5V control voltage applied to VOSADJ produces
∆VOS = –2048 LSB in any output range (assumes a 5V
reference voltage at RIN). See System Offset and Gain
Adjustments in the Operation section. Tie to ground if
not used.
IOUT1 (Pin 26): Current Output Pin. This pin is a virtual
ground when the DAC is operating and should reside at
0V. For normal operation tie to the negative input of the
I/V converter amplifier (see the Typical Applications sec-
tion).
RFB (Pins 27, 28): Feedback Resistor. For normal operation
tie both pins to the output of the I/V converter amplifier
(see the Typical Applications section). The DAC output
current from IOUT1 flows through the feedback resistor
to the RFB pins.
LTC2756
10
2756f
block DiagraM
18-BIT DAC WITH SPAN SELECT
INPUT REGISTER
RCOM
RIN
DAC REGISTER
SPAN
REGISTERS
CODE
REGISTERS
INPUT REGISTER
DAC REGISTER
R2
20k
R1
20k
ROFS
REF RFB
27, 28
IOUT1
VOSADJ
2.56M
IOUT2
2756 BD
POWER-ON
RESET 3
3
CONTROL AND READBACK LOGIC
18
18
26
25
3 2
GEADJ
4
VDD
VDD 7
SRO
12
RFLAG
18
14
5
GND
(6, 8, 13, 15, 16, 24)
M-SPAN S0 S1 S2 LDAC
23
CS/LD
9
SDI
10
SCK
11
CLR
1719 20 21 22
1
LTC2756
11
2756f
SDI
SRO Hi-Z
CS/LD
SCK
LSB 2756 TD
LSB
t2
t9
t8
t5t7
1 2 31 32
t6
t1
LDAC
t3t4
t11
TiMing DiagraM
LTC2756
12
2756f
operaTion
Output Ranges
The LTC2756 is a current-output, serial-input precision
multiplying DAC with selectable output ranges. Ranges
can either be programmed in software for maximum
flexibility—the DAC can be programmed to any one of six
output ranges—or hardwired through pin-strapping. Two
unipolar ranges are available (0V to 5V and 0V to 10V), and
four bipolar ranges (±2.5V, ±5V, ±10V and –2.5V to 7.5V).
These ranges are obtained when an external precision 5V
reference is used. The output ranges for other reference
voltages are easy to calculate by observing that each range
is a multiple of the external reference voltage. The ranges
can then be expressed: 0 to 1×, 0 to 2×, ±0.5×, ±1×, ±2×,
and –0.5× to 1.5×.
Manual Span Configuration
Multiple output ranges are not needed in some applica-
tions. To configure the LTC2756 to operate in a single span
without additional operational overhead, tie the M-SPAN
pin directly to VDD. The active output range is then set via
hardware pin strapping of pins S2, S1 and S0 (rather than
through the SPI port); and Write and Update commands
have no effect on the active output span. See Figure 1
and Table 2.
Tie the M-SPAN pin to ground for normal SoftSpan
operation.
LTC2756
M-SPAN
S2
S1
S0
2756 F01
CS/LD SDI SCK
VDD
VDD
±10V
–
+
Figure 1. Using M-SPAN to Configure the LTC2756
for Single-Span Operation (±10V Range Shown)
Input and DAC Registers
The LTC2756 has two sets of double-buffered regis-
ters—one set for the code data, and one for the output
range of the DAC—plus one readback register, for a total
of five registers. Double buffering provides the capability to
simultaneously update the span (output range) and code,
which allows smooth voltage transitions when changing
output ranges.
Each set of double-buffered registers comprises an Input
register and a DAC register.
Input register: The Write operation shifts data from the
SDI pin into a chosen Input register. The Input registers
are holding buffers; Write operations do not affect the
DAC outputs.
DAC register: The Update operation copies the contents
of an Input register to its associated DAC register. The
contents of a DAC register directly updates the associated
DAC output voltage or output range.
Note that updates always include both Code and Span
register sets; but the values held in the DAC registers will
only change if the associated Input register values have
previously been altered via a Write operation.
LTC2756
13
2756f
operaTion
when checking the output range. In both cases, all other
bits in the 24-bit data field are filled by zeros. Figure 2
shows the input and readback sequences.
The data outputted by SRO is always in the same position
and sequence as the input data. Note, however, that this
means that the SRO data shifts out one-half clock cycle
earlier than the corresponding bit shifting in on SDI. For
example, code bit D9, which is shifted in to SDI on the
rising edge of SCK clock 17, is clocked out of SRO on the
falling edge of clock 16. This allows D9 to be clocked to an
external microprocessor on the rising edge of clock 17.
For Read commands, the requested data is shifted out of
SRO in the 3-byte (24-bit) data field immediately after the
command byte. There is no instruction-cycle latency for
Read commands; the data shifts out in the same instruc-
tion cycle in which it was requested.
For non-read (i.e., Write and/or Update) commands, SRO
automatically shifts out the contents of the buffer that
was acted upon in the preceding command. This “rolling
readback” default mode of operation can dramatically re-
duce the number of instruction cycles needed, since most
commands can be verified during subsequent commands
with no additional overhead. A conceptual flow diagram
is shown in Figure 3. Table 1 shows, for each anteced-
ent command, which register (‘readback pointer’) will be
copied into the Readback register and outputted from SRO
during the following instruction cycle.
Span Readback in Manual Span Configuration
If the Span DAC register is chosen for readback, SRO
responds by outputting the actual output span; this is true
whether the LTC2756 is configured for SoftSpan (M-SPAN
tied to GND) or manual span (M-SPAN tied to VDD).
In SoftSpan configuration, SRO outputs the span code
from the Span DAC register (programmed through the
SPI port). In manual span configuration, the active output
range is controlled by pins S2, S1 and S0, so SRO outputs
the logic values of these pins. The span code bits S2, S1
and S0 always appear in the same order and positions in
the SRO output sequence; see Figure 2.
Serial Interface
When the CS/LD pin is taken low, the data on the SDI pin
is loaded into the shift register on the rising edge of the
clock (SCK pin). The loading sequence required for the
LTC2756 is one byte consisting of a 4-bit command word
(C3 C2 C1 C0) and four zeros, then three bytes (24 bits)
of data.
When writing a code, the code data is left (MSB) justified;
so that the 24-bit data field consists of 18 code bits fol-
lowed by 6 don’t-care bits.
When writing an output range, the span data should oc-
cupy the last 4 bits of the second data byte, ordered S3
through S0. Figure 2 shows the SDI input word syntax
for writing.
When CS/LD is low, the SRO pin (Serial Readback Output)
is an active output. The readback data begins after the
first byte has been shifted in to SDI. SRO outputs a logic
low from the falling edge of CS/LD until the Readback
data begins.
When CS/LD is high, the SRO pin presents a high imped-
ance (three-state) output.
LDAC is an asynchronous update pin. When LDAC is taken
low, the DAC is updated with code and span data (data in
the Input buffers is copied into the DAC buffers). CS/LD
must be high during this operation; otherwise LDAC is
locked out and will have no effect. The use of LDAC is
functionally identical to the serial input command.
The codes for the command (C3-C0) are defined in Table 1.
Readback
In addition to the Code and Span register sets, the LTC2756
has one Readback register. At the end of every instruc-
tion cycle, the contents of one of the on-chip registers is
copied into the Readback register and serially shifted out
through the SRO pin.
Readback data always appears in the 24-bit data field,
starting on the falling SCK edge immediately after the
first byte is shifted in on SDI. When reading a code, code
data occupies the first 18 bits of the 24-bit field; and the
span bits are the last four bits of the second data byte
LTC2756
14
2756f
Table 1. Command Codes
CODE
COMMAND
READBACK POINTER–
CURRENT INPUT WORD W0
READBACK POINTER–
NEXT INPUT WORD W+1
C3 C2 C1 C0
0 0 1 0 Write Span Set by Previous Command Input Span Register
0 0 1 1 Write Code Set by Previous Command Input Code Register
0 1 0 0 Update Set by Previous Command DAC Span Register
0 1 1 0 Write Span; Update Set by Previous Command DAC Span Register
0 1 1 1 Write Code; Update Set by Previous Command DAC Code Register
1 0 1 0 Read Input Span Register Input Span Register Input Span Register
1 0 1 1 Read Input Code Register Input Code Register Input Code Register
1 1 0 0 Read DAC Span Register DAC Span Register DAC Span Register
1 1 0 1 Read DAC Code Register DAC Code Register DAC Code Register
1 1 1 1 No Operation Set by Previous Command DAC Code Register
— System Clear — DAC Span Register
— Initial Power-Up or Power Interrupt — DAC Span Register
Codes not shown are reserved—do not use.
Table 2. Span Codes
S3 S2 S1 S0 SPAN
0 0 0 0 Unipolar 0V to 5V
0 0 0 1 Unipolar 0V to 10V
0 0 1 0 Bipolar –5V to 5V
0 0 1 1 Bipolar –10V to 10V
0 1 0 0 Bipolar –2.5V to 2.5V
0 1 0 1 Bipolar –2.5V to 7.5V
Codes not shown are reserved–do not use.
operaTion
LTC2756
15
2756f
operaTion
SDI C2 C1 C0 0 0 0 0 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2C3 D0 X X X X X XD1
SDI C2 C1 C0 0 0 0 0 X X X X X X X X X X X X S3 S2 S1 S0C3 X X X X X X XX
SRO 0 0 0 0 0 0 0 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D20 D0 0 0 0 0 0 0D1
COMMAND 4 ZEROS 18-BIT DAC CODE 6 DON’T-CARE
COMMAND
Hi-Z
4 ZEROS 12 DON’T-CARE SPAN
2756 F02
8 DON’T-CARE
READBACK CODE
WRITE CODE
WRITE SPAN
SRO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S3 S2 S1 S00 0 0 0 0 0 0 00
Hi-Z
READBACK SPAN
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CS/LD
SCK
Figure 2. Serial Input and Output Sequences
LTC2756
16
2756f
operaTion
SDI
SRO ...
WRITE CODE
READ CODE
INPUT REGISTER
WRITE SPAN
READ SPAN
INPUT REGISTER
UPDATE
READ SPAN
DAC REGISTER
WRITE CODE
READ CODE
INPUT REGISTER
...
2756 F03
Figure 3. Rolling Readback Example
LTC2756
17
2756f
operaTion
Examples
1. Load ±5V range with the output at 0V. Note that since
span and code are updated together, the output stays
at 0V throughout the example.
a) CS/LD ↓. Clock SDI:
00100000 XXXXXXXX XXXX0010 XXXXXXXX
b) CS/LD ↑
Span Input register – range set to bipolar ±5V.
c) CS/LD ↓. Clock SDI:
00110000 10000000 00000000 00XXXXXX
d) CS/LD ↑
Code Input register – code set to mid-scale.
e) CS/LD ↓. Clock SDI:
01000000 XXXXXXXX XXXXXXXX XXXXXXXX
f) CS/LD ↑
Update code and range.
Alternatively steps e and f could be replaced with
LDAC .
2. Load ±10V range with the output at 5V, changing to
–5V.
a) CS/LD ↓. Clock SDI:
00110000 11000000 00000000 00XXXXXX
b) CS/LD ↑
Code Input register set to ¾-scale code.
c) CS/LD ↓. Clock SDI:
01100000 XXXXXXXX XXXX0011 XXXXXXXX
d) CS/LD ↑
Span Input register set to ±10V range. Update
code and range. Output goes to 5V.
g) CS/LD ↓. Clock SDI:
01110000 01000000 00000000 00XXXXXX
h) CS/LD ↑
Code Input register set to ¼-scale code. Update
code and range (note update does not change
range, since no new range has been written).
Output goes to –5V.
3. Write and update mid-scale code in 0V to 10V range
(VOUT = 5V) using readback to check the contents of
the Input registers before updating.
a) CS/LD ↓. Clock SDI:
00110000 10000000 00000000 00XXXXXX
b) CS/LD ↑
Code Input register set to mid-scale.
c) CS/LD ↓. Clock SDI:
00100000 XXXXXXXX XXXX0001 XXXXXXXX
Data out on SRO:
00000000 10000000 00000000 00000000
Verifies Code Input register set to mid-scale.
d) CS/LD ↑
Span Input register set to 0V to 10V range.
e) CS/LD ↓. Clock SDI:
10100000 XXXXXXXX XXXXXXXX XXXXXXXX
Data out on SRO:
00000000 00000000 00000001 00000000
Verifies Span Input register set to 0V to 10V
range.
f) CS/LD ↑
g) CS/LD ↓. Clock SDI:
01000000 XXXXXXXX XXXXXXXX XXXXXXXX
h) CS/LD ↑
Update code and range. Output goes to 5V.
LTC2756
18
2756f
System Offset and Reference Adjustments
Many systems require compensation for overall system
offset. This may be an order of magnitude or more greater
than the offset of the LTC2756, which is so low as to be
dominated by external output amplifier errors even when
using the most precise op amps.
The offset adjust pin VOSADJ can be used to null unipolar
offset or bipolar zero error. The offset change expressed
in LSB is the same for any output range:
∆VOS LSB
[ ]
=
–V(V
OSADJ
)
V(RIN )•2048
A 5V control voltage applied to VOSADJ produces ∆VOS =
–2048 LSB in any output range, assuming a 5V reference
voltage at RIN.
In voltage terms, the offset delta is attenuated by a factor
of 32, 64 or 128, depending on the output range. (These
functions hold regardless of reference voltage.)
∆VOS = –(1/128)VOSADJ [0V to 5V, ±2.5V spans]
∆VOS = –(1/64)VOSADJ [0V to 10V, ±5V, –2.5V to
7.5V spans]
∆VOS = –(1/32)VOSADJ [±10V span]
The gain error adjust pins GEADJ can be used to null gain
error or to compensate for reference errors. The gain er-
ror change expressed in LSB is the same for any output
range:
∆GE =V(GEADJ )
V(RIN )•2048
The gain-error delta is non-inverting for positive reference
voltages.
Note that this pin compensates the gain by altering the
inverted reference voltage V(REF). In voltage terms, the
V(REF) delta is inverted and attenuated by a factor of
128.
∆V(REF) = –(1/128)GEADJ
The nominal input range of these pins is ±5V; other volt-
ages of up to ±15V may be used if needed. However, do
operaTion
not use voltages divided down from power supplies; ref-
erence-quality, low-noise inputs are required to maintain
the best DAC performance.
The VOSADJ pin has an input impedance of 1.28MΩ. It
should be driven with a Thevenin-equivalent impedance
of 10k or less to preserve the settling performance of
the LTC2756. The VOSADJ pin should be shorted to GND
if not used.
The GEADJ pin has an input impedance of 2.56MΩ, and
is intended for use with fixed reference voltages only. It
should be shorted to GND if not used.
Power-On Reset and Clear
When power is first applied to the LTC2756, the DAC
powers up in unipolar 5V mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC output
initializes to zero volts.
If the part is configured for manual span operation, the
DAC will be set into the pin-strapped range at the first
Update command. This allows the user to simultaneously
update span and code for a smooth voltage transition into
the chosen output range.
When the CLR pin is taken low, a system clear results.
The DAC buffers are reset to 0 and the DAC output is reset
to zero volts. The Input buffers are left intact, so that any
subsequent Update command (including the use of LDAC)
restores the DAC to its previous state.
If CLR is asserted during an instruction, i.e., when CS/LD
is low, the instruction is aborted. Integrity of the relevant
Input buffers is not guaranteed under these conditions,
therefore the contents should be checked using readback
or replaced.
The RFLAG pin is used as a flag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
at power-up, system clear, or if the supply VDD dips below
approximately 2V; and stays asserted until any valid Update
command is executed.
LTC2756
19
2756f
Op Amp Selection
Because of the extremely high accuracy of the 18-bit
LTC2756, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
applicaTions inForMaTion
Table 4. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1
Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp.
Tables 3 and 4 contain equations for evaluating the ef-
fects of op amp parameters on the LTC2756’s accuracy
when programmed in a unipolar or bipolar output range.
These are the changes the op amp can cause to the INL,
DNL, unipolar offset, unipolar gain error, bipolar zero and
bipolar gain error.
Table 5 contains a partial list of LTC precision op amps
recommended for use with the LTC2756. The easy-to-use
design equations simplify the selection of op amps to meet
the system’s specified error budget. Select the amplifier
from Table 5 and insert the specified op amp parameters
in Table 4. Add up all the errors for each category to de-
termine the effect the op amp has on the accuracy of the
part. Arithmetic summation gives an (unlikely) worst-case
effect. A root-sum-square (RMS) summation produces a
more realistic estimate.
A3•VOS1•78.6•
IB1•0.524•
0
A4•VOS2•52.4•
A4•IB2•0.524•
A4•
( )
5V
VREF
( )
5V
VREF
( )
66
AVOL1
OP AMP
VOS1 (mV)
IB1 (nA)
AVOL1 (V/mV)
VOS2 (mV)
IB2 (nA)
AVOL2 (V/mV)
VOS1•12.1•
IB1•0.0012•
A1•
0
0
0
INL (LSB)
( )
5V
VREF
( )
5V
VREF
( )
6
AVOL1
( )
262
AVOL2
( )
524
AVOL1
( )
524
AVOL1
( )
524
AVOL2
( )
524
AVOL2
VOS1•3.1•
IB1•0.00032•
A2•
0
0
0
DNL (LSB)
( )
5V
VREF
( )
5V
VREF
A3•VOS1•52.4•
IB1•0.524•
0
0
0
0
UNIPOLAR
OFFSET (LSB)
( )
5V
VREF
( )
5V
VREF
( )
5V
VREF
VOS1•52.4•
IB1•0.0072•
A5•
VOS2•104.8•
IB2•1.048•
BIPOLAR GAIN
ERROR (LSB)
( )
5V
VREF
( )
5V
VREF
( )
5V
VREF
( )
5V
VREF
BIPOLAR ZERO
ERROR (LSB)
UNIPOLAR GAIN
ERROR (LSB)
( )
5V
VREF
( )
5V
VREF
( )
5V
VREF
( )
5V
VREF
( )
5V
VREF
VOS1•52.4•
IB1•0.0072•
A5•
VOS2•104.8•
IB2•1.048•
Table 5. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC2756 with Relevant Specifications
AMPLIFIER
AMPLIFIER SPECIFICATIONS
VOS
µV
IB
nA
AVOL
V/mV
VOLTAGE
NOISE
nV/√Hz
CURRENT
NOISE
pA/√Hz
SLEW
RATE
V/µs
GAIN BANDWIDTH
PRODUCT
MHz
tSETTLING
with LTC2756
µs
POWER
DISSIPATION
mW
LTC1150 10 0.05 5600 90 0.0018 3 2.5 10ms 24
LT1001 25 2 800 10 0.12 0.25 0.8 120 46
LT1012 25 0.1 2000 14 0.02 0.2 1 120 11.4
LT1097 50 0.35 2500 14 0.008 0.2 0.7 120 11
LT1468 75 10 5000 5 0.6 22 90 2.1 117
Table 3. Coefficients for the Equations of Table 4
OUTPUT RANGE A1 A2 A3 A4 A5
5V 1.1 2 1 – 1
10V 2.2 3 0.5 – 1.5
±5V 2 2 1 1 1.5
±10V 4 4 0.83 1 2.5
±2.5V 1 1 1.4 1 1
–2.5V to 7.5V 1.9 3 0.7 0.5 1.5
LTC2756
20
2756f
applicaTions inForMaTion
Op amp offset contributes mostly to DAC output offset
and gain error, and has minimal effect on INL and DNL.
For example, consider the LTC2756 in unipolar 5V output
range. (Note that for this example, the LSB size is 19µV.)
An op amp offset of 35µV will cause 1.8LSB of output
offset, and 1.8LSB of gain error; but 0.4LSB of INL, and
just 0.1LSB of DNL.
While not directly addressed by the simple equations in
Tables 3 and 4, temperature effects can be handled just as
easily for unipolar and bipolar applications. First, consult
an op amp’s data sheet to find the worst-case VOS and IB
over temperature. Then, plug these numbers in the VOS
and IB equations from Table 4 and calculate the tempera-
ture-induced effects.
For applications where fast settling time is important, Ap-
plication Note 120,
1ppm Settling Time Measurement for
a Monolithic 18-Bit DAC
, offers a thorough discussion of
18-bit DAC settling time and op amp selection.
Recommendations
For DC or low-frequency applications, the LTC1150 is the
simplest 18-bit accurate output amplifier. An auto-zero
amp, its exceptionally low offset (10µV max) and offset
drift (0.01µV/°C) make nulling unnecessary. For swings
above 8V, add an LT1010 buffer to boost the load current
capability. The settling of auto-zero amps is a special case;
see Application Note 120,
1ppm Settling Time Measure-
ment for a Monolithic 18-Bit DAC
, Appendix E, for details.
The LT1012 and LT1001 are good intermediate output-amp
solutions that achieve moderate speed and good accuracy.
They are also excellent choices for the reference inverting
amplifier in fixed-reference applications.
For high speed applications, the LT1468 settles in 2.1µs.
Note that the 75µV max offset will degrade the INL at the
DAC output by up to 0.9LSB. For high-speed applications
demanding higher precision, the amplifier offset can be
nulled with a digital potentiometer.
Figure 5 shows a composite output amplifier that achieves
fast settling (8µs) and very low offset (3µV max) without
offset nulling. This circuit offers high open-loop gain
(1000V/mV min), low input bias current (0.15nA max),
fast slew rate (25V/µs min), and a high gain-bandwidth
product (30MHz typ). The high speed path consists of an
LTC6240, which is an 18MHz ultralow bias current amplifier,
followed by an LT1360, a 50MHz fast-slewing amplifier
which provides additional gain and the ability to swing
to ±10V at the output. Compensation is taken from the
output of the LTC6240, allowing the use of a much larger
compensation capacitor than if taken after the gain-of-five
stage. An LTC2054 auto-zero amplifier senses the voltage
at IOUT1 and drives the non-inverting input of the LTC6240
to eliminate the offset of the high speed path. The 100:1
attenuator and input filter reduce the low frequency noise
in this stage while maintaining low DC offset.
Precision Voltage Reference Considerations
Much in the same way selecting an operational amplifier
for use with the LTC2756 is critical to the performance of
the system, selecting a precision voltage reference also
requires due diligence. The output voltage of the LTC2756
is directly affected by the voltage reference; thus, any
voltage reference error will appear as a DAC output volt-
age error.
There are three primary error sources to consider
when selecting a precision voltage reference for 18-bit
applications: output voltage initial tolerance, output voltage
temperature coefficient and output voltage noise.
Initial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
with low output voltage initial tolerance, like the LTC6655
(±0.025%), minimizes the gain error caused by the refer-
ence; however, a calibration sequence that corrects for sys-
tem zero- and full-scale error is always recommended.
A reference’s output voltage temperature coefficient affects
not only the full-scale error, but can also affect the circuit’s
INL and DNL performance. If a reference is chosen with
a loose output voltage temperature coefficient, then the
DAC output voltage along its transfer characteristic will
be very dependent on ambient conditions. Minimizing
the error due to reference temperature coefficient can be
achieved by choosing a precision reference with a low
output voltage temperature coefficient and/or tightly con-
trolling the ambient temperature of the circuit to minimize
temperature gradients.
LTC2756
21
2756f
applicaTions inForMaTion
Table 6. Partial List of LTC Precision References Recommended
for Use with the LTC2756 with Relevant Specifications
REFERENCE
INITIAL
TOLERANCE
TEMPERATURE
DRIFT
0.1Hz to 10Hz
NOISE
LT1019A-5,
LT1019A-10
±0.05% max 5ppm/°C max 12µVP-P
LT1236A-5,
LT1236A-10
±0.05% max 5ppm/°C max 3µVP-P
LT1460A-5,
LT1460A-10
±0.075% max 10ppm/°C max 20µVP-P
LT1790A-2.5 ±0.05% max 10ppm/°C max 12µVP-P
LTC6652A-5 ±0.05% max 5ppm/°C max 2.8ppmP-P
LTC6655A-2.5
LTC6655A-5
±0.025% max 2ppm/°C max 0.25ppmP-P
As precision DAC applications move to 18-bit perfor-
mance, reference output voltage noise may contribute a
dominant share of the system’s noise floor. This in turn can
degrade system dynamic range and signal-to-noise ratio.
Care should be exercised in selecting a voltage reference
with as low an output noise voltage as practical for the
system resolution desired. Precision voltage references
like the LT1236 or LTC6655 produce low output noise in
the 0.1Hz to 10Hz region, well below the 18-bit LSB level
in 5V or 10V full-scale systems. However, as the circuit
bandwidths increase, filtering the output of the reference
may be required to minimize output noise.
Grounding
As with any high-resolution converter, clean grounding is
important. A low-impedance analog ground plane is nec-
essary, as are star grounding techniques. Keep the board
layer used for star ground continuous to minimize ground
resistances; that is, use the star-ground concept without
using separate star traces. The IOUT2 pin is of particular
importance; INL will be degraded by the code-dependent
currents carried by IOUT2 if voltage drops to ground are
allowed to develop. The best strategy here is to tie the pins
to the star ground plane by multiple vias located directly
underneath the part. Alternatively, the pin may be routed
to the star ground point if necessary; route a trace of no
more than 30 squares of 1oz copper.
In the rare case in which neither of these alternatives is
practicable, a force/sense amplifier should be used as a
ground buffer (see Figure 4). Note, however, that the volt-
age offset of the ground buffer amp directly contributes to
the effects on accuracy specified in Table 4 under ‘VOS1’.
The combined effects of the offsets can be calculated by
substituting the total offset from IOUT1 to IOUT2 for VOS1
in the equations.
LTC2756
22
2756f
applicaTions inForMaTion
Figure 4. If a Low-Impedance GND Plane Is Unavailable, Drive IOUT2 with a Force/Sense Amplifier As Shown.
Use Circuit A to Minimize Impact on Settling Time, or Circuit B for Lower Power Consumption and Better Accuracy
–
+
LT1468DAC
LTC2756
VREF
5V
2
6
3
6
IOUT1
27pF
IOUT2
RFB
VOSADJ
REF
RCOM
RIN
ROFS
VOUTA
–
+
6
1
2 3
IOUT2
2
3
*SCHOTTKY BARRIER DIODE
ZETEX*
BAT54S
LT1012
2756 F05
1000pF
CIRCUIT A
6
1
2 3
77
–
+
LT1468
3
ZETEX
BAT54S
2
200Ω
200Ω
IOUT2
150pF
3
2
GEADJ
–
+
LT1012
1
5
4
3
2
27, 28
26
7
25
CIRCUIT B
LTC2756
23
2756f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
package DescripTion
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
G28 SSOP 0204
0.09 – 0.25
(.0035 – .010)
0° – 8°
0.55 – 0.95
(.022 – .037)
5.00 – 5.60**
(.197 – .221)
7.40 – 8.20
(.291 – .323)
1 2 3 4 5678 9 10 11 12 1413
9.90 – 10.50*
(.390 – .413)
2526 22 21 20 19 18 17 16 1523242728
2.0
(.079)
MAX
0.05
(.002)
MIN
0.65
(.0256)
BSC 0.22 – 0.38
(.009 – .015)
TYP
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.42 ±0.03 0.65 BSC
5.3 – 5.7
7.8 – 8.2
RECOMMENDED SOLDER PAD LAYOUT
1.25 ±0.12
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC2756
24
2756f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 l FAX: (408) 434-0507 l www.linear.com
LINEAR TECHNOLOGY CORPORATION 2012
LT 0212 • PRINTED IN USA
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LTC2757 Single Parallel 18-Bit IOUT SoftSpan DAC ±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm LQFP-48 Package
LTC1592 Single Serial 16-/14-/12-Bit IOUT SoftSpan DACs ±1LSB INL/DNL, Software-Selectable Ranges, 16-Lead SSOP Package
LTC2751 Single Parallel 16-/14-/12-Bit IOUT SoftSpan DACs ±1LSB INL/DNL, Software-Selectable Ranges, 5mm × 7mm QFN-38 Package
LTC1597/LTC1591 Single Parallel 16-/14-Bit IOUT DACs ±1LSB INL/DNL, Integrated 4-Quadrant Resistors, 28-Lead SSOP Package
LTC2758 Dual Serial 18-Bit IOUT SoftSpan DAC ±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm LQFP-48 Package
LTC2754 Quad Serial 16-/12-Bit IOUT SoftSpan DACs ±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 8mm QFN-52 Package
LTC2704 Quad Serial 16-/14-/12-Bit VOUT SoftSpan DACs ±1LSB INL/DNL, Software-Selectable Ranges, Integrated Amplifiers
LTC2641/LTC2642 16-/14-/12-Bit VOUT DACs ±1LSB INL/DNL, 0.5nV•s Glitch, 1µs Settling, 3mm × 3mm DFN
References
LTC6655A-2.5/
LTC6655A-5
Low Drift Precision Buffered Reference 0.025% Max Tolerance, 2ppm/°C Max, 0.25ppmP-P 0.1Hz to 10Hz Noise
LT1236A-5/
LT1236A-10
Precision Reference 0.05% Max Tolerance, 5ppm/°C Max, 3µVP-P 0.1Hz to 10Hz Noise
LT1460A-5/
LT1460A-10
Micropower Precision Series Reference 0.075% Max Tolerance, 10ppm/°C Max, 20µVP-P 0.1Hz to 10Hz Noise
LT1790A-2.5 Micropower Low Dropout Reference 0.05% Max Tolerance, 10ppm/°C Max, 12µVP-P 0.1Hz to 10Hz Noise
LTC6652A-5 Precision Low Drift Low Noise Buffered Reference 0.05% Max Tolerance, 5ppm/°C Max, 2.8ppmP-P 0.1Hz to 10Hz Noise
Amplifiers
LT1150 Zero-Drift Op Amp with Internal Capacitors 10µV Max Offset, ±16V High Voltage Operation, 1.8µVP-P Noise
LT1012 Precision Op Amp 25µV Max Offset, 100pA Max Input Current, 0.5µVP-P Noise,
380µA Supply Current
LT1001 Precision Op Amp 25µV Max Offset, 0.3µVP-P Noise, High Output Drive
LT1468 Single 16-Bit Accurate Op Amp 900ns Settling, 90MHz GBW, 22V/μs Slew Rate, 75µV Max Offset
100pF
10µF
OUTIN +
–
LT1012
–
+
LTC2054
LTC2756
RCOM
RIN
ROFS REF
RFB
IOUT1
VOUT
IOUT2
GND
VDD
LDAC
CLR
VOSADJ
GEADJ
M-SPAN
S0
S1
S2
10k
1µF
15V
–15V
2756 TA02
0.1µF
12V
LT6655-5
10k
10k
14
23
25
4
19
20
21
22
17
CS/LD SDI SCK SRO
1211109
SPI BUS
1k
27, 28
26
2351
7
6, 8, 13,
15, 16, 24
10k 5V
–5V
–
+
LTC6240
5V
–5V –
+
LTC1360
15V
–15V
1k
10Ω
100pF
5pF
1k
4.02k
1µF
Figure 5. Composite Amplifier Provides Both 18-Bit Precision and Fast Settling
