®
Mobile
AMD-K6-2
Processor
Data Sheet
Publication # 21896 Rev: E Amendment/0
Issue Date: May 2000
Preliminary Information
®
Trademarks
AMD , t he AMD lo go , K6, 3D No w!, and combination s ther e of, an d Super7 are tr a demar ks, and AM D-K6 and RISC86
are registered trademarks of Advanced Micro Devices, Inc.
MMX is a trademark of Intel Corporation.
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Other product names used in this publication are for identification purposes only and may be trademarks of their
respective companies.
© 2000 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connectio n with Advanced Micro Devices , Inc.
(“AMD”) products. AMD mak es no r epresentations or w arr anties with respect to the accur acy
or completeness of the content s of this publication and reserves the right to make changes to
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express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted
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assumes no li ability whatsoe ver, and disc laims any expr ess or i mplied warr anty, r elating to its
products including, but not limited to, the implied warrant y of merchantability, fitness for a
particular purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use as components
in systems intended for surgical implant into the body, or in other applications intended to
suppor t or sust ain life, or in an y other applic ation in whic h the failur e of AM D’ s pr oduct co uld
create a situation where personal injury, death, or severe property or environmental damage
ma y occur. AMD reserv es the right to discontinue or make c hanges to its products at any time
without notice.
Preliminary Information
Contents iii
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xi
About This Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii
Part One
Mobile AMD-K6®-2 Processor 1
1 Mobile AMD-K 6®-2 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Super7™ Platform Initiative . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Super7 Platform Enhancements:. . . . . . . . . . . . . . . . . . . . . . . .5
2 Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Mobile AMD-K6®-2 Processor Microarchitecture
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Enhanced RISC86® Microarchitecture . . . . . . . . . . . . . . . . . . . 8
2.3 Cache, Instruction Prefetch, and Predecode Bits . . . . . . . . .11
Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Predecode Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.4 Instruction Fetch and Decode . . . . . . . . . . . . . . . . . . . . . . . . .13
Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Instruction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Centrali zed Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.6 Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Register X and Y Pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7 Branch-Prediction Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Branch History Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Branch Tar get Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Return Address Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Branch Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Logic Symbol Diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5 Mobile AMD-K6-2 Processor Operation . . . . . . . . . . . . . . . . . 37
5.1 Process Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
5.2 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
iv Contents
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Stop Grant Inquire State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
5.3 System Management Mode (SMM ) . . . . . . . . . . . . . . . . . . . . .42
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
SMM Operating Mode and Default Register Values . . . . . . .42
SMM State-Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
SMM Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Halt Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
I/O Tr ap Dword. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
I/O Tr ap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Exceptions, Interrupts, and D ebug in SMM . . . . . . . . . . . . . .51
6 Signal Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . 53
6.1 CLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 53
6.2 Clock Switching Characteristics for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3 Clock Switching Characteristics for 66-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.4 Valid Delay, Float, Setup, and Hold Timings . . . . . . . . . . . .55
6.5 Output Delay T imings for 100-M Hz Bus Operation . . . . . . .56
6.6 Input Setup and Hold Timings for 100- MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.7 Output Delay Timings for 66-MHz Bus Operation . . . . . . . .60
6.8 Input Setup and Hold Timings for 66- MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.9 RESET and Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . .64
7 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.1 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
7.2 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
7.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
7.4 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.5 Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Decoupling Recom mendations . . . . . . . . . . . . . . . . . . . . . . . . 77
Pin Connection Requirements. . . . . . . . . . . . . . . . . . . . . . . . .77
8 Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8.1 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . .79
Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Measuring Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 82
Contents v
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
9 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.1 321-Pin Staggered CPGA Package Specification . . . . . . . . .83
9.2 360-Pin Model 8 CBGA Package Specification . . . . . . . . . . .85
9.3 360-Pin CBGA Mechanical Specification . . . . . . . . . . . . . . . .87
10 Pin Description Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.1 360-Pin CBGA Pin Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . .89
10.2 321-Pin CPGA Pin Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . .91
10.3 Pin Designations by Functional Grouping . . . . . . . . . . . . . . . 93
11 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Part Two
Mobile AMD-K6-2-P Processor 97
12 Mobile AMD-K6-2-P Processor . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.1 Super7 Platform Initiative . . . . . . . . . . . . . . . . . . . . . . . . . .101
Super7 Platform Enhancements:. . . . . . . . . . . . . . . . . . . . . .101
13 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.1 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.2 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
13.4 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
13.5 Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Decoupling Recom mendations . . . . . . . . . . . . . . . . . . . . . . .110
Pin Connection Requirements. . . . . . . . . . . . . . . . . . . . . . . .111
14 Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
14.1 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . .113
Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Measuring Case Temperature . . . . . . . . . . . . . . . . . . . . . . . .115
15 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
vi Contents
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
List of Figures vii
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
List of Figures
Part One
Mobile AMD-K6®-2 Processor 1
Figure 1. Mobile AMD-K6®-2 Processor Block Diagram. . . . . . . . . . . . . . . 9
Figure 2. Cache Sector Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 3. The Instruction Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4. Mobile AMD-K6-2 Processor Decode Logic. . . . . . . . . . . . . . . .14
Figure 5. Mobile AMD-K6-2 Processor Scheduler. . . . . . . . . . . . . . . . . . .17
Figure 6. Registe r X and Y Functional Units . . . . . . . . . . . . . . . . . . . . . .19
Figure 7. Clock Control State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 8. SMM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 9. CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 10. Diagrams Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 11. Output Valid Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 12. Maximum Float Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . .68
Figure 13. Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 14. Reset and Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 15. TCK Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Figure 16. TRST# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 17. Test Signal Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 18. Suggested Component Placement . . . . . . . . . . . . . . . . . . . . . . .76
Figure 19. Thermal Model (CBGA Package) . . . . . . . . . . . . . . . . . . . . . . . .80
Figure 20. Power Consumption versus Thermal Resistance . . . . . . . . . . .80
Figure 21. Processor’s Heat Dissipation Path (CBGA Package) . . . . . . . .81
Figure 22. Measuring Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . .82
Figure 23. 321-Pin Staggered CPGA Package Specification . . . . . . . . . . . 84
Figure 24. 360-Pin CBGA Package Specification . . . . . . . . . . . . . . . . . . . .86
Figure 25. Mobile AMD-K6-2 Processor Ball-Side View (CBGA). . . . . . . .89
Figure 26. Mobile AMD-K6-2 Processor Top-Side View (CBGA). . . . . . . . 90
Figure 27. Mobile AMD-K6-2 Processor Bottom-Side View (CPGA) . . . . .91
Figure 28. Mobile AMD-K6-2 Processor Top-Side View (CPGA). . . . . . . . 92
viii List of Figures
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Part Two
Mobile AMD-K6-2-P Processor 97
Figure 29. Suggested Component Placement . . . . . . . . . . . . . . . . . . . . . .110
Figure 30. Thermal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Figure 31. Power Consumption versus Thermal Resistance . . . . . . . . . .114
Figure 32. Processor’s Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . 115
Figure 33. Measuring Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 116
List of Tables ix
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
List of Tables
Part One
Mobile AMD-K6®-2 Processor 1
Table 1. Execution Latency and Throughput of Execution Units . . . . .18
Table 2. Input Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 3. Output Pin Float Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 4. Input/Output Pin Float Conditions. . . . . . . . . . . . . . . . . . . . . . .35
Table 5. Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 6. Bus Cycle Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7. Special Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 8. Initial State of Registers in SMM . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 9. SMM State-Save Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 10. SMM Revision Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 11. I/O Trap Dword Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 12. I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 13. CLK Switching Characteristics for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 14. CLK Switching Characteristics for 66-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 15. Output Delay Timings for 100-MHz Bus Operation . . . . . . . . .56
Table 16. Input Setup and Hold Timings for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 17. Output Delay Timings for 66-MHz Bus Operatio n . . . . . . . . . .60
Table 18. Input Setup and Hold Timings for 66-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 19. RESET and Configuration Signals for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 20. RESET and Configuration Signals for 66-M Hz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 21. TCK Waveform and TRST# Timing at 25 MH z . . . . . . . . . . . . .66
Table 22. Test Signal Timing at 25 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 23. Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 24. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 25. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 26. Typical and Maximum Power Dissipation. . . . . . . . . . . . . . . . .74
Table 27. Package Thermal Specif ications. . . . . . . . . . . . . . . . . . . . . . . . . 79
xList of Tables
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Table 28. 321-Pin Staggered CPGA Package Specification . . . . . . . . . . . 83
Table 29. 360-Pin Model 8 CBG A Package Specification . . . . . . . . . . . . .85
Table 30. 360-Pin CBGA Mechanical Specification. . . . . . . . . . . . . . . . . .87
Table 31. Valid Ordering Part Number Combinations . . . . . . . . . . . . . . .95
Part Two
Mobile AMD-K6-2-P Processor 97
Table 32. Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Table 33. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Table 34. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Table 35. Power Dissipation (2.2 V Components) . . . . . . . . . . . . . . . . . .107
Table 36. Power Dissipation (2.0 V and 2.1 V Components) . . . . . . . . . 108
Table 37. Package Thermal Specif ications. . . . . . . . . . . . . . . . . . . . . . . . 113
Table 38. Valid Ordering Part Number Combinations . . . . . . . . . . . . . .117
Revision History xi
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
Revision History
Date Rev Description
Jan 1999 A Initial published release.
June 1999 B Added Part 2 which contains information specific to the Mobile AMD-K6®-2-P processor.
July 1999 C Added two VCC2 decoupling capacitors to the CBGA package on Figure 18, “Suggested Component
Placement,” on page 76 and to the CPGA package on Figure 29 on page 110.
Sept 1999 D Added specifications and OPNs for 433 MHz, 450 MHz, and 475 MHz frequencies in Chapter 13,
“Electrical Data”, Chapter 14, “ Thermal Design”, and Chapter 15, “Ordering Inform ation”.
May 2000 E Added specifications and OPN for 500 MHz frequency in Chapter 13, “Electrical Data”, Chapter 14,
“Thermal Design”, and Chapter 15, “Ordering Information”.
xii Revision History
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
About This Data Sheet xiii
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
About This Data Sheet
The Mobile AMD-K6®-2 Processor Data Sheet is a supplement to the AMD-K6®-2
Processor Data Sheet, order# 21850. When combin ed, the two data sheet s provide the
complete specification of the Mobile AMD-K6-2 and Mobile AMD-K6-2-P processors.
The Mobile AMD-K6®-2 Processor Data Sheet is divided into two pa rts. Part One
(chapters 1–11) contains information that pertains to the entire Mobile AMD-K6-2
processor family. Part Two (chapters 12–15) contains additional information spec ific
to the Mobil e AMD-K6-2-P Processor.
xiv About This Data Sheet
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
Part 1 Mobile AMD-K6®-2 Processor Data Sheet 1
Part One
Mobile AMD-K6 -2
Proc essor
The Mobile AMD-K6®-2 Processor Data Sheet is a supplement to the AMD-K6®-2
Processor Data Sheet, order# 21850. When combin ed, the two data sheet s provide the
complete specification of the Mobile AMD-K6-2 and Mobile AMD-K6-2-P processors.
The Mobile AMD-K6 ®-2 Processor Data Sheet is divided in to two parts. Part One
(chapters 1–11) contains information that pertains to the entire Mobile AMD-K6-2
processor family.
®
2Mobile AMD-K6®-2 Processor Data Sheet Part 1
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Chapter 1 Mobile AMD-K6®-2 Processor 3
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
1 Mobile AMD-K6®-2 Pr ocessor
■Advanced 6-Issue RISC86® Superscalar Microarchitecture
◆Ten parallel specialized execution units
◆Multiple sophisticated x86-to -RISC86 instruction decoders
◆Advanced two-level branch prediction
◆Speculative execution
◆Out-of-order ex ecution
◆Register renaming and data forwarding
◆Issues up to six RISC86 instructions per clock
■Large On-Chip Split 64-Kbyte Level-One (L1) Cache
◆32-Kbyte instruction cache with additional predecode cache
◆32-Kbyte writeback dual-por ted data cache
◆MESI protocol support
■High-Performance IEEE 754-Compatible and 854-Compatibl e Floa ting-Point Unit
■Superscalar MM X™ unit supports industry-standard MMX instructions
■3DNow!™ Technology for high-performance multimedia and 3D graphics
capabilities
■Compatible with Super7™ 10 0-M H z frontsi de bus or So ck e t 7 66-MHz notebook
design
■Cer amic Ball Grid Arr a y (CBGA) and Soc k et 7-Compatible Cer amic Pin Grid Arr a y
(CPGA) Pa ckage Options
■Industry-Standard System Management Mode (SMM)
■IEEE 1149.1 Boundary Scan
■x86 Binary Software Compatibility
■Low Voltage 0.25-Micron Process Technology
The Mobile AMD-K6®-2 proc essor is AMD’s second generation mob ile AMD-K6
processor delivering high performance for x86 notebook PC systems. The Mobile
AMD-K6-2 processor is a natural extension of the Mobile AMD-K6 processor and
incorporates the same leading-edge features, including the innovative and efficient
RISC86 mi croarchitecture , a larg e 64-Kbyt e level-one cache (32-Kbyte dual-ported
data cache, 32-Kbyte instruct ion c ache with predecode data ), a nd a powerful IEEE
754-compatible and 854-compatible floating-point execution unit. In addition, the
Mobile AMD-K6 -2 processor inc orporates a number of new features, including a
superscalar MMX unit, support for a 100-MHz frontside bus, and AMD’s innovative
3DNow! tec hnolog y f or high-perf ormance multimedia and 3D graphics operation.
4Mobile AMD-K6®-2 Processor Chapter 1
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Preliminary Information
The Mobile AMD-K6-2 processor includes several key features for the mobile market.
The processor is implemented using an AMD-developed, state-of-the-art low powe r
0.25-micron process technology. This process technology features a split-plane design
that allows the processor core to operate at a lower voltage while the I/O portion
oper ates at the industry-standar d 3.3V level. T he 0.25-micr on process technolog y with
the split-plane voltage desig n enables the Mobile AMD-K6-2 processor to deliver
excellent portable PC performance solutions while utilizing a lower processor core
v oltage, which r esults in low er pow er consumption and longer batter y life. In addition,
the Mobile AMD-K6-2 processor includes the complete industry-standard System
Management Mode (SMM), which is critical to system resource and power
management. The M obile AMD-K6-2 processor also features the i ndustry-standard
Stop-Clo ck (STPC LK# ) c ont rol circ uitry and the Ha lt i nstr uct ion , bot h required for
implementing the ACPI power management specification. Finally, the Mobile
AMD-K6-2 processor is offered in either a small, low-profile, lightweight,
thermally-efficient, 360-ball Ball Grid Array (CBGA) pack age that enab les thin and
light sys tem desi gns, or a standard Socket 7-compatibl e, 321-pin Ceramic Pi n Grid
Arr ay (CPGA) pac kage.
The Mobile AMD-K6-2 processor’s RISC86 microarchitecture is a decoupled
decode/execution superscalar design that implements state-of-the-art design
techniques to achieve leading-edge performance. Advanced design techniques
implemented in the Mobile AMD-K6-2 processor include multiple x86 instruction
decode, single-clock internal RISC operations, ten execution units that support
super scalar oper ation, out-of-order exec ution, data forwar ding, speculati v e execution,
and register renaming. In addition, the processor supports the industry’s most
advanced branch prediction logic by implementing an 8192-entry branch history
table, the industry’s only branch target cache, and a return address stack, which
combine to de li v er bet ter than a 95% pr e diction r ate . T hese design te c hniques ena ble
the Mobile AMD-K6-2 pr ocessor to issue, execute, and r etir e m ultiple x86 instructions
per clock, resulting in excellent scaleable performance.
AMD’s 3DNow! technolog y is an instruction set e x tension to x86, that includes 21 new
instructions to improve 3D graphics operations and other single precision floating-
point compute intensive operations. AMD has already shipped millions of AMD-K6-2
processors with 3DNow! technology for desktop PCs, revolutionizing the 3D
experience with up to four times the peak floating-point performance of prev ious
generation solutions. AMD is now bringing this advanced capability to notebook
computing, workin g in co njunction with advanced mobile 3D g raphic contro llers to
reach new levels of realism in mobile computing. With support f rom Microsoft ® and
the x86 software developer community, a new generation of visually compelling
applications is coming to market that support the 3DNow! technology.
The Mobile AMD-K6-2 processor remains pin compatible with existing Socket 7
notebook solu tions, however for maximum system performance, the processor works
optimally in newer Super7 designs that incorporate advanced features such as
support fo r the 100-MHz frontside bus and AGP graphics.
Chapter 1 Mobile AMD-K6®-2 Processor 5
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Preliminary Information
The Mobile AMD-K6-2 processo r has undergone ex tensive testing and is co mpatible
with Windows® 98, Windows NT® and other leadi ng operating s ystems. The Mo bile
AMD-K6-2 processor is also compatible with more than 60,000 software applications,
including the latest 3DNo w ! technology and MMX technology softw are. As the wor ld’s
second-largest supplier of processors for the Windows environment, AMD has
shipped more than 50 million Microsoft Windows compatible processors in the last
five ye ars.
The Mobile AMD-K6-2 processor is the next generation in a long line of Microsoft
Windows compatible processors from AMD. With its combination of state-of-the-art
features, leading-edge performance, high-performance multimedia engine, x86
compatibility, and low-cost infrastructure, the Mobile AMD-K6-2 processor is the
superior choice for portable personal computers.
1.1 Super7™ Platform Initiative
AMD and its industry partners are investing in the future of Socket 7 with the new
Super7 platform initia tive. The goal of the i nitiative is to maintain the competitive
vitality of the Socket 7 infrastructure through a series of planned enhancements,
including the development of an industry-standard 100-MHz processor bus proto col.
In addi tion to the 100-MHz processor bus protocol, the Super7 initiative includes the
introduction of chipsets that support the AGP specification, and support for a
backside L2 cache and front side L3 ca che.
Super7™ Platform Enhancements:
■100-MHz processor bu s—The Mobile AMD-K6-2 processor supports a 100-MHz, 800
Mbyte/second frontside bus to provide a high-speed interface to Super7
platform-based chipsets. The 100-MHz interface to the frontside Level 2 (L2)
cache and main system memory speeds up access to the frontside cache and main
memory by 50 percent over the 66-MHz Socket 7 interface—resulting in a
significant increase of 10% in overall system performance.
■Accelerated graphics port support—AGP improves the performance of mid-range
PCs that have small amounts of video memory on the graphics card. The
industry-standard AGP specification enables a 133-MHz graphics interface and
will scale to even higher levels of performance.
■Support for backside L2 and frontside L3 cache—The Super7 platform has the
‘headroom’ to support higher-performance AMD-K6 processors, with clock speeds
scaling to 500 MHz and beyond. Future versions of the AMD-K6 processor are
planned to feature a full-speed, on-chip backsi de 256-Kbyte L2 cache design ed to
deliver new levels of system performance to notebook PC systems. These versions
of the processor are also planned to support an optional 100-MHz frontside L3
cache for even higher-performance system configurat ions.
6Mobile AMD-K6®-2 Processor Chapter 1
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2 Internal Architecture
2.1 Introduction
T he Mobil e AMD-K6- 2 pr ocessor impl ements adv anced de sign
techniques known as the RISC86 microarchitecture. The RISC86
microarchitecture is a decoupled decode/execution design
appr oach that yiel ds superi or sixth-generation performance f or
x86-based softw ar e. T his c hapter describes the tec hniques used
and the functional elements of the RISC86 microarchitecture.
2.2 Mobile AMD-K6®-2 Processor Microarchitecture Ov erview
W hen discussing pr ocessor design, it is important to understand
the terms architecture, microarchitecture, and design
implementation. The term architecture refers to the instruction
set and features of a processor that are visible to software
programs running on the processor. The architecture
determines what software the processor can run. The
architecture of the Mobile AMD-K6-2 processor is the
industr y-standar d x86 instruction set.
The term microarchitecture refer s to the design tec hniques used
in the proce ssor to reach the targe t cost, performance, and
functionality g oals. The Mobile AMD -K6 family of processors
are based on a sophisticated RISC core known as the Enhanced
RISC86 microarchitecture. The Enhanced RISC86
microarchitecture is an advanced, second-order decoupled
decode/execution design approach that enables
industr y-leading perf ormance f or x86-based software.
The t erm design implementation refers to the actual logic and
cir cuit designs fr om whic h the pr ocessor is crea ted accor ding to
the microar chitectur e specifications.
8Internal Architecture Chapter 2
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Preliminary Information
Enhanced RISC86®
Microarchitecture The Enhanced RISC86 microarchitecture defines the
cha ra cteri sti cs of the AM D-K6 family. The innovative R ISC 86
microarchitecture approach implements the x86 instruction set
by internally translating x86 instructions into RISC86
oper ations. These RISC86 ope rations wer e specially designed to
include direct support for the x86 instruction set while
observing the RISC performance principles of fixed length
encoding, regularized instruction fields, and a large regist er
set. The Enhanced RISC86 microarchitecture used in the
Mobile AMD-K6-2 processor enables higher processor core
performance and promotes straightforward extensions, such as
those added in the current Mobile AMD-K6-2 processor and
those planned for the future. Instead of directly executing
complex x86 instructions, which have lengths of 1 to 15 bytes,
the Mobile AMD-K6-2 processor executes the simpler and
easier fixed-length RISC86 operations, while maintaining the
instruction coding efficiencies found in x86 pr o gr ams.
The M obile AMD-K6-2 proc essor contains parallel decoders , a
centraliz ed RISC86 operation scheduler, and ten execution
units that support sup erscalar operation—multiple decode,
execution, and r etirement—of x86 instructions. These elements
are packed into an aggressive and highly efficient six-stage
pipeline.
Mobile AMD-K6®-2 Processor Block Diagram. As shown in Figure 1 on
page 9, the high-performance, out-of-order execution engine of
the Mobile AMD-K6-2 processor is mated to a split level-one
64-Kbyte writeback cache with 32 Kbytes of instruction cache
and 32 Kbytes of data cache. The instruction cache feeds the
decoder s and, in turn, the decoders feed the sc heduler. T he ICU
issues and retires RISC86 operations contained in the
scheduler. The system bus int erface is an indu stry-s tandard
64-bit Super7 and Soc k et 7 demultiple xed bus.
The Mobile AMD-K6-2 processor combines the latest in
processor microarchitecture to provide the highest x86
performance for today’s personal computers. The Mobile
AMD-K6-2 processor offers true sixth-generation per formance
and x86 binar y softwar e compatibility.
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Figure 1. Mobile AMD-K6®-2 Processor Block Diagram
Decoders. Decoding of the x86 instructions begins when the
on-chip instruction cache is filled. Predecode logic determines
the length of an x86 instruction on a byte-by-byte basis. This
predecode information is stored, along with the x86
instructions, in the instruction cache, to be used later by the
decode rs. The decoders translat e on-the-fly, with no additional
latency, up to two x86 instructions per clock into RISC86
operations.
Note: In this chapter, “clock” refers to a processor clock.
Th e Mobile AMD-K6-2 processor categoriz es x86 instructions
into three types of decodes—short, long, and vector. The
decoders process eit he r two shor t, one long, or one vec tor
decode at a time. T he three types of decodes hav e the f ollowing
characteristics:
■Short decodes—x86 instructions less than or equal to seven
b ytes in length
■Long decodes—x86 instructions less than or equal to 11
b ytes in length
■Vector decodes—c omplex x 86 instruc tions
Store
Unit Branch
Unit
Store
Queue
Instruction
Control Unit
Scheduler
Buffer
(24 RISC86)
Six RISC86 ®
Operation Issue
Four RISC86
Decode
Out-of-Order
Execution Engine
32-KByte Level-One Dual-Port Data Cache 128-Entry DTLB
20-KB yte Predecode Cache 64-Entry ITLB
Multiple Instruction Decoders
x86 to RISC86
Branch Logic
(8192-Entry BH T)
(16-Entry B TC)
(16-Entry RAS )
16-Byte Fetch
Load
Unit
Predecode
Logic
Level-One Cache
Controller
FPU
32-KByte Level-One Instruction Cache
Register Y Functional Units
Integer/
Multimedia /3DNow!
100 MHz
Super7™
Bus
Interface
Register X Functi onal Units
Integer/
Multimedia/3DNow!
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Short and long decodes are processed completely within the
decoders. Vector decodes are started by the decoders and then
completed by fetched sequences from an on-chip ROM. After
decoding, the RISC86 oper ations are delivered to the sc heduler
f or dispatc hing to the e xecutions units.
Scheduler/Instruction Control Unit. The centralized scheduler or
buffer is managed by the Instruction Control Unit (ICU). The
ICU buffers and manage s up to 24 RISC 86 operations at a time .
T his equals fr om 6 to 12 x86 instructions. T his buffer size (24) is
perfectly matched to the processor’s six-stage RISC86 pipeline
and four RISC86-oper ations decode r ate. T he scheduler accepts
as many as four RISC86 operations at a time from the decoders
and retires up to four RISC86 operations per clock cycle. The
ICU is capable of simultaneously issuing up to six RISC86
operations at a time to the execution units. Th is consists of the
f ollowing types of oper ations:
■Memory load operation
■Memory stor e oper ation
■Complex integer, MMX or 3DNow! r egister oper ation
■Simple integer, MM X or 3DNo w! register oper at ion
■Floating-point r egister operation
■Br anch condition e v alua tion
Registers. When managing the 24 R ISC86 operations, the ICU
uses 69 physical registers contained within the RISC86
microarchitecture. 48 of the physical registers are located in a
general register file and are grouped as 24 committed or
architectural registers plus 24 rename registers. The 24
architectural regis ters co nsist of 16 scratch registers and 8
r egister s that corr espond to t he x86 gener al -purpose r e gister s—
EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI. There is an
analogous set of registers specifically for MMX and 3DNow !
operations. There are 9 MMX/3DNow! committed or
architectural registers plus 12 MMX/3DNow! rename registers.
The 9 architectural registers consist of one scratch register and
8 registers that correspond to the MMX registers (mm0–mm7).
For more detailed information, see the 3DNow!™ Tech nology
Manual, order# 21928.
Branch Logic. The Mobile AMD-K6-2 processor is de sign ed wit h
highly sophisticated dy namic branch logic consisting of the
following:
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■Br anch histor y/Prediction ta ble
■Branch target cache
■Return addr ess stack
T he Mobi le AMD-K6-2 processor impleme nts a tw o-le vel br anc h
prediction sc hem e based on an 8192-entry branch histor y table.
The branch history table stores prediction information that is
used for predicting conditional branches. Because the branch
history table does not store predicted t arget addresses, special
address ALUs calculate t arg et addresses o n-t he-fly during
instruction decode. The branch target cache augments
predicted branch performance by avoiding a one clock
cache-fetch penalty. This specializ ed target cache does this by
supplying the first 16 bytes of target instructions to the
decoders when branches are predict ed. The return addres s
stack is a unique device specifically designed for optimizing
CALL and RETURN pai rs. In summary, the Mobile AMD-K6-2
processor uses dynamic branch logic to minimize delays due to
the br anch instructions that ar e common in x86 softw ar e.
3DNow!™ Technology. AMD has taken a lead role in improving the
multimedia and 3D capa bilities of the x86 processor famil y with
the introduction of 3DNow! technol ogy, which uses a packed,
single-precision, floating-point data format and Single
Instruction Multipl e Data (SIMD) operati ons based on the
MMX tec hnolo g y model.
2.3 Cache, Instruction Prefetch, and Predecode Bits
The writeback level-one cache on the Mobile AMD-K6-2
processor is organized as a separate 32-Kbyte instruction cache
and a 32-Kby te data c ache with two-way set assoc iat ivity. The
cache line siz e is 32 bytes and lines are prefetched from main
memory usin g an effi cient pipeli ned bu rs t transaction. As the
instruction cache is filled, each instruction byte is analyzed for
instruction boundaries using predecoding logic. Predecoding
annotates inf orma tion (5 bits per byte) to eac h instruction byte
that lat er enables the de code rs t o effici ently decode multiple
instructions simultaneously.
Cache The processor cache design takes advantage of a sectored
organization (se e Figure 2 on page 12). Each sector co nsist s of
64 by tes configured as two 32-byte cache lines. Th e two cache
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Preliminary Information
lines of a sector share a common tag but have separate pairs of
MESI (Modified, Exclusive, Shared, Invalid) bits that track the
state of each cache line.
Two forms of cache misses and associated cach e fills can take
place—a tag-miss cache fill and a ta g-hit cache fill. In the case
of a tag-miss cache fill, the miss is due to a tag mismatch, in
which case the required cache line is filled from external
memory, and th e cache line within the sector that was not
required is marked as invalid. In the case of a tag-hit cache fill,
the address ma tches the t ag, but the requeste d cach e line is
marked as invalid. The required cache line is filled from
external memory, and the cache line within the sector that is
not r equir ed r emains in the same cac he state.
Prefetching The Mobile AMD-K6 -2 processor conditionally performs cache
prefe tch ing wh ich resul ts in th e fillin g of the required cache
line fir st, and a pr efetc h of the second cac he line making up the
other half of the sector. From the perspective of the external
bus, the two cache-line fills typically appear as two 32-byte
burst read cycles occurring back-to-back or, if allowed, as
pipelined c ycles.
The 3DNow! technology includes an instruction called
PREFETCH that allows a cache line to be prefetched into the
data cache. For more detailed information, see the 3DNow!™
Tec hnology Manual, order# 21928 .
Predecode Bits Decoding x86 instructions is particularly difficult because the
instructions are variable-length and can be from 1 to 15 bytes
long. Predecode logic supplies the five pre decode bits that are
associated with each instruction byte. The pre decode bits
indicate the number of bytes to the start of the next x86
instruction. The predecode bits are stored in an extended
instruction cache alongside each x86 instruction byte as shown
in Figure 2. The predecode bits are passed with the instruction
bytes to the decoders where they assist with parallel x86
instruction decoding.
Figure 2. Cache Sector Organization
Tag
Address Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
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2.4 Instruction Fetch and Decode
Instruction Fetch The processor can fetch up to 16 bytes per clock out of the
instruction cache or branch target cache. The fetched
inform ation is placed into a 16-byt e instruction buffer that
feeds directly into the dec oders ( see Figure 3) . Fet ching c an
occur along a single execution stream with up to seven
outstanding br anc hes tak en.
The instruction fetch logic is capable of retrieving any 16
contiguous bytes of information within a 32-byte boundary.
T her e is no additional penalty when the 16 b ytes of instructions
lie across a cache line boundary. Th e in struction bytes are
loaded into the instruction buffer as they are consumed by the
decoders. Although i nstructions can be consumed with byte
granularity, the instruction buffer is managed on a
memory-aligned word (two bytes) organization. The refore,
instructions are loaded and replaced with word granularity.
Wh en a control transfer occurs—such as a JMP instr uction—
the entir e instruction buffer is flushed and r eloaded with a ne w
set of 16 instruction b ytes.
Figure 3. The Instruction Buffer
16 Instruction Bytes
plus
16 Sets of Predecode Bits
Branch-Target Cache
16 x 16 Bytes
2:1
Instruction Buffer
16 Bytes
16 Bytes
Branch Target
Addres s Add e rs
Return Address Stack
16 x 16 Bytes
32-Kbyte Level-One
Instruction Cache
Fetch Unit
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Instruction Decode The Mobile AMD-K6-2 processor decode logic is designed to
decode multiple x86 instructions per clock (see Figure 4). The
decode logic accepts x86 instruct ion bytes and their predecode
bits from the instruction buffer, locates the actual in struc tion
boundaries, and generates RISC86 operations from these x86
instructions.
RISC86 operations are fixed-length internal instructions. Most
RISC86 oper ati ons e xecute in a sing le clock. RISC86 operations
are comb ined to perform every function of the x86 inst ruct ion
set. Some x86 instructions are decoded into as few as z ero
RISC86 operations—for instance a NOP—or one RISC86
operation—a register-to-register add. More complex x86
instructions ar e decoded into se v er al RISC86 oper at ions.
Figure 4. Mobile AMD-K6®-2 Processor Decode Logic
Instruction Buffer
4 RISC86 Operations
Long Decode r
Short Decoder #1
Short Decoder #2
Vector Address
Vector Decoder
RISC86® Sequencer
On-Chip ROM
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The Mobile AMD-K6-2 processor uses a combination of
decoders to convert x86 instructions into RISC86 operations.
The hardware consists of three sets of decoders—two parallel
short decoders, one long decoder, and one vector decoder. The
two parallel short decoders transl ate the most commonly-used
x86 instructions (moves, shifts, branches, ALU, FPU) and the
extensions to the x86 instruction set (including MMX and
3DNow! instructions) into z ero, one, or t wo RISC86 operations
each. The short decoders only operate on x86 instructions that
are up t o seven bytes long. In addition, they are designed to
decode up to two x86 instructions per clock. The
common ly-used x86 instructi ons that are greater than seve n
b ytes but not mor e than 11 b ytes long, and semi-commonl y-used
x86 instructions that are up to seven bytes long are handled by
the long decoder.
The long decoder only performs one decode per clock and
generates up t o four RISC86 operations. All other translations
(complex instructions, serializing conditions, interrupts and
exceptions, etc.) are handled by a combination of the vector
decoder and RISC86 operation sequences fetched from an
on-chip ROM. For complex operations, the vector decoder logic
provides the first set of RISC86 operations and a ve ctor ( initial
ROM address) to a sequence of further RISC86 operations. The
same types of RISC86 operations are fetched from the ROM as
those that ar e gener ated b y the har d w are decoder s.
Note: Although all three sets of decoders are simultaneously fed a
copy of the instruction buffer contents, only one of the three
types of decoders is used during any one decode clock.
The decoders or the on-chip RISC86 ROM always generate a
group of four RISC86 operations. F or decodes that cannot fill the
entire group with four RISC86 operations, RISC86 NOP
operations are placed in the empty locations of the grouping. F or
example, a long-decoded x86 instruction that converts to only
three RISC86 operations is padded with a single RISC86 NOP
operation an d then passed to the scheduler. Up to six groups or
24 RISC86 operations can be placed in the scheduler at a time.
All of the common, and a few of the uncommon, floating-point
instr uction s (also k now n as ESC instruc tions) a re ha rdwa re
deco ded as short deco des. This dec ode g enera tes a RI SC86
floating-point operation and, optionally, an associated
floating-point load or store operation. Floating-point or ESC
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Preliminary Information
instruction decode is onl y allow ed in the fir st short decoder, but
non-ESC instructions can be decoded simultaneously by the
second short decoder along with an ESC instruction decode in
the fir st short decode r.
All of the MMX and 3 DNow! instructions, with the exception of
the EMMS, FEMMS, and PREFETCH instructions, are
hardware decoded as short decodes. The MMX instruction
decode generates a RISC86 MMX operation and, optionally, an
associated MMX load or store operation. A 3DNow! instruction
decode generates a RISC86 3DNow! operation and, optionally,
an associated load or store operation. MMX and 3DNow!
instructions can be decoded in either or both of the short
decoders.
2.5 Centralized Scheduler
The scheduler is the he art of the Mobile AMD-K6-2 processor
(see Fi gure 5 on page 17). It contains the logic necessary to
manage out-of-order execution, data forwarding, register
renaming, simultaneous issue and retirement of multiple
RISC86 operations, and speculative execution. The scheduler’s
buffer can hold up to 24 RISC86 operations. This equates to a
maximum of 12 x86 instructions. The scheduler can issue
RISC86 o perations from any of the 2 4 loc atio ns in th e buffer.
When possible, the scheduler can simultaneously issue a RISC86
operation to any available execution unit (store, load, branch,
register X integer/multimedia, register Y integer/multimedia, or
floating-point). In total, the scheduler can issue up to six and
r etir e up to f our RISC86 oper ations per cloc k.
T he mai n ad vantage of the sc hedul er and its operation buf fer is
the ability to examine an x86 instruction window equal to 12
x86 instructions at one time. This advantage is due to the fact
that the scheduler operates on the RISC86 operations in
parallel and allows the Mobile AMD-K6-2 processor to perform
dynamic on-the-fly instruction code scheduling for optimized
exe cution. Although the s c heduler can iss ue RISC86 operations
for out-of-order execution, it always retires x86 instructions in
order.
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Figure 5. Mobile AMD-K6®-2 Processor Scheduler
2.6 Execution Units
The Mobile AMD-K6-2 processor contains ten parallel
execution units—store, load, integer X ALU, integer Y ALU,
MMX ALU (X), MMX ALU (Y), MMX/3DNow! multiplier,
3DNo w! ALU , floating-point, and branc h condition. Eac h unit is
independent and capable of handling the RISC86 operations.
Table 1 on page 18 details the execution units, functions
performed within these units, operation latency, and operation
throughput.
Th e store and load execution units are t wo-sta ge pipelined
designs. The store unit performs data writes and register
calculation for LEA/PUSH. Data memory and regi ster writes
from stores are available after one clock. Store operations are
held in a store queue prior to execution. From there, they
execute in order. The load unit performs data memory reads.
Data is a vailable fr om the loa d unit after tw o cloc ks.
RISC86 Oper ation Buffer
RISC86 Issue Buses
RISC86 # 0 RISC86 #1 RISC86 #2 RISC86 #3
Centralized RISC86®
Operati on Schedul e r
From Decod e Logi c
18 Internal Architecture Chapter 2
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
The Integer X execution unit can operate on all ALU
operations, mu ltiplies, divides (signed and unsigned), shifts,
and r otates.
T he Integer Y execution unit can operate on the basic wor d and
doubleword ALU operations—ADD, AND, CMP, OR, SUB,
XOR, zero-e xtend and sign-e xtend oper ands.
Register X and Y
Pipelines The functional units that execute MMX and 3DNow!
instructions share pipeline control with the I nteger X and
Integer Y units.
The register X and Y functional units are attached to the issue
bus f or the register X execution pipeline or the issue bus f or the
register Y execution pipeline or both. Each register pipeline
has dedicated resources that consist of an integer execution
unit and an MMX ALU execution unit, therefore allowing
superscalar operation on integer and MMX instructions. I n
addition, both the X and Y issue buses are connected to the
3DNow! ALU, the MMX/3DNow! multiplier and MMX shifter,
which allow s the a ppropriate RISC8 6 operat ion to be issued
thr ough either bus. Figure 6 on page 19 sho ws the details of the
X and Y r egister pipelines.
Table 1. Execution Latency and Throughput of Execution Units
F u nct i onal Uni t F un cti on Latency Throughput
Store LEA/PUS H, Address (Pipelined) 1 1
Memory Store (Pipelined) 1 1
Load Memory Loads (Pipelined) 2 1
Integer X Integer ALU 1 1
Integer Multiply 2–3 2–3
Integer Shift 1 1
Multimedia
(processes
MMX instructions)
MMX ALU 1 1
MMX Shifts, Packs, Unpack 1 1
MMX Multiply 2 1
Integer Y Basic ALU (16-bit and 32-bit operands) 1 1
Branch Resolves Branch Conditions 1 1
FPU FADD, FSUB, FMUL 2 2
3DNow! 3DNow! ALU 2 1
3DNow! Multiply 2 1
3DNow! Convert 2 1
Chapter 2 Internal Architecture 19
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Confidential - Advance
Figure 6. Register X and Y Functional Units
The branch condition unit is separate from the branch
prediction logic in that it resolves conditional branches such as
JCC and LOOP after the br anc h condition has been evaluated.
2.7 Branch-Prediction Logic
Sophisticated branch logic that can minimize or hide the impact
of changes in program flow is designed into the Mobil e
AMD-K6-2 processor. Branches in x86 code fit into two
categories—unconditional branches, which always change
program flow (that is, the branches are always taken) and
conditional branches, which ma y or may not divert progr am flow
(that is, the branches are taken or not-taken). When a conditional
branch is not taken, the processor simply continues decoding and
executing the next instructions in memory .
Typical applications have up to 10% of unconditional branches
and another 10% to 20% conditional branches. The Mobile
AMD-K6-2 processor branch logic has been designed to handle
MMX/
3DNow!
Multiplier
Integer X
ALU MMX
ALU MMX
Shifter 3DNow!
ALU MMX
ALU Integer Y
ALU
Scheduler
Buffer
(24 RISC86® Operations)
Issue Bus
for the
Register X
Execution
Pipeline
Issue Bus
for the
Register Y
Execution
Pipeline
20 Internal Architecture Chapter 2
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
this type of program behavior and its negative effects on
instruction execution, such as sta lls due to delayed instruction
fetching and the draining of the pr ocessor pipeline. The br anch
logic contains an 8192-entry branch history table, a 16-entry by
16-byte branch target cach e, a 16-entry return address stack,
and a br anc h execution unit.
Branch History Table The Mobile AMD-K6-2 processor handles unconditional
branches without any penalty by redirecting instruction
fetching to the target address of the unconditional branch.
However, conditional branches re quire the use of the dynamic
branch -pre diction mechanism built into the Mobile AM D-K6-2
processor. A two-level adaptive history algorithm is
implement ed in an 8192 -entry branch h ist ory tab le. This table
stores executed branch information, predicts individual
branches, and predict s the behavior of groups of branches. To
accommodate the large branch history table, the Mobile
AMD-K6-2 processor does not store predicted target addresses.
Instead, t he branch target addresses are ca lculated on-the-fly
using ALUs during the decode stage. The adders calculate all
possible target addresses before the instructions are fully
decoded and the pr ocessor chooses whic h ad dr esses ar e v alid.
Branch Target Cache To avoid a one clock cache-fetch penalty when a branch is
pr edicted take n, a built-in br anc h tar get cac he supplies the first
16 bytes of instructions directly to the instruction buffer
(assum ing th e target address hit s thi s cache). (See Fig ure 3 on
page 13.) The branch ta rget cache is organized as 16 entries of
16 bytes. In total, the branch prediction logic achieves branch
pr ediction r ates gr eater than 95%.
Return Address Stack The return address stack is a special device designed to
optimiz e CALL and RET pairs. Softwa re is typi cally compiled
with subroutines that are frequently called from various places
in a program. This is usually done to save space. Entry into the
subroutine occurs with the execution of a CALL instruction. At
that time, the processor pushes the address of the next
instruction in memory following the CALL instruction onto the
stack (allocated space in memory). When the processor
encounters a RET instruction (within or at the end of the
subrout ine), the branch logic pops the address from the stack
and begins fetching from that location. To avoid the latency of
main memory acc esses during CALL and RET op erati ons, the
r eturn addr ess stac k cac hes the pushed ad dr esses.
Chapter 2 Internal Architecture 21
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Confidential - Advance
Branch Execution
Unit The branch execution unit enables efficient speculative
execution. This unit gives the processor the ability to execute
instructions beyond conditional branches before knowing
whether the branch prediction was correct. The Mobile
AMD-K6-2 processor does not permanently update the x86
registers or memory locations until all speculatively executed
conditional br anch instructions ar e resolv ed. When a pr ediction
is incorrect, the processor backs out to the point of the
mispredicted branch instruction and restores all regist ers. The
Mobile AMD-K6-2 processor can support up to seven
outstanding br anc hes.
22 Internal Architecture Chapter 2
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Chapter 3 Logic Symbol Diagram 23
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
3 Logic Symbol Diagram
A20M#
A[31:3]
AP
ADS#
ADSC#
APCHK#
BE[7:0]#
AHOLD
BOFF#
BREQ
HLDA
HOLD
D/C#
EWBE#
LOCK#
M/IO#
NA#
SCYC
W/R#
CACHE#
KEN#
PCD
PWT
WB/WT#
Clock
Bus
Arbitration
CLK BF[2:0]
TCK TDI TDO TMS TRST#
BRDY#
BRDYC#
D[63:0]
DP[7:0]
PCHK#
EADS#
HIT#
HITM#
INV
FERR#
IGNNE#
FLUSH#
INIT
INTR
NMI
RESET
SMI#
SMIACT#
STPCLK#
JTAG Test
Data
and
Data
Parity
Inquire
Cycles
Floating-Point
Error Handling
External
Interrupts,
SMM, Reset and
Initialization
Address
and
Address
Parity
Cycle
Definition
and
Control
Cache
Control
Mobile AMD-K6®-2
Processor
Voltage Detection
VCC2DET VCC2H/L#
Note:
The voltage detection pins are only supported in the CPGA package. They are not supported in the CBGA package.
24 Logic Symbol Diagram Chapter 3
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Chapter 4 Signal Descriptions 25
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
4 Signal Descriptions
Signal
Name Pin Location
CBGA/CPGA Pin Attribute Name and Summary
A20M# V09/AK-08 Input Address Bit 20 Mask
A20M# is used to simulate the behavior of the 8086 when it is
running in Real mode. The assertion of A20M# causes the
processor to force bit 20 of the physical address to 0 prior to
accessing the cache or driving out a memory bus cycle. The
clearing of address bit 2 0 m aps addr esses that wr ap abo ve 1 Mb yte
to addresses below 1 Mbyte.
A[31:3] See “Pin
Designations
by F unctional
Grouping” on
page 93.
A31-A5: Bidirectional
A4-A3: Output Address Bus
A[31:3] contains the physical address for the current bus c ycle. The
processor drives addresses on A[31:3] during memory and I/O
cycles, and cycle definition information during special bus cycles.
The processor samples addresses on A[31:5] during inquire cycles.
ADS# P03/AJ-05 Output Address Strobe
The assertion of ADS# indicates the beginning of a new bus cycle.
The address bus and all cycle definition signals corresponding to
this bus cycle are driven valid off the same clock edge as ADS#.
ADSC# W07/AM-02 Output Address Strobe Copy
ADSC# has the identical function and timing as ADS#. In the event
ADS# becomes too heavily loaded due to a large fanout in a
system, ADSC# can be used to split the load across two outputs,
which improves timing.
AHOLD H19/V-04 Input Address Hold
AHOLD can be asserted by the system to initiate one or more
inquire c ycles. To allow the system to drive the address bus during
an inquire cycle, the processor floats A[31:3] and AP off the clock
edge on which AHOLD is sampled asserted. The data bus and all
other control and status signals remain under the control of the
processor and are not floated.
AP N02/AK-02 Bidirectional Address Parity
AP contains the even parity bit for cache line addresses driven and
sampled on A[31:5]. The term even parity means that the total
number of 1 bits on AP and A[31:5] is even. (A4 and A3 are not
used for the generation or checking of address parity because
these bits are not required to address a cache line.)
26 Signal Descriptions Chapter 4
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
APCHK# R03/AE-05 Output Address Parity Check
If the processor detects an address parity error during an inquire
cycle, APCHK# is asserted for one clock.
BE[7:0]# See “Pin
Designations
by F unctional
Grouping” on
page 93.
Output Byte Enables
BE[7:0]# are used by the processor to indicate the valid data by tes
during a write cycle and the requested data bytes during a read
cycle. The eight byte enables correspond to the eight bytes of the
data bus as follows:
The by te enables are also used to distinguish between special bus
cycles as defined in Table 7 on page 36.
BF[2:0] See “Pin
Designations
by F unctional
Grouping” on
page 93.
Inputs,
Internal Pullups Bus Frequency
BF[2:0] determine the internal operating frequency of the
processor. The frequency of the CLK input signal is multiplied
internally by a ratio determined by the state of these signals as
shown below:
BF[2:0] have weak internal pullups and default to the 3.5 ratio if left
unconnected.
Signal
Name Pin Location
CBGA/CPGA Pin Attribute Name and Summary
■BE7#: D[63:56]
■BE6#: D[55:48]
■BE5#: D[4 7:40]
■BE4#: D[39:32]
■BE3#: D[31:24]
■BE2#: D[2 3:16]
■BE1#: D[15:8]
■BE0#: D[7:0]
State of
BF[2:0] Inputs
100b
101b
111b
010b
000b
001b
011b
110b
Processor-Clock to
Bus-Clock Ratio
2.5x
3.0x
3.5x
4.0x
4.5x
5.0x
5.5x
6.0x
Chapter 4 Signal Descriptions 27
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
BOFF# J18/Z-04 Input Backoff
If BOF F# is sampled asserted, the processor unconditionally aborts
any cycles in progress and transitions to a bus hold state by floating
the following signals: A[31:3], ADS#, ADSC#, AP, BE[7:0]#,
CACHE#, D[63:0], D/C#, DP[7:0], LOCK#, M/IO#, PCD, PWT, SCYC,
and W/R#. These signals remain floated until BOFF# is sampled
negated. This allows an alternate bus master or the system to
control the bus.
BRDY# K03/X-04 Input,
Internal Pullup Burst Ready
BRDY# is asserted to the processor by system logic to indicate
either that the data bus is being driven with valid data during a
read cycle or that the data bus has been latched during a write
c ycle. B RDY# is also used to indic ate the completion of special bus
cycles.
BR DYC# M01/Y-03 Input,
Internal Pullup Burst Ready Copy
BR DYC# has the identical function as BRDY#. In the event BRDY#
becomes too heavily loaded due to a large fanout in a system,
BRDYC# can be used to reduce this loading, which improves
timing. In addition, BR DYC# is sampled when RE S ET is negated to
configure the drive strength of A[20:3], ADS#, HITM#, and W/R#.
BREQ W03/AJ-01 Output Bus Request
BREQ is asserted by the processor to request the bus in order to
complete an internally pending bus c ycle. The system logic can us e
BREQ to arbitrate among the bus participants.
CACHE# T03/U-03 Output Cacheable Access
For reads, CACHE# is asserted to indicate the cacheability of the
current bus cycle. For write c ycles, C AC HE# is asserted to indicate
the current bus cycle is a modified cache-line writeback.
CLK W10/AK-18 Input Clock
The CLK signal is the bus clock for the processor and is the
reference for all signal timings under normal operation.
D/C# W04/AK-04 Output Data/Code
The processor drives D/C# during a memory bus c ycle to indicate
whether it is addressing data or executable code. D/C# is also used
to define other bus cycles, including interrupt acknowledge and
special cycles.
Signal
Name Pin Location
CBGA/CPGA Pin Attribute Name and Summary
28 Signal Descriptions Chapter 4
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
D[63:0] See “Pin
Designations
by F unctional
Grouping” on
page 93.
Bidirectional Data Bus
D[63:0] represent the processor’s 64-bit data bus. Each of the eight
bytes of data that comprise this bus is qualified by a corresponding
byte enable.
DP[7:0] See “Pin
Designations
by F unctional
Grouping” on
page 93.
Bidirectional Data Parity
DP[7:0] are even parity bits for each valid byte of data—as defined
by BE[7:0]#—driven and sampled on the D[63:0] data bus. If the
processor detects bad parity on any valid byte of data during a
read cycle, PCHK# is asserted.
The eight data parity bits corr espond to the eight bytes of the data
bus as follows:
For systems that do not support data parity, DP[7:0] should be
connected to VCC3 through pullup resistors.
EADS# U11/AM-04 Input External Address Strobe
System logic asserts EADS# during a cache inquire cycle to indicate
that the address bus contains a valid address.
EWBE# U03/W-03 Input E xternal Write Buffer Empty
The system logic can negate EWBE# to the processor to indicate
that its external write buffers are full and that additional data
cannot be stored at this time. This causes the processor to delay the
following activ ities until EWBE# is sampled asserted:
■The commitment of write hit cycles to cache lines in the
modified state or exclusive state in the processor’s cache
■The decode and execution of an instruction that follows a
currently-executing serializing instruction
■The assertion or negation of SMIACT#
■The entering of the Halt state and the Stop Grant state
FERR# L03/Q-05 Output Floating-Point Error
The assertion of FERR# indicates the occurrence of an unmasked
floating-point exception resulting from the execution of a
floating-point instruction.
Signal
Name Pin Location
CBGA/CPGA Pin Attribute Name and Summary
■DP7: D[63:56]
■DP6: D[55:48]
■DP5: D[4 7:40]
■DP4: D[39:32]
■DP3: D[31:24]
■DP2: D[23:16]
■DP1: D[15:8]
■DP0: D[7:0]
Chapter 4 Signal Descriptions 29
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
FLUSH# U13/AN-07 Input Cache Flush
In response to sampling FLUSH# asserted, the processor writes
back any data cache lines that are in the modified state, invalidates
all lines in the instruction and data caches, and then executes a
flush acknowledge special cycle. In addition, FLUSH# is sampled
when RESET is negated to determine if the processor enters
Tr i-State Test mode.
HIT# V08/AK-06 Output Inquire Cycle Hit
The processor asserts H IT# during an inquire cy cle to indicate that
the cache line is valid within the processor’s internal instruction or
data cache (also known as a cache hit).
HITM# U10/AL-05 Output Inquire Cycle Hit To Modified Line
The processor asserts HITM# during an inquire cycle to indicate
that the cache line exists in the processor’s data cache in the
modified state. The processor performs a writeback cycle as a
result of this cache hit.
HLDA P02/AJ-03 Output Hold Acknowledge
When HOLD is sampled asserted, the processor completes the
current bus cycles, floats the processor bus, and asserts HLDA in an
acknowledgment that these events have been completed. The
following signals are floated when HLDA is asserted: A[31:3], ADS#,
ADSC#, AP, BE[7:0]#, CACHE#, D[63:0], D/C#, DP[7:0], LOCK#,
M/IO#, PCD, P WT, SCYC, and W/R#.
HOLD J07/AB-04 Input Bus Hold Request
The system logic can assert HOLD to gain control of the processor’s
bus. When HOLD is sampled asserted, the processor completes the
current bus cycles, floats the processor bus, and asserts HLDA in an
acknowledgment that these events have been completed.
IGNNE# V12/AA-35 Input Ignore Numeric Exception
IGNNE# is used by external logic to control the effect of an
unmasked floating-point exception. Under certain circumstances, if
IGNNE# is sampled asserted, the processor ignores the
floating-point exception.
Signal
Name Pin Location
CBGA/CPGA Pin Attribute Name and Summary
30 Signal Descriptions Chapter 4
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
INIT V15/AA-33 Input Initialization
The assertion of I N IT causes the processor to flush its pipelines, to
initialize most of its internal state, and to branch to address
FFFF_FFF0h—the same instruction execution starting point used
after R ES ET. Unlike R E SE T, the processor preserves the contents of
its caches, the floating-point state, the MMX state, model-specific
registers, the CD and NW bits of the CR0 register, and oth er specific
internal resources.
INTR V13/AD-34 Input Maskable Interrupt
INTR is the system’s maskable interrupt input to the processor.
When the processor samples and recognizes INTR asserted, the
processor executes a pair of interrupt ackno wledge bus cycles and
then jumps to the interrupt service routine specified by the
interrupt number that was returned during the interrupt
acknowledge sequence.
INV T02/U-05 Input Invalidation Request
During an inquire cycle, the state of INV determines whether an
addressed cache line that is found in the processor’s instruction or
data cache transitions to the invalid state or the shared state.
KEN# M02/W-05 Input Cache Enable
If KEN# is sampled asserted, it indicates that the address presented
by the processor is c acheable. Otherwise, a single-transfer c ycle is
executed and the processor does not cache the data. KEN# is
ignored during writebacks.
LOCK# P01/AH-04 Output Bus Lock
The processor asserts LOCK# during a sequence of bus cycles to
ensure that the cycles are completed without allowing other bus
masters to intervene.
M/IO# N01/T-04 Output Memory or I/O
The processor drives M/IO# during a bus cycle to indicate whether
it is addressing the memory or I/O space. M/IO# is used to define
other bus cycles, including interrupt acknowledge and special
cycles.
NA# T01/Y-05 Input Next Address
System logic asserts NA# to indicate to the processor that it is
ready to accept another address pipelined into the previous bus
cycle.
Signal
Name Pin Location
CBGA/CPGA Pin Attribute Name and Summary
Chapter 4 Signal Descriptions 31
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
NMI V14/AC-33 Input Non-Maskable Interrupt
When NMI is sampled asserted, the processor jumps to the
interrupt service routine defined by interrupt number 02h. Unlike
the INTR signal, software cannot mask the effect of NMI if it is
sampled asserted by the processor.
PCD U07/AG-05 Output Page Cache Disable
The processor drives PCD to indicate the operating system’s
specification of cacheability for the page being addressed. System
logic can use PCD to control external c aching.
PCHK# M03/AF-04 Output Parity Check
The processor asserts PCHK# during read cycles if it detects an
even parity error on one or more valid bytes of D[63:0] during a
read cycle.
PWT V07/AL-03 Output Page Wr itethrough
The processor drives PWT to indicate the operating system’s
specification of the writeback state or writethrough state for the
page being addressed. PW T, together with WB/W T#, specifies the
data cache-line state during cacheable read misses and write hits to
shared cache lines.
RESET H18/AK-20 Input Reset
When the processor samples RESET asserted, it immediately
flushes and initializes all internal resources and its internal state
including its pipelines and caches, the floating-point state, the MMX
state, and all registers, and then the processor jumps to address
FFFF_FFF0h to start instruction execution.
The signals BRDYC# and FLUSH# are sampled during the falling
transition of RESET to select the drive strength of selected output
signals and to invoke the Tri-State Test mode, respectively.
R SVD See “Pin
Designations
by F unctional
Grouping” on
page 93.
—Reserved
Reserved signals are a special class of pins on the CPGA package
that can be treated in one of the following ways:
■As no-connect (NC) pins, in which case these pins are left
unconnected
■As pins connected to the system logic as defined by the
industry-standard Super7 and Soc ket 7 interface
■Any combination of NC an d Socket 7 pins
Signal
Name Pin Location
CBGA/CPGA Pin Attribute Name and Summary
32 Signal Descriptions Chapter 4
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
SCYC W15/AL-17 Output Split Cycle
The processor asserts SCYC during misaligned, locked transfers on
the D[63:0] data bus.
SMI# U14/AB-34 Input,
Internal Pullup System Management Interrupt
The assertion of SMI# causes the processor to enter System
Management Mode (SMM). Upon recognizing SMI#, the processor
performs the following actions, in the order shown:
1. Flushes its instruction pipelines.
2. Completes all pending and in-progress bus cycles.
3. Acknowledges the interrupt by asserting SMIACT# after
sampling EWBE# asserted (if EWBE# is masked off, then
S MIACT# is not affected by EWBE#).
4. Saves the internal processor state in SMM memory.
5. Disa bl es interrupts.
6. Jumps to the entry point of the SMM service routine.
SMIACT# U01/AG-03 Output System Management Interrupt Active
The processor acknowledges the assertion of SMI# with the
assertion of SMIACT# to indicate that the processor has entered
System Management Mode (SMM).
STPCLK# K18/V-34 Input,
Internal Pullup Stop Clock
The assertion of STPCLK# causes the processor to enter the Stop
Grant state, during which the processor’s internal clock is stopped.
From the Stop Grant state, the processor can subsequently
transition to the Stop Clock state, in which the bus clock CLK is
stopped. Upon recognizing STPCLK#, the processor performs the
following actions, in the order show n:
1. Flushes its instruction pipelines.
2. Completes all pending and in-progress bus cycles.
3. Acknowledges the STPCLK# assertion by executing a Stop
Grant special bus c ycle (see Table 7 on page 36).
4. Stops its internal clock after BRDY# of the Stop Grant special
bus cycle is sampled asserted and after EWBE# is sampled
asserted (if EWBE# is masked off, then entry into the Stop
Grant state is not affected by EWBE#).
5. Enters the Stop Clock state if the system logic stops the bus
clock CLK (optional).
Signal
Name Pin Location
CBGA/CPGA Pin Attribute Name and Summary
Chapter 4 Signal Descriptions 33
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
TCK D18/M-34 Input,
Internal Pullup Test Clock
TCK is the clock for boundary-scan testing using the Test Access
Port (TAP).
TDI E17/N-35 Input,
Internal Pullup Test Data Input
TDI is the serial test data and instruction input for boundary-scan
testing using the Test Access Port (TAP).
TDO D19/N-33 Output Test Data Output
TDO is the se rial t est data and ins truction output for boundary-scan
testing using the Test Access Port (TAP).
TM S E18/P-34 Input,
Internal Pullup Test Mode Select
TMS specifies the test function and sequence of state changes for
boundary-scan testing using the Test Access Port (TAP).
TRST# E19/Q-33 Input,
Internal Pullup Test Reset
The assertion of TRST# initializes the Test Access Port (TAP) by
resetting its state machine to the Test-Logic-Reset state.
VCC2DET na/AL-01 Output VCC2 Detect
VCC2DET is tied to VSS (logic level 0) to indicate to the system logic
that it must supply the specified dual-voltage requirements to the
VCC2 and VCC3 pins.
VCC2H/L# na/AN-05 Output VCC2 High/Low
VCC2H/L# is tied to VSS (logic level 0) to indicate to the system
logic that it must supply the specified processor core voltage to the
VCC2 pins.
W/R# W05/AM-06 Output Write/Read
The processor drives W/R# to indicate whether it is performing a
write or a read cycle on the bus. In addition, W/R# is used to define
other bus cycles, including interrupt acknowledge and special
cycles.
WB/WT# N03/AA-05 Input Writeback or Writethrough
WB/WT#, together with PWT, specifies the data cache-line state
during cacheable read misses and write hits to shared cache lines.
Signal
Name Pin Location
CBGA/CPGA Pin Attribute Name and Summary
34 Signal Descriptions Chapter 4
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Table 2. Input Pin Types
Name Type Note Name Type Note
A20M# Asynchronous Note 1 IGNNE# Asynchronous Note 1
AHOLD Synchronous INIT Asynchronous Note 2
BF[2:0] Synchronous Note 4 INTR Asynchronous Note 1
BOFF# Synchronous INV Synchronous
BRDY# Synchronous KEN# Synchronous
BRDYC# Synchronous Note 7 NA# Synchronous
CLK Clock NMI Asynchronous Note 2
EADS# S yn chr onous RESET Asynchronous Note 5, 6
EWB E# Synchronous SMI# Asynchronous Note 2
FLUSH# Asynchronous Note 2, 3 STPCLK# Asynchronous Note 1
HOLD Synchronous WB/WT# Synchronous
Notes:
1 . These level-sensitive signals can be asserted synchronously or asynchronously . To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously . To be sampled on a specific clock edge, setup and
hold times must be met. If ass erted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
3. FLUSH# is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be
sampled on a specific c lock edge, setup a nd hold times must be met the clock edge befo re the clock edge on which R ES ET is
sampled negated. If asser ted async hronously, FLUS H# must meet a mi nimum setu p and hol d time of two clocks relative t o the
negation of RESET.
4. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1 .0 ms and a minimum hold
time of two clocks relative to the negation of RESET.
5. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1 .0 ms after CLK and VCC reach
specification before it is negated.
6. During a warm reset, while C LK an d VCC are within their specification, R ESET must remain asser ted for a minimum of 15 clocks
prior to its negation.
7. BRD Y C # is also sampled during the falling transition of RESET. If RESET is driven synchronously, BRD Y C# must meet the specified
hold time relative to the negation of RES ET. If asser ted asynchr onou sly, B RDYC# must meet a minimum setup and ho ld time of
two clocks relative to the negation of RESET.
Chapter 4 Signal Descriptions 35
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Preliminary Information
Table 3. Output Pin Float Conditions
Name Floated At: (Note 1) Note Name Floated At: (Note 1) Note
A[4:3] HLDA, AHOLD, BOFF# Note 2,3 HLDA Always Driven
ADS# HLDA, BOFF# Note 2 LOCK# HLDA, BOFF# Note 2
ADSC# HLDA, BOFF# Note 2 M/IO# HLDA, BOFF# Note 2
APCHK# Always Driven PCD HLDA, BOFF# Note 2
BE[7:0]# HLDA, BOFF# Note 2 PCHK# Always Driven
BREQ Always Driven PWT HLDA, BOFF# Note 2
CACHE# HLDA, BOFF# Note 2 SCYC HLDA, BOFF# Note 2
D/C# HLDA, BOFF# Note 2 SMIACT# Always Driven
FERR# Always Driven VCC2DET Always Driven
HIT# Always Driven VCC2H/L# Always Driven
HITM# Always Driven W/R# HLDA, BOFF# Note 2
Notes:
1. All outputs except VCC2DET, VCC2H/L#, and TDO float during Tri-State Test mode.
2. Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that HLDA is asserted.
3. Floated off the clock edge that AHOLD is sampled asserted.
Table 4. Input/Output Pin Float Conditions
Name Floated At: (Note 1) Note
A[31:5] HLDA, AHOLD, BOFF# Note 2,3
AP HLDA, AHOLD, BOFF# Note 2,3
D[63:0] HLDA, BOFF# Note 2
DP[7:0] HLDA, BOFF# Note 2
Notes:
1. All outputs except VCC2DET and TDO float during Tri-State Test mode.
2. Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that HLDA is asserted.
3. Floated off the clock edge that AHOLD is sampled asserted.
Table 5. Test Pins
Name Type Note
TCK Clock
TDI Input Sampled on the rising edge of TCK
TDO Output Driven on the falling edge of TCK
TMS Input Sampled on the rising edge of TCK
TRST# Input Asynchronous (Independent of TCK)
36 Signal Descriptions Chapter 4
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Table 6. Bus Cycle Definition
Bus Cycle Initiated Generated by CPU Generated
by System Logic
M/IO# D/C# W/R# CACHE# KEN#
Code Read, Instruction Cache Line Fill 1 0 0 0 0
Code Read, Noncacheable 1 0 0 1 x
Code Read, Noncacheable 1 0 0 x 1
Encoding for Special Cycle 0011 x
Interrupt Acknowledge 0 0 0 1 x
I/O Read 0 1 0 1 x
I/O Write 0 1 1 1 x
Memory Read, Data Cache Line Fill 1 1 0 0 0
Memory Read, Noncacheable 1 1 0 1 x
Memory Read, Noncacheable 1 1 0 x 1
Memory Write, Data Cache Writeback 1 1 1 0 x
Memory Write, Noncacheable 1 1 1 1 x
Note:
x means “don’t care”
Table 7. Special Cycles
Special Cycle
A4
BE7#
BE6#
BE5#
BE4#
BE3#
BE2#
BE1#
BE0#
M/IO#
D/C#
W/R#
CACHE#
KEN#
Stop Grant 111111011 0 01 1 x
Flush Acknowledge
(FLUSH# sampled
asserted) 011101111 0 01 1 x
Writeback (WBINVD
instruction) 011110111 0 01 1 x
Halt 011111011 0 01 1 x
Flush (INVD, WBINVD
instruction) 011111101 0 01 1 x
Shutdown 011111110 0 01 1 x
Note:
x means “don’t care”
Chapter 5 Mobile AMD-K6®-2 Processor Operation 37
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Preliminary Information
5 Mobile AMD-K6®-2 Processor Operation
5.1 Process Technology
The Mobile AMD-K6-2 processor is implemented using an
advanced CMOS process technology that utiliz es a split core
and I/O v oltage suppl y, whic h allo ws the cor e of t he pr ocessor to
operate at a low voltage while the I/O portion operates at the
industry-standard 3.3 volts. This technology enables high
perfor manc e while reducing power co nsump tion by operating
the cor e at a lo w voltage and limiting pow er requir ements to the
acceptable le v els f or toda y’s mobile PCs.
5.2 Clock Control
The Mobi le AMD-K6-2 processor sup po rts five mode s of clock
control. The processor can transition between these mode s to
maximiz e performance, to minimize power dissipation, or to
provide a balance between performance and power. (See
“Power Dissipation” on page 74 for the maximum power
dissipation of the Mobile AMD-K6-2 within the normal and
r educed-pow er states.)
T he five clock-contr ol states supported ar e as f ollo ws:
■Normal State: The processor is running in Real Mode,
V irtual-8086 Mode, Pr otected Mode, or System Management
Mode (SMM). In this state, all clocks are running—
including the external bus clock CLK and the internal
processor clock—and the full features and functions of the
pr ocessor ar e av ailabl e.
■Halt State: This low-power state is entered following the
successful execution of the HLT instruction. During this
state, the internal pr ocessor clock is stopped.
■Stop Grant State: This low-power state is entered following
the recognition of the assertion of the STPCLK# signal.
During this state, the internal processor clock is stopped.
■Stop Grant Inquire Stat e: T his state is ent er ed fr om the Halt
state and the Stop Grant state as the result of a
system-initiated inquir e c ycle.
■Stop Clock State: This low-power state is entered from the
Stop Gr ant s tate when the C LK signal is stopped.
38 Mobile AMD-K6®-2 Processor Operation Chapter 5
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Preliminary Information
The following sections describe each of the fou r low-power
states. Figure 7 on page 41 illustrates the clock control state
transitions.
Halt State Enter Halt State. During the execution of the HLT instruction, the
Mobile AMD-K6-2 pr ocessor executes a Halt special cycle. After
BRDY# is sampled asserted during this cycle, and then EWBE#
is also sampled asserted (if not masked off), the processor
enters the Halt state in which the processor disables most of its
internal clock distribution. In order to support the following
oper ations, the internal phase-loc k loop (PLL) continues to run,
and so me intern al r eso ur ces are still cloc ked in the Halt s tate:
■Inquire Cycles: The processor continues to sample AHOLD,
BOFF#, and HOLD in order to support inquire cycles that
ar e initiated b y the system logic. The pr ocessor transitions to
the Stop Grant Inquire state during the inquire cycle. After
returning to the Halt state following the inquire cycle, the
pr ocessor does not e xecute another Halt speci al c ycle.
■Flush Cycles: T he pr ocessor contin ues to sample FLUSH#. If
FLUSH# is sampled asserted, the processor performs the
flush operation in the same manner as it is perf ormed in the
Normal state. Upon completing the flush operation, the
processor executes the Halt special cycle which indicates
the processor is in the Halt state.
■Time Stamp Counter (TSC): The TSC continues to count in
the Halt state.
■Signal Sampling: The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
After e ntering the Halt state, all si gnals dri v en b y the pr ocessor
retain their state as they existed following the completion of
the Halt special cycle.
Exit Halt State. The Mobile AMD-K6-2 processor remains in the
Halt state until it samples INIT, INTR (if interrupts are
ena bled), NM I, RESET, or SMI# asserted. I f an y of these signa ls
is sampled asser ted , the processor returns to the Norma l state
and performs th e corresponding ope rat ion. Al l of the no rmal
r equir ements f or r ecognition of these input signals appl y within
the Hal t state.
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Preliminary Information
Stop Grant State Enter Stop Grant State. After recognizing the assertion of
STPCLK#, the Mobile AMD-K6-2 processor flushes its
instruction pipelines, completes all pending and in-progress
bus cycles, and acknowledges the STPCLK# assertion by
executing a Sto p Gra nt special bus cycle. Af ter BRDY# is
sampled asserted during this cycl e, and after EWBE# is also
sampled asserted (if not ma sked off), the processor enters the
Stop Gra nt st ate. The Stop Grant st ate is like the Halt sta te in
that the processor disables most of its internal clock
distribution in the Stop Grant state. In order to su pport the
foll owing operations, the internal PLL still runs, and some
internal resour ces are still cloc ked in the Stop Gr ant s tate:
■Inquire cycles: The processor transitions to the Stop Grant
Inquire state during an inq uire cy cle. After returni ng to the
Stop Grant state following the inquire cycle, the processor
does not e xecute an other Stop Grant special c ycl e.
■Time Stamp Counter (TSC): The TSC continues to count in
the Stop Gr ant state.
■Signal Sampling: The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
FLUSH# is not reco gnized in the Stop Gr ant state (unlik e while
in the Ha lt sta te).
Upon entering the Stop Grant state, all signals driven by the
processor retain their state as they existed following the
completion of the Stop Grant special cycle.
Exit Stop Grant State. The Mobile AMD-K6-2 processor remains in
the Stop Grant state until it samples STPCLK# negated or
RESET asserted. If STPCLK# is sampled negated, the processor
returns to the Normal state in less than 10 bus clock (CLK)
periods. After the transition to the Normal state, the processor
resumes execution at the instruction boundary on which
STPCLK# w as initiall y r ecognized.
If STPCLK# is recognized as negated in the Stop Grant state
and subsequently sampled asserted pr ior to returning to the
Normal sta te, a minimum of one instruction i s executed prior to
r e-entering the Stop Gr ant state.
If INIT, INTR (if interrupts are enabled), FLUSH#, NMI, or
SMI# are sampled asserted in the Stop Grant state, the
processor latches the edge-s ensi tive signals (INIT, FLUSH#,
40 Mobile AMD-K6®-2 Processor Operation Chapter 5
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Preliminary Information
NMI, and SMI#), but otherwise does not exit the Stop Grant
state to ser vice the interrupt. W hen the pr ocessor r eturns to the
Normal state due to sampling STPCLK# negated, any pending
interrupts are recognized after returning to the Normal state.
To ensure their recognition, all of the normal requirements for
these input signals apply within the Stop Gr ant state.
If RESE T is sample d asserted in t he Stop Grant state, t he
proces sor immediately returns to the Normal state and the
r eset pr ocess begins.
Stop Grant Inquire
State Enter Stop Grant Inquire State. The Stop Grant Inquire state is
entered from the Stop Grant state or the Halt state when
EADS# is sampled asserted during an inquire c ycle initiated b y
the system logic. The Mobile AMD-K6-2 processor responds to
an inquire cycle in the same manner as in the Normal state by
driving HIT# and HITM#. If the inquire cycle hits a modified
data cache line, the pr ocessor perf orms a write bac k cycle.
Exit Stop Grant Inquire State. Following the completion of any
writeback, the pro cessor returns to the state from w hich it
enter ed the Stop Gr ant Inquire state.
Stop Clock State Enter Stop Clock State. If the CLK signal is stopped while the
Mobile AMD-K6-2 processor is in the Stop Grant state, the
processor enters the Stop Clock state. Because all internal
clocks and the PLL are not running in the Stop Clock state, the
Stop Clock state represents the minimum-power state of all
clock control states. The CLK signal must be held Low while it
is stopped.
T he Stop Cloc k st ate cannot be ente r ed fr om the Halt state .
INTR is the only input signal that is allowed to change states
while the pr o cessor is in the Stop Cloc k s tate. How e ver, INTR is
not sampled until the pr oce ssor r eturns to the Stop Grant state.
All other input signals must remain unchanged in the Stop
Cloc k state.
Exit Stop Clock State. The Mobile AMD-K6-2 processor returns to
the Stop Grant state from the Stop Clock state afte r the CLK
signal is started and the internal PLL has stabilized. PLL
stabilization is achieved after the CLK signal has been running
within its specification f or a minimum of 1.0 ms.
Chapter 5 Mobile AMD-K6®-2 Processor Operation 41
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Preliminary Information
T he frequency of CLK wh en exiti ng the Stop Clock state can be
different than the frequency of CLK wh en entering the Stop
Clock state.
The st ate of the BF[2:0] signals when exiting the Stop Clock
state is ignore d because the BF[2: 0] signals are only sampled
during the falling transition of RESET.
Figure 7. Clock Control State Transitions
EADS# Asserted EADS# Asserted
HLT Instruction
Stop Grant
State
Normal Mode
– Real
– Virtual-8 086
– Protected
– SMM
Halt
State
Stop Clock
State
RESET, SMI#, INIT,
or I NTR Asserted
Stop Grant
Inquire
State
STPCLK# Asserted
STPCLK# Negat ed,
or RESET Asserted
CLK
Started CLK
Stopped
Writeback
Completed
Writeback
Completed
42 Mobile AMD-K6®-2 Processor Operation Chapter 5
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Preliminary Information
5.3 System Management Mode (SMM)
Overview SMM is an alternate oper ating mode enter ed b y wa y of a system
management interrupt (SMI) and handled by an interrupt
service routine. SMM is designed for system control activities
such as power management. These activities appear
transparent to conventional operating systems like DOS and
Windows. SMM is primarily targeted for use by the Basic Input
Output System (BIOS) and specialized low-level device drivers.
The c ode and data for SMM are stored in the SMM memory
ar ea , whic h is isolated fr om main me mor y.
T he processor enters SMM by the system logic’s assertion of the
SMI# interrupt and the processor’s acknowledgment by the
assertion of SMIACT#. At this point the processor sa ves its state
into the SMM mem ory stat e-save area and jumps to the SMM
service routine. The processor returns from SMM when it
executes the RSM ( re sum e) instruc tion from within the SMM
service routine. Subsequently, the processor restores its state
from the SMM save area, negates SMIACT#, and resumes
execution with the instruction following the point wh ere it
enter ed SMM.
The following sections summariz e the SMM state-save area,
entry into and exit f rom SMM, exceptions and interrupts in
SMM, memor y allocation and addr essing in SMM, and the SMI#
and SMIACT# signa ls.
SMM Operating
Mode and Default
Register Values
The software environment within SMM has the following
characteristics:
■Addressing and operation in Real mode
■4-Gb yte segment l imits
■Default 16-bit operand, address, and stack sizes, although
instruction pr efixes can o v erride these def aults
■Control transfers that do not override the default operand
size truncate the EIP to 16 bits
■Far jumps or calls canno t transfer c ontrol to a se gment with
a base address requiring more than 20 bits, as in Real mode
segment-base ad dr es sing
■A20M# i s masked
■Interrupt v ector s use the Real-mode interrupt vector ta ble
■T he IF flag in EFLAGS is cleared (INTR not r eco gnized)
Chapter 5 Mobile AMD-K6®-2 Processor Operation 43
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Preliminary Information
■The TF flag in EFLAGS is cleared
■T he NMI and INIT interrupts are disa bled
■De bug r egister DR7 is clear ed (de bug tr aps disabled)
Figure 8 show s the default map o f the SMM mem ory area . It
consists of a 64-Kbyte area, between 0003_0000h and
0003_FFFFh, of which the top 32 Kbytes (0003_8000h to
0003_FFFFh) must be populated with RAM. The default
code-segment (CS) base address for the area—called the SMM
base address—is at 0003_0000h. The top 512 bytes
(0003_FE00h to 0003_FFFFh) contain a fill-down SMM
state-save area. The default entry point for the SMM service
r outine is 0003_8000h.
Figure 8. SMM Memory
SMM
State-Save
Area
SMM Base Address (CS)
Service Routine Entry Point
Fill Down
SMM
Service Routine
32-Kbyte
Minimum RAM
0003_8000h
0003_FE00h
0003_FFFFh
0003_0000h
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Preliminary Information
Ta ble 8 sho w s the initi al state of register s whe n entering SM M.
SMM State-Save Area When the processor acknowledges an SMI# interrupt by
asserting SMIACT#, it saves its state in a 512-byte SMM
state-save area shown in Table 9. The save begins at the top of
the SMM memory area (SMM base address + FFFFh) and fills
do wn to SMM base addr ess + FE00h.
Table 9 shows the offsets in the SMM state-save area relative to
the SMM base address. The SMM service routine can alter any
of the r e ad/write v alues in the state- sa ve ar ea.
Table 8. Initial State of Registers in SMM
Registers SMM Initial State
General Purpose Registers unmodified
EFLAGs 0000_0002h
CR0 PE, EM, TS, and PG are cleared (bits 0, 2, 3,
and 31). The other bits are unmodified.
DR7 0000_0400h
GDTR, LDTR, IDTR, TSSR, DR6 unmodified
EIP 0000_8000h
CS 0003_0000h
DS, ES, FS, GS, SS 0000_0000h
Table 9. SMM State-Save Area Map
Address Offset Contents Saved
FFFCh CR0
FFF8h CR3
FFF4h EFLAGS
FFF0h EIP
FFECh EDI
FFE8h ESI
FFE4h EBP
FFE0h ESP
FFDCh EBX
FFD8h EDX
Notes:
— No data dump at that address
* Only contains information if SMI# is asserted during a valid I/O bus cycle.
Chapter 5 Mobile AMD-K6®-2 Processor Operation 45
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Preliminary Information
FFD4h ECX
FFD0h EAX
FFCCh DR6
FFC8h DR7
FFC4h TR
FFC0h LDTR Base
FFBCh GS
FFB8h FS
FFB4h DS
FFB0h SS
FFACh CS
FFA8h ES
FFA4h I/O Trap Dword
FFA0h —
FF9Ch I/O Trap EIP*
FF98h —
FF94h —
FF90h IDT Base
FF8Ch IDT Limit
FF88h GDT Base
FF84h G DT Limit
FF80h TSS Attr
FF7Ch TSS Base
FF78h TSS Limit
FF74h —
FF70h LDT High
FF6Ch LDT Low
FF68h GS Attr
FF64h GS Base
FF60h GS Limit
FF5Ch F S Attr
Table 9. SMM State-Save Area Map (continued)
Address Offset Contents Saved
Notes:
— No data dump at that address
* Only contains information if SMI# is asserted during a valid I/O bus cycle.
46 Mobile AMD-K6®-2 Processor Operation Chapter 5
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Preliminary Information
FF58h FS Base
FF54h FS Limit
FF50h DS Attr
FF4Ch DS Base
FF48h DS Limit
FF44h SS Attr
FF40h SS Base
FF3Ch SS Limit
FF38h CS Attr
FF34h CS Base
FF30h C S Limit
FF2Ch ES Attr
FF28h ES Base
FF24h ES Limit
FF20h —
FF1Ch —
FF18h —
FF14h CR2
FF10h CR4
FF0Ch I/O restart ESI*
FF08h I/O restart ECX*
FF04h I/O restart EDI*
FF02h HALT Restart Slot
FF00h I/O Trap Restart Slot
FEFCh SMM RevID
FEF8h SMM BASE
FEF7h–FE00h —
Table 9. SMM State-Save Area Map (continued)
Address Offset Contents Saved
Notes:
— No data dump at that address
* Only contains information if SMI# is asserted during a valid I/O bus cycle.
Chapter 5 Mobile AMD-K6®-2 Processor Operation 47
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Preliminary Information
SMM Revision
Identifier The SMM revision identifier at offset FEFCh in the SMM
state-save ar ea specifies the v er sion of SMM and the extensions
that are a v aila bl e on the processor. T he SMM r e visio n identifier
fields ar e as follo ws:
■Bits 31–18—Reserved
■Bit 17—SMM base address r elocation (1 = ena bled)
■Bit 16—I/O tr ap r e start (1 = ena bled)
■Bits 15–0—SMM revision level for the Mobile AMD-K6-2
pr ocessor = 0002h
Table 10 shows the format of the SMM Revision Identifier.
SMM Base Address During RESET, the processor sets the base address of the
code-segment (CS) for the SMM memory area—the SMM base
address—to its default, 0003_0000h. Th e SMM base address at
offset FEF8h in the SMM state-sa v e area can be c hanged by the
SMM service routine to any address that is aligned to a
32-Kbyte boundary. (Locations not aligned to a 32-Kbyte
boundary cause the pr ocessor to enter the Shutdo wn state when
executing the RSM instruction.)
In some operating environments it may be desirable to relocate
the 64-Kbyte SMM mem or y area to a high memor y ar ea in or der
to pr o vide more low me mor y f or leg ac y softw ar e. During system
initialization, the base of the 64-Kbyt e SMM mem ory area is
relocated by the BIOS. To rel ocate the SMM base address, the
system ente rs the SMM handler at the default address. This
handler changes the SMM base address location in the SMM
state-save area, copies the SMM handler to the new location,
and exits SMM.
The next time SMM is entered, the processor saves its state at
the new base address. This new address is used for every SMM
entr y until the SMM base addr ess in the SMM state-save ar ea is
c hanged or a har dwar e r eset occurs.
Table 10. SMM Revision Identifier
31–18 17 16 15–0
Reserved SMM Base Relocation I/O Trap Extension SMM Revision Level
0 1 1 0002h
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Halt Restart Slot During entry into SMM, the halt restart s lot at offse t FF02h in
the SMM state-sav e ar ea indicates if SMM w as enter ed from the
Halt state. Before returning from SMM, the halt restart slot
(offset FF02h) can be written to by the SMM service routine to
specify whether the return from SMM takes the processor back
to the Halt state or to the next instruction after the HLT
instruction.
Upon entry into SMM, the ha lt r estart s lot is defined a s f ollo ws:
■Bits 15–1—Reserved
■Bit 0—Point of entr y to SMM:
1 = entered from Halt state
0 = not entered from Halt state
After entry into the SMI handler and before re turning from
SMM, the halt restart slot can be written using the following
definition:
■Bits 15–1—Reserved
■Bit 0—Point of r eturn when exiting from SMM:
1 = return to Halt state
0 = return to next instruction after the HLT instruction
If the return from SMM takes the processor back to the Halt
state, the HLT instruction is not re-executed, but the Halt
special bus c ycle is dri ven on the bus after the r eturn.
I/O Trap Dword If the assertion of SMI# is r ecognized during the execution of an
I/O instruction, the I/O trap dword at offset FFA4h in the SMM
state-save area contains information about the instruction. The
fields of t he I/O tr ap d w o r d ar e confi gur ed as f oll o ws:
■Bits 31–16—I/O por t addr e ss
■Bits 15–4—Reserved
■Bit 3—REP (repeat) string oper ation (1 = REP string, 0 = not
a REP string)
■Bit 2—I/O string operation (1 = I/O string, 0 = not a I/O
string)
■Bit 1—Valid I/O instruction (1 = v alid, 0 = invalid)
■Bit 0—Input or output instruction ( 1 = INx, 0 = OUTx)
Chapter 5 Mobile AMD-K6®-2 Processor Operation 49
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Preliminary Information
Table 11 shows the format of the I/O tr ap dw or d.
The I/O trap dword is relat ed to the I/O trap restart slot (see
“I/O Trap Restart Slot” on page 49). If bit 1 of the I/O trap
dword is set by the processor, it means that SMI# was asserted
during the execution of an I/O instruction. The SMI handler
tests bit 1 to see if there is a valid I/O instruction trapped. If
the I/O instruction is vali d, the SMI handler is required to
ensure the I/O trap restart slot is set properly. The I/O trap
restart slot informs the CPU whether it should re-execute the
I/O instruction after the RSM or execute the instruction
following the trapped I/O in struction.
Note: If SMI# is sampled asserted dur ing an I/O bus cycle a mini-
m um of three clock edges before BRDY# is sample d asser ted,
the associated I/O instruction is guaranteed to be trapped by
the SMI handler.
I/O Trap Restart Slot The I/O trap restart slot at offset FF00h in the SMM state-save
area specifies whether the trapped I/O instruction shoul d be
r e-executed on return from SMM. This slot in the state-save ar ea
is ca lled the I/O instruction re start function. Re-executing a
trapped I/O instruction is useful, for example, if an I/O write
occurs to a disk that is powered down. The system logic
monitoring such an access can assert SMI#. Then the SMM
ser vice r outine w ould quer y the system lo gic, detect a f ailed I/O
write, take action to power-up the I/O device, enable the I/O
tr ap restart slot feature, and r eturn f rom SMM.
T he fiel ds of the I/O tr a p r estar t slot are defined as f ollo ws:
■Bits 31–16—Reserved
■Bits 15–0—I/O instruc tion restart on r eturn fr om S MM:
0000h = execute the next instruction after the trapped
I/O instruction
00FFh = re-execute the trapped I/O instruction
Table 11. I/O Trap Dword Configuration
31—16 15—4 3 2 1 0
I/O Port
Address Reserved REP String
Operation I/O String
Operation Valid I/O
Instruction Input or
Output
50 Mobile AMD-K6®-2 Processor Operation Chapter 5
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Ta ble 12 sho w s the f orm at of the I/O trap r estar t slot.
The processor initializes the I/O trap restart slot to 0000h upon
entry into SMM. If SMM was entered due to a trapped I/O
instruction, the processor indicates the validity of the I/O
instruction by setting or clearing bit 1 of the I/ O trap dwo rd at
offset FFA4h in the SMM state-save area . The SMM service
routine should test bit 1 of the I/O trap dword to determine if a
valid I/O instruction was being executed when entering SMM
and bef or e writing the I/O tr ap restart slot. If the I/O instruction
is valid, the SMM service r outine can safel y re write the I/O trap
r estart slot with the v alue 00FFh, whic h causes the pr ocessor to
re-execute the trapped I/O instruction when the RSM
instruction is executed. If the I/O instruction is invalid, writing
the I/O trap restart slot has undefined results.
If a second SMI# is asserted and a valid I/O instruction was
trapp ed by the first SMM handler, the CPU services the second
SMI# prior to re-executing the trapped I/O instruction. The
second entr y into SMM ne ver has bit 1 of the I/O tr ap dw or d set,
and the second SMM service routine must no t rewrite the I/O
tr ap r estart slot.
During a simul taneous SMI# I/O instruction trap and debug
breakpoint trap, the Mobile AMD-K6-2 processor first responds
to the SMI# and postpones recognizing the debug ex ception
until after returning from SMM via the RSM instruction. If the
de bug r egisters DR3–DR0 ar e used while in SMM, they m ust be
saved and restored by the SMM handler. The processor
automatically saves and restores D R7–DR6. If the I/O trap
resta rt slot in the SMM s tate-save area c ontains th e value
00FFh when the R SM instruct ion is executed, th e debug trap
does not occur until after the I/O instruction is r e-executed.
Table 12. I/O Trap Restart Slot
31–16 15–0
Reserved I/O Instruction restart on return from SMM:
■0000h = execute the next instr uction after the tr apped I/O
■00FFh = re-execute the trapped I/O instruct ion
Chapter 5 Mobile AMD-K6®-2 Processor Operation 51
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
Exceptions,
Interrupts, and
Debug in SMM
During an SMI# I/O trap, the e xception/interrupt priority of the
Mobile AMD-K 6-2 processor changes from its normal priority.
The normal priority places the debug traps at a priority higher
than the sampling of the FLUSH# or SMI# signals. However,
during an SMI# I/O trap, the sampling of the FLUSH# or SMI#
signals takes pr eced ence o v e r debug traps.
The proce ssor recognizes t he assertion of NMI within SMM
immediately after the completion of an IRET instruction. Once
NMI is recognized within SMM, NMI recognition remains
enabled until SMM is exited, at which point NMI masking is
r esto r ed to the s tate it was in bef ore entering SMM.
52 Mobile AMD-K6®-2 Processor Operation Chapter 5
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Chapter 6 Signal Switching C haracteristics 53
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
6 Signal Switching Characteristics
The Mobile AMD-K6-2 processor signal switching
characteristics are presented in Table 13 through Table 22.
Valid delay, float, setup, and hold timing specifications are
listed. These specifications are provided for the system
designer to determine if the timings necessary f or the processor
to interface with the system lo gic ar e met. Table 13 and Ta ble 14
contain the s witching c har acteristics of the CLK input. Table 15
through Table 18 contain the timings for the normal operation
signals. Table 19 and Table 20 contain the timings for RESET
and the configur ation signals. Table 21 and Table 22 contain the
timing s f or the test ope r atio n signa ls.
All signal timings pr o v ided ar e:
■Measured between CLK, TCK, or RESET at 1.5 V and the
corresponding signal at 1.5 V—this applies to input and
output signals that are switching from Low to High, or from
High to Lo w
■Based on input signals applied at a slew rate of 1 V/ns
betw een 0 V and 3 V (rising) and 3 V to 0 V (falli ng)
■Valid within the operating ranges given in “Operating
Ranges” on page 71
■Based on a load capacitance (CL) of 0 pF
6.1 CLK Switching Characteristics
Table 13 and Table 14 contain the switching charac teristics of
the CLK input to the Mobile AMD-K6 -2 processor for 100-MHz
and 66-MHz bus operation, respectively, as measured at the
v oltage lev els indicated by Figur e 9 on page 55.
T he CLK Period Sta bility specifies the variance (jitter) allowed
betw een successi v e periods of the CLK input measur ed at 1.5 V.
Th is parameter must be considered as one of the elements of
cloc k skew betw een the Mobile A MD-K6-2 and the system lo gic.
54 Signal Switching Characteristics Chapter 6
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
6.2 Clock Switching Char acteristics for 100-MHz Bus Operation
6.3 C lock Switching Characteristics for 66-MHz Bus Operation
Table 13. CLK Switching Characteristics for 100-MHz Bus Operation
Symbol Par am eter Desc rip tion Preliminary Data Figure Comments
Min Max
Frequency 33.3 MHz 100 MHz In Normal Mode
t1CLK Period 10.0 ns 9 In Normal Mode
t2CLK High Time 3.0 ns 9
t3CLK Low Time 3.0 ns 9
t4CLK Fall Time 0.15 ns 1.5 ns 9
t5CLK Rise Time 0.15 ns 1.5 ns 9
CLK Period Stability ± 250 ps Note
Note:
Jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 kHz.
Table 14. CLK Switching Characteristics for 66-MHz Bus Operation
Symbol Par am eter Desc rip tion Preliminary Data Figure Comments
Min Max
Frequency 33.3 MHz 66.6 MHz In Normal Mode
t1CLK Period 15.0 ns 30.0 ns 9 In No rmal Mode
t2CLK High Time 4.0 ns 9
t3CLK Low Time 4.0 ns 9
t4CLK Fall Time 0.15 ns 1.5 ns 9
t5CLK Rise Time 0.15 ns 1.5 ns 9
CLK Period Stability ± 250 ps Note
Note:
Jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 KHz.
Chapter 6 Signal Switching C haracteristics 55
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
Figure 9. CLK Waveform
6.4 Valid Delay, Float, Setup, and Hold Timings
Valid delay and float tim ings ar e giv en f or output signals during
functional operation and are given relativ e to the rising edge of
CLK. During boundary-scan testing, valid delay and float
timings fo r output signals ar e with r espect to the f alling edge of
TCK. The maximum valid delay timings are provided to allow a
system designer to determine if setup times to the system logic
can be met. Lik ewise, the minim um valid dela y timings ar e used
to anal yze hold times to the system lo gic.
The setup and hold time requirements for the Mobile
AMD-K6-2 processor input signals must be m et by the system
logic to assure the proper operation of the processor. The setup
and hold timings during functional and boundary-scan test
mode are given relative to the rising edge of CLK and TCK,
respectively.
t5
2.0 V
1.5 V
0.8 V
t2
t3
t4
t1
56 Signal Switching Characteristics Chapter 6
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
6.5 Output Delay Timings for 100-MHz Bus Operation
Table 15. Output Delay Timings for 100-MHz Bus Operation
Symbol Par am eter Desc rip tion Preliminary Data Figure Comments
Min Max
t6A[31:3] Valid Delay 1.1 ns 4.0 ns 11
t7A[31:3] Float Delay 7.0 ns 12
t8ADS# Valid Delay 1.0 ns 4.0 ns 11
t9ADS# Float Delay 7.0 ns 12
t10 ADSC# Valid Delay 1.0 ns 4.0 ns 11
t11 ADSC# Float Delay 7.0 ns 12
t12 AP Valid Delay 1.0 ns 5.5 ns 11
t13 AP Float Delay 7.0 ns 12
t14 APCHK# Valid Delay 1.0 ns 4.5 ns 11
t15 BE[7:0]# Valid Delay 1.0 ns 4.0 ns 11
t16 BE[7:0]# Float Delay 7.0 ns 12
t17 BREQ Valid Delay 1.0 ns 4.0 ns 11
t18 CACHE# Val id Delay 1.0 ns 4.0 ns 11
t19 CACH E# Float Delay 7.0 ns 12
t20 D/C# Valid Delay 1.0 ns 4.0 ns 11
t21 D/C# Float Delay 7.0 ns 12
t22 D[63:0] Write Data Valid Delay 1.3 ns 4.5 ns 11
t23 D[63:0] Write Data Float Delay 7.0 ns 12
t24 DP[7:0] Write Data Valid Delay 1.3 ns 4.5 ns 11
t25 DP[7:0] Write Data Float Delay 7.0 ns 12
t26 FERR# Valid Delay 1.0 ns 4.5 ns 11
t27 HIT# Valid Delay 1.0 ns 4.0 ns 11
t28 HITM# Valid Delay 1.1 ns 4.0 ns 11
t29 HLDA Valid Delay 1.0 ns 4.0 ns 11
t30 LOCK# Valid Delay 1.1 ns 4.0 ns 11
t31 LOCK# Float Delay 7.0 ns 12
t32 M/IO# Valid Delay 1.0 ns 4.0 ns 11
t33 M/IO# Float Delay 7.0 ns 12
Chapter 6 Signal Switching C haracteristics 57
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
t34 PCD Valid Delay 1.0 ns 4.0 ns 11
t35 PCD Float Delay 7.0 ns 12
t36 PCHK# Valid Delay 1.0 ns 4.5 ns 11
t37 P WT Valid Delay 1.0 ns 4.0 ns 11
t38 PWT Float Delay 7.0 ns 12
t39 SCYC Valid Delay 1.0 ns 4.0 ns 11
t40 SCYC Float Delay 7.0 ns 12
t41 SMIACT# Valid Delay 1.0 ns 4.0 ns 11
t42 W/R# Valid Delay 1.0 ns 4.0 ns 11
t43 W/R# Float Delay 7.0 ns 12
Table 15. Output Delay Timings for 100-MHz Bus Operation (continued)
Symbol Par am eter Desc rip tion Preliminary Data Figure Comments
Min Max
58 Signal Switching Characteristics Chapter 6
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
6.6 Input Setup and Hold Timings for 100-MHz Bus Operation
Table 16. Input Setup and Hold Timings for 100-MHz Bus Operation
Symbol Par am eter Desc rip tion Preliminary Data Figure Comments
Min Max
t44 A[31:5] Setup Time 3.0 ns 13
t45 A[31:5] Hold Time 1.0 ns 13
t46 A20M# Setup Time 3.0 ns 13 Note 1
t47 A20M# Hold Time 1.0 ns 13 Note 1
t48 AHOLD Setup Time 3.5 ns 13
t49 AHOLD Hold Time 1.0 ns 13
t50 AP Setup Time 1.7 ns 13
t51 AP Hold Time 1.0 ns 13
t52 BOFF# Setup Time 3.5 ns 13
t53 BOFF# Hold Time 1.0 ns 13
t54 BRDY# Setup Time 3.0 ns 13
t55 BRDY# Hold Time 1.0 ns 13
t56 BR DYC# Setup Time 3.0 ns 13
t57 BRDYC# Hold Time 1.0 ns 13
t58 D[63:0] Read Data Setup Time 1.7 ns 13
t59 D[63:0] Read Data Hold Time 1.5 ns 13
t60 DP[7:0] Read Data Setup Time 1.7 ns 13
t61 DP[7:0] Read Data Hold Time 1.5 ns 13
t62 EADS# Setup Time 3.0 ns 13
t63 EADS# Hold Time 1.0 ns 13
t64 EWBE# Setup Time 1.7 ns 13
t65 EWBE# Hold Time 1.0 ns 13
t66 FLUSH# Setup Time 1.7 ns 13 Note 2
t67 FLUSH# Hold Time 1.0 ns 13 Note 2
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously . To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously . To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
Chapter 6 Signal Switching C haracteristics 59
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
t68 HOLD Setup Time 1.7 ns 13
t69 HOLD Hold Time 1.5 ns 13
t70 IGNNE# Setup Time 1.7 ns 13 Note 1
t71 IGNNE# Hold Time 1.0 ns 13 Note 1
t72 INIT Setup Time 1.7 ns 13 Note 2
t73 INIT Hold Time 1.0 ns 13 Note 2
t74 INTR Setup Time 1.7 ns 13 Note 1
t75 INTR Hold Time 1.0 ns 13 Note 1
t76 INV Setup Time 1.7 ns 13
t77 INV Hold Time 1.0 ns 13
t78 KEN# Setup Time 3.0 ns 13
t79 KEN# Hold Time 1.0 ns 13
t80 NA# Setup Time 1.7 ns 13
t81 NA# Hold Time 1.0 ns 13
t82 NMI Setup Time 1.7 ns 13 Note 2
t83 NMI H old Time 1.0 ns 13 Note 2
t84 SMI# Setup Time 1.7 ns 13 Note 2
t85 SMI# Hold Time 1.0 ns 13 Note 2
t86 STPCLK# Setup Time 1.7 ns 13 Note 1
t87 STPCLK# Hold Time 1.0 ns 13 Note 1
t88 WB/WT# Setup Time 1.7 ns 13
t89 WB/WT# Hold Time 1.0 ns 13
Table 16. Input Setup and Hold Timings for 100-MHz Bus Operation (continued)
Symbol Par am eter Desc rip tion Preliminary Data Figure Comments
Min Max
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously . To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously . To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
60 Signal Switching Characteristics Chapter 6
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
6.7 Output Delay Timings for 66-MHz Bus Operation
Table 17. Output Delay Timings for 66-MHz Bus Operation
Symbol Par am eter Desc rip tion Preliminary Data Figure Comments
Min Max
t6A[31:3] Valid Delay 1.1 ns 6.3 ns 11
t7A[31:3] Float Delay 10.0 ns 12
t8ADS# Valid Delay 1.0 ns 6.0 ns 11
t9ADS# Float Delay 10.0 ns 12
t10 ADSC# Valid Delay 1.0 ns 7.0 ns 11
t11 ADSC# Float Delay 10.0 ns 12
t12 AP Valid Delay 1.0 ns 8.5 ns 11
t13 AP Float Delay 10.0 ns 12
t14 APCHK# Valid Delay 1.0 ns 8.3 ns 11
t15 BE[7:0}# Valid Delay 1.0 ns 7.0 ns 11
t16 BE[7:0}# Float Delay 10.0 ns 12
t17 BREQ Valid Delay 1.0 ns 8.0 ns 11
t18 CACHE# Val id Delay 1.0 ns 7.0 ns 11
t19 CACH E# Float Delay 10.0 ns 12
t20 D/C# Valid Delay 1.0 ns 7.0 ns 11
t21 D/C# Float Delay 10.0 ns 12
t22 D[63:0] Write Data Valid Delay 1.3 ns 7.5 ns 11
t23 D[63:0] Write Data Float Delay 10.0 ns 12
t24 DP[7:0] Write Data Valid Delay 1.3 ns 7.5 ns 11
t25 DP[7:0] Write Data Float Delay 10.0 ns 12
t26 FERR# Valid Delay 1.0 ns 8.3 ns 11
t27 HIT# Valid Delay 1.0 ns 6.8 ns 11
t28 HITM# Valid Delay 1.1 ns 6.0 ns 11
t29 HLDA Valid Delay 1.0 ns 6.8 ns 11
t30 LOCK# Valid Delay 1.1 ns 7.0 ns 11
t31 LOCK# Float Delay 10.0 ns 12
t32 M/IO# Valid Delay 1.0 ns 5.9 ns 11
t33 M/IO# Float Delay 10.0 ns 12
Chapter 6 Signal Switching C haracteristics 61
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
t34 PCD Valid Delay 1.0 ns 7.0 ns 11
t35 PCD Float Delay 10.0 ns 12
t36 PCHK# Valid Delay 1.0 ns 7.0 ns 11
t37 P WT Valid Delay 1.0 ns 7.0 ns 11
t38 PWT Float Delay 10.0 ns 12
t39 SCYC Valid Delay 1.0 ns 7.0 ns 11
t40 SCYC Float Delay 10.0 ns 12
t41 SMIACT# Valid Delay 1.0 ns 7.3 ns 11
t42 W/R# Valid Delay 1.0 ns 7.0 ns 11
t43 W/R# Float Delay 10.0 ns 12
Table 17. Output Delay Timings for 66-MHz Bus Operation (continued)
Symbol Par am eter Desc rip tion Preliminary Data Figure Comments
Min Max
62 Signal Switching Characteristics Chapter 6
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
6.8 Input Setup and Hold Timings for 66-MHz Bus Operation
Table 18. Input Setup and Hold Timings for 66-MHz Bus Operation
Symbol Par am eter Desc rip tion Preliminary Data Figure Comments
Min Max
t44 A[31:5] Setup Time 6.0 ns 13
t45 A[31:5] Hold Time 1.0 ns 13
t46 A20M# Setup Time 5.0 ns 13 Note 1
t47 A20M# Hold Time 1.0 ns 13 Note 1
t48 AHOLD Setup Time 5.5 ns 13
t49 AHOLD Hold Time 1.0 ns 13
t50 AP Setup Time 5.0 ns 13
t51 AP Hold Time 1.0 ns 13
t52 BOFF# Setup Time 5.5 ns 13
t53 BOFF# Hold Time 1.0 ns 13
t54 BRDY# Setup Time 5.0 ns 13
t55 BRDY# Hold Time 1.0 ns 13
t56 BR DYC# Setup Time 5.0 ns 13
t57 BRDYC# Hold Time 1.0 ns 13
t58 D[63:0] Read Data Setup Time 2.8 ns 13
t59 D[63:0] Read Data Hold Time 1.5 ns 13
t60 DP[7:0] Read Data Setup Time 2.8 ns 13
t61 DP[7:0] Read Data Hold Time 1.5 ns 13
t62 EADS# Setup Time 5.0 ns 13
t63 EADS# Hold Time 1.0 ns 13
t64 EWBE# Setup Time 5.0 ns 13
t65 EWBE# Hold Time 1.0 ns 13
t66 FLUSH# Setup Time 5.0 ns 13 Note 2
t67 FLUSH# Hold Time 1.0 ns 13 Note 2
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously . To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously . To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
Chapter 6 Signal Switching C haracteristics 63
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
t68 HOLD Setup Time 5.0 ns 13
t69 HOLD Hold Time 1.5 ns 13
t70 IGNNE# Setup Time 5.0 ns 13 Note 1
t71 IGNNE# Hold Time 1.0 ns 13 Note 1
t72 INIT Setup Time 5.0 ns 13 Note 2
t73 INIT Hold Time 1.0 ns 13 Note 2
t74 INTR Setup Time 5.0 ns 13 Note 1
t75 INTR Hold Time 1.0 ns 13 Note 1
t76 INV Setup Time 5.0 ns 13
t77 INV Hold Time 1.0 ns 13
t78 KEN# Setup Time 5.0 ns 13
t79 KEN# Hold Time 1.0 ns 13
t80 NA# Setup Time 4.5 ns 13
t81 NA# Hold Time 1.0 ns 13
t82 NMI Setup Time 5.0 ns 13 Note 2
t83 NMI H old Time 1.0 ns 13 Note 2
t84 SMI# Setup Time 5.0 ns 13 Note 2
t85 SMI# Hold Time 1.0 ns 13 Note 2
t86 STPCLK# Setup Time 5.0 ns 13 Note 1
t87 STPCLK# Hold Time 1.0 ns 13 Note 1
t88 WB/WT# Setup Time 4.5 ns 13
t89 WB/WT# Hold Time 1.0 ns 13
Table 18. Input Setup and Hold Timings for 66-MHz Bus Operation (continued)
Symbol Par am eter Desc rip tion Preliminary Data Figure Comments
Min Max
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously . To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously . To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
64 Signal Switching Characteristics Chapter 6
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
6.9 RESET and Test Signal Timing
Table 19. RESET and Configuration Signals for 100-MHz Bus Operation
Symbol Parameter Des c rip tion Preliminary Data Figure Comments
Min Max
t90 RESET Setup Time 1.7 ns 14
t91 RESET Hold Time 1.0 ns 14
t92 R ESET Pulse Width, VCC and CLK Stable 15 clocks 14
t93 R ESET Active After VCC and CLK Stable 1.0 ms 14
t94 BF[2:0] Setup Time 1.0 ms 14 Note 3
t95 BF[2:0] Hold Time 2 clocks 14 Note 3
t96 BRDYC# Hold Time 1.0 ns 14 Note 4
t97 BR DYC# Setup Time 2 clocks 14 Note 2
t98 BRDYC# Hold Time 2 clocks 14 Note 2
t99 FLUSH# Setup Time 1.7 ns 14 Note 1
t100 FLU SH# Hold Time 1.0 ns 14 Note 1
t101 FLUSH# Setup Time 2 clocks 14 Note 2
t102 FLUSH# Hold Time 2 clocks 14 Note 2
Notes:
1. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET
is sampled negated.
2. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of
RESET.
3. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.
4. If RESET is driven synchronously, BRDYC# must meet the specified hold time relative to the negation of RESET.
Chapter 6 Signal Switching C haracteristics 65
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
Table 20. RESET and Configuration Signals for 66-MHz Bus Operation
Symbol Parameter Des c rip tion Preliminary Data Figure Comments
Min Max
t90 RESET Setup Time 5.0 ns 14
t91 RESET Hold Time 1.0 ns 14
t92 R ESET Pulse Width, VCC and CLK Stable 15 clocks 14
t93 R ESET Active After VCC and CLK Stable 1.0 ms 14
t94 BF[2:0] Setup Time 1.0 ms 14 Note 3
t95 BF[2:0] Hold Time 2 clocks 14 Note 3
t96 BRDYC# Hold Time 1.0 ns 14 Note 4
t97 BR DYC# Setup Time 2 clocks 14 Note 2
t98 BRDYC# Hold Time 2 clocks 14 Note 2
t99 FLUSH# Setup Time 5.0 ns 14 Note 1
t100 FLU SH# Hold Time 1.0 ns 14 Note 1
t101 FLUSH# Setup Time 2 clocks 14 Note 2
t102 FLUSH# Hold Time 2 clocks 14 Note 2
Notes:
1. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET
is sampled negated.
2. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of
RESET.
3. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.
4. If RESET is driven synchronously, BRDYC# must meet the specified hold time relative to the negation of RESET.
66 Signal Switching Characteristics Chapter 6
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Table 21. TCK Waveform and TRST# Timing at 25 MHz
S ym bol P arameter Description Preliminary Data Figure Comments
Min Max
TCK Fr equency 25 MHz 15
t103 TCK Period 40.0 ns 15
t104 TCK High Time 14.0 ns 15
t105 TCK Low Time 14.0 ns 15
t106 TCK Fall Time 5.0 ns 15 Note 1, 2
t107 TCK Rise Time 5.0 ns 15 Note 1, 2
t108 TRST# Pulse Width 30.0 ns 16 Asynchronous
Notes:
1. Rise/Fall times can be increased by 1.0 ns for each 10 MHz that TCK is run below its maximum frequency of 25 MHz.
2. Rise/Fall times are measured between 0.8 V and 2.0 V.
Table 22. Test Signal Timing at 25 MHz
S ym bol Parameter Description Preliminary Data Figure Notes
Min Max
t109 TDI Setup Time 5.0 ns 17 Note 2
t110 TDI Hold Time 9.0 ns 17 Note 2
t111 TMS Setup Time 5.0 ns 17 Note 2
t112 TMS Hold Time 9.0 ns 17 Note 2
t113 TDO Valid Delay 3 .0 ns 13.0 ns 17 Note 1
t114 TDO Float Delay 16.0 ns 17 Note 1
t115 All Outputs (Non-Test) Valid Delay 3.0 ns 13.0 ns 17 Note 1
t116 All Outputs (Non-Test) Float Delay 16.0 ns 17 Note 1
t117 All Inputs (Non-Test) Setup Time 5.0 ns 17 Note 2
t118 All Inputs (Non-Test) Hold Time 9.0 ns 17 Note 2
Notes:
1. Parameter is measured from the TCK falling edge.
2. Parameter is measured from the TCK rising edge.
Chapter 6 Signal Switching C haracteristics 67
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
Figure 10. Diagrams Key
Figure 11. Output Valid Delay Timing
Must be steady
Can change from
High to Low
Can change
from Low to High
(Does not apply)
Don’t care, any
change permitted
Steady
Changing from High to Low
Changing from Low to High
Changing, State Unknown
Center line is high
impedance state
WAVEFORM INPUTS OUTPUTS
Min
Max
V alid n +1
tv
V alid n
CLK
Output Signal
Tx
Tx
1.5 V
v = 6, 8, 10, 12, 14, 15, 17, 18, 20, 22, 24, 26, 27, 28, 29, 30, 32, 34, 36, 37, 39, 41, 42
68 Signal Switching Characteristics Chapter 6
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Figure 12. Maximum Float Delay Timing
Figure 13. Input Setup and Hold Timing
TxTxTx
Valid
Tx
tv
Min
Output Signal
tf
CLK 1.5 V
v = 6, 8, 10, 12, 15, 18, 20, 22, 24, 30, 32, 34, 37, 39, 42
f = 7, 9, 11, 13, 16, 19, 21, 23, 25, 31, 33, 35, 38, 40, 43
CLK TxTxTxTx
Input Signal
tsth
1.5 V
s = 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88
h = 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89
Chapter 6 Signal Switching C haracteristics 69
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
Figure 14. Reset and Configuration Timing
Tx
CLK
RESET
Tx
t90
FLUSH#
(Synchronous)
1.5 V
1.5 V
1.5 V • • •
t92, 93
t91
t99 t100
• • •
BF[2:0]
(Asynchronous) t94
• • •
t95
FLUSH#, BRD YC#
(Asynchronous) t97, 101 t98, 102
• • •
• • •
70 Signal Switching Characteristics Chapter 6
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Figure 15. TCK Waveform
Figure 16. TRST# Timing
Figure 17. Test Signal Timing Diagram
t107
2.0 V
1.5 V
0.8 V
t105
t106
t103
t104
1.5 V
t108
TCK
TDI, TMS
TDO
Output
Signals
Input
Signals
t103
t109, 111 t110, 112
t113
t115 t116
t117 t118
t114
1.5 V
Chapter 7 Electrical Data 71
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
7 Electrical Data
7.1 Operating Ranges
The Mobile AMD-K6-2 processor is designed to provide
functional o per atio n if the voltage and te mper atur e par amet er s
ar e within the limits defined in Table 23.
7.2 Absolute Ratings
T he AM D-K6-2 processor is not designed to be operated beyond
the operating ranges listed in Table 23. Exposure to conditions
outside these operating ranges for extended periods of time can
affect long-term reliabil ity. Permanent damage can occur if the
a bsolute ratings listed in Table 24 are e xceeded.
Table 23. Operating Ranges
Parameter Minimum Typical Maximum Comments
VCC2 1.7 V 1.8 V 1.9 V Note 1, 2
VCC3 3.135 V 3.3 V 3.6 V Note 1
TCASE 0°C85°C (CBGA)
85°C (CPGA)
Note:
1. VCC2 and VCC3 are referenced from VSS.
2. VCC2 specification for 1.8 V component.
Table 24. Absolute Ratings
Parameter Minimum Maximum Comments
VCC2 –0.5 V 2.6 V
VCC3 –0.5 V 3.6 V
VPIN –0.5 V Vcc3 + 0.5 V and < 4.0 V Note
TCASE (under bias) –65°C +110°C
TSTORAGE –65°C +150°C
Note:
VPIN (the voltage on any I/O pin) must not be greater than 0.5 V above the voltage being applied
to VCC3. In addition, the VPIN voltage must never exceed 4.0 V.
72 Electrical Data Chapter 7
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
7.3 DC Characteristics
The DC charact eristics of the Mobile AMD-K6-2 processor are
sho wn in Table 25.
Table 25. DC Characteristics
Symbol Parameter Description Preliminary Data Comments
Min Max
VIL Input Low Voltage –0.3 V +0.8 V
VIH Input High Voltage 2.0 V VCC3+0.3V Note 1
VOL Output Low Voltage 0.4 V IOL = 4.0-mA load
VOH Output High Voltage 2.4 V IOH = 3.0-mA load
ICC2 1.8 V Power Supply Current 5.05 A 266 MHz, Note 2, 7
5.50 A 300 MHz, Note 2, 8
6.25 A 333 MHz, Note 2, 9
ICC3 3.3 V Power Supply Current 0.54 A 266 M Hz, Note 3, 7
0.56 A 300 MHz, Note 3, 8
0.58 A 333 MHz, Note 3, 9
ILI Input Leakage Current ±15 µA Note 4
ILO Output Leakage Current ±15 µA Note 4
IIL Input Leakage Current Bias w ith Pullup –400 µA Note 5
IIH Input Leakage Current Bias with Pulldown 200 µA Note 6
CIN Input Capacitance 10 pF
COUT Output Capacitance 15 pF
COUT I/O Capacitance 20 pF
CCLK CLK Capacitance 10 pF
Notes:
1. VCC3 refers to the voltage being applied to VCC3 during functional operation.
2. VCC2 = 1.9 V — The maximum power supply current must be taken into account when designing a power supply.
3. VCC3 = 3.6 V — The maximum power supply current must be taken into account when designing a power supply.
4. Refers to inputs and I/O without an internal pullup resistor and 0 ≤ VIN ≤ VCC3.
5. Refers to inputs with an internal pullup and VIL = 0.4 V.
6. Refers to inputs with an internal pulldown and VIH = 2.4 V.
7. This specification applies to components using a CLK frequency of 66 MHz.
8. This specification applies to components using a CLK frequency of 66 MHz or 100 MHz.
9. This specification applies to components using a CLK frequency of 66 MHz or 95 MHz.
Chapter 7 Ele ctrical Data 73
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
CTIN Test Input Capacitance (TDI, TMS, TRST#) 10 pF
CTOUT Test Output Capacitance (TDO) 15 pF
CTCK TCK Capacitance 10 pF
Table 25. DC Characteristics (continued)
Symbol Parameter Description Preliminary Data Comments
Min Max
Notes:
1. VCC3 refers to the voltage being applied to VCC3 during functional operation.
2. VCC2 = 1.9 V — The maximum power supply current must be taken into account when designing a power supply.
3. VCC3 = 3.6 V — The maximum power supply current must be taken into account when designing a power supply.
4. Refers to inputs and I/O without an internal pullup resistor and 0 ≤ VIN ≤ VCC3.
5. Refers to inputs with an internal pullup and VIL = 0.4 V.
6. Refers to inputs with an internal pulldown and VIH = 2.4 V.
7. This specification applies to components using a CLK frequency of 66 MHz.
8. This specification applies to components using a CLK frequency of 66 MHz or 100 MHz.
9. This specification applies to components using a CLK frequency of 66 MHz or 95 MHz.
74 Electrical Data Chapter 7
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
7.4 Pow er Dissipation
Table 26 contains the typical and maximum powe r dissipation
of the Mob ile AMD-K6-2 processor during normal and reduced
po w er states.
Table 26. Typical and Maximum Power Dissipation
Clock Control State 266 MHz6300 M Hz7333 MH z8Comments
Typ Max Typ Max Typ Max
Design Power 8.00 W 9.00 W 8.85 W 10.00 W 9.65 W 11.00 W Note 1, 2
Application Power 6.30 W -- 7.00 W -- 7.70 W -- Note 3
Stop Grant / Halt (Maximum) -- 1.20 W -- 1.20 W -- 1.20 W Note 4
Stop Clock (Maximum) -- 1.00 W -- 1.00 W -- 1.00 W Note 5
Notes:
1. Design PowerMax r epresents the total power dissipated by all components within the processor while executing a worse-
case instruction sequence under normal system operation with VCC2 = 1.8 V and VCC3 = 3.3 V. Thermal solutions must be
designed to dissipate the processor’s maximum design power unless the system uses thermal feedback to limit the
processor’s maximum power.
2. Design PowerTyp represents the maximum power dissipated while executing software or instruction sequences under
normal system operation with VCC2 = 1.8 V and VCC3 = 3.3 V.
3. Application Power represents the average power dissipated while executing software or instruction sequences under
normal system operation with VCC2 = 1.8 V and VCC3 = 3.3 V.
4. The CLK signal and the internal PLL are still running but most internal clocking has stopped.
5. The CLK signal, the internal PLL, and all internal clocking has stopped.
6. This specification applies to components using a CLK frequency of 66 MHz.
7. This specification applies to components using a CLK frequency of 66 MHz or 100 MHz.
8. This specification applies to components using a CLK frequency of 66 MHz or 95 MHz.
Chapter 7 Ele ctrical Data 75
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
7.5 Power and Grounding
Power Connections The Mobile AMD-K6-2 processor is a dual volt age device. Two
separate supply voltages are required: VCC2 and VCC3. V CC2
provides the core voltage for the Mobile AMD-K6-2 processor
and VCC3 prov ides the I/O voltage. See “Elect rical Data” on
page 71 f or the value and r ange of VCC2 and VCC3.
There are 28 VCC2, 32 VCC3, and 68 VSS pins on the CPGA and
42 VCC2, 42 VCC3, and 85 VSS pins on the CBGA Mobile
AMD-K 6-2. (See Chapter 10, “P in Description D iagrams” on
page 89 for all power and ground pin designations.) The large
number of power and ground pins are provided to ensure that
the proc essor and pack age maintain a clean and stable power
distribution netw ork.
For pr ope r operation and functionality, all VCC2, VCC3, and VSS
pins must be connected to the appropriate planes in the circuit
board. The powe r planes have be en arra nged in a pa ttern to
simplify routing and minimiz e crosstalk on the circuit board.
Th e isolati on regi on between two voltage plan es must be a t
least 0.254mm if they ar e in the same la yer of the cir cuit boar d.
(See Figur e 18 on page 76.) In or der to maintain lo w-impedance
current sink and reference, the ground plane mus t never be
split.
Although the Mobile AMD-K6-2 processor has two separate
supply voltages, there are no special power sequencing
requirements. The best procedure is to minimize the time
betw een which VCC2 and VCC3 ar e eithe r both on or both off .
76 Electrical Data Chapter 7
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Figure 18. Suggested Component Placement
CPGA Package
VCC2 (Core) Plane
VCC3 (I/O) Plane
0.254mm (min.) for
isolation region
C1
CC5
CC3
C2
+
+
+
+
C5
C6
C7
C8
C9
C10
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
CC4
+
CC6
C14
C15
C16
CC8
CC7
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
19
18
17
16
15
1413
1211109
8
7
6
5
4
3
21
1918
17
16
15
14
1312
11
10
9
87
6
5
4
3
2
1
Bottom View
CC6 CC5 CC4
CC3
Other
VSS Pins
V
CC3
Pins
V
CC2
Pins
C1
C2
CC7
CC10
0.254m m (min.) for
isolation region
CC9 CC8
CBGA Package
Chapter 7 Ele ctrical Data 77
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
Decoupling
Recommendations In addition to the isolation region mentioned in “Power
Connections” on page 75, adequate decoupling capacitance is
required between the two system power planes and the ground
plane to minimize ringing and to pr ovide a lo w-impedance path
for return currents. Suggested decoupling capacitor placement
is sho w n in Figur e 18 on pa ge 76.
Surface mounted capacitors should be used as close as possible
to the processor to minimize resistance and inductance in the
lead lengths while maintaining minimal height. For
r ecommendat ions r egar ding the v alue, quantity, and location of
the capacitors illustr a ted in Figur e 18 , see the Mobile AMD-K6®
Processor P ower Supply Application Note, or der # 22495.
Pin Connection
Requirements For proper operation, the following requirements for signal pin
connections must be met:
■Do not drive address and data signals into large capacitive
loads at high frequencies. If necessary, use buffer chips to
dri v e lar ge capaciti v e loads.
■Lea v e all NC (no-connect) pins unconnected.
■Unused inputs should alwa ys be connected to an appropriate
signal le v e l.
•Active Low inputs that are not being used should be
connected to VCC3 thr ough a 20k- ohm pullup r esistor.
•Active High inputs that are not being used should be
connected to GND thr ough a pulldo wn r esistor.
■Reserved signals (CPGA only) can be treated in one of the
f o llo w ing w ays:
•As no-connect (NC) pins, in whic h case these pins ar e left
unconnected
•As pins connected to the system logic as defined by the
industr y-standar d Super7 and Soc k et 7 interface
•An y combination of NC and Soc k et 7 pins
■K eep tr ace l engths to a mi nim um.
78 Electrical Data Chapter 7
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Chapter 8 Thermal Design 79
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
8 Thermal Design
8.1 Package Thermal Specifications
The Mobile AMD-K6-2 processor operating spec ificatio ns call
for the case temperature (TC) to be in the range of 0°C to 85°C
for the CBGA package and 0°C to 85°C for the CPGA package.
The ambient temperature (TA) is no t specified as long a s the
case temper ature is not violated. The case temperatur e m ust be
measured on the top center of the package. Table 27 shows the
Mobile AMD-K6-2 processor thermal specifications.
Figu re 19 on page 80 shows the thermal mo del of a processor
with a passive thermal solution. The case-to-ambient
temperature (TCA) can be calculated from the following
equation:
TCA = PMAX • θCA
= PMAX • ( θIF + θSA)
Where:
PMAX = Maximum Power Consumption
θCA = Case-to-Ambient Thermal Resistance
θIF = Interface Material Thermal Resistance
θSA = Sink-to-Ambient Thermal Resistance
Table 27. Package Thermal Specifications
TC
Case Temper atu re
Maximum Design Power
1.8 V Component
266 MHz 300 M Hz 333 MHz
0°C – 85°C (CBGA)
0°C – 85°C (CPGA) 9.00 W 10.00 W 11.00 W
80 Thermal Design Chapter 8
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Figure 19. Thermal Model (CBGA Package)
Figure 20 illustrates the case-to-ambient temperature (TCA) in
relation to the power consumption (X-axis) and the thermal
resistance (Y-axis). If the power consumption and case
temperature are known, the thermal resistance (θCA)
r equir ement can be calculated f or a gi v en ambient temper ature
(TA) va lue.
Figure 20. Power Consumption versus Thermal Resistance
The thermal resistance of a heatsink is determined by the heat
dissipation surface area, the material and shape of the
heatsink, and the airflow volume across the heatsink. In
general, the larger the surface area the lower t he thermal
resistance.
Temperature Thermal
θSA θCA
θIF
(°C/W)
(Ambient)
Case
Sink
TCA
Substrate
Heat Exchange Device
Resistance
0.0
1.0
2.0
3.0
4.0
5.0
6.0
6 W 9 W 12 W 15 W 18 W
Power Consum pti on (Watts)
Thermal Resistance (°C/W)
30° C
25° C
20° C
15° C
T
CA
TCA = TC - TA
Chapter 8 Thermal Design 81
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
The re quired thermal resistance of a heatsink ( θSA) can be
calculat ed using the f ollowing exa mple:
If:
TC = 85°C (CBGA package)
TA = 55°C
PMAX = 11.00W at 333MHz
Then:
Thermal grease is recommended as interface material because
it provides the lowest thermal resistance (approx. 0.20°C/W).
Th e required thermal resistance (θSA) of the heat sink in this
example is calculated as follo ws:
θSA = θCA – θIF = 2.73 – 0.20 = 2.53(°C/W)
Heat Dissipation Path Figure 21 illustrates the heat dissipation path of the processor.
Due to the lower thermal resistance between the processor die
junction and case, most of the heat generated by the processor
is transferred from the top surface of the case. Part of the heat
gener ated fr om the bottom si de of the pr ocessor is dissipated to
the cir cuit boar d thr ough the ball contacts.
Figure 21. Processor’s Heat Dissipation Path (CBGA Package)
θCA TCTA
–
PMAX
-------------------
≤30°C
11.00W
--------------------- 2.73 °CW⁄()
==
Substrate
C ase Temperature
Ambient Temperature
(Ceramic)
PCB
82 Thermal Design Chapter 8
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Measuring Case
Temperature The processor case temperature is measured to ensure that the
thermal solution meets the processor’s operational
specification. This temperature should be measured on the top
center of the package where most of the heat is dissipated.
Figure 22 shows the c orrect locat ion for measuring the case
temperature. If a heatsink is installed while measuring, the
thermocouple must be installed into the heatsink via a small
hole drilled through the heatsink base (for example, 1/16 of an
inch). The thermocouple is then attached to the base of the
heatsink and the small hole filled using thermal epoxy, allowing
the tip of the thermocouple to touch the top of the processor
case.
Figure 22. Measuring Case Temperature
For mor e information on thermal design consider ations, see the
AMD-K6® Thermal Solution Design Application Note, orde r#
21085.
Thermocouple
Thermally Conductive Epoxy
Chapter 9 Package Specifications 83
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
9 Package Specifications
9.1 321-Pin Staggered CPGA Package Specification
Table 28. 321-Pin Staggered CPGA Package Specification
Symbol Millimeters Inches Notes
Min Max Min Max
A 49.28 49.78 1.940 1.960
B 45.59 45.85 1.795 1.805
C 31.01 32.89 1.221 1.295
D 44.90 45.10 1.768 1.776
E 2.91 3.63 0.115 0.143
F 1.30 1.52 0.051 0.060
G 3.05 3.30 0.120 0.130
H 0.43 0.51 0.017 0.020
M 2.29 2.79 0.090 0.110
N 1.14 1.40 0.045 0.055
d 1.52 2.29 0.060 0.090
e 1.52 2.54 0.060 0.100
f — 0.13 — 0.005 Flatness
84 Package Specifications Chapter 9
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Figure 23. 321-Pin Staggered CPGA Package Specification
Chapter 9 Package Specifications 85
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
9.2 360-Pin Model 8 CBGA Package Specification
Table 29. 360-Pin Model 8 CBGA Package Specification
Symbol Millimeters Inches Notes
Min Max Min Max
A 24.75 25.25 0.975 0.994
B 22.60 23.10 0.890 0.910
C 6.45 6.85 0.254 0.270
D 11.40 12.02 0.449 0.474
E 2.64 2.92 0.104 0.115
F 0.73 0.88 0.029 0.035
G 1.02 1.18 0.040 0.046
H 0.77 1.01 0.030 0.040
J—13.65—0.5371
K—20.14—0.7931
M 1.27 BSC. 0.050 BSC.
e 0.11 — 0.004 — 2
f — 0.10 — 0.004 Flatness
Notes:
1. This area represents the component outline in which decoupling capacitors may be mounted on the ceramic
by AM D.
2. The decoupling capacitors shown in Figure 24 on page 86 are for illustrative purposes only. AMD will
determine the exact placement and number of these capacitors.
86 Package Specifications Chapter 9
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Figure 24. 360-Pin CBGA Package Specification
A
A
B
B
C
J
E
F
M
HH
0.150 T
f
e
G
D
K
M
Chapter 9 Package Specifications 87
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
9.3 360-Pin CBGA Mechanical Specification
Table 30. 360-Pin CBGA Mechanical Specification
Parameter Min Max Notes
Continuous Compressive Mechanical Load 8 lbf 1
Non-continuous Compressive Mechanical Load 30 lbf 2
Dynamic Load During Mechanical Shock 5 lbf 3, 4, 5, 6
Nominal Package Height ± RSS tolerance 2.78 mm ± 0.130 7, 8
Package Height 2.64 mm 2.92 mm 7, 8
Solder Ball Coplanarity 0.150 mm 7, 8
Notes:
1. Appl y the load uniformly over the die surface. A compressible thermal pad is recommended to ensure l oad distribution
and prevent of damage to the exposed silicon die during shipping and use. Thermal greases and waxes are also
acceptable.
2. This parameter represents a compressive load applied to the CBGA for no more than 30 seconds.
3. The dynamic load represents the dynamic acceleration imparted to the total mass, which includes the chip carrier and any
mass supported by the chip carrier.
4. For designs that apply a continuous load to the CBGA, separation of the thermal interface must be prevented during
mechanical shock.
5. This dynamic load specification is subject to t he manner in which the board is suppo rted. Adequate mechanica l support
should be provided to minimize board flexure during mechanical shock and vibration. AMD can provide example
mechanical designs that exceed the dynamic specification.
6. AMD recommends that mechanical shock be used as preconditioning prior to temperature cycling during system
qualification.
7. The sur face mount assembly and boa rd flatness affect the tolerance in height and parallelism of the back of t he Mobi le
AMD-K6-2 die relative to the board on which the CBGA is mounted.
8. The root sum square (RSS) specified tolerance acknowledges that the case of all the minimum or all the maximum
tolerances occurring simultaneously is very remote. The R SS preserves the confidence le vel at which the initial tolerances
are specified. For exampl e, if the component tolerances are estimated at 99.9 9% confi dence, the RS S combination is at
99.99% confidence.
88 Package Specifications Chapter 9
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Chapter 10 Pin Description Diagrams 89
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
10 Pin Description Diagrams
10.1 360-Pin CBGA Pin Diagrams
Figure 25. Mobile AMD-K6®-2 Processor Ball-Side View (CBGA)
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
WVUTRPNMLKJHGFEDCBA
W
VUTRPNMLKJHGFEDCBA
NMI
BE1#
A20INIT
SCYC
A19 A18 A17
A16 A15 A11
A14 A12
A13
A8
A9
A10
A5
CLK
EADS#
BE7#
BE4#
BF0
IGNNE#
BE6#
FLUSH#
INTRBE2#
SMI#
BOFF#
ADS#
AHOLD
AP
APCHK#
A4 A30 A24
STPCLK#
A27
A23
A25
A20M#
BRDY#
BREQ CACHE#
A21
DP7
D63
D61
D62
D60
D58
D59
D55
D56
D52
D53
D54
D49
D50
D51
D47
D48
D44
D45 D43
D41
D42
D46
D39
D40
D36D37
D38
D33
D34
D35
D31
D32
D28
D29D30
D25
D26
D27
D23
TDO#
DP6 DP5
DP4
DP3
DP2
A22
EWBE# FERR#
A28
RESET
HLDA
A26
A6 A29
INV KEN#
M/IO#
NA#
A3
BF2
PCHK#
HIT#
A7
A31
SMIACT#
BE5#
D/C#
W/R#
TRST#
WB/WT#
Signal Pin
VSS
VCC3
VCC2
No Connects
PCD
BRDYC#
D15
D17
D20
D12
LOCK# D57
D9
D7
D4
DP1
D18
D21
D13
D10
DP0
D5
D3
D24
D22
D19
D16
D14
D11
D8
D6
D2
D1
HITM#
PWT
BE0#
ADSC#
BE3#
TCK
TMS
HOLD BF1
D0
TDI
90 Pin Description Diagrams C hapter 10
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Figure 26. Mobile AMD-K6®-2 Processor Top-Side View (CBGA)
W
V
U
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R
P
N
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F
E
D
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A
19 18 17 16 15 14 13 12 11 10 987654321
19 18 17 16 15 14 13 12 11 10 987654321
A3
A4
A5
A6
A7
A10 A9 A8
A13 A12 A11
A14 A15
A16
A17
A18
A19
A20
A21
A22
A23A24
A25
A26
A27
A28A29A30
A31
A20M#
ADS#
ADSC#
AHOLD
AP
APCHK#
BE0#
BE1# BE2# BE3#
BE4#
BE5#
BE6#
BE7#
BF0
BF1
BOFF#
BRDY#
BRDYC#
BREQ
CACHE#
CLK
D0
D1 D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42 D43
D44
D45
D46
D47
D48
D49D50
D51
D52
D53
D54
D55
D56
D57
D58D59
D60
D61
D62
D63
D/C#
DP0 DP1 DP2 DP3 DP4
DP5
DP6
DP7
EADS# EWBE#
FERR#
FLUSH#
HIT#
HITM#
HLDA
HOLD
IGNNE#
INIT INTR
INV
KEN#
LOCK#
M/IO#
NA#
NMI
PCD
PCHK#
PWT
RESET
SCYC
SMI# SMIACT#
STPCLK#
TCK
TDI
TDO
TMS
TRST#
W/R#
WB/WT#
Signal Pin
VSS
VCC3
VCC2
No Connects
BF2
Chapter 10 Pin Description Diagrams 91
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Preliminary Information
10.2 321-Pin CPGA Pin Diagrams
Figure 27. Mobile AMD-K6®-2 Processor Bottom-Side View (CPGA)
92 Pin Description Diagrams C hapter 10
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Figure 28. Mobile AMD-K6®-2 Processor Top-Side View (CPGA)
Chapter 10 Pin Description Diagrams 93
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
10.3 Pin Designations by Functional Grouping
Pin
Name CPGA
Pin No. CBGA
Pin No. Pin
Name CPGA
Pin No. CBGA
Pin No. Pin
Name CPGA
Pin No. CBGA
Pin No. Pin
Name CPGA
Pin No. CBGA
Pin No.
Address Data Control Test
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
AL-35
AM-34
AK-32
AN-33
AL-33
AM-32
AK-30
AN-31
AL-31
AL-29
AK-28
AL-27
AK-26
AL-25
AK-24
AL-23
AK-22
AL-21
AF-34
AH-36
AE-33
AG-35
AJ-35
AH-34
AG-33
AK-36
AK-34
AM-36
AJ-33
P18
P19
R17
R18
R19
T17
T18
T19
U17
U18
U19
V18
V17
W17
U16
V16
W16
U15
K19
L17
L18
L19
M17
M18
M19
N17
N18
N19
P17
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
K-34
G-35
J-35
G-33
F-36
F-34
E-35
E-33
D-34
C-37
C-35
B-36
D-32
B-34
C-33
A-35
B-32
C-31
A-33
D-28
B-30
C-29
A-31
D-26
C-27
C-23
D-24
C-21
D-22
C-19
D-20
C-17
C-15
D-16
C-13
D-14
C-11
D-12
C-09
D-10
D-08
A-05
E-09
B-04
D-06
C-05
E-07
C-03
D-04
E-05
D-02
F-04
E-03
G-05
E-01
G-03
H-04
J-03
J-05
K-04
L-05
L-03
M-04
N-03
D17
C19
C18
B18
A17
B17
C17
A16
C16
A15
B15
C15
A14
B14
C14
A13
C13
A12
B12
C12
A11
B11
C11
A10
C10
A09
B09
C09
A08
B08
C08
A07
C07
A06
B06
C06
A05
B05
C05
A04
C04
A03
B03
B02
C01
C02
C03
D01
D03
E01
E02
E03
F01
F02
F03
G01
G03
H01
H02
H03
J01
J02
J03
K01
A20M#
ADS#
ADSC#
AHOLD
APCHK#
BE0#
BE1#
BE2#
BE3#
BE4#
BE5#
BE6#
BE7#
BF0
BF1
BF2
BOFF#
BRDY#
BRDYC#
BREQ
CACHE#
CLK
D/C#
EADS#
EWBE#
FERR#
FLUSH#
HIT#
HITM#
HLDA
HOLD
IGNNE#
INIT
INTR
INV
KEN#
LOCK#
M/IO#
NA#
NMI
PCD
PCHK#
PWT
RESET
SCYC
SMI#
SMIACT#
STPCLK#
VCC2DET
VCC2H/L#
W/R#
WB/WT#
AK-08
AJ-05
AM-02
V-04
AE-05
AL-09
AK-10
AL-11
AK-12
AL-13
AK-14
AL-15
AK-16
Y-33
X-34
W-35
Z-04
X-04
Y-03
AJ-01
U-03
AK-18
AK-04
AM-04
W-03
Q-05
AN-07
AK-06
AL-05
AJ-03
AB-04
AA-35
AA-33
AD-34
U-05
W-05
AH-04
T-04
Y-05
AC-33
AG-05
AF-04
AL-03
AK-20
AL-17
AB-34
AG-03
V-34
AL-01
AN-05
AM-06
AA-05
V09
P03
W07
H19
R03
W09
W14
W13
W06
W11
V10
W12
V11
U12
H17
G17
J18
K03
M01
W03
T03
W10
W04
U11
U03
L03
U13
V08
U10
P02
J17
V12
V15
V13
T02
M02
P01
N01
T01
V14
U07
M03
V07
H18
W15
U14
U01
K18
n/a
n/a
W05
N03
TCK
TDI
TDO
TMS
TRST#
AP
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
M-34
N-35
N-33
P-34
Q-33
AK-02
D-36
D-30
C-25
D-18
C-07
F-06
F-02
N-05
D18
E17
D19
E18
E19
N02
B16
B13
B10
B07
B04
D02
G02
K02
Parity
94 Pin Description Diagrams C hapter 10
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
CPGA Pin
No. CBGA P in
No. CPGA Pin
No. CBGA Pin
No. CPGA Pin
No. CBGA Pin
No. CPGA Pin No. CBGA Pin No. CPGA Pin
No.
NC VCC2 VCC3 VSS INC
A-37
E-17
E-25
R-34
S-33
S-35
W-33
AJ-15
AJ-23
AL-19
AN-35
A02
A18
A19
B01
B19
F17
F18
F19
G18
G19
J19
L01
L02
R01
R02
U02
U04
U05
U06
U08
U09
V01
V02
V03
V04
V05
V06
V19
W01
W02
W08
W18
W19
A-07
A-09
A-11
A-13
A-15
A-17
B-02
E-15
G-01
J-01
L-01
N-01
Q-01
S-01
U-01
W-01
Y-01
AA-01
AC-01
AE-01
AG-01
AJ-11
AN-09
AN-11
AN-13
AN-15
AN-17
AN-19
F04
F05
F06
F07
G06
G07
H08
H09
H12
H13
J04
J05
J08
J09
J10
J11
J12
J13
K04
K05
K06
K07
K10
K11
L04
L05
L08
L09
L10
L11
L12
L13
M08
M09
M12
M13
N06
N07
P04
P05
P06
P07
A-19
A-21
A-23
A-25
A-27
A-29
E-21
E-27
E-37
G-37
J-37
L-33
L-37
N-37
Q-37
S-37
T-34
U-33
U-37
W-37
Y-37
AA-37
AC-37
AE-37
AG-37
AJ-19
AJ-29
AN-21
AN-23
AN-25
AN-27
AN-29
D07
D08
D09
D12
D13
E07
E08
E09
E12
E13
F10
F11
F14
G10
G11
G14
G15
G16
H14
H15
H16
K17
M14
M15
M16
N10
N11
N14
N15
N16
P10
P11
P14
R07
R08
R09
R12
R13
T07
T08
T09
T12
T13
A-03 AM-20
B-06 AM-22
B-08 AM-24
B-10 AM-26
B-12 AM-28
B-14 AM-30
B-16 AN-37
B-18
B-20
B-22
B-24
B-26
B-28
E-11
E-13
E-19
E-23
E-29
E-31
H-02
H-36
K-02
K-36
M-02
M-36
P-02
P-36
R-02
R-36
T-02
T-36
U-35
V-02
V-36
X-02
X-36
Z-02
Z-36
AB-02
AB-36
AD-02
AD-36
AF-02
AF-36
AH-02
AJ-07
AJ-09
AJ-13
AJ-17
AJ-21
AJ-25
AJ-27
AJ-31
AJ-37
AL-37
AM-08
AM-10
AM-12
AM-14
AM-16
AM-18
D04 N12
D05 N13
D06 P08
D10 P09
D11 P12
D14 P13
D15 P15
D16 P16
E04 R04
E05 R05
E06 R06
E10 R10
E11 R11
E14 R14
E15 R15
E16 R16
F08 T04
F09 T05
F12 T06
F13 T10
F15 T11
F16 T14
G04 T15
G05 T16
G08
G09
G12
G13
H04
H05
H06
H07
H10
H11
J06
J07
J14
J15
J16
K08
K09
K12
K13
K14
K15
K16
L06
L07
L14
L15
L16
M04
M05
M06
M07
M10
M11
N04
N05
N08
N09
C-01
H-34
Y-35
Z-34
AC-35
AL-07
AN-01
AN-03
RSVD
J-33
L-35
P-04
Q-03
Q-35
R-04
S-03
S-05
AA-03
AC-03
AC-05
AD-04
AE-03
AE-35
KEY
AH-32
Chapter 11 Ordering Information 95
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Preliminary Information
11 Ordering Information
Standard Products
AMD standard mobile products are available in several operating ranges. The
ordering part number (OPN) is formed by a combination of the elements below.
Table 31. Valid Ordering Part Number Combinations
OPN Package Type Operating Voltage Case Temperature
AMD-K6-2/333ANZ
AMD-K6-2/333BNZ 321-pin CPGA
360-pin CBGA 1.7V–1.9V (Core)
3.135V–3.6V (I/O) 0°C–85°C (C PGA)
0°C–85°C (CBGA)
AMD-K6-2/300ANZ
AMD-K6-2/300BNZ 321-pin CPGA
360-pin CBGA 1.7V–1.9V (Core)
3.135V–3.6V (I/O) 0°C–85°C (C PGA)
0°C–85°C (CBGA)
AMD-K6-2/266ANZ
AMD-K6-2/266BNZ 321-pin CPGA
360-pin CBGA 1.7V–1.9V (Core)
3.135V–3.6V (I/O) 0°C–85°C (C PGA)
0°C–85°C (CBGA)
Note: This table lists configurations planned to be supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific valid combinations and to check on
newly-released combinations.
AAMD-K6-2
Package Type
Family/Core
A = 321-pin CPGA
B = 360-pin CBGA
AMD-K6-2
Case Temperature
Z = 0°C–85°C
/333
Performance Rating
/333
/300
/266
Operating Voltage
N = 1.7 V–1.9 V (Cor e) / 3.135 V–3.6 V (I /O)
N Z
96 Ordering Information Chapter 11
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
Part 2 Mobile AMD-K6®-2 Processor Data Sheet 97
Part Two
Mobile AMD-K6 -2-P
Proc essor
The Mobile AMD-K6®-2 Processor Data Sheet is a supplement to the AMD-K6®-2
Processor Data Sheet, order# 21850. When combin ed, the two data sheet s provide the
complete specification of the Mobile AMD-K6-2 and Mobile AMD-K6-2-P processors.
The Mobile AMD-K6®-2 Processor Data Sheet is divided in to two parts. Part Two
(c hapte r s 12 –15) contai ns ad ditional in f orma tion spe cif ic to the Mobil e AMD-K 6-2 -P
Processor.
®
98 Mobile AMD-K6®-2 Processor Data Sheet Part 2
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Preliminary Information
Chapter 12 Mobile AMD-K6®-2-P Processor 99
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
12 Mobile AMD-K6®-2-P Processor
■Advanced 6-Issue RISC86® Superscalar Microarchitecture
◆Ten parallel specialized execution units
◆Multiple sophisticated x86-to -RISC86 instruction decoders
◆Advanced two-level branch prediction
◆Speculative execution
◆Out-of-order ex ecution
◆Register renaming and data forwarding
◆Issues up to six RISC86 instructions per clock
■Large On-Chip Split 64-Kbyte Level-One (L1) Cache
◆32-Kbyte instruction cache with additional predecode cache
◆32-Kbyte writeback dual-por ted data cache
◆MESI protocol support
■High-Performance IEEE 754-Compatible and 854-Compatibl e Floa ting-Point Unit
■Superscalar MM X™ unit supports industry-standard MMX instructions
■3DNow!™ Technology for high-performance multimedia and 3D graphics
capabilities
■Compatible with Super7™ 10 0-M H z frontsi de bus or So ck e t 7 66- MHz notebook
design
■Socket 7-Compatible Ceramic Pin Grid Array (CPGA) Package
■Industry-Standard System Management Mode (SMM)
■IEEE 1149.1 Boundary Scan
■x86 Binary Software Compatibility
■Low Voltage 0.25-Micron Process Technology
T he Mobile AMD-K6-2-P processor is a high-performance CPU optimized for note book
PC design s. The Mobile AMD-K6-2-P processor is a natu ral extensi on o f t he Mob ile
AMD-K6-2 processor and incorp orates the same leading-edge features, including the
innova tive and efficient RIS C86 microarchitecture, a large 64-Kbyte level-one cache
(32-Kbyte dual-ported dat a cache, 32-Kbyte instruction cache with prede cod e data),
and a powerful IEEE 754-compatible and 854-compatible floating-point execution
unit. In addition, the Mobile AMD-K6-2-P incorpora tes a number of new features,
including a supers calar MMX unit, support for a 100-MHz frontside bus, and AMD’s
innovative 3DNow! technology for high-perfo rmance mu ltimedia and 3D graphics
operation.
100 Mobile AMD-K6 ®-2-P Processor Chapter 12
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
The Mobile AMD-K6-2-P processor includes several key features for the mobile
market. The processor is implemented using an AMD-developed, state-of-the-art low
power 0.25-micron process technology. This process technology features a split-plane
design that allows the processor core to operate at a lower voltage while the I/O
portion operates at the industry-standard 3.3V level. In addition, the Mobile
AMD-K6-2-P processor includes the complete industry-standard System Management
Mode (SMM), whic h is critical to system r esour ce and pow er management. The Mobile
AMD-K6-2-P processor also features the industry -standard Stop-Clock (STPCLK#)
control circuitry and the Halt instruction, both requi red for implementing the AC PI
power management specification. The Mobile AMD-K6-2 -P processor is offered in a
standar d Soc k et 7-compatible, 321-pin Cer a mic Pin Grid Arr a y (CPGA) pac kage.
The Mobile AMD-K6-2-P processor’s RISC86 microarchitecture is a decoupled
decode/execution superscalar design that implements state-of-the-art design
techniques to achieve leading-edge performance. Advanced design techniques
implemented in the M obile AMD-K6-2-P processo r include multiple x86 instruction
decode, single-clock internal RISC operations, ten execution units that support
super scalar oper ation, out-of-order exec ution, data forwar ding, speculati v e execution,
and register renaming. In addition, the processor supports the industry’s most
advanced branch prediction logic by implementing an 8192-entry branch history
table, the industry’s only branch target cache, and a return address stack, which
combine to de li v er bet ter than a 95% pr e diction r ate . T hese design te c hniques ena ble
the Mobile AMD-K6-2-P to issue, ex ecute, and retire multiple x86 instructions per
clock, resulting in excellent scaleable performance.
AMD’s 3DNow! technolog y is an instruction set e x tension to x86, that includes 21 new
instructions to improve 3D graphics operations and other single precision floating-
point compute intensive operations. AMD has already shipped millions of AMD-K6-2
processors with 3DNow! technology for desktop PCs, revolutionizing the 3D
experience with up to four times the peak floating-point performance of prev ious
generation solutions. AMD is now bringing this advanced capability to notebook
computing, workin g in co njunction with advanced mobile 3D g raphic contro llers to
reach new levels of realism in mobile computing. With support f rom Microsoft ® and
the x86 software developer community, a new generation of visually compelling
applications is coming to market that support the 3DNow! technology.
The Mobile AMD-K6-2-P processor remains pin compatible with existing Socket 7
notebook solu tions, however for maximum system performance, the processor works
optimally in newer Super7 designs that incorporate advanced features such as
support fo r the 100-MHz frontside bus and AGP graphics.
T he Mobile AMD-K6-2-P pr ocessor has under gone extensi ve testing and is compatible
with Windows® 98, Windows NT® and other leadi ng operating s ystems. The Mo bile
AMD-K6-2-P processor is also compatible with more than 60,000 software
applications, includin g the latest 3DNow! technology and MMX technology software.
As the world’s second-largest supplier of processors for the Windows environment,
Chapter 12 Mobile AMD-K6®-2-P Processor 101
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
AMD has shipped more than 50 million Microsoft Windows compatible processors in
the last five years.
The Mobi le AMD-K6-2-P processor is th e next generation in a long lin e of M icrosof t
Windows compatible processors from AMD. With its combination of state-of-the-art
features, leading-edge performance, high-performance multimedia engine, x86
compatibility, and low-co st infrastructure , the Mobile AMD-K6-2-P pro cessor delivers
unparalleled price/performance for a new genera tion of notebook PCs.
12.1 Super7™ Platform Initiative
AMD and its industry partners are investing in the future of Socket 7 with the new
Super7 platform initia tive. The goal of the i nitiative is to maintain the competitive
vitality of the Socket 7 infrastructure through a series of planned enhancements,
including the development of an industry-standard 100-MHz processor bus proto col.
In addi tion to the 100-MHz processor bus protocol, the Super7 initiative includes the
introduction of chipsets that support the AGP specification, and support for a
backside L2 cache and front side L3 ca che.
Super7™ Platform Enhancements:
■100-MHz processor bus—The Mobile AMD-K6-2-P processor supports a 100-MHz,
800 Mbyte/second frontside bus to provide a high-speed interface to Super7
platform-based chipsets. The 100-MHz interface to the frontside Level 2 (L2)
cache and main system memory speeds up access to the frontside cache and main
memory by 50 percent over the 66-MHz Socket 7 interface—resulting in a
significant increase of 10% in overall system performance.
■Accelerated graphics port support—AGP improves the performance of mid-range
PCs that have small amounts of video memory on the graphics card. The
industry-standard AGP specification enables a 133-MHz graphics interface and
will scale to even higher levels of performance.
■Support for backside L2 and frontside L3 cache—The Super7 platform has the
‘headroom’ to support higher-performance AMD-K6 processors, with clock speeds
scaling to 500 MHz and beyond. Future versions of the AMD-K6 processor are
planned to feature a full-speed, on-chip backsi de 256-Kbyte L2 cache design ed to
deliver new levels of system performance to notebook PC systems. These versions
of the processor are also planned to support an optional 100-MHz frontside L3
cache for even higher-performance system configurat ions.
102 Mobile AMD-K6 ®-2-P Processor Chapter 12
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Preliminary Information
Chapter 13 Electrical Data 103
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Preliminary Information
13 Electrical Data
13.1 Operating Ranges
The Mobile AMD-K6-2-P processor is designed to provide
functional o per atio n if the voltage and te mper atur e par amet er s
ar e within the limits defined in Table 32.
Table 32. Operating Ranges
Parameter Minimum Typical Maximum Comments
VCC2
1.9 V 2.0 V 2.1 V Note 1, 2
2.0 V 2.1 V 2.2 V Note 1, 3
2.1 V 2.2 V 2.3 V Note 1, 4
VCC3 3.135 V 3.3 V 3.6 V Note 1
TCASE 0°C 80°C
Note:
1. VCC2 and VCC3 are referenced from VSS.
2. VCC2 specification for 2.0 V component.
3. VCC2 specification for 2.1 V component.
4. VCC2 specification for 2.2 V component.
104 Electrical Data Chapter 13
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
13.2 Absolute Ratings
The Mobile AMD-K6-2-P processor is not designed to be
operated beyond the operating ranges listed in Table 32.
Exposure to conditions out side these operating ranges for
extended periods of time can affect long-term reliability.
Permanent damage can occur if the absolute ratings listed in
Table 33 ar e exceeded.
Table 33. Absolute Ratings
Parameter Minimum Maximum Comments
VCC2 –0.5 V 2.4 V Note 1
–0.5 V 2.6 V Note 2
VCC3 –0.5 V 3.6 V
VPIN –0.5 V Vcc3 + 0.5 V and < 4.0 V Note 3
TCASE (under bias) –65°C +110°C
TSTORAGE –65°C +150°C
Note:
1. VCC2 specification for 2.0 V and 2.1 V components.
2. VCC2 specification for 2.2 V components.
3. VPIN (the voltage on any I/O pin) must not be greater than 0.5 V above the voltage being
applied to VCC3. In addition, the VPIN voltage must never exceed 4.0 V.
Chapter 13 Electrical Data 105
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Preliminary Information
13.3 DC Char acteristics
T he DC char acteristics of the Mobile AMD-K6-2-P pr ocessor are
sho wn in Table 34.
Table 34. DC Characteristics
Symbol Parameter Description Preliminary Data Comments
Min Max
VIL Input Low Voltage –0.3 V +0.8 V
VIH Input High Voltage 2.0 V VCC3+0.3V Note 1
VOL Output Low Vo ltage 0.4 V IOL = 4.0-mA load
VOH Output High Voltage 2.4 V IOH = 3.0-mA l oad
ICC2
2.0 V Power Sup ply Current 8.0 0 A 400 MHz, Note 2,9,11
475 M H z , N o t e 2, 10
2.1 V Power Supply Current 8.50 A 433 MHz, Note 3,12
450 MHz, Note 3,11
10.50 A 500 M Hz, Note 3,11
2.2 V Power Sup ply Current 8.0 0 A
350 M Hz, N ote 4,11
366 MHz, Note 4,9
380 MHz, Note 4,10
400 MHz, Note 4,9,11
Notes:
1. VCC3 refers to the voltage being applied to VCC3 during functional operation.
2. VCC2 = 2.1 V — The maximum power supply current must be taken into account when designing a power supply.
3. VCC2 = 2.2 V — The maximum power supply current must be taken into account when designing a power supply.
4. VCC2 = 2.3 V — The maximum power supply current must be taken into account when designing a power supply.
5. VCC3 = 3.6 V — The maximum power supply current must be taken into account when designing a power supply.
6. Refers to inputs and I/O without an internal pullup resistor and 0 ≤ VIN ≤ VCC3.
7. Refers to inputs with an internal pullup and VIL = 0.4 V.
8. Refers to inputs with an internal pulldown and VIH = 2.4 V.
9. This specification applies to components using a CLK frequency of 66 MHz.
10. This specification applies to components using a CLK frequency of 95 MHz.
11. This specification applies to components using a CLK frequency of 100 MHz.
12. This specification applies to components using a CLK frequency of 96.2 MHz.
106 Electrical Data Chapter 13
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
ICC3 3.3 V Po wer Supply Current
0.60 A 350 M Hz, Note 5,11
0.60 A 366 MHz, Note 5,9
0.61 A 380 M Hz, No te 5,10
0.62 A 400 MHz, Note 5,9,11
0.64 A 433 M Hz, N ote 5,12
0.66 A 450 M Hz, N ote 5,11
0.67 A 475 M Hz, Note 5,10
0.69 A 500 M Hz, Note 5,11
ILI Input Leakage Current ±15 µA Note 6
ILO Output Leakage Current ±15 µA Note 6
IIL Input Leakage Current Bias with Pullup –400 µA Note 7
IIH Input Leakage Current Bias with Pulldown 200 µA Note 8
CIN Input Capacitance 10 pF
COUT Output Capacitance 15 pF
COUT I/O Capacitance 20 pF
CCLK CLK Capacitance 10 pF
CTIN Test Input Capacitance (TDI, TMS, TRST#) 10 pF
CTOUT Test Output Capacitance (TDO) 15 pF
CTCK TCK Capacitance 10 pF
Table 34. DC Characteristics (continued)
Symbol Parameter Description Preliminary Data Comments
Min Max
Notes:
1. VCC3 refers to the voltage being applied to VCC3 during functional operation.
2. VCC2 = 2.1 V — The maximum power supply current must be taken into account when designing a power supply.
3. VCC2 = 2.2 V — The maximum power supply current must be taken into account when designing a power supply.
4. VCC2 = 2.3 V — The maximum power supply current must be taken into account when designing a power supply.
5. VCC3 = 3.6 V — The maximum power supply current must be taken into account when designing a power supply.
6. Refers to inputs and I/O without an internal pullup resistor and 0 ≤ VIN ≤ VCC3.
7. Refers to inputs with an internal pullup and VIL = 0.4 V.
8. Refers to inputs with an internal pulldown and VIH = 2.4 V.
9. This specification applies to components using a CLK frequency of 66 MHz.
10. This specification applies to components using a CLK frequency of 95 MHz.
11. This specification applies to components using a CLK frequency of 100 MHz.
12. This specification applies to components using a CLK frequency of 96.2 MHz.
Chapter 13 Electrical Data 107
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
13.4 Power Dissipation
Table 35 contains the typical and maximum powe r dissipation
of the 2.2 V Mobile AMD-K6-2-P processor during normal and
r educed po w e r states .
Table 35. Power Dissipation (2.2 V Components)
Clock Control State 350 MHz7366 MHz5380 MHz6400 MHz8Comments
Design Power 16.00 W 16.00 W Note 1
Application Power 12.60 W 12.60 W Note 2
Stop Grant / Halt (Maximum) 2.56 W 3.00 W Note 3
Stop Clock (Maximum) 2.25 W 2.70 W Note 4
Notes:
1. Design Power represents the maximum sustained power dissipated while executing software or instruction sequences under
normal system operation with VCC 2 = 2.2 V and VCC3 = 3.3 V . Thermal solutions must use thermal feedback to limit the processor’s
peak power. Specified through characterization.
2. Application Power represents the average power dissipated while executing software or instruction sequences under normal
system operation with VCC2 = 2.2 V and VCC3 = 3.3 V.
3. The CLK signal and the internal PLL are still running but most internal clocking has stopped.
4. The CLK signal, the internal PLL, and all internal clocking has stopped.
5. This specification applies to components using a CLK frequency of 66 MHz.
6. This specification applies to components using a CLK frequency of 95 MHz.
7. This specification applies to components using a CLK frequency of 100 MHz.
8. This specification applies to components using a CLK frequency of 66 MHz or 100 MHz.
108 Electrical Data Chapter 13
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Table 36 contains the typical and maximum powe r dissipation
of the 2.0V and 2.1V Mobile AMD-K6-2-P processors during
normal and reduced po w er states.
Table 36. Power Dissipation (2.0 V and 2.1 V Components)
Clock Control St ate 400 MHz5,7 433 MHz8450 MHz7475 MHz6500 MH z7Comments
Design Power 16.00 W 20.00 W Note 1
Application Power 12.60 W 15.80 W Note 2
Stop Grant / Halt (Maximum) 2.56 W 2.56 W Note 3
Stop Clock (Maximum) 2.25 W 2.25 W Note 4
Notes:
1. Design Power represents the maximum sustained power dissipated while executing publicly-available software or instruction
sequences under normal system operation with VCC2 = 2.0 V (for 2.0 V components) or VCC2 = 2.1 V (for 2.1 V components) and
VCC3 = 3.3 V . Thermal solutions must use thermal feedback to limit the processor’s peak power . Specified through characterization.
2. Application Power represents the average power dissipated while executing publicly-available soft ware or instruction sequences
under normal system operation with VCC2 = 2.0 V (for 2.0 V components) or VCC2 = 2. 1 V (for 2.1 V components) and VCC3 = 3. 3 V .
3. The CLK signal and the internal PLL are still running but most internal clocking has stopped.
4. The CLK signal, the internal PLL, and all internal clocking has stopped.
5. This specification applies to components using a CLK frequency of 66 MHz.
6. This specification applies to components using a CLK frequency of 95 MHz.
7. This specification applies to components using a CLK frequency of 100 MHz.
8. This specification applies to components using a CLK frequency of 96.2 MHz.
Chapter 13 Electrical Data 109
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Preliminary Information
13.5 Power and Gr ounding
Power Connections T he Mobile AMD -K6-2-P pr oc esso r is a dual voltage de vice. Tw o
separate supply voltages are required: VCC2 and VCC3. V CC2
provi des the core voltage for the Mobile AMD-K6-2-P processor
and VCC3 prov ides the I/O voltage. See “Elect rical Data” on
page 103 f or the v alue and r ang e of VCC2 and VCC3.
There are 28 VCC2, 32 VCC3, and 68 VSS pins on the Mobile
AMD-K6-2-P processor. (See “Pin Description Diagrams” on
page 89 for all power and ground pin designations.) The large
number of power and ground pins are provided to ensure that
the proc essor and pack age maintain a clean and stable power
distribution netw ork.
For pr ope r operation and functionality, all VCC2, VCC3, and VSS
pins must be connected to the appropriate planes in the circuit
board. The powe r planes have be en arra nged in a pa ttern to
simplify routing and minimiz e crosstalk on the circuit board.
Th e isolati on regi on between two voltage plan es must be a t
least 0.254mm if they ar e in the same la yer of the cir cuit boar d.
(See Figure 29 on page 110.) In order to maintain
low-impedance current sink and reference, the ground plane
m ust nev e r be split.
Althoug h t he Mobi le A MD-K6-2-P processor has two separat e
supply voltages, there are no special power sequencing
requirements. The best procedure is to minimize the time
betw een which VCC2 and VCC3 ar e eithe r both on or both off .
110 Electrical Data Chapter 13
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Figure 29. Suggested Component Placement
Decoupling
Recommendations In addition to the isolation region mentioned in “Power
Connections” on page 109, adequate decoupling cap aci tance is
required between the two system power planes and the ground
plane to minimize ringing and to pr ovide a lo w-impedance path
for return currents. Suggested decoupling capacitor placement
is shown in Figur e 29.
Surface mounted capacitors should be used as close as possible
to the processor to minimize resistance and inductance in the
lead lengths while maintaining minimal height. For
r ecommendat ions r egar ding the v alue, quantity, and location of
the capacitors illustr a ted in Figur e 29 , see the Mobile AMD-K6®
Processor P ower Supply Application Note, or der # 22495.
VCC2 (Core) PlaneVCC3 (I/O) Plane
0.254mm (min.) for
isolation region
C1
CC5
CC3
C2
+
+
+
+
C5
C6
C7
C8
C9
C10
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
CC4
+
CC6
C14
C15
C16
CC9
CC7 CC10CC8
Chapter 13 Electrical Data 111
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Preliminary Information
Pin Connection
Requirements For proper operation, the following requirements for signal pin
connections must be met:
■Do not drive address and data signals into large capacitive
loads at high frequencies. If necessary, use buffer chips to
dri v e lar ge capaciti v e loads.
■Lea v e all NC (no-connect) pins unconnected.
■Unused inputs should alwa ys be connected to an appropriate
signal le v e l.
•Active Low inputs that are not being used should be
connected to VCC3 thr ough a 20k-Ohm pullup r esistor.
•Active High inputs that are not being used should be
connected to GND thr ough a pulldo wn r esistor.
■Reser v ed signa ls can be tr eated in one of the follo wing w ays:
•As no-connect (NC) pins, in whic h case these pins ar e left
unconnected
•As pins connected to the system logic as defined by the
industr y-standar d Super7 and Soc k et 7 interface
•An y combination of NC and Soc k et 7 pins
■K eep tr ace l engths to a mi nim um.
112 Electrical Data Chapter 13
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Chapter 14 Thermal Design 113
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
14 Thermal Design
14.1 Package Thermal Specifications
T he Mobile AMD-K6-2-P processor oper ating specifications call
for the case temperature (TC) to be in the range of 0°C to 80°C.
The ambient temperature (TA) is no t specified as long a s the
case temper ature is not violated. The case temperatur e m ust be
measured on the top center of the package. Table 37 shows the
Mobile AMD-K6-2 -P pr ocessor therma l specifications.
Figure 30 on page 113 shows the thermal model of a processor
with a passive thermal solution. The case-to-ambient
temperature (TCA) can be calculated from the following
equation:
TCA = PMAX • θCA
= PMAX • ( θIF + θSA)
Where:
PMAX = Maximum Power Consumption
θCA = Case-to-Ambient Thermal Resistance
θIF = Interface Material Thermal Resistance
θSA = Sink-to-Ambient Thermal Resistance
Figure 30. Thermal Model
Table 37. Package Thermal Specifications
TC
Case Temperature
Maximum Design Power
2.0 V, 2.1 V, and 2.2 V Components
350 MHz 366 MHz 380 MHz 400 MHz 433 MHz 450 MHz 475 MHz 500 MHz
0°C – 80°C 16.00 W 20.00 W
Heat Exchange Device
Temperature
(Ambient)
Case
Sink
TCA
Thermal
θSA θCA
θIF
(°C/W)
Resistance
114 Thermal Design Chapter 14
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Figure 31 illustrates the case-to-ambient temperature (TCA) in
relation to the power consumption (X-axis) and the thermal
resistance (Y-axis). If the power consumption and case
temperature are known, the thermal resistance (θCA)
r equir ement can be calculated f or a gi v en ambient temper ature
(TA) va lue.
Figure 31. Power Consumption versus Thermal Resistance
The thermal resistance of a heatsink is determined by the heat
dissipation surface area, the material and shape of the
heatsink, and the airflow volume across the heatsink. In
general, the larger the surface area the lower t he thermal
resistance.
The re quired thermal resistance of a heatsink ( θSA) can be
calculat ed using the f ollowing exa mple:
If:
TC = 80°C
TA = 55°C
PMAX = 20.00W at 500MHz
0.0
1.0
2.0
3.0
4.0
5.0
6.0
6 W 9 W 12 W 15 W 18 W
Power Consum pti on (Watts)
Thermal Resistance (°C/W)
30° C
25° C
20° C
15° C
T
CA
TCA = TC - TA
Chapter 14 Thermal Design 115
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
Then:
Thermal grease is recommended as interface material because
it provides the lowest thermal resistance (approx. 0.20°C/W).
Th e required thermal resistance (θSA) of the heat sink in this
example is calculated as follo ws:
θSA = θCA – θIF = 1.25 – 0.20 = 1.05 (°C/W)
Heat Dissipation Path Figure 32 illustrates the heat dissipation path of the processor.
Due to the lower thermal resistance between the processor die
junction and case, most of the heat generated by the processor
is transferred from the top surface of the case. The small
amount of heat gener ated from the bottom side of the processor
where the processor socket blocks the convection can be safely
ignored.
Figure 32. Processor’s Heat Dissipation Path
Measuring Case
Temperature The processor case temperature is measured to ensure that the
thermal solution meets the processor’s operational
specification. This temperature should be measured on the top
center of the package where most of the heat is dissipated.
Figure 33 shows the c orrect locat ion for measuring the case
temperature. If a heatsink is installed while measuring, the
thermocouple must be installed into the heatsink via a small
hole drilled through the heatsink base (for example, 1/16 of an
inch). The thermocouple is then attached to the base of the
heatsink and the small hole filled using thermal epoxy, allowing
θCA TCTA
–
PMAX
-------------------
≤25°C
20.0W
------------------ 1.25 °CW
⁄()
==
Thin Lid
Case temperature
Ambient Temper ature
116 Thermal Design Chapter 14
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
the tip of the thermocouple to touch the top of the processor
case.
Figure 33. Measuring Case Temperature
For mor e information on thermal design consider ations, see the
AMD-K6® Thermal Solution Design Application Note, orde r#
21085.
Thermocouple
Thermally Conductive Epoxy
Chapter 15 Ordering Information 117
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
15 Ordering Information
Standard AMD-K6-2-P Pro ducts
AMD mobile performance products are available in several operating ranges. The
ordering part number (OPN) is formed by a combination of the elements below.
Table 38. Valid Ordering Part Number Combinations
OPN Package Type Operating Voltage Case Temperature
AMD-K6-2/500ADK 321-pin CPGA 2.0V–2.2V (Core)
3.135V–3.6V (I/O) 0°C–80°C (CPGA)
AMD-K6-2/475ACK 321-pin CPGA 1.9V–2.1V (Core)
3.135V–3.6V (I/O) 0°C–80°C (CPGA)
AMD-K6-2/450ADK 321-pin CPGA 2.0V–2.2V (Core)
3.135V–3.6V (I/O) 0°C–80°C (CPGA)
Note: This table lists configurations planned to be supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific valid combinations and to check on
newly-released combinations.
AAMD-K6-2
Package Type
Family/Core
A = 321-pin CPGA
AMD-K6-2
Case Temperature
K = 0°C–80°C
/500
Performance Rating
/500
/400
Operating Voltage
C = 1.9 V–2.1 V (Core) / 3.135 V–3.6 V (I/O)
D = 2.0 V–2.2 V (Cor e) / 3.135 V–3.6 V (I /O)
F = 2.1 V–2.3 V (Core) / 3.135 V–3.6 V (I/O)
D K
/475
/380 /450
/366 /433
/350
118 Ordering Information Chapter 15
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
AMD-K6-2/433ADK 321-pin CPGA 2.0V–2.2V (Core)
3.135V–3.6V (I/O) 0°C–80°C (CPGA)
AMD-K6-2/400ACK 321-pin CPGA 1.9V–2.1V (Core)
3.135V–3.6V (I/O) 0°C–80°C (CPGA)
AMD-K6-2/400AFK 321-pin CPGA 2.1V–2.3V (Core)
3.135V–3.6V (I/O) 0°C–80°C (CPGA)
AMD-K6-2/380AFK 321-pin CPGA 2.1V–2.3V (Core)
3.135V–3.6V (I/O) 0°C–80°C (CPGA)
AMD-K6-2/366AFK 321-pin CPGA 2.1V–2.3V (Core)
3.135V–3.6V (I/O) 0°C–80°C (CPGA)
AMD-K6-2/350AFK 321-pin CPGA 2.1V–2.3V (Core)
3.135V–3.6V (I/O) 0°C–80°C (CPGA)
Table 38. Valid Ordering Part Number Combinations (continued)
OPN Package Type Operating Voltage Case Temperature
Note: This table lists configurations planned to be supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific valid combinations and to check on
newly-released combinations.
Index 119
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
Index
Numerics
100-MHz Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 101
input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . . 58
321-Pin Staggered CPGA
package specification. . . . . . . . . . . . . . . . . . . . . . .83 –84, 86
pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
360-Pin CBGA
package specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3DNow ! Techno logy . . . . . . . . . . . . . . . . . . . . 9, 11–12, 15–19
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18–19
register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
66-MHz Bus
clock switching characteristics . . . . . . . . . . . . . . . . . . . . . 54
input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . . 62
output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
A
Accelerated Graphic Po rt (AGP). . . . . . . . . . . . . . . . . . .5, 101
Address
stack, return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Address Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25, 28
AGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4–5, 100–101
Architecture
internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7–21
B
Bits, Predecode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Boundary-Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Branch
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
history table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 11, 21, 99
prediction logic . . . . . . . . . . . . . . . . . . . 3–4, 19–20, 99–100
target cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bus
100-MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 101
address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25, 28
cycle definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25–28, 32
C
Cache . . . . . . . . . . . . . . . . . . . . . . . 3–5, 11, 23, 25, 27–31, 33,
. . . . . . . . . . . . . . . . . . . . . . .35–36, 40, 56, 60, 99–101
branch target. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
writeback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8, 11
Case Temperature. . . . . . . . . . . .79–80, 82, 95, 113–116, 118
CBGA Mechanical Specification . . . . . . . . . . . . . . . . . . . . . . 87
Cen t ralized Sched uler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Clock Control
state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
states
halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
stop clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
stop grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
stop grant inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . 76, 110
Control
unit, scheduler/instruction . . . . . . . . . . . . . . . . . . . . . . . . 10
Cycles
inquire. . . . . . . . . . . . . . . . . . . . . . . . . .25–26, 28–29, 37–40
interrupt acknowledge . . . . . . . . . . . . . . . . . . . . . 27, 33, 36
pipelined. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
special. . . . . . . . . . . . . . . . . . . . . . . . . 29, 32, 36, 38–39, 48
writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29, 40–41
D
Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25–28, 32
Decode, Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Deco d e rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 9, 99
Dual Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75, 109
E
Electrical Specifications
absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 104
operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 103
Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28–29, 50–51
debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Exceptions, Interrupts, and Debug in SMM . . . . . . . . . . . . 51
Execution
units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 99
Execution Unit
3DNow! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 18–19
branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 16, 21
floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 16
load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 16
multi m e dia . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9, 16, 18–19
registe r X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 16, 18–19
registe r Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 16, 18–19
store. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 16
Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10, 17
F
Fetch, Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Float Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Floating-Point Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Frequency . . . . . . . . . . . . . . . .26, 41, 54, 66, 72, 74, 105, 107
Functional Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
multimedia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
H
Halt
restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
120 Index
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
Heat Dissipation Path. . . . . . . . . . . . . . . . . . . . . . . . . . .81, 115
History Table, Bra nch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Hold
acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53, 68
I
I/O
trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48–49
trap re start slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
IEEE 1149.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 33, 99
Ignore Numeric Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Input
pin types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
setup and hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Input Setup and Hold Timings for
100-MHz bus o peration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Input/Output Pin Float Conditions. . . . . . . . . . . . . . . . . . . . 35
Inquire Cycles. . . . . . . . . . . . . . . . . . . . . 25–26, 28–29, 37–40
Instruction
decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Instructions
EMMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FEMMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PREFETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Internal
architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21
Interrupt . . . . . . . . . . . . . . . . . . 27, 30–33, 36, 40, 42, 44, 51
acknowledge cycles. . . . . . . . . . . . . . . . . . . . . . . . 27, 33, 36
service routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
system management. . . . . . . . . . . . . . . . . . . . . . . 32, 42, 44
J
JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23, 33
L
Logic
branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
branch-prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–20
Logic, Branch-prediction . . . . . . . . . . . . . . . . . . . . . . . . .4, 100
M
MESI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 12, 99
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . .3–4, 99–100
enha n c e d RI SC86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
overview, AMD-K6-2 processor . . . . . . . . . . . . . . . . . . . . . . 7
MMX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 5, 30–31, 99–100
MMX Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–19
register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Multimedia
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18–19
functional unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
O
Operating Ranges . . . . . . . . . . . . . . .53, 71, 95, 103–104, 117
OPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 117–118
Ordering Part Number (OPN). . . . . . . . . . . . . . . . . . . . 95, 117
Output
pin float conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
P
Parity. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23, 25–26, 28, 31, 93
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 28
check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 31
Pa rt N umber. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 117–118
Pin Co nnec t i o n R e quiremen t s . . . . . . . . . . . . . . . . . . . 77, 111
Pipeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
register X and Y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
six-stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8, 10
Pipel i n e d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11, 18, 30
cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pipelined Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Power
and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77, 110
connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75, 109
dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80, 114
Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–12
Prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
R
Register X. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Register X and Y
pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register Y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .10, 30–31, 44, 50
X and Y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–18
Reset and Configuration Timing . . . . . . . . . . . . . . . . . . . . . 69
Return Address Stack . . . . . . . . . . . . . . . . . . . . . . . . 4, 20, 100
RISC86 Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
RSM Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47, 50
S
Scheduler
centralized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
instruction control unit. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Signal Descri ptions
A[31:3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
A20M#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 42
ADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ADSC#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 38
AP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
APCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
BE[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
BF[2 :0 ]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 41
BOFF#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 38
BRDY#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 38–39, 49
BRDYC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
BREQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Index 121
21896E /0—May 2000 Mobile AMD-K6®-2 Processor Data Sheet
Preliminary Information
CACHE#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . 27, 37, 39–41, 53–54
D/C# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
D[63:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DP[7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28, 40
EWBE#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28, 38–39
FERR# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FLUSH#. . . . . . . . . . . . . . . . . . . . . . . . . . . 29, 36, 38–39, 51
HIT#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29, 40
HITM# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29, 40
HLDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
HOLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29, 38
IGNNE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30, 38–39, 43
INTR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30, 38–39
INV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
KEN# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LOCK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
M/IO# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
NA#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
NMI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31, 38–39, 43, 51
PCHK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PWT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31, 38–39, 41, 53
RSVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SCYC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SMI# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32, 38–39, 42, 49
SMIACT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32, 42
STPCLK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32, 37, 39–40
TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33, 53
TDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
VCC2DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
VCC2H/L# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
W/R#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
WB/WT#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Single Instruction Multiple Data (SIMD). . . . . . . . . . . . . . . 11
SMM
base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
default register values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
initial state of regis ters . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
operating mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
revision identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
state-save area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Special Bus Cycle . . . . . . . . . . . . . . . . . . 29, 32, 36, 38–39, 48
Stack, Return Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Stop
clock state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
grant inquire state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
grant state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Super7 Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 101
initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 101
Switching Characteristics
66-MHz bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
input setup and hold timings for 100-MHz bus. . . . . . . . 58
T
Table, Branch History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Target Cache, Branch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TCK Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66, 70
Te m perature. . . . . 7 1, 79–80, 82, 87, 95, 103, 113–116, 118
case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79–80, 113–114
Test Access Port (TAP)
TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TDI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TDO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Te st Signal
timing at 25 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
timing diag ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Thermal. . . . . . . . . . . . . . . . . . . . 74, 79–82, 87, 107, 113–116
model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
model (CBGA Package). . . . . . . . . . . . . . . . . . . . . . . . . . . 80
resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80, 114
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 113
TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66, 70
TSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38–39
V
Voltage . . . . . . . . . . . . . . . . . . 3–4, 23, 33, 37, 53, 71–72, 75,
. . . . . . . . . . . . . . . . . . . 95, 99–100, 103–105, 109, 118
dual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75, 109
W
Writeback . . . . . . . . . . . . . . . .3, 27, 29, 31, 33, 36, 40–41, 99
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8, 11
cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29, 40–41
122 Index
Mobile AMD-K6®-2 Processor Data Sheet 21896E/0—May 2000
Preliminary Information
