Precision MEMS IMU Module ADIS16465 Data Sheet FEATURES GENERAL DESCRIPTION Triaxial, digital gyroscope 125/sec, 500/sec, 2000/sec dynamic range models 2/hr in-run bias stability (ADIS16465-1) 0.15/hr angular random walk (ADIS16465-1 and ADIS16465-2) 0.05 axis to axis misalignment error Triaxial, digital accelerometer, 8 g 3.6 g in-run bias stability Triaxial, delta angle, and delta velocity outputs Factory calibrated sensitivity, bias, and axial alignment Calibration temperature range: -40C to +85C SPI-compatible data communications Programmable operation and control Automatic and manual bias correction controls Data ready indicator for synchronous data acquisition External sync modes: direct, pulse, scaled, and output On demand self test of inertial sensors On demand self test of flash memory Single-supply operation (VDD): 3.0 V to 3.6 V 2000 g mechanical shock survivability Operating temperature range: -40C to +105C The ADIS16465 is a precision, microelectric mechanical system (MEMS), inertial measurement unit (IMU) that includes a triaxial gyroscope and a triaxial accelerometer. Each inertial sensor in the ADIS16465 combines with signal conditioning to optimize dynamic performance. The factory calibration characterizes each sensor for sensitivity, bias, alignment, linear acceleration (gyroscope bias), and point of percussion (accelerometer location). Therefore, each sensor has dynamic compensation formulas that provide accurate sensor measurements over a broad set of conditions. The ADIS16465 provides a simple, cost effective method for integrating accurate, multiaxis inertial sensing into industrial systems, especially when compared to the complexity and investment associated with discrete designs. All necessary motion testing and calibration are part of the production process at the factory, greatly reducing system integration time. Tight orthogonal alignment simplifies inertial frame alignment in navigation systems. The serial peripheral interface (SPI) and register structure provide a simple interface for data collection and configuration control. The ADIS16465 is in an aluminum module package that is approximately 22.4 mm x 22.4 mm x 9 mm with a 14-lead connector interface. APPLICATIONS Navigation, stabilization, and instrumentation Unmanned and autonomous vehicles Smart agriculture and construction machinery Factory/industrial automation, robotics Virtual/augmented reality Internet of Moving Things FUNCTIONAL BLOCK DIAGRAM DR SELF TEST RST POWER MANAGEMENT INPUT/OUTPUT OUTPUT DATA REGISTERS TRIAXIAL GYROSCOPE TRIAXIAL ACCELEROMETER CONTROLLER CALIBRATION AND FILTERS GND CS SPI USER CONTROL REGISTERS SCLK DIN DOUT CLOCK ADIS16465 SYNC 15438-001 TEMPERATURE SENSOR VDD Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2017-2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADIS16465 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Device Configuration ................................................................ 15 Applications ...................................................................................... 1 User Register Memory Map.......................................................... 16 General Description ......................................................................... 1 User Register Defintions ............................................................... 18 Functional Block Diagram .............................................................. 1 Gyroscope Data .......................................................................... 18 Revision History ............................................................................... 2 Delta Angles ................................................................................ 21 Specifications .................................................................................... 3 Delta Velocity ............................................................................. 22 Timing Specifications .................................................................. 5 Calibration .................................................................................. 24 Absolute Maximum Ratings ....................................................... 7 Applications Information ............................................................. 30 Thermal Resistance ...................................................................... 7 Assembly and Handling Tips ................................................... 30 ESD Caution.................................................................................. 7 Power Supply Considerations .................................................. 30 Pin Configuration and Function Descriptions ............................ 8 Breakout Board ........................................................................... 30 Typical Performance Characteristics ............................................. 9 Serial Port Operation ................................................................. 31 Theory of Operation ...................................................................... 11 Digital Resolution of Gyroscopes and Accelerometers ........ 31 Introduction ................................................................................ 11 PC-Based Evaluation Tools ...................................................... 32 Inertial Sensor Signal Chain ..................................................... 11 Ordering Information.................................................................... 33 Register Structure ....................................................................... 12 Outline Dimensions ................................................................... 33 Serial Peripheral Interface (SPI) ............................................... 13 Ordering Guide .......................................................................... 33 Data Ready (DR) ........................................................................ 13 Reading Sensor Data .................................................................. 14 REVISION HISTORY 4/2020--Rev. B to Rev. C Changes to Table 1 ........................................................................... 3 Changes to Figure 18 ..................................................................... 10 Changes to Reading Sensor Data Section and Burst Read Function Section ............................................................................. 14 3/2019--Rev. A to Rev. B Changes to Serial Peripheral Interface (SPI) Section ................ 13 Changes to Figure 32 ..................................................................... 14 Changes to Table 10 ....................................................................... 18 Added Serial Port Operation Section, Maximum Throughput Section, and Serial Port SCLK Underrun/Overrun Conditions .. 32 Moved Gyroscope Data Width (Digital Resolution) Section... 32 Moved Accelerometer Data Width (Digital Resolution) Section . 32 Added Digital Resolution of Gyroscopes and Accelerometers Section .............................................................................................. 32 11/2018--Rev. 0 to Rev. A Changes to Table 1 ........................................................................... 3 Changes to Table 2 ........................................................................... 5 Changes to Figure 5.......................................................................... 6 Added Figure 11, Figure 12, and Figure 13; Renumbered Sequentially ........................................................................................9 Added Figure 14, Figure 15, Figure 16, and Figure 17 .............. 10 Changes to Figure 18, Figure 19, and Figure 20 ........................ 11 Changes to Figure 22 and Figure 23 ............................................ 12 Added Gyroscope Data Width (Digital Resolution) Section ... 18 Changes to Gyroscope Measurement Range/Scale Factor Section, Table 11, Gyroscope Data Formatting Section, Table 12, Table 13, Table 17, Table 21, and Table 25 .................................................. 19 Added Accelerometer Data Width (Digital Resolution) Section ........................................................................................................... 20 Changed Accelerometer Resolution Section to Accelerometer Data Formatting Section ............................................................... 20 Change to Calibration, Accelerometer Bias (XA_BIAS_LOW and XA_BIAS_HIGH) Section..................................................... 25 Change to Filter Control Register (FILT_CTRL) Section ........ 26 Changes to Direct Sync Mode Section ........................................ 27 Changes to Pulse Sync Mode Section .......................................... 28 Changes to Sensor Self Test Section ............................................ 29 Changes to Outline Dimensions .................................................. 33 12/2017--Revision 0: Initial Version Rev. C | Page 2 of 33 Data Sheet ADIS16465 SPECIFICATIONS Case temperature (TC) = 25C, VDD = 3.3 V, angular rate = 0/sec, and dynamic range = 2000/sec 1 g, unless otherwise noted. Table 1. Parameter GYROSCOPES Dynamic Range Sensitivity Repeatability1 Error over Temperature Misalignment Error Nonlinearity2 Bias Repeatability1 In-Run Bias Stability Angular Random Walk Error over Temperature Linear Acceleration Effect Vibration Rectification Effect Output Noise Rate Noise Density 3 dB Bandwidth Sensor Resonant Frequency ACCELEROMETERS3 Dynamic Range Sensitivity Repeatability1 Error over Temperature Misalignment Error Nonlinearity Test Conditions/Comments Min ADIS16465-1 ADIS16465-2 ADIS16465-3 ADIS16465-1, 16-bit ADIS16465-2, 16-bit ADIS16465-3, 16-bit ADIS16465-1, 32-bit ADIS16465-2, 32-bit ADIS16465-3, 32-bit -40C TC +85C, 1 -40C TC +85C, 1 Axis to axis, 1 ADIS16465-1, full scale (FS) = 125/sec ADIS16465-2, FS = 500/sec ADIS16465-3, FS = 2000/sec 125 500 2000 -40C TC +85C, 1 ADIS16465-1, 1 ADIS16465-2, 1 ADIS16465-3, 1 ADIS16465-1, 1 ADIS16465-2, 1 ADIS16465-3, 1 -40C TC +85C, 1 Any direction, 1 Random vibration, 2 g rms, bandwidth = 50 Hz to 2 kHz ADIS16465-1, 1 , no filtering, x-axis ADIS16465-1, 1 , no filtering, y-axis and z-axis ADIS16465-2, 1 , no filtering, x-axis ADIS16465-2, 1 , no filtering, y-axis and z-axis ADIS16465-3, 1 , no filtering, x-axis ADIS16465-3, 1 , no filtering, y-axis and z-axis ADIS16465-1, 10 Hz to 40 Hz, x-axis ADIS16465-1, 10 Hz to 40 Hz, y-axis and z-axis ADIS16465-2, 10 Hz to 40 Hz, x-axis ADIS16465-2, 10 Hz to 40 Hz, y-axis and z-axis ADIS16465-3, 10 Hz to 40 Hz, x-axis ADIS16465-3, 10 Hz to 40 Hz, y-axis and z-axis Typ Max Unit 160 40 10 10,485,760 2,621,440 655,360 0.3 0.3 0.05 0.2 0.2 0.25 /sec /sec /sec LSB//sec LSB//sec LSB//sec LSB//sec LSB//sec LSB//sec % % Degrees % FS % FS % FS 0.4 2 2.5 6 0.15 0.15 0.26 0.2 0.009 0.0005 0.05 0.07 0.05 0.08 0.11 0.16 0.002 0.003 0.002 0.003 0.004 0.0065 550 66 /sec /hr /hr /hr /hr /hr /hr /sec /sec/g /sec/g2 /sec rms /sec rms /sec rms /sec rms /sec rms /sec rms /sec/Hz rms /sec/Hz rms /sec/Hz rms /sec/Hz rms /sec/Hz rms /sec/Hz rms Hz kHz 262,144,000 0.2 0.1 0.05 0.25 0.5 1.5 g LSB/g % % Degrees % FS % FS % FS Each axis 8 32-bit data format -40C TC +85C, 1 -40C TC +85C, 1 Axis to axis Best fit straight line, 2 g Best fit straight line, 8 g, x-axis Best fit straight line, 8 g, y-axis and z-axis Rev. C | Page 3 of 33 ADIS16465 Parameter Bias Repeatability1 In-Run Bias Stability Velocity Random Walk Error over Temperature Output Noise Noise Density 3 dB Bandwidth Sensor Resonant Frequency TEMPERATURE SENSOR Scale Factor LOGIC INPUTS4 Input Voltage High, VIH Low, VIL RST Pulse Width Input Current Logic 1, IIH Logic 0, IIL All Pins Except RST RST Pin Input Capacitance, CIN DIGITAL OUTPUTS Output Voltage High, VOH Low, VOL FLASH MEMORY Data Retention6 FUNCTIONAL TIMES7 Power-On Start-Up Time Reset Recovery Time Factory Calibration Restore Flash Memory Backup Flash Memory Test Time Self Test Time9 CONVERSION RATE Initial Clock Accuracy Sync Input Clock POWER SUPPLY, VDD Power Supply Current10 Data Sheet Test Conditions/Comments Min -40C TC +85C, 1 1 1 -40C TC +85C, 1 No filtering Bandwidth = 10 Hz to 40 Hz (no filtering) Typ Max Unit Y-axis and z-axis X-axis 1.4 3.6 0.012 1 0.6 23 600 2.4 2.2 mg g m/sec/hr mg mg rms g/Hz rms Hz kHz kHz Output = 0x0000 at 0C (5C) 0.1 C/LSB 2.0 0.8 V V s 10 A 10 A mA pF 1 VIH = 3.3 V VIL = 0 V 0.33 10 ISOURCE = 0.5 mA ISINK = 2.0 mA Endurance5 TJ = 85C Time until data is available 2.4 0.4 10000 20 259 198 198 142 72 32 14 2000 3 Register GLOB_CMD, Bit 7 = 1 (see Table 113) RST pulled low, then restored to high8 Register GLOB_CMD, Bit 1 = 1 (see Table 113) Register GLOB_CMD, Bit 3 = 1 (see Table 113) Register GLOB_CMD, Bit 4 = 1 (see Table 113) Register GLOB_CMD, Bit 2 = 1 (see Table 113) Operating voltage range Normal mode, VDD = 3.3 V 1 1.9 3.0 44 2.1 3.6 55 V V Cycles Years ms ms ms ms ms ms ms SPS % kHz V mA Bias repeatability provides an estimate for long-term drift in the bias, as observed during 500 hours of High-Temperature Operating Life (HTOL) at +105C. This measurement is based on the deviation from a best fit linear model. 3 All specifications associated with the accelerometers relate to the full-scale range of 8 g, unless otherwise noted. 4 The digital input/output signals use a 3.3 V system. 5 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at -40C, +25C, +85C, and +125C. 6 The data retention specification assumes a junction temperature (TJ) of 85C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ. 7 These times do not include thermal settling and internal filter response times, which may affect overall accuracy. 8 The RST line must be in a low state for at least 10 s to ensure a proper reset initiation and recovery. 9 The self test time can extend when using external clock rates lower than 2000 Hz. 10 Power supply current transients can reach 100 mA during initial startup or reset recovery. 2 Rev. C | Page 4 of 33 Data Sheet ADIS16465 TIMING SPECIFICATIONS TA = 25C, VDD = 3.3 V, unless otherwise noted. Table 2. Normal Mode Min Typ Max 0.1 2 16 24 200 Parameter fSCLK tSTALL tREADRATE tCS Description Serial clock Stall period between data Read rate Chip select to SCLK edge tDAV tDSU tDHD tSCLKR, tSCLKF tDR, tDF tSFS t1 DOUT valid after SCLK edge DIN setup time before SCLK rising edge DIN hold time after SCLK rising edge SCLK rise/fall times DOUT rise/fall times CS high after SCLK edge Input sync positive pulse width; pulse sync mode, Register MSC_CTRL, Bits[4:1] = 101 (binary, see Table 105) Input sync to data ready valid transition Direct sync mode, Register MSC_CTRL, Bits[4:2] = 001 (binary, see Table 105) Pulse sync mode, Register MSC_CTRL, Bits[4:2] = 101 (binary, see Table 105) Data invalid time Input sync period2 tSTDR tNV t2 1 2 Burst Read Mode Min1 Typ Max 0.1 1 N/A 200 25 25 25 50 25 50 5 5 12.5 12.5 0 5 5 5 12.5 12.5 0 5 256 256 20 256 256 20 477 477 Timing Diagrams tSCLKR tSCLKF tCS tSFS SCLK 2 3 4 5 tDAV MSB DOUT DB14 R/W A6 15 16 tDR DB13 tDSU DIN 6 DB12 DB11 tDHD A5 DB10 DB2 DB1 LSB tDF A4 A3 A2 D2 D1 15438-002 1 LSB Figure 2. SPI Timing and Sequence Diagram tREADRATE tSTALL 15438-003 CS SCLK Figure 3. Stall Time and Data Rate Timing Diagram Rev. C | Page 5 of 33 ns ns ns ns ns ns s s s s s N/A means not applicable. This specification is rounded up from the cycle time that comes from the maximum input clock frequency (2100 Hz). CS Unit MHz s s ns ADIS16465 Data Sheet t2 tSTDR t1 DR tNV 15438-004 SYNC Figure 4. Input Clock Timing Diagram, Pulse Sync Mode, Register MSC_CTRL, Bits[4:2] = 101 (Binary) t2 t1 SYNC tNV tSTDR 15438-005 DR Figure 5. Input Clock Timing Diagram, Direct Sync Mode, Register MSC_CTRL, Bits[4:2] = 001 (Binary) Rev. C | Page 6 of 33 Data Sheet ADIS16465 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Parameter Mechanical Shock Survivability Any Axis, Unpowered Any Axis, Powered VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Calibration Temperature Range Operating Temperature Range Storage Temperature Range1 Barometric Pressure 1 Rating The ADIS16465 is a multichip module that includes many active components. The values in Table 4 identify the thermal response of the hottest component inside of the ADIS16465, with respect to the overall power dissipation of the module. This approach enables a simple method for predicting the temperature of the hottest junction, based on either ambient or case temperature. 2000 g 2000 g -0.3 V to +3.6 V -0.3 V to VDD + 0.2 V -0.3 V to VDD + 0.2 V -40C to +85C -40C to +105C -65C to +150C 2 bar For example, when the ambient temperature is 70C, the hottest junction temperature (TJ) inside of the ADIS16465 is 75.3C. Extended exposure to temperatures that are lower than -40C or higher than +105C can adversely affect the accuracy of the factory calibration. TJ = JA x VDD x IDD + 70C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. TJ = 36.5C/W x 3.3 V x 0.044 A + 70C TJ = 75.3C Table 4. Thermal Resistance Package Type ML-14-63 1 JA1 36.5C/W JC2 16.9C/W Mass (g) 15 JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. 3 Thermal impedance values come from direct observation of the hottest temperature inside of the ADIS16465 when it is attached to an FR4-08 PCB that has two metal layers and has a thickness of 0.063 inches. 2 ESD CAUTION Rev. C | Page 7 of 33 ADIS16465 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADIS16465 PIN 1 TOP VIEW (Not to Scale) DNC DIN SCLK DR 9 7 5 3 1 14 12 10 8 6 4 2 DNC DNC RST CS DOUT SYNC NOTES 1. THIS REPRESENTS THE PIN ASSIGNMENTS WHEN LOOKING DOWN AT THE CONNECTOR. SEE FIGURE 7. 2. MATING CONNECTOR: SAMTEC CLM-107-02 SERIES OR EQUIVALENT. 3. DNC = DO NOT CONNECT. 15438-007 DNC 11 15438-006 GND VDD 13 DNC PIN 14 Figure 6. Pin Assignments, Bottom View Figure 7. Pin Assignments, Package Level View Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic DR SYNC SCLK DOUT DIN CS DNC RST DNC DNC VDD DNC GND DNC Type Output Input/output Input Output Input Input Not applicable Input Not applicable Not applicable Supply Not applicable Supply Not applicable Description Data Ready Indicator. External Sync Input/Output, per MSC_CTRL. See Table 105. SPI Serial Clock. SPI Data Output. This pin clocks the output on the SCLK falling edge. SPI Data Input. This pin clocks the input on the SCLK rising edge. SPI Chip Select. Do Not Connect. Do not connect to this pin. Reset. Do Not Connect. Do not connect to this pin. Do Not Connect. Do not connect to this pin. Power Supply. Do Not Connect. Do not connect to this pin. Power Ground. Do Not Connect. Do not connect to this pin. Rev. C | Page 8 of 33 Data Sheet ADIS16465 TYPICAL PERFORMANCE CHARACTERISTICS 1000 ALLAN DEVIATION (g) 100 10 1 0.1 0.001 0.01 0.1 1 10 100 1000 10000 100000 INTEGRATION PERIOD (Seconds) 100 10 1 0.1 0.001 0.1 1 10 100 1000 10000 100000 Figure 11. Accelerometer Allan Deviation, TC = 25C 0.4 X-AXIS Y-AXIS Z-AXIS 0.3 100 SENSITIVITY ERROR (%) ALLAN DEVIATION (Degrees/Hour) 0.01 INTEGRATION PERIOD (Seconds) Figure 8. Gyroscope Allan Deviation, TC = 25C, ADIS16465-1 1000 X-AXIS Y-AXIS Z-AXIS 15438-111 X-AXIS Y-AXIS Z-AXIS 15438-008 ALLAN DEVIATION (Degrees/Hour) 1000 10 1 0.2 0.1 + 1 0 -0.1 - 1 -0.2 0.01 0.1 1 10 100 1000 10000 100000 INTEGRATION PERIOD (Seconds) Figure 9. Gyroscope Allan Deviation, TC = 25C, ADIS16465-2 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE (C) Figure 12. ADIS16465-1 Gyroscope Sensitivity Error vs. Ambient Temperature 0.4 X-AXIS Y-AXIS Z-AXIS 0.3 SENSITIVITY ERROR (%) 100 10 1 0.2 0.1 + 1 0 -0.1 -0.2 - 1 0.1 0.001 0.01 0.1 1 10 100 1000 10000 100000 INTEGRATION PERIOD (Seconds) Figure 10. Gyroscope Allan Deviation, TC = 25C, ADIS16465-3 -0.4 -60 -40 -20 0 20 40 60 AMBIENT TEMPERATURE (C) 80 100 15438-113 -0.3 15438-010 ALLAN DEVIATION (Degrees/Hour) 1000 -0.4 -60 15438-009 0.1 0.001 15438-112 -0.3 Figure 13. ADIS16465-2 Gyroscope Sensitivity Error vs. Ambient Temperature Rev. C | Page 9 of 33 ADIS16465 Data Sheet 0.4 0.5 0.4 BIAS ERROR (Degrees/Second) 0.2 0.1 0 + 1 -0.1 -0.2 - 1 -0.3 0.2 + 1 0.1 0 -0.1 - 1 -0.2 -0.3 -0.4 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE (C) -0.5 -60 15438-114 -0.4 -60 0.3 Figure 14. ADIS16465-3 Gyroscope Sensitivity Error vs. Ambient Temperature -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE (C) 15438-117 SENSITIVITY ERROR (%) 0.3 Figure 17. ADIS16465-3 Gyroscope Bias Error vs. Ambient Temperature 0.5 0.3 0.2 BIAS ERROR (Degrees/Second) BIAS ERROR (Degrees/Second) 0.4 + 1 0.1 0 -0.1 - 1 -0.2 -0.3 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE (C) Figure 15. ADIS16465-1 Gyroscope Bias Error vs. Ambient Temperature 0 BIAS ERROR (Degrees/Second) 0.3 + 1 0.1 0 -0.1 - 1 -0.3 -40 -20 0 20 40 60 AMBIENT TEMPERATURE (C) 80 100 15438-116 -0.4 -0.5 -60 15 20 25 30 35 Figure 18. ADIS16465-3 Gyroscope Bias Error vs. Power-On Time at 25C. (Applicable to All ADIS16465 Models) 0.4 -0.2 10 POWER-ON TIME (Minutes) 0.5 0.2 5 15438-118 -0.5 -60 15438-115 -0.4 Figure 16. ADIS16465-2 Gyroscope Bias Error vs. Ambient Temperature Rev. C | Page 10 of 33 Data Sheet ADIS16465 THEORY OF OPERATION When using the factory default configuration for all user configurable control registers, the ADIS16465 initializes and automatically starts a continuous process of sampling, processing, and loading calibrated sensor data into the output registers at a rate of 2000 SPS. The ADIS16465 provides three different modes of operation that support the device using an external clock to control the internal processing rate (fSM in Figure 20 and Figure 21) through the SYNC pin. The MSC_CTRL register (see Table 105) provides the configuration options for these external clock modes in Bits[4:2]. INERTIAL SENSOR SIGNAL CHAIN Inertial Sensor Calibration Figure 19 shows the basic signal chain for the inertial sensors in the ADIS16465. This signal chain produces an update rate of 2000 SPS in the output data registers when it operates in internal clock mode (default, see Register MSC_CTRL, Bits[4:2] in Table 105). The inertial sensor calibration function for the gyroscopes and the accelerometers has two components: factory calibration and user calibration (see Figure 22). MEMS SENSORS BARTLETT WINDOW FIR FILTER AVERAGING DECIMATING FILTER CALIBRATION OUTPUT DATA REGISTERS Figure 19. Signal Processing Diagram, Inertial Sensors FROM BARTLETT WINDOW FIR FILTER fSG = 4100Hz TO BARTLETT WINDOW FIR FILTER fSM = 2000Hz 15438-012 INTERNAL DATA REGISTER Figure 20. Gyroscope Data Sampling Accelerometer Data Sampling The three accelerometers produce linear acceleration measurements along the same orthogonal axes (x, y, and z) as the gyroscopes. Figure 21 shows the data sampling plan for each accelerometer when the ADIS16465 operates in internal clock mode (default, see Register MSC_CTRL, Bits[4:2] in Table 105). ADC 1 2 a(n) 2 n =1 /2 2 x fSM = 4000Hz Figure 21. Accelerometer Data Sampling TO BARTLETT WINDOW FIR FILTER 15438-013 MEMS ACCELEROMETER TO AVERAGING DECIMATING FILTER Figure 22. Inertial Sensor Calibration Processing The three gyroscopes produce angular rate measurements around three orthogonal axes (x, y, and z). Figure 20 shows the data sampling plan for each gyroscope when the ADIS16465 operates in internal clock mode (default, see Register MSC_CTRL, Bits[4:2] in Table 105). Each gyroscope has an analog-to-digital converter (ADC) and sample clock (fSG) that drives data sampling at a rate of 4100 Hz (5%). The internal processor reads and processes this data from each gyroscope at a rate of 2000 Hz (fSM). ADC USER CALIBRATION The factory calibration of the gyroscope applies the following correction formulas to the data of each gyroscope: Gyroscope Data Sampling MEMS GYROSCOPE FACTORY CALIBRATION 15438-014 External Clock Options 15438-011 INTRODUCTION XC m11 m12 YC m21 m22 ZC m31 m32 l11 l12 l21 l22 l31 l32 m13 X bX m23 Y bY m33 Z bZ l13 a XC l23 aYC l33 aZC where: XC, YC, and ZC are the gyroscope outputs (post calibration). m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and alignment correction. X, Y, and Z are the gyroscope outputs (precalibration). bX, bY, and bZ provide bias correction. l11, l12, l13, l21, l22, l23, l31, l32, and l33 provide linear g correction aXC, aYC, and aZC are the accelerometer outputs (post calibration). All of the correction factors in this relationship come from direct observation of the response of each gyroscope at multiple temperatures over the calibration temperature range (-40C TC +85C). These correction factors are stored in the flash memory bank, but they are not available for observation or configuration. Register MSC_CTRL, Bit 7 (see Table 105) provides the only user configuration option for the factory calibration of the gyroscopes: an on/off control for the linear g compensation. See Figure 45 for more details on the user calibration options available for the gyroscopes. Rev. C | Page 11 of 33 ADIS16465 Data Sheet 0 p32 FROM MEMS SENSOR p13 2XC p 23 2YC 0 2ZC 1 N (n) N n =1 1 N (n) N n =1 TO FACTORY CALIBRATION Figure 23. Bartlett Window FIR Filter Signal Path Averaging/Decimating Filter where: aXC, aYC, and aZC are the accelerometer outputs (post calibration). m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and alignment correction. aX, aY, and aZ are the accelerometer outputs (precalibration). bX, bY, and bZ provide bias correction. p12, p13, p21, p23, p31, and p32 provide a point of percussion alignment correction (see Figure 48). 2XC, 2YC, and 2ZC are the square of the gyroscope outputs (post calibration). All of the correction factors in this relationship come from direct observation of the response of each accelerometer at multiple temperatures over the calibration temperature range (-40C TC +85C). These correction factors are stored in the flash memory bank, but they are not available for observation or configuration. Register MSC_CTRL, Bit 6 (see Table 105) provides the only user configuration option for the factory calibration of the accelerometers: an on/off control for the point of percussion, alignment function. See Figure 46 for more details on the user calibration options available for the accelerometers. The second digital filter averages multiple samples together to produce each register update. In this type of filter structure, the number of samples in the average is equal to the reduction in the update rate for the output data registers. The DEC_RATE register (see Table 109) provides the configuration controls for this filter. FROM USER CALIBRATION 1 N (n) N n =1 /N TO OUTPUT REGISTERS Figure 24. Averaging/Decimating Filter Diagram REGISTER STRUCTURE All communication between the ADIS16465 and an external processor involves either reading the contents of an output register or writing configuration or command information to a control register. The output data registers include the latest sensor data, error flags, and identification information. The control registers include sample rate, filtering, calibration, and diagnostic options. Each user accessible register has two bytes (upper and lower), each of which has a unique address. See Table 8 for a detailed list of all user registers and the corresponding addresses. TRIAXIAL GYROSCOPE TRIAXIAL ACCELEROMETER TEMPERATURE SENSOR SENSOR SIGNAL PROCESSING OUTPUT REGISTERS CONTROLLER CONTROL REGISTERS Figure 25. Basic Operation of the ADIS16465 Rev. C | Page 12 of 33 15438-017 p12 15438-016 0 p 21 p31 m13 a X b X m23 aY bY m33 a Z bZ The Bartlett window finite impulse response (FIR) filter (see Figure 23) contains two averaging filter stages in a cascade configuration. The FILT_CTRL register (see Table 101) provides the configuration controls for this filter. SPI a XC m11 m12 aYC m21 m22 a ZC m31 m32 Bartlett Window FIR Filter 15438-015 The factory calibration of the accelerometer applies the following correction formulas to the data of each accelerometer: Data Sheet ADIS16465 DATA READY (DR) The SPI provides access to the user registers (see Table 8). Figure 26 shows the most common connections between the ADIS16465 and a SPI master device, which is often an embedded processor that has an SPI-compatible interface. In this example, the SPI master uses an interrupt service routine to collect data every time the data ready (DR) signal pulses. The factory default configuration provides users with a DR signal on the DR pin (see Table 5) that pulses when the output data registers update. Connect the DR pin to a pin on the embedded processor to trigger data collection, on the second edge of this pulse. Register MSC_CTRL, Bit 0 (see Table 105), controls the polarity of this signal. In Figure 27, Register MSC_ CTRL, Bit 0 = 1, which means that data collection must start on the rising edges of the DR pulses. Additional information on the ADIS16465 SPI can be found in the Applications Information section of this data sheet. INPUT/OUTPUT LINES ARE COMPATIBLE WITH 3.3V LOGIC LEVELS +3.3V VDD DR ACTIVE Figure 27. Data Ready When Register MSC_CTRL, Bit 0 = 1 (Default) ADIS16465 SCLK SCLK MOSI DIN MISO DOUT During the start-up and reset recovery processes, the DR signal may exhibit some transient behavior before data production begins. Figure 28 shows an example of the DR behavior during startup, and Figure 29 and Figure 30 provide examples of the DR behavior during recovery from reset commands. 15438-018 DR TIME THAT VDD > 3V Figure 26. Electrical Connection Diagram VDD PULSING INDICATES DATA PRODUCTION Table 6. Generic SPI Master Pin Mnemonics and Functions Function Slave select Serial clock Master output, slave input Master input, slave output Interrupt request DR START-UP TIME Figure 28. Data Ready Response During Startup Embedded processors typically use control registers to configure serial ports for communicating with SPI slave devices, such as the ADIS16465. Table 7 provides a list of settings that describe the SPI protocol of the ADIS16465. The initialization routine of the master processor typically establishes these settings using firmware commands to write them into the control registers. SOFTWARE RESET COMMAND GLOB_CMD[7] = 1 DR PULSING RESUMES DR RESET RECOVERY TIME Figure 29. Data Ready Response During Reset (Register GLOB_CMD, Bit 7 = 1) Recovery Table 7. Generic Master Processor SPI Settings Processor Setting Master SCLK 2 MHz1 SPI Mode 3 MSB First Mode 16-Bit Mode 1 15438-020 CS 15438-021 SS IRQ Mnemonic SS SCLK MOSI MISO IRQ INACTIVE Description ADIS16465 operates as slave Maximum serial clock rate CPOL = 1 (polarity), CPHA = 1 (phase) Bit sequence, see Figure 31 for coding Shift register and data length RST PIN RELEASED RST DR PULSING RESUMES DR A burst mode read requires this value to be 1 MHz (see Table 2 for more information). RESET RECOVERY TIME Figure 30. Data Ready Response During Reset (RST = 0) Recovery Rev. C | Page 13 of 33 15438-022 SYSTEM PROCESSOR SPI MASTER 15438-019 SERIAL PERIPHERAL INTERFACE (SPI) ADIS16465 Data Sheet CS DIN R/W DOUT D15 A6 A5 A4 A3 A2 A1 A0 DC7 D14 D13 D12 D11 D10 D9 D8 D7 DC6 DC5 D6 DC4 D5 DC3 DC2 D4 D3 D2 R/W DC1 DC0 D1 D0 D15 A6 A5 D14 D13 NOTES 1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0. 2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE FOR OTHER DEVICES. 15438-023 SCLK Figure 31. SPI Communication Bit Sequence 1 CS 2 3 11 SCLK 0x6800 DIAG_STAT DOUT XGYRO_OUT 15438-024 DIN CHECKSUM Figure 32. Burst Read Sequence DIN = 0x7200 = 0111 0010 0000 0000 DOUT HIGH-Z HIGH-Z DOUT = 0100 0000 0101 0001 = 0x4051 = 16465 (PROD_ID) 15438-025 CS SCLK DIN Figure 33. SPI Signal Pattern, Repeating Read of the PROD_ID Register Burst Read Function Reading a single register requires two 16-bit cycles on the SPI: one to request the contents of a register and another to receive those contents. The 16-bit command code (see Figure 31) for a read request on the SPI has three parts: the read bit (R/W = 0), either address of the register, [A6:A0], and eight don't care bits, [DC7:DC0]. Figure 34 shows an example that includes two register reads in succession. This example starts with DIN = 0x0C00 to request the contents of the Z_GYRO_LOW register, and follows with 0x0E00 to request the contents of the Z_GYRO_OUT register. The sequence in Figure 34 also shows full duplex mode of operation, which means that the ADIS16465 can receive requests on DIN while also transmitting data out on DOUT within the same 16-bit SPI cycle. The burst read function provides a method to read the same group of output data registers using a continuous stream of bits at an SCLK rate of up to 1 MHz. This method does not require a stall time between each 16-bit segment (see Figure 3). To start this mode, set DIN = 0x6800 to read Register 0x68, and then read each register in the sequence out of DOUT while keeping CS low for the entire 176-bit sequence (see Figure 32). It is critical to read all 176 bits before the CS pin goes high. DIN DOUT 0x0C00 0x0E00 NEXT ADDRESS Z_GYRO_LOW Z_GYRO_OUT 15438-026 READING SENSOR DATA Figure 34. SPI Read Example Figure 33 shows an example of the four SPI signals when reading the PROD_ID register (see Table 121) in a repeating pattern. This pattern can be helpful when troubleshooting the SPI interface setup and communications because the signals are the same for each 16-bit sequence, except during the first cycle. Note that the read and write functions using the SPI interface are always 16-bits long. The only exception is the burst read function described in the Burst Read Function section. The burst read function provides a way to read a batch of output data registers, using a continuous stream of bits, at a rate of up to 1 MHz (SCLK). This method does not require a stall time between each 16-bit segment (see Figure 3). As shown in Figure 32, start this mode by setting DIN = 0x6800, and then read each of the registers in the sequence out of DOUT while keeping CS low for the entire 176-bit sequence. The sequence of registers (and checksum value) in the burst read response depends on which sample clock mode that the ADIS16465 is operating in (Register MSC_CTRL, Bits[4:2], see Table 105). In all clock modes, except when operating in scaled sync mode (Register MSC_CTRL, Bits[4:2] = 010), the burst read response includes the following registers and value: DIAG_STAT, X_GYRO_OUT, Y_GYRO_OUT, Z_GYRO_OUT, X_ACCL_ OUT, Y_ACCL_OUT, Z_ACCL_OUT, TEMP_OUT, DATA_ CNTR, and the checksum value. In these cases, use the following formula to verify the checksum value, treating each byte in the formula as an independent, unsigned, 8-bit number: Rev. C | Page 14 of 33 Data Sheet ADIS16465 When operating in scaled sync mode (Register MSC_CTRL, Bits[4:2] = 010), the burst read response includes the following registers and value: DIAG_STAT, X_GYRO_OUT, Y_GYRO _OUT, Z_GYRO_OUT, X_ACCL_OUT, Y_ACCL_OUT, Z_ACCL_OUT, TEMP_OUT, TIME_STAMP, and the checksum value. In this case, use the following formula to verify the checksum value, treating each byte in the formula as an independent, unsigned, 8-bit number: Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] + X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] + Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] + Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] + X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] + Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] + Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] + TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] + TIME_STAMP, Bits[15:8] + TIME_STAMP, Bits[7:0] CS DIN 0xDC04 15438-027 SCLK 0xDD00 Figure 35. SPI Sequence for Writing 0x0004 to FILT_CTRL Memory Structure Figure 36 shows a functional diagram for the memory structure of the ADIS16465. The flash memory bank contains the operational code, unit specific calibration coefficients, and user configuration settings. During initialization (power application or reset recover), this information loads from the flash memory into the static random access memory (SRAM), which supports all normal operation, including register access through the SPI port. Writing to a configuration register using the SPI updates the SRAM location of the register but does not automatically update the settings in the flash memory bank. The manual flash memory update command (Register GLOB_CMD, Bit 3, see Table 113) provides a convenient method for saving all of these settings to the flash memory bank at one time. A yes in the Flash Backup column of Table 8 identifies the registers that have storage support in the flash memory bank. DEVICE CONFIGURATION Each configuration register contains 16 bits (two bytes). Bits[7:0] contain the low byte, and Bits[15:8] contain the high byte of each register. Each byte has a unique address in the user register map (see Table 8). Updating the contents of a register requires writing to both bytes in the following sequence: low byte first, high byte second. There are three parts to coding an SPI command (see Figure 31) that write a new byte of data to a register: the write bit (R/W = 1), the address of the byte, [A6:A0], and the new data for that location, [DC7:DC0]. Figure 35 shows a coding example for writing 0x0004 to the FILT_CTRL register (see Table 101). In Figure 35, the 0xDC04 command writes 0x04 to Address 0x5C (lower byte) and the 0xDD00 command writes 0x00 to Address 0x5D (upper byte). Rev. C | Page 15 of 33 MANUAL FLASH BACKUP NONVOLATILE FLASH MEMORY VOLATILE SRAM (NO SPI ACCESS) SPI ACCESS START-UP RESET Figure 36. SRAM and Flash Memory Diagram 15438-028 Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] + X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] + Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] + Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] + X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] + Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] + Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] + TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] + DATA_CNTR, Bits[15:8] + DATA_CNTR, Bits[7:0] ADIS16465 Data Sheet USER REGISTER MEMORY MAP Table 8. User Register Memory Map (N/A Means Not Applicable) Name Reserved DIAG_STAT X_GYRO_LOW X_GYRO_OUT Y_GYRO_LOW Y_GYRO_OUT Z_GYRO_LOW Z_GYRO_OUT X_ACCL_LOW X_ACCL_OUT Y_ACCL_LOW Y_ACCL_OUT Z_ACCL_LOW Z_ACCL_OUT TEMP_OUT TIME_STAMP Reserved DATA_CNTR X_DELTANG_LOW X_DELTANG_OUT Y_DELTANG_LOW Y_DELTANG_OUT Z_DELTANG_LOW Z_DELTANG_OUT X_DELTVEL_LOW X_DELTVEL_OUT Y_DELTVEL_LOW Y_DELTVEL_OUT Z_DELTVEL_LOW Z_DELTVEL_OUT Reserved XG_BIAS_LOW XG_BIAS_HIGH YG_BIAS_LOW YG_BIAS_HIGH ZG_BIAS_LOW ZG_BIAS_HIGH XA_BIAS_LOW XA_BIAS_HIGH YA_BIAS_LOW YA_BIAS_HIGH ZA_BIAS_LOW ZA_BIAS_HIGH Reserved FILT_CTRL RANG_MDL MSC_CTRL UP_SCALE R/W N/A R R R R R R R R R R R R R R R N/A R R R R R R R R R R R R R N/A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W N/A R/W R R/W R/W Flash Backup N/A No No No No No No No No No No No No No No No N/A No No No No No No No No No No No No No N/A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes N/A Yes No Yes Yes Address 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x0E, 0x0F 0x10, 0x11 0x12, 0x13 0x14, 0x15 0x16, 0x17 0x18, 0x19 0x1A, 0x1B 0x1C, 0x1D 0x1E, 0x1F 0x20, 0x21 0x22, 0x23 0x24, 0x25 0x26, 0x27 0x28, 0x29 0x2A, 0x2B 0x2C, 0x2D 0x2E, 0x2F 0x30, 0x31 0x32, 0x33 0x34, 0x35 0x36, 0x37 0x38, 0x39 0x3A, 0x3B 0x3C to 0x3F 0x40, 0x41 0x42, 0x43 0x44, 0x45 0x46, 0x47 0x48, 0x49 0x4A, 0x4B 0x4C, 0x4D 0x4E, 0x4F 0x50, 0x51 0x52, 0x53 0x54, 0x55 0x56, 0x57 0x58 to 0x5B 0x5C, 0x5D 0x5E, 0x5F 0x60, 0x61 0x62, 0x63 Default N/A 0x0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 N/A 0x0000 N/A1 0x00C1 0x07D0 DEC_RATE R/W Yes 0x64, 0x65 0x0000 Rev. C | Page 16 of 33 Register Description Reserved Output, system error flags Output, x-axis gyroscope, low word Output, x-axis gyroscope, high word Output, y-axis gyroscope, low word Output, y-axis gyroscope, high word Output, z-axis gyroscope, low word Output, z-axis gyroscope, high word Output, x-axis accelerometer, low word Output, x-axis accelerometer, high word Output, y-axis accelerometer, low word Output, y-axis accelerometer, high word Output, z-axis accelerometer, low word Output, z-axis accelerometer, high word Output, temperature Output, time stamp Reserved New data counter Output, x-axis delta angle, low word Output, x-axis delta angle, high word Output, y-axis delta angle, low word Output, y-axis delta angle, high word Output, z-axis delta angle, low word Output, z-axis delta angle, high word Output, x-axis delta velocity, low word Output, x-axis delta velocity, high word Output, y-axis delta velocity, low word Output, y-axis delta velocity, high word Output, z-axis delta velocity, low word Output, z-axis delta velocity, high word Reserved Calibration, offset, gyroscope, x-axis, low word Calibration, offset, gyroscope, x-axis, high word Calibration, offset, gyroscope, y-axis, low word Calibration, offset, gyroscope, y-axis, high word Calibration, offset, gyroscope, z-axis, low word Calibration, offset, gyroscope, z-axis, high word Calibration, offset, accelerometer, x-axis, low word Calibration, offset, accelerometer, x-axis, high word Calibration, offset, accelerometer, y-axis, low word Calibration, offset, accelerometer, y-axis, high word Calibration, offset, accelerometer, z-axis, low word Calibration, offset, accelerometer, z-axis, high word Reserved Control, Bartlett window FIR filter Measurement range (model specific) identifier Control, input/output and other miscellaneous options Control, scale factor for input clock, pulse per second (PPS) mode Control, decimation filter (output data rate) Data Sheet Name NULL_CNFG GLOB_CMD Reserved FIRM_REV FIRM_DM FIRM_Y PROD_ID SERIAL_NUM USER_SCR_1 USER_SCR_2 USER_SCR_3 FLSHCNT_LOW FLSHCNT_HIGH 1 ADIS16465 R/W R/W W N/A R R R R R R/W R/W R/W R R Flash Backup Yes No N/A No No No No No Yes Yes Yes No No Address 0x66, 0x67 0x68, 0x69 0x6A to 0x6B 0x6C, 0x6D 0x6E, 0x6F 0x70, 0x71 0x72, 0x73 0x74, 0x75 0x76, 0x77 0x78, 0x79 0x7A, 0x7B 0x7C, 0x7D 0x7E, 0x7E Default 0x070A N/A N/A N/A N/A N/A 0x4051 N/A N/A N/A N/A N/A N/A See Table 102 for the default value in this register, which is model specific. Rev. C | Page 17 of 33 Register Description Control, bias estimation period Control, global commands Reserved Identification, firmware revision Identification, date code, day and month Identification, date code, year Identification, device number Identification, serial number User Scratch Register 1 User Scratch Register 2 User Scratch Register 3 Output, flash memory write cycle counter, lower word Output, flash memory write cycle counter, upper word ADIS16465 Data Sheet USER REGISTER DEFINTIONS Status/Error Flag Indicators (DIAG_STAT) GYROSCOPE DATA Table 9. DIAG_STAT Register Definition The gyroscopes in the ADIS16465 measure the angular rate of rotation around three orthogonal axes (x, y, and z). Figure 37 shows the orientation of each gyroscope axis, along with the direction of rotation that produces a positive response in each measurement. Access R Flash Backup No Table 10. DIAG_STAT Bit Assignments Bits [15:8] 7 6 5 4 3 2 1 0 Description Reserved. Clock error. A 1 indicates that the internal data sampling clock (fSM, see Figure 20 and Figure 21) does not synchronize with the external clock, which only applies when using scaled sync mode (Register MSC_CTRL, Bits[4:2] = 010, see Table 105). When this error occurs, adjust the frequency of the clock signal on the SYNC pin to operate within the appropriate range. Memory failure. A 1 indicates a failure in the flash memory test (Register GLOB_CMD, Bit 4, see Table 113), which involves a comparison between a cyclic redundancy check (CRC) calculation of the present flash memory and a CRC calculation from the same memory locations at the time of initial programming (during the production process). If this error occurs, repeat the same test. If this error persists, replace the ADIS16465. Sensor failure. A 1 indicates failure of at least one sensor, at the conclusion of the self test (Register GLOB_CMD, Bit 2, see Table 113). If this error occurs, repeat the same test. If this error persists, replace the ADIS16465. Motion during the execution of this test can cause a false failure. Standby mode. A 1 indicates that the voltage across VDD and GND is <2.8 V, which causes data processing to stop. When VDD 2.8 V for 250 ms, the ADIS16465 reinitializes and starts producing data again. SPI communication error. A 1 indicates that the total number of SCLK cycles is not equal to an integer multiple of 16. When this error occurs, repeat the previous communication sequence. Persistence in this error may indicate a weakness in the SPI service that the ADIS16465 is receiving from the system it is supporting. Flash memory update failure. A 1 indicates that the most recent flash memory update (Register GLOB_CMD, Bit 3, see Table 113) failed. If this error occurs, ensure that VDD 3 V and repeat the update attempt. If this error persists, replace the ADIS16465. Datapath overrun. A 1 indicates that one of the datapaths experienced an overrun condition. If this error occurs, initiate a reset using the RST pin (see Table 5, Pin 8) or Register GLOB_CMD, Bit 7 (see Table 113). See the Serial Port Operation section for more details on conditions that may cause this bit to be set to 1. Reserved. The DIAG_STAT register (see Table 9 and Table 10) provides error flags for monitoring the integrity and operation of the ADIS16465. Reading this register causes all of the bits to return to 0. The error flags in DIAG_STAT are sticky, meaning that, when the flags raise to 1, the flags remain there until a read request clears the flags. If an error condition persists, the flag (bit) automatically returns to an alarm value of 1. Z-AXIS z Y-AXIS X-AXIS x y 15438-029 Default 0x0000 Figure 37. Gyroscope Axis and Polarity Assignments Each gyroscope has two output data registers. Figure 38 shows how these two registers combine to support a 32-bit, twos complement data format for the x-axis gyroscope measurements. This format also applies to the y- and z-axes. X_GYRO_OUT X_GYRO_LOW BIT 15 BIT 0 BIT 15 BIT 0 X-AXIS GYROSCOPE DATA 15438-030 Addresses 0x02, 0x03 Figure 38. Gyroscope Output Data Structure Gyroscope Measurement Range/Scale Factor Table 11 provides the measurement range (MAX) and scale factor (KG) for the gyroscope in each ADIS16465 model. Table 11. Gyroscope Measurement Range and Scale Factors Model ADIS16465-1 ADIS16465-2 ADIS16465-3 Range, MAX (/sec) 125 500 2000 Scale Factor, KG (LSB//sec) 160 40 10 Gyroscope Data Formatting Table 12 and Table 13 offer various numerical examples that demonstrate the format of the rotation rate data in both 16-bit and 32-bit formats using the generic measurement range (MAX) and scale factor (KG) definitions from Table 11. Table 12. 16-Bit Gyroscope Data Format Examples Rotation Rate +MAX +2/KG +1/KG 0/sec -1/KG -2/KG -MAX Rev. C | Page 18 of 33 Decimal +20,000 +2 +1 0 -1 -2 -20,000 Hex. 0x4E20 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0xB1E0 Binary 0100 1110 0010 0000 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1011 0001 1110 0000 Data Sheet ADIS16465 Z-Axis Gyroscope (Z_GYRO_LOW and Z_GYRO_OUT) Table 13. 32-Bit Gyroscope Data Format Examples Rotation Rate (/sec) +MAX +2/(KG x 216) +1/(KG x 216) 0 -1/(KG x 216) -2/(KG x 216) -MAX Decimal +1,310,720,000 +2 +1 0 -1 -2 -1,310,720,000 Hex. 0x4E200000 0x00000002 0x00000001 0x0000000 0xFFFFFFFF 0xFFFFFFFE 0xB1E00000 Table 22. Z_GYRO_LOW Register Definition Addresses 0x0C, 0x0D Default Not applicable Access R Table 23. Z_GYRO_LOW Bit Definitions Bits [15:0] Description Z-axis gyroscope data; additional resolution bits Table 24. Z_GYRO_OUT Register Definition X-Axis Gyroscope (X_GYRO_LOW and X_GYRO_OUT) Table 14. X_GYRO_LOW Register Definition Addresses 0x0E, 0x0F Addresses 0x04, 0x05 Table 25. Z_GYRO_OUT Bit Definitions Default Not applicable Access R Flash Backup No Bits [15:0] Table 15. X_GYRO_LOW Bit Definitions Bits [15:0] Description X-axis gyroscope data; additional resolution bits Table 16. X_GYRO_OUT Register Definition Addresses 0x06, 0x07 Default Not applicable Access R Flash Backup No Table 17. X_GYRO_OUT Bit Definitions Bits [15:0] Flash Backup No Description X-axis gyroscope data; high word; twos complement, 0/sec = 0x0000, 1 LSB = 1/KG (see Table 11 for KG) The X_GYRO_LOW (see Table 14 and Table 15) and X_GYRO_ OUT (see Table 16 and Table 17) registers contain the gyroscope data for the x-axis. Default Not applicable Access R Flash Backup No Description Z-axis gyroscope data; high word; twos complement, 0/sec = 0x0000, 1 LSB = 1/KG (see Table 11 for KG) The Z_GYRO_LOW (see Table 22 and Table 23) and Z_GYRO_ OUT (see Table 24 and Table 25) registers contain the gyroscope data for the z-axis. Acceleration Data The accelerometers in the ADIS16465 measure both dynamic and static (response to gravity) acceleration along the same three orthogonal axes that define the axes of rotation for the gyroscopes (x, y, and z). Figure 39 shows the orientation of each accelerometer axis, along with the direction of acceleration that produces a positive response in each measurement. Z-AXIS az Y-Axis Gyroscope (Y_GYRO_LOW and Y_GYRO_OUT) Y-AXIS X-AXIS Table 18. Y_GYRO_LOW Register Definition Addresses 0x08, 0x09 Default Not applicable Access R ax ay Flash Backup No Bits [15:0] 15438-031 Table 19. Y_GYRO_LOW Bit Definitions Description Y-axis gyroscope data; additional resolution bits Figure 39. Accelerometer Axis and Polarity Assignments Table 20. Y_GYRO_OUT Register Definition Addresses 0x0A, 0x0B Default Not applicable Access R Flash Backup No Each accelerometer has two output data registers. Figure 40 shows how these two registers combine to support a 32-bit, twos complement data format for the x-axis accelerometer measurements. This format also applies to the y- and z-axes. Table 21. Y_GYRO_OUT Bit Definitions X_ACCL_OUT Description Y-axis gyroscope data; high word; twos complement, 0/sec = 0x0000, 1 LSB = 1/KG (see Table 11 for KG) The Y_GYRO_LOW (see Table 18 and Table 19) and Y_GYRO_ OUT (see Table 20 and Table 21) registers contain the gyroscope data for the y-axis. BIT 15 X_ACCL_LOW BIT 0 BIT 15 BIT 0 X-AXIS ACCELEROMETER DATA 15438-032 Bits [15:0] Figure 40. Accelerometer Output Data Structure Accelerometer Data Formatting Table 26 and Table 27 show various numerical examples that demonstrate the format of the linear acceleration data in both 16-bit and 32-bit formats. Rev. C | Page 19 of 33 ADIS16465 Data Sheet Table 26. 16-Bit Accelerometer Data Format Examples Table 35. Y_ACCL_OUT Bit Definitions Acceleration +8 g +0.5 mg +0.25 mg 0 mg -0.25 mg -0.5 mg -8 g Bits [15:0] Decimal +32,000 +2 +1 0 -1 -2 -32,000 Hex. 0x7D00 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0x8300 Binary 0111 1101 0000 0000 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1000 0011 0000 0000 Decimal +2,097,152,000 +2 +1 0 -1 -2 -2,097,152,000 Access R Bits [15:0] Flash Backup No Access R Addresses 0x1A, 0x1B Default Not applicable Access R Flash Backup No Bits [15:0] Description Z-axis accelerometer data, high word; twos complement, 8 g range; 0 g = 0x0000, 1 LSB = 0.25 mg Internal Temperature (TEMP_OUT) Flash Backup No Table 31. X_ACCL_OUT Bit Definitions Bits [15:0] Description Z-axis accelerometer data; additional resolution bits The Z_ACCL_LOW (see Table 36 and Table 37) and Z_ACCL_OUT (see Table 38 and Table 39) registers contain the accelerometer data for the z-axis. Table 30. X_ACCL_OUT Register Definition Default Not applicable Flash Backup No Table 39. Z_ACCL_OUT Bit Definitions Description X-axis accelerometer data; additional resolution bits Addresses 0x12, 0x13 Access R Table 38. Z_ACCL_OUT Register Definition Table 29. X_ACCL_LOW Bit Definitions Bits [15:0] Default Not applicable Table 37. Z_ACCL_LOW Bit Definitions Table 28. X_ACCL_LOW Register Definition Default Not applicable Z-Axis Accelerometer (Z_ACCL_LOW and Z_ACCL_OUT) Addresses 0x18, 0x19 Hex. 0x7D000000 0x00000002 0x00000001 0x00000000 0xFFFFFFFF 0xFFFFFFFE 0x83000000 X-Axis Accelerometer (X_ACCL_LOW and X_ACCL_OUT) Addresses 0x10, 0x11 The Y_ACCL_LOW (see Table 32 and Table 33) and Y_ACCL_ OUT (see Table 34 and Table 35) registers contain the accelerometer data for the y-axis. Table 36. Z_ACCL_LOW Register Definition Table 27. 32-Bit Accelerometer Data Format Examples Acceleration +8 g +0.25/215 mg +0.25/216 mg 0 -0.25/216 mg -0.25/215 mg -8 g Description Y-axis accelerometer data, high word; twos complement, 8 g range; 0 g = 0x0000, 1 LSB = 0.25 mg Description X-axis accelerometer data, high word; twos complement, 8 g range; 0 g = 0x0000, 1 LSB = 0.25 mg The X_ACCL_LOW (see Table 28 and Table 29) and X_ACCL_ OUT (see Table 30 and Table 31) registers contain the accelerometer data for the x-axis. Table 40. TEMP_OUT Register Definition Addresses 0x1C, 0x1D Default Not applicable Access R Flash Backup No Table 41. TEMP_OUT Bit Definitions Bits [15:0] Description Temperature data; twos complement, 1 LSB = 0.1C, 0C = 0x0000 Y-Axis Accelerometer (Y_ACCL_LOW and Y_ACCL_OUT) The TEMP_OUT register (see Table 40 and Table 41) provides a coarse measurement of the temperature inside of the ADIS16465. This data is most useful for monitoring relative changes in the thermal environment. Table 32. Y_ACCL_LOW Register Definition Table 42. TEMP_OUT Data Format Examples Addresses 0x14, 0x15 Default Not applicable Access R Flash Backup No Table 33. Y_ACCL_LOW Bit Definitions Bits [15:0] Description Y-axis accelerometer data; additional resolution bits Table 34. Y_ACCL_OUT Register Definition Addresses 0x16, 0x17 Default Not applicable Access R Flash Backup No Temperature (C) +105 +25 +0.2 +0.1 +0 +0.1 +0.2 -40 Rev. C | Page 20 of 33 Decimal +1050 +250 +2 +1 0 -1 -2 -400 Hex. 0x041A 0x00FA 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0xFE70 Binary 0000 0100 0001 1010 0000 0000 1111 1010 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1111 1110 0111 0000 Data Sheet ADIS16465 Table 43. TIME_STAMP Register Definition Addresses 0x1E, 0x1F Default Not applicable Access R Flash Backup No Table 44. TIME_STAMP Bit Definitions Bits [15:0] Description Time from the last pulse on the SYNC pin; offset binary format, 1 LSB = 49.02 s The TIME_STAMP register (see Table 43 and Table 44) works in conjunction with scaled sync mode (Register MSC_CTRL, Bits[4:2] = 010, see Table 105). The 16-bit number in TIME_ STAMP contains the time associated with the last sample in each data update relative to the most recent edge of the clock signal in the SYNC pin. For example, when the value in the UP_SCALE register (see Table 107) represents a scale factor of 20, DEC_RATE = 0, and the external SYNC rate = 100 Hz, the following time stamp sequence results: 0 LSB, 10 LSB, 21 LSB, 31 LSB, 41 LSB, 51 LSB, 61 LSB, 72 LSB, ..., 194 LSB for the 20th sample, which translates to 0 s, 490 s, ..., 9510 s, the time from the first SYNC edge. Data Update Counter (DATA_CNTR) The delta angle outputs represent an integration of the gyroscope measurements and use the following formula for all three axes (x-axis displayed): x , n D Default Not applicable Access R When using the internal sample clock, fS is equal to a nominal rate of 2000 SPS. For better precision in this measurement, measure the internal sample rate (fS) using the data ready signal on the DR pin (DEC_RATE = 0x0000, see Table 108), divide each delta angle result (from the delta angle output registers) by the data ready frequency, and multiply it by 2000. Each axis of the delta angle measurements has two output data registers. Figure 42 shows how these two registers combine to support a 32-bit, twos complement data format for the x-axis delta angle measurements. This format also applies to the y- and z-axes. X_DELTANG_OUT Flash Backup No BIT 15 X_DELTANG_LOW BIT 0 BIT 15 BIT 0 X-AXIS DELTA ANGLE DATA Figure 42. Delta Angle Output Data Structure Table 46. DATA_CNTR Bit Definitions Bits [15:0] where: x is the x-axis. n is the sample time, prior to the decimation filter. D is the decimation rate (DEC_RATE + 1, see Table 109). fS is the sample rate. d is the incremental variable in the summation formula. X is the x-axis rate of rotation (gyroscope). Table 45. DATA_CNTR Register Definition Addresses 0x22, 0x23 D 1 1 x , n D d x , n D d 1 2 fS d 0 15438-034 Time Stamp (TIME_STAMP) Description Data update counter, offset binary format Delta Angle Measurement Range When the ADIS16465 goes through the power-on sequence or when it recovers from a reset command, DATA_CNTR (see Table 45 and Table 46) starts with a value of 0x0000 and increments every time new data loads into the output registers. When the DATA_CNTR value reaches 0xFFFF, the next data update causes it to wrap back around to 0x0000, where it continues to increment every time new data loads into the output registers. DELTA ANGLES In addition to the angular rate of rotation (gyroscope) measurements around each axis (x, y, and z), the ADIS16465 also provides delta angle measurements that represent a calculation of angular displacement between each sample update. Table 47 shows the measurement range and scale factor for each ADIS16465 model. Table 47. Delta Angle Measurement Range and Scale Factor Model ADIS16465-1BMLZ ADIS16465-2BMLZ ADIS16465-3BMLZ Measurement Range, MAX () 360 720 2160 X-Axis Delta Angle (X_DELTANG_LOW and X_DELTANG_OUT) Table 48. X_DELTANG_LOW Register Definitions Addresses 0x24, 0x25 Default Not applicable Access R Flash Backup No Z-AXIS Table 49. X_DELTANG_LOW Bit Definitions z Y-AXIS Bits [15:0] X-AXIS Table 50. X_DELTANG_OUT Register Definitions x Addresses 0x26, 0x27 15438-033 y Description X-axis delta angle data; low word Figure 41. Delta Angle Axis and Polarity Assignments Rev. C | Page 21 of 33 Default Not applicable Access R Flash Backup No ADIS16465 Data Sheet Table 51. X_DELTANG_OUT Bit Definitions Delta Angle Resolution Bits [15:0] Table 60 and Table 61 show various numerical examples that demonstrate the format of the delta angle data in both 16-bit and 32-bit formats. Description X-axis delta angle data; twos complement, 0 = 0x0000, 1 LSB = MAX/215 (see Table 47 for MAX) The X_DELTANG_LOW (see Table 48 and Table 49) and X_DELTANG_OUT (see Table 50 and Table 51) registers contain the delta angle data for the x-axis. Table 60. 16-Bit Delta Angle Data Format Examples Y-Axis Delta Angle (Y_DELTANG_LOW and Y_DELTANG_OUT) Table 52. Y_DELTANG_LOW Register Definitions Addresses 0x28, 0x29 Default Not applicable Access R Flash Backup No Delta Angle () MAX x (215-1)/215 +MAX/214 +MAX/215 0 -MAX/215 -MAX/214 -MAX Decimal +32,767 +2 +1 0 -1 -2 -32,768 Hex. 0x7FFF 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0x8000 Binary 0111 1111 1110 1111 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0000 0000 Table 53. Y_DELTANG_LOW Bit Definitions Bits [15:0] Table 61. 32-Bit Delta Angle Data Format Examples Description Y-axis delta angle data; low word Table 54. Y_DELTANG_OUT Register Definitions Addresses 0x2A, 0x2B Default Not applicable Access R Flash Backup No Table 55. Y_DELTANG_OUT Bit Definitions Bits [15:0] Description Y-axis delta angle data; twos complement, 0 = 0x0000, 1 LSB = MAX/215 (see Table 47 for MAX) Delta Angle () +MAX x (231 - 1)/231 +MAX/230 +MAX/231 0 -MAX/231 -MAX/230 -MAX Decimal +2,147,483,647 +2 +1 0 -1 -2 -2,147,483,648 DELTA VELOCITY In addition to the linear acceleration measurements along each axis (x, y, and z), the ADIS16465 also provides delta velocity measurements that represent a calculation of linear velocity change between each sample update. The Y_DELTANG_LOW (see Table 52 and Table 53) and Y_DELTANG_OUT (see Table 54 and Table 55) registers contain the delta angle data for the y-axis. Z-Axis Delta Angle (Z_DELTANG_LOW and Z_DELTANG_OUT) Z-AXIS V z Table 56. Z_DELTANG_LOW Register Definitions Addresses 0x2C, 0x2D Default Not applicable Access R Hex. 0x7FFFFFFF 0x00000002 0x00000001 0x00000000 0xFFFFFFFF 0xFFFFFFFE 0x80000000 Flash Backup No Y-AXIS X-AXIS Vx V y Table 57. Z_DELTANG_LOW Bit Definitions Description Z-axis delta angle data; low word 15438-035 Bits [15:0] Table 58. Z_DELTANG_OUT Register Definitions Addresses 0x2E, 0x2F Default Not applicable Access R Figure 43. Delta Velocity Axis and Polarity Assignments Flash Backup No Table 59. Z_DELTANG_OUT Bit Definitions Bits [15:0] Description Z-axis delta angle data; twos complement, 0 = 0x0000, 1 LSB = MAX/215 (see Table 47 for MAX) The Z_DELTANG_LOW (see Table 56 and Table 57) and Z_DELTANG_OUT (see Table 58 and Table 59) registers contain the delta angle data for the z-axis. The delta velocity outputs represent an integration of the acceleration measurements and use the following formula for all three axes (x-axis displayed): Vx , n D D 1 1 a x , n D d a x , n D d 1 2 fS d 0 where: x is the x-axis. n is the sample time, prior to the decimation filter. D is the decimation rate (DEC_RATE + 1, see Table 109). fS is the sample rate. d is the incremental variable in the summation formula. aX is the x-axis acceleration. Rev. C | Page 22 of 33 Data Sheet ADIS16465 When using the internal sample clock, fS is equal to a nominal rate of 2000 SPS. For better precision in this measurement, measure the internal sample rate (fS) using the data ready signal on the DR pin (DEC_RATE = 0x0000, see Table 108), divide each delta angle result (from the delta angle output registers) by the data ready frequency, and multiply it by 2000. Each axis of the delta velocity measurements has two output data registers. Figure 44 shows how these two registers combine to support a 32-bit, twos complement data format for the delta velocity measurements along the x-axis. This format also applies to the y- and z-axes. Table 69. Y_DELTVEL_OUT Bit Definitions Bits [15:0] Description Y-axis delta velocity data; twos complement, 100 m/sec range, 0 m/sec = 0x0000; 1 LSB = 100 m/sec / 215 = ~0.003052 m/sec The Y_DELTVEL_LOW (see Table 66 and Table 67) and Y_DELTVEL_OUT (see Table 68 and Table 69) registers contain the delta velocity data for the y-axis. Z-Axis Delta Velocity (Z_DELTVEL_LOW and Z_DELTVEL_OUT) Table 70. Z_DELTVEL_LOW Register Definition BIT 15 X_ DELTVEL_LOW BIT 0 BIT 15 BIT 0 X-AXIS DELTA VELOCITY DATA Addresses 0x38, 0x39 15438-036 X_ DELTVEL_OUT Default Not applicable Access R Flash Backup No Table 71. Z_DELTVEL_LOW Bit Definitions Figure 44. Delta Velocity Output Data Structure Bits [15:0] X-Axis Delta Velocity (X_DELTVEL_LOW and X_DELTVEL_OUT) Description Z-axis delta velocity data; additional resolution bits Table 62. X_DELTVEL_LOW Register Definition Table 72. Z_DELTVEL_OUT Register Definition Addresses 0x30, 0x31 Addresses 0x3A, 0x3B Default Not applicable Access R Flash Backup No Default Not applicable Access R Table 63. X_DELTVEL_LOW Bit Definitions Table 73. Z_DELTVEL_OUT Bit Definitions Bits [15:0] Bits [15:0] Description X-axis delta velocity data; additional resolution bits Table 64. X_DELTVEL_OUT Register Definition Addresses 0x32, 0x33 Default Not applicable Access R Flash Backup No Table 65. X_DELTVEL_OUT Bit Definitions Bits [15:0] Table 74. 16-Bit Delta Velocity Data Format Examples Y-Axis Delta Velocity (Y_DELTVEL_LOW and Y_DELTVEL_OUT) Table 66. Y_DELTVEL_LOW Register Definition Access R Flash Backup No Table 67. Y_DELTVEL_LOW Bit Definitions Bits [15:0] Description Y-axis delta velocity data; additional resolution bits Table 68. Y_DELTVEL_OUT Register Definition Addresses 0x36, 0x37 Default Not applicable Access R The Z_DELTVEL_LOW (see Table 70 and Table 71) and Z_DELTVEL_OUT (see Table 72 and Table 73) registers contain the delta velocity data for the z-axis. Table 74 and Table 75 offer various numerical examples that demonstrate the format of the delta velocity data in both 16-bit and 32-bit formats. The X_DELTVEL_LOW (see Table 62 and Table 63) and X_DELTVEL_OUT (see Table 64 and Table 65) registers contain the delta velocity data for the x-axis. Default Not applicable Description Z-axis delta velocity data; twos complement, 100 m/sec range, 0 m/sec = 0x0000; 1 LSB = 100 m/sec / 215 = ~0.003052 m/sec Delta Velocity Resolution Description X-axis delta velocity data; twos complement, 100 m/sec range, 0 m/sec = 0x0000; 1 LSB = 100 m/sec / 215 = ~0.003052 m/sec Addresses 0x34, 0x35 Flash Backup No Flash Backup No Velocity (m/sec) +100 x (215 - 1)/215 +100/214 +100/215 0 -100/215 -100/214 -100 Decimal +32,767 +2 +1 0 -1 -2 -32,768 Hex. 0x7FFF 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0x8000 Binary 0111 1111 1111 1111 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0000 0000 Table 75. 32-Bit Delta Velocity Data Format Examples Velocity (m/sec) +100 x (231 - 1)/231 +100/230 +100/231 0 -100/231 -100/230 -100 Rev. C | Page 23 of 33 Decimal +2,147,483,647 +2 +1 0 -1 -2 +2,147,483,648 Hex. 0x7FFFFFFF 0x00000002 0x00000001 0x00000000 0xFFFFFFFF 0xFFFFFFFE 0x80000000 ADIS16465 Data Sheet CALIBRATION Table 82. YG_BIAS_HIGH Register Definition The signal chain of each inertial sensor (accelerometers and gyroscopes) includes the application of unique correction formulas, which are derived from extensive characterization of bias, sensitivity, alignment, response to linear acceleration (gyroscopes), and point of percussion (accelerometer location) over a temperature range of -40C to +85C, for each ADIS16465. These correction formulas are not accessible, but users do have the opportunity to adjust the bias for each sensor individually through user accessible registers. These correction factors follow immediately after the factory derived correction formulas in the signal chain, which processes at a rate of 2000 Hz when using the internal sample clock. Addresses 0x46, 0x47 Default 0x0000 Access R/W Flash Backup Yes Table 83. YG_BIAS_HIGH Bit Definitions Bits [15:0] Description Y-axis gyroscope offset correction factor, upper word Table 76. XG_BIAS_LOW Register Definition The YG_BIAS_LOW (see Table 80 and Table 81) and YG_BIAS_ HIGH (see Table 82 and Table 83) registers combine to allow users to adjust the bias of the y-axis gyroscopes. The data format examples in Table 12 also apply to the YG_BIAS_HIGH register, and the data format examples in Table 13 apply to the 32-bit combination of the YG_BIAS_LOW and YG_BIAS_HIGH registers. These registers influence the y-axis gyroscope measurements in the same manner that the XG_BIAS_LOW and XG_BIAS_HIGH registers influence the x-axis gyroscope measurements (see Figure 45). Addresses 0x40, 0x41 Calibration, Gyroscope Bias (ZG_BIAS_LOW and ZG_BIAS_HIGH) Calibration, Gyroscope Bias (XG_BIAS_LOW and XG_BIAS_HIGH) Default 0x0000 Access R/W Flash Backup Yes Table 77. XG_BIAS_LOW Bit Definitions Table 84. ZG_BIAS_LOW Register Definition Bits [15:0] Addresses 0x48, 0x49 Description X-axis gyroscope offset correction; lower word Default 0x0000 Access R/W Table 78. XG_BIAS_HIGH Register Definition Table 85. ZG_BIAS_LOW Bit Definitions Addresses 0x42, 0x43 Bits [15:0] Default 0x0000 Access R/W Flash Backup Yes Flash Backup Yes Description Z-axis gyroscope offset correction; lower word Table 79. XG_BIAS_HIGH Bit Definitions Table 86. ZG_BIAS_HIGH Register Definition Bits [15:0] Addresses 0x4A, 0x4B Description X-axis gyroscope offset correction factor, upper word The XG_BIAS_LOW (see Table 76 and Table 77) and XG_BIAS_ HIGH (see Table 78 and Table 79) registers combine to allow users to adjust the bias of the x-axis gyroscopes. The data format examples in Table 12 also apply to the XG_BIAS_HIGH register, and the data format examples in Table 13 apply to the 32-bit combination of the XG_BIAS_LOW and XG_BIAS_HIGH registers. See Figure 45 for an illustration of how these two registers combine and influence the x-axis gyroscope measurements. XG_BIAS_HIGH X_GYRO_OUT X_GYRO_LOW 15438-037 FACTORY CALIBRATION AND FILTERING X-AXIS GYRO XG_BIAS_LOW Figure 45. User Calibration Signal Path, Gyroscopes Default 0x0000 Access R/W Flash Backup Yes Table 87. ZG_BIAS_HIGH Bit Definitions Bits [15:0] Description Z-axis gyroscope offset correction factor, upper word The ZG_BIAS_LOW (see Table 84 and Table 85) and ZG_BIAS_ HIGH (see Table 86 and Table 87) registers combine to allow users to adjust the bias of the z-axis gyroscopes. The data format examples in Table 12 also apply to the ZG_BIAS_HIGH register, and the data format examples in Table 13 apply to the 32-bit combination of the ZG_BIAS_LOW and ZG_BIAS_HIGH registers. These registers influence the z-axis gyroscope measurements in the same manner that the XG_BIAS_LOW and XG_BIAS_HIGH registers influence the x-axis gyroscope measurements (see Figure 45). Calibration, Gyroscope Bias (YG_BIAS_LOW and YG_BIAS_HIGH) Calibration, Accelerometer Bias (XA_BIAS_LOW and XA_BIAS_HIGH) Table 80. YG_BIAS_LOW Register Definition Table 88. XA_BIAS_LOW Register Definition Addresses 0x44, 0x45 Addresses 0x4C, 0x4D Default 0x0000 Access R/W Flash Backup Yes Default 0x0000 Access R/W Table 81. YG_BIAS_LOW Bit Definitions Table 89. XA_BIAS_LOW Bit Definitions Bits [15:0] Bits [15:0] Description Y-axis gyroscope offset correction; lower word Rev. C | Page 24 of 33 Flash Backup Yes Description X-axis accelerometer offset correction; lower word Data Sheet ADIS16465 Table 90. XA_BIAS_HIGH Register Definition Table 97. ZA_BIAS_LOW Bit Definitions Addresses 0x4E, 0x4F Bits [15:0] Default 0x0000 Access R/W Flash Backup Yes Description Z-axis accelerometer offset correction; lower word Table 91. XA_BIAS_HIGH Bit Definitions Table 98. ZA_BIAS_HIGH Register Definition Bits [15:0] Addresses 0x56, 0x57 Description X-axis accelerometer offset correction, upper word The XA_BIAS_LOW (see Table 88 and Table 89) and XA_BIAS_ HIGH (see Table 90 and Table 91) registers combine to allow users to adjust the bias of the x-axis accelerometers. The data format examples in Table 26 also apply to the XA_BIAS_ HIGH register and the data format examples in Table 27 apply to the 32-bit combination of the XA_BIAS_LOW and XA_BIAS_HIGH registers. See Figure 46 for an illustration of how these two registers combine and influence the x-axis accelerometer measurements. XA_BIAS_HIGH X_ACCL_OUT X_ACCL_LOW 15438-038 FACTORY CALIBRATION AND FILTERING X-AXIS ACCL XA_BIAS_LOW Figure 46. User Calibration Signal Path, Accelerometers Default 0x0000 Access R/W Table 99. ZA_BIAS_HIGH Bit Definitions Bits [15:0] Description Z-axis accelerometer offset correction, upper word The ZA_BIAS_LOW (see Table 96 and Table 97) and ZA_BIAS_ HIGH (see Table 98 and Table 99) registers combine to allow users to adjust the bias of the z-axis accelerometers. The data format examples in Table 26 also apply to the ZA_BIAS_HIGH register and the data format examples in Table 27 apply to the 32-bit combination of the ZA_BIAS_LOW and ZA_BIAS_HIGH registers. These registers influence the z-axis accelerometer measurements in the same manner that the XA_BIAS_LOW and XA_BIAS_HIGH registers influence the x-axis accelerometer measurements (see Figure 46). Calibration, Accelerometer Bias (YA_BIAS_LOW and YA_BIAS_HIGH) Filter Control Register (FILT_CTRL) Table 92. YA_BIAS_LOW Register Definition Addresses 0x5C, 0x5D Addresses 0x50, 0x51 Default 0x0000 Access R/W Table 100. FILT_CTRL Register Definition Flash Backup Yes Bits [15:3] [2:0] Description Y-axis accelerometer offset correction; lower word Default 0x0000 Access R/W Flash Backup Yes Table 95. YA_BIAS_HIGH Bit Definitions Bits [15:0] Access R/W Flash Backup Yes Description Not used Filter Size Variable B; number of taps in each stage; N = 2B The FILT_CTRL register (see Table 100 and Table 101) provides user controls for the Bartlett window FIR filter (see Figure 23), which contains two cascaded averaging filters. For example, use the following sequence to set Register FILT_CTRL, Bits[2:0] = 100, which sets each stage to have 16 taps: 0xCC04 and 0xCD00. Figure 47 provides the frequency response for several settings in the FILT_CTRL register. Table 94. YA_BIAS_HIGH Register Definition Addresses 0x52, 0x53 Default 0x0000 Table 101. FILT_CTRL Bit Definitions Table 93. YA_BIAS_LOW Bit Definitions Bits [15:0] Flash Backup Yes Description Y-axis accelerometer offset correction, upper word 0 -20 -40 Calibration, Accelerometer Bias (ZA_BIAS_LOW and ZA_BIAS_HIGH) Default 0x0000 Access R/W -80 -100 -120 -140 0.001 Table 96. ZA_BIAS_LOW Register Definition Addresses 0x54, 0x55 -60 N=2 N=4 N = 16 N = 64 0.01 0.1 FREQUENCY (f/fS Flash Backup Yes Figure 47. Bartlett Window, FIR Filter Frequency Response (Phase Delay = N Samples) Rev. C | Page 25 of 33 1 15438-039 MAGNITUDE (dB) The YA_BIAS_LOW (see Table 92 and Table 93) and YA_BIAS_HIGH (see Table 94 and Table 95) registers combine to allow users to adjust the bias of the y-axis accelerometers. The data format examples in Table 26 also apply to the YA_BIAS_HIGH register, and the data format examples in Table 27 apply to the 32-bit combination of the YA_BIAS_LOW and YA_BIAS_ HIGH registers. These registers influence the y-axis accelerometer measurements in the same manner that the XA_BIAS_LOW and XA_BIAS_HIGH registers influence the x-axis accelerometer measurements (see Figure 46). ADIS16465 Data Sheet Range Identifier (RANG_MDL) Table 102. RANG_MDL Register Definition Addresses 0x5E, 0x5F Default Not applicable Access R Flash Backup No Bits [15:3] [3:2] [1:0] Description Not used Gyroscope measurement range 00 = 125/sec (ADIS16465-1BMLZ) 01 = 500/sec (ADIS16465-2BMLZ) 10 = reserved 11 = 2000/sec (ADIS16465-3BMLZ) Reserved, binary value = 11 POINT OF PERCUSSION ALIGNMENT REFERENCE POINT SEE MSC_CTRL[6] Figure 48. Point of Percussion Reference Point Linear Acceleration Effect on Gyroscope Bias Register MSC_CTRL, Bit 7 (see Table 105) provides an on/off control for the linear g compensation in the signal calibration routines of the gyroscope. The factory default contents in the MSC_CTRL register enable this compensation. To turn the compensation off, set Register MSC_CTRL, Bit 7 = 0, using the following sequence on the DIN pin: 0xE041, 0xE100. Miscellaneous Control Register (MSC_CTRL) Table 104. MSC_CTRL Register Definition Addresses 0x60, 0x61 Default 0x00C1 Access R/W 15438-040 Table 103. RANG_MDL Bit Definitions Flash Backup Yes Internal Clock Mode Table 105. MSC_CTRL Bit Definitions Bits [15:8] 7 6 5 [4:2] 1 0 Description Not used Linear g compensation for gyroscopes (1 = enabled) Point of percussion alignment (1 = enabled) Not used, always set to zero SYNC function setting 111 = reserved (do not use) 110 = reserved (do not use) 101 = pulse sync mode 100 = reserved (do not use) 011 = output sync mode 010 = scaled sync mode 001 = direct sync mode 000 = internal clock mode (default) SYNC polarity (input or output) 1 = rising edge triggers sampling 0 = falling edge triggers sampling DR polarity 1 = active high when data is valid 0 = active low when data is valid Point of Percussion Register MSC_CTRL, Bit 6 (see Table 105) offers an on/off control for the point of percussion alignment function, which maps the accelerometer sensors to the corner of the package shown in Figure 48. The factory default setting in the MSC_CTRL register activates this function. To turn this function off while retaining the rest of the factory default settings in the MSC_CTRL register, set Register MSC_CTRL, Bit 6 = 0, using the following command sequence on the DIN pin: 0xE081, then 0xE100. Register MSC_CTRL, Bits[4:2] (see Table 105), provide five different configuration options for controlling the clock (fSM; see Figure 20 and Figure 21), which controls data acquisition and processing for the inertial sensors. The default setting for Register MSC_CTRL, Bits[4:2] is 000 (binary), which places the ADIS16465 in internal clock mode. In this mode, an internal clock controls inertial sensor data acquisition and processing at a nominal rate of 2000 Hz. In this mode, each accelerometer data update comes from an average of two data samples (sample rate = 4000 Hz). Direct Sync Mode When Register MSC_CTRL, Bits[4:2] = 001, the ADIS16465 operates in direct sync mode. The signal on the SYNC pin directly controls the sample clock. In this mode, the internal processor collects gyroscope data samples on the rising edge of the clock signal (SYNC pin) and collects accelerometer data samples on both rising and falling edges of the clock signal. The internal processor averages both accelerometer samples (from rising and falling edges of the clock signal) together to produce a single data sample. Therefore, when operating the ADIS16465 in this mode, the clock signal (SYNC pin) must have a duty cycle of 50% and a frequency that is within the range of 1900 Hz to 2100 Hz. The ADIS16465 is capable of operating when the clock frequency (SYNC pin) is less than 1900 Hz, but with risk of performance degradation, especially when tracking dynamic inertial conditions (including vibration). Scaled Sync Mode When Register MSC_CTRL, Bits[4:2] = 010, the ADIS16465 operates in scaled sync mode that supports a frequency range of 1 Hz to 128 Hz for the clock signal on the SYNC pin. This mode of operation is particularly useful when synchronizing the data processing with a PPS signal from a global positioning system (GPS) receiver or with a synchronization signal from a video processing system. When operating in scaled sync mode, Rev. C | Page 26 of 33 Data Sheet ADIS16465 the frequency of the sample clock is equal to the product of the external clock scale factor, KECSF (from the UP_SCALE register, see Table 106 and Table 107), and the frequency of the clock signal on the SYNC pin. For example, when using a 1 Hz input signal, set UP_SCALE = 0x07D0 (KECSF = 2000 (decimal)) to establish a sample rate of 2000 SPS for the inertial sensors and the signal processing. Use the following sequence on the DIN pin to configure UP_SCALE for this scenario: 0xE2D0, then 0xE307. Table 106. UP_SCALE Register Definition Addresses 0x62, 0x63 Default 0x07D0 Access R/W Data Update Rate in External Sync Modes Flash Backup Yes When using the input sync option, in scaled sync mode (Register MSC_CTRL, Bits[4:2] = 010, see Table 105), the output data rate is equal to Table 107. UP_SCALE Bit Definitions Bits [15:0] Description KECSF; binary format (fSYNC x KECSF)/(DEC_RATE + 1) Output Sync Mode When Register MSC_CTRL, Bits[4:2] = 011, the ADIS16465 operates in output sync mode, which is the same as internal clock mode with one exception: the SYNC pin pulses when the internal processor collects data from the inertial sensors. Figure 49 provides an example of this signal. GYROSCOPE AND ACCELEROMETER DATA ACQUISITION where: fSYNC is the frequency of the clock signal on the SYNC pin. KESCF is the value from the UP_SCALE register (see Table 107). When using direct sync mode and pulse sync mode, KESCF = 1. Continuous Bias Estimation (NULL_CNFG) Table 110. NULL_CNFG Register Definition Addresses 0x66, 0x67 ACCELEROMETER DATA ACQUISITION Default 0x070A Access R/W Flash Backup Yes Table 111. NULL_CNFG Bit Definitions SYNC 15438-041 250s 500s Figure 49. Sync Output Signal, Register MSC_CTRL, Bits[4:2] = 011 Pulse Sync Mode When operating in pulse sync mode (Register MSC_CTRL, Bits[4:2] = 101), the internal processor only collects accelerometer samples on the leading edge of the clock signal, which enables the use of a narrow pulse width (see Table 2) in the clock signal on the SYNC pin. Using pulse sync mode also lowers the bandwidth on the inertial sensors to 370 Hz. When operating in pulse sync mode, the ADIS16465 provides the best performance when the frequency of the clock signal (SYNC pin) is within the range of 1000 Hz to 2100 Hz. The ADIS16465 is capable of operating when the clock frequency (SYNC pin) is less than 1000 Hz, but with risk of performance degradation, especially when tracking dynamic inertial conditions (including vibration). Decimation Filter (DEC_RATE) Table 108. DEC_RATE Register Definition Addresses 0x64, 0x65 The DEC_RATE register (see Table 108 and Table 109) provides user control for the averaging decimating filter, which averages and decimates the gyroscope and accelerometer data; it also extends the time that the delta angle and the delta velocity track between each update. When the ADIS16465 operates in internal clock mode (see Register MSC_CTRL, Bits[4:2], in Table 105), the nominal output data rate is equal to 2000/ (DEC_RATE + 1). For example, set DEC_RATE = 0x0013 to reduce the output sample rate to 100 SPS (2000 / 20), using the following DIN pin sequence: 0xE413, then 0xE500. Default 0x0000 Access R/W Flash Backup Yes Bits [15:14] 13 12 11 10 9 8 [7:4] [3:0] Description Not used Z-axis accelerometer bias correction enable (1 = enabled) Y-axis accelerometer bias correction enable (1 = enabled) X-axis accelerometer bias correction enable (1 = enabled) Z-axis gyroscope bias correction enable (1 = enabled) Y-axis gyroscope bias correction enable (1 = enabled) X-axis gyroscope bias correction enable (1 = enabled) Not used Time base control (TBC), range: 0 to 12 (default = 10); tB = 2TBC/2000, time base; tA = 64 x tB, average time The NULL_CNFG register (see Table 110 and Table 111) provides the configuration controls for the continuous bias estimator (CBE), which associates with the bias correction update command in Register GLOB_CMD, Bit 0 (see Table 113). Register NULL_ CNFG, Bits[3:0], establishes the total average time (tA) for the bias estimates and Register NULL_CNFG, Bits[13:8], provide the on/off controls for each sensor. The factory default configuration for the NULL_CNFG register enables the bias null command for the gyroscopes, disables the bias null command for the accelerometers, and sets the average null time to ~32 sec. Global Commands (GLOB_CMD) Table 109. DEC_RATE Bit Definitions Table 112. GLOB_CMD Register Definition Bits [15:11] [10:0] Addresses 0x68, 0x69 Description Don't care Decimation rate, binary format, maximum = 1999 Rev. C | Page 27 of 33 Default Not applicable Access W Flash Backup No ADIS16465 Data Sheet 7. Report the pass and fail result to Register DIAG_STAT, Bit 5 (see Table 10). Table 113. GLOB_CMD Bit Definitions Bits [15:8] 7 [6:5] 4 3 2 1 0 Description Not used Software reset Not used Flash memory test Flash memory update Sensor self test Factory calibration restore Bias correction update Motion during the execution of this test can indicate a false failure. Factory Calibration Restore The GLOB_CMD register (see Table 112 and Table 113) provides trigger bits for several operations. Write a 1 to the appropriate bit in GLOB_CMD to start a particular function. During the execution of these commands, data production stops, pulsing stops on the DR pin, and the SPI interface does not respond to requests. Table 1 provides the execution time for each GLOB_CMD command. Software Reset Use the following DIN sequence to set Register GLOB_CMD, Bit 1 = 1, to restore the factory default settings for the MSC_ CTRL, DEC_RATE, and FILT_CTRL registers and to clear all user configurable bias correction settings: 0xE802, then 0xE900. Executing this command results in writing 0x0000 to the following registers: XG_BIAS_LOW, XG_BIAS_HIGH, YG_BIAS_LOW, YG_BIAS_HIGH, ZG_BIAS_LOW, ZG_BIAS_HIGH, XA_BIAS_ LOW, XA_BIAS_HIGH, YA_BIAS_LOW, YA_BIAS_HIGH, ZA_BIAS_LOW, and ZA_BIAS_HIGH. Bias Correction Update Use the following DIN pin sequence to set Register GLOB_CMD, Bit 0 = 1, to trigger a bias correction, using the correction factors from the CBE (see Table 111): 0xE801, then 0xE900. Use the following DIN sequence to set Register GLOB_CMD, Bit 7 = 1, which triggers a reset: 0xE880, then 0xE900. This reset clears all data, and then restarts data sampling and processing. This function provides a firmware alternative to toggling the RST pin (see Table 5, Pin 8). Firmware Revision (FIRM_REV) Flash Memory Test Table 115. FIRM_REV Bit Definitions Use the following DIN sequence to set Register GLOB_CMD, Bit 4 = 1, which tests the flash memory: 0xE810, then 0xE900. The command performs a CRC computation on the flash memory (excluding user register locations) and compares it to the original CRC value, which comes from the factory configuration process. If the current CRC value does not match the original CRC value, Register DIAG_STAT, Bit 6 (see Table 10), rises to 1, indicating a failing result. Bits [15:0] Flash Memory Update Table 116. FIRM_DM Register Definition Use the following DIN sequence to set Register GLOB_CMD, Bit 3 = 1, which triggers a backup of all user configurable registers in the flash memory: 0xE808, then 0xE900. Register DIAG_ STAT, Bit 2 (see Table 10), identifies success (0) or failure (1) in completing this process. Sensor Self Test Use the following DIN sequence to set Register GLOB_CMD, Bit 2 = 1, which triggers the self test routine for the inertial sensors: 0xE804, then 0xE900. The self test routine uses the following steps to validate the integrity of each inertial sensor: 1. Measure the output on each sensor. 2. Activate an internal stimulus on the mechanical elements of each sensor to move them in a predictable manner and create an observable response in the sensors. 3. Measure the output response on each sensor. 4. Deactivate the internal stimulus on each sensor. 5. Calculate the difference between the sensor measurements from Step 1 (stimulus is off) and from Step 3 (stimulus is on). 6. Compare the difference with internal pass and fail criteria. Table 114. FIRM_REV Register Definition Addresses 0x6C, 0x6D Default Not applicable Access R Flash Backup No Description Firmware revision, binary coded decimal (BCD) format The FIRM_REV register (see Table 114 and Table 115) provides the firmware revision for the internal firmware. This register uses a BCD format, where each nibble represents a digit. For example, if FIRM_REV = 0x0104, the firmware revision is 1.04. Firmware Revision Day and Month (FIRM_DM) Addresses 0x6E, 0x6F Default Not applicable Access R Flash Backup No Table 117. FIRM_DM Bit Definitions Bits [15:8] [7:0] Description Factory configuration month, BCD format Factory configuration day, BCD format The FIRM_DM register (see Table 116 and Table 117) contains the month and day of the factory configuration date. Register FIRM_DM, Bits[15:8], contain digits that represent the month of the factory configuration. For example, November is the 11th month in a year and is represented by Register FIRM_DM, Bits[15:8] = 0x11. Register FIRM_DM, Bits[7:0], contain the day of factory configuration. For example, the 27th day of the month is represented by Register FIRM_DM, Bits[7:0] = 0x27. Firmware Revision Year (FIRM_Y) Table 118. FIRM_Y Register Definition Addresses 0x70, 0x71 Rev. C | Page 28 of 33 Default Not applicable Access R Flash Backup No Data Sheet ADIS16465 Table 119. FIRM_Y Bit Definitions Table 129. USER_SCR_3 Bit Definitions Bits [15:0] Bits [15:0] Description Factory configuration year, BCD format The FIRM_Y register (see Table 118 and Table 119) contains the year of the factory configuration date. For example, the year, 2017, is represented by FIRM_Y = 0x2017. Product Identification (PROD_ID) Table 120. PROD_ID Register Definition Default 0x4051 Access R Flash Backup No The USER_SCR_1 (see Table 124 and Table 125), USER_SCR_2 (see Table 126 and Table 127), and USER_SCR_3 (see Table 128 and Table 129) registers provide three locations for the user to store information. For nonvolatile storage, use the manual flash memory update command (Register GLOB_CMD, Bit 3, see Table 113), after writing information to these registers. Flash Memory Endurance Counter (FLSHCNT_LOW and FLSHCNT_HIGH) Table 121. PROD_ID Bit Definitions Table 130. FLSHCNT_LOW Register Definition Bits [15:0] Addresses 0x7C, 0x7D Description Product identification = 0x4051 The PROD_ID register (see Table 120 and Table 121) contains the numerical portion of the device number (16,475). See Figure 33 for an example of how to use a looping read of this register to validate the integrity of the communication. Default Not applicable Access R Flash Backup No Table 131. FLSHCNT_LOW Bit Definitions Bits [15:0] Description Flash memory write counter, low word Serial Number (SERIAL_NUM) Table 132. FLSHCNT_HIGH Register Definition Table 122. SERIAL_NUM Register Definition Addresses 0x7E, 0x7F Addresses 0x74, 0x75 Default Not applicable Access R Flash Backup No Bits [15:0] Description Lot specific serial number Scratch Registers (USER_SCR_1 to USER_SCR_3) Table 124. USER_SCR_1 Register Definition Addresses 0x76, 0x77 Default Not applicable Access R/W Flash Backup Yes Table 125. USER_SCR_1 Bit Definitions Bits [15:0] Description User defined Access R/W Flash Backup Yes Table 127. USER_SCR_2 Bit Definitions Bits [15:0] Description User defined Table 128. USER_SCR_3 Register Definition Addresses 0x7A, 0x7B Default Not applicable Access R/W Description Flash memory write counter, high word 600 RETENTION (Years) Default Not applicable Flash Backup No The FLSHCNT_LOW (see Table 130 and Table 131) and FLSHCNT_HIGH (see Table 132 and Table 133) registers combine to provide a 32-bit, binary counter that tracks the number of flash memory write cycles. In addition to the number of write cycles, the flash memory has a finite service lifetime, which depends on the junction temperature. Figure 50 provides guidance for estimating the retention life for the flash memory at specific junction temperatures. The junction temperature is approximately 7C above the case temperature. Table 126. USER_SCR_2 Register Definition Addresses 0x78, 0x79 Access R Table 133. FLSHCNT_HIGH Bit Definitions Bits [15:0] Table 123. SERIAL_NUM Bit Definitions Default Not applicable 450 300 150 Flash Backup Yes 0 30 40 55 70 85 100 125 JUNCTION TEMPERATURE (C) Figure 50. Flash Memory Retention Rev. C | Page 29 of 33 135 150 15438-042 Addresses 0x72, 0x73 Description User defined ADIS16465 Data Sheet APPLICATIONS INFORMATION ASSEMBLY AND HANDLING TIPS BREAKOUT BOARD Mounting Tips The ADIS16IMU4/PCBZ breakout board provides a ribbon cable interface for simple connection to an embedded processor development system. Figure 52 shows the electrical schematic, and Figure 53 shows a top view for this breakout board. J2 mates directly to the electrical connector on the ADIS16465, and J1 easily mates to a 1 mm ribbon cable system. 0.019685 [0.5000] (TYP) 0.0240 [0.610] 0.054 [1.37] 0.0394 [1.00] J1 DR SYNC SCLK DOUT DIN CS DNC RST DNC DNC VDD DNC GND DNC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1 0805 10F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C2 0603 1F 0.1800 [4.57] 15438-044 The ADIS16465 package supports installation onto a PCB or rigid enclosure, using three M2 or 2-56 machine screws, using a torque that is between 20 inch ounces and 40 inch ounces. When designing a mechanical interface for the ADIS16465, avoid placing unnecessary translational stress on the electrical connector because this can influence the bias repeatability behaviors of the inertial sensors. When the same PCB also has the mating connector, the use of passthrough holes for the mounting screws may be required. Figure 51 shows a detailed view of the PCB pad design when using one of the connector variants in the CLM-107-02 family. 15438-043 Figure 52. ADIS16IMU4/PCBZ Electrical Schematic 0.0394 [1.00] 0.022 DIA (TYP) 0.022 DIA THROUGH HOLE (TYP) NONPLATED THROUGH HOLE 2x NONPLATED THROUGH HOLE Figure 51. Mating Connector Design Detail POWER SUPPLY CONSIDERATIONS The ADIS16465 contains 6 F of decoupling capacitance across the VDD and GND pins. When the VDD voltage raises from 0 V to 3.3 V, the charging current for this capacitor bank imposes the following current profile (in amperes): I DD t C dVDD dVDD t 6 10 6 dt dt Figure 53. ADIS16IMU4/PCBZ Top View J1 RST 1 2 SCLK CS 3 4 DOUT DIN DNC 5 6 GND 7 8 GND GND 9 10 VDD VDD 11 12 VDD DR 13 14 SYNC NC 15 16 NC 15438-046 For example, if VDD follows a linear ramp from 0 V to 3.3 V, in 66 s, the charging current is 300 mA for that timeframe. The ADIS16465 also contains embedded processing functions that present transient current demands during initialization or reset recovery operations. During these processes, the peak current demand reaches 250 mA and occurs at a time that is approximately 40 ms after VDD reaches 3.0 V (or ~40 ms after initiating a reset sequence). 15438-045 where: IDD(t) is the current demand on the VDD pin during the initial power supply ramp, with respect to time. C is the internal capacitance across the VDD and GND pins (6 F). VDD(t) is the voltage on the VDD pin, with respect to time. Figure 54. ADIS16IMU4/PCBZ J1 Pin Assignments Rev. C | Page 30 of 33 Data Sheet ADIS16465 SERIAL PORT OPERATION DIGITAL RESOLUTION OF GYROSCOPES AND ACCELEROMETERS Maximum Throughput When operating with the maximum output data (DEC_RATE = 0x0000, as described in Table 109), the maximum SCLK rate (defined in Table 2) and minimum stall time, the SPI port can support up to 12, 16-bit register reads in between each pulse of the data ready signal. Attempting to read more than 12 registers can result in a datapath overrun error in the DIAG_STAT register (see Table 10). The serial port stall time (tSTALL) to meet these requirements must be no more than 10% greater than the minimum specification for tSTALL in Table 2. The number of allowable registers reads between each pulse on the data ready line increases proportionally with the decimation rate (set by the DEC_RATE register, see Table 109). For example, when the decimation rate equals 3 (DEC_RATE = 0x0002), the SPI is able to support up to 36 register reads, assuming maximum SCLK rate and minimum stall times in the protocol. Decreasing the SCLK rate and increasing the stall time lowers the total number of register reads supported by the ADIS16465 before a datapath overrun error occurs. This limitation of reading 12, 16-bit registers does not impact the ability of the user to access the full precision of the gyroscopes and accelerometers if the factory default settings of DEC_RATE = 0x0000 and FILT_CTRL = 0x0000 are used. In this case, the data width for the gyroscope and accelerometer data is 16 bits, and application processors can acquire all relevant information through the X_GYRO_OUT, Y_GYRO_OUT, Z_GYRO_OUT, X_ACCEL_OUT, Y_ACCEL_OUT, and Z_ACCEL_OUT registers. Thirty-two bit reads of the sensor data do not provide additional precision in this case. See the Gyroscope Data Width (Digital Resolution) section and the Accelerometer Data Width (Digital Resolution) section for more information. Serial Port SCLK Underrun/Overrun Conditions The serial port operates in 16-bit segments and it is critical that the number of SCLK cycles be equal to an integer multiple of 16 when the CS pin is low. Failure to meet this condition causes the serial port controller inside of the ADIS16465 to be unable to correctly receive and respond to new requests. If too many SCLK cycles are received before the CS pin is deasserted, the user can recover serial port operation by asserting CS, providing 17 rising edges on the SCLK line, deasserting CS, and then attempting to correctly read the PROD_ID (or other read-only) register on the ADIS16465. The user should repeat these steps up to a maximum of 15 times until the correct data is read. If CS is deasserted before enough SCLK cycles are received, the user must either power cycle or issue a hard reset (using the RST pin) to regain SPI port access. Gyroscope Data Width (Digital Resolution) The decimation filter (DEC_RATE register, see Table 109) and Bartlett window filter (FILT_CTRL register, see Table 101) have direct influence over the total number of bits in the output data registers, which contain relevant information. When using the factory default settings (DEC_RATE = 0x0000, FILT_CTRL = 0x0000) for these filters, the data width for the gyroscope data width is 16 bits, which means that application processors can acquire all relevant information through the X_GYRO_OUT, Y_GYRO_OUT, and Z_GYRO_OUT registers. The X_GYRO_LOW, Y_GYRO_LOW, and Z_GYRO_ LOW registers capture the bit growth that comes from each accumulation operation in the decimation and Bartlett window filters. When using these filters (DEC_RATE 0x0000 and/or FILT_CTRL 0x0000), the bit growth is equal to the square root of the number of summations in each filter stage. For example, when DEC_RATE = 0x0007, the decimation filter adds eight (7 + 1 = 8, see Table 109) successful samples together, which causes the data width to increase by 3 bits (80.5 = 3). When FILT_CTRL = 0x0002, both stages in the Bartlett window filter use four (22 = 4, see Table 101) summation operations, which increases the data width by two bits (40.5 = 2). When using both DEC_RATE = 0x0007 and FILT_CTRL = 0x0002, the total bit growth is 7 bits, which increases the overall data width to 23 bits. Accelerometer Data Width (Digital Resolution) The decimation filter (DEC_RATE register, see Table 109) and Bartlett window filter (FILT_CTRL register, see Table 101) have direct influence over the total number of bits in the output data registers, which contain relevant information. When using the factory default settings (DEC_RATE = 0x0000, FILT_CTRL = 0x0000) for these filters, the data width for the accelerometer data is 20 bits. The X_ACCL_OUT, Y_ACCL_OUT, and Z_ACCL_ OUT registers contain the most significant 16 bits of this data, while the remaining (least significant) bits are in the upper 4 bits of the X_ACCL_LOW, Y_ACCL_LOW, and Z_ACCL_ LOW registers. Because the total noise (0.6 mg rms, see Table 1) in the accelerometer data (DEC_RATE = 0x0000, FILT_CTRL = 0x0000) is greater than the 16-bit quantization noise (0.25 mg / 120.5 = 0.072 mg), application processors can acquire all relevant information through the X_ACCL_OUT, Y_ACCL_OUT, and Z_ACCL_OUT registers. This setup enables applications to preserve optimal performance, while using the burst read (see Figure 32), which only provides 16-bit data for the accelerometers. The X_ACCL_LOW, Y_ACCL_LOW, and Z_ACCL_LOW registers also capture the bit growth that comes from each accumulation operation in the decimation and Bartlett window filters. When using these filters (DEC_RATE 0x0000 and/or FILT_CTRL 0x0000), the bit growth is proportional to the square root of the number of summations in each filter stage. For example, when DEC_RATE = 0x0001, the decimation filter Rev. C | Page 31 of 33 ADIS16465 Data Sheet adds two (1 + 1 = 2, see Table 109) successful samples together, which causes the data width to increase by 1 bit (20.5 = 1). When FILT_CTRL = 0x0001, both stages in the Bartlett window filter use two (21 = 2, see Table 101) summation operations, which increases the data width by 1 bit (20.5 = 1). When using both DEC_RATE = 0x0001 and FILT_CTRL = 0x0001, the total bit growth is 3 bits, which increases the overall data width to 23 bits. PC-BASED EVALUATION TOOLS The ADIS16IMU4/PCBZ provides a simple way to connect the ADIS16465 to the EVAL-ADIS2 evaluation system, which provides a PC-based method for evaluation of basic function and performance. For more information, visit the EVALADIS2 Wiki Guide. Rev. C | Page 32 of 33 Data Sheet ADIS16465 ORDERING INFORMATION OUTLINE DIMENSIONS 22.47 22.40 22.33 R 2.75 O 2.40 22.47 22.40 22.33 18.25 BSC 24.37 24.30 24.23 0.19 7.10 REF TOP VIEW 14.20 BSC 1.00 BSC PITCH 1.50 END VIEW 0.57 11-09-2018-B 9.07 9.00 8.93 Figure 55. 14-Lead Module with Connector Interface [MODULE] (ML-14-6) Dimensions shown in millimeters ORDERING GUIDE Model1 ADIS16465-1BMLZ ADIS16465-2BMLZ ADIS16465-3BMLZ 1 Temperature Range -40C to +105C -40C to +105C -40C to +105C Package Description 14-Lead Module with Connector Interface [MODULE] 14-Lead Module with Connector Interface [MODULE] 14-Lead Module with Connector Interface [MODULE] Z = RoHS Compliant Part. (c)2017-2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15438-4/20(C) Rev. C | Page 33 of 33 Package Option ML-14-6 ML-14-6 ML-14-6