1
Standard Products
UT54ACTQ16245
RadHard CMOS 16-bit Bidirectional Transceiver, TTL Inputs, and
Three-State Outputs
Datasheet
May 16, 2012
www.aeroflex.com/radhard
FEATURES
16 non-inverting bidirectio nal buffers with three-state out-
puts
Guaranteed simultaneously switching noise level and
dynamic threshold performance
Separate control logic for each byte
0.6m Commercial RadHardTM CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
High speed, low power consumption
Output source/sink 24mA
Standard Microcircuit Drawing 5962-06244
- QML compliant part
Package:
- 48-lead flatpack, 25 mi l pi tch (.390 x .640)
DESCRIPTION
The 16-bit wide UT54ACTQ1 6245 transceiver is built using
Aeroflex’s Commercial RadHardTM epitaxial CMOS technol-
ogy and is ideal for space applications. This high speed, low
power UT54ACTQ16245 transceiver is designed to perform
asynchronous two-way communication and signal buffering.
Balanced outputs and low "on" outpu t impe dance mak e the
UT54ACTQ16245 well sui ted for dri ving high capacitance
loads and low impedance backplanes. The Transmit/Receive
input (T/R) controls the direction of data flow through the de-
vice. The output enable input (OEn, active low) overrides the
direction co ntrol (T/R) and disables both the A and B ports by
placing them in a high impedance state. These signals can be
driven from either port A or B. The direction and output enable
controls operate these devices as either two independent 8-bit
transceivers or one 16-bit transceiver
LOGIC SYMBOL
PIN DESCRIP TION
FUNCTION TABLE
Pin Names Description
OEnOutput Enable Input (Active Low)
T/RnDirection Control Inputs
A0-A15 Side A Inputs or 3-State Outputs
B0-B15 Side B Inputs or 3-State Outputs
ENABLE
OEnDIRECTION
T/RnOPERATION
L L B Data To A Bus
L H A Data To B Bus
H X Isolation, High-Z State on
Bus A and Bus B
(48)
OE1
G2
(47)
A0
(46)
A1 (44)
(2) B0
(5)
(3) B1
A2 (43)
A3 (41)
A4 (40)
A5
B2
(9) B5
(8) B4
(6) B3
(38)
A6 (37)
A7 (12) B7
(11) B6
(1)
T/R11EN1 (BA)
1EN2 (AB)
11 12
(25)
OE2G1 (24) T/R2
21 22
(36)
A8 B8
(13)
(35)
A9 (33)
A10 (32)
A11 (30)
A12 (29)
A13 (27)
A14 (26)
A15
(16) B9
B10
(20) B13
(19) B12
(17) B11
(23) B15
(22) B14
(14)
2EN1 (BA)
2EN2 (AB)
2
PINOUTS
1
2
3
4
5
7
6
48
47
46
45
44
42
43
T/R1
B0
B1
VSS
B2
B3
VDD
OE1
A0
A1
VSS
A2
VDD
841
B4 A4
A3
940
B5 A5
10 39
VSS VSS
48-Lead Flatpack
Top View
B6
B7
B8
B9
VSS
B10
B11
VDD
B12
B13
11
12
13
14
15
17
16
18
19
20
VSS
B14
B15
T/R2
21
22
23
24
38
37
36
35
34
32
33
A6
A7
A8
A9
VSS
A11
31 VDD
A10
30 A12
29 A13
28 VSS
27 A14
26 A15
25 OE2
3
LOGIC DIAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
T/R1(1)
(47)
(48)
(2)
(46)
(3)
(44)
(5)
(43)
(6)
(41)
(8)
(40)
(9)
(38)
(11)
(37)
(12)
B0
B1
B2
B5
B4
B3
B7
B6
OE1
A8
A9
A10
A11
A12
A13
A14
A15
T/R2(24)
(36)
(25)
(13)
(35)
(14)
(33)
(16)
(32)
(17)
(30)
(19)
(29)
(20)
(27)
(22)
(26)
(23)
B8
B9
B10
B13
B12
B11
B15
B14
OE2
4
RADIATION HARDNESS SPECIFICATIONS 1
Notes:
1. Logic will not latchup during radiation exposure within the limits VDD = 5.5V, T = 125oC.
2. Not tested, inherent of CMOS technology.
3. This device contains no memory storage elements which can be upset.
ABSOLUTE MAXIMUM RATINGS1
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E5 rad(Si)
SEL Latchup >108 MeV-cm2/mg
SEU Onset Let N/A3MeV-cm2/mg
Neutron Fluence21.0E14 n/cm2
SYMBOL PARAMETER LIMIT (Mil only) UNITS
VI/O Voltage any pin during operation -.3 to VDD +.3 V
VDD Supply voltage -0.3 to 6.0 V
TSTG Storage Temperature range -65 to +150 C
TJMaximum junction temperature +175 C
JC Thermal resistance junction to case 20 C/W
IIDC input current 10 mA
PDMaximum p ower dissipation 310 mW
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage 4.5 to 5.5 V
VIN Input voltage any pin 0 to VDD V
TCTemperature range -55 to + 125 C
tINRISE
tINFALL
Maximum input rise or fall time
(VIN transitioning between VIL (max) and VIH (min)) 20 ns
5
DC ELECTRICAL CHARACTERISTICS 1
( -55C < TC < +125C)
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIL Low level input voltage2 VDD from 4.5V to 5.5V 0.8 V
VIH High level input voltag e2 VDD from 4.5 V to 5.5V 2.0 V
IIN Input leakage current VDD from 4.5V to 5.5V
VIN = VDD or VSS
-1 1 A
IOZ Three-state output leakage current VDD from 4.5V to 5.5V
VIN = VDD or VSS
-10 10 A
IOS Short-circuit output current 3,4 VO = VDD or VSS
VDD from 4.5V to 5.5V
-600 600 mA
VOL1 Low-level output voltage5IOL= 24mA -55C, 25C
IOL= 24mA +125C
IOL= 100A
VIN = 2.0V or 0.8V
VDD = 4.5V to 5.5V
0.35
0.5
0.2
V
VOL2 Low-level output voltage5,6 IOL= 50 mA -55C, 25C
VIN = 2.0V or 0.8V
VDD = 5.5V
0.8 V
VOH1 High-level output voltage5IOH= -24 mA -55C, 25C
IOL= -24mA +125C
IOH= -100A
VIN = 2.0V or 0.8V
VDD = 4.5V to 5.5V
VDD - 0.64
VDD - 0.8
VDD - 0.2
V
VOH2 High-level output voltage5, 6 IOH= -50 mA -55C, 25C
VIN = 2.0V or 0.8V
VDD = 5.5V
VDD - 1.1 V
VIC+ Positive input clamp voltage For input under test, IIN = 18mA
VDD = 0.0V
0.4 1.5 V
VIC- Negative input clamp voltage For input under test, IIN = -18mA
VDD = open
-1.5 -0.4 V
Ptotal Power dissipation 7, 8, 9 CL = 20pF
VDD from 4.5V to 5.5V
1.5 mW/MHz
+125C
+125CVDD - 1.3
1.0
6
Notes:
1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-ST D-883, Method 1019.
2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above spec ified range, but are
guaranteed to VIH(min) and VIL(max).
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. Supplied as a design limit, but not guaranteed or tested.
5. Per MIL-PRF-3853 5, for current density 5.0E5 amps/cm 2, the maximum product of load capacitance (per output buf fer) times frequency should not exceed 3,765
pF-MHz.
6. T ran smission driving tests are performed at VDD = 5.5V, only one output loaded at a time with a duration not to exceed 2ms. The test is guaranteed, if not tested,
for VIN=VIH minimum or VIL maximum.
7. Guaranteed by characterization.
8. Power does not include power contribution of any CMOS output sink current.
9. Power dissipation specified per switching output.
10.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
1 1. This test is for qualification only . VSS and VDD bounce tests are perfor med on a non-switching (quiescent) output and are used to measure the magnitude of induced
noise caused by other simultaneously switching outputs. The test is perfor med on a low noise bench test fixture.
IDDQ Standby Supply Current VDD
Pre-Rad 25oC
Pre-Rad -55oC to +125oC
Post-Rad 25oC
VIN = VDD or VSS
VDD = 5.5V
OEn = VDD
OEn = VDD
OEn = VDD
10
160
160
A
IDDQ Quiescent Supply Current Delta, TTL in-
put level For input under test
VIN = VDD - 2.1V
For other inputs
VIN = VDD or VSS
VDD = 5.5V
1.6
mA
CIN Input capacitance10 = 1MHz @ 0V
VDD from 4.5V to 5.5V
15 pF
COUT Output capacitance10 = 1MHz @ 0V
VDD from 4.5V to 5.5V
15 pF
VOLP
VOLV
Low level VSS bounce noise11 VIN = 3.0V, VIL = 0.0V, TA=+25oC,
VDD = 5.0V
1200
-1500 mV
mV
VOHP
VOHV
High level VDD bounce noise11 See figure "Quiet Output Under Test" VOH
+1500
VOH
-1600
mV
mV
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AC ELECTRICAL CHARACTERISTICS1
(VDD = 5V 10%, -55C < TC < +125C)
Notes:
1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019.
2. T/Rn to bus times are guaranteed by design, but not tested. OEx to bus times are tested
3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs low-to-high.
4. Differential skew is defined as a comparison of any two output transitions high-to-low vs. low-to-high and low-to-high vs high-to low.
5. Guaranteed by characterization, but not tested.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
tPLH Propagation delay Data to Bus CL = 40 pF 3 8.5 ns
tPHL Propagation delay Data to Bus RL = 5038.5ns
tPZL1 Output enable time OEn to Bus See figure "Test
Load" 310ns
tPZH1 Output enable time OEn to Bus 3 10 ns
tPLZ1 Output disable time OEn to Bus hi gh impedance 2.5 9.5 ns
tPHZ1 Output disable time OEn to Bus hi gh impedance 2.5 9.5 ns
tPZL22Output enable time T/Rn to Bus 2.5 13 ns
tPZH22Output enable time T/Rn to Bus 2.5 13 ns
tPLZ22Output disable tim e T/Rn to Bus high impedance 1.5 15 ns
tPHZ22Output disable time T/Rn to Bus high impedance 1.5 15 ns
tSKEW3Skew between outputs - 1.0 ns
tDSKEW4Differential skew between outputs - 1.25 ns
tSKEWPP3,5 Part-to-Part output skew 500 ps
8
tPLZn
tPZHn
tPZLn
tPHZN
Control Input
5V Output
Normally Low
Enable Disable Times
5V Output
Normally High
3.0V
1.5V
0V
VDD/2
VDD/2
.8VDD
.2VDD
VDD/2+0.2
VDD/2-0.2 .2VDD + .2V
.8VDD - .2V
tPHL
Propagation Delay
Input
Output
3.0V
1.5V
0V
tPLH
VOH
VOL
VDD/2
Bounce Noise
Active Outputs VOH
VOL
Quiet Outputs
Under Test VOLP
VOLV
VOL
VOHP VOH
VOHV
VSS
Test Load or Equivalent1
VDD
40pf 100ohms
VDD
100ohms
Notes
1. Equivalent test circuit means that DUT performance will be correlated and remain guaranteed to the applicable test circuit, above, whenever a test platform
change necessitates a deviation from the applicable test circuit.
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PACKAGE
10
ORDERING INFORMATION
UT54ACTQ16245: SMD
Lead Finish: (NOTES 1 & 2)
(A) = Hot solder dip
(C) = Gold
(X) = Factory op tio n (g old or sold er)
Case Outline:
(X) = 48 lead BB FP (Gold only)
Class Designator:
(Q) = Class Q
(V) = Class V
Device Type
(01) = 16-bit Bi-Directional Transceiver (4.5V - 5.5V)
Drawing Number: 06244
Total Dose: (NOTE 3)
(R) = 1E5 rad(Si)
Federal Stock Class Designator: No options
5962 R 06244 ** * * *
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering. QML Q not available without radiation hardening.
11
UT54ACTQ16245
UT54 *** ****** -* * *
Lead Finish: (NOTES 1 & 2)
(A) = Hot Solder Dip
(C) = Gold
(X) = Factory Option (Gold or Solder)
Screening: (NOTES 3 & 4)
(C) = Mil Temp
(P) = Prototype
Package Type:
(U) = 48-lead BB FP
Part Number:
(16245) = 16-bit Bi-Directional Transceiver
I/O Type:
(ACTQ)= CMOS compatible I/O Level
Aeroflex Core Part Number
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Manufacturing Flows Document. T ested at 25C only . Lead finish is Gold "C" only . Radiation neither tested nor guaranteed.
4. Military T emperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55C, room temp, and 125C. Radiation neither
tested nor gu ara nteed.
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changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
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