Advanced Power Electronics Corp. Technology Licensed from International Rectifier APU3048 SYNCHRONOUS PWM CONTROLLER WITH OVER CURRENT PROTECTION FEATURES DESCRIPTION LDO Controller with 40mA drive Dual Synchronous Controller in 16-Pin Package with 180o out-of-phase operation Configured as 2-Independent PWM Controller Flexible, Same or Separate Supply Operation Operation from 4V to 25V Input Internal 200KHz Oscillator Soft-Start controls all outputs Fixed Frequency Voltage Mode The APU3048 IC combines a Dual synchronous Buck controller and a linear regulator controller, providing a costffective, high performance and flexible solution for multioutput applications. The Dual synchronous controller is configured as 2-independent PWM controller. APU3048 provides a separate adjustable output by driving a switch as a linear regulator. This device features an internal 200KHz oscillator, under-voltage lockout for all input supplies, an external programmable soft start function as well as output under-voltage detection that latches off the device when an output short is detected. 500mA Peak Output Drive Capability Programmable Outputs RoHS Compliant & Halogen Free Product APPLICATIONS DDR Memory Source Sink Vtt Application Graphic Card Hard Disk Drive Power supplies requiring multiple outputs TYPICAL APPLICATION Figure 1 - Typical application of APU3048 ORDERING INFORMATION APU3048X Package Type O : TSSOP-16 M : SOP-16 Data and specifications subject to change without notice 1 20130814V5.1 Advanced Power Electronics Corp. APU3048 ABSOLUTE MAXIMUM RATINGS Vcc Supply Voltage .................................................. 25V VcH1=VcH2 Supply Voltage ...................................... 30V (not rated for inductive load) Storage Temperature Range ...................................... -65C To 150C Operating Junction Temperature Range ..................... 0C To 125C CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. PACKAGE INFORMATION ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over V cc=5V, VcH1=VcH2=12V, TA=0 to 70C. Typical values refer TA=25C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient tempera Parameter SYM TEST CONDITION TYP MAX UNITS 1.225 1.250 1.275 V - % MIN Reference Voltage Fb Voltage Initial Accuracy VFB Fb Voltage Line Regulation LREG 5V<Vcc<12V - 0.2 Supply Ramping Up - 4.2 - V - 0.25 - V 3.5 - V UVLO UVLO Threshold - Vcc UVLO Hysteresis - Vcc UVLO VCC UVLO Threshold - Vc UVLO VC Supply Ramping Up - 0.2 - V UVLO Fb Fb Ramping Down - 0.6 - V - 0.1 - V UVLO Hysteresis - Vc UVLO Threshold - Fb UVLO Hysteresis - FB Supply Current Dyn ICC Freq=200KHz, CL=1500pF - 5.0 - mA VcH1 Dynamic Supply Current Dyn ICH1 Freq=200KHz, CL=1500pF - 7 - mA VcH2 Dynamic Supply Current Dyn ICH2 Vcc Dynamic Supply Current Freq=200KHz, CL=1500pF - 7 - mA ICCQ SS=0V - 3.5 - mA VcH1 Static Supply Current ICH1Q SS=0V - 2 - mA VcH2 Static Supply Current ICH2Q SS=0V - 2 - mA Vcc Static Supply Current 2 Advanced Power Electronics Corp. APU3048 ELECTRICAL SPECIFICATIONS(Cont.) Parameter SYM TEST CONDITION MIN TYP MAX UNITS - -0.1 -64 - uA uA Error Amp Fb Voltage Input Bias Current IFB1 Fb Voltage Input Bias Current IFB2 SS=3V SS=0V Transconductance 1 Transconductance 2 gm1 gm2 - 400 - umho Note 1 - 600 - umho SS IB SS=0V 15 25 30 uA 180 200 220 KHz Note 1 - 1.25 - Vpp Tr CL=1500pF - 35 100 ns Tf CL=1500pF Soft-Start Section Charge Current Oscillator Section Freq Frequency Ramp Amplitude VRAMP Output Drivers Rise Time Fall Time Dead Band Time TDB Max Duty Cycle TON Min Duty Cycle TOFF - 50 100 ns 50 150 250 ns Fb=1V, Freq=200KHz 85 90 - % Fb=1.5V 0 0 - % LDO Controller ILDO 30 45 - mA Fb Voltage VFBLDO 1.225 1.25 1.275 V Input Bias Current ILDO(BIAS) - 0.5 2 uA Drive Current PIN DESCRIPTIONS PIN DESCRIPITON PIN SYMBOL GND PIN# 1 FB2 2 Inverting inputs to the error amplifiers. These pins work as feedback FB1 16 inputs for each channel, and are connected directly to the output of Ground pin. the switching regulator via a resistor divider to set the output voltages. Comp1 3 Comp2 VcH2 4 5 VcH1 12 Compensation pins for the error amplifiers. Supply voltage for the high side output drivers. These are connected to voltages that must be at least 4V higher than their bus voltages (assuming 5V threshold MOSFET). A minimum of 1mF high frequency capacitor must be connected from these pins to PGnd pin to provide peak drive current capability. HDrv2 6 Output driver for the high side power MOSFET. Connect a diode, HDrv1 11 such as BAT54 or 1N4148, from these pins to ground for the application when the inductor current goes negative (Source/Sink), soft-start at no load and for the fast load transient from full load to no load. 3 Advanced Power Electronics Corp. APU3048 PIN DESCRIPTIONS PIN SYMBOL LDrv2 PIN# 7 LDrv1 10 PGnd 8 PIN DESCRIPITON Output driver for the synchronous power MOSFET. This pin serves as the separate ground for MOSFET's driver and Vcc 9 Supply voltage for the internal blocks of the IC. VOUT3 13 Driver signal for the LDO's external transistor. Fb3 14 LDO's feedback pin, connected to a resistor divider to set the output SS 15 Soft-Start pin. The converter can be shutdown by pulling this pin below 0.5V. voltage of LDO. BLOCK DIAGRAM Figure 2 - Simplified block diagram of the APU3048. 4 Advanced Power Electronics Corp. APU3048 THEORY OF OPERATION Introduction Shutdown The APU3048 is designed for multi-outputs applications. It includes two synchronous buck controllers and a linear regulator controller. The two synchronous controller operates with fixed frequency voltage mode and is configured as two independent controllers. The timing of the IC is provided through an internal oscillator circuit. These are two out of phase oscillators. Soft-Start The APU3048 has a programmable soft start to control the output voltage rise and limit the current surge at the start-up. To ensure correct start-up, the soft-start sequence initiates when the Vcc, VcH1 and VcH2 rise above their threshold and generates the Power On Reset (POR) signal. Soft-start function operates by sourcing an internal current to charge an external capacitor to about 3V. Initially, the soft-start function clamps the E/A's output of the PWM onverter. As the charging voltage of the external capacitor ramps up, the PWM signals increase from zero to the point the feedback loop takes control. The converter can be shutdown by pulling the softstart pin below 0.5V. This can be easily done by using an external small signal transistor. During shutdown the MOSFET drivers and the LDO controller turn off. Short-Circuit Protection The outputs are protected against the short circuit. The APU3048 protects the circuit for shorted output by sensing the output voltages. The APU3048 shuts down the PWM signals and LDO controller, when the output voltages drops below the set values. Under-Voltage Lockout The under-voltage lockout circuit assures that the MOSFET driver outputs and LDO controller remain in the off state whenever the supply voltages drop below set parameters. Normal operation resumes once the supply voltages rise above the set values. Out of Phase Operation The APU3048 drives its two output stages 180 o out of phase. In application with single input voltage, the out of phase peration reduces the input ripple current. This results in much smaller RMS current in the input capacitor and reduction of input capacitors. APPLICATION INFORMATION Design Example: The following example is a typical application for APU3048in current sharing mode. The schematic is Figure 9 on page 12. For Switcher VIN1 = 12V VOUT1 = 3.3V IOUT1 = 4A VIN2 = 5V VOUT2 = 1.8V IOUT2 = 4A VOUT = 75mV fS = 200KHz When an external resistor divider is connected to the output as shown in Figure 3. For Linear Regulator VIN3 = 3.3V VOUT3 = 2.5V IOUT3 = 2A PWM Section Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb1 pin is the inverting input of the error amplifier, which is internally referenced to 1.25V. The divider is ratioed to provide 1.25V at the Fb1 pin when the output is at its desired value. The output voltage is defined by using the following equation: Figure 3 - Typical application of the APU3048 for programming the output voltage. Equation (1) can be rewritten as: Will result to: VOUT1=3.3V VREF=1.25V R8=1K, R6=1.64K VOUT2=1.8V VREF=1.25V R15=1K, R14=442 5 Advanced Power Electronics Corp. APU3048 Output Capacitor Selection If the high value feedback resistors are used, the input bias current of the Fb pin could cause a slight increase in output voltage. The output voltage set point can be more accurate by using precision resistor. Soft-Start Programming The soft-start timing can be programmed by selecting the soft start capacitance value. The start up time of the converter can be calculated by using: tSTART = 75 x Css (ms) ---(2) Where: CSS is the soft-start capacitor (mF) For a start-up time of 7.5ms, the soft-start capacitor will be 0.1uF. Choose a ceramic capacitor at 0.1uF. Boost Supply Vc To drive the high-side switch it is necessary to supply a gate voltage at least 4V greater than the bus voltage. This is achieved by using a charge pump configuration as shown in Figure 9. The capacitor is charged up to approximately twice the bus voltage. A capacitor in the range of 0.1mF to 1mF is generally adequate for most applications. Input Capacitor selection The input filter capacitor should be based on how much ripple the supply can tolerate on the DC input line. The ripple current generated during the on time of control MOSFET should be provided by input capacitor. The RMS value of this ripple is expressed by: Where: D is the Duty Cycle, simply D=VOUT/VIN IRMS is the RMS value of the input capacitor current. IOUT is the output current for each channel. For VIN1=12V, IOUT1=4A and D1=0.275 Results to: IRMS1=1.78A The criteria to select the output capacitor is normally based on the value of the Effective Series Resistance (ESR). In general, the output capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy stability requirements. The ESR of the output capacitor is calculated by the following relationship: Where: VO = Output Voltage Ripple IO = Output Current VO=75mV and IO=3A, results to: ESR=25m The Sanyo TPC series, PosCap capacitor is a good choice. The 6TPC150M 150uF, 6.3V has an ESR 40m. Selecting two of these capacitors in parallel for each output, results to an ESR of around 20m which achieves our low ESR goal. The capacitor value must be high enough to absorb the inductor's ripple current. The larger the value of capacitor, the lower will be the output ripple voltage. The resulting output ripple current is smaller then each channel ripple current due to the 180o phase shift. These currents cancel each other. The cancellation is not the maximum because of the different duty cycle for each channel. Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. Low inductor value causes large ripple current, resulting in the smaller size, but poor efficiency and high output noise. Generally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor (i); the optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for desired operating ripple current can be determined using the following relation: And for VIN2=5V, IOUT2=4A and D2=0.36 Results to: IRMS2 =1.92A For higher efficiency, a low ESR capacitor is recommended. For VIN1=12V, choose one Poscap from Sanyo 16TPB47M (16V, 47uF, 70m, 1.4A) For VIN2=5V, choose one 6TPC150M (6.3V, 150uF, 40m, 1.9A). Where: VIN = Max Input Voltage VOUT = Output Voltage i = Inductor Ripple Current fS = Switching Frequency t = Turn On Time D = Duty Cycle 6 Advanced Power Electronics Corp. For i1=25% of I1, we get L1=9.9uH For i2=25% of I2, we get: L2=5.7uH Panasonic provides a range of inductors in different values and low profile for large currents. For L1 choose ETQP6F102HFA (10.2uH, 4A) For L2 choose ELLATV6R8M (6.8uH, 4A) Power MOSFET Selection The selections criteria to meet power transfer requirements is based on maximum drain-source voltage (VDSS), gate-source drive voltage (VGS), maximum output current, On-resistance RDS(ON) and thermal management. The MOSFET must have a maximum operating voltage (VDSS) exceeding the maximum input voltage (VIN). The gate drive requirement is almost the same for both MOSFETs. Caution should be taken with devices at very low VGS to prevent undesired turn-on of the complementary MOSFET, which results a shootthrough current. APU3048 The total conduction losses for channel 1 is: PCON1 = 0.24W The total conduction losses for channel 2 is: PCON2 = 0.24W The control MOSFET contributes to the majority of the switching losses in synchronous Buck converter. The synchronous MOSFET turns on under zero-voltage condition, therefore the turn on losses for synchronous MOSFET can be neglected. With a linear approximation, the total switching loss can be expressed as: Where: VDS(OFF) = Drain to Source Voltage at off time tr = Rise Time tf = Fall Time T = Switching Period ILOAD = Load Current The total power dissipation for MOSFETs includes onduction and switching losses. For the Buck converter the average inductor current is equal to the DC load current. The conduction loss is defined as: Figure 4 - Switching time waveforms. The total conduction loss is defined as: The RDS(ON) temperature dependency should be considered for the worst case operation. This is typically given in the MOSFET data sheet. Ensure that the conduction losses and switching losses do not exceed the packageratings or violate the overall thermal budget. For this design, AP9408AGH is a good choice. These devices provide low on-resistance in a compact TO-252 3Pin package. From AP9408AGH data sheet we obtain: AP9408AGH tr = 5ns tf = 6ns These values are taken under a certain condition test. For more detail please refer to the AP9408AGH data sheet. By using equation (6), we can calculate the switching losses. PSW1 = 52.8mW PSW2 = 22mW The MOSFETs have the following data: AP9408AGH VDSS = 30V ID = 33A @ 100oC RDS(ON) = 10m @ VGS=10V = 1.5 for 150 oC (Junction Temperature) 7 Advanced Power Electronics Corp. APU3048 Feedback Compensation The APU3048 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency and adequate phase margin (greater than 45o). The output LC filter introduces a double pole, -40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180 o (see Figure 5). The Resonant frequency of the LC filter is expressed as follows: Figure 6 - Compensation network without local feedback and its asymptotic gain plot. Figure 5 shows gain and phase of the LC filter. Since we already have 180o phase shift just from the output filter, the system risks being unstable. The transfer function (Ve / VOUT) is given by: The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: Figure 5 - Gain and phase of LC filter. The APU3048's error amplifier is a differentialinput transconductance amplifier. The output is available for DC gain control or AC phase compensation. The E/A can be compensated with or without the use of local feedback. When operated without local feedback the transconductance properties of the E/A become evident and can be used to cancel one of the output filter poles. This will be accomplished with a series RC circuit from Comp1 pin to ground as shown in Figure 6. The ESR zero of the LC filter expressed as follows: The gain is determined by the voltage divider and E/A's transconductance gain. First select the desired zero-crossover frequency (Fo): Use the following equation to calculate R4: Where: VIN1 = Maximum Input Voltage VOSC = Oscillator Ramp Voltage FO1 = Crossover Frequency for the master E/A FESR1 = Zero Frequency of the Output Capacitor FLC1 = Resonant Frequency of Output Filter gm = Error Amplifier Transconductance R8 and R6 = Resistor Dividers for Output Voltage Programming 8 Advanced Power Electronics Corp. For: VIN1 = 12V VOSC = 1.25V FO1 = 30KHz FESR1 = 26.5KHz APU3048 FLC1 = 2.8KHz R8 = 1K R6 = 1.64K gm = 600umho This results to R9=46.4K; Choose R9=46.4K To cancel one of the LC filter poles, place the zero be-fore the LC filter resonant frequency pole: For: L3 = 10.2uH Co = 300uF Fz = 2.1KHz R9 = 46.4K Using equations (11) and (13) to calculate C9, we get: C9 = 1630pF; Choose C9 = 1800pF We get: R11 = 38.9K; Choose R11 = 39.2K C19 = 1554pF; Choose C19 = 1800pF One more capacitor is sometimes added in parallel with C9 and R4. This introduces one more pole which is mainly used to supress the switching noise. The additional pole is given by: The pole sets to one half of switching frequency which results in the capacitor CPOLE: Figure 7 - Compensation network with local feedback and its asymptotic gain plot. In such configuration, the transfer function is given by: The error amplifier gain is independent of the transconductance under the following condition: By replacing ZIN and Zf according to figure 7, the transformer function can be expressed as: As known, transconductance amplifier has high impedance (current source) output, therefore, consider should be taken when loading the E/A output. It may exceed its source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two zeros and they are expressed as follows: For a general solution for unconditionally stability for any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensation network. The typically used compensation network for voltage-mode controller is shown in Figure 7. 9 Advanced Power Electronics Corp. APU3048 8) Use equation (1) to calculate R5: Cross Over Frequency: Where: VIN = Maximum Input Voltage VOSC = Oscillator Ramp Voltage Lo = Output Inductor Co = Total Output Capacitors The stability requirement will be satisfied by placing the poles and zeros of the compensation network according to following design rules. The consideration has been taken to satisfy condition 14 regarding transconductance error amplifier. 1) Select the crossover frequency: Fo < FESR and Fo < (1/10 ~ 1/6) x fS 2) Select R7, so that R7 >> These design rules will give a crossover frequency approximately one-tenth of the switching frequency. The higher the band width, the potentially faster the load transient speed. The gain margin will be large enough to provide high DC-regulation accuracy (typically -5dB to 12dB). The phase margin should be greater than 458 for overall stability. LDO Section Output Voltage Programming Output voltage for LDO is programmed by reference voltage and external voltage divider. The Fb3 pin is the inverting input of the error amplifier, which is internally referenced to 1.25V. The divider is ratioed to provide 1.25V at the Fb3 pin when the output is at its desired value. The output voltage is defined by using the following equation: 3) Place first zero before LC's resonant frequency pole. 4) Place third pole at the half of the switching For: VOUT2 = 2.5V VREF = 1.25V RLOW = 1K Results to: RHIGH=1K LDO Power MOSFET Selection If not, change R7 selection. The first step in selecting the power MOSFET for the linear regulator is to select the maximum R DS(ON) based on the input to the dropout voltage and the maximum load current. 5) Place R7 in (15) and calculate C10: 6) Place second pole at ESR zero. For: VIN3 = 3.3V VOUT2 = 2.5V IOUT2 = 2A Results to: RDS(ON)(MAX) = 0.4 Note that since the MOSFET RDS(ON) increases with temperature, this number must be divided by ~1.5 in order to find the RDS(ON)(MAX) at room temperature. The AP20T03GH has a maximum of 0.05 RDS(ON) at room temperature, which meets our requirements. If R8 is too small, increase R7 and start from step2. 7) Place second zero around the resonant frequency. FZ2 = FLC 10 Advanced Power Electronics Corp. APU3048 Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the connection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to reduce the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. In multilayer PCB use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. TYPICAL APPLICATION 12V to 3.3V @ 4A 12V to 1.8V @ 4A 3.3V to 2.5V @ 2A Figure 8 - Typical application of APU3048 in an on-board DC - DC converter using a single 12V supply for switcher. 11 Advanced Power Electronics Corp. APU3048 TYPICAL APPLICATION 12V to 3.3V @ 4A 5V to 1.8V @ 4A 3.3V to 2.5V @ 2A Figure 9 - Demo-board application of APU3048. 12 Advanced Power Electronics Corp. APU3048 DEMO-BOARD APPLICATION 12V to 3.3V @ 4A 5V to 1.8V @ 4A 3.3V to 2.5V @ 2A Ref Desig Description Value Qty Part# Manuf Web site (www.) a-power.com.tw Q1 MOSFET 30V, 50mohm, 1.5A 1 AP20T03GH APEC Q2 MOSFET 30V, 10mo hm, 53A 2 AP9408AGH APEC Q3 MOSFET 30V, 6mohm, 68A 2 AP9412AGH APEC U1 Controller Synchronous PWM 1 APU3048 APEC D1 Diode Fast Switching 1 BAT54S L1, L2 Inductor 1uH, 2.9A 2 ELL6SH1R0M Panasonic maco.panasonic.co.jp L3 Inductor 6.8uH, 4A 1 ELLATV6R8M Panasonic L4 Inductor 10.2uH, 4A 1 ETQP6F102HFA Panasonic 7 ECJ-2VF1C105Z Panasonic C1,7,8,13, 14,17,23 Cap, Ceramic 1uF, Y5V, 16V IR C2, C4 Cap, Tantalum 33uF, 16V 2 ECS-T1CD336R C3, C24 Cap, Ceramic 0.1uF, Y5V, 25V 2 ECJ-2VF1E104Z Panasonic C5 Cap, Ceramic 1uF, X7R, 25V 1 ECJ-3YB1E105K Panasonic C9, C15 Cap, Tantalum 47uF, 10V 2 ECS-T1AD476R C10, C20 Cap, Ceramic 470pF, X7R, 50V 2 ECJ-2VC1H471J Panasonic C18, C19 Cap, Ceramic 1800pF, X7R, 50V 2 ECJ-2VB1H182K Panasonic C6 Cap, Poscap 47uF, 16V, 70m 1 16TPB47M Sanyo Cap, Poscap 150uF, 6.3V, 40m 5 6TPC150M Sanyo R1,3,10,12 Resistor 2.15 4 R2 Resistor 10 1 R4, R13 Resistor 4.7 2 R5,7,8,15 Resistor 1K, 1% 4 R6 Resistor 1.65K, 1% 1 R9 Resistor 46.4K 1 R11 Resistor 39.2K 1 R14 Resistor 442, 1% 1 C11,12,16 21,22 irf.com Panasonic Panasonic sanyo.com/industrial 13 Advanced Power Electronics Corp. APU3048 WAVEFORMS Figure 10 - Transient response @ I OUT = 0 to 2A for 3.3V Figure 11 - Transient response @ I OUT = 0 to 2A for 1.8V Figure 12 - Transient response @ I OUT = 0 to 2A for 2.5V Figure 13 - Output voltage ripple for 3.3V @ 4A. Figure 14 - Output voltage ripple for 1.8V @ 4A. Figure 15 - Soft-start voltage Vs. output voltages. 14 Advanced Power Electronics Corp. APU3048 WAVEFORMS Figure 16 - Gate signals for 3.3V output. Ch1: Output current 2A/div. Ch2: Gate signal for control FET 20V/div. Ch3: Gate signal for sync FET 10V/div. Figure 17 - Gate signals for 1.8V output. Ch1: Output current 2A/div. Ch2: Gate signal for control FET 10V/div. Ch3: Gate signal for sync FET 10V/div. 15 Advanced Power Electronics Corp. APU3048 MARKING INFORMATION SOP-16 / TSSOP-16 U3048X Part Number Package Code : M : SOP-16 O : TSSOP-16 YWWSSS Date Code (YWWSSS) YLast Digit Of The Year WWWeek SSSSequence 16