DS2165 - Dallas Semiconductor

1 of 18 092299

FEATURES

§ Compresses/expands 64 kbps PCM voice

to/from either 32 kbps, 24 kbps, or 16 kbps

§ Dual, fully independent channel architecture;

device can be programmed to perform either:

- two expansions

- two compressions

- one expansion and one compression

§ Interconnects directly to combo-codec

devices

§ Input to output delay is less than 375 µs

§ Simple serial port used to configure the

device

§ Onboard Time Slot Assigner Circuit (TSAC)

function allows data to be input/output at

various time slots

§ Supports Channel Associated Signaling

§ Each channel can be independently idled or

placed into bypass

§ Available hardware mode requires no host

processor; ideal for voice storage

applications

§ Backward-compatible with the DS2167

ADPCM Processor Chip

§ Single +5V supply; low-power CMOS

technology

§ Available in 24-pin DIP and 28-pin PLCC

PIN ASSIGNMENT

DESCRIPTION

The DS2165 ADPCM Processor Chip is a dedicated Digital Signal Processing (DSP) chip that has been

optimized to perform Adaptive Differential Pulse Code Modulation (ADPCM) speech compression at

three different rates. The chip can be programmed to compress (expand) 64 kbps voice data down to (up

from) either 32 kbps, 24 kbps, or 16 kbps. The compression to 32 kbps follows the algorithm specified by

CCITT Recommendation G.721 (July 1986) and ANSI document T1.301 (April 1987). The compression

to 24 kbps follows ANSI document T1.303. The compression to 16 kbps follows a proprietary algorithm

developed by Dallas Semiconductor. The DS2165 can switch compression algorithms on-the-fly. This

allows the user to make maximum use of the available bandwidth on a dynamic basis.

DS2165/DS2165Q

16/24/32kpbs ADPCM Processor

www.dalsemi.com

28-PIN PLCC

FSY

YOUT

SDI

SCLK

XOUT

TM1

TM0

RST

VDD

YIN

CLKY

SPS

MCLK

VSS

XIN

CLKX

FSX

4 3 2 1 28 27 26

12 13 14 15 16 17 18

TM1

SPS

MCLK

VSS

VDD

YIN

CLKY

FSY

YOUT

SDI

SCLK

XOUT

FSX

CLKX

XIN

TM0

RST

24-PIN DIP (600-mil)

A 3-volt Operation Version

is Available (DS2165QL)

DS2165/DS2165Q

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OVERVIEW

The DS2165 contains three major functional blocks: a high performance (10 MIPS) DSP engine, two

independent PCM interfaces (X and Y) which connect directly to serial Time Division Multiplexed

(TDM) backplanes, and a serial port that can configure the device on-the-fly via an external controller. A

10 MHz master clock is required by the DSP engine. The DS2165 can be configured to perform either

two expansions, two compressions, or one expansion and one compression. The PCM/ADPCM data

interfaces support data rates from 256 kHz to 4.096 MHz. Typically, the PCM data rates will be 1.544

MHz for µ-law and 2.048 MHz for A-law. Each channel on the device samples the serial input PCM or

ADPCM bit stream during a user-programmed input time slot, processes the data and outputs the result

during a user-programmed output time slot.

Each PCM interface has a control register which specifies functional characteristics (compress, expand,

bypass, and idle), data format (µ-law or A-law), and algorithm reset control. With the SPS pin strapped

high, the software mode is enabled and the serial port can be used to configure the device. In this mode, a

novel addressing scheme allows multiple devices to share a common 3-wire control bus, simplifying

system-level interconnect.

With SPS low, the hardware mode is enabled. This mode disables the serial port and maps certain control

controller is required and all PCM/ADPCM input and output time slots default to time slot 0.

HARDWARE RESET

RST allows the user to reset both channel algorithms and the contents of the internal registers. This pin

must be held low for at least 1 ms on system power-up after the master clock is stable to ensure that that

the device has initialized properly. RST should also be asserted when changing to or from the hardware

mode. RST clears all bits of the Control Register for both channels except the IPD bits; the IPD bits for

both channels are set to 1.

SOFTWARE MODE

Tying SPS high enables the software mode. In this mode, an external host controller writes configuration

data to the DS2165 via the serial port through inputs SCLK, SDI, and CS . (See Figure 2.) Each write to

the DS2165 is either a 2-byte write or a 4-byte write. A 2-byte write consists of the Address/Command

Byte (ACB), followed by a byte to configure the Control Register (CR) for either the X or Y channel. The

4-byte write consists of the ACB, followed by a byte to configure the CR, and then 1 byte to set the input

time slot and another byte to set the output time slot.

ADDRESS/COMMAND BYTE

In the software mode, the address/command byte is the first byte written to the serial port; it identifies

which of the 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must

match that at inputs A0 to A5. If no match occurs, the device ignores the following configuration data. If

an address match occurs, the next 3 bytes written are accepted as control, input and output time slot data.

Bit ACB.6 determines which side (X or Y) of the device is to be updated. The PCM and ADPCM

outputs are tristated during register updates.

CONTROL REGISTER

The control register establishes idle, algorithm reset, bypass, data format and channel coding for the

selected channel.

The X and Y side PCM interfaces can be independently disabled (output 3-stated) via IPD. When IPD is

set for both channels, the device enters a low-power standby mode. In this mode, the serial port must not

be operated faster than 39 kHz.

DS2165/DS2165Q

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ALRST resets the algorithm coefficients for the selected channel to their initial values. ALRST will be

cleared by the device when the algorithm reset is complete.

PIN DESCRIPTION Table 1

PIN SYMBOL TYPE DESCRIPTION

1RST IReset. A high-low-high transition resets the algorithm. The device

should be reset on power-up and when changing to or from the

hardware mode.

TM0

TM1

ITest Modes 0 and 1. Tie to VSS for normal operation.

IAddress Select. A0 = LSB; A5 = MSB; must match

address/command word to enable the serial port.

10 SPS ISerial Port Select. Tie to V

to select the serial port; tie to V

select the hardware mode.

11 MCLK IMaster Clock. 10 MHz clock for the ADPCM processing engine;

may be asynchronous to SCLK, CLKX, and CLKY.

12 VSS -Signal Ground. 0.0 volts.

13 XIN IX Data In. Sampled on falling edge of CLKX during selected time

slots.

14 CLKX I X Data Clock. Data clock for the X side PCM interface; must be

synchronous with FSX.

15 FSX IX Frame Sync. 8 kHz frame sync for the X side PCM interface.

16 XOUT OX Data Output. Updated on rising edge of CLKX during selected

time slots.

17 SCLK ISerial Data Clock. Used to write to the serial port registers.

18 SDI ISerial Data In. Data for onboard control registers; sampled on the

rising edge of SCLK. LSB sent first.

19 CS IChip Select. Must be low to write to the serial port.

20 YOUT OY Data Output. Updated on rising edge of CLKY during selected

time slots.

21 FSY IY Frame Sync. 8 kHz frame sync for the Y side PCM interface.

22 CLKY I Y Data Clock. Data clock for the Y side PCM interface; must be

synchronous with FSY.

23 YIN IY Data In. Sampled on falling edge of CLKY during selected time

slots.

24 VDD -Positive Supply. 5.0 volts (or 3.0 volts for DS2165QL).

DS2165/DS2165Q

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DS2165 BLOCK DIAGRAM Figure 1

SERIAL PORT WRITE Figure 2

NOTE:

1. A 2-byte write is shown.

The bypass feature is enabled when BYP is set and IPD is cleared. During bypass, no expansion or

compression occurs. Bypass operates on bytewide (8 bits) slots when CP/

is set and on nibble-wide (4

bits) slots when CP/

is cleared.

A-law (U/

= 0) and µ-law (U/

= 1) PCM coding is independently selected for the X and Y channels

via CR.2. If BYP and IPD are cleared, then CP/

determines if the input data is to be compressed or

expanded.

DS2165/DS2165Q

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ADDRESS/COMMAND BYTE Figure 3

(MSB) (LSB)

-X/

A5 A4 A3 A2 A1 A0

SYMBOL POSITION NAME AND DESCRIPTION

-ACB.7 Reserved; must be 0 for proper operation

ACB.6X/Y Channel Select

0 = update channel Y characteristics

1 = update channel X characteristics

A5 ACB.5 MSB of Device Address

A4 ACB.4

A3 ACB.3

A2 ACB.2

A1 ACB.1

A0 ACB.0 LSB of Device Address

CONTROL REGISTER Figure 4

(MSB) (LSB)

AS0 AS1 IPD ALRST BYP U/

AS2 CP/

SYMBOL POSITION NAME AND DESCRIPTION

AS0 CR.7 Algorithm Select 0. See Table 2.

AS1 CR.6 Algorithm Select 1. See Table 2.

IPD CR.5 Idle and Power-Down.

0 = channel enabled

1 = channel disabled (output 3-stated)

ALRST CR.4 Algorithm Reset.

0 = normal operation

1 = reset algorithm for selected channel

BYP CR.3 Bypass.

0 = normal operation

1 = bypass selected channel

CR.2 Data Format.

0 = A-law

1 = m-law

AS2 CR.1 Algorithm Select 2. See Table 2.

CP/

CR.0 Channel Coding.

0 = expand (decode) selected channel

1 = compress (encode) selected channel

DS2165/DS2165Q

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ALGORITHM SELECT BITS Table 2

ALGORITHM SELECTED AS2 AS1 AS0

64 kbps to/from 32 kbps 0 0 0

64kbps to/from 24 kbps 1 1 1

64 kbps to/from 16 kbps 1 0 1

INPUT TIME SLOT REGISTER Figure 5

(MSB) (LSB)

- - D5 D4 D3 D2 D1 D0

SYMBOL POSITION NAME AND DESCRIPTION

-ITR.7 Reserved; must be 0 for proper operation.

-ITR.6 Reserved; must be 0 for proper operation.

D5 ITR.5 MSB of input time slot register.

D4 ITR.4

D3 ITR.3

D2 ITR.2

D1 ITR.1

D0 ITR.0 LSB of input time slot register.

OUTPUT TIME SLOT REGISTER Figure 6

(MSB) (LSB)

- - D5 D4 D3 D2 D1 D0

SYMBOL POSITION NAME AND DESCRIPTION

-OTR.7 Reserved; must be 0 for proper operation.

-OTR.6 Reserved; must be 0 for proper operation.

D5 OTR.5 MSB of output time slot register.

D4 OTR.4

D3 OTR.3

D2 OTR.2

D1 OTR.1

D0 OTR.0 LSB of output time slot register.

DS2165/DS2165Q

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TIME SLOT ASSIGNMENT/ORGANIZATION

Onboard counters establish when PCM and ADPCM I/O occur. The counters are programmed via the

time slot registers. Time slot size (number of bits wide) is determined by the state of CP/

. The number

of time slots available is determined by the state of both CP/

and U/

. (See Figures 7 through 10.)

For example, if the X channel is set to compress (CP/

= 1) and it is set to expect µ-law data

(U/

= 1), then the input port (XIN) is set up for 32 8-bit time slots and the output port (XOUT) is set up

for 64 4-bit time slots. The time slot organization is not dependent on which algorithm has been selected.

NOTE: Time slots are counted from the frame sync signal starting at the first rising edge of either CLKX

or CLKY after the frame sync.

DS2165 m-LAW PCM INTERFACE Figure 7

DS2165 m-LAW ADPCM INTERFACE Figure 8

DS2165/DS2165Q

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DS2165 A-LAW PCM INTERFACE Figure 9

DS2165 A-LAW ADPCM INTERFACE Figure 10

DS2165/DS2165Q

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HARDWARE MODE

The hardware mode is intended for applications that do not have an external controller available or do not

require the extended features offered by the serial port. Tying the SPS pin to VSS disables the serial port,

clears all internal register bits and maps the IPD, U/

, and CP/

bits for both channels to external bits.

(See Table 3.) In the hardware mode, both the input and output time slots default to time slot 0.

HARDWARE MODE Table 3

PIN # / NAME REG. LOCATION NAME AND DESCRIPTION

4 / A0 CP/

(Channel X)

Channel X Coding Configuration

0 = Expand

1 = Compress

5 / A1 AS0/AS1/AS2

(Channel X & Y) Algorithm Select (see Table 5)

6 / A2 U/

(Channel X) Channel X Data Format

0 = A-law

1 = µ-law

7 / A3 CP/

(Channel Y) Channel Y Coding Configuration

0 = Expand

1 = Compress

8 / A4 AS0/AS1/AS2

(Channel X & Y) Algorithm Select (see Table 5)

9 / A5 U/

(Channel Y) Channel Y Data Format

0 = A-law

1 = µ-law

18 / SDI IPD

(Channel Y) Channel Y Idle Select

0 = Channel active

1 = Channel idle

19 / CS IPD

(Channel X) Channel X Idle Select

0 = Channel active

1 = Channel idle

NOTES:

1. SCLK must be tied to VSS when the hardware mode is selected.

2. When both channels are idled, power consumption is significantly reduced.

3. The NIL will power-up within 800 ms after either channel is returned to active from an idle state.

DS2165/DS2165Q

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ALGORITHM SELECT FOR HARDWARE MODE Table 4

ALGORITHM CONFIGURATION OF A1 AND A4

64kbps to/from 32kbps Tie both A1 and A4 to VSS.

64kpbs to/from 24kbps Hold A1 and A4 low during a hardware reset; take both A1 and A4 high

after the RST pin has returned high (allow 3 µs after RST returns high

before taking A1 and A4 high).

64kbps to/from 16kbps Tie both A1 and A4 to VDD.

DS2165 CONNECTION TO CODEC/FILTER Figure 11

NOTE:

Suggested Codec/Filters

TP305X National Semiconductor

ETC505X SGS-Thomson Microelectronics

MC1455XX Motorola

TCM29CXX Texas Instruments

HD44238C Hitachi

*other generic Codec/Filter devices can be substituted.

DS2165/DS2165Q

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PCM AND ADPCM INPUT/OUTPUT

Since the organization of the input and output time slots on the DS2165 does not depend on the algorithm

selected, it always assumes that PCM input and output will be in 8-bit bytes and that ADPCM input and

output will be in 4-bit bytes. Figure 12 demonstrates how the DS2165 handles the I/O for the three

different algorithms. In the figure, it is assumed that channel X is in the compression mode (CP/

= 1)

and channel Y is in the expansion mode (CP/

= 0). Also, it is assumed that both the input and output

time slots for both channels are set to 0.

PCM AND ADPCM I/O EXAMPLE Figure 12

NOTE:

1. The bit after the LSB in the 24kbps ADPCM output will only be a 1 when the DS2165 is operated in

the software mode and is programmed to perform 24kbps compression; in all other configurations, it

will be a 0.

DS2165/DS2165Q

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TIME SLOT RESTRICTIONS

Under certain conditions, the DS2165 does contain some restrictions on the output time slots that are

available. These restrictions are covered in detail in a separate application note. No restrictions occur if

the DS2165 is operated in the hardware mode.

INPUT TO OUTPUT DELAY

With all three compressions algorithms, the total delay, from the time the PCM data sample is captured

by the DS2165 to the time it is output, is always less than 375 µs. The exact delay is determined by the

input and output time slots selected for each channel.

CHANNEL ASSOCIATED SIGNALING

The DS2165 supports Channel Associated Signaling (CAS) via its ability to automatically change from

the 32 kbps compression algorithm to the 24 kbps algorithm. If the DS2165 is configured to perform the

32 kbps algorithm, then in both the hardware and software mode it will sense the frame sync inputs (FSX

and FSY) for a double-wide frame sync pulse. Whenever the DS2165 receives a double-wide pulse, it

will automatically switch from the 32kbps algorithm to the 24kbps algorithm. Switching to the 24kbps

algorithm allows the user to insert signaling data into the LSB bit position of the ADPCM output because

this bit does not contain any useful speech information.

ON-THE-FLY ALGORITHM SELECTION

In the software mode, the user can switch between the three available algorithms on-the-fly. That is, the

DS2165 does not need to be reset or stopped to make the change from one algorithm to another. The

DS2165 reads the Control Register before it starts to process each PCM or ADPCM sample. If the user

wishes to switch algorithms, then the Control Register must be updated via the serial port before the first

input sample to be processed with the new algorithm arrives at either XIN or YIN. The PCM and

ACPCM outputs will tristate during register updates.

DS2165/DS2165Q

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ABSOLUTE MAXIMUM RATINGS*

Voltage on any Pin Relative to Ground -1.0V to +7.0V

Operating Temperature 0°C to 70°C

Storage Temperature -55°C to +125°C

Soldering Temperature 260°C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operation sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Logic 1 VIH 2.0 VCC+0.3 V5

Logic 0 VIL -0.3 +0.8 V5

Supply VDD 4.5 5.5 V5

Logic 1 VIH 2.2 VCC+0.3 V6

Logic 0 VIL -0.3 +0.4 V6

Supply VDD 2.7 3.6 V6

CAPACITANCE (tA =25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance CIN 5pF

Output Capacitance COUT 10 pF

(0°C to 70°C; VDD=5V 6 10%)

DC ELECTRICAL CHARACTERISTICS (VDD=3.0V + 20% - 10% for DS2165QL)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Active Supply Current IDDA 20 mA 1, 2, 5

Active Supply Current IDDA 12 mA 1, 2, 6

Idle Supply Current IDDPD 1 mA 1, 2, 3

Input Leakage II-1.0 +1.0 mA

Output Leakage IO-1.0 +1.0 mA4

Output Current (2.4V) IOH -1.0 mA 5

Output Current (0.4V) IOL +4.0 mA 5

Output Current (2.2V) IOH -0.5 mA 6

Output Current (0.4V) IOL +2.0 mA 6

NOTES:

1. CLKX = CLKY = 1.544 MHz; MCLK = 10

MHz.

2. Outputs open; inputs swinging full supply

levels.

3. Both channels in idle mode.

4. XOUT and YOUT are 3-stated.

5. Applies only to 5V device.

6. Applies only to 3V device (DS2165QL).

DS2165/DS2165Q

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PCM INTERFACE (0°C to 70°C; VDD=5V 6 10%)

AC ELECTRICAL CHARACTERISTICS (VDD=3.0V + 20% - 10% for DS2165QL)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

CLKX, CLKY Period tPXY 244 3906 ns 1

CLKX, CLKY Pulse Width tWXYL

tWXYH

100 ns

CLKX, CLKY Rise Fall Times tRXY

tFXY

10 20 ns

Hold Time from CLKX, CLKY to FSX,

FSY tHOLD 0ns 2

Setup Time from FSX, FSY high to

CLKX, CLKY low tSF 50 ns 2

Hold Time from CLKX, CLKY low to

FSX, FSY low tHF 100 ns 2

Setup Time for XIN, YIN to CLKX,

CLKY low tSD 50 ns 2

Hold Time for XIN, YIN to CLKX,

CLKY low tHD 50 ns 2

Delay Time from CLKX, CLKY to

Valid XOUT, YOUT tDXYO 10 150 ns 3

Delay Time from CLKX, CLKY to

XOUT, YOUT 3-stated tDXYZ 20 150 ns 2, 3, 4

NOTES:

1. Maximum width of FSX and FSY is one CLKX or CLKY period (except for signaling frames).

2. Measured at VIH = 2.0V, VIL = 0.8V, and 10 ns maximum rise and fall times.

3. Load = 150 pF + 2 LSTTL loads.

4. For LSB of PCM or ADPCM byte.

MASTER CLOCK / RESET (0°C to 70°C; VDD=5V 6 10%)

AC ELECTRICAL CHARACTERISTICS (VDD=3.0V + 20% - 10% for DS2165QL)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

MCLK Period tPM 100 ns 1

MCLK Pulse Width tWMH,

tWML

45 50 55 ns

MCLK Rise/Fall Times tRM, tFM 10 ns

RST Pulse Width tRST 1ms

NOTE:

1. MCLK = 10 MHz 6 500 ppm

DS2165/DS2165Q

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SERIAL PORT (0°C to 70°C; VDD=5V 6 10%)

AC ELECTRICAL CHARACTERISTICS (VDD=3.0V + 20% - 10% for DS2165QL)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

SDI to SCLK Set Up tDC 55 ns 1

SCLK to SDI Hold tCDH 55 ns 1

SCLK Low Time tCL 250 ns 1

SCLK High Time tCH 250 ns 1

SCLK Rise and Fall Time tR, tF100 ns 1

CS to SCLK Setup tCC 50 ns 1

SCLK to CS Hold tCCH 250 ns 1

CS Inactive Time tCWH 250 ns 1

SCLK Setup to CS Falling tSCC 50 ns 1

NOTE:

1. Measured at VIH = 2.0V, VIL = 0.8V, and 10ns maximum rise and fall times.

PCM INTERFACE AC TIMING DIAGRAM Figure 13

DS2165/DS2165Q

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MASTER CLOCK/RESET AC TIMING DIAGRAM Figure 14

SERIAL PORT AC TIMING DIAGRAM Figure 15

NOTE:

1. SCLK may be either high or low when CS is taken low.

DS2165/DS2165Q

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DS2165 16/24/32KBPS ADPCM PROCESSOR 24-PIN DIP

PKG 24-PIN

DIM MIN MAX

A IN.

MM 1.150

29.21 1.260

32.00

B IN.

MM 0.250

6.35 0.270

6.86

C IN.

MM 0.120

3.05 0.140

3.56

D IN.

MM 0.300

7.62 0.325

8.26

E IN.

MM 0.015

0.38 0.040

1.02

F IN.

MM 0.125

3.18 0.135

3.48

G IN.

MM 0.090

2.23 0.110

2.79

H IN.

MM 0.320

8.13 0.370

9.40

J IN.

MM 0.008

0.20 0.012

0.30

K IN.

MM 0.015

0.38 0.022

0.56

DS2165/DS2165Q

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DS2165Q 16/24/32KBPS ADPCM PROCESSOR 28-PIN PLCC

INCHES

DIM MIN MAX

A0.165 0.180

A1 0.090 0.120

A2 0.020 -

B0.026 0.033

B1 0.013 0.021

C0.009 0.012

D0.485 0.495

D1 0.450 0.456

D2 0.390 0.430

E0.485 0.495

E1 0.450 0.456

E2 0.390 0.430

L1 0.060 -

N28 -

e1 0.050 BSC

CH1 0.042 0.048