MC34912BACR2 - Freescale Semiconductor, Inc.

Document Number: MC33912

Rev. 8.0, 3/2010

Freescale Semiconductor

Advance Information

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

MC33912G5AC / MC34912G5AC

LIN System Basis Chip with DC

Motor Pre-driver and Current

Sense

The 33912G5/BAC is a Serial Peripheral Interface (SPI) controlled

System Basis Chip (SBC), combining many frequently used functions

in an MCU based system, plus a Local Interconnect Network (LIN)

transceiver. The 33912 has a 5.0 V, 50 mA/60 mA low dropout

regulator with full protection and reporting features. The device

provides full SPI readable diagnostics and a selectable timing

watchdog for detecting errant operation. The LIN Protocol Specification

2.0 and 2.1 compliant LIN transceiver has waveshaping circuitry that

can be disabled for higher data rates.

Two 50 mA/60 mA high side switches and two 150 mA/160 mA low

side switches with output protection are available. All outputs can be

pulse-width modulated (PWM). Four high voltage inputs are available

for use in contact monitoring, or as external wake-up inputs. These

inputs can be used as high voltage Analog Inputs. The voltage on these

pins is divided by a selectable ratio and available via an analog

multiplexer.

The 33912 has three main operating modes: Normal (all functions

available), Sleep (VDD off, wake-up via LIN, wake-up inputs (L1-L4),

cyclic sense and forced wake-up), and Stop (VDD on with limited current

capability, wake-up via CS, LIN bus, wake-up inputs, cyclic sense,

forced wake-up and external reset).

The 33912 is compatible with LIN Protocol Specification 2.0, 2.1, and

SAEJ2602-2.

Features

• Full-duplex SPI interface at frequencies up to 4.0 MHz

• LIN transceiver capable of up to 100 kbps with wave shaping

• Current sense module

• Four high voltage analog/logic Inputs

• Configurable window watchdog

• Switched/protected 5.0 V output (used for Hall sensors)

•Two 50 mA high side and two 150 mA/160 mA low side protected switches

•5.0 V low drop regulator with fault detection and low voltage reset (LVR) circuitry

• Pb-free packaging designated by suffix code AC

Figure 1. 33912 Simplified Application Diagram

33912

ORDERING INFORMATION

Device Temperature

Range (TA)Package

MC33912G5AC/R2 - 40°C to 125°C

32-LQFP

MC34912G5AC/R2 -40°C to 85°C

MC33912BAC/R2 - 40°C to 125°C

MC34912BAC/R2 -40°C to 85°C

AC SUFFIX (Pb-FREE)

98ASH70029A

32-PIN LQFP

SYSTEM BASIS CHIP WITH LIN

2ND GENERATION

* See Page 2 for Device Variations

MCU

33912

LIN INTERFACE

VS1

VS2

VSENSE

HS1

LS1

LS2

ISENSEH

ISENSEL

HVDD

HS2

WDCONF

AGND

LGND

PGND

LIN

VDD

PWMIN

ADOUT0

ADOUT1

MOSI

MISO

SCLK

RXD

TXD

IRQ

RST

BAT

Analog Integrated Circuit Device Data

2Freescale Semiconductor

33912

DEVICE VARIATIONS

MC33912G5AC / MC34912G5AC

DEVICE VARIATIONS

The 33912G5 data sheet is within MC33912G5 Product

Specifications Pages 3 to 47

The 33912BAC data sheet is within MC33912BAC

Product Specifications Pages 48 to 90

Table 1. Device Variations for the MC33912

Device Temperature Generation Changes

MC33912G5AC/R2 - 40°C to 125°C

2.5

1. Increase ESD Gun IEC61000-4-2 (gun test contact with 150 pF, 330 ohm test

conditions) performance to achieve ±6.0 kV min on the LIN pin.

2. Immunity against ISO7637 pulse 3b

3. Reduce EMC emission level on LIN

4. Improve EMC immunity against RF - target new specification including

3x68pF

5. Comply with J2602 conformance test

MC34912G5AC/R2 - 40°C to 85°C

MC33912BAC/R2 - 40°C to 125°C

2.0 Initial release

MC34912BAC/R2 - 40°C to 85°C

Analog Integrated Circuit Device Data

Freescale Semiconductor 3

33912

MC33912G5 PRODUCT SPECIFICATIONS PAGES 3 TO 47

MC33912G5AC / MC34912G5AC

MC33912G5 PRODUCT SPECIFICATIONS

PAGES 3 TO 47

Analog Integrated Circuit Device Data

4Freescale Semiconductor

33912

INTERNAL BLOCK DIAGRAM

MC33912G5AC / MC34912G5AC

INTERNAL BLOCK DIAGRAM

Figure 2. 33912 Simplified Internal Block Diagram

VOLTAGE REGULATOR

HIGH SIDE

CONTROL

MODULE

INTERRUPT CONTROL

MODULE

RESET CONTROL

MODULE

LVR, WD, EXT µC

WINDOW

WATCHDOG

MODULE

SPI

CONTROL

LIN PHYSICAL

LAYER

WAKE-UP MODULE

DIGITAL INPUT MODULE

ANALOG INPUT

CHIP TEMPERATURE

SENSE MODULE

ANALOG MULTIPLEXER

MODULE

AGND

PGND

HS1

LIN

RST IRQ VS2 VS1 VDD

PWMIN

MISO

MOSI

SCLK

ADOUT0

RXD

TXD

LGND WDCONF

VS2

LOW SIDE

CONTROL

MODULE

5V OUTPUT

MODULE HVDD

HS2

VS2

BAT

SENSE MODULE

VSENSE

LS2

LS1

CURRENT SENSE MODULE

ISENSEL

ISENSEH

ADOUT1

INTERNAL BUS

LVI, HVI,

ALL OT (VDD,HS,LS,LIN,SD)

Analog Integrated Circuit Device Data

Freescale Semiconductor 5

33912

PIN CONNECTIONS

MC33912G5AC / MC34912G5AC

PIN CONNECTIONS

Figure 3. 33912 Pin Connections

Table 2. 33912 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 24.

Pin Pin Name Formal Name Definition

1RXD Receiver Output This pin is the receiver output of the LIN interface which reports the state of

the bus voltage to the MCU interface.

2TXD Transmitter Input This pin is the transmitter input of the LIN interface which controls the state of

the bus output.

3MISO SPI Output SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the

high-impedance state.

4MOSI SPI Input SPI (Serial Peripheral Interface) data input.

5SCLK SPI Clock SPI (Serial Peripheral Interface) clock Input.

6CS SPI Chip Select SPI (Serial Peripheral Interface) chip select input pin. CS is active low.

7ADOUT0 Analog Output Pin 0 Analog Multiplexer Output.

8PWMIN PWM Input High Side and Low Side Pulse Width Modulation Input.

9RST Internal Reset I/O Bidirectional Reset I/O pin - driven low when any internal reset source is

asserted. RST is active low.

10 IRQ Internal Interrupt

Output

Interrupt output pin, indicating wake-up events from Stop mode or events from

Normal and Normal request modes. IRQ is active low.

11 ADOUT1 Analog Output Pin 1 Current sense analog output.

8PWMIN

7ADOUT0

5SCLK

4MOSI

3MISO

1RXD

2TXD

6CS

17 LS2

18 PGND

20 L4

21 L3

22 L2

24 HS2

23 L1

19 LS1

25 HS1

26 VS2

28 NC

29 VSENSE

30 HVDD

32 AGND

31 VDD

27 VS1

ISENSEH

LIN

WDCONF

ADOUT1

RST

IRQ

ISENSEL

LGND

Analog Integrated Circuit Device Data

6Freescale Semiconductor

33912

PIN CONNECTIONS

MC33912G5AC / MC34912G5AC

12 WDCONF Watchdog

Configuration Pin

This input pin is for configuration of the watchdog period and allows the

disabling of the watchdog.

13 LIN LIN Bus This pin represents the single-wire bus transmitter and receiver.

14 LGND LIN Ground Pin This pin is the device LIN ground connection. It is internally connected to the

PGND pin.

ISENSEL

ISENSEH Current Sense Pins Current Sense differential inputs.

LS2

LS1 Low Side Outputs Relay drivers low side outputs.

18 PGND Power Ground Pin This pin is the device low side ground connection. It is internally connected to

the LGND pin.

Wake-up Inputs These pins are the wake-up capable digital inputs(1). In addition, all Lx inputs

can be sensed analog via the analog multiplexer.

HS2

HS1 High Side Outputs High side switch outputs.

VS2

VS1 Power Supply Pin These pins are device battery level power supply pins. VS2 is supplying the

HSx drivers while VS1 supplies the remaining blocks.(2)

28 NC Not Connected This pin can be left open or connected to any potential ground or power

supply.

29 VSENSE Voltage Sense Pin Battery voltage sense input.(3)

30 HVDD Hall Sensor Supply

Output +5.0 V switchable supply output pin.(4)

31 VDD Voltage Regulator

Output +5.0 V main voltage regulator output pin.(5)

32 AGND Analog Ground Pin This pin is the device analog ground connection.

Notes

1. When used as digital input, a series 33 kΩ resistor must be used to protect against automotive transients.

2. Reverse battery protection series diodes must be used externally to protect the internal circuitry.

3. This pin can be connected directly to the battery line for voltage measurements. The pin is self protected against reverse battery

connections. It is strongly recommended to connect a 10 kΩ resistor in series with this pin for protection purposes.

4. External capacitor (1.0 µF < C < 10 µF; 0.1 Ω < ESR < 5.0 Ω) required.

5. External capacitor (2.0 µF < C < 100 µF; 0.1 Ω < ESR < 10 Ω) required.

Table 2. 33912 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 24.

Pin Pin Name Formal Name Definition

Analog Integrated Circuit Device Data

Freescale Semiconductor 7

33912

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

MC33912G5AC / MC34912G5AC

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 3. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings Symbol Value Unit

ELECTRICAL RATINGS

Supply Voltage at VS1 and VS2

Normal Operation (DC)

Transient Conditions (load dump)

VSUP(SS)

VSUP(PK)

-0.3 to 27

-0.3 to 40

Supply Voltage at VDD VDD -0.3 to 5.5 V

Input / Output Pins Voltage(6)

CS, RST, SCLK, PWMIN, ADOUT0, ADOUT1, MOSI, MISO, TXD, RXD,

HVDD

Interrupt Pin (IRQ)(7)

VIN

VIN(IRQ)

-0.3 to VDD +0.3

-0.3 to 11

HS1 and HS2 Pin Voltage (DC) VHS - 0.3 to VSUP +0.3 V

LS1 and LS2 Pin Voltage (DC) VLS -0.3 to 45 V

L1, L2, L3 and L4 Pin Voltage

Normal Operation with a series 33 k resistor (DC)

Transient input voltage with external component (according to ISO7637-2)

(See Figure 5, page 20)

VLxDC

VLxTR

-18 to 40

±100

ISENSEH and ISENSEL Pin Voltage (DC) VISENSE -0.3 to 40 V

VSENSE Pin Voltage (DC) VVSENSE -27 to 40 V

LIN Pin Voltage

Normal Operation (DC)

Transient input voltage with external component (according to ISO7637-2)

(See Figure 4, page 20)

VBUSDC

VBUSTR

-18 to 40

-150 to 100

VDD output current IVDD Internally Limited A

Notes

6. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device.

7. Extended voltage range for programming purpose only.

Analog Integrated Circuit Device Data

8Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

MC33912G5AC / MC34912G5AC

ESD Capability

AECQ100

Human Body Model - JESD22/A114 (CZAP = 100 pF, RZAP = 1500 Ω)

LIN Pin

L1, L2, L3, and L4

all other Pins

Charge Device Model - JESD22/C101 (CZAP = 4.0 pF)

Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25 and 32)

All other Pins (Pins 2-7, 10-15, 18-23, 26-31)

According to LIN Conformance Test Specification / LIN EMC Test

Specification, August 2004 (CZAP = 150 pF, RZAP = 330 Ω)

Contact Discharge, Unpowered

LIN pin with 220 pF

LIN pin without capacitor

VS1/VS2 (100 nF to ground)

Lx inputs (33 kΩ serial resistor)

According to IEC 61000-4-2 (CZAP = 150 pF, RZAP = 330 Ω)

Unpowered

LIN pin with 220 pF and without capacitor

VS1/VS2 (100 nF to ground)

Lx inputs (33 kΩ serial resistor)

VESD1-1

VESD1-2

VESD1-3

VESD2-1

VESD2-2

VESD3-1

VESD3-2

VESD3-3

VESD3-4

VESD4-1

VESD4-2

VESD4-3

± 8.0k

± 6.0k

±2000

± 750

± 500

± 20k

± 11k

>± 12k

±6000

± 8000

THERMAL RATINGS

Operating Ambient Temperature (8)

33912

34912

-40 to 125

-40 to 85

°C

Operating Junction Temperature TJ-40 to 150 °C

Storage Temperature TSTG -55 to 150 °C

Thermal Resistance, Junction to Ambient

Natural Convection, Single Layer board (1s)(8), (9)

Natural Convection, Four Layer board (2s2p)(8), (10)

RθJA

°C/W

Thermal Resistance, Junction to Case(11) RθJC 23 °C/W

Peak Package Reflow Temperature During Reflow(12), (13) TPPRT Note 13 °C

Notes

8. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

9. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.

10. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

11. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

12. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

13. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL), go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and

enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

Table 3. Maximum Ratings (continued)

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings Symbol Value Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 9

33912

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

MC33912G5AC / MC34912G5AC

STATIC ELECTRICAL CHARACTERISTICS

Table 4. Static Electrical Characteristics

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

SUPPLY VOLTAGE RANGE (VS1, VS2)

Nominal Operating Voltage VSUP 5.5 –18 V

Functional Operating Voltage(14) VSUPOP – – 27 V

Load Dump VSUPLD – – 40 V

SUPPLY CURRENT RANGE (VSUP = 13.5 V)

Normal Mode (IOUT at VDD = 10 mA), LIN Recessive State(15) IRUN –4.5 10 mA

Stop Mode, VDD ON with IOUT = 100 µA, LIN Recessive State(15), (16),

(17), (18)

5.5 V < VSUP < 12 V

VSUP = 13.5 V

13.5 V < VSUP < 18 V

ISTOP

–

180

400

µA

Sleep Mode, VDD OFF, LIN Recessive State(15), (17)

5.5 V < VSUP < 12 V

VSUP = 13.5 V

13.5 V ≤ VSUP < 18 V

ISLEEP

–

160

300

µA

Cyclic Sense Supply Current Adder(19) ICYCLIC –10 –µA

SUPPLY UNDER/OVER-VOLTAGE DETECTIONS

Power-On Reset (BATFAIL)(20)

Threshold (measured on VS1)(19)

Hysteresis (measured on VS1)(19)

VBATFAIL

VBATFAIL_HYS

1.5

–

3.0

0.9

3.9

–

VSUP under-voltage detection (VSUV Flag) (Normal and Normal Request

Modes, Interrupt Generated)

Threshold (measured on VS1)

Hysteresis (measured on VS1)

VSUV

VSUV_HYS

5.55

–

6.0

0.2

6.6

–

VSUP over-voltage detection (VSOV Flag) (Normal and Normal Request

Modes, Interrupt Generated)

Threshold (measured on VS1)

Hysteresis (measured on VS1)

VSOV

VSOV_HYS

–

19.25

1.0

20.5

–

Notes

14. Device is fully functional. All features are operating.

15. Total current (IVS1 + IVS2) measured at GND pins excluding all loads, cyclic sense disabled.

16. Total IDD current (including loads) below 100 µA.

17. Stop and Sleep Modes current will increase if VSUP exceeds13.5 V.

18. This parameter is guaranteed after 90 ms.

19. This parameter is guaranteed by process monitoring but not production tested.

20. The Flag is set during power up sequence. To clear the flag, a SPI read must be performed.

Analog Integrated Circuit Device Data

10 Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

MC33912G5AC / MC34912G5AC

VOLTAGE REGULATOR(21) (VDD)

Normal Mode Output Voltage

1.0 mA < IVDD < 50 mA; 5.5 V < VSUP < 27 V

VDDRUN

4.75 5.00 5.25

Normal Mode Output Current Limitation IVDDRUN 60 110 200 mA

Dropout Voltage(22)

IVDD = 50 mA

VDDDROP

–0.1 0.25

Stop Mode Output Voltage

IVDD < 5.0 mA

VDDSTOP

4.75 5.0 5.25

Stop Mode Output Current Limitation IVDDSTOP 6.0 13 36 mA

Line Regulation

Normal Mode, 5.5 V < VSUP < 18 V; IVDD = 10 mA

Stop Mode, 5.5 V < VSUP < 18 V; IVDD = 1.0 mA

LRRUN

LRSTOP

–

Load Regulation

Normal Mode, 1.0 mA < IVDD < 50 mA

Stop Mode, 0.1 mA < IVDD < 5.0 mA

LDRUN

LDSTOP

–

Over-temperature Prewarning (Junction)(23)

Interrupt generated, VDDOT Bit Set

TPRE

90 115 140

°C

Over-temperature Prewarning Hysteresis(23) TPRE_HYS –13 –°C

Over-temperature Shutdown Temperature (Junction)(23) TSD 150 170 190 °C

Over-temperature Shutdown Hysteresis(23) TSD_HYS –13 –°C

HALL SENSOR SUPPLY OUTPUT(24) (HVDD)

VDD Voltage matching HVDDACC = (HVDD-VDD) / VDD * 100%

IHVDD = 15 mA

HVDDACC

-2.0 –2.0

Current Limitation IHVDD 20 35 50 mA

Dropout Voltage

IHVDD = 15 mA; IVDD = 5.0 mA

HVDDDROP

–160 300

Line Regulation

IHVDD = 5.0 mA; IVDD = 5.0 mA

LRHVDD

– – 40

Load Regulation

1.0 mA > IHVDD > 15 mA; IVDD = 5.0 mA

LDHVDD

– – 20

Notes

21. Specification with external capacitor 2.0 µF < C < 100 µF and 100 mΩ ≤ ESR ≤ 10 Ω.

22. Measured when voltage has dropped 250 mV below its nominal Value (5.0 V).

23. This parameter is guaranteed by process monitoring but not production tested.

24. Specification with external capacitor 1.0 µF < C < 10 µF and 100 mΩ ≤ ESR ≤ 10 Ω.

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 11

33912

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

MC33912G5AC / MC34912G5AC

RST INPUT/OUTPUT PIN (RST)

VDD Low Voltage Reset Threshold VRSTTH 4.3 4.5 4.7 V

Low-state Output Voltage

IOUT = 1.5 mA; 3.5 V ≤ VSUP ≤ 27 V

VOL

0.0 –0.9

High-state Output Current (0 V < VOUT < 3.5 V) IOH -150 -250 -350 µA

Pull-down Current Limitation (internally limited)

VOUT = VDD

IPD_MAX

1.5 –8.0

Low-state Input Voltage VIL -0.3 –0.3 x VDD V

High-state Input Voltage VIH 0.7 x VDD – VDD +0.3 V

MISO SPI OUTPUT PIN (MISO)

Low-state Output Voltage

IOUT = 1.5 mA

VOL

0.0 –1.0

High-state Output Voltage

IOUT = -250 µA

VOH

VDD -0.9 – VDD

Tri-state Leakage Current

0 V ≤ VMISO ≤ VDD

ITRIMISO

-10 –10

µA

SPI INPUT PINS (MOSI, SCLK, CS)

Low-state Input Voltage VIL -0.3 –0.3 x VDD V

High-state Input Voltage VIH 0.7 x VDD – VDD +0.3 V

MOSI, SCLK Input Current

0 V ≤ VIN ≤ VDD

IIN

-10 –10

µA

CS Pull-up Current

0 V < VIN < 3.5 V

IPUCS

10 20 30

µA

INTERRUPT OUTPUT PIN (IRQ)

Low-state Output Voltage

IOUT = 1.5 mA

VOL

0.0 –0.8

High-state Output Voltage

IOUT = -250 µA

VOH

VDD -0.8 – VDD

Leakage Current

VDD ≤ VOUT ≤ 10 V

IOUT

– – 2.0

PULSE WIDTH MODULATION INPUT PIN (PWMIN)

Low-state Input Voltage VIL -0.3 –0.3 x VDD V

High-state Input Voltage VIH 0.7 x VDD – VDD +0.3 V

Pull-up current

0 V < VIN < 3.5 V

IPUPWMIN

10 20 30

µA

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

12 Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

MC33912G5AC / MC34912G5AC

HIGH SIDE OUTPUTS HS1 AND HS2 PINS (HS1, HS2)

Output Drain-to-Source On Resistance

TJ = 25°C, ILOAD = 50 mA; VSUP > 9.0 V

TJ = 150°C, ILOAD = 50 mA; VSUP > 9.0 V(25)

TJ = 150°C, ILOAD = 30 mA; 5.5 V < VSUP < 9.0 V(25)

RDS(ON)

–

7.0

Output Current Limitation(26)

0 V < VOUT < VSUP - 2.0 V

ILIMHSX

60 90 250

Open Load Current Detection(27) IOLHSX –5.0 7.5 mA

Leakage Current

-0.2 V < VHSX < VS2 + 0.2 V

ILEAK

– – 10

µA

Short-circuit Detection Threshold(28)

5.5 V < VSUP < 27 V

VTHSC

VSUP -2.0 – –

Over-temperature Shutdown(29), (33) THSSD 140 160 180 °C

Over-temperature Shutdown Hysteresis(33) THSSD_HYS –10 –°C

LOW SIDE OUTPUTS LS1 AND LS2 PINS (LS1, LS2)

Output Drain-to-Source On Resistance

TJ = 25°C, ILOAD = 150 mA, VSUP > 9.0 V

TJ = 125°C, ILOAD = 150 mA, VSUP > 9.0 V

TJ = 125°C, ILOAD = 120 mA, 5.5 V < VSUP < 9.0 V

RDS(ON)

–

2.5

4.5

Output Current Limitation(30)

2.0 V < VOUT < VSUP

ILIMLSX

160 275 350

Open Load Current Detection(31) IOLLSX –7.5 12 mA

Leakage Current

-0.2 V < VOUT < VS1

ILEAK

– – 10

µA

Active Output Energy Clamp

IOUT = 150 mA

VCLAMP

VSUP +2.0 – VSUP +5.0

Short-circuit Detection Threshold(28)

5.5 V < VSUP < 27 V

VTHSC

2.0 – –

Over-temperature Shutdown(32), (33) TLSSD 140 160 180 °C

Over-temperature Shutdown Hysteresis(33) TLSSD_HYS –10 –°C

Notes

25. This parameter is production tested up to TA = 125°C, and guaranteed by process monitoring up to TJ = 150°C.

26. When over-current occurs, the corresponding high side stays ON with limited current capability and the HSxCL flag is set in the HSSR.

27. When open load occurs, the flag (HSxOP) is set in the HSSR.

28. HS and LS automatically shutdown if HSOT or LSOT occurs or if the HVSE flag is enabled and an over-voltage occurs.

29. When over-temperature shutdown occurs, both high sides are turned off. All flags in HSSR are set.

30. When over-current occurs, the corresponding low side stays ON with limited current capability and the LSxCL flag is set in the LSSR.

31. When open load occurs, the flag (LSxOP) is set in the LSSR.

32. When over-temperature shutdown occurs, both low sides are turned off. All flags in LSSR are set.

33. Guaranteed by characterization but not production tested

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 13

33912

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

MC33912G5AC / MC34912G5AC

L1, L2, L3 AND L4 INPUT PINS (L1, L2, L3, L4)

Low Detection Threshold(34)

5.5 V < VSUP < 27 V

VTHL

2.0 2.5 3.0

High Detection Threshold(34)

5.5 V < VSUP < 27 V

VTHH

3.0 3.5 4.0

Hysteresis(34)

5.5 V < VSUP < 27 V

VHYS

0.4 0.8 1.4

Input Current(35)

-0.2 V < VIN < VS1

IIN

-10 –10

µA

Analog Input Impedance(36) RLXIN 800 1300 2000 kΩ

Analog Input Divider Ratio (RATIOLx = VLx / VADOUT0)

LXDS (Lx Divider Select) = 0

LXDS (Lx Divider Select) = 1

RATIOLX

0.95

3.42

1.0

3.6

1.05

3.78

Analog Output offset Ratio

LXDS (Lx Divider Select) = 0

LXDS (Lx Divider Select) = 1

VRATIOLx-

OFFSET -80

-22

6.0

2.0

Analog Inputs Matching

LXDS (Lx Divider Select) = 0

LXDS (Lx Divider Select) = 1

LXMATCHING

100

104

WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)(37)

External Resistor Range REXT 20 –200 kΩ

Watchdog Period Accuracy with External Resistor (Excluding Resistor

Accuracy)(38) WDACC -15 –15 %

ANALOG MULTIPLEXER

Temperature Sense Analog Output Voltage

TA = -40°C

TA = 25°C

TA = 125°C

VADOUT0_TEMP

2.0

2.8

3.6

3.0

2.8

3.6

4.6

Temperature Sense Analog Output Voltage per characterization(39)

TA = 25°C

VADOUT0_25 3.1 3.15 3.2 V

Internal Chip Temperature Sense Gain STTOV 9.0 10.5 12 mV/K

Internal Chip Temperature Sense Gain per characterization at 3

temperatures(39) See Figure 16, Temperature Sense Gain

STTOV_3T 9.9 10.2 10.5 mV/K

VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / VADOUT0)

5.5 V < VSUP < 27 V

RATIOVSENSE

5.0 5.25 5.5

Notes

34. The unused Lx pins must be connected to ground.

35. Analog multiplexer input disconnected from Lx input pin.

36. Analog multiplexer input connected to Lx input pin.

37. For VSUP 4.7 V to 18 V

38. Watchdog timing period calculation formula: tPWD [ms] = [0.466 * (REXT - 20)] + 10 with (REXT in kΩ)

39. These limits have been defined after laboratory characterization on 3 lots and 30 samples. These tighten limits could not be guaranteed

by production test.

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

14 Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

MC33912G5AC / MC34912G5AC

VSENSE Input Divider Ratio (RATIOVSENSE=VSENSE/VADOUT0) per

characterization(40)

5.5 <VSUP< 27 V

RATIOVSENSEC

5.15 5.25 5.35

VSENSE Output Related Offset OFFSETVSENSE

-30 -10 30

VSENSE Output Related Offset per characterization(40) OFFSETVSENSE

_CZ -30 -12.6 0

ANALOG OUTPUTS (ADOUT0 AND ADOUT1)

Maximum Output Voltage

-5.0 mA < IO < 5.0 mA

VOUT_MAX

VDD -0.35 – VDD

Minimum Output Voltage

-5.0 mA < IO < 5.0 mA

VOUT_MIN

0.0 –0.35

CURRENT SENSE AMPLIFIER (ISENSEH, ISENSEL)

Gain

CSGS (Current Sense Gain Select) = 0

CSGS (Current Sense Gain Select) = 1

14.5

Differential Input Impedance

CSGS (Current Sense Gain Select) = 0

CSGS (Current Sense Gain Select) = 1

DIFF

2.0

5.0

kΩ

Common Mode Input Impedance

CSGS (Current Sense Gain Select) = 0

CSGS (Current Sense Gain Select) = 1

100

–

200

kΩ

ISENSEH, ISENSEL Input Voltage Range VIN -0.2 –3.0 V

Input Offset Voltage

CSAZ (Current Sense Auto Zero) = 0

CSAZ (Current Sense Auto Zero) = 1

VIN_OFFSET

-15

-2.0

–

2.0

RXD OUTPUT PIN (LIN PHYSICAL LAYER) (RXD)

Low-state Output Voltage

IOUT = 1.5 mA

VOL

0.0 –0.8

High-state Output Voltage

IOUT = -250 µA

VOH

VDD -0.8 – VDD

TXD INPUT PIN (LIN PHYSICAL LAYER) (TXD)

Low-state Input Voltage VIL -0.3 –0.3 x VDD V

High-state Input Voltage VIH 0.7 x VDD – VDD +0.3 V

Pin Pull-up Current, 0 V < VIN < 3.5 V IPUIN 10 20 30 µA

LIN PHYSICAL LAYER WITH J2602 FEATURE ENABLED (BIT DIS_J2602 = 0)

LIN Under-voltage threshold

Positive and Negative threshold (VTHP, VTHN)

VTH_UNDER_VOL

TAGE 5.0 -6.0

Hysteresis (VTHP - VTHN)VJ2602_DEG -400 -mV

Notes

40. These limits have been defined after laboratory characterization on 3 lots and 30 samples. These tighten limits could not be guaranteed

by production test.

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 15

33912

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

MC33912G5AC / MC34912G5AC

LIN PHYSICAL LAYER, TRANSCEIVER (LIN)(41)

Operating Voltage Range VBAT 8.0 -18 V

Supply Voltage Range VSUP 7.0 -18 V

Voltage Range within which the device is not destroyed VSUP_NON_OP -0.3 -40 V

Current Limitation for Driver Dominant State

Driver ON, VBUS = 18 V

IBUS_LIM

40 90 200

Input Leakage Current at the receiver

Driver off; VBUS = 0 V; VBAT = 12 V

IBUS_PAS_DOM

-1.0 – –

Leakage Output Current to GND

Driver Off; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS ≥ VBAT

IBUS_PAS_REC

– – 20

µA

Control unit disconnected from ground(42)

GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V

IBUS_NO_GND

-1.0 –1.0

VBAT Disconnected; VSUP_DEVICE = GND; 0 V < VBUS < 18 V(43) IBUSNO_BAT

– – 100

µA

Receiver Dominant State VBUSDOM

– – 0.4

VSUP

Receiver Recessive State VBUSREC

0.6 – –

VSUP

Receiver Threshold Center

(VTH_DOM + VTH_REC)/2

VBUS_CNT

0.475 0.5 0.525

VSUP

Receiver Threshold Hysteresis

(VTH_REC - VTH_DOM)

VHYS

– – 0.175

VSUP

Voltage Drop at the serial Diode in pull-up path VSERDIODE 0.4 1.0 V

VBAT_SHIFT VSHIFT_BAT 011.5% VBAT

GND_SHIFT VSHIFT_GND 011.5% VBAT

LIN Wake-up threshold from Stop or Sleep mode(44) VBUSWU 5.3 5.8 V

LIN Pull-up Resistor to VSUP RSLAVE 20 30 60 kΩ

Over-temperature Shutdown(45) TLINSD 140 160 180 °C

Over-temperature Shutdown Hysteresis TLINSD_HYS –10 –°C

Notes

41. Parameters guaranteed for 7.0 V ≤ VSUP ≤ 18 V.

42. Loss of local ground must not affect communication in the residual network.

43. Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition.

44. This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, Freescale

does not guarantee this parameter during the product's life time.

45. When over-temperature shutdown occurs, the LIN bus goes in recessive state and the flag LINOT in LINSR is set.

Table 4. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

16 Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

MC33912G5AC / MC34912G5AC

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

SPI INTERFACE TIMING (SEE Figure 13, PAGE 23)

SPI Operating Frequency f

SPIOP – – 4.0 MHz

SCLK Clock Period tPSCLK 250 – N/A ns

SCLK Clock High Time(46) tWSCLKH 110 – N/A ns

SCLK Clock Low Time(46) tWSCLKL 110 – N/A ns

Falling Edge of CS to Rising Edge of SCLK(46) tLEAD 100 – N/A ns

Falling Edge of SCLK to CS Rising Edge(46) tLAG 100 – N/A ns

MOSI to Falling Edge of SCLK(46) tSISU 40 – N/A ns

Falling Edge of SCLK to MOSI(46) tSIH 40 – N/A ns

MISO Rise Time(46)

CL = 220 pF

tRSO

–40 –

MISO Fall Time(46)

CL = 220 pF

tFSO

–40 –

Time from Falling or Rising Edges of CS to:(46)

- MISO Low-impedance

- MISO High-impedance

tSOEN

tSODIS

0.0

–

Time from Rising Edge of SCLK to MISO Data Valid(46)

0.2 x VDD ≤ MISO ≥ 0.8 x VDD, CL = 100 pF

tVALID

0.0 –75

RST OUTPUT PIN

Reset Low-level Duration After VDD High (see Figure 12, page 23)t

RST 0.65 1.0 1.35 ms

Reset Deglitch Filter Time t

RSTDF 350 480 900 ns

WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)

Watchdog Time Period(47)

External Resistor REXT = 20 kΩ (1%)

External Resistor REXT = 200 kΩ (1%)

Without External Resistor REXT (WDCONF Pin Open)

t PWD

8.5

110

150

11.5

108

205

CURRENT SENSE AMPLIFIER(46)

Common Mode Rejection Ratio CMR 70 – – dB

Supply Voltage Rejection Ratio(48) SVR 60 – – dB

Gain Bandwidth Product GBP 0.75 3.0 –MHz

Output Slew-Rate SR 0.5 – – V/µs

Notes

46. This parameter is guaranteed by process monitoring but not production tested.

47. Watchdog timing period calculation formula: tPWD [ms] = [0.466 * (REXT - 20)] + 10 with (REXT in kΩ)

48. Analog Outputs are supplied by VDD and from 100 Hz to 4.0 kHz

Analog Integrated Circuit Device Data

Freescale Semiconductor 17

33912

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

MC33912G5AC / MC34912G5AC

L1, L2, L3 AND L4 INPUTS

Lx Filter Time Deglitcher(49) t

WUF 8.0 20 38 μs

STATE MACHINE TIMING

Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)

and Stop Mode Activation(49) t

STOP

– – 5.0

μs

Normal Request Mode Timeout (see Figure 12, page 23)t

NR TOUT 110 150 205 ms

Cyclic Sense ON Time from Stop and Sleep mode(50) TON 130 200 270 µs

Cyclic Sense Accuracy(49) -35 +35 %

Delay Between SPI Command and HS /LS Turn On(51)

9.0 V < VSUP < 27 V

t S-ON

– – 10

μs

Delay Between SPI Command and HS /LS Turn Off(51)

9.0 V < VSUP < 27 V

S-OFF

– – 10

μs

Delay Between Normal Request and Normal mode After a Watchdog Trigger

Command (Normal Request Mode)(49) t

SNR2N

– – 10

μs

Delay Between CS Wake-up (CS LOW to HIGH) in Stop mode and:

Normal Request mode, VDD ON and RST HIGH

First Accepted SPI Command

WUCS

WUSPI

9.0

—

N/A

μs

Minimum Time Between Rising and Falling Edge on the CS t

2CS 4.0 — — μs

J2602 DEGLITCHER

VSUP Deglitcher(52)

(DIS_J2602 = 0)

tJ2602_DEG

35 50 70

μs

Notes

49. This parameter is guaranteed by process monitoring but not production tested.

50. This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, Freescale

does not guarantee this parameter during the product's life time.

51. Delay between turn on or off command (rising edge on CS) and HS or LS ON or OFF, excluding rise or fall time due to external load.

52. This parameter has not been monitoring during operating life test.

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

18 Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

MC33912G5AC / MC34912G5AC

LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0KBIT/SEC ACCORDING TO LIN PHYSICAL

LAYER SPECIFICATION(53), (54)

Duty Cycle 1:

THREC(MAX) = 0.744 * VSUP

THDOM(MAX) = 0.581 * VSUP

D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V ≤ VSUP ≤ 18 V

0.396 — —

Duty Cycle 2:

THREC(MIN) = 0.422 * VSUP

THDOM(MIN) = 0.284 * VSUP

D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V ≤ VSUP ≤ 18 V

— — 0.581

LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER

SPECIFICATION(53), (55)

Duty Cycle 3:

THREC(MAX) = 0.778 * VSUP

THDOM(MAX) = 0.616 * VSUP

D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V ≤ VSUP ≤ 18 V

0.417 — —

Duty Cycle 4:

THREC(MIN) = 0.389 * VSUP

THDOM(MIN) = 0.251 * VSUP

D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V ≤ VSUP ≤ 18 V

— — 0.590

Notes

53. Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal

threshold defined at each parameter. See Figure 6, page 21.

54. See Figure 7, page 21.

55. See Figure 8, page 21.

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 19

33912

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

MC33912G5AC / MC34912G5AC

LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE

LIN Fast Slew Rate (Programming mode) SRFAST —20 — V / μs

LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS(56)

Propagation Delay and Symmetry(57)

Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF)

Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR

REC_PD

REC_SYM

—

- 2.0

4.2

—

6.0

2.0

μs

Bus Wake-Up Deglitcher (Sleep and Stop modes)(58)(62) (59) t PROPWL 42 70 95 μs

Bus Wake-Up Event Reported

From Sleep Mode(60)

From Stop Mode(61)

WAKE_SLEEP

WAKE_STOP

—

9.0

—

1500

μs

TXD Permanent Dominant State Delay t TXDDOM 0.65 1.0 1.35 s

PULSE WIDTH MODULATION INPUT PIN (PWMIN)

PWMIN pin(62)

Max. frequency to drive HS and LS output pins

fPWMIN

-10 -

kHz

Notes

56. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD

signal to LIN signal threshold defined at each parameter. See Figure 6, page 21.

57. See Figure 9, page 22

58. See Figure 10, page 22 for Sleep and Figure 11, page 22 for Stop Mode.

59. This parameter is tested on automatic tester but has not been monitoring during operating life test.

60. The measurement is done with 1µF capacitor and 0mA current load on VDD. The value takes into account the delay to charge the

capacitor. The delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when VDD reaches 3.0V.

See Figure 10, page 22. The delay depends of the load and capacitor on VDD.

61. In Stop Mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 11,

page 22.

62. This parameter is guaranteed by process monitoring but not production tested.

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

20 Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

MC33912G5AC / MC34912G5AC

TIMING DIAGRAMS

Figure 4. Test Circuit for Transient Test Pulses (LIN)

Figure 5. Test Circuit for Transient Test Pulses (Lx)

Figure 6. Test Circuit for LIN Timing Measurements

Note

Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.

LIN

TRANSIENT PULSE

PGND

GENERATOR

1.0 nF

(

NOTE

)

GND

33912

LGND AGND

L1, L2, L3, L4

Transient Pulse

PGND

Generator

1.0 nF

(Note)

10 k

Note

Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b,.

GND

33912

LGND AGND

R0 AND C0 COMBINATIONS:

• 1.0 KΩ and 1.0 nF

• 660 Ω and 6.8 nF

• 500 Ω and 10 nF

VSUP

TXD

RXD

LIN

C0C0

Analog Integrated Circuit Device Data

Freescale Semiconductor 21

33912

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

MC33912G5AC / MC34912G5AC

Figure 7. LIN Timing Measurements for Normal Slew Rate

Figure 8. LIN Timing Measurements for Slow Slew Rate

TXD

LIN

RXD

tBIT tBIT

tBUS_DOM(MAX) tBUS_REC(MIN)

tREC_PDF(1)

74.4% V

SUP

42.2% VSUP

58.1% VSUP

28.4% VSUP

tBUS_REC(MAX)

VLIN_REC

tBUS_DOM(MIN)

RXD

Output of receiving Node 1

Output of receiving Node 2

THREC(MAX)

THDOM(MAX)

THREC(MIN)

THDOM(MIN)

Thresholds of

receiving node 1

Thresholds of

receiving node 2

tREC_PDR(1)

tREC_PDF(2)

tREC_PDR(2)

TXD

LIN

RXD

tBIT tBIT

tBUS_DOM(MAX) tBUS_REC(MIN)

tREC_PDF(1)

77.8% V

SUP

38.9% VSUP

61.6% VSUP

25.1% VSUP

tBUS_REC(MAX)

VLIN_REC

tBUS_DOM(MIN)

RXD

Output of receiving Node 1

Output of receiving Node 2

THREC(MAX)

THDOM(MAX)

THREC(MIN)

THDOM(MIN)

Thresholds of

receiving node 1

Thresholds of

receiving node 2

tREC_PDR(1)

tREC_PDF(2)

tREC_PDR(2)

Analog Integrated Circuit Device Data

22 Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

MC33912G5AC / MC34912G5AC

Figure 9. LIN Receiver Timing

Figure 10. LIN Wake-Up Sleep Mode Timing

Figure 11. LIN Wake-up Stop Mode Timing

VBUSREC

VBUSDOM

VSUP

LIN BUS SIGNAL

tREC_PDR

tREC_PDF

RXD

VLIN_REC

0.4% VSUP

0.6% VSUP

DOMINANT LEVEL

5.0 V

VLIN_REC

LIN

VDD

tPROPWL tWAKE_SLEEP

3.0 V

VBUSWU

tPROPWL tWAKE_STOP

IRQ

VBUSWU

DOMINANT LEVEL

5.0 V

VLIN_REC

LIN

Analog Integrated Circuit Device Data

Freescale Semiconductor 23

33912

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

MC33912G5AC / MC34912G5AC

Figure 12. Power On Reset and Normal Request Timeout Timing

Figure 13. SPI Timing Characteristics

VSUP

VDD

RST

tRST

tNRTOUT

UNDEFINED DON’T CARE D7 DON’T CARE

tLEAD

tSIH

tSISU

tLAG

tPSCLK

tWSCLKH

tWSCLKL

tVALID

DON’T CARE D7

tSODIS

SCLK

MOSI

MISO

tSOEN

Analog Integrated Circuit Device Data

24 Freescale Semiconductor

33912

FUNCTIONAL DESCRIPTION

INTRODUCTION

MC33912G5AC / MC34912G5AC

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33912 was designed and developed as a highly

integrated and cost-effective solution for automotive and

industrial applications. For automotive body electronics, the

33912 is well suited to perform relay control in applications

such as a window lift, sunroof, etc. via the LIN bus.

Power switches are provided on the device configured as

high side and low side outputs. Other ports are also provided,

which include a current and voltage sense port, a Hall Sensor

port supply, and four wake-up capable pins. An internal

voltage regulator provides power to a MCU device.

Also included in this device is a LIN physical layer, which

communicates using a single wire. This enables this device

to be compatible with 3-wire bus systems, where one wire is

used for communication, one for battery, and one for ground.

FUNCTIONAL PIN DESCRIPTION

See Figure 1, 33912 Simplified Application Diagram,

page 1, for a graphic representation of the various pins

referred to in the following paragraphs. Also, see the pin

diagram on page 5 for a description of the pin locations in the

package.

RECEIVER OUTPUT PIN (RXD)

The RXD pin is a digital output. It is the receiver output of

the LIN interface and reports the state of the bus voltage:

RXD Low when LIN bus is dominant, RXD High when LIN bus

is recessive.

TRANSMITTER INPUT PIN (TXD)

The TXD pin is a digital input. It is the transmitter input of

the LIN interface and controls the state of the bus output

(dominant when TXD is Low, recessive when TXD is High).

This pin has an internal pull-up to force recessive state in

case the input is left floating.

LIN BUS PIN (LIN)

The LIN pin represents the single-wire bus transmitter and

receiver. It is suited for automotive bus systems and is

compliant to the LIN bus specification 2.0, 2.1, and SAE

J2602-2.

The LIN interface is only active during Normal Mode. See

Table 6, Operating Modes Overview.

SERIAL DATA CLOCK PIN (SCLK)

The SCLK pin is the SPI clock input. MISO data changes

on the positive transition of the SCLK. MOSI is sampled on

the negative edge of the SCLK.

MASTER OUT SLAVE IN PIN (MOSI)

The MOSI digital pin receives SPI data from the MCU. This

data input is sampled on the negative edge of SCLK.

MASTER IN SLAVE OUT PIN (MISO)

The MISO pin sends data to an SPI-enabled MCU. It is a

digital tri-state output used to shift serial data to the

microcontroller. Data on this output pin changes on the

positive edge of the SCLK. When CS is High, this pin will

remain in the high-impedance state.

CHIP SELECT PIN (CS)

CS is an active low digital input. It must remain low during

a valid SPI communication and allow for several devices to

be connected in the same SPI bus without contention. A

rising edge on CS signals the end of the transmission and the

moment the data shifted in is latched. A valid transmission

must consist of 8 bits only.

While in STOP Mode, a low-to-high level transition on this

pin will generate a wake-up condition for the 33912.

ANALOG MULTIPLEXER PIN (ADOUT0)

The ADOUT0 pin can be configured via the SPI to allow

the MCU A/D converter to read the several inputs of the

Analog Multiplexer, including the VSENSE, L1, L2, L3, L4

input voltages, and the internal junction temperature.

CURRENT SENSE AMPLIFIER PIN (ADOUT1)

The ADOUT1 pin is an analog interface to the MCU A/D

converter. It allows the MCU to read the output of the current

sense amplifier.

PWM INPUT CONTROL PIN (PWMIN)

This digital input can control the high sides and low sides

drivers in Normal Request and Normal Mode.

To enable PWM control, the MCU must perform a write

operation to the High Side Control Register (HSCR) or the

Low Side Control Register (LSCR).

This pin has an internal 20 μA current pull-up.

Analog Integrated Circuit Device Data

Freescale Semiconductor 25

33912

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

MC33912G5AC / MC34912G5AC

RESET PIN (RST)

This bidirectional pin is used to reset the MCU in case the

33912 detects a reset condition, or to inform the 33912 that

the MCU has just been reset. After release of the RST pin,

Normal Request Mode is entered.

The RST pin is an active low filtered input and output

formed by a weak pull-up and a switchable pull-down

structure which allows this pin to be shorted either to VDD or

to GND during software development, without the risk of

destroying the driver.

INTERRUPT PIN (IRQ)

The IRQ pin is a digital output used to signal events or

faults to the MCU while in Normal and Normal Request mode

or to signal a wake-up from Stop mode. This active low output

will transition to high only after the interrupt is acknowledged

by a SPI read of the respective status bits.

WATCHDOG CONFIGURATION PIN (WDCONF)

The WDCONF pin is the configuration pin for the internal

watchdog. A resistor can be connected to this pin to configure

the window watchdog period. When connected directly to

ground, the watchdog will be disabled. When this pin is left

open, the watchdog period is fixed to its lower precision

internal default value (150 ms typical).

GROUND CONNECTION PINS (AGND, PGND,

LGND)

The AGND, PGND and LGND pins are the Analog and

Power ground pins.

The AGND pin is the ground reference of the voltage

regulator and the current sense module.

The PGND and LGND pins are used for high current load

return as in the relay-drivers and LIN interface pin.

Note: PGND, AGND and LGND pins must be connected

together.

CURRENT SENSE AMPLIFIER INPUT PINS

(ISENSEH AND ISENSEL)

The ISENSEH and ISENSEL pins are the input pins of a

ground compatible differential amplifier designed to be used

to sense the voltage drop over a shunt resistor. The main

purpose of this amplifier is to implement accurate current

sensors. The gain of the differential amplifier can be set by

SPI.

LOW SIDE PINS (LS1 AND LS2)

LS1 and LS2 are the low side driver outputs. Those

outputs are short-circuit protected and include active clamp

circuitry to drive inductive loads. Due to the energy clamp

voltage on this pin, it can raise above the battery level when

switched off. The switches are controlled through the SPI and

can be configured to respond to a signal applied to the

PWMIN input pin.

Both low side switches are protected against overheating.

In case of VS1 disconnection and the low sides are still

supplied by VBAT through a load, both low sides will have a

VDS voltage equal to the clamping value, as stated in the

specification.

DIGITAL/ANALOG PINS (L1, L2, L3 AND L4)

The Lx pins are multi purpose inputs. They can be used as

digital inputs, which can be sampled by reading the SPI and

used for wake-up when 33912 is in low power mode or used

as analog inputs for the analog multiplexer. When used to

sense voltage outside the module, a 33 kohm series resistor

must be used on each input.

When used as wake-up inputs L1-L4 can be configured to

operate in cyclic-sense mode. In this mode one or both of the

high side switches are configured to be periodically turned on

and sample the wake-up inputs. If a state change is detected

between two cycles a wake-up is initiated. The 33912 can

also wake-up from Stop or Sleep by a simple state change on

L1-L4.

When used as analog inputs, the voltage present on the Lx

pins is scaled down by an selectable internal voltage divider

and can be routed to the ADOUT0 output through the analog

multiplexer.

Note: If an Lx input is selected in the analog multiplexer, it

will be disabled as a digital input and remains disabled in low

power mode. No wake-up feature is available in that

condition.

When an Lx input is not selected in the analog multiplexer,

the voltage divider is disconnected from that input.

HIGH SIDE OUTPUT PINS (HS1 AND HS2)

These two high side switches are able to drive loads such

as relays or lamps. Their structures are connected to the VS2

supply pin. The pins are short-circuit protected and both

outputs are also protected against overheating.

HS1 and HS2 are controlled by SPI and can respond to a

signal applied to the PWMIN input pin.

HS1 and HS2 outputs can also be used during low-power

mode for the cyclic-sense of the wake inputs.

POWER SUPPLY PINS (VS1 AND VS2)

Those are the battery level voltage supply pins. In an

application, VS1 and VS2 pins must be protected against

reverse battery connection and negative transient voltages

with external components. These pins sustain standard

automotive voltage conditions such as a load dump at 40 V.

The high side switches (HS1 and HS2) are supplied by the

VS2 pin. All other internal blocks are supplied by the VS1 pin.

Analog Integrated Circuit Device Data

26 Freescale Semiconductor

33912

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

MC33912G5AC / MC34912G5AC

VOLTAGE SENSE PIN (VSENSE)

This input can be connected directly to the battery line. It

is protected against battery reverse connection. The voltage

present in this input is scaled down by an internal voltage

divider, and can be routed to the ADOUT0 output pin and

used by the MCU to read the battery voltage.

The ESD structure on this pin allows for excursion up to

+40 V and down to -27 V, allowing this pin to be connected

directly to the battery line. It is strongly recommended to

connect a 10 kohm resistor in series with this pin for

protection purposes.

HALL SENSOR SWITCHABLE SUPPLY PIN (HVDD)

This pin provides a switchable supply for external hall

sensors. While in Normal Mode, this current limited output

can be controlled through the SPI.

The HVDD pin needs to be connected to an external

capacitor to stabilize the regulated output voltage.

+5V MAIN REGULATOR OUTPUT PIN (VDD)

An external capacitor has to be placed on the VDD pin to

stabilize the regulated output voltage. The VDD pin is

intended to supply a microcontroller. The pin is current limited

against shorts to GND and over-temperature protected.

During Stop mode, the voltage regulator does not operate

with its full drive capabilities and the output current is limited.

During Sleep mode, the regulator output is completely shut

down.

Analog Integrated Circuit Device Data

Freescale Semiconductor 27

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912G5AC / MC34912G5AC

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

INTRODUCTION

The 33912 offers three main operating modes: Normal

(Run), Stop, and Sleep (Low Power). In Normal mode, the

device is active and is operating under normal application

conditions. The Stop and Sleep modes are low power modes

with wake-up capabilities.

In Stop mode, the voltage regulator still supplies the MCU

with VDD (limited current capability), while in Sleep mode the

voltage regulator is turned off (VDD = 0 V).

Wake-up from Stop mode is initiated by a wake-up

interrupt. Wake-up from Sleep mode is done by a reset and

the voltage regulator is turned back on.

The selection of the different modes is controlled by the

MOD1:2 bits in the Mode Control Register (MCR).

Figure 14 describes how transitions are done between the

different operating modes. Table 6, 29, gives an overview of

the operating modes.

RESET MODE

The 33912 enters the Reset mode after a power up. In this

mode, the RST pin is low for 1.0 ms (typical value). After this

delay, it enters the Normal Request mode and the RST pin is

driven high.

The Reset mode is entered if a reset condition occurs (VDD

low, watchdog trigger fail, after wake-up from Sleep mode,

Normal Request mode timeout occurs).

NORMAL REQUEST MODE

This is a temporary mode automatically accessed by the

device after the Reset mode, or after a wake-up from Stop

mode.

In Normal Request mode, the VDD regulator is ON, the

RESET pin is High, and the LIN is operating in RX Only

mode.

As soon as the device enters in the Normal Request mode

an internal timer is started for 150 ms (typical value). During

these 150 ms, the MCU must configure the Timing Control

MOD2 and MOD1 bits set = 0, to enter the Normal mode. If

within the 150 ms timeout, the MCU does not command the

33912 to Normal mode, it will enter in Reset mode. If the

WDCONF pin is grounded in order to disable the watchdog

function, it goes directly in Normal mode after the Reset

mode.

NORMAL MODE

In Normal mode, all 33912 functions are active and can be

controlled by the SPI interface and the PWMIN pin.

The VDD regulator is ON and delivers its full current

capability.

If an external resistor is connected between the WDCONF

pin and the Ground, the window watchdog function will be

enabled.

The wake-up inputs (L1-L4) can be read as digital inputs

or have its voltage routed through the analog-multiplexer.

The LIN interface has slew rate and timing compatible with

the LIN protocol specification 2.0, 2.1 and SAEJ2602. The

LIN bus can transmit and receive information.

The high side and low side switches are active and have

PWM capability according to the SPI configuration.

The interrupts are generated to report failures for VSUP

over/under-voltage, thermal shutdown, or thermal shutdown

prewarning on the main regulator.

SLEEP MODE

The Sleep mode is a low power mode. From Normal

mode, the device enters into Sleep mode by sending one SPI

command through the Mode Control Register (MCR), or (VDD

low > 150 ms) with VSUV = 0. When in Reset mode, a VDD

under-voltage condition with no VSUP undervoltage (VSUV =

0) will send the device to Sleep mode. All blocks are in their

lowest power consumption condition. Only some wake-up

sources (wake-up inputs with or without cyclic sense, forced

wake-up and LIN receiver) are active. The 5.0 V regulator is

OFF. The internal low-power oscillator may be active if the IC

is configured for cyclic-sense. In this condition, one of the

high side switches is turned on periodically and the wake-up

inputs are sampled.

Wake-up from Sleep mode is similar to a power-up. The

device goes in Reset mode except that the SPI will report the

wake-up source and the BATFAIL flag is not set.

STOP MODE

The Stop mode is the second low power mode, but in this

case the 5.0 V regulator is ON with limited current drive

capability. The application MCU is always supplied while the

33912 is operating in Stop mode.

The device can enter into Stop mode only by sending the

SPI command. When the application is in this mode, it can

wake-up from the 33912 side (for example: cyclic sense,

force wake-up, LIN bus, wake inputs) or the MCU side (CS,

RST pins). Wake-up from Stop mode will transition the 33912

to Normal Request mode and generates an interrupt except

if the wake-up event is a low to high transition on the CS pin

or comes from the RST pin.

Analog Integrated Circuit Device Data

28 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912G5AC / MC34912G5AC

Figure 14. Operating Modes and Transitions

Reset

Power

Down

Notes:

WD - means Watchdog

WD disabled - means Watchdog disabled (WDCONF terminal connected to GND)

WD trigger – means Watchdog is triggered by SPI command

WD failed – means no Watchdog trigger or trigger occurs in closed window

STOP Command - means STOP command sent via SPI

SLEEP Command - means SLEEP command send via SPI

Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge

Normal

Request

VDD High and Reset Delay (tRST) expired

Normal

Normal Request timeout expired (NRTOUT)

WD trigger

Sleep

Wake-Up (Reset) Stop

VDD Low

VDD Low (>NRTOUT) expired

and VSUV = 0 SLEEP Command

VDD Low

STOP Command

Wake-Up Interrupt

WD disabled

VDD Low

WD failed

Normal Request Timeout Expired (t

NRTOUT

)

High and

Reset Delay (t

RST

) Expired

Low

WD Failed

LOW (>t

NRTOUT

) Expired

and VSUV = 0 Sleep Command

Stop Command

Wake-up (Reset)

WD Trigger

WD Disabled

Power Up

Wake-up (Interrupt)

Legend

WD: Watchdog

WD Disabled: Watchdog disabled (WDCONF pin connected to GND)

WD Trigger: Watchdog is triggered by SPI command

WD Failed: No watchdog trigger or trigger occurs in closed window

Stop Command: Stop command sent via SPI

Sleep Command: Sleep command sent via SPI

Wake-up from Stop Mode: L1, L2, L3 or L4 state change, LIN bus wake-up, Periodic wake-up,

rising edge wake-up or RST wake-up.

Low

Wake-up from Sleep Mode: L1, L2, L3 or L4 state change, LIN bus wake-up, Periodic wake-up.

Analog Integrated Circuit Device Data

Freescale Semiconductor 29

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912G5AC / MC34912G5AC

INTERRUPTS

Interrupts are used to signal a microcontroller that a

peripheral needs to be serviced. The interrupts which can be

generated, change according to the operating mode. While in

Normal and Normal Request modes, the 33912 signals

through interrupts special conditions which may require a

MCU software action. Interrupts are not generated until all

pending wake-up sources are read in the Interrupt Source

While in Stop mode, interrupts are used to signal wake-up

events. Sleep mode does not use interrupts. Wake-up is

performed by powering-up the MCU. In Normal and Normal

Request mode the wake-up source can be read by SPI.

The interrupts are signaled to the MCU by a low logic level

of the IRQ pin, which will remain low until the interrupt is

acknowledged by a SPI read command of the ISR register.

The IRQ pin will then be driven high.

Interrupts are only asserted while in Normal, Normal

Request and Stop mode. Interrupts are not generated while

the RST pin is low.

The following is a list of the interrupt sources in Normal and

Normal Request modes. Some of these can be masked by

writing to the SPI - Interrupt Mask Register (IMR).

Low-voltage Interrupt:

Signals when the supply line (VS1) voltage drops below

the VSUV threshold (VSUV).

High-voltage Interrupt:

Signals when the supply line (VS1) voltage increases

above the VSOV threshold (VSOV).

Over-temperature Prewarning:

Signals when the 33912 temperature has reached the pre-

shutdown warning threshold. It is used to warn the MCU that

an over-temperature shutdown in the main 5.0 V regulator is

imminent.

LIN Over-temperature Shutdown / TXD Stuck At

Dominant / RXD Short-circuit:

These signal fault conditions within the LIN interface will

cause the LIN driver to be disabled. In order to restart the

operation, the fault must be removed and TXD must go

recessive.

High Side Over-temperature Shutdown:

Signals a shutdown in the high side outputs.

Low Side Over-temperature Shutdown:

Signals a shutdown in the low side outputs.

Table 6. Operating Modes Overview

Function Reset Mode Normal Request Mode Normal

Mode Stop Mode Sleep Mode

VDD Full Full Full Stop -

HVDD -SPI(63) SPI - -

LSx -SPI/PWM(64) SPI/PWM - -

HSx -SPI/PWM(64) SPI/PWM Note(65) Note(66)

Analog Mux -SPI SPI - -

Lx -Inputs Inputs Wake-up Wake-up

Current Sense On On On - -

LIN -Rx-Only Full/Rx-Only Rx-Only/Wake-up Wake-up

Watchdog -150 ms (typ.) timeout On(67)/Off - -

Voltage

Monitoring

VSUP/VDD VSUP/VDD VSUP/VDD VDD -

Notes

63. Operation can be enabled/controlled by the SPI.

64. Operation can be controlled by the PWMIN input.

65. HSx switches can be configured for cyclic sense operation in Stop mode.

66. HSx switches can be configured for cyclic sense operation in Sleep mode.

67. Windowing operation when enabled by an external resistor.

Analog Integrated Circuit Device Data

30 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912G5AC / MC34912G5AC

RESET

To reset a MCU the 33912 drives the RST pin low for the

time the reset condition lasts.

After the reset source is removed, the state machine will

drive the RST output low for at least 1.0ms (typical value)

before driving it high.

In the 33912, four main reset sources exist:

5.0 V Regulator Low-voltage-Reset (VRSTTH)

The 5.0 V regulator output VDD is continuously monitored

against brown outs. If the supply monitor detects that the

voltage at the VDD pin has dropped below the reset threshold

VRSTTH the 33912 will issue a reset. In case of over-

temperature, the voltage regulator will be disabled and the

voltage monitoring will issue a VDDOT Flag independently of

the VDD voltage.

Window Watchdog Overflow

If the watchdog counter is not properly serviced while its

window is open, the 33912 will detect an MCU software run-

away and will reset the microcontroller.

Wake-up From Sleep Mode

During Sleep mode, the 5V regulator is not active, hence

all wake-up requests from Sleep mode require a power-up/

reset sequence.

External Reset

The 33912 has a bidirectional reset pin which drives the

device to a safe state (same as Reset mode) for as long as

this pin is held low. The RST pin must be held low long

enough to pass the internal glitch filter and get recognized by

the internal reset circuit. This functionality is also active in

Stop mode.

After the RST pin is released, there is no extra t

RST to be

considered.

WAKE-UP CAPABILITIES

Once entered into one of the low-power modes (Sleep or

Stop) only wake-up sources can bring the device into Normal

mode operation.

In Stop mode, a wake-up is signaled to the MCU as an

interrupt, while in Sleep mode the wake-up is performed by

activating the 5.0 V regulator and resetting the MCU. In both

cases the MCU can detect the wake-up source by accessing

the SPI registers and reading the Interrupt Source Register.

There is no specific SPI register bit to signal a CS wake-up or

external reset. If necessary this condition is detected by

excluding all other possible wake-up sources.

Wake-up from Wake-up inputs (L1-L4) with cyclic sense

disabled

The wake-up lines are dedicated to sense state changes

of external switches and wake-up the MCU (in Sleep or Stop

mode).

In order to select and activate direct wake-up from Lx

inputs, the Wake-up Control Register (WUCR) must be

configured with appropriate LxWE inputs enabled or

disabled. The wake-up input’s state is read through the

Wake-up Status Register (WUSR).

Lx inputs are also used to perform cyclic-sense wake-up.

Note: Selecting an Lx input in the analog multiplexer

before entering low power mode will disable the wake-up

capability of the Lx input

Wake-up from Wake-up inputs (L1-L4) with cyclic sense

timer enabled

The SBCLIN can wake-up at the end of a cyclic sense

period if on one of the four wake-up input lines (L1-L4) a state

change occurs. One or both HSx switch can be activated in

Sleep or Stop modes from an internal timer. Cyclic sense and

force wake-up are exclusive. If cyclic sense is enabled, the

force wake-up can not be enabled.

In order to select and activate the cyclic sense wake-up

from Lx inputs, before entering in low power modes (Stop or

Sleep modes), the following SPI set-up has to be performed:

In WUCR: select the Lx input to WU-enable.

In HSCR: enable the desired HSx.

• In TIMCR: select the CS/WD bit and determine the

cyclic sense period with CYSTx bits.

• Perform Goto Sleep/Stop command.

Forced Wake-up

The 33912 can wake-up automatically after a

predetermined time spent in Sleep or Stop mode. Cyclic

sense and Forced wake-up are exclusive. If Forced wake-up

is enabled, the Cyclic Sense can not be enabled.

To determine the wake-up period, the following SPI set-up

has to be sent before entering in low power modes:

• In TIMCR: select the CS/WD bit and determine the low

power mode period with CYSTx bits.

• In HSCR: all HSx bits must be disabled.

CS Wake-up

While in Stop mode, a rising edge on the CS will cause a

wake-up. The CS wake-up does not generate an interrupt,

and is not reported on SPI.

LIN Wake-up

While in the low-power mode, the 33912 monitors the

activity on the LIN bus. A dominant pulse larger than t PROPWL

followed by a dominant to recessive transition will cause a

LIN wake-up. This behavior protects the system from a short

to ground bus condition. The bit RXONLY = 1 from LINCR

Analog Integrated Circuit Device Data

Freescale Semiconductor 31

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912G5AC / MC34912G5AC

RST Wake-up

While in Stop mode, the 33912 can wake-up when the

RST pin is held low long enough to pass the internal glitch

filter. Then, the 33912 will change to Normal Request or

Normal modes depending on the WDCONF pin

configuration. The RST wake-up does not generate an

interrupt and is not reported via SPI.

From Stop mode, the following wake-up events can be

configured:

• Wake-up from Lx inputs without cyclic sense

• Cyclic sense wake-up inputs

• Force wake-up

•CS wake-up

• LIN wake-up

•RST wake-up

From Sleep mode, the following wake-up events can be

configured:

• Wake-up from Lx inputs without cyclic sense

• Cyclic sense wake-up inputs

• Force wake-up

• LIN wake-up

WINDOW WATCHDOG

The 33912 includes a configurable window watchdog

which is active in Normal mode. The watchdog can be

configured by an external resistor connected to the WDCONF

pin. The resistor is used to achieve higher precision in the

timebase used for the watchdog.

SPI clears are performed by writing through the SPI in the

MOD bits of the Mode Control Register (MCR).

During the first half of the SPI timeout, watchdog clears are

not allowed, but after the first half of the SPI timeout window,

the clear operation opens. If a clear operation is performed

outside the window, the 33912 will reset the MCU, in the

same way as when the watchdog overflows.

Figure 15. Window Watchdog Operation

To disable the watchdog function in Normal mode the user

must connect the WDCONF pin to ground. This measure

effectively disables Normal Request mode. The WDOFF bit

in the Watchdog Status Register (WDSR) will be set. This

condition is only detected during Reset mode.

If neither a resistor nor a connection to ground is detected,

the watchdog falls back to the internal lower precision

timebase of 150 ms (typ.) and signals the faulty condition

through the Watchdog Status Register (WDSR).

The watchdog timebase can be further divided by a

prescaler which can be configured by the Timing Control

window watchdog is not active but there is a 150 ms (typ.)

timeout for leaving the Normal Request mode. In case of a

timeout, the 33912 will enter into Reset mode, resetting the

microcontroller before entering again into Normal Request

mode.

FAULTS DETECTION MANAGEMENT

The 33912 has the capability to detect faults like an over

or under-voltage on VS1, TxD in permanent Dominant State,

Over-temperature on HS, LIN. It is able to take corrective

actions accordingly. Most of faults are monitoring through

SPI and the Interrupt pin. The microcontroller can also take

actions.

The following table summarizes all fault sources the

device is able to detect with associated conditions. The status

for a device recovery and the SPI or pins monitoring are also

described.

WD PERIOD (tPWD)

WINDOW CLOSED

NO WATCHDOG CLEAR

ALLOWED

WINDOW OPEN

FOR WATCHDOG

CLEAR

WD TIMING X 50% WD TIMING X 50%

WD TIMING SELECTED BY RESISTOR

ON WDCONF PIN

Analog Integrated Circuit Device Data

32 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912G5AC / MC34912G5AC

Table 7. Fault Detection Management Conditions

BLOCK FAULT MODE CONDITION FALLOUT RECOVERY

MONITORING(69)

REG (FLAG,

BIT) INTERRUPT

Power Supply

BATTERY FAIL All modes VSUP<3.0 V (typ)

then power-up -Condition gone VSR (BATFAIL, 0) -

VSUP OVER-

VOLTAGE Normal, Normal

Request

VSUP > 19.25 V (typ)

In Normal mode, HS

and LS shutdown if

bit HVSE=1 (reg

MCR)

Condition gone, to

re-enable HS or LS

write to HSCR or

LSCR registers

VSR (VSOV,3)

IRQ low +

ISR (0101)

(70)

VSUP UNDER-

VOLTAGE VSUP < 6.0 V (typ) -

Condition gone

VSR (VSUV,2) IRQ low + ISR

(0101)

VDD UNDER-

VOLTAGE All except Sleep VDD < 4.5 V (typ) Reset (68) - -

VDD OVER-TEMP

PREWARNING All except Low

Power modes

Temperature >

115°C (typ) -VSR (VDDOT,1) IRQ low + ISR

(0101)

VDD OVER-

TEMPERATURE

Temperature >

170°C (typ)

VDD shutdown,

Reset then Sleep - -

LIN

RXD PIN SHORT

CIRCUIT

Normal, Normal

Request

RXD pin shorted to

GND or 5 V LIN trans shutdown

LIN transmitter re-

enabled once the

condition is gone and

TXD is high

LINSR,

(RXSHORT,3)

IRQ low + ISR

(0100)(70)

TXD PIN

PERMANENT

DOMINANT

TXD pin low for more

than 1s (typ) LIN transmitter

shutdown

LINSR (TXDOM,2)

LIN DRIVER OVER-

TEMPERATURE

Temperature >

160°C (typ) LINSR (LINOT,1)

High Side

HIGH SIDE DRIVERS

OVER-

TEMPERATURE

Normal, Normal

Request

Temperature >

160°C (typ)

Both HS thermal

shutdown

Condition gone, to

re-enable HS write to

HSCR reg

All flags in HSSR

are set

IRQ low + ISR

(0010) (70)

HS1 OPEN-LOAD

DETECTION Current through HSx

< 5.0 mA (typ) -

Condition gone

HSSR (HS1OP,1)

HS2 OPEN-LOAD

DETECTION HSSR (HS2OP,3)

HS1 OVER-

CURRENT Current through HSx

tends to rise above

the current limit

60 mA (min)

HSx on with limited

current capability

60 mA (min)

HSSR (HS1CL,0)

HS2 OVER-

CURRENT HSSR (HS2CL,2)

Low Side

LOW SIDE DRIVERS

OVER-

TEMPERATURE

Normal, Normal

Request

Temperature >

160°C (typ)

Both LS thermal

shutdown

Condition gone, to

re-enable LS write to

LSCR reg

All flags in LSSR are

set

IRQ low + ISR

(0011) (70)

LS1 OPEN-LOAD Current through LSx

< 7.5mA (typ) -

LSSR (LS1OP,1)

LS2 OPEN-LOAD LSSR (LS2OP,3)

LS1 OVER-CURRENT Current through LSx

tends to rise above

the current limit

160 mA (min)

LSx on with limited

current capability

160 mA (min)

LSSR (LS1CL,0)

LS2 OVER-CURRENT LSSR (LS2CL,2)

Watchdog

NORMAL REQUEST

TIME-OUT EXPIRED Normal Request

The MCU did not

command the device

to Normal mode

within the 150 ms

timeout after reset

Reset

WATCHDOG

TIMEOUT Normal

WD timeout or WD

clear within the

window closed

Reset WDSR (WDTO, 3)

WATCHDOG ERROR Normal WDCONF pin is

floating

WD internal lower

precision timebase

150 ms (typ)

Connect WDCONF

to a resistor or to

GND

WDSR (WDERR, 2)

Notes

68. When in Reset mode a VDD under-voltage condition combined with no VSUP under-voltage (VSUV=0) will send the device to Sleep mode.

69. Registers to be read when back in Normal Request or Normal mode depending on the fault. Interrupts only generated in Normal, Normal Request and Stop modes

70. Unless masked, If masked IRQ remains high and the ISR flags are not set.

Analog Integrated Circuit Device Data

Freescale Semiconductor 33

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912G5AC / MC34912G5AC

TEMPERATURE SENSE GAIN

The analog multiplexer can be configured via SPI to allow

the ADOUT0 pin to deliver the internal junction temperature

of the device.

The graph below illustrates the internal chip temp sense

obtained per characterization at 3 temperatures with 3

different lots and 30 samples.

Figure 16. Temperature Sense Gain

HIGH SIDE OUTPUT PINS HS1 AND HS2

These outputs are two high side drivers intended to drive

small resistive loads or LEDs incorporating the following

features:

• PWM capability (software maskable)

• Open load detection

• Current limitation

• Over-temperature shutdown (with maskable interrupt)

• High-voltage shutdown (software maskable)

• Cyclic sense

The high side switches are controlled by the bits HS1:2 in

the High Side Control Register (HSCR).

PWM Capability (direct access)

Each high side driver offers additional (to the SPI control)

direct control via the PWMIN pin.

If both the bits HS1 and PWMHS1 are set in the High Side

Control Register (HSCR), then the HS1 driver is turned on if

the PWMIN pin is high and turned of if the PWMIN pin is low.

This applies to HS2 configuring HS2 and PWMHS2 bits.

Temperature Sense Analog Output Voltage

2.5

3.5

4.5

-50 0 50 100 150

Temperature (°C)

Vadout0 (V)

Analog Integrated Circuit Device Data

34 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912G5AC / MC34912G5AC

Figure 17. High Side Drivers HS1 and HS2

Open Load Detection

Each high side driver signals an open load condition if the

current through the high side is below the open load current

threshold.

The open load condition is indicated with the bits HS1OP

and HS2OP in the High Side Status Register (HSSR).

Current Limitation

Each high side driver has an output current limitation. In

combination with the over-temperature shutdown the high-

side drivers are protected against over-current and short-

circuit failures.

When the driver operates in the current limitation area, it is

indicated with the bits HS1CL and HS2CL in the HSSR.

Note: If the driver is operating in current limitation mode,

excessive power might be dissipated.

Over-temperature Protection (HS Interrupt)

Both high side drivers are protected against over-

temperature. In case of an over-temperature condition both

high side drivers are shut down and the event is latched in the

Interrupt Control Module. The shutdown is indicated as HS

Interrupt in the Interrupt Source Register (ISR).

A thermal shutdown of the high side drivers is indicated by

setting all HSxOP and HSxCL bits simultaneously.

If the bit HSM is set in the Interrupt Mask Register (IMR),

then an interrupt (IRQ) is generated.

A write to the High Side Control Register (HSCR), when

the over-temperature condition is gone, will re-enable the

high side drivers.

High-voltage Shutdown

In case of a high voltage condition and if the high voltage

shutdown is enabled (bit HVSE in the Mode Control Register

(MCR) is set both high side drivers are shut down.

A write to the High Side Control Register (HSCR), when

the high voltage condition is gone, will re-enable the high side

drivers.

Sleep And Stop Mode

The high side drivers can be enabled to operate in Sleep

and Stop mode for cyclic sensing. Also see Table 6,

Operating Modes Overview.

LOW SIDE OUTPUT PINS LS1 AND LS2

These outputs are two low side drivers intended to drive

relays incorporating the following features:

• PWM capability (software maskable)

• Open load detection

• Current limitation

• Over-temperature shutdown (with maskable interrupt)

• Active clamp (for driving relays)

• High-voltage shutdown (software maskable)

The low side switches are controlled by the bit LS1:2 in the

Low Side Control Register (LSCR).

High Side Driver

charge pump

open load detection

current limitation

over-temperture shutdown (interrupt maskable)

high voltage shutdown (maskable)

Control

on/off

Status

PWMIN

VDD

PWMHSx

HSx

HVSE

HSxOP

HSxCL

MOD1:2

Interrupt

Control

Module

HSx

VS2

High Voltage Shutdown

High-Side Interrupt

VDD

Wakeup

Module

Cyclic Sense

Analog Integrated Circuit Device Data

Freescale Semiconductor 35

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912G5AC / MC34912G5AC

To protect the device against over-voltage when an

inductive load (relay) is turned off. An active clamp will re-

enable the low side FET if the voltage on the LS1 or LS2 pin

exceeds a certain level.

PWM Capability (direct access)

Each low side driver offers additional (to the SPI control)

direct control via the PWMIN pin.

If both the bits LS1 and PWMLS1 are set in the Low Side

Control Register (LSCR), then the LS1 driver is turned on if

the PWMIN pin is high and turned off if the PWMIN pin is low.

The same applies to the LS2 and PWMLS2 bits for the LS2

driver.

Figure 18. Low Side Drivers LS1 and LS2

Open Load Detection

Each low side driver signals an open load condition if the

current through the low side is below the open load current

threshold.

The open load condition is indicated with the bit LS1OP

and LS2OP in the Low Side Status Register (LSSR).

Current Limitation

Each low side driver has a current limitation. In

combination with the over-temperature shutdown the low

side drivers are protected against over-current and short-

circuit failures.

When the drivers operate in current limitation, this is

indicated with the bits LS1CL and LS2CL in the LSSR.

Note: If the drivers are operating in current limitation mode

excessive power might be dissipated.

Over-temperature Protection (LS Interrupt)

Both low side drivers are protected against over-

temperature. In case of an over-temperature condition both

low side drivers are shut down and the event is latched in the

Interrupt Control Module. The shutdown is indicated as an LS

Interrupt in the Interrupt Source Register (ISR).

If the bit LSM is set in the Interrupt Mask Register (IMR)

then an Interrupt (IRQ) is generated.

A write to the Low Side Control Register (LSCR), when the

over-temperature condition is gone, will re-enable the low

side drivers.

High-voltage Shutdown

In case of a high-voltage condition and if the high-voltage

shutdown is enabed (bit HVSE in the Mode Control Register

(MCR) is set) both low sides drivers are shut down.

A write to the Low Side Control Register (LSCR), when the

high-voltage condition is gone, will re-enable the low side

drivers.

Sleep And Stop Mode

The low side drivers are disabled in Sleep and Stop mode.

Also see Table 6, Operating Modes Overview.

LIN PHYSICAL LAYER

The LIN bus pin provides a physical layer for single-wire

communication in automotive applications. The LIN physical

layer is designed to meet the LIN physical layer specification

and has the following features:

• LIN physical layer 2.0, 2.1 and SAEJ2602 compliant

• Slew rate selection

• Over-temperature shutdown

• Advanced diagnostics

The LIN driver is a low side MOSFET with thermal

shutdown. An internal pull-up resistor with a serial diode

structure is integrated, so no external pull-up components are

required for the application in a slave node. The fall time from

dominant to recessive and the rise time from recessive to

dominant is controlled. The symmetry between both slopes is

guaranteed.

LSx

Low Side Driver

(active clamp)

Open-load Detection

Current Limitation

Over-temperture Shutdown (interrupt maskable)

High-voltage shutdown (maskable)

PGND

active

clamp

Interrupt

Control

Module

HVSE

Control

on/off

Status

LSx

LSxOP

LSxCL

MOD1:2

High-voltage Shutdown

Low Side Interrupt

PWMIN

VDD

PWMLSx

VDD

Analog Integrated Circuit Device Data

36 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912G5AC / MC34912G5AC

LIN Pin

The LIN pin offers a high susceptibility immunity level from

external disturbance, guaranteeing communication during

external disturbance.

Figure 19. LIN Interface

Slew Rate Selection

The slew rate can be selected for optimized operation at

10.4 and 20 kBit/s as well as a fast baud rate for test and

programming. The slew rate can be adapted with the bits

LSR1:0 in the LIN Control Register (LINCR). The initial slew

rate is optimized for 20 kBit/s.

J2602 Conformance

To be compliant with the SAE J2602-2 specification, the

J2602 feature has to be enabled in the LINCR Register (bit

DIS_J2602 sets to 0). The LIN transmitter is disabled in case

of a VSUP under-voltage condition occurs and TXD is in

Recessive State: the LIN bus goes in Recessive State and

RXD goes high. The LIN transmitter is not disabled if TXD is

in Dominant State. A deglitcher on Vsup (tJ2602_DEG) is

implemented to avoid false switching.

If the (DIS_J2602) bit is set to 1, the J2602 feature is

disabled and the communication TXD-LIN-RXD works for

VSUP down to 4.6 V (typical value) and then the

communication is interrupted.

The (DIS_J2602) bit is set per default to 0.

Over-temperature Shutdown (LIN Interrupt)

The output low side FET is protected against over-

temperature conditions. In case of an over-temperature

condition, the transmitter will be shut down and the LINOT bit

in the LIN Status Register (LINSR) is set.

If the LINM bit is set in the Interrupt Mask Register (IMR),

an Interrupt IRQ will be generated.

The transmitter is automatically re-enabled once the

condition is gone and TXD is high.

RXD Short-circuit Detection (LIN Interrupt)

The LIN transceiver has a short-circuit detection for the

RXD output pin. If the device transmits and in case of a short-

RXONLY

MOD1:2

LSR0:1

J2602 LIN DRIVER

Slope and Slew Rate Control

Over-temperature Shutdown (interrupt maskable)

VS1

WAKE-UP

RXSHORT

TXDOM

LINOT

LIN

FILTER

SLOPE

CONTROL

30 K

LGND

LIN

RECEIVER

TXD

RXD

Wake-up

WAKE-UP

MODULE

Analog Integrated Circuit Device Data

Freescale Semiconductor 37

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912G5AC / MC34912G5AC

circuit condition, either 5.0 V or Ground, the RXSHORT bit in

the LIN Status Register (LINSR) is set and the transmitter is

shut down.

If the LINM bit is set in the Interrupt Mask Register (IMR),

an Interrupt IRQ will be generated.

The transmitter is automatically re-enabled once the

condition is gone (transition on RXD) and TXD is high.

A read of the LIN Status Register (LINSR) without the RXD

pin short-circuit condition will clear the bit RXSHORT.

TXD Dominant Detection (LIN Interrupt)

The LIN transceiver monitors the TXD input pin to detect a

stuck in dominant (0 V) condition. In case of a stuck condition

(TXD pin 0 V for more than 1 second (typ.)), the transmitter is

shut down and the TXDOM bit in the LIN Status Register

(LINSR) is set.

If the LINM bit is set in the IMR, an Interrupt IRQ will be

generated.

The transmitter is automatically re-enabled once TXD is

high.

A read of the LIN Status Register (LINSR) with the TXD pin

at 5.0 V will clear the bit TXDOM.

LIN Receiver Operation Only

While in Normal mode, the activation of the RXONLY bit

disables the LIN TXD driver. In case of a LIN error condition,

this bit is automatically set. If Stop mode is selected with this

bit set, the LIN wake-up functionality is disabled and the RXD

pin will reflect the state of the LIN bus.

STOP Mode And Wake-up Feature

During Stop mode operation, the transmitter of the

physical layer is disabled. The receiver is still active and able

to detect wake-up events on the LIN bus line.

A dominant level longer than TPROPWL followed by a rising

edge will generate a wake-up interrupt, and will be reported

in the Interrupt Source Register (ISR). Also see Figure 11,

page 22.

SLEEP Mode And Wake-up Feature

During Sleep mode operation, the transmitter of the

physical layer is disabled. The receiver must be active to

detect wake-up events on the LIN bus line.

A dominant level longer than TPROPWL followed by a rising

edge will generate a system wake-up (Reset), and will be

reported in the Interrupt Source Register (ISR). Also see

Figure 10, page 22.

Analog Integrated Circuit Device Data

38 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912G5AC / MC34912G5AC

LOGIC COMMANDS AND REGISTERS

33912 SPI INTERFACE AND CONFIGURATION

The serial peripheral interface creates the communication

link between a microcontroller (master) and the 33912.

The interface consists of four pins (see Figure 20):

•CS — Chip Select

•MOSI — Master-out Slave-in

•MISO — Master-in Slave-out

•SCLK— Serial Clock

A complete data transfer via the SPI consists of 1 byte.

The master sends 4 bits of address (A3:A0) + 4 bits of control

information (C3:C0) and the slave replies with 4 system

status bits (VMS,LINS,HSS,LSS) + 4 bits of status

information (S3:S0).

Figure 20. SPI Protocol

During the inactive phase of the CS (HIGH), the new data

transfer is prepared.

The falling edge of the CS indicates the start of a new data

transfer and puts the MISO in the low-impedance state and

latches the analog status data (Register read data).

With the rising edge of the SPI clock (SCLK), the data is

moved to MISO/MOSI pins. With the falling edge of the SPI

clock (SCLK), the data is sampled by the receiver.

The data transfer is only valid if exactly 8 sample clock

edges are present during the active (low) phase of CS.

The rising edge of the Chip Select CS indicates the end of

the transfer and latches the write data (MOSI) into the

state.

condition. Reset condition is the condition causing the bit to

be set to its reset value. The main reset conditions are:

- Power-On Reset (POR): the level at which the logic is

reset and BATFAIL flag sets.

- Reset mode

- Reset done by the RST pin (ext_reset)

MOSI

MISO

SCLK

A2 A1 A0 C3 C2 C1 C0A3

VMS LINS HSS LSS S3 S2 S1 S0

Read Data Latch

Rising: 33912 changes MISO/

MCU changes MOSI

Falling: 33912 samples MOSI/

MCU samples MISO

Write Data Latch

Analog Integrated Circuit Device Data

Freescale Semiconductor 39

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912G5AC / MC34912G5AC

SPI REGISTER OVERVIEW

Table 9 summarizes the SPI Register content for Control Information (C3:C0)=W and status information (S3:S0) = R.

Table 8. System Status Register

Adress(A3:A0) Register Name / Read / Write Information

BIT

7654

$0 - $F SYSSR - System Status Register R VMS LINS HSS LSS

Table 9. SPI Register Overview

Adress(A3:A0) Register Name / Read / Write Information

BIT

3 2 1 0

MCR - Mode Control Register WHVSE 0MOD2 MOD1

VSR - Voltage Status Register RVSOV VSUV VDDOT BATFAIL

$1 VSR - Voltage Status Register RVSOV VSUV VDDOT BATFAIL

WUCR - Wake-up Control Register WL4WE L3WE L2WE L1WE

WUSR - Wake-up Status Register RL4 L3 L2 L1

$3 WUSR - Wake-up Status Register RL4 L3 L2 L1

LINCR - LIN Control Register WDIS_J2602 RXONLY LSR1 LSR0

LINSR - LIN Status Register RRXSHORT TXDOM LINOT 0

$5 LINSR - LIN Status Register RRXSHORT TXDOM LINOT 0

HSCR - High Side Control Register WPWMHS2 PWMHS1 HS2 HS1

HSSR - High Side Status Register RHS2OP HS2CL HS1OP HS1CL

$7 HSSR - High Side Status Register RHS2OP HS2CL HS1OP HS1CL

LSCR - Low Side Control Register WPWMLS2 PWMLS1 LS2 LS1

LSSR - Low Side Status Register RLS2OP LS2CL LS1OP LS1CL

$9 LSSR - Low Side Status Register RLS2OP LS2CL LS1OP LS1CL

TIMCR - Timing Control Register W CS/WD

WD2 WD1 WD0

CYST2 CYST1 CYST0

WDSR - Watchdog Status Register RWDTO WDERR WDOFF WDWO

$B WDSR - Watchdog Status Register RWDTO WDERR WDOFF WDWO

$C AMUXCR - Analog Multiplexer Control Register WLXDS MX2 MX1 MX0

$D CFR - Configuration Register WHVDD CYSX8 CSAZ CSGS

IMR - Interrupt Mask Register WHSM LSM LINM VMM

ISR - Interrupt Source Register RISR3 ISR2 ISR1 ISR0

$F ISR - Interrupt Source Register RISR3 ISR2 ISR1 ISR0

Analog Integrated Circuit Device Data

40 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912G5AC / MC34912G5AC

System Status Register - SYSSR

The System Status Register (SYSSR) is always

transferred with every SPI transmission and gives a quick

system status overview. It summarizes the status of the

Voltage Monitor Status (VMS), LIN Status (LINS), High Side

Status (HSS), and the Low Side Status (LSS).

VMS - Voltage Monitor Status

This read-only bit indicates that one or more bits in the

VSR are set.

1 = Voltage Monitor bit set

0 = None

Figure 21. Voltage Monitor Status

LINS - LIN Status

This read-only bit indicates that one or more bits in the

LINSR are set.

1 = LIN Status bit set

0 = None

Figure 22. LIN Status

HSS - High Side Switch Status

This read-only bit indicates that one or more bits in the

HSSR are set.

1 = High Side Status bit set

0 = None

Figure 23. High Side Status

LSS - Low Side Switch Status

This read-only bit indicates that one or more bits in the

LSSR are set.

1 = Low Side Status bit set

0 = None

Figure 24. Low Side Status

Mode Control Register - MCR

The Mode Control Register (MCR) allows switching

between the operation modes and to configure the 33912.

Writing the MCR will return the VSR.

HVSE - High-voltage Shutdown Enable

This write-only bit enables/disables automatic shutdown of

the high side and the low side drivers during a high-voltage

VSOV condition.

1 = automatic shutdown enabled

0 = automatic shutdown disabled

Table 10. System Status Register

S7 S6 S5 S4

Read VMS LINS HSS LSS

VMS

BATFAIL

VDDOT

VSUV

VSOV

LINS

LINOT

TXDOM

RXSHORT

Table 11. Mode Control Register - $0

C3 C2 C1 C0

Write HVSE 0 MOD2 MOD1

Reset

Value 10--

Reset

Condition POR POR - -

HS2OP

HS2CL

HS1OP

HS1CL

HSS

LS2OP

LS2CL

LS1OP

LS1CL

LSS

Analog Integrated Circuit Device Data

Freescale Semiconductor 41

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912G5AC / MC34912G5AC

MOD2, MOD1 - Mode Control Bits

These write-only bits select the operating mode and allow

clearing the watchdog in accordance with Table 8 Mode

Control Bits.

Voltage Status Register - VSR

Returns the status of the several voltage monitors. This

VSOV - VSUP Over-voltage

This read-only bit indicates an over-voltage condition on

the VS1 pin.

1 = Over-voltage condition.

0 = Normal condition.

VSUV - VSUP Under-voltage

This read-only bit indicates an under-voltage condition on

the VS1 pin.

1 = Under-voltage condition.

0 = Normal condition.

VDDOT - Main Voltage Regulator Over-temperature

Warning

This read-only bit indicates that the main voltage regulator

temperature reached the Over-temperature Prewarning

Threshold.

1 = Over-temperature Prewarning

0 = Normal

BATFAIL - Battery Fail Flag.

This read-only bit is set during power-up and indicates that

the 33912 had a Power-On-Reset (POR).

Any access to the MCR or VSR will clear the BATFAIL flag.

1 = POR Reset has occurred

0 = POR Reset has not occurred

Wake-up Control Register - WUCR

This register is used to control the digital wake-up inputs.

Writing the WUCR will return the Wake-Up Status Register

(WUSR).

LxWE - Wake-up Input x Enable

This write-only bit enables/disables which Lx inputs are

enabled. In Stop and Sleep mode the LxWE bit determines

which wake inputs are active for wake-up. If one of the Lx

inputs is selected on the analog multiplexer, the

corresponding LxWE is masked to 0.

1 = Wake-up Input x enabled.

0 = Wake-up Input x disabled.

Wake-up Status Register - WUSR

This register is used to monitor the digital wake-up inputs

and is also returned when writing to the WUCR.

Lx - Wake-up input x

This read-only bit indicates the status of the corresponding

Lx input. If the Lx input is not enabled, then the according

Wake-up status will return 0.

After a wake-up from Stop or Sleep mode these bits also

allow to determine which input has caused the wake-up, by

first reading the Interrupt Status Register (ISR) and then

reading the WUSR. The source of the wake-up is only

reported on the first WUCR or WUSR access.

1 = Lx pin high, or Lx is the source of the wake-up.

0 = Lx pin low, disabled or selected as an analog input.

Table 12. Mode Control Bits

MOD2 MOD1 Description

0 0 Normal Mode

0 1 Stop Mode

1 0 Sleep Mode

1 1 Normal Mode + Watchdog Clear

Table 13. Voltage Status Register - $0/$1

S3 S2 S1 S0

Read VSOV VSUV VDDOT BATFAIL

Table 14. Wake-Up Control Register - $2

C3 C2 C1 C0

Write L4WE L3WE L2WE L1WE

Reset

Value 1111

Reset

Condition POR, Reset mode or ext_reset

Table 15. Wake-up Status Register - $2/$3

S3 S2 S1 S0

Read L4 L3 L2 L1

Analog Integrated Circuit Device Data

42 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912G5AC / MC34912G5AC

LIN Control Register - LINCR

This register controls the LIN physical interface block.

Writing the LIN Control Register (LINCR) returns the LIN

Status Register (LINSR).

* LIN failure gone: if LIN failure (over-temp, TXD/RXD short) was set,

the flag resets automatically when the failure is gone.

J2602 - LIN Dominant Voltage Select

This write-only bit controls the J2602 circuitry. If the

circuitry is enabled (bit sets to 0), the TXD-LIN-RXD

communication works down to the battery under-voltage

condition is detected. Below, the bus is in recessive state. If

the circuitry is disabled (bit sets to 1), the communication

TXD-LIN-RXD works down to 4.6 V (typical value).

0 = Enabled J2602 feature.

1 = Disabled J2602 feature.

RXONLY - LIN Receiver Operation Only

This write-only bit controls the behavior of the LIN

transmitter.

In Normal mode, the activation of the RXONLY bit disables

the LIN transmitter. In case of a LIN error condition, this bit is

automatically set.

In Stop mode this bit disables the LIN wake-up

functionality, and the RXD pin will reflect the state of the LIN

bus.

1 = only LIN receiver active (Normal mode) or LIN wake-

up disabled (Stop mode).

0 = LIN fully enabled.

LSRx - LIN Slew-Rate

This write-only bit controls the LIN driver slew-rate in

accordance with Table .

LIN Status Register - LINSR

This register returns the status of the LIN physical

interface block and is also returned when writing to the

LINCR.

RXSHORT - RXD Pin Short-circuit

This read-only bit indicates a short-circuit condition on the

RXD pin (shorted either to 5.0 V or to Ground). The short-

circuit delay must be a worst case of 8µs to be detected and

to shut down the driver. To clear this bit, it must be read after

the condition is gone (transition detected on RXD pin). The

LIN driver is automatically re-enabled once the condition is

gone and TXD is high.

1 = RXD short-circuit condition.

0 = None.

TXDOM - TXD Permanent Dominant

This read-only bit signals the detection of a TXD pin stuck

at dominant (Ground) condition and the resultant shutdown in

the LIN transmitter. This condition is detected after the TXD

pin remains in dominant state for more than 1 second (typical

value).

To clear this bit, it must be read after TXD has gone high.

The LIN driver is automatically re-enabled once TXD goes

High.

1 = TXD stuck at dominant fault detected.

0 = None.

LINOT - LIN Driver Over-temperature

This read-only bit signals that the LIN transceiver was

shutdown due to over-temperature. The transmitter is

automatically re-enabled after the over-temperature

condition is gone and TXD is high. The LINOT bit is cleared

after SPI read once the condition is gone.

1 = LIN over-temperature shutdown

0 = None

Table 16. LIN Control Register - $4

C3 C2 C1 C0

Write DIS_J2602 RXONLY LSR1 LSR0

Reset

Value 0000

Reset

Condition POR

POR, Reset

mode, ext_reset

or LIN failure

gone*

POR

Table 17. LIN Slew Rate Control

LSR1 LSR0 Description

0 0 Normal Slew Rate (up to 20 kb/s)

0 1 Slow Slew Rate (up to 10 kb/s)

1 0 Fast Slew Rate (up to 100 kb/s)

1 1 Reserved

Table 18. LIN Status Register - $4/$5

S3 S2 S1 S0

Read RXSHORT TXDOM LINOT 0

Analog Integrated Circuit Device Data

Freescale Semiconductor 43

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912G5AC / MC34912G5AC

High Side Control Register - HSCR

This register controls the operation of the high side drivers.

Writing to this register returns the High Side Status Register

(HSSR).

PWMHSx - PWM Input Control Enable.

This write-only bit enables/disables the PWMIN input pin

to control the respective high side switch. The corresponding

high side switch must be enabled (HSx bit).

1 = PWMIN input controls HSx output.

0 = HSx is controlled only by SPI.

HSx - HSx Switch Control.

This write-only bit enables/disables the corresponding

high side switch.

1 = HSx switch on.

0 = HSx switch off.

High Side Status Register - HSSR

This register returns the status of the high side switches

and is also returned when writing to the HSCR.

High Side Thermal Shutdown

A thermal shutdown of the high side drivers is indicated by

setting all HSxOP and HSxCL bits simultaneously.

HSxOP - High Side Switch Open-Load Detection

This read-only bit signals that the high side switches are

conducting current below a certain threshold indicating

possible load disconnection.

1 = HSx Open Load detected (or thermal shutdown)

0 = Normal

HSxCL - High Side Current Limitation

This read-only bit indicates that the respective high side

switch is operating in current limitation mode.

1 = HSx in current limitation (or thermal shutdown)

0 = Normal

Low Side Control Register - LSCR

This register controls the operation of the low side drivers.

Writing the Low Side Control Register (LSCR) will also return

the Low Side Status Register (LSSR).

PWMLx - PWM Input Control Enable.

This write-only bit enables/disables the PWMIN input pin

to control the respective low side switch. The corresponding

low side switch must be enabled (LSx bit).

1 = PWMIN input controls LSx.

0 = LSx is controlled only by SPI.

LSx - LSx Switch Control.

This write-only bit enables/disables the corresponding low

side switch.

1 = LSx switch on.

0 = LSx switch off.

Low Side Status Register - LSSR

This register returns the status of the low side switches

and is also returned when writing to the LSCR.

Low Side Thermal Shutdown

A thermal shutdown of the low side drivers is indicated by

setting all LSxOP and LSxCL bits simultaneously.

LSxOP - Low Side Switch Open-Load Detection

This read-only bit signals that the low side switches are

conducting current below a certain threshold indicating

possible load disconnection.

1 = LSx Open Load detected (or thermal shutdown)

0 = Normal

LSxCL - Low Side Current Limitation

This read-only bit indicates that the respective low side

switch is operating in current limitation mode.

1 = LSx in current limitation (or thermal shutdown)

0 = Normal

Table 19. High Side Control Register - $6

C3 C2 C1 C0

Write PWMHS2 PWMHS1 HS2 HS1

Reset

Value 00 0 0

Reset

Condition POR POR, Reset mode, ext_reset, HSx

over-temp or (VSOV & HVSE)

Table 20. High Side Status Register - $6/$7

S3 S2 S1 S0

Read HS2OP HS2CL HS1OP HS1CL

Table 21. Low Side Control Register - $8

C3 C2 C1 C0

Write PWMLS2 PWMLS1 LS2 LS1

Reset

Value 00 0 0

Reset

Condition POR POR, Reset mode, ext_reset, LSx

over-temp or (VSOV & HVSE)

Table 22. Low Side Status Register - $8/$9

C3 C2 C1 C0

Read LS2OP LS2CL LS1OP LS1CL

Analog Integrated Circuit Device Data

44 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912G5AC / MC34912G5AC

Timing Control Register - TIMCR

This register allows to configure the watchdog, the cyclic

sense and Forced Wake-up periods. Writing to the Timing

Control Register (TIMCR) will also return the Watchdog

Status Register (WDSR).

CS/WD - Cyclic Sense or Watchdog Prescaler Select

This write-only bit selects which prescaler is being written

to, the Cyclic Sense/Forced Wake-up prescaler or the

Watchdog prescaler.

1 = Cyclic Sense/Forced Wake-up Prescaler selected

0 = Watchdog Prescaler select

WDx - Watchdog Prescaler

This write-only bits selects the divider for the watchdog

prescaler and therefore selects the watchdog period in

accordance with Table 24. This configuration is valid only if

windowing watchdog is active.

Table 24. watchdog Prescaler

CYSTx - Cyclic Sense Period Prescaler Select

This write-only bits selects the interval for the wake-up

cyclic sensing together with the bit CYSX8 in the

Configuration Register (CFR) (see page 45).

This option is only active if one of the high side switches is

enabled when entering in Stop or Sleep mode. Otherwise, a

timed wake-up is performed after the period shown in

Table 25.

Table 25. Cyclic Sense and Force Wake up Interval

Watchdog Status Register - WDSR

This register returns the Watchdog status information and

is also returned when writing to the TIMCR.

WDTO - Watchdog Timeout

This read-only bit signals the last reset was caused by

either a watchdog timeout or by an attempt to clear the

Watchdog within the window closed.

Any access to this register or the Timing Control Register

(TIMCR) will clear the WDTO bit.

1 = Last reset caused by watchdog timeout

0 = None

Table 23. Timing Control Register - $A

C3 C2 C1 C0

Write CS/WD

WD2 WD1 WD0

CYST2 CYST1 CYST0

Reset

Value -000

Reset

Condition -POR

WD2 WD1 WD0 Prescaler Divider

0 0 0 1

0 0 1 2

0 1 0 4

0 1 1 6

1 0 0 8

101 10

110 12

111 14

CYSX8(71) CYST2 CYST1 CYST0 Interval

X 0 0 0 No cyclic sense(72)

0001 20 ms

0010 40 ms

0011 60 ms

0100 80 ms

0101 100 ms

0110 120 ms

0111 140 ms

1001 160 ms

1010 320 ms

1011 480 ms

1100 640 ms

1101 800 ms

1110 960 ms

1111 1120 ms

Notes

71. bit CYSX8 is located in Configuration Register (CFR)

72. No Cyclic Sense and no Force Wake-up available.

Table 26. Watchdog Status Register - $A/$B

S3 S2 S1 S0

Read WDTO WDERR WDOFF WDWO

Analog Integrated Circuit Device Data

Freescale Semiconductor 45

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912G5AC / MC34912G5AC

WDERR - Watchdog Error

This read-only bit signals the detection of a missing

watchdog resistor. In this condition the watchdog is using the

internal, lower precision timebase. The Windowing function is

disabled.

1 = WDCONF pin resistor missing

0 = WDCONF pin resistor not floating

WDOFF - Watchdog Off

This read-only bit signals that the watchdog pin connected

to Ground and therefore disabled. In this case watchdog

timeouts are disabled and the device automatically enters

Normal mode out of Reset. This might be necessary for

software debugging and for programming the Flash memory.

1 = Watchdog is disabled

0 = Watchdog is enabled

WDWO - Watchdog Window Open

This read-only bit signals when the watchdog window is

open for clears. The purpose of this bit is for testing. Should

be ignored in case WDERR is High.

1 = Watchdog window open

0 = Watchdog window closed

Analog Multiplexer Control Register - MUXCR

This register controls the analog multiplexer and selects

the divider ration for the Lx input divider.

LXDS - Lx Analog Input Divider Select

This write-only bit selects the resistor divider for the Lx

analog inputs. Voltage is internally clamped to VDD.

0 = Lx Analog divider: 1

1 = Lx Analog divider: 3.6 (typ.)

MXx - Analog Multiplexer Input Select

These write-only bits selects which analog input is

multiplexed to the ADOUT0 pin according to Table 28.

When disabled or when in Stop or Sleep mode, the output

buffer is not powered and the ADOUT0 output is left floating

to achieve lower current consumption.

Table 28. Analog Multiplexer Channel Select

Configuration Register - CFR

This register controls the Hall Sensor Supply enable/

disable, the cyclic sense timing multiplier, enables/disables

the Current Sense Auto-zero function and selects the gain for

the current sense amplifier.

HVDD - Hall Sensor Supply Enable

This write-only bit enables/disables the state of the hall

sensor supply.

1 = HVDD on

0 = HVDD off

CYSX8 - Cyclic Sense Timing x 8.

This write-only bit influences the cyclic sense and Forced

Wake-up period as shown in Table 25.

1 = Multiplier enabled

0 = None

CSAZ - Current Sense Auto-Zero Function Enable

This write-only bit enables/disables the circuitry to lower

the offset voltage of the current sense amplifier.

1 = Auto-zero function enabled

0 = Auto-zero function disabled

CSGS - Current Sense Amplifier Gain Select

This write-only bit selects the gain of the current sense

amplifier.

1 = 14.5 (typ.)

0 = 30 (typ.)

Table 27. Analog Multiplexer Control Register -$C

C3 C2 C1 C0

Write LXDS MX2 MX1 MX0

Reset

Value 1 000

Reset

Condition POR POR, Reset mode or ext_reset

MX2 MX1 MX0 Meaning

000 Disabled

001 Reserved

010 Die Temperature Sensor

011 VSENSE input

100 L1 input

101 L2 input

110 L3 input

111 L4 input

Table 29. Configuration Register - $D

C3 C2 C1 C0

Write HVDD CYSX8 CSAZ CSGS

Reset

Value 0000

Reset

Condition

POR, Reset

mode or

ext_reset

POR POR POR

Analog Integrated Circuit Device Data

46 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912G5AC / MC34912G5AC

Interrupt Mask Register - IMR

This register allows masking of some of the interrupt

sources. No interrupt will be generated to the MCU and no

flag will be set in the ISR register. The 5.0 V Regulator over-

temperature prewarning interrupt and under-voltage (VSUV)

interrupts can not be masked and will always cause an

interrupt.

Writing to the IMR will return the ISR.

HSM - High Side Interrupt Mask

This write-only bit enables/disables interrupts generated in

the high side block.

1 = HS Interrupts Enabled

0 = HS Interrupts Disabled

LSM - Low Side Interrupt Mask

This write-only bit enables/disables interrupts generated in

the low side block.

1 = LS Interrupts Enabled

0 = LS Interrupts Disabled

LINM - LIN Interrupts Mask

This write-only bit enables/disables interrupts generated in

the LIN block.

1 = LIN Interrupts Enabled

0 = LIN Interrupts Disabled

VMM - Voltage Monitor Interrupt Mask

This write-only bit enables/disables interrupts generated in

the Voltage Monitor block. The only maskable interrupt in the

Voltage Monitor Block is the VSUP over-voltage interrupt.

1 = Interrupts Enabled

0 = Interrupts Disabled

Interrupt Source Register - ISR

This register allows the MCU to determine the source of

the last interrupt or wake-up respectively. A read of the

high, in case there are no other pending interrupts. If there

are pending interrupts, IRQ will be driven high for 10 µs and

then be driven low again.

This register is also returned when writing to the Interrupt

Mask Register (IMR).

ISRx - Interrupt Source Register

These read-only bits indicate the interrupt source following

Table 32. If no interrupt is pending then all bits are 0.

In case more than one interrupt is pending, the interrupt

sources are handled sequentially multiplex.

Table 32. Interrupt Sources

Table 30. Interrupt Mask Register - $E

C3 C2 C1 C0

Write HSM LSM LINM VMM

Reset

Value 1111

Reset

Condition POR

Table 31. Interrupt Source Register - $E/$F

S3 S2 S1 S0

Read ISR3 ISR2 ISR1 ISR0

Interrupt Source Priority

ISR3 ISR2 ISR1 ISR0 none maskable maskable

0000 no interrupt no interrupt none

0001 Lx Wake-up from Stop and Sleep mode -highest

0010 - HS Interrupt (Over-temperature)

0011 - LS Interrupt (Over-temperature)

0100 LIN Wake-up LIN Interrupt (RXSHORT, TXDOM, LIN OT)

0101 Voltage Monitor Interrupt

(Low Voltage and VDD over-temperature)

Voltage Monitor Interrupt

(High Voltage)

0110 Forced Wake-up -lowest

Analog Integrated Circuit Device Data

Freescale Semiconductor 47

33912

TYPICAL APPLICATION

MC33912G5AC / MC34912G5AC

TYPICAL APPLICATION

The 33912 can be configured in several applications. The figure below shows the 33912 in the typical Slave Node Application.

Voltage Regulator

SPI

CONTROL

Reset

Control Module

LVR, HVR, HTR, WD,

Window

Watchdog Module

LIN Physical Layer

VS2

5V Output Module

HS1

LS2

HVDD

VSENSE

ISENSEL

Analog Input Module

Digital Input Module

LIN

RXD

ADOUT0

SCLK

MOSI

MISO

TXD

Wake Up Module

Current Sense Module

Interrupt

Control Module

LVI, HVI, HTI, OCI

Low Side Control

Module

VBAT Sense Module

Analog Multiplexer

HS2

LS1

ISENSEH

PGND

WDCONF

Chip Temp Sense Module

PWMIN

High Side Control

Module

LGND

Internal

Bus

MCU

RST

IRQ

ADOUT1

AGND

PGND

VS1

AGND

VDD

A/D

SCI

SPI

TIMER

RST

VDD

IRQ

C4 C3

C2 C1

Analog Input

LIN

Hall Sensor Supply

HB Type Relay

Motor Output

BAT

Typical Component Values:

C1 = 47 µF; C2 = C4 = 100 nF; C3 = 10 µF; C5 = 4.7 µF; C6 = 22 0pF or 68 pF

R1 = 10 kΩ; R2 = R3 = 10 kΩ; R4 = R5 = 33 kΩ; R6 = 20 Ω; R7 = 20 kΩ-

200 kΩ

Recommended Configuration of the not Connected Pins (NC):

Pin 28 = this pin is not internally connected and may be used for PCB routing

optimization.

Analog Integrated Circuit Device Data

Freescale Semiconductor 48

33912

MC33912BAC PRODUCT SPECIFICATIONS PAGES 48 TO 90

MC33912BAC / MC34912BAC

MC33912BAC PRODUCT SPECIFICATIONS

PAGES 48 TO 90

Analog Integrated Circuit Device Data

Freescale Semiconductor 49

33912

INTERNAL BLOCK DIAGRAM

MC33912BAC / MC34912BAC

INTERNAL BLOCK DIAGRAM

Figure 25. 33912 Simplified Internal Block Diagram

VOLTAGE REGULATOR

HIGH SIDE

CONTROL

MODULE

INTERRUPT

CONTROL

MODULE

LVI, HVI, HTI, OCI

RESET CONTROL

MODULE

LVR, HVR, HTR, WD

WINDOW

WATCHDOG

MODULE

SPI

CONTROL

LIN PHYSICAL

LAYER

WAKE-UP MODULE

DIGITAL INPUT MODULE

ANALOG INPUT

CHIP TEMPERATURE

SENSE MODULE

ANALOG MULTIPLEXER

MODULE

AGND

PGND

HS1

LIN

RST IRQ VS2 VS1 VDD

PWMIN

MISO

MOSI

SCLK

ADOUT0

RXD

TXD

LGND WDCONF

VS2

LOW SIDE

CONTROL

MODULE

5V OUTPUT

MODULE HVDD

HS2

VS2

BAT

SENSE MODULE

VSENSE

LS2

LS1

CURRENT SENSE MODULE

ISENSEL

ISENSEH

ADOUT1

INTERNAL BUS

Analog Integrated Circuit Device Data

50 Freescale Semiconductor

33912

PIN CONNECTIONS

MC33912BAC / MC34912BAC

PIN CONNECTIONS

Figure 26. 33912 Pin Connections

Table 33. 33912 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description on page 68.

Pin Pin Name Formal Name Definition

1RXD Receiver Output This pin is the receiver output of the LIN interface which reports the state of

the bus voltage to the MCU interface.

2TXD Transmitter Input This pin is the transmitter input of the LIN interface which controls the state of

the bus output.

3MISO SPI Output SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the

high-impedance state.

4MOSI SPI Input SPI (Serial Peripheral Interface) data input.

5SCLK SPI Clock SPI (Serial Peripheral Interface) clock Input.

6CS SPI Chip Select SPI (Serial Peripheral Interface) chip select input pin. CS is active low.

7ADOUT0 Analog Output Pin 0 Analog Multiplexer Output.

8PWMIN PWM Input High Side and Low Side Pulse Width Modulation Input.

9RST Internal Reset I/O Bidirectional Reset I/O pin - driven low when any internal reset source is

asserted. RST is active low.

10 IRQ Internal Interrupt

Output

Interrupt output pin, indicating wake-up events from Stop mode or events from

Normal and Normal request modes. IRQ is active low.

11 ADOUT1 Analog Output Pin 1 Current sense analog output.

8PWMIN

7ADOUT0

5SCLK

4MOSI

3MISO

1RXD

2TXD

6CS

17 LS2

18 PGND

20 L4

21 L3

22 L2

24 HS2

23 L1

19 LS1

25 HS1

26 VS2

28 NC

29 VSENSE

30 HVDD

32 AGND

31 VDD

27 VS1

ISENSEH

LIN

WDCONF

ADOUT1

RST

IRQ

ISENSEL

LGND

Analog Integrated Circuit Device Data

Freescale Semiconductor 51

33912

PIN CONNECTIONS

MC33912BAC / MC34912BAC

12 WDCONF Watchdog

Configuration Pin

This input pin is for configuration of the watchdog period and allows the

disabling of the watchdog.

13 LIN LIN Bus This pin represents the single-wire bus transmitter and receiver.

14 LGND LIN Ground Pin This pin is the device LIN ground connection. It is internally connected to the

PGND pin.

ISENSEL

ISENSEH Current Sense Pins Current Sense differential inputs.

LS2

LS1 Low Side Outputs Relay drivers low side outputs.

18 PGND Power Ground Pin This pin is the device low side ground connection. It is internally connected to

the LGND pin.

Wake-up Inputs These pins are the wake-up capable digital inputs(73). In addition, all Lx inputs

can be sensed analog via the analog multiplexer.

HS2

HS1 High Side Outputs High side switch outputs.

VS2

VS1 Power Supply Pin These pins are device battery level power supply pins.VS2 is supplying the

HSx drivers while VS1 supplies the remaining blocks.(74)

29 VSENSE Voltage Sense Pin Battery voltage sense input.(75)

30 HVDD Hall Sensor Supply

Output +5.0 V switchable supply output pin.(76)

31 VDD Voltage Regulator

Output +5.0 V main voltage regulator output pin.(77)

32 AGND Analog Ground Pin This pin is the device analog ground connection.

Notes

73. When used as digital input, a series 33 kΩ resistor must be used to protect against automotive transients.

74. Reverse battery protection series diodes must be used externally to protect the internal circuitry.

75. This pin can be connected directly to the battery line for voltage measurements. The pin is self protected against reverse battery

connections. It is strongly recommended to connect a 10kΩ resistor in series with this pin for protection purposes.

76. External capacitor (1.0 µF < C < 10 µF; 0.1 Ω < ESR < 5.0 Ω) required.

77. External capacitor (2.0 µF < C < 100 µF; 0.1 Ω < ESR < 10.0 Ω) required.

Table 33. 33912 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description on page 68.

Pin Pin Name Formal Name Definition

Analog Integrated Circuit Device Data

52 Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

MC33912BAC / MC34912BAC

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 34. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings Symbol Value Unit

ELECTRICAL RATINGS

Supply Voltage at VS1 and VS2

Normal Operation (DC)

Transient Conditions (load dump)

VSUP(SS)

VSUP(PK)

-0.3 to 27

-0.3 to 40

Supply Voltage at VDD VDD -0.3 to 5.5 V

Input / Output Pins Voltage(78)

CS, RST, SCLK, PWMIN, ADOUT0, ADOUT1, MOSI, MISO, TXD, RXD,

HVDD

Interrupt Pin (IRQ)(79)

VIN

VIN(IRQ)

-0.3 to VDD +0.3

-0.3 to 11

HS1 and HS2 Pin Voltage (DC) VHS - 0.3 to VSUP +0.3 V

LS1 and LS2 Pin Voltage (DC) VLS -0.3 to 45 V

L1, L2, L3 and L4 Pin Voltage

Normal Operation with a series 33 k resistor (DC)

Transient input voltage with external component (according to ISO7637-2)

(See Figure 28)

VLxDC

VLxTR

-18 to 40

±100

ISENSEH and ISENSEL Pin Voltage (DC) VISENSE -0.3 to 40 V

VSENSE Pin Voltage (DC) VVSENSE -27 to 40 V

LIN Pin Voltage

Normal Operation (DC)

Transient input voltage with external component (according to ISO7637-2)

(See Figure 27)

VBUSDC

VBUSTR

-18 to 40

-150 to 100

VDD output current IVDD Internally Limited A

ESD Voltage(80)

Human Body Model - LIN Pin

Human Body Model - all other Pins

Machine Model

Charge Device Model

Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25 and 32)

All other Pins (Pins 2-7, 10-15, 18-23, 26-31)

VESD1-1

VESD1-2

VESD2

VESD3-1

VESD3-2

± 8000

±2000

± 150

± 750

± 500

Notes

78. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device.

79. Extended voltage range for programming purpose only.

80. Testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), Machine Model (CZAP = 200 pF,

RZAP = 0 Ω) and the Charge Device Model, Robotic (CZAP = 4.0 pF).

Analog Integrated Circuit Device Data

Freescale Semiconductor 53

33912

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

MC33912BAC / MC34912BAC

THERMAL RATINGS

Operating Ambient Temperature (81)

33912

34912

-40 to 125

-40 to 85

°C

Operating Junction Temperature TJ-40 to 150 °C

Storage Temperature TSTG -55 to 150 °C

Thermal Resistance, Junction to Ambient

Natural Convection, Single Layer board (1s)(82), (83)

Natural Convection, Four Layer board (2s2p)(82), (84)

RθJA

°C/W

Thermal Resistance, Junction to Case(85) RθJC 23 °C/W

Peak Package Reflow Temperature During Reflow(86), (87) TPPRT Note 87 °C

Notes

81. The limiting factor is junction temperature; taking into account the power dissipation, thermal resistance, and heat sinking.

82. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

83. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.

84. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

85. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

86. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

87. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes

and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

Table 34. Maximum Ratings (continued)

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings Symbol Value Unit

Analog Integrated Circuit Device Data

54 Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

MC33912BAC / MC34912BAC

STATIC ELECTRICAL CHARACTERISTICS

Table 35. Static Electrical Characteristics

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

SUPPLY VOLTAGE RANGE (VS1, VS2)

Nominal Operating Voltage VSUP 5.5 –18 V

Functional Operating Voltage(88) VSUPOP – – 27 V

Load Dump VSUPLD – – 40 V

SUPPLY CURRENT RANGE (VSUP = 13.5 V)

Normal Mode (IOUT at VDD = 10 mA), LIN Recessive State(89) IRUN –4.5 10 mA

Stop mode, VDD ON with IOUT = 100 µA, LIN Recessive State(89), (90), (91)

5.5 V < VSUP < 12 V

VSUP = 13.5 V

ISTOP

–

µA

Sleep mode, VDD OFF, LIN Recessive State(89), (91)

5.5 V < VSUP < 12 V

12 V ≤ VSUP < 13.5 V

ISLEEP

–

µA

Cyclic Sense Supply Current Adder(92) ICYCLIC –10 –µA

SUPPLY UNDER/OVER-VOLTAGE DETECTIONS

Power-On Reset (BATFAIL)(93)

Threshold (measured on VS1)(92)

Hysteresis (measured on VS1)(92)

VBATFAIL

VBATFAIL_HYS

1.5

–

3.0

0.9

3.9

–

VSUP Under-voltage Detection (VSUV Flag) (Normal and Normal Request

modes, Interrupt Generated)

Threshold (measured on VS1)

Hysteresis (measured on VS1)

VSUV

VSUV_HYS

5.55

–

6.0

1.0

6.6

–

VSUP Over-voltage Detection (VSOV Flag) (Normal and Normal Request

modes, Interrupt Generated)

Threshold (measured on VS1)

Hysteresis (measured on VS1)

VSOV

VSOV_HYS

–

19.25

1.0

20.5

–

Notes

88. Device is fully functional. All features are operating.

89. Total current (IVS1 + IVS2) measured at GND pins excluding all loads, cyclic sense disabled.

90. Total IDD current (including loads) below 100 µA.

91. Stop and Sleep modes current will increase if VSUP exceeds13.5 V.

92. This parameter is guaranteed by process monitoring but not production tested.

93. The Flag is set during power up sequence. To clear the flag, a SPI read must be performed.

Analog Integrated Circuit Device Data

Freescale Semiconductor 55

33912

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

MC33912BAC / MC34912BAC

VOLTAGE REGULATOR(94) (VDD)

Normal Mode Output Voltage

1.0 mA < IVDD < 50 mA; 5.5 V < VSUP < 27 V

VDDRUN

4.75 5.00 5.25

Normal Mode Output Current Limitation IVDDRUN 60 110 200 mA

Dropout Voltage(95)

IVDD = 50 mA

VDDDROP

–0.1 0.25

Stop Mode Output Voltage

IVDD < 5.0 mA

VDDSTOP

4.75 5.0 5.25

Stop Mode Output Current Limitation IVDDSTOP 6.0 12 36 mA

Line Regulation

Normal mode, 5.5 V < VSUP < 18 V; IVDD = 10 mA

Stop mode, 5.5 V < VSUP < 18 V; IVDD = 1.0 mA

LRRUN

LRSTOP

–

5.0

Load Regulation

Normal mode, 1.0 mA < IVDD < 50 mA

Stop mode, 0.1 mA < IVDD < 5.0 mA

LDRUN

LDSTOP

–

Over-temperature Prewarning (Junction)(96)

Interrupt generated, VDDOT Bit Set

TPRE

110 125 140

°C

Over-temperature Prewarning Hysteresis(96) TPRE_HYS –10 –°C

Over-temperature Shutdown Temperature (Junction)(96) TSD 155 170 185 °C

Over-temperature Shutdown Hysteresis(96) TSD_HYS –10 –°C

HALL SENSOR SUPPLY OUTPUT(97) (HVDD)

VDD Voltage matching HVDDACC = (HVDD-VDD) / VDD * 100%

IHVDD = 15 mA

HVDDACC

-2.0 –2.0

Current Limitation IHVDD 20 30 50 mA

Dropout Voltage

IHVDD = 15 mA; IVDD = 5.0 mA

HVDDDROP

–160 300

Line Regulation

IHVDD = 5.0 mA; IVDD = 5.0 mA

LRHVDD

–25 40

Load Regulation

1.0 mA > IHVDD > 15 mA; IVDD = 5.0 mA

LDHVDD

–10 20

Notes

94. Specification with external capacitor 2.0 µF < C < 100 µF and 100 mΩ ≤ ESR ≤ 10 Ω.

95. Measured when voltage has dropped 250 mV below its nominal Value (5.0 V).

96. This parameter is guaranteed by process monitoring but not production tested.

97. Specification with external capacitor 1.0 µF < C < 10 µF and 100 mΩ ≤ ESR ≤ 10 Ω.

Table 35. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

56 Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

MC33912BAC / MC34912BAC

RST INPUT/OUTPUT PIN (RST)

VDD Low Voltage Reset Threshold VRSTTH 4.3 4.5 4.7 V

Low-state Output Voltage

IOUT = 1.5 mA; 3.5 V ≤ VSUP ≤ 27 V

VOL

0.0 –0.9

High-state Output Current (0 < VOUT < 3.5 V) IOH -150 -250 -350 µA

Pull-down Current Limitation (internally limited)

VOUT = VDD

IPD_MAX

1.5 –8.0

Low-state Input Voltage VIL -0.3 –0.3 x VDD V

High-state Input Voltage VIH 0.7 x VDD – VDD +0.3 V

MISO SPI OUTPUT PIN (MISO)

Low-state Output Voltage

IOUT = 1.5 mA

VOL

0.0 –1.0

High-state Output Voltage

IOUT = -250 µA

VOH

VDD -0.9 – VDD

Tri-state Leakage Current

0 V ≤ VMISO ≤ VDD

ITRIMISO

-10 –10

µA

SPI INPUT PINS (MOSI, SCLK, CS)

Low-state Input Voltage VIL -0.3 –0.3 x VDD V

High-state Input Voltage VIH 0.7 x VDD – VDD +0.3 V

MOSI, SCLK Input Current

0 V ≤ VIN ≤ VDD

IIN

-10 –10

µA

CS Pull-up Current

0 V < VIN < 3.5 V

IPUCS

10 20 30

µA

INTERRUPT OUTPUT PIN (IRQ)

Low-state Output Voltage

IOUT = 1.5 mA

VOL

0.0 –0.8

High-state Output Voltage

IOUT = -250 µA

VOH

VDD -0.8 – VDD

Leakage Current

VDD ≤ VOUT ≤ 10 V

VOH

– – 2.0

PULSE WIDTH MODULATION INPUT PIN (PWMIN)

Low-state Input Voltage VIL -0.3 –0.3 x VDD V

High-state Input Voltage VIH 0.7 x VDD – VDD +0.3 V

Pull-up current

0 V < VIN < 3.5 V

IPUPWMIN

10 20 30

µA

Table 35. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 57

33912

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

MC33912BAC / MC34912BAC

HIGH SIDE OUTPUTS HS1 AND HS2 PINS (HS1, HS2)

Output Drain-to-Source On Resistance

TJ = 25°C, ILOAD = 50 mA; VSUP > 9.0 V

TJ = 150°C, ILOAD = 50 mA; VSUP > 9.0 V(98)

TJ = 150°C, ILOAD = 30 mA; 5.5 V < VSUP < 9.0 V(98)

RDS(ON)

–

7.0

Output Current Limitation(99)

0 V < VOUT < VSUP - 2.0 V

ILIMHSX

60 120 250

Open Load Current Detection(100) IOLHSX –5.0 7.5 mA

Leakage Current

-0.2 V < VHSX < VS2 + 0.2 V

ILEAK

– – 10

µA

Short-circuit Detection Threshold(101)

5.5 V < VSUP < 27 V

VTHSC

VSUP -2.0 – –

Over-temperature Shutdown(102), (107) THSSD 150 165 180 °C

Over-temperature Shutdown Hysteresis(107) THSSD_HYS –10 –°C

LOW SIDE OUTPUTS LS1 AND LS2 PINS (LS1, LS2)

Output Drain-to-Source On Resistance

TJ = 25°C, ILOAD = 150 mA, VSUP > 9.0 V

TJ = 125°C, ILOAD = 150 mA, VSUP > 9.0 V

TJ = 125°C, ILOAD = 120 mA, 5.5 V < VSUP < 9.0 V

RDS(ON)

–

2.5

4.5

Output Current Limitation(103)

2.0 V < VOUT < VSUP

ILIMLSX

160 275 350

Open Load Current Detection(104) IOLLSX –8.0 12 mA

Leakage Current

-0.2 V < VOUT < VS1

ILEAK

– – 10

µA

Active Output Energy Clamp

IOUT = 150 mA

VCLAMP

VSUP +2.0 – VSUP +5.0

Short-circuit Detection Threshold(105)

5.5 V < VSUP < 27 V

VTHSC

2.0 – –

Over-temperature Shutdown(106), (107) TLSSD 150 165 180 °C

Over-temperature Shutdown Hysteresis(107) TLSSD_HYS –10 –°C

Notes

98. This parameter is production tested up to TA = 125°C and guaranteed by process monitoring up to TJ = 150°C.

99. When over-current occurs, the corresponding high side stays ON with limited current capability and the HSxCL flag is set in the HSSR.

100. When open load occurs, the flag (HSxOP) is set in the HSSR.

101. When short-circuit occurs and if HVSE flag is enabled, both HS automatic shutdown.

102. When over-temperature shutdown occurs, both high sides are turned off. All flags in HSSR are set.

103. When over-current occurs, the corresponding low side stays ON with limited current capability and the LSxCL flag is set in the LSSR.

104. When open load occurs, the flag (LSxOP) is set in the LSSR.

105. When short-circuit occurs and if HVSE Flag is enabled, both LS automatic shutdown

106. When over-temperature shutdown occurs, both low sides are turned off. All flags in LSSR are set.

107. Guaranteed by characterization but not production tested

Table 35. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

58 Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

MC33912BAC / MC34912BAC

L1, L2, L3 AND L4 INPUT PINS (L1, L2, L3, L4)

Low Detection Threshold

5.5 V < VSUP < 27 V

VTHL

2.0 2.5 3.0

High Detection Threshold

5.5 V < VSUP < 27 V

VTHH

3.0 3.5 4.0

Hysteresis

5.5 V < VSUP < 27 V

VHYS

0.5 1.0 1.5

Input Current(108)

-0.2 V < VIN < VS1

IIN

-10 –10

µA

Analog Input Impedance(109) RLXIN 800 1550 – kΩ

Analog Input Divider Ratio (RATIOLx = VLx / VADOUT0)

LXDS (Lx Divider Select) = 0

LXDS (Lx Divider Select) = 1

RATIOLX

0.95

3.42

1.0

3.6

1.05

3.78

Analog Output offset Ratio

LXDS (Lx Divider Select) = 0

LXDS (Lx Divider Select) = 1

VRATIOLx-

OFFSET -80

-22

0.0

Analog Inputs Matching

LXDS (Lx Divider Select) = 0

LXDS (Lx Divider Select) = 1

LXMATCHING

100

104

WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)

External Resistor Range REXT 20 –200 kΩ

Watchdog Period Accuracy with External Resistor (Excluding Resistor

Accuracy)(110) WDACC -15 –15 %

ANALOG MULTIPLEXER

Internal Chip Temperature Sense Gain STTOV –10.5 –mV/K

VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / VADOUT0)

5.5 V < VSUP < 27 V

RATIOVSENSE

5.0 5.25 5.5

VSENSE Output Related Offset

-40°C < TA < -20°C

OFFSETVSENSE -30

-45

–

ANALOG OUTPUTS (ADOUT0 AND ADOUT1)

Maximum Output Voltage

-5.0 mA < IO < 5.0 mA

VOUT_MAX

VDD -0.35 – VDD

Minimum Output Voltage

-5.0 mA < IO < 5.0 mA

VOUT_MIN

0.0 –0.35

Notes

108. Analog multiplexer input disconnected from Lx input pin.

109. Analog multiplexer input connected to Lx input pin.

110. Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in kΩ)

Table 35. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 59

33912

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

MC33912BAC / MC34912BAC

CURRENT SENSE AMPLIFIER (ISENSEH, ISENSEL)

Gain

CSGS (Current Sense Gain Select) = 0

CSGS (Current Sense Gain Select) = 1

14.5

Differential Input Impedance

CSGS (Current Sense Gain Select) = 0

CSGS (Current Sense Gain Select) = 1

DIFF

2.0

5.0

kΩ

Common Mode Input Impedance

CSGS (Current Sense Gain Select) = 0

CSGS (Current Sense Gain Select) = 1

–

300

kΩ

ISENSEH, ISENSEL Input Voltage Range VIN -0.2 –3.0 V

Input Offset Voltage

CSAZ (Current Sense Auto Zero) = 0

CSAZ (Current Sense Auto Zero) = 1

VIN_OFFSET

-15

-2.0

–

2.0

RXD OUTPUT PIN (LIN PHYSICAL LAYER) (RXD)

Low-state Output Voltage

IOUT = 1.5 mA

VOL

0.0 –0.8

High-state Output Voltage

IOUT = -250 µA

VOH

VDD -0.8 – VDD

TXD INPUT PIN (LIN PHYSICAL LAYER) (TXD)

Low-state Input Voltage VIL -0.3 –0.3 x VDD V

High-state Input Voltage VIH 0.7 x VDD – VDD +0.3 V

Pin Pull-up Current, 0V < VIN < 3.5V IPUIN 10 20 30 µA

Table 35. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

60 Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

MC33912BAC / MC34912BAC

LIN PHYSICAL LAYER, TRANSCEIVER (LIN)(111)

Output Current Limitation

Dominant State, VBUS = 18 V

IBUSLIM

40 120 200

Leakage Output Current to GND

Dominant State; VBUS = 0 V; VBAT = 12 V

Recessive State; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS ≥ VBAT

GND Disconnected; GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V

VBAT Disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18 V

IBUS_PAS_dom

IBUS_PAS_REC

IBUS_NO_GND

IBUS

-1.0

–

-1.0

–

1.0

100

µA

Receiver Input Voltages

Receiver Dominant State

Receiver Recessive State

Receiver Threshold Center (VTH_DOM + VTH_REC)/2

Receiver Threshold Hysteresis (VTH_REC - VTH_DOM)

VBUSDOM

VBUSREC

VBUS_CNT

VHYS

–

0.6

0.475

–

0.5

–

0.4

–

0.525

0.175

VSUP

LIN Transceiver Output Voltage

Recessive State, TXD HIGH, IOUT = 1.0 µA

Dominant State, TXD LOW, 500 Ω External Pull-up Resistor, LDVS = 0

Dominant State, TXD LOW, 500 Ω External Pull-up Resistor, LDVS = 1

VLIN_REC

VLIN_DOM_0

VLIN_DOM_1

VSUP -1.0

–

1.1

1.7

–

1.4

LIN Pull-up Resistor to VSUP RSLAVE 20 30 60 kΩ

Over-temperature Shutdown(112) TLINSD 150 165 180 °C

Over-temperature Shutdown Hysteresis TLINSD_HYS –10 –°C

Notes

111. Parameters guaranteed for 7.0 V ≤ VSUP ≤ 18 V.

112. When over-temperature shutdown occurs, the LIN bus goes in recessive state and the flag LINOT in LINSR is set.

Table 35. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 61

33912

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

MC33912BAC / MC34912BAC

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 36. Dynamic Electrical Characteristics

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

SPI INTERFACE TIMING (SEE Figure 36)

SPI Operating Frequency f

SPIOP – – 4.0 MHz

SCLK Clock Period tPSCLK 250 – N/A ns

SCLK Clock High Time(113) tWSCLKH 110 – N/A ns

SCLK Clock Low Time(113) tWSCLKL 110 – N/A ns

Falling Edge of CS to Rising Edge of SCLK(113) tLEAD 100 – N/A ns

Falling Edge of SCLK to CS Rising Edge(113) tLAG 100 – N/A ns

MOSI to Falling Edge of SCLK(113) tSISU 40 – N/A ns

Falling Edge of SCLK to MOSI(113) tSIH 40 – N/A ns

MISO Rise Time(113)

CL = 220 pF

tRSO

–40 –

MISO Fall Time(113)

CL = 220 pF

tFSO

–40 –

Time from Falling or Rising Edges of CS to:(113)

- MISO Low-impedance

- MISO High-impedance

tSOEN

tSODIS

0.0

–

Time from Rising Edge of SCLK to MISO Data Valid(113)

0.2 x VDD ≤ MISO ≥ 0.8 x VDD, CL = 100 pF

tVALID

0.0 –75

RST OUTPUT PIN

Reset Low-level Duration After VDD High (see Figure 35)t

RST 0.65 1.0 1.35 ms

Reset Deglitch Filter Time t

RSTDF 350 600 900 ns

WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)

Watchdog Time Period(114)

External Resistor REXT = 20 kΩ (1%)

External Resistor REXT = 200 kΩ (1%)

Without External Resistor REXT (WDCONF Pin Open)

t PWD

8.5

110

150

11.5

108

205

CURRENT SENSE AMPLIFIER(113)

Common Mode Rejection Ratio CMR 70 – – dB

Supply Voltage Rejection Ratio(115) SVR 60 – – dB

Gain Bandwidth Product GBP 0.75 3.0 –MHz

Output Slew-rate SR 0.5 – – V/µs

Notes

113. This parameter is guaranteed by process monitoring but not production tested.

114. Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in kΩ)

115. Analog Outputs are supplied by VDD

Analog Integrated Circuit Device Data

62 Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

MC33912BAC / MC34912BAC

L1, L2, L3 AND L4 INPUTS

Wake-up Filter Time t

WUF 8.0 20 38 μs

STATE MACHINE TIMING

Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)

and Stop mode Activation(116) t

STOP

– – 5.0

μs

Normal Request Mode Timeout (see Figure 35)t

NR TOUT 110 150 205 ms

Delay Between SPI Command and HS /LS Turn On(117)

9.0 V < VSUP < 27 V

t S-ON

– – 10

μs

Delay Between SPI Command and HS /LS Turn Off(117)

9.0 V < VSUP < 27 V

S-OFF

– – 10

μs

Delay Between Normal Request and Normal Mode After a Watchdog Trigger

Command (Normal Request Mode)(116) t

SNR2N

– – 10

μs

Delay Between CS Wake-up (CS LOW to HIGH) in Stop mode and:

Normal Request mode, VDD ON and RST HIGH

First Accepted SPI Command

WUCS

WUSPI

9.0

—

N/A

μs

Minimum Time Between Rising and Falling Edge on the CS t

2CS 4.0 — — μs

LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC(118), (119)

Duty Cycle 1: D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs

7.0 V ≤ VSUP ≤ 18 V

0.396 — —

Duty Cycle 2: D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs

7.6 V ≤ VSUP ≤ 18 V

— — 0.581

LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC(118), (120)

Duty Cycle 3: D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs

7.0 V ≤ VSUP ≤ 18 V

0.417 — —

μs

Duty Cycle 4: D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96µs

7.6 V ≤ VSUP ≤ 18 V

— — 0.590

μs

Notes

116. This parameter is guaranteed by process monitoring but not production tested.

117. Delay between turn on or off command (rising edge on CS) and HS or LS ON or OFF, excluding rise or fall time due to external load.

118. Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal

threshold defined at each parameter. See Figure 29.

119. See Figure 30.

120. See Figure 31.

Table 36. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

Freescale Semiconductor 63

33912

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

MC33912BAC / MC34912BAC

LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE

LIN Fast Slew Rate (Programming mode) SRFAST —20 — V / μs

LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS(121)

Propagation Delay and Symmetry(122)

Propagation Delay Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF)

Symmetry of Receiver Propagation Delay tREC_PDF - tREC_PDR

REC_PD

REC_SYM

—

- 2.0

3.0

—

6.0

2.0

μs

Bus Wake-up Deglitcher (Sleep and Stop modes)(123) t PROPWL 42 70 95 μs

Bus Wake-up Event Reported

From Sleep mode(124)

From Stop mode(125)

WAKE

—

9.0

—

1500

μs

TXD Permanent Dominant State Delay t TXDDOM 0.65 1.0 1.35 s

PULSE WIDTH MODULATION INPUT PIN (PWMIN)

PWMIN pin(126)

Max. frequency to drive HS and LS output pins

fPWMIN

-10 -

kHz

Notes

121. VSUP from 7.0 V to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD

signal to LIN signal threshold defined at each parameter. See Figure 29.

122. See Figure 32.

123. See Figure 33 for Sleep and Figure 34 for Stop mode.

124. The measurement is done with 1µF capacitor and 0 mA current load on VDD. The value takes into account the delay to charge the

capacitor. The delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when VDD reaches 3.0 V.

See Figure 33. The delay depends of the load and capacitor on VDD.

125. In Stop mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 34.

126. This parameter is guaranteed by process monitoring but not production tested.

Table 36. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33912 and -40°C ≤ TA ≤ 85°C for the

34912, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal

conditions, unless otherwise noted.

Characteristic Symbol Min Typ Max Unit

Analog Integrated Circuit Device Data

64 Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

MC33912BAC / MC34912BAC

TIMING DIAGRAMS

Figure 27. Test Circuit for Transient Test Pulses (LIN)

Figure 28. Test Circuit for Transient Test Pulses (Lx)

Figure 29. Test Circuit for LIN Timing Measurements

Note

Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.

LIN

TRANSIENT PULSE

PGND

GENERATOR

1.0 nF

(

NOTE

)

GND

33912

LGND AGND

L1, L2, L3, L4

Transient Pulse

PGND

Generator

1.0 nF

(Note)

10 k

Note

Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b,.

GND

33912

LGND AGND

R0 AND C0 COMBINATIONS:

• 1.0 KΩ and 1.0 nF

• 660 Ω and 6.8 nF

• 500 Ω and 10 nF

VSUP

TXD

RXD

LIN

C0C0

Analog Integrated Circuit Device Data

Freescale Semiconductor 65

33912

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

MC33912BAC / MC34912BAC

Figure 30. LIN Timing Measurements for Normal Slew Rate

Figure 31. LIN Timing Measurements for Slow Slew Rate

TXD

LIN

RXD

tBIT tBIT

tBUS_DOM (MAX) tBUS_REC (MIN)

tREC - MAX

tDOM - MIN

tRREC

tRDOM

28.4% VSUP

58.1% VSUP

40.0% VSUP

60.0% VSUP

74.4% VSUP

42.2% VSUP

40.0% VSUP

58.1% VSUP

28.4% VSUP

tBUS_DOM (MIN)

tBUS_REC (MAX)

tDOM - MAX tREC - MIN

VLIN_REC

TXD

LIN

RXD

tBIT tBIT

tBUS_DOM (MAX) tBUS_REC (MIN)

tREC - MAX

tDOM - MIN

tRREC

tRDOM

25.1% VSUP

61.6% VSUP

40.0% VSUP

60.0% VSUP

77.8% VSUP

38.9% VSUP

40.0% VSUP

61.6% VSUP

25.1% VSUP

tBUS_DOM (MIN)

tBUS_REC (MAX)

tDOM - MAX tREC - MIN

VLIN_REC

Analog Integrated Circuit Device Data

66 Freescale Semiconductor

33912

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

MC33912BAC / MC34912BAC

Figure 32. LIN Receiver Timing

Figure 33. LIN Wake-up Sleep Mode Timing

Figure 34. LIN Wake-up Stop Mode Timing

VBUSREC

VBUSDOM

VSUP

LIN BUS SIGNAL

tRX_PDR

tRX_PDF

RXD

VLIN_REC

DOMINANT LEVEL

0.4 VSUP

VLIN_REC

LIN

VDD

tPROPWL tWAKE

IRQ

LIN

Vrec

TpropWL Twake

Dominant level

0.4VSUP

Dominant Level

0.4 VSUP

VLIN_REC

tPROPWL tWAKE

Analog Integrated Circuit Device Data

Freescale Semiconductor 67

33912

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

MC33912BAC / MC34912BAC

Figure 35. Power On Reset and Normal Request Timeout Timing

Figure 36. SPI Timing Characteristics

VSUP

VDD

RST

tRST

tNRTOUT

UNDEFINED DON’T CARE D7 DON’T CARE

tLEAD

tSIH

tSISU

tLAG

tPSCLK

tWSCLKH

tWSCLKL

tVALID

DON’T CARE D7

tSODIS

SCLK

MOSI

MISO

tSOEN

Analog Integrated Circuit Device Data

68 Freescale Semiconductor

33912

FUNCTIONAL DESCRIPTION

INTRODUCTION

MC33912BAC / MC34912BAC

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33912 was designed and developed as a highly

integrated and cost-effective solution for automotive and

industrial applications. For automotive body electronics, the

33912 is well suited to perform relay control in applications

like window lift, sunroof, etc. via LIN bus.

Power switches are provided on the device configured as

high side and low side outputs. Other ports are also provided,

which include a current and voltage sense port, a Hall Sensor

port supply, and four wake-up capable pins. An internal

voltage regulator provides power to a MCU device.

Also included in this device is a LIN physical layer, which

communicates using a single wire. This enables this device

to be compatible with 3-wire bus systems, where one wire is

used for communication, one for battery, and one for ground.

FUNCTIONAL PIN DESCRIPTION

See Figure 1, 33912 Simplified Application Diagram, for a

graphic representation of the various pins referred to in the

following paragraphs. Also, see the pin diagram on page 50

for a description of the pin locations in the package.

RECEIVER OUTPUT PIN (RXD)

The RXD pin is a digital output. It is the receiver output of

the LIN interface and reports the state of the bus voltage:

RXD Low when LIN bus is dominant, RXD High when LIN bus

is recessive.

TRANSMITTER INPUT PIN (TXD)

The TXD pin is a digital input. It is the transmitter input of

the LIN interface and controls the state of the bus output

(dominant when TXD is Low, recessive when TXD is High).

This pin has an internal pull-up to force recessive state in

case the input is left floating.

LIN BUS PIN (LIN)

The LIN pin represents the single-wire bus transmitter and

receiver. It is suited for automotive bus systems and is

compliant to the LIN bus specification 2.0.

The LIN interface is only active during Normal and Normal

Request modes.

SERIAL DATA CLOCK PIN (SCLK)

The SCLK pin is the SPI clock input pin. MISO data

changes on the negative transition of the SCLK. MOSI is

sampled on the positive edge of the SCLK.

MASTER OUT SLAVE IN PIN (MOSI)

The MOSI digital pin receives SPI data from the MCU. This

data input is sampled on the positive edge of SCLK.

MASTER IN SLAVE OUT PIN (MISO)

The MISO pin sends data to an SPI-enabled MCU. It is a

digital tri-state output used to shift serial data to the

microcontroller. Data on this output pin changes on the

negative edge of the SCLK. When CS is High, this pin will

remain in high-impedance state.

CHIP SELECT PIN (CS)

CS is an active low digital input. It must remain low during

a valid SPI communication and allow for several devices to

be connected in the same SPI bus without contention. A

rising edge on CS signals the end of the transmission and the

moment the data shifted in is latched. A valid transmission

must consist of 8 bits only.

While in STOP mode, a low-to-high level transition on this

pin will generate a wake-up condition for the 33912.

ANALOG MULTIPLEXER PIN (ADOUT0)

The ADOUT0 pin can be configured via the SPI to allow

the MCU A/D converter to read the several inputs of the

Analog Multiplexer, including the VSENSE, L1, L2, L3, L4

input voltages, and the internal junction temperature.

CURRENT SENSE AMPLIFIER PIN (ADOUT1)

The ADOUT1 pin is an analog interface to the MCU A/D

converter. It allows the MCU to read the output of the current

sense amplifier.

PWM INPUT CONTROL PIN (PWMIN)

This digital input can control the high sides and low sides

drivers in Normal Request- and Normal mode.

To enable PWM control, the MCU must perform a write

operation to the High Side Control Register (HSCR) or the

Low Side Control Register (LSCR).

This pin has an internal 20 μA current pull-up.

Analog Integrated Circuit Device Data

Freescale Semiconductor 69

33912

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

MC33912BAC / MC34912BAC

RESET PIN (RST)

This bidirectional pin is used to reset the MCU in case the

33912 detects a reset condition, or to inform the 33912 that

the MCU has just been reset. After release of the RST pin,

Normal Request mode is entered.

The RST pin is an active low filtered input and output

formed by a weak pull-up and a switchable pull-down

structure which allows this pin to be shorted either to VDD or

to GND during software development, without the risk of

destroying the driver.

INTERRUPT PIN (IRQ)

The IRQ pin is a digital output used to signal events or

faults to the MCU while in Normal and Normal Request mode

or to signal a wake-up from Stop mode. This active low output

will transition to high only after the interrupt is acknowledged

by a SPI read of the respective status bits.

WATCHDOG CONFIGURATION PIN (WDCONF)

The WDCONF pin is the configuration pin for the internal

watchdog. A resistor can be connected to this pin to configure

the window watchdog period. When connected directly to

ground, the watchdog will be disabled. When this pin is left

open, the watchdog period is fixed to its lower precision

internal default value (150 ms typical).

GROUND CONNECTION PINS (AGND, PGND,

LGND)

The AGND, PGND and LGND pins are the Analog and

Power ground pins.

The AGND pin is the ground reference of the voltage

regulator and the current sense module.

The PGND and LGND pins are used for high current load

return as in the relay-drivers and LIN interface pin.

Note: PGND, AGND and LGND pins must be connected

together.

CURRENT SENSE AMPLIFIER INPUT PINS

(ISENSEH AND ISENSEL)

The ISENSEH and ISENSEL pins are the input pins of a

ground compatible differential amplifier designed to be used

to sense the voltage drop over a shunt resistor. The main

purpose of this amplifier is to implement accurate current

sensors. The gain of the differential amplifier can be set by

SPI.

LOW SIDE PINS (LS1 AND LS2)

LS1 and LS2 are the low side driver outputs. Those

outputs are short-circuit protected and include active clamp

circuitry to drive inductive loads. Due to the energy clamp

voltage on this pin, it can raise above the battery level when

switched off. The switches are controlled through the SPI and

can be configured to respond to a signal applied to the

PWMIN input pin.

Both low side switches are protected against overheating.

DIGITAL/ANALOG PINS (L1, L2, L3 AND L4)

The Lx pins are multi purpose inputs. They can be used as

digital inputs, which can be sampled by reading the SPI and

used for wake-up when 33912 is in low power mode or used

as analog inputs for the analog multiplexer. When used to

sense voltage outside the module, a 33 kohms series resistor

must be used on each input.

When used as wake-up inputs L1-L4 can be configured to

operate in cyclic-sense mode. In this mode one of the high

side switches is configured to be periodically turned on and

sample the wake-up inputs. If a state change is detected

between two cycles a wake-up is initiated. The 33912 can

also wake-up from Stop or Sleep by a simple state change on

L1-L4.

When used as analog inputs, the voltage present on the Lx

pins is scaled down by an selectable internal voltage divider

and can be routed to the ADOUT0 output through the analog

multiplexer.

Note: If an Lx input is selected in the analog multiplexer, it

will be disabled as a digital input and remains disabled in low

power mode. No wake-up feature is available in that

condition.

When an Lx input is not selected in the analog multiplexer,

the voltage divider is disconnected from that input.

HIGH SIDE OUTPUT PINS (HS1 AND HS2)

These two high side switches are able to drive loads such

as relays or lamps. Their structures are connected to the VS2

supply pin. The pins are short-circuit protected and both

outputs are also protected against overheating.

HS1 and HS2 are controlled by SPI and can respond to a

signal applied to the PWMIN input pin.

HS1 and HS2 outputs can also be used during low-power

mode for the cyclic-sense of the wake inputs.

POWER SUPPLY PINS (VS1 AND VS2)

Those are the battery level voltage supply pins. In an

application, VS1 and VS2 pins must be protected against

reverse battery connection and negative transient voltages

with external components. These pins sustain standard

automotive voltage conditions such as a load dump at 40 V.

The high side switches (HS1 and HS2) are supplied by the

VS2 pin. All other internal blocks are supplied by VS1 pin.

Analog Integrated Circuit Device Data

70 Freescale Semiconductor

33912

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

MC33912BAC / MC34912BAC

VOLTAGE SENSE PIN (VSENSE)

This input can be connected directly to the battery line. It

is protected against battery reverse connection. The voltage

present in this input is scaled down by an internal voltage

divider, and can be routed to the ADOUT0 output pin and

used by the MCU to read the battery voltage.

The ESD structure on this pin allows for excursion up to

+40 V and down to -27 V, allowing this pin to be connected

directly to the battery line. It is strongly recommended to

connect a 10 kohm resistor in series with this pin for

protection purposes.

HALL SENSOR SWITCHABLE SUPPLY PIN (HVDD)

This pin provides a switchable supply for external hall

sensors. While in Normal mode, this current limited output

can be controlled through the SPI.

The HVDD pin needs to be connected to an external

capacitor to stabilize the regulated output voltage.

+5V MAIN REGULATOR OUTPUT PIN (VDD)

An external capacitor has to be placed on the VDD pin to

stabilize the regulated output voltage. The VDD pin is

intended to supply a microcontroller. The pin is current limited

against shorts to GND and over-temperature protected.

During Stop mode, the voltage regulator does not operate

with its full drive capabilities and the output current is limited.

During Sleep mode, the regulator output is completely shut

down.

Analog Integrated Circuit Device Data

Freescale Semiconductor 71

33912

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

MC33912BAC / MC34912BAC

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

Figure 37. Functional Internal Block Diagram

ANALOG CIRCUITRY

The 33912 is designed to operate under automotive

operating conditions. A fully configurable window watchdog

circuit will reset the connected MCU in case of an overflow.

Two low power modes are available with several different

wake-up sources to reactivate the device. Four analog /

digital inputs can be sensed or used as the wake-up source.

The device is capable of sensing the supply voltage

(VSENSE), the internal chip temperature (CTEMP) as well as

the motor current using an external sense resistor.

HIGH SIDE DRIVERS

Two current and temperature protected High Side drivers

with PWM capability are provided to drive small loads such as

Status LED’s or small lamps. Both Drivers can be configured

for periodic sense during low power modes.

LOW SIDE DRIVERS

Two current and temperature protected Low Side drivers

with PWM capability are provided to drive H-Bridge type

relays for power motor applications

MCU INTERFACE

The 33912 is providing its control and status information

through a standard 8-Bit SPI interface. Critical system events

such as Low- or High-voltage/Temperature conditions as well

as over-current conditions in any of the driver stages can be

reported to the connected MCU via IRQ or RST. Both Low

Side and both High Side driver outputs can be controlled via

the SPI register as well as the PWMIN input. The integrated

LIN physical layer interface can be configured via SPI register

and its communication is driven through the RXD and TXD

device pins. All internal analog sources are multiplexed to the

ADOUT 0 pin. The current sense analog signal is directly

routed through ADOUT1.

VOLTAGE REGULATOR OUTPUTS

Two independent voltage regulators are implemented on

the 33912. The VDD main regulator output is designed to

supply a MCU with a precise 5.0 V. The switchable HVDD

output is dedicated to supply small peripherals as hall

sensors.

LIN PHYSICAL LAYER INTERFACE

The 33912 provides a LIN 2.0 compatible LIN physical

layer interface with selectable slew rate and various

diagnostic features.

MC33912 - Functional Block Diagram

Ana

og Circuitr

MCU Inter

ace and Output Control

riv

ntegrate

Supp

ide Drivers

1 - H

LIN

Phy

Int

face

Driv

1 - L

Integrated Supply

Hall Sensor Supply

HVDD

Voltage Regulator

VDD

Analog Circuitry

Digital / Analog Input

Voltage, Current & Temperature Sense

Wake-Up

Window Watchdog

MCU Interface and Output Control

PI Int

ace

- PWM

ntr

Analog Output 0/1

IN Interface / Control

eset

Analog Integrated Circuit Device Data

72 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912BAC / MC34912BAC

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

Introduction

The 33912 offers three main operating modes: Normal

(Run), Stop, and Sleep (Low Power). In Normal mode, the

device is active and is operating under normal application

conditions. The Stop and Sleep modes are low-power modes

with wake-up capabilities.

In Stop mode, the voltage regulator still supplies the MCU

with VDD (limited current capability), while in Sleep mode the

voltage regulator is turned off (VDD = 0 V).

Wake-up from Stop mode is initiated by a wake-up

interrupt. Wake-up from Sleep mode is done by a reset and

the voltage regulator is turned back on.

The selection of the different modes is controlled by the

MOD1:2 bits in the Mode Control Register (MCR).

Figure 38 describes how transitions are done between the

different operating modes. Table 37 gives an overview of the

operating modes.

RESET MODE

The 33912 enters the Reset mode after a power up. In this

mode, the RST pin is low for 1ms (typical value). After this

delay, it enters the Normal Request mode and the RST pin is

driven high.

The Reset mode is entered if a reset condition occurs (VDD

low, watchdog trigger fail, after wake-up from Sleep mode,

Normal Request mode timeout occurs).

NORMAL REQUEST MODE

This is a temporary mode automatically accessed by the

device after the Reset mode, or after a wake-up from Stop

mode.

In Normal Request mode, the VDD regulator is ON, the

RESET pin is High, and the LIN is operating in RX Only

mode.

As soon as the device enters in the Normal Request mode

an internal timer is started for 150 ms (typical value). During

these 150 ms, the MCU must configure the Timing Control

MOD2 and MOD1 bits set = 0, to enter the Normal mode. If

within the 150ms timeout, the MCU does not command the

33912 to Normal mode, it will enter in Reset mode. If the

WDCONF pin is grounded in order to disable the watchdog

function, it goes directly in Normal mode after the Reset

mode. If the WDCONF pin is open, the 33912 stays typically

for 150 ms in Normal Request before entering in Normal

mode.

NORMAL MODE

In Normal mode, all 33912 functions are active and can be

controlled by the SPI interface and the PWMIN pin.

The VDD regulator is ON and delivers its full current

capability.

If an external resistor is connected between the WDCONF

pin and the Ground, the window watchdog function will be

enabled.

The wake-up inputs (L1-L4) can be read as digital inputs

or have its voltage routed through the analog-multiplexer.

The LIN interface has slew rate and timing compatible with

the LIN protocol specification 2.0. The LIN bus can transmit

and receive information.

The high side and low side switches are active and have

PWM capability according to the SPI configuration.

The interrupts are generated to report failures for VSUP

over/under-voltage, thermal shutdown, or thermal shutdown

prewarning on the main regulator.

SLEEP MODE

The Sleep mode is a low power mode. From Normal

mode, the device enters into Sleep mode by sending one SPI

command through the Mode Control Register (MCR). All

blocks are in their lowest power consumption condition. Only

some wake-up sources (wake-up inputs with or without cyclic

sense, forced wake-up and LIN receiver) are active. The

5.0 V regulator is OFF. The internal low-power oscillator may

be active if the IC is configured for cyclic-sense. In this

condition, one of the high side switches is turned on

periodically and the wake-up inputs are sampled.

Wake-up from Sleep mode is similar to a power-up. The

device goes in Reset mode except that the SPI will report the

wake-up source and the BATFAIL flag is not set.

STOP MODE

The Stop mode is the second low power mode, but in this

case the 5.0 V regulator is ON with limited current drive

capability. The application MCU is always supplied while the

33912 is operating in Stop mode.

The device can enter into Stop mode only by sending the

SPI command. When the application is in this mode, it can

wake-up from the 33912 side (for example: cyclic sense,

force wake-up, LIN bus, wake inputs) or the MCU side (CS,

RST pins). Wake-up from Stop mode will transition the 33912

to Normal Request mode and generates an interrupt except

if the wake-up event is a low to high transition on the CS pin

or comes from the RST pin.

Analog Integrated Circuit Device Data

Freescale Semiconductor 73

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912BAC / MC34912BAC

Figure 38. Operating Modes and Transitions

Reset

Power

Down

Notes:

WD - means Watchdog

WD disabled - means Watchdog disabled (WDCONF terminal connected to GND)

WD trigger – means Watchdog is triggered by SPI command

WD failed – means no Watchdog trigger or trigger occurs in closed window

STOP Command - means STOP command sent via SPI

SLEEP Command - means SLEEP command send via SPI

Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge

Normal

Request

VDD High and Reset Delay (tRST) expired

Normal

Normal Request timeout expired (NRTOUT)

WD trigger

Sleep

Wake-Up (Reset) Stop

VDD Low

VDD Low (>NRTOUT) expired

and VSUV = 0 SLEEP Command

VDD Low

STOP Command

Wake-Up Interrupt

WD disabled

VDD Low

WD failed

Normal Request Timeout Expired (t

NRTOUT

)

High and

Reset Delay (t

RST

) Expired

Low

WD Failed

LOW (>t

NRTOUT

) Expired

and VSUV = 0 Sleep Command

Stop Command

Wake-up (Reset)

WD Trigger

WD Disabled

Power Up

Wake-Up (Interrupt)

Legend

WD: Watchdog

WD Disabled: Watchdog disabled (WDCONF pin connected to GND)

WD Trigger: Watchdog is triggered by SPI command

WD Failed: No watchdog trigger or trigger occurs in closed window

Stop Command: Stop command sent via SPI

Sleep Command: Sleep command sent via SPI

Wake-Up from Stop Mode: L1, L2, L3 or L4 state change, LIN bus wake-up, Periodic wake-up,

rising edge wake-up or RST wake-up.

Low

Wake-Up from Sleep Mode: L1, L2, L3 or L4 state change, LIN bus wake-up, Periodic wake-up.

Analog Integrated Circuit Device Data

74 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912BAC / MC34912BAC

INTERRUPTS

Interrupts are used to signal a microcontroller that a

peripheral needs to be serviced. The interrupts which can be

generated, change according to the operating mode. While in

Normal and Normal Request modes, the 33912 signals

through interrupts special conditions which may require a

MCU software action. Interrupts are not generated until all

pending wake-up sources are read in the Interrupt Source

While in Stop mode, interrupts are used to signal wake-up

events. Sleep mode does not use interrupts. Wake-up is

performed by powering-up the MCU. In Normal and Normal

Request mode the wake-up source can be read by SPI.

The interrupts are signaled to the MCU by a low logic level

of the IRQ pin, which will remain low until the interrupt is

acknowledged by a SPI read. The IRQ pin will then be driven

high.

Interrupts are only asserted while in Normal, Normal

Request and Stop mode. Interrupts are not generated while

the RST pin is low.

The following is a list of the interrupt sources in Normal and

Normal Request modes. Some of these can be masked by

writing to the SPI - Interrupt Mask Register (IMR).

Low-voltage Interrupt:

Signals when the supply line (VS1) voltage drops below

the VSUV threshold (VSUV).

High-voltage Interrupt:

Signals when the supply line (VS1) voltage increases

above the VSOV threshold (VSOV).

Over-temperature Prewarning:

Signals when the 33912 temperature has reached the pre-

shutdown warning threshold. It is used to warn the MCU that

an over-temperature shutdown in the main 5.0 V regulator is

imminent.

LIN Over-current Shutdown / Over-temperature

Shutdown / TXD Stuck At Dominant / RXD Short-circuit:

These signal fault conditions within the LIN interface will

cause the LIN driver to be disabled, except for the LIN over-

current condition. In order to restart operation, the fault must

be removed and must be acknowledged by reading the SPI.

The LINOC bit functionality in the LIN Status Register

(LINSR) is to indicate an LIN over-current has occurred and

the driver remains enabled.

High Side Over-temperature Shutdown:

Signals a shutdown in the high side outputs.

Low Side Over-temperature Shutdown:

Signals a shutdown in the low side outputs.

RESET

To reset a MCU the 33912 drives the RST pin low for the

time the reset condition lasts.

Table 37. Operating Modes Overview

Function Reset Mode Normal Request Mode Normal

Mode Stop Mode Sleep Mode

VDD Full Full Full Stop -

HVDD -SPI(127) SPI - -

LSx -SPI/PWM(128) SPI/PWM - -

HSx -SPI/PWM(128) SPI/PWM Note(129) Note(130)

Analog Mux -SPI SPI - -

Lx -Inputs Inputs Wake-up Wake-up

Current Sense On On On - -

LIN -Rx-Only Full/Rx-Only Rx-Only/Wake-up Wake-up

Watchdog -150 ms (typ.) timeout On(131)/Off - -

VSENSE On On On VDD -

Notes

127. Operation can be enabled/controlled by the SPI.

128. Operation can be controlled by the PWMIN input.

129. HSx switches can be configured for cyclic sense operation in Stop mode.

130. HSx switches can be configured for cyclic sense operation in Sleep mode.

131. Windowing operation when enabled by an external resistor.

Analog Integrated Circuit Device Data

Freescale Semiconductor 75

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912BAC / MC34912BAC

After the reset source is removed, the state machine will

drive the RST output low for at least 1.0 ms (typical value)

before driving it high.

In the 33912, four main reset sources exist:

5.0 V Regulator Low-voltage-Reset (VRSTTH)

The 5.0 V regulator output VDD is continuously monitored

against brown outs. If the supply monitor detects that the

voltage at the VDD pin has dropped below the reset threshold

VRSTTH the 33912 will issue a reset. In case of over-

temperature, the voltage regulator will be disabled and the

voltage monitoring will issue a VDDOT Flag independently of

the VDD voltage.

Window Watchdog Overflow

If the watchdog counter is not properly serviced while its

window is open, the 33912 will detect an MCU software run-

away and will reset the microcontroller.

Wake-up From Sleep Mode

During Sleep mode, the 5V regulator is not active, hence

all wake-up requests from Sleep mode require a power-up/

reset sequence.

External Reset

The 33912 has a bidirectional reset pin which drives the

device to a safe state (same as Reset mode) for as long as

this pin is held low. The RST pin must be held low long

enough to pass the internal glitch filter and get recognized by

the internal reset circuit. This functionality is also active in

Stop mode.

After the RST pin is released, there is no extra t

RST to be

considered.

WAKE-UP CAPABILITIES

Once entered into one of the low-power modes (Sleep or

Stop) only wake-up sources can bring the device into Normal

mode operation.

In Stop mode, a wake-up is signaled to the MCU as an

interrupt, while in Sleep mode the wake-up is performed by

activating the 5.0 V regulator and resetting the MCU. In both

cases the MCU can detect the wake-up source by accessing

the SPI registers. There is no specific SPI register bit to signal

a CS wake-up or external reset. If necessary this condition is

detected by excluding all other possible wake-up sources.

Wake-up from Wake-up inputs (L1-L4) with cyclic sense

disabled

The wake-up lines are dedicated to sense state changes

of external switches and wake-up the MCU (in Sleep or Stop

mode).

In order to select and activate direct wake-up from Lx

inputs, the Wake-up Control Register (WUCR) must be

configured with appropriate LxWE inputs enabled or

disabled. The wake-up input’s state is read through the

Wake-up Status Register (WUSR).

Lx inputs are also used to perform cyclic-sense wake-up.

Note: Selecting an Lx input in the analog multiplexer

before entering low power mode will disable the wake-up

capability of the Lx input

Wake-up from Wake-up inputs (L1-L4) with cyclic sense

timer enabled

The SBCLIN can wake-up at the end of a cyclic sense

period if on one of the four wake-up input lines (L1-L4) a state

change occurs. The HSx switch is activated in Sleep or Stop

modes from an internal timer. Cyclic sense and force wake-

up are exclusive. If cyclic sense is enabled, the force wake-

up can not be enabled.

In order to select and activate the cyclic sense wake-up

from Lx inputs, before entering in low power modes (Stop or

Sleep modes), the following SPI set-up has to be performed:

In WUCR: select the Lx input to WU-enable.

In HSCR: enable the desired HSx.

• In TIMCR: select the CS/WD bit and determine the

cyclic sense period with CYSTx bits.

• Perform Goto Sleep/Stop command.

Forced Wake-up

The 33912 can wake-up automatically after a

predetermined time spent in Sleep or Stop mode. Cyclic

sense and Forced wake-up are exclusive. If Forced wake-up

is enabled, the Cyclic Sense can not be enabled.

To determine the wake-up period, the following SPI set-up

has to be sent before entering in low power modes:

• In TIMCR: select the CS/WD bit and determine the low

power mode period with CYSTx bits.

• In HSCR: all HSx bits must be disabled.

CS Wake-up

While in Stop mode, a rising edge on the CS will cause a

wake-up. The CS wake-up does not generate an interrupt,

and is not reported on SPI.

LIN Wake-up

While in the low-power mode, the 33912 monitors the

activity on the LIN bus. A dominant pulse larger than t PROPWL

followed by a dominant to recessive transition will cause a

LIN wake-up. This behavior protects the system from a short

to ground bus condition.

Analog Integrated Circuit Device Data

76 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912BAC / MC34912BAC

RST Wake-up

While in Stop mode, the 33912 can wake-up when the

RST pin is held low long enough to pass the internal glitch

filter. Then, the 33912 will change to Normal Request or

Normal modes depending on the WDCONF pin

configuration. The RST wake-up does not generate an

interrupt and is not reported via SPI.

From Stop mode, the following wake-up events can be

configured:

• Wake-up from Lx inputs without cyclic sense

• Cyclic sense wake-up inputs

• Force wake-up

•CS wake-up

• LIN wake-up

•RST wake-up

From Sleep mode, the following wake-up events can be

configured:

• Wake-up from Lx inputs without cyclic sense

• Cyclic sense wake-up inputs

• Force wake-up

• LIN wake-up

WINDOW WATCHDOG

The 33912 includes a configurable window watchdog

which is active in Normal mode. The watchdog can be

configured by an external resistor connected to the WDCONF

pin. The resistor is used to achieve higher precision in the

timebase used for the watchdog.

SPI clears are performed by writing through the SPI in the

MOD bits of the Mode Control Register (MCR).

During the first half of the SPI timeout, watchdog clears are

not allowed, but after the first half of the SPI timeout window,

the clear operation opens. If a clear operation is performed

outside the window, the 33912 will reset the MCU, in the

same way as when the watchdog overflows.

Figure 39. Window Watchdog Operation

To disable the watchdog function in Normal mode the user

must connect the WDCONF pin to ground. This measure

effectively disables Normal Request mode. The WDOFF bit

in the Watchdog Status Register (WDSR) will be set. This

condition is only detected during Reset mode.

If neither a resistor nor a connection to ground is detected,

the watchdog falls back to the internal lower precision

timebase of 150 ms (typ.) and signals the faulty condition

through the Watchdog Status Register (WDSR).

The watchdog timebase can be further divided by a

prescaler which can be configured by the Timing Control

window watchdog is not active but there is a 150 ms (typ.)

timeout for leaving the Normal Request mode. In case of a

timeout, the 33912 will enter into Reset mode, resetting the

microcontroller before entering again into Normal Request

mode.

HIGH SIDE OUTPUT PINS HS1 AND HS2

These outputs are two high side drivers intended to drive

small resistive loads or LEDs incorporating the following

features:

• PWM capability (software maskable)

• Open load detection

• Current limitation

• Over-temperature shutdown (with maskable interrupt)

• High-voltage shutdown (software maskable)

• Cyclic sense

The high side switches are controlled by the bits HS1:2 in

the High Side Control Register (HSCR).

PWM Capability (direct access)

Each high side driver offers additional (to the SPI control)

direct control via the PWMIN pin.

If both the bits HS1 and PWMHS1 are set in the High Side

Control Register (HSCR), then the HS1 driver is turned on if

the PWMIN pin is high and turned of if the PWMIN pin is low.

This applies to HS2 configuring HS2 and PWMHS2 bits.

WD PERIOD (tPWD)

WINDOW CLOSED

NO WATCHDOG CLEAR

ALLOWED

WINDOW OPEN

FOR WATCHDOG

CLEAR

WD TIMING X 50% WD TIMING X 50%

WD TIMING SELECTED BY REGISTER

ON WDCONF PIN

Analog Integrated Circuit Device Data

Freescale Semiconductor 77

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912BAC / MC34912BAC

Figure 40. High Side Drivers HS1 and HS2

Open Load Detection

Each high side driver signals an open load condition if the

current through the high side is below the open load current

threshold.

The open load condition is indicated with the bits HS1OP

and HS2OP in the High Side Status Register (HSSR).

Current Limitation

Each high side driver has an output current limitation. In

combination with the over-temperature shutdown the high-

side drivers are protected against over-current and short-

circuit failures.

When the driver operates in the current limitation area, it is

indicated with the bits HS1CL and HS2CL in the HSSR.

Note: If the driver is operating in current limitation mode,

excessive power might be dissipated.

Over-temperature Protection (HS Interrupt)

Both high side drivers are protected against over-

temperature. In case of an over-temperature condition both

high side drivers are shut down and the event is latched in the

Interrupt Control Module. The shutdown is indicated as HS

Interrupt in the Interrupt Source Register (ISR).

A thermal shutdown of the high side drivers is indicated by

setting all HSxOP and HSxCL bits simultaneously.

If the bit HSM is set in the Interrupt Mask Register (IMR),

then an interrupt (IRQ) is generated.

A write to the High Side Control Register (HSCR), when

the over-temperature condition is gone, will re-enable the

high side drivers.

High-voltage Shutdown

In case of a high voltage condition and if the high voltage

shutdown is enabled (bit HVSE in the Mode Control Register

(MCR) is set) both high side drivers are shut down.

A write to the High Side Control Register (HSCR), when

the high voltage condition is gone, will re-enable the high side

drivers.

Sleep And Stop Mode

The high side drivers can be enabled to operate in Sleep

and Stop mode for cyclic sensing. Also see Table 37.

High Side - Driver

charge pump

open load detection

current limitation

Over-temperture shutdown (interrupt maskable)

high voltage shutdown (maskable)

Control

on/off

Status

PWMIN

VDD

PWMHSx

HSx

HVSE

HSxOP

HSxCL

MOD1:2

Interrupt

Control

Module

HSx

VS2

High Voltage Shutdown

High-Side Interrupt

VDD

Wakeup

Module

Cyclic Sense

Analog Integrated Circuit Device Data

78 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912BAC / MC34912BAC

LOW SIDE OUTPUT PINS LS1 AND LS2

These outputs are two low side drivers intended to drive

relays incorporating the following features:

• PWM capability (software maskable)

• Open load detection

• Current limitation

• Over-temperature shutdown (with maskable interrupt)

• Active clamp (for driving relays)

• High-voltage shutdown (software maskable)

The low side switches are controlled by the bit LS1:2 in the

Low Side Control Register (LSCR).

To protect the device against over-voltage when an

inductive load (relay) is turned off. An active clamp will re-

enable the low side FET if the voltage on the LS1 or LS2 pin

exceeds a certain level.

PWM Capability (direct access)

Each low side driver offers additional (to the SPI control)

direct control via the PWMIN pin.

If both the bits LS1 and PWMLS1 are set in the Low Side

Control Register (LSCR), then the LS1 driver is turned on if

the PWMIN pin is high and turned off if the PWMIN pin is low.

The same applies to the LS2 and PWMLS2 bits for the LS2

driver.

Figure 41. Low Side Drivers LS1 and LS2

Open Load Detection

Each low side driver signals an open load condition if the

current through the low side is below the open load current

threshold.

The open load condition is indicated with the bit LS1OP

and LS2OP in the Low Side Status Register (LSSR).

Current Limitation

Each low side driver has a current limitation. In

combination with the over-temperature shutdown the low

side drivers are protected against over-current and short-

circuit failures.

When the drivers operate in current limitation, this is

indicated with the bits LS1CL and LS2CL in the LSSR.

Note: If the drivers are operating in current limitation mode

excessive power might be dissipated.

Over-temperature Protection (LS Interrupt)

Both low side drivers are protected against over-

temperature. In case of an over-temperature condition both

low side drivers are shut down and the event is latched in the

Interrupt Control Module. The shutdown is indicated as an LS

Interrupt in the Interrupt Source Register (ISR).

If the bit LSM is set in the Interrupt Mask Register (IMR)

than an Interrupt (IRQ) is generated.

A write to the Low Side Control Register (LSCR), when the

over-temperature condition is gone, will re-enable the low

side drivers.

High-voltage Shutdown

In case of a high-voltage condition and if the high-voltage

shutdown is enabed (bit HVSE in the Mode Control Register

(MCR) is set) both low sides drivers are shut down.

A write to the Low Side Control Register (LSCR), when the

high-voltage condition is gone, will re-enable the low side

drivers.

Sleep And Stop Mode

The low side drivers are disabled in Sleep and Stop mode.

Also see Table 37.

LSx

Low Side Driver

(active clamp)

Open-load Detection

Current Limitation

Over-temperture Shutdown (interrupt maskable)

High-voltage shutdown (maskable)

PGND

active

clamp

Interrupt

Control

Module

HVSE

Control

on/off

Status

LSx

LSxOP

LSxCL

MOD1:2

High-voltage Shutdown

Low Side Interrupt

PWMIN

VDD

PWMLSx

VDD

Analog Integrated Circuit Device Data

Freescale Semiconductor 79

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912BAC / MC34912BAC

LIN PHYSICAL LAYER

The LIN bus pin provides a physical layer for single-wire

communication in automotive applications. The LIN physical

layer is designed to meet the LIN physical layer specification

and has the following features:

• LIN physical layer 2.0 compliant

• Slew rate selection

• Over-current shutdown

• Over-temperature shutdown

• LIN pull-up disable in Stop and Sleep modes

• Advanced diagnostics

• LIN dominant voltage level selection

The LIN driver is a low side MOSFET with over-current

and thermal shutdown. An internal pull-up resistor with a

serial diode structure is integrated, so no external pull-up

components are required for the application in a slave node.

The fall time from dominant to recessive and the rise time

from recessive to dominant is controlled. The symmetry

between both slopes is guaranteed.

LIN Pin

The LIN pin offers a high susceptibility immunity level from

external disturbance, guaranteeing communication during

external disturbance.

Figure 42. LIN Interface

Slew Rate Selection

The slew rate can be selected for optimized operation at

10.4 and 20 kBit/s as well as a fast baud rate for test and

programming. The slew rate can be adapted with the bits

LSR 1:0 in the LIN Control Register (LINCR). The initial slew

rate is optimized for 20 kBit/s.

LIN Pull-up Disable In Stop And Sleep Modes

In cases of a LIN bus short to GND or LIN bus leakage

during low-power mode, the internal pull-up resistor on the

LIN pin can be disconnected by clearing the LINPE bit in the

Mode Control Register (MCR). The LINPE bit also changes

the Bus wake-up threshold (VBUSWU).

This feature will reduce the current consumption in STOP

and SLEEP modes. It also improves performance and safe

operation.

High-voltage High Side

RXONLY

MOD1:2

LSR0:1

LINPE

LDVS

INTERRUPT

CONTROL

MODULE

LIN – DRIVER

Slope and Slew Rate Control

Over-current Shutdown (interrupt maskable)

Over-temperature Shutdown (interrupt maskable)

VS1

WAKE-UP

RXSHORT

LINOC

TXDOM

LINOT

LIN

FILTER

SLOPE

CONTROL

30K

LGND

LIN

RECEIVER

TXD

RXD

InterruptShutdown Wake-up

WAKE-UP

MODULE

Analog Integrated Circuit Device Data

80 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

MC33912BAC / MC34912BAC

Current Limit (LIN Interrupt)

The output low side FET is protected against over-current

conditions. In case of an over-current condition (e.g. LIN bus

short to VBAT), the transmitter will not be shut down. The bit

LINOC in the LIN Status Register (LINSR) is set.

If the LINM bit is set in the Interrupt Mask Register (IMR),

an Interrupt IRQ will be generated.

Over-temperature Shutdown (LIN Interrupt)

The output low side FET is protected against over-

temperature conditions. In case of an over-temperature

condition, the transmitter will be shut down and the LINOT bit

in the LIN Status Register (LINSR) is set.

If the LINM bit is set in the Interrupt Mask Register (IMR),

an Interrupt IRQ will be generated.

The transmitter is automatically re-enabled once the

condition is gone and TXD is high.

A read of the LIN Status Register (LINSR) with the TXD pin

high, will re-enable the transmitter.

RXD Short-circuit Detection (LIN Interrupt)

The LIN transceiver has a short-circuit detection for the

RXD output pin. In case of an short-circuit condition, either 5V

or Ground, the RXSHORT bit in the LIN Status Register

(LINSR) is set and the transmitter is shut down.

If the LINM bit is set in the Interrupt Mask Register (IMR),

an Interrupt IRQ will be generated.

The transmitter is automatically re-enabled once the

condition is gone (transition on RXD) and TXD is high.

A read of the LIN Status Register (LINSR) without the RXD

pin short-circuit condition will clear the bit RXSHORT.

TXD Dominant Detection (LIN Interrupt)

The LIN transceiver monitors the TXD input pin to detect a

stuck in dominant (0V) condition. In case of a stuck condition

(TXD pin 0 V for more than 1 second (typ.)), the transmitter is

shut down and the TXDOM bit in the LIN Status Register

(LINSR) is set.

If the LINM bit is set in the IMR, an Interrupt IRQ will be

generated.

The transmitter is automatically re-enabled once TXD is

high.

A read of the LIN Status Register (LINSR) with the TXD pin

at 5.0 V will clear the bit TXDOM.

LIN Dominant Voltage Level Selection

The LIN dominant voltage level can be selected by the bit

LDVS in the LIN Control Register (LINCR).

LIN Receiver Operation Only

While in Normal mode, the activation of the RXONLY bit

disables the LIN TXD driver. If case of a LIN error condition,

this bit is automatically set. If a low-power mode is selected

with this bit set, the LIN wake-up functionality is disabled,

then in STOP mode, the RXD pin will reflect the state of the

LIN bus.

STOP Mode And Wake-up Feature

During Stop mode operation, the transmitter of the

physical layer is disabled. If the LIN-PU bit was set in the Stop

mode sequence, the internal pull-up resistor is disconnected

from VSUP and a small current source keeps the LIN pin in

the recessive state. The receiver is still active and able to

detect wake-up events on the LIN bus line.

A dominant level longer than TPROPWL followed by a rising

edge will generate a wake-up interrupt, and will be reported

in the Interrupt Source Register (ISR). Also see Figure 34.

SLEEP Mode And Wake-up Feature

During Sleep mode operation, the transmitter of the

physical layer is disabled. If the LIN-PU bit was set in the

Sleep mode sequence, the internal pull-up resistor is

disconnected from VSUP and a small current source keeps

the LIN pin in recessive state. The receiver must be active to

detect wake-up events on the LIN bus line.

A dominant level longer than TPROPWL followed by a rising

edge will generate a system wake-up (Reset), and will be

reported in the Interrupt Source Register (ISR). Also see

Figure 33.

Analog Integrated Circuit Device Data

Freescale Semiconductor 81

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912BAC / MC34912BAC

LOGIC COMMANDS AND REGISTERS

33912 SPI INTERFACE AND CONFIGURATION

The serial peripheral interface creates the communication

link between a microcontroller (master) and the 33912.

The interface consists of four pins (see Figure 43):

•CS — Chip Select

•MOSI — Master-Out Slave-In

•MISO — Master-In Slave-Out

•SCLK— Serial Clock

A complete data transfer via the SPI consists of 1 byte.

The master sends 4 bits of address (A3:A0) + 4 bits of control

information (C3:C0) and the slave replies with 4 system

status bits (VMS,LINS,HSS,LSS) + 4 bits of status

information (S3:S0).

Figure 43. SPI Protocol

During the inactive phase of the CS (HIGH), the new data

transfer is prepared.

The falling edge of the CS indicates the start of a new data

transfer and puts the MISO in the low-impedance state and

latches the analog status data (Register read data).

With the rising edge of the SPI clock (SCLK), the data is

moved to MISO/MOSI pins. With the falling edge of the SPI

clock (SCLK), the data is sampled by the receiver.

The data transfer is only valid if exactly 8 sample clock

edges are present during the active (low) phase of CS.

The rising edge of the Chip Select CS indicates the end of

the transfer and latches the write data (MOSI) into the

state.

condition. Reset condition is the condition causing the bit to

be set to its reset value. The main reset conditions are:

- Power-On Reset (POR): the level at which the logic is

reset and BATFAIL flag sets.

- Reset mode

- Reset done by the RST pin (ext_reset)

MOSI

MISO

SCLK

A2 A1 A0 C3 C2 C1 C0A3

VMS LINS HSS LSS S3 S2 S1 S0

Read Data Latch

Rising Edge of SCLK

Change MISO/MISO Output

Falling Edge of SCLK

Sample MISO/MISO Input

Write Data Latch

Analog Integrated Circuit Device Data

82 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912BAC / MC34912BAC

SPI REGISTER OVERVIEW

Table 39 summarizes the SPI Register content for Control Information (C3:C0)=W and status information (S3:S0) = R.

Table 38. System Status Register

Adress(A3:A0) Register Name / Read / Write Information

BIT

7 6 5 4

$0 - $F SYSSR - System Status Register RVMS LINS HSS LSS

Table 39. SPI Register Overview

Adress(A3:A0) Register Name / Read / Write Information

BIT

3 2 1 0

MCR - Mode Control Register WHVSE LINPE MOD2 MOD1

VSR - Voltage Status Register RVSOV VSUV VDDOT BATFAIL

$1 VSR - Voltage Status Register RVSOV VSUV VDDOT BATFAIL

WUCR - Wake-up Control Register WL4WE L3WE L2WE L1WE

WUSR - Wake-up Status Register RL4 L3 L2 L1

$3 WUSR - Wake-up Status Register RL4 L3 L2 L1

LINCR - LIN Control Register WLDVS RXONLY LSR1 LSR0

LINSR - LIN Status Register RRXSHORT TXDOM LINOT LINOC

$5 LINSR - LIN Status Register RRXSHORT TXDOM LINOT LINOC

HSCR - High Side Control Register WPWMHS2 PWMHS1 HS2 HS1

HSSR - High Side Status Register RHS2OP HS2CL HS1OP HS1CL

$7 HSSR - High Side Status Register RHS2OP HS2CL HS1OP HS1CL

LSCR - Low Side Control Register WPWMLS2 PWMLS1 LS2 LS1

LSSR - Low Side Status Register RLS2OP LS2CL LS1OP LS1CL

$9 LSSR - Low Side Status Register RLS2OP LS2CL LS1OP LS1CL

TIMCR - Timing Control Register W CS/WD

WD2 WD1 WD0

CYST2 CYST1 CYST0

WDSR - Watchdog Status Register RWDTO WDERR WDOFF WDWO

$B WDSR - Watchdog Status Register RWDTO WDERR WDOFF WDWO

$C AMUXCR - Analog Multiplexer Control Register WLXDS MX2 MX1 MX0

$D CFR - Configuration Register WHVDD CYSX8 CSAZ CSGS

IMR - Interrupt Mask Register WHSM LSM LINM VMM

ISR - Interrupt Source Register RISR3 ISR2 ISR1 ISR0

$F ISR - Interrupt Source Register RISR3 ISR2 ISR1 ISR0

Analog Integrated Circuit Device Data

Freescale Semiconductor 83

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912BAC / MC34912BAC

System Status Register - SYSSR

The System Status Register (SYSSR) is always

transferred with every SPI transmission and gives a quick

system status overview. It summarizes the status of the

Voltage Status Register (VSR), LIN Status Register (LINSR),

High Side Status Register (HSSR), and the Low Side Status

VMS - Voltage Monitor Status

This read-only bit indicates that one or more bits in the

VSR are set.

1 = Voltage Monitor bit set

0 = None

Figure 44. Voltage Monitor Status

LINS - LIN Status

This read-only bit indicates that one or more bits in the

LINSR are set.

1 = LIN Status bit set

0 = None

Figure 45. LIN Status

HSS - High Side Switch Status

This read-only bit indicates that one or more bits in the

HSSR are set.

1 = High Side Status bit set

0 = None

Figure 46. High Side Status

LSS - Low Side Switch Status

This read-only bit indicates that one or more bits in the

LSSR are set.

1 = Low Side Status bit set

0 = None

Figure 47. Low Side Status

Mode Control Register - MCR

The Mode Control Register (MCR) allows switching

between the operation modes and to configure the 33912.

Writing the MCR will return the VSR.

HVSE - High-voltage Shutdown Enable

This write-only bit enables/disables automatic shutdown of

the high side and the low side drivers during a high-voltage

VSOV condition.

1 = automatic shutdown enabled

0 = automatic shutdown disabled

LINPE - LIN pull-up enable.

This write-only bit enables/disables the 30 kΩ LIN pull-up

resistor in STOP and SLEEP modes. This bit also controls

the LIN bus wake-up threshold.

1 = LIN pull-up resistor enabled

0 = LIN pull-up resistor disabled

Table 40. System Status Register

S7 S6 S5 S4

Read VMS LINS HSS LSS

VMS

BATFAIL

VDDOT

VSUV

VSOV

LINS

LINOC

LINOT

TXDOM

RXSHORT

Table 41. Mode Control Register - $0

C3 C2 C1 C0

Write HVSE LINPE MOD2 MOD1

Reset

Value 11--

Reset

Condition POR POR - -

HS2OP

HS2CL

HS1OP

HS1CL

HSS

LS2OP

LS2CL

LS1OP

LS1CL

LSS

Analog Integrated Circuit Device Data

84 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912BAC / MC34912BAC

MOD2, MOD1 - Mode Control Bits

These write-only bits select the operating mode and allow

clearing the watchdog in accordance with Table 82 Mode

Control Bits.

Voltage Status Register - VSR

Returns the status of the several voltage monitors. This

VSOV - VSUP Over-voltage

This read-only bit indicates an over-voltage condition on

the VS1 pin.

1 = Over-voltage condition.

0 = Normal condition.

VSUV - VSUP Under-Voltage

This read-only bit indicates an under-voltage condition on

the VS1 pin.

1 = Under-voltage condition.

0 = Normal condition.

VDDOT - Main Voltage Regulator Over-temperature

Warning

This read-only bit indicates that the main voltage regulator

temperature reached the Over-temperature Prewarning

Threshold.

1 = Over-temperature Prewarning

0 = Normal

BATFAIL - Battery Fail Flag.

This read-only bit is set during power-up and indicates that

the 33912 had a Power-On-Reset (POR).

Any access to the MCR or VSR will clear the BATFAIL flag.

1 = POR Reset has occurred

0 = POR Reset has not occurred

Wake-up Control Register - WUCR

This register is used to control the digital wake-up inputs.

Writing the WUCR will return the Wake-up Status Register

(WUSR).

LxWE - Wake-up Input x Enable

This write-only bit enables/disables which Lx inputs are

enabled. In Stop and Sleep mode the LxWE bit determines

which wake inputs are active for wake-up. If one of the Lx

inputs is selected on the analog multiplexer, the

corresponding LxWE is masked to 0.

1 = Wake-Up Input x enabled.

0 = Wake-Up Input x disabled.

Wake-up Status Register - WUSR

This register is used to monitor the digital wake-up inputs

and is also returned when writing to the WUCR.

Lx - Wake-up input x

This read-only bit indicates the status of the corresponding

Lx input. If the Lx input is not enabled, then the according

Wake-Up status will return 0.

After a wake-up from Stop or Sleep mode these bits also

allow to determine which input has caused the wake-up, by

first reading the Interrupt Status Register (ISR) and then

reading the WUSR.

1 = Lx Wake-up.

0 = Lx Wake-up disabled or selected as analog input.

Table 42. Mode Control Bits

MOD2 MOD1 Description

0 0 Normal Mode

0 1 Stop Mode

1 0 Sleep Mode

1 1 Normal Mode + Watchdog Clear

Table 43. Voltage Status Register - $0/$1

S3 S2 S1 S0

Read VSOV VSUV VDDOT BATFAIL

Table 44. Wake-up Control Register - $2

C3 C2 C1 C0

Write L4WE L3WE L2WE L1WE

Reset

Value 1111

Reset

Condition POR, Reset mode or ext_reset

Table 45. Wake-up Status Register - $2/$3

S3 S2 S1 S0

Read L4 L3 L2 L1

Analog Integrated Circuit Device Data

Freescale Semiconductor 85

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912BAC / MC34912BAC

LIN Control Register - LINCR

This register controls the LIN physical interface block.

Writing the LIN Control Register (LINCR) returns the LIN

Status Register (LINSR).

* LIN failure gone: if LIN failure (over-temp, TXD/RXD short) was set, the flag

resets automatically when the failure is gone.

LDVS - LIN Dominant Voltage Select

This write-only bit controls the LIN Dominant voltage:

1 = LIN Dominant Voltage = VLIN_DOM_1 (1.7V typ)

0 = LIN Dominant Voltage = VLIN_DOM_0 (1.1V typ)

RXONLY - LIN Receiver Operation Only

This write-only bit controls the behavior of the LIN

transmitter.

In Normal mode, the activation of the RXONLY bit disables

the LIN transmitter. In case of a LIN error condition, this bit is

automatically set.

In Stop mode this bit disables the LIN wake-up

functionality, and the RXD pin will reflect the state of the LIN

bus.

1 = only LIN receiver active (Normal mode) or LIN wake-

up disabled (Stop mode).

0 = LIN fully enabled.

LSRx - LIN Slew-Rate

This write-only bit controls the LIN driver slew-rate in

accordance with Table 47.

LIN Status Register - LINSR

This register returns the status of the LIN physical

interface block and is also returned when writing to the

LINCR.

RXSHORT - RXD Pin Short-circuit

This read-only bit indicates a short-circuit condition on the

RXD pin (shorted either to 5.0 V or to Ground). The short-

circuit delay must be a worst case of 8µs to be detected and

to shut down the driver. To clear this bit, it must be read after

the condition is gone (transition detected on RXD pin). The

LIN driver is automatically re-enabled once the condition is

gone.

1 = RXD short-circuit condition.

0 = None.

TXDOM - TXD Permanent Dominant

This read-only bit signals the detection of a TXD pin stuck

at dominant (Ground) condition and the resultant shutdown in

the LIN transmitter. This condition is detected after the TXD

pin remains in dominant state for more than 1 second (typical

value).

To clear this bit, it must be read after TXD has gone high.

The LIN driver is automatically re-enabled once TXD goes

High.

1 = TXD stuck at dominant fault detected.

0 = None.

LINOT - LIN Driver Over-temperature Shutdown

This read-only bit signals that the LIN transceiver was

shutdown due to over-temperature. The transmitter is

automatically re-enabled after the over-temperature

condition is gone and TXD is high. The LINOT bit is cleared

after SPI read once the condition is gone.

1 = LIN over-temperature shutdown

0 = None

LINOC - LIN Driver Over-Current Shutdown

This read-only bit signals an over-current condition

occurred on the LIN pin. The LIN driver is not shut down but

an IRQ is generated. To clear this bit, it must be read after the

condition is gone.

1 = LIN over-current shutdown

0 = None

Table 46. LIN Control Register - $4

C3 C2 C1 C0

Write LDVS RXONLY LSR1 LSR0

Reset

Value 0000

Reset

Condition

POR, Reset

mode or

ext_reset

POR, Reset

mode, ext_reset

or LIN failure

gone*

POR

Table 47. LIN Slew-Rate Control

LSR1 LSR0 Description

0 0 Normal Slew Rate (up to 20kb/s)

0 1 Slow Slew Rate (up to 10kb/s)

1 0 Fast Slew Rate (up to 100kb/s)

1 1 Reserved

Table 48. LIN Status Register - $4/$5

S3 S2 S1 S0

Read RXSHORT TXDOM LINOT LINOC

Analog Integrated Circuit Device Data

86 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912BAC / MC34912BAC

High Side Control Register - HSCR

This register controls the operation of the high side drivers.

Writing to this register returns the High Side Status Register

(HSSR).

PWMHSx - PWM Input Control Enable.

This write-only bit enables/disables the PWMIN input pin

to control the respective high side switch. The corresponding

high side switch must be enabled (HSx bit).

1 = PWMIN input controls HSx output.

0 = HSx is controlled only by SPI.

HSx - HSx Switch Control.

This write-only bit enables/disables the corresponding

high side switch.

1 = HSx switch on.

0 = HSx switch off.

High Side Status Register - HSSR

This register returns the status of the high side switches

and is also returned when writing to the HSCR.

High Side Thermal Shutdown

A thermal shutdown of the high side drivers is indicated by

setting all HSxOP and HSxCL bits simultaneously.

HSxOP - High Side Switch Open-Load Detection

This read-only bit signals that the high side switches are

conducting current below a certain threshold indicating

possible load disconnection.

1 = HSx Open Load detected (or thermal shutdown)

0 = Normal

HSxCL - High Side Current Limitation

This read-only bit indicates that the respective high side

switch is operating in current limitation mode.

1 = HSx in current limitation (or thermal shutdown)

0 = Normal

Low Side Control Register - LSCR

This register controls the operation of the low side drivers.

Writing the Low Side Control Register (LSCR) will also return

the Low Side Status Register (LSSR).

PWMLx - PWM input control enable.

This write-only bit enables/disables the PWMIN input pin

to control the respective low side switch. The corresponding

low side switch must be enabled (LSx bit).

1 = PWMIN input controls LSx.

0 = LSx is controlled only by SPI.

LSx - LSx switch control.

This write-only bit enables/disables the corresponding low

side switch.

1 = LSx switch on.

0 = LSx switch off.

Low Side Status Register - LSSR

This register returns the status of the low side switches

and is also returned when writing to the LSCR.

Low Side Thermal Shutdown

A thermal shutdown of the low side drivers is indicated by

setting all LSxOP and LSxCL bits simultaneously.

LSxOP - Low Side Switch Open-Load Detection

This read-only bit signals that the low side switches are

conducting current below a certain threshold indicating

possible load disconnection.

1 = LSx Open Load detected (or thermal shutdown)

0 = Normal

LSxCL - Low Side Current Limitation

This read-only bit indicates that the respective low side

switch is operating in current limitation mode.

1 = LSx in current limitation (or thermal shutdown)

0 = Normal

Table 49. High Side Control Register - $6

C3 C2 C1 C0

Write PWMHS2 PWMHS1 HS2 HS1

Reset

Value 00 0 0

Reset

Condition POR POR, Reset mode, ext_reset, HSx

over-temp or (VSOV & HVSE)

Table 50. High Side Status Register - $6/$7

S3 S2 S1 S0

Read HS2OP HS2CL HS1OP HS1CL

Table 51. Low Side Control Register - $8

C3 C2 C1 C0

Write PWMLS2 PWMLS1 LS2 LS1

Reset

Value 00 0 0

Reset

Condition POR POR, Reset mode, ext_reset, LSx

over-temp or (VSOV & HVSE)

Table 52. Low Side Status Register - $8/$9

C3 C2 C1 C0

Read LS2OP LS2CL LS1OP LS1CL

Analog Integrated Circuit Device Data

Freescale Semiconductor 87

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912BAC / MC34912BAC

Timing Control Register - TIMCR

This register is a double purpose register which allows to

configure the watchdog and the cyclic sense periods. Writing

to the Timing Control Register (TIMCR) will also return the

Watchdog Status Register (WDSR).

CS/WD - Cyclic Sense or Watchdog prescaler select

This write-only bit selects which prescaler is being written

to, the Cyclic Sense prescaler or the Watchdog prescaler.

1 = Cyclic Sense Prescaler selected

0 = Watchdog Prescaler select

WDx - Watchdog Prescaler

This write-only bits selects the divider for the watchdog

prescaler and therefore selects the watchdog period in

accordance with Table 54. This configuration is valid only if

windowing watchdog is active.

Table 54. Watchdog Prescaler

CYSTx - Cyclic Sense Period Prescaler Select

This write-only bits selects the interval for the wake-up

cyclic sensing together with the bit CYSX8 in the

Configuration Register (CFR) (see Configuration Register -

CFR).

This option is only active if one of the high side switches is

enabled when entering in Stop or Sleep mode. Otherwise a

timed wake-up is performed after the period shown in

Table 55.

Watchdog Status Register - WDSR

This register returns the Watchdog status information and

is also returned when writing to the TIMCR.

WDTO - Watchdog Timeout

This read-only bit signals the last reset was caused by

either a watchdog timeout or by an attempt to clear the

Watchdog within the window closed.

Any access to this register or the Timing Control Register

(TIMCR) will clear the WDTO bit.

1 = Last reset caused by watchdog timeout

0 = None

Table 53. Timing Control Register - $A

C3 C2 C1 C0

Write CS/WD

WD2 WD1 WD0

CYST2 CYST1 CYST0

Reset

Value -000

Reset

Condition -POR

WD2 WD1 WD0 Prescaler Divider

0 0 0 1

0 0 1 2

0 1 0 4

0 1 1 6

1 0 0 8

101 10

110 12

111 14

Table 55. Cyclic Sense Interval

CYSX8(132) CYST2 CYST1 CYST0 Interval

X 0 0 0 No cyclic sense

0 0 0 1 20 ms

0 0 1 0 40 ms

0 0 1 1 60 ms

0 1 0 0 80 ms

0 1 0 1 100 ms

0 1 1 0 120 ms

0 1 1 1 140 ms

1 0 0 1 160 ms

1 0 1 0 320 ms

1 0 1 1 480 ms

1 1 0 0 640 ms

1 1 0 1 800 ms

1 1 1 0 960 ms

1 1 1 1 1120 ms

Notes

132. bit CYSX8 is located in Configuration Register (CFR)

Table 56. Watchdog Status Register - $A/$B

S3 S2 S1 S0

Read WDTO WDERR WDOFF WDWO

Analog Integrated Circuit Device Data

88 Freescale Semiconductor

33912

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33912BAC / MC34912BAC

WDERR - Watchdog Error

This read-only bit signals the detection of a missing

watchdog resistor. In this condition the watchdog is using the

internal, lower precision timebase. The Windowing function is

disabled.

1 = WDCONF pin resistor missing

0 = WDCONF pin resistor not floating

WDOFF - Watchdog Off

This read-only bit signals that the watchdog pin connected

to Ground and therefore disabled. In this case watchdog

timeouts are disabled and the device automatically enters

Normal mode out of Reset. This might be necessary for

software debugging and for programming the Flash memory.

1 = Watchdog is disabled

0 = Watchdog is enabled

WDWO - Watchdog Window Open

This read-only bit signals when the watchdog window is

open for clears. The purpose of this bit is for testing. Should

be ignored in case WDERR is High.

1 = Watchdog window open

0 = Watchdog window closed

Analog Multiplexer Control Register - MUXCR

This register controls the analog multiplexer and selects

the divider ration for the Lx input divider.

LXDS - Lx Analog Input Divider Select

This write-only bit selects the resistor divider for the Lx

analog inputs. Voltage is internally clamped to VDD.

0 = Lx Analog divider: 1

1 = Lx Analog divider: 3.6 (typ.)

MXx - Analog Multiplexer Input Select

These write-only bits selects which analog input is

multiplexed to the ADOUT0 pin according to Table 58.

When disabled or when in Stop or Sleep mode, the output

buffer is not powered and the ADOUT0 output is left floating

to achieve lower current consumption.

Table 58. Analog Multiplexer Channel Select

Configuration Register - CFR

This register controls the Hall Sensor Supply enable/

disable, the cyclic sense timing multiplier, enables/disables

the Current Sense Auto-zero function and selects the gain for

the current sense amplifier.

HVDD - Hall Sensor Supply Enable

This write-only bit enables/disables the state of the hall

sensor supply.

1 = HVDD on

0 = HVDD off

CYSX8 - Cyclic Sense Timing x 8.

This write-only bit influences the cyclic sense period as

shown in Table 55.

1 = Multiplier enabled

0 = None

CSAZ - Current Sense Auto-Zero Function Enable

This write-only bit enables/disables the circuitry to lower

the offset voltage of the current sense amplifier.

1 = Auto-zero function enabled

0 = Auto-zero function disabled

CSGS - Current Sense Amplifier Gain Select

This write-only bit selects the gain of the current sense

amplifier.

1 = 14.5 (typ.)

0 = 30 (typ.)

Table 57. Analog Multiplexer Control Register -$C

C3 C2 C1 C0

Write LXDS MX2 MX1 MX0

Reset

Value 1 000

Reset

Condition POR POR, Reset mode or ext_reset

MX2 MX1 MX0 Meaning

000 Disabled

001 Reserved

010 Die Temperature Sensor

011 VSENSE input

100 L1 input

101 L2 input

110 L3 input

111 L4 input

Table 59. Configuration Register - $D

C3 C2 C1 C0

Write HVDD CYSX8 CSAZ CSGS

Reset

Value 0000

Reset

Condition

POR, Reset

mode or

ext_reset

POR POR POR

Analog Integrated Circuit Device Data

Freescale Semiconductor 89

33912

FUNCTIONAL DEVICE OPERATIONS

MC33912BAC / MC34912BAC

Interrupt Mask Register - IMR

This register allows masking of some of the interrupt

sources. The respective flags within the Interrupt Source

interrupts to the MCU. The 5.0 V Regulator over-temperature

prewarning interrupt and Under-Voltage (VSUV) interrupts

can not be masked and will always cause an interrupt.

Writing to the IMR will return the ISR.

HSM - High Side Interrupt Mask

This write-only bit enables/disables interrupts generated in

the high side block.

1 = HS Interrupts Enabled

0 = HS Interrupts Disabled

LSM - Low Side Interrupt Mask

This write-only bit enables/disables interrupts generated in

the low side block.

1 = LS Interrupts Enabled

0 = LS Interrupts Disabled

LINM - LIN Interrupts Mask

This write-only bit enables/disables interrupts generated in

the LIN block.

1 = LIN Interrupts Enabled

0 = LIN Interrupts Disabled

VMM - Voltage Monitor Interrupt Mask

This write-only bit enables/disables interrupts generated in

the Voltage Monitor block. The only maskable interrupt in the

Voltage Monitor Block is the VSUP over-voltage interrupt.

1 = Interrupts Enabled

0 = Interrupts Disabled

Interrupt Source Register - ISR

This register allows the MCU to determine the source of

the last interrupt or wake-up respectively. A read of the

high, in case there are no other pending interrupts. If there

are pending interrupts, IRQ will be driven high for 10 µs and

then be driven low again.

This register is also returned when writing to the Interrupt

Mask Register (IMR).

ISRx - Interrupt Source Register

These read-only bits indicate the interrupt source following

Table 62. If no interrupt is pending then all bits are 0.

In case more than one interrupt is pending, the interrupt

sources are handled sequentially multiplex.

Table 62. Interrupt Sources

Table 60. Interrupt Mask Register - $E

C3 C2 C1 C0

Write HSM LSM LINM VMM

Reset

Value 1111

Reset

Condition POR

Table 61. Interrupt Source Register - $E/$F

S3 S2 S1 S0

Read ISR3 ISR2 ISR1 ISR0

Interrupt Source Priority

ISR3 ISR2 ISR1 ISR0 none maskable maskable

0000 no interrupt no interrupt none

0001 Lx Wake-up from Stop mode- highest

0010 - HS Interrupt (Over-temperature)

0011 - LS Interrupt (Over-temperature)

0100 LIN Interrupt (RXSHORT, TXDOM, LIN OT, LIN

OC) or LIN Wake-up

0101 Voltage Monitor Interrupt

(Low Voltage and VDD over-temperature)

Voltage Monitor Interrupt

(High Voltage)

0110 - Forced Wake-up lowest

Analog Integrated Circuit Device Data

90 Freescale Semiconductor

33912

TYPICAL APPLICATION

MC33912BAC / MC34912BAC

TYPICAL APPLICATION

The 33912 can be configured in several applications. The figure below shows the 33912 in the typical Slave Node Application.

Voltage Regulator

SPI

CONTROL

Reset

Control Module

LVR, HVR, HTR, WD,

Window

Watchdog Module

LIN Physical Layer

VS2

5V Output Module

HS1

LS2

HVDD

VSENSE

ISENSEL

Analog Input Module

Digital Input Module

LIN

RXD

ADOUT0

SCLK

MOSI

MISO

TXD

Wake Up Module

Current Sense Module

Interrupt

Control Module

LVI, HVI, HTI, OCI

Low Side Control

Module

VBAT Sense Module

Analog Multiplexer

HS2

LS1

ISENSEH

PGND

WDCONF

Chip Temp Sense Module

PWMIN

High Side Control

Module

LGND

Internal

Bus

MCU

RST

IRQ

ADOUT1

AGND

PGND

VS1

AGND

VDD

A/D

SCI

SPI

TIMER

RST

VDD

IRQ

C4 C3

C2 C1

Analog Input

LIN

Hall Sensor Supply

HB Type Relay

Motor Output

BAT

Typical Component Values:

C1 = 47µF; C2 = C4 = 100nF; C3 = 10µF; C5 = 4.7µF; C6 = 220pF

R1 = 10kΩ; R2 = R3 = 10kΩ; R4 = R5 = 33kΩ; R6 = 20Ω; R7 = 20kΩ-200kΩ

Recommended Configuration of the not Connected Pins (NC):

Pin 28 = this pin is not internally connected and may be used for PCB routing

optimization.

Analog Integrated Circuit Device Data

Freescale Semiconductor 91

33912

PACKAGING

PACKAGE DIMENSIONS

MC33912BAC / MC34912BAC

PACKAGING

PACKAGE DIMENSIONS

Important For the most current revision of the package, visit www.Freescale.com and select Documentation, then under

Available Documentation column select Packaging Information.

AC SUFFIX (PB-FREE)

32-PIN LQFP

98ASH70029A

REVISION D

Analog Integrated Circuit Device Data

92 Freescale Semiconductor

33912

IMPORTANT FOR THE MOST CURRENT REVISION OF THE PACK-

AGE, VISIT WWW.FREESCALE.COM AND SELECT DOCUMENTA-

MC33912BAC / MC34912BAC

PACKAGE DIMENSIONS (Continued)

AC SUFFIX (PB-FREE)

32-PIN LQFP

98ASH70029A

REVISION D

Analog Integrated Circuit Device Data

Freescale Semiconductor 93

33912

REVISION HISTORY

MC33912BAC / MC34912BAC

REVISION HISTORY

Revision Date Description of Changes

1.0 5/2007 • Initial Release

2.0 9/2007 • Several textual corrections

• Page 11: “Analog Output offset Ratio” (LXDS=1) changed to “Analog Output offset” +/-22mV

• Page 11: VSENSE Input Divider Ratio adjusted to 5,0/5,25/5,5

• Page 12: Common mode input impedance corrected to 75kΩ

• Page 13/15: LIN PHYSICAL LAYER parameters adjusted to final LIN specification release

3.0 9/2007 • Revision number incremented at engineering request.

4.0 2/2008 • Changed Functional Block Diagram on page 24.

• This Data Sheet and previous versions cover Part Numbers MC33912BAC and MC34912BAC. Future

revisions do not cover these Part Numbers.

5.0 10/2008 • Datasheet updated according to the Pass1.2 silicon version electrical parameters

• Add Maximum Rating on IBUS_NO_GND parameter

• Added L1, L2, L3, and L4, Temperature Sense Analog Output Voltage per characterization(39), Internal Chip

Temperature Sense Gain per characterization at 3 temperatures(39) See Figure 16, Temperature Sense Gain,

VSENSE Input Divider Ratio (RATIOVSENSE=VSENSE/VADOUT0) per characterization(40), and VSENSE

Output Related Offset per characterization(40) parameters

• Added Temperature Sense Gain section

• Minor corrections to ESD Capability, (18), Cyclic Sense ON Time from Stop and Sleep mode(50), Lin Bus Pin

(LIN), Serial Data Clock Pin (SCLK), Master Out Slave In Pin (MOSI), Master In Slave Out Pin (MISO), Low

Side Pins (LS1 and LS2), Digital/analog Pins (L1, L2, L3 and L4), Normal Request Mode, Sleep Mode, LIN

Over-temperature Shutdown / TXD Stuck At Dominant / RXD Short-circuit:, Fault Detection Management

Conditions, Lin Physical Layer, LIN Interface, Over-temperature Shutdown (LIN Interrupt), LIN Receiver

Operation Only, SPI Protocol, Lx - Wake-up input x, LIN Control Register - LINCR, and RXSHORT - RXD Pin

Short-circuit

• This data sheet does not contain electrical parameters for MC33912BAC and MC34912BAC (see revision

4.0).

• Updated Freescale form and style

6.0 2/2009 • Added explanation for pins Not Connected (NC).

• This data sheet does not contain electrical parameters for MC33912BAC and MC34912BAC (see revision

4.0).

7.0 3/2009 • Changed VBAT_SHIFT and GND_SHIFT maximum from 10% to 11.5% for both parameters on page 14.

• This data sheet does not contain electrical parameters for MC33912BAC and MC34912BAC (see revision

4.0).

8.0 3/2010 • Combined Complete Data sheet for Part Numbers MC33912BAC and MC34912BAC to the back of this data

sheet.

• Changed ESD Voltage for Machine Model from ± 200 to ± 150

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MC33912

Rev. 8.0

3/2010

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