LTC2632
1
Rev. C
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BLOCK DIAGRAM
FEATURES DESCRIPTION
Dual 12-/10-/8-Bit SPI
VOUT DACs with
10ppm/°C Reference
The LTC
®
2632 is a family of dual 12-, 10-, and 8-bit
voltage-output DACs with an integrated, high-accuracy,
low-drift reference in an 8-lead TSOT-23 package. It has
rail-to-rail output buffers and is guaranteed monotonic.
The LTC2632-L has a full-scale output of 2.5V, and oper-
ates from a single 2.7V to 5.5V supply. The LTC2632-H
has a full-scale output of 4.096V, and operates from a
4.5V to 5.5V supply. Each DAC can also operate with an
external reference, which sets the full-scale output to the
external reference voltage.
These DACs communicate via a simple SPI/MICROWIRE
compatible 3-wire serial interface which operates at clock
rates up to 50MHz. The LTC2632 incorporates a power-on
reset circuit. Options are available for reset to zero-scale
or reset to mid-scale in internal reference mode, or reset
to mid-scale in external reference mode after power-up.
Integral Nonlinearity (LTC2632A-LZ12)
APPLICATIONS
n Integrated Precision Reference
2.5V Full-Scale 10ppm/°C (LTC2632-L)
4.096V Full-Scale 10ppm/°C (LTC2632-H)
n Maximum INL Error: ±1.5LSB (LTC2632A-12)
n Low Noise: 0.75mVP-P 0.1Hz to 200kHz
n Guaranteed Monotonic –40°C to 125°C Automotive
Temperature Range
n Selectable Internal or External Reference
n 2.7V to 5.5V Supply Range (LTC2632-L)
n Low Power Operation 0.4mA at 3V
n Power-On-Reset to Zero-Scale/Mid-Scale
n Double-Buffered Data Latches
n 8-Lead ThinSOT™ Package
n Mobile Communications
n Process Control and Industrial Automation
n Automatic Test Equipment
n Portable Equipment
n Automotive
CODE
0
INL (LSB)
2
1
0
–1
–2 1024 3072
2632 TA01
40952048
VCC = 3V
INTERNAL REF.
REGISTER
INTERNAL
REFERENCE
REGISTER
REGISTER
POWER-ON
RESET
32-BIT SHIFT REGISTER
REGISTER
CONTROL
LOGIC DECODE
SCK
REF
VREF
2632 BD
CS/LD SDI
VOUTA
VCC
VOUTB
DAC A DAC B
SWITCH
GND
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 5396245, 5859606, 6891433, and 6937178.
LTC2632
2
Rev. C
For more information www.analog.com
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) ................................... –0.3V to 6V
SCK, SDI ...................................................... –0.3V to 6V
CS/LD (Note 10) ...............–0.3V to Min (VCC + 0.3V, 6V)
VOUTA, VOUTB ...................–0.3V to Min (VCC + 0.3V, 6V)
REF ..................................–0.3V to Min (VCC + 0.3V, 6V)
Operating Temperature Range
LTC2632C ................................................ 0°C to 70°C
LTC2632H .......................................... –40°C to 125°C
Maximum Junction Temperature .......................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ...................300°C
(Notes 1, 2)
1
2
3
4
8
7
6
5
TOP VIEW
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
T
JMAX = 150°C (NOTE 6), θJA
= 195°C/W
SDI
VCC
VOUTB
VOUTA
SCK
CS/LD
REF
GND
ORDER INFORMATION
LTC2632 A C TS8 –L Z 12 #TRM PBF
LEAD FREE DESIGNATOR
TAPE AND REEL
TR = 2,500-Piece Tape and Reel
TRM = 500-Piece Tape and Reel
RESOLUTION
12 = 12-Bit
10 = 10-Bit
8 = 8-Bit
POWER-ON RESET
I = Reset to Mid-Scale in Internal Reference Mode
X = Reset to Mid-Scale in External Reference Mode (2632-L Only)
Z = Reset to Zero-Scale in Internal Reference Mode
FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE
L = 2.5V
H = 4.096V
PACKAGE TYPE
TS8 = 8-Lead Plastic TSOT-23
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
H = Automotive Temperature Range (–40°C to 125°C)
ELECTRICAL GRADE (OPTIONAL)
A = ±1.5LSB Maximum INL (12-Bit)
PRODUCT PART NUMBER
Contact the factory for parts specified with wider operating temperature ranges.
Contact the factory for information on lead based finish parts.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
LTC2632
3
Rev. C
For more information www.analog.com
PRODUCT SELECTION GUIDE
PART NUMBER PART MARKING*
VFS WITH INTERNAL
REFERENCE
POWER-ON
RESET TO CODE
POWER-ON
REFERENCE MODE RESOLUTION VCC MAXIMUM INL
LTC2632A-LI12
LTC2632A-LX12
LTC2632A-LZ12
LTC2632A-HI12
LTC2632A-HZ12
LTFSJ
LTFSH
LTFSG
LTFSM
LTFSK
2.5V • (4095/4096)
2.5V • (4095/4096)
2.5V • (4095/4096)
4.096V • (4095/4096)
4.096V • (4095/4096)
Mid-Scale
Mid-Scale
Zero
Mid-Scale
Zero
Internal
External
Internal
Internal
Internal
12-Bit
12-Bit
12-Bit
12-Bit
12-Bit
2.7V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
±1.5LSB
±1.5LSB
±1.5LSB
±1.5LSB
±1.5LSB
LTC2632-LI12
LTC2632-LI10
LTC2632-LI8
LTFSJ
LTFSQ
LTFSW
2.5V • (4095/4096)
2.5V • (1023/1024)
2.5V • (255/256)
Mid-Scale
Mid-Scale
Mid-Scale
Internal
Internal
Internal
12-Bit
10-Bit
8-Bit
2.7V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
±2.5LSB
±1LSB
±0.5LSB
LTC2632-LX12
LTC2632-LX10
LTC2632-LX8
LTFSH
LTFSP
LTFSV
2.5V • (4095/4096)
2.5V • (1023/1024)
2.5V • (255/256)
Mid-Scale
Mid-Scale
Mid-Scale
External
External
External
12-Bit
10-Bit
8-Bit
2.7V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
±2.5LSB
±1LSB
±0.5LSB
LTC2632-LZ12
LTC2632-LZ10
LTC2632-LZ8
LTFSG
LTFSN
LTFST
2.5V • (4095/4096)
2.5V • (1023/1024)
2.5V • (255/256)
Zero
Zero
Zero
Internal
Internal
Internal
12-Bit
10-Bit
8-Bit
2.7V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
±2.5LSB
±1LSB
±0.5LSB
LTC2632-HI12
LTC2632-HI10
LTC2632-HI8
LTFSM
LTFSS
LTFSY
4.096V • (4095/4096)
4.096V • (1023/1024)
4.096V • (255/256)
Mid-Scale
Mid-Scale
Mid-Scale
Internal
Internal
Internal
12-Bit
10-Bit
8-Bit
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
±2.5LSB
±1LSB
±0.5LSB
LTC2632-HZ12
LTC2632-HZ10
LTC2632-HZ8
LTFSK
LTFSR
LTFSX
4.096V • (4095/4096)
4.096V • (1023/1024)
4.096V • (255/256)
Zero
Zero
Zero
Internal
Internal
Internal
12-Bit
10-Bit
8-Bit
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
±2.5LSB
±1LSB
±0.5LSB
* The temperature grade is identified by a label on the shipping container.
Above options are available in an 8-lead TSOT package (LTC2632xTS8).
LTC2632
4
Rev. C
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2632-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8, LTC2632A-LI12/-LX12/-LZ12 (VFS = 2.5V)
SYMBOL PARAMETER CONDITIONS
LTC2632-8 LTC2632-10 LTC2632-12 LTC2632A-12
UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
DC Performance
Resolution l8 10 12 12 Bits
Monotonicity VCC = 3V, Internal Ref.
(Note 3)
l8 10 12 12 Bits
DNL Differential
Nonlinearity
VCC = 3V, Internal Ref.
(Note 3)
l±0.5 ±0.5 ±1 ±1 LSB
INL Integral
Nonlinearity
VCC = 3V, Internal Ref.
(Note 3)
l±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 ±0.5 ±1.5 LSB
ZSE Zero-Scale
Error
VCC = 3V, Internal Ref.,
Code = 0
l0.5 5 0.5 5 0.5 5 0.5 5 mV
VOS Offset Error VCC = 3V, Internal Ref.
(Note 4)
l±0.5 ±5 ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV
VOSTC VOS
Temperature
Coefficient
VCC = 3V, Internal Ref. ±10 ±10 ±10 ±10 µV/°C
GE Gain Error VCC = 3V, Internal Ref. l0.2 0.8 0.2 0.8 0.2 0.8 0.2 0.8 %FSR
GETC Gain
Temperature
Coefficient
VCC = 3V, Internal Ref.
(Note 9)
C-Grade
H-Grade
10
10
10
10
10
10
10
10
ppm/°C
ppm/°C
Load
Regulation
Internal Ref., Mid-Scale,
VCC = 3V±10%,
–5mA ≤ IOUT ≤ 5mA
VCC = 5V±10%,
–10mA ≤ IOUT ≤ 10mA
l
l
0.009
0.009
0.016
0.016
0.035
0.035
0.064
0.064
0.14
0.14
0.256
0.256
0.14
0.14
0.256
0.256
LSB/mA
LSB/mA
ROUT DC Output
Impedance
Internal Ref., Mid-Scale,
VCC = 3V±10%,
–5mA ≤ IOUT ≤ 5mA
VCC = 5V±10%,
–10mA ≤ IOUT ≤ 10mA
l
l
0.09
0.09
0.156
0.156
0.09
0.09
0.156
0.156
0.09
0.09
0.156
0.156
0.09
0.09
0.156
0.156
Ω
Ω
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOUT DAC Output Span External Reference
Internal Reference
0 to VREF
0 to 2.5
V
V
PSR Power Supply Rejection VCC = 3V±10% or 5V±10% –80 dB
ISC Short-Circuit Output Current (Note 5)
Sinking
Sourcing
VFS = VCC = 5.5V
Zero-Scale; VOUT Shorted to VCC
Full-Scale; VOUT Shorted to GND
l
l
27
–28
48
–48
mA
mA
Power Supply
VCC Positive Supply Voltage For Specified Performance l2.7 5.5 V
ICC Supply Current (Note 6) VCC = 3V, VREF = 2.5V, External Reference
VCC = 3V, Internal Reference
VCC = 5V VREF = 2.5V, External Reference
VCC = 5V, Internal Reference
l
l
l
l
0.3
0.4
0.3
0.4
0.5
0.6
0.5
0.6
mA
mA
mA
mA
ISD Supply Current in Power-Down Mode
(Note 6)
VCC = 5V l0.5 2 µA
LTC2632
5
Rev. C
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2632-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8, LTC2632A-LI12/-LX12/-LZ12 (VFS = 2.5V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Input
Input Voltage Range l1 VCC V
Resistance l120 160 200 kΩ
Capacitance 12 pF
IREF Reference Current, Power-Down Mode DAC Powered Down l0.005 5.0 µA
Reference Output
Output Voltage l1.24 1.25 1.26 V
Reference Temperature Coefficient ±10 ppm/°C
Output Impedance 0.5 kΩ
Capacitive Load Driving 10 µF
Short-Circuit Current VCC = 5.5V, REF Shorted to GND 2.5 mA
Digital I/O
VIH Digital Input High Voltage VCC = 3.6V to 5.5V
VCC = 2.7V to 3.6V
l
l
2.4
2.0
V
V
VIL Digital Input Low Voltage VCC = 4.5V to 5.5V
VCC = 2.7V to 4.5V
l
l
0.8
0.6
V
V
ILK Digital Input Leakage VIN = GND to VCC l±1 µA
CIN Digital Input Capacitance (Note 7) l8 pF
AC Performance
tSSettling Time VCC = 3V (Note 8)
±0.39% (±1LSB at 8 Bits)
±0.098% (±1LSB at 10 Bits)
±0.024% (±1LSB at 12 Bits)
3.5
3.9
4.4
µs
µs
µs
Voltage Output Slew Rate 1.0 V/µs
Capacitive Load Driving 500 pF
Glitch Impulse At Mid-Scale Transition 2.8 nV•s
DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switch 0 to FS 4.5 nV•s
Multiplying Bandwidth External Reference 320 kHz
enOutput Voltage Noise Density At f = 1kHz, External Reference
At f = 10kHz, External Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
180
160
200
180
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Output Voltage Noise 0.1Hz to 10Hz, External Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, External Reference
0.1Hz to 200kHz, Internal Reference
CREF = 0.1µF
30
35
680
730
µVP-P
µVP-P
µVP-P
µVP-P
LTC2632
6
Rev. C
For more information www.analog.com
LTC2632-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8, LTC2632A-LI12/-LX12/-LZ12 (VFS = 2.5V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t1SDI Valid to SCK Setup (Figure 1) l4 ns
t2SDI Valid to SCK Hold (Figure 1) l4 ns
t3SCK High Time (Figure 1) l9 ns
t4SCK Low Time (Figure 1) l9 ns
t5CS/LD Pulse Width (Figure 1) l10 ns
t6LSB SCK High to CS/LD High (Figure 1) l7 ns
t7CS/LD Low to SCK High (Figure 1) l7 ns
t10 CS/LD High to SCK Positive Edge (Figure 1) l7 ns
SCK Frequency 50% Duty Cycle l50 MHz
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2632
7
Rev. C
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2632-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8, LTC2632A-HI12/-HZ12 (VFS = 4.096V)
SYMBOL PARAMETER CONDITIONS
LTC2632-8 LTC2632-10 LTC2632-12 LTC2632A-12
UNITS
MIN
TYP MAX
MIN
TYP MAX MIN TYP MAX MIN TYP MAX
DC Performance
Resolution l8 10 12 12 Bits
Monotonicity VCC = 5V, Internal Ref. (Note 3) l8 10 12 12 Bits
DNL Differential
Nonlinearity
VCC = 5V, Internal Ref. (Note 3) l±0.5 ±0.5 ±1 ±1 LSB
INL Integral
Nonlinearity
VCC = 5V, Internal Ref. (Note 3) l±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 ±0.5 ±1.5 LSB
ZSE Zero-Scale
Error
VCC = 5V, Internal Ref., Code
= 0
l0.5 5 0.5 5 0.5 5 0.5 5 mV
VOS Offset Error VCC = 5V, Internal Ref. (Note 4) l±0.5 ±5 ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV
VOSTC VOS
Temperature
Coefficient
VCC = 5V, Internal Ref. ±10 ±10 ±10 ±10 µV/°C
GE Gain Error VCC = 5V, Internal Ref. l0.2 0.8 0.2 0.8 0.2 0.8 0.2 0.8 %FSR
GETC Gain
Temperature
Coefficient
VCC = 5V, Internal Ref. (Note 9)
C-Grade
H-Grade
10
10
10
10
10
10
10
10
ppm/°C
ppm/°C
Load
Regulation
VCC = 5V±10%, Internal Ref.
Mid-Scale, –10mA ≤ IOUT ≤ 10mA
l0.006 0.01 0.022 0.04 0.09 0.16 0.09 0.16 LSB/
mA
ROUT DC Output
Impedance
VCC = 5V±10%, Internal Ref.
Mid-Scale, –10mA ≤ IOUT ≤ 10mA
l0.09
0.156
0.09
0.156
0.09
0.156
0.09 0.156 Ω
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOUT DAC Output Span External Reference
Internal Reference
0 to VREF
0 to 4.096
V
V
PSR Power Supply Rejection VCC = 5V±10% –80 dB
ISC Short-Circuit Output Current (Note 5)
Sinking
Sourcing
VFS = VCC = 5.5V
Zero-Scale; VOUT Shorted to VCC
Full-Scale; VOUT Shorted to GND
l
l
27
–28
48
–48
mA
mA
Power Supply
VCC Positive Supply Voltage For Specified Performance l4.5 5.5 V
ICC Supply Current (Note 6) VCC = 5V, VREF = 4.096V, External Reference
VCC = 5V, Internal Reference
l
l
0.4
0.5
0.6
0.7
mA
mA
ISD Supply Current in Power-Down Mode
(Note 6)
VCC = 5V l0.5 2 µA
LTC2632
8
Rev. C
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2632-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8, LTC2632A-HI12/-HZ12 (VFS = 4.096V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Input
Input Voltage Range l1 VCC V
Resistance l120 160 200 kΩ
Capacitance 12 pF
IREF Reference Current, Power-Down Mode DAC Powered Down l0.005 5.0 µA
Reference Output
Output Voltage l2.032 2.048 2.064 V
Reference Temperature Coefficient ±10 ppm/°C
Output Impedance 0.5 kΩ
Capacitive Load Driving 10 µF
Short-Circuit Current VCC = 5.5V; REF Shorted to GND 4 mA
Digital I/O
VIH Digital Input High Voltage l2.4 V
VIL Digital Input Low Voltage l0.8 V
ILK Digital Input Leakage VIN = GND to VCC l±1 µA
CIN Digital Input Capacitance (Note 7) l8 pF
AC Performance
tSSettling Time VCC = 5V (Note 8)
±0.39% (±1LSB at 8 Bits)
±0.098% (±1LSB at 10 Bits)
±0.024% (±1LSB at 12 Bits)
3.9
4.1
4.9
µs
µs
µs
Voltage Output Slew Rate 1.0 V/µs
Capacitive Load Driving 500 pF
Glitch Impulse At Mid-Scale Transition 3.0 nV•s
DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switch 0 to FS 6.7 nV•s
Multiplying Bandwidth External Reference 320 kHz
enOutput Voltage Noise Density At f = 1kHz, External Reference
At f = 10kHz, External Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
180
160
250
230
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Output Voltage Noise 0.1Hz to 10Hz, External Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, External Reference
0.1Hz to 200kHz, Internal Reference
CREF = 0.1µF
30
40
680
750
µVP-P
µVP-P
µVP-P
µVP-P
LTC2632
9
Rev. C
For more information www.analog.com
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2632-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8, LTC2632A-HI12/-HZ12 (VFS = 4.096V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t1SDI Valid to SCK Setup (Figure 1) l4 ns
t2SDI Valid to SCK Hold (Figure 1) l4 ns
t3SCK High Time (Figure 1) l9 ns
t4SCK Low Time (Figure 1) l9 ns
t5CS/LD Pulse Width (Figure 1) l10 ns
t6LSB SCK High to CS/LD High (Figure 1) l7 ns
t7CS/LD Low to SCK High (Figure 1) l7 ns
t10 CS/LD High to SCK Positive Edge (Figure 1) l7 ns
SCK Frequency 50% Duty Cycle l50 MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are with respect to GND
Note 3: Linearity and monotonicity are defined from code kL to code 2N–1,
where N is the resolution and kL is given by kL = 0.016•(2N/VFS), rounded to
the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity is
defined from code 26 to code 4,095. For VFS = 4.096V and N = 12, kL = 16
and linearity is defined from code 16 to code 4,095.
Note 4: Inferred from measurement at code 16 (LTC2632-12), code 4
(LTC2632-10) or code 1 (LTC2632-8), and at full-scale.
Note 5: This IC includes current limiting that is intended to protect the
device during momentary overload conditions. Junction temperature can
exceed the rated maximum during current limiting. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.
Note 6: Digital inputs at 0V or VCC.
Note 7: Guaranteed by design and not production tested.
Note 8: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND.
Note 9: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 10: CS/LD can be held at high voltage as VCC ramps upon power-up.
LTC2632
10
Rev. C
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
INL vs Temperature DNL vs Temperature
Reference Output Voltage
vs Temperature
Settling to ±1LSB Rising Settling to ±1LSB Falling
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
TA = 25°C, unless otherwise noted. LTC2632-L12 (Internal Reference, VFS = 2.5V)
CODE
0
INL (LSB)
1.0
0.5
0
–0.5
–1.0 1024 3072
2632 G01
40952048
VCC = 3V
CODE
0
DNL (LSB)
1.0
0.5
0
–0.5
–1.0 1024 3072
2632 G02
40952048
VCC = 3V
2µs/DIV
CS/LD
5V/DIV
VOUT
1LSB/DIV
2632 G06
1/4 SCALE TO
3/4 SCALE STEP
VCC = 3V,
VFS = 2.5V
RL = 2k,
CL = 100pF
AVERAGE OF
256 EVENTS
3.3µs
2µs/DIV
CS/LD
5V/DIV
VOUT
1LSB/DIV
2632 G07
4.4µs
3/4 SCALE TO
1/4 SCALE STEP
VCC = 3V,
VFS = 2.5V
RL = 2k,
CL = 100pF
AVERAGE OF
256 EVENTS
TEMPERATURE (°C)
–50
INL (LSB)
1.0
0.5
0
–0.5
–1.0 –25 125100755025
2632 G03
1500
VCC = 3V
INL (POS)
INL (NEG)
TEMPERATURE (°C)
–50
DNL (LSB)
1.0
0.5
0
–0.5
–1.0 –25 125100755025
2632 G04
1500
VCC = 3V
DNL (POS)
DNL (NEG)
TEMPERATURE (°C)
–50
VREF (V)
1.260
1.255
1.250
1.245
1.240 –25 125100755025
2632 G05
1500
VCC = 3V
LTC2632
11
Rev. C
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted. LTC2632-H12 (Internal Reference, VFS = 4.096V)
INL vs Temperature DNL vs Temperature
Reference Output Voltage
vs Temperature
Settling to ±1LSB Rising Settling to ±1LSB Falling
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
CODE
0
INL (LSB)
1.0
0.5
0
–0.5
–1.0 1024 3072
2632 G08
40952048
VCC = 5V
CODE
0
DNL (LSB)
1.0
0.5
0
–0.5
–1.0 1024 3072
2632 G09
40952048
VCC = 5V
2µs/DIV
CS/LD
5V/DIV
VOUT
1LSB/DIV
2632 G13
4.1µs
1/4 SCALE TO
3/4 SCALE STEP
VCC = 3V,
VFS = 4.095V
RL = 2k,
CL = 100pF
AVERAGE OF
256 EVENTS
2µs/DIV
CS/LD
5V/DIV
VOUT
1LSB/DIV
2632 G14
4.9µs
3/4 SCALE TO
1/4 SCALE STEP
VCC = 5V,
VFS = 4.095V
RL = 2k,
CL = 100pF
AVERAGE OF
256 EVENTS
TEMPERATURE (°C)
–50
INL (LSB)
1.0
0.5
0
–0.5
–1.0 –25 125100755025
2632 G10
1500
VCC = 5V
INL (POS)
INL (NEG)
TEMPERATURE (°C)
–50
DNL (LSB)
1.0
0.5
0
–0.5
–1.0 –25 125100755025
2632 G11
1500
VCC = 5V
DNL (POS)
DNL (NEG)
TEMPERATURE (°C)
–50
VREF (V)
2.068
2.058
2.048
2.038
2.028 –25 125100755025
2632 G12
1500
VCC = 5V
LTC2632
12
Rev. C
For more information www.analog.com
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
Load Regulation Current Limiting Offset Error vs Temperature
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2632-10
LTC2632-8
LTC2632
CODE
0
INL (LSB)
1.0
0.5
0
–0.5
–1.0 256 768
2632 G15
1023512
VCC = 3V
VFS = 2.5V
INTERNAL REF
CODE
0
DNL (LSB)
1.0
0.5
0
–0.5
–1.0 256 768
2632 G16
1023512
VCC = 3V
VFS = 2.5V
INTERNAL REF
CODE
0
INL (LSB)
0.50
0.25
0
–0.25
–0.50 64 192
2632 G17
255128
VCC = 3V
VFS = 2.5V
INTERNAL REF
CODE
0
DNL (LSB)
0.50
0.25
0
–0.25
–0.50 64 192
2632 G18
255128
VCC = 3V
VFS = 2.5V
INTERNAL REF
IOUT (mA)
–30
∆VOUT (mV)
10
6
2
8
4
0
–4
–2
–8
–6
–10 –20 –10 20
2632 G19
30100
INTERNAL REFERENCE
CODE = MID-SCALE
VCC = 5V (LTC2632-H)
VCC = 5V (LTC2632-L)
VCC = 3V (LTC2632-L)
IOUT (mA)
–30
∆VOUT (V)
0.20
0.15
0.05
0.10
0
–0.05
–0.15
–0.10
–0.20 –20 –10 20
2632 G20
30100
INTERNAL REFERENCE
CODE = MID-SCALE
VCC = 5V (LTC2632-H)
VCC = 5V (LTC2632-L)
VCC = 3V (LTC2632-L)
TEMPERATURE (°C)
–50
3
2
1
0
–1
–2
–3 –25 125100755025
2632 G21
1500
LTC2632
13
Rev. C
For more information www.analog.com
Headroom at Rails
vs Output Current Exiting Power-Down to Mid-Scale
Power-On Reset to Mid-Scale Supply Current vs Logic Voltage
Large-Signal Response Mid-Scale Glitch Impulse Power-On Reset Glitch
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2632
2µs/DIV
VOUT
0.5V/DIV
2632 G22
VFS = VCC = 5V
1/4 SCALE to 3/4 SCALE
2µs/DIV
CS/LD
5V/DIV
VOUT
2mV/DIV
2632 G23
LTC2632-H12, VCC = 5V
3.0nV-s TYP
LTC2632-L12, VCC = 3V
2.8nV-s TYP
200µs/DIV
VOUT
10mV/DIV
VCC
2V/DIV
2632 G24
LTC2632-L
ZERO-SCALE
IOUT (mA)
0
VOUT (V)
5.0
4.0
3.0
4.5
3.5
2.5
1.5
2.0
0.5
1.0
021 3 8
2632 G25
106 974 5
5V SOURCING
5V SINKING
3V (LTC2632-L) SOURCING
3V (LTC2632-L) SINKING
5µs/DIV
VOUTA
0.5V/DIV
CS/LD
5V/DIV
2632 G26
LTC2632-H
VCC = 5V
INTERNAL REF
DAC B IN
POWER-DOWN
MODE
200µs/DIV
VOUT
0.5V/DIV
VCC
2V/DIV
2632 G27
LTC2632-H
LTC2632-L
LOGIC VOLTAGE (V)
0
I
CC
(mA)
1.2
1.0
0.8
0.4
0.6
0.2 21 4
2632 G28
53
VCC = 3V
(LTC2632-L)
VCC = 5V
SWEEP SCK, SDI, CS/LD
BETWEEN
0V AND VCC
LTC2632
14
Rev. C
For more information www.analog.com
TA = 25°C, unless otherwise noted.
LTC2632
TYPICAL PERFORMANCE CHARACTERISTICS
Gain Error vs Reference Input 0.1Hz to 10Hz Voltage Noise
DAC to DAC Crosstalk (Dynamic) Gain Error vs Temperature
Multiplying Bandwidth Noise Voltage vs Frequency
FREQUENCY (Hz)
1k
dB
2
0
–2
–6
–4
–8
–12
–10
–16
–14
–18 100k
2632 G29
1M10k
VCC = 5V
VREF(DC) = 2V
VREF(AC) = 0.2VP-P
CODE = FULL-SCALE
REFERENCE VOLTAGE (V)
1 2.52
GAIN ERROR (%FSR)
0.8
0.4
0.6
0
0.2
–0.4
–0.6
–0.2
–0.8 4.5
2632 G31
5.53.51.5 4 53
VCC = 5.5V
GAIN ERROR OF 2 CHANNELS
1s/DIV
10µV/DIV
2632 G32
VCC = 5V, VFS = 2.5V
CODE = MID-SCALE
INTERNAL REFERENCE
2µs/DIV
VOUT
2mV/DIV
1 DAC
SWITCH 0-FS
2V/DIV
CS/LD
5V/DIV
2632 G33
LTC2632-H12, VCC = 5V
6.7nV-s TYP
TEMPERATURE (°C)
–50
GAIN ERROR (%FSR)
1.0
0.5
0
–0.5
–1.0 –25 125100755025
2634 G34
1500
FREQUENCY (Hz)
100 1k
NOISE VOLTAGE (nV/√Hz)
500
300
400
100
200
0100k
2632 G30
1M10k
VCC = 5V
CODE = MID-SCALE
INTERNAL REFERENCE
LTC2632-H
LTC2632-L
LTC2632
15
Rev. C
For more information www.analog.com
PIN FUNCTIONS
SCK (Pin 1): Serial Interface Clock Input. CMOS and TTL
compatible.
CS/LD (Pin 2): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
SDI into the register. When CS/LD is taken high, SCK
is disabled and the specified command (see Table1) is
executed.
REF (Pin 3): Reference Voltage Input or Output. When
external reference mode is selected, REF is an input (1V ≤
VREF ≤ VCC) where the voltage supplied sets the full-scale
DAC output voltage. When internal reference is selected,
the 10ppm/°C 1.25V (LTC2632-L) or 2.048V (LTC2632-H)
internal reference (half full-scale) is available at the pin.
This output may be bypassed to GND with up to 10µF
(0.1µF is recommended) and must be buffered when driv
-
ing external DC load current.
GND (Pin 4): Ground.
VOUT A, VOUT B (Pins 5, 6): DAC Analog Voltage Output.
VCC (Pin 7): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V
(LTC2632-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2632-H). Bypass
to GND with a 0.1µF capacitor.
SDI (Pin 8): Serial Interface Data Input. Data on SDI
is clocked into the DAC on the rising edge of SCK. The
LTC2632 accepts input word lengths of either 24 or 32
bits.
LTC2632
16
Rev. C
For more information www.analog.com
BLOCK DIAGRAM
TIMING DIAGRAM
REGISTER
INTERNAL
REFERENCE
REGISTER
REGISTER
POWER-ON
RESET
32-BIT SHIFT REGISTER
REGISTER
CONTROL
LOGIC DECODE
SCK
REF
VREF
2632 BD
CS/LD SDI
VOUTA
VCC
VOUTB
DAC A DAC B
SWITCH
GND
SDI
CS/LD
SCK
t2
t10
t5t7
t6
t1
t3t4
1 2 3 23 24
2632 F01
Figure1. Serial Interface Timing
LTC2632
17
Rev. C
For more information www.analog.com
OPERATION
The LTC2632 is a family of dual voltage output DACs in
an 8-lead TSOT package. Each DAC can operate rail-to-rail
using an external reference, or with its full-scale voltage
set by an integrated reference. Fifteen combinations of
accuracy (12-, 10-, and 8-bit), power-on reset value (zero-
scale, mid-scale in internal reference mode, or mid-scale
in external reference mode), and full-scale voltage (2.5V
or 4.096V) are available. The LTC2632 is controlled using
a 3-wire SPI/MICROWIRE compatible interface.
Power-On Reset
The LTC2632-HZ/LTC2632-LZ clear the output to zero-
scale when power is first applied, making system initial-
ization consistent and repeatable.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2632 con-
tains circuitry to reduce the power-on glitch: the analog
output typically rises less than 10mV above zero-scale
during power-on if the power supply is ramped to 5V in
1ms or more. In general, the glitch amplitude decreases as
the power supply ramp time is increased. See “Power-On
Reset Glitch” in the Typical Performance Characteristics
section.
The LTC2632-HI/LTC2632-LI/LTC2632-LX provides an
alternative reset, setting the output to mid-scale when
power is first applied. The LTC2632-LI and LTC2632-HI
power-up in internal reference mode, with the output set
to a mid-scale voltage of 1.25V and 2.048V respectively.
The LTC2632-LX powers up in external reference mode,
with the output set to mid-scale of the external refer-
ence. Default reference mode selection is described in
the Reference Modes section.
Power Supply Sequencing
The voltage at REF (Pin 3) must be kept within the range
–0.3V ≤ VREF ≤ VCC + 0.3V (see the Absolute Maximum
Ratings section). Particular care should be taken to
observe these limits during power supply turn-on and
turn-off sequences, when the voltage at VCC is in transition.
Transfer Function
The digital-to-analog transfer function is
VOUT(IDEAL) =k
2
N
⎛
⎝
⎜⎞
⎠
⎟• VREF
where k is the decimal equivalent of the binary DAC
input code, N is the resolution, and V
REF
is either 2.5V
(LTC2632-LI/LTC2632-LX/LTC2632-LZ) or 4.096V
(LTC2632-HI/LTC2632-HZ) when in internal reference
mode, and the voltage at REF when in external reference
mode.
Table1. Command Codes
COMMAND*
C3 C2 C1 C0
0 0 0 0 Write to Input Register n
0 0 0 1 Update (Power-Up) DAC Register n
0 0 1 0 Write to Input Register n, Update (Power-Up) All
0 0 1 1 Write to and Update (Power-Up) DAC Register n
0 1 0 0 Power-Down n
0 1 0 1 Power-Down Chip (All DAC’s and Reference)
0 1 1 0 Select Internal Reference (Power-Up Reference)
0 1 1 1 Select External Reference (Power-Down Internal
Reference)
1 1 1 1 No Operation
*Command codes not shown are reserved and should not be used.
Table2. Address Codes
ADDRESS (n)*
A3 A2 A1 A0
0 0 0 0 DAC A
0 0 0 1 DAC B
1 1 1 1 All DACs
* Address codes not shown are reserved and should not be used.
LTC2632
18
Rev. C
For more information www.analog.com
OPERATION
Serial Interface
The CS/LD input is level triggered. When this input is
taken low, it acts as a chip-select signal, enabling the
SDI and SCK buffers and the input shift register. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded first; then the 4-bit
DAC address, A3-A0; and finally the 16-bit data word.
The data word comprises the 12-, 10- or 8-bit input code,
ordered MSB-to-LSB, followed by 4, 6 or 8 don’t-care bits
(LTC2632-12, LTC2632-10 and LTC2632-8 respectively;
see Figure2). Data can only be transferred to the device
when the CS/LD signal is low, beginning on the first rising
edge of SCK. SCK may be high or low at the falling edge
of CS/LD. The rising edge of CS/LD ends the data transfer
and causes the device to execute the command specified
in the 24-bit input sequence. The complete sequence is
shown in Figure3a.
The command (C3-C0) and address (A3-A0) assignments
are shown in Tables 1 and 2. The first four commands in
Table1 consist of write and update operation. A Write
operation loads a 16-bit data word from the 24-bit shift
register into the input register of the selected DAC, n. An
Update operation copies the data word from the input
register to the DAC register. Once copied into the DAC
register, the data word becomes the active 12-, 10-, or
8-bit input code, and is converted to an analog voltage at
the DAC output. Write to and Update combines the first
two commands. The Update operation also powers up the
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
While the minimum input sequence is 24 bits, it may
optionally be extended to 32 bits to accommodate micro-
processors that have a minimum word width of 16 bits (2
bytes). To use the 32-bit width, 8 don’t-care bits are trans-
ferred to the device first, followed by the 24-bit sequence
described. Figure3b shows the 32-bit sequence.
The 16-bit data word is ignored for all commands that do
not include a Write operation.
2632 F02
C3 C2 C1 C0
COMMAND
INPUT WORD (LTC2632-12)
INPUT WORD (LTC2632-10)
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
ADDRESS DATA (12 BITS + 4 DON’T-CARE BITS)
C3 C2 C1 C0
COMMAND
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X
ADDRESS DATA (10 BITS + 6 DON’T-CARE BITS)
C3 C2 C1 C0
COMMAND
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 XX X X X X X X
ADDRESS
MSB LSB
MSB LSB
MSB LSB
DATA (8 BITS + 8 DON’T-CARE BITS)
INPUT WORD (LTC2632-8)
Figure2. Command and Data Input Format
LTC2632
19
Rev. C
For more information www.analog.com
OPERATION
Reference Modes
For applications where an accurate external reference
is not available, nor desirable due to limited space, the
LTC2632 has a user-selectable, integrated reference. The
integrated reference voltage is internally amplified by 2x
to provide the full-scale DAC output voltage range. The
LTC2632-LI/LTC2632-LX/LTC2632-LZ provides a full-
scale output of 2.5V. The LTC2632-HI/LTC2632-HZ pro-
vides a full-scale output of 4.096V. The internal reference
can be useful in applications where the supply voltage is
poorly regulated. Internal reference mode can be selected
by using command 0110b, and is the power-on default
for LTC2632-HZ/LTC2632-LZ, as well as for LTC2632-HI/
LTC2632-LI.
The 10ppm/°C, 1.25V (LTC2632-LI/LTC2632-LX/
LTC2632-LZ) or 2.048V (LTC2632-HI/LTC2632-HZ) inter-
nal reference is available at the REF pin. Adding bypass
capacitance to the REF pin will improve noise perfor-
mance; 0.1µF is recommended, and up to 10µF can be
driven without oscillation. This output must be buffered
when driving an external DC load current.
Alternatively, the DAC can operate in external reference
mode using command 0111b. In this mode, an input
voltage supplied externally to the REF pin provides the
reference (1V ≤ V
REF
≤ V
CC
) and the supply current is
reduced. The external reference voltage supplied sets the
full-scale DAC output voltage. External reference mode is
the power-on default for the LTC2632-LX.
The reference mode of LTC2632-HZ/LTC2632-LZ/
LTC2632-HI/LTC2632-LI (internal reference power-on
default), can be changed by software command after
power-up. The same is true for the LTC2632-LX (external
reference power-on default).
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than two DAC outputs are needed. When in power-down,
the buffer amplifiers, bias circuits, and integrated ref-
erence circuits are disabled, and draw essentially zero
current. The DAC outputs are put into a high-impedance
state, and the output pins are passively pulled to ground
through individual 200k resistors. Input and DAC-register
contents are not disturbed during power-down.
Either channel or both channels can be put into power-
down mode by using command 0100b in combination
with the appropriate DAC address (n). The supply cur-
rent is reduced approximately 30% for each DAC powered
down. The integrated reference is automatically powered
down when external reference is selected using command
0111b. In addition, all the DAC channels and the inte-
grated reference together can be put into power-down
mode using power-down chip command 0101b. When
the integrated reference is in power-down mode, the REF
pin becomes high impedance (typically > 1GΩ). For all
power-down commands the 16-bit data word is ignored.
Normal operation resumes after executing any com-
mand that includes a DAC update (as shown in Table1).
The selected DAC is powered up as its voltage output is
updated. When a DAC which is in a powered-down state
is powered up and updated, normal settling is delayed. If
less than two DACs are in a powered-down state prior to
the update command, the power-up delay time is 10µs.
However, if both DACs and the integrated reference are
powered down, then the main bias generation circuit block
has been automatically shut down in addition to the DAC
amplifiers and reference buffers. In this case, the power
up delay time is 12µs. The power-up of the integrated
reference depends on the command that powered it down.
If the reference is powered down using the select external
reference command (0111b), then it can only be pow-
ered back up using select internal reference command
(0110b). However, if the reference was powered down
using power-down chip command (0101b), then in addi-
tion to the select internal reference command (0110b),
any command that powers up the DACs will also power-up
the integrated reference.
LTC2632
20
Rev. C
For more information www.analog.com
Voltage Output
The LTC2632’s integrated rail-to-rail amplifier has guar-
anteed load regulation when sourcing or sinking up to
10mA at 5V, and 5mA at 3V.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load current. The measured change in output voltage per
change in forced load current is expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to ohms. The amplifier’s DC output
impedance is 0.1Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 50Ω typical channel resistance of the output devices
(e.g., when sinking 1mA, the minimum output voltage is
50Ω • 1mA, or 50mV). See the graph Headroom at Rails
vs Output Current in the Typical Performance Charac-
teristics section.
The amplifier is stable driving capacitive loads of up to
500pF.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is lim-
ited to voltages within the supply range.
Since the analog output of the DAC cannot go below
ground, it may limit for the lowest codes as shown in
Figure 4b. Similarly, limiting can occur near full-scale
when the REF pin is tied to V
CC
. If V
REF
= V
CC
and the
DAC full-scale error (FSE) is positive, the output for the
highest codes limits at VCC, as shown in Figure 4c. No
full-scale limiting can occur if VREF is less than VCC–FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
OPERATION
Board Layout
The PC board should have separate areas for the analog
and digital sections of the circuit. A single, solid ground
plane should be used, with analog and digital signals care-
fully routed over separate areas of the plane. This keeps
digital signals away from sensitive analog signals and
minimizes the interaction between digital ground currents
and the analog section of the ground plane. The resistance
from the LTC2632 GND pin to the ground plane should
be as low as possible. Resistance here will add directly to
the effective DC output impedance of the device (typically
0.1Ω). Note that the LTC2632 is no more susceptible to
this effect than any other parts of this type; on the con-
trary, it allows layout-based performance improvements
to shine rather than limiting attainable performance with
excessive internal resistance.
Another technique for minimizing errors is to use a sepa-
rate power ground return trace on another board layer.
The trace should run between the point where the power
supply is connected to the board and the DAC ground pin.
Thus the DAC ground pin becomes the common point for
analog ground, digital ground, and power ground. When
the LTC2632 is sinking large currents, this current flows
out the ground pin and directly to the power ground trace
without affecting the analog ground plane voltage.
It is sometimes necessary to interrupt the ground plane
to confine digital ground currents to the digital portion of
the plane. When doing this, make the gap in the plane only
as long as it needs to be to serve its purpose and ensure
that no traces cross over the gap.
Bypass capacitors should be placed as close to the pins
as possible with a low impedance path to GND.
LTC2632
21
Rev. C
For more information www.analog.com
OPERATION
Figure3a. . LTC2632-12 24-Bit Load Sequence (Minimum Input Word)
LTC2632-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits;
LTC2632-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits
Figure3b. LTC2632-12 32-Bit Load Sequence
LTC2632-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits;
LTC2632-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits
2632 F03a
C3 C2 C1 C0
COMMAND WORD
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
ADDRESS DATA WORD
SDI
SCK
CS/LD
18 19 20 21 22 23 241 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
24-BIT INPUT WORD
2632 F03b
C3 C2 C1 C0
COMMAND WORD
A3 A2 A1 A0
X X X X X X XX D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
8 DON’T CARE BITS ADDRESS DATA WORD
SDI
SCK
CS/LD
18 19 20 21 22 23 241 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 26 27 28 29 30 31 3225
32-BIT INPUT WORD
LTC2632
22
Rev. C
For more information www.analog.com
OPERATION
2632 F04
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
0V 2,0480 4,095
INPUT CODE
OUTPUT
VOLTAGE
(a)
VREF = VCC
VREF = VCC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
Figure4. Effects of Rail-to-Rail Operation On a DAC Transfer Curve (Shown for 12 Bits)
(a) Overall Transfer Function
(b) Effect of Negative Offset for Codes Near Zero
(c) Effect of Positive Full-Scale Error for Codes Near Full-Scale
PACKAGE DESCRIPTION
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.22 – 0.36
8 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3)
TS8 TSOT-23 0710 REV A
2.90 BSC
(NOTE 4)
0.65 BSC
1.95 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.40
MAX
0.65
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637 Rev A)
LTC2632
23
Rev. C
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 03/11 Revised part numbering. 2 to 9, 17, 19,
24
B 06/17 Removed Note 3. 9
C 07/19 Changed A-Grade INL from ±1LSB to ±1.5LSB. 1 to 4, 7
LTC2632
24
Rev. C
For more information www.analog.com
ANALOG DEVICES, INC. 2011-2019
07/19
www.analog.com
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LTC1662 Dual 10-Bit Ultralow Power VOUT DAC in 8-Lead MSOP
with External Reference
1.5µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2602/LTC2612/
LTC2622
Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP
with External Reference
300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2607/LTC2617/
LTC2627
Dual 16-/14-/12-Bit VOUT DACs in 12-Lead DFN
with External Reference
260µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,
I2C Serial Interface
LTC2630 Single 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference
in SC70
180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
Rail-to-Rail Output, SPI Serial Interface
LTC2631 Single 12-/10-/8-Bit I2C VOUT DACs with 10ppm/°C
Reference in ThinSOT
180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
External REF Mode, Rail-to-Rail Output, I2C Interface
LTC2634 Quad 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference 125µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
External REF Mode, Rail-to-Rail Output, SPI Interface
LTC2636 Octal 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference 125µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
External REF Mode, Rail-to-Rail Output, SPI Interface
LTC2640 Single 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference
in ThinSOT
180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
External REF Mode, Rail-to-Rail Output, SPI Interface
LTC2654 Quad 16-/12-Bit VOUT DACs with ±4 LSB INL, ±1 LSB DNL 4mm × 4mm QFN-20, SSOP-16 Packages, SPI Interface,
Internal 10ppm/°C (Max) Reference
RELATED PARTS
LTC2632 DACs Adjust LTC2755-16 Offset, Amplified with LT1991 PGA to ±5V
–
+
DAC A
DAC D
LTC2755
RCOM1
RIN1
OUTA
–15V
15V
ROFSA
RFBA
RVOSA
GND
IOUT1A
IOUT2A
VDD
5V
REFA
–
+
1/2 LT1469 1/2 LT1469
15V
–15V
DAC C
–15V
30k
LT1634-1.25
SERIAL
BUS
DAC A
CS/LD
SCK
2632 TA02
0.1µF
GND
LTC2632TS8-LI12
REF
5V
5V
VCC
SDI
DAC B
M9
M3
M1 OUT VOUT
±6V
LT1991
REF
VEE
VCC
P1
P3
P9
0.1µF
0.1µF
10V
–10V
DAC B
–
+
0.1µF
LT6240
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF 30pF
30pF
0.1µF