MX93000A FEATURES . On-chip differential line driver . On-chip ALC (automatic level control) . On-chip digital volume control . On-chip 8ohm power amplifier . On-chip programmable receive/transmit gain control . Easy interface to general purpose DSP . Easy Read/Write of control registers by MCU . Easy interface to FAX or Cordless phone . Automatic power-down function . Support 2.048 or 1.536MHz master clock . Support smart power management . 44-pin PQFP/PLCC package . Single +5V power supply PCM CODEC . Support u/A law and 16-bit format linear data . Support switch paths for DAM (digital answering machine) related product applications . Support 2 OPAMPs for RING and POH (parallel telephone off-hook detection) detector or other application . Support power-low and battery-low detectors . Support power on reset function for DSP and MCU use . Support external L.P.F for D/A output path . Support external volume control PIN CONFIGURATION 3 3 3 3 2 2 2 2 2 2 2 3 2 1 0 9 8 7 6 5 4 3 34 35 36 37 38 39 40 41 42 43 44 S V A L L V R U P P X F F D 2 C C D 2 1 1 S V D D 2 S P K N S G N D S P K P C P P C C O N C P C P P R S T P V B O P A WO T B WB S D E N SDATA B SCLK DX DR FS MCLK VDD DGND RINGO RINGN RINGP C V B A T L O U T P L O U T N F I L T ALCC2 ALCC1 ALCRC PGAC AUX1 LIN MIC VREF VAG VBG AGND A V D D 4 4 4 4 4 6 5 4 3 2 1 4 3 2 1 0 7 8 9 10 11 12 13 14 15 16 17 22 21 20 19 18 17 16 15 14 13 12 S V D D 2 S P K N S G N D S V A L L P S R U P P K V X F F P D 2 C C D 2 1 1 C P P C C O N C P C P P R S T P V O P WO B W S D E SDATA N B SCLK DX DR FS MCLK VDD DGND RINGO RINGN RINGP C B A T B V B A T L O U T P L O U T N F I L T ALCC2 ALCC1 ALCRC PGAC AUX1 LIN MIC VREF VAG VBG AGND A V D D 1 2 3 4 5 6 7 8 9 1 1 0 1 1 1 2 2 2 2 2 2 2 2 2 8 9 0 1 2 3 4 5 6 7 8 44 PINS PQFP 44 PINS PLCC P/N:PM0391 39 38 37 36 35 34 33 32 31 30 29 REV. 3.2.1, AUG. 06, 1998 1 MX93000A PRODUCT OVERVIEW The MX93000A PCM CODEC integrates key functions of the analog-front-end of DAM related products into an integrated circuit. The MX93000A PCM CODEC is especially powerful when applied to some DAM models which are intended to meet different countries' specifications in the same system hardware. User can achieve this goal by simply setting control firmware. This benefit will help DAM system makers to save developing time and R&D resources. The MX93000A has one A/D, D/A converter so as to meet the requirement of the DAM application. The on-chip digital filters, which are carried out with 16-bit and 2's complement format, are used to get required frequency response of a PCM CODEC. The CODEC can support 8-bit u/A law and linear data format. For the latter, it is 16-bit format with 14-bit resolution. Before the A/D digitizing the voice-band analog signal into digital format, the analog signal can be processed by a built-in Automatic Level Control (ALC) and PRE-Programmable Gain Amplifier (PRE-PGA). The ALC circuit controls the signal level about 1.2Vpp and AD-PGA can provide 0 ~ 18dB gain to get more larger signal. The PRE-PGA circuit is used to control the gain of different sources like MIC, AUX1 or LIN input. After the digital data is converted into analog signal by D/A converter, a fully differential line driver and speaker driver are supported to drive the telephone line and 8ohm speaker directly without needing any external amplifiers. Besides, the analog signal can be monitored by passing the on-chip volume control or external volume control. The MX93000A supports many switches as well. User can program the control registers of the PCM CODEC to accomplish all specific operations of DAM related products. In order to let MCU (Micro controller) easily Read/Write the control registers of the MX93000A, the sampling clock of the serial control data is clocked by external SCLK clock and synchronized by SDENB, where SDENB signal is coming from the MCU output port by detecting one of the rising edge of external SCLK clock. P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 2 MX93000A BLOCK DIAGRAM ( PQFP ) AUX- I/O AVDD C8 C13 C1 F AX RXA Cor eles sph on e RXA 23 R5 15 VREF AGND 11 12 AVDD AGND DGND 40 41 VDD DGND F ILT AG S WI S WA S WC 16 MI C a b 18 AUX1 b 17 L IN c C4 PCM CODEC S WD A AIN MIC PRE PGA A C14 AG 19 PGAC 20 ALCRC 21 ALCC1 22 ALCC2 9 L OUTP 10 L OUTN AD P GA a d ALC R6 C7 + C6 39 FS 38 DR 37 DSP T ran smi t DATA DX 36 DSP Recei ve DATA SCLK 35 uP Send SCLK SDENB 33 uP Ena ble SDATA S WB S WJ C5 DSP Ma ster Clo ck sig na l MCL K DSP F ram e Sync . si gn al S WE TE LE PHONE LINE I NT ERFACE AVDD C12 28 SVDD1 32 SVDD2 30 SGND 29 8 ohms SPK AOUT LI N DRV S WG A SPKP S PK DRV 31 SPKN 27 VR 25 L PF C2 L PF C1 S WL S WF ATT 1 a B S ERIAL CONTROL UNIT L. P. F. DA P GA ATT 2 VR1 24 C10 SDAT A C9 POW 1.2 5V RING Dete cto r u P chec k RING CPC Dete cto r u P chec k POH 44 43 RINGP 42 RINGO 3 POHP 2 POHN 1 POHO 13 VBG 14 AG 34 POWB 5 BATB 7 RING RINGN S WK S WH BAT 1.2 5V uP T X / RX Co ntr ol DAT A uP ch eck SYST EM Powe r uP ch eck SYST EM Batt ery OR POH 125 ms Powe r-o n L og ic-H DELAY PRST 4 u P/DSP Powe r On Reset C2 AG C3 AUX2 VPO W 26 AUX- I/O AC/DC ADAPT OR F AX RXA VBAT 6 R1 R2 8 BATT ERY POWER R3 R4 Cor eles sph on e RXA P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 3 MX93000A PIN DESCRIPTION SYMBOL PIN POHO POHN POHP PRST O (A) I (A) I (A) O (A) PIN NBR. TYPE (PLCC) 1 (18) 2 (19) 3 (20) 4 (21) POWB VPOW O (A) I (A) 5 (22) 6 (23) BATB VBAT O (A) I (A) 7 (24) 8 (25) LOUTP LOUTN AVDD AGND VBG O (A) O (A) P(A) P(A) O (A) 9 (26) 10 (27) 11 (28) 12 (29) 13 (30) VAG O (A) 14 (31) VREF MIC LIN AUX1 PGAC ALCRC ALCC1 ALCC2 FILT O (A) I (A) I (A) I (A) O (A) O (A) O (A) O (A) I/O (A) 15 (32) 16 (33) 17 (34) 18 (35) 19 (36) 20 (37) 21 (38) 22 (39) 23 (40) DESCRIPTION PQFP the output of POH comparator the inverting input of POH comparator; with 7V surge protection the Non-inverting input of POH comparator; with 7V surge protection power on reset (active high); please refer to the description of power man agement in FUNCTIONAL DESCRIPTION the output of POW comparator; active low the non-inverting input of POW comparator; the voltage is divided from sys tem DC power for comparison with 1.25V ; with 7V surge protection the output of BAT comparator; active low the non-inverting input of BAT comparator; the voltage is divided from bat tery power for comparison with 1.25V ; with 7V surge protection the non-inverting output of LIN-DRV with PGA; see NOTE 4 the inverting output of LIN-DRV with PGA; see NOTE 4 analog power supply; 5V power supply for all internal analog circuits analog power ground band-gap reference; nominal 1.25V and should not be used to sink or source current internal analog signal ground; nominal 2.25V and should not be used to sink or source current voltage reference; nominal 2.25VW and can sink 450uA microphone input with PRE-PGA; see NOTE 1 telephone line signal input with PRE-PGA; see NOTE 1 auxiliary signal input with PRE-PGA; see NOTE 1 programmable gain amplifier (PRE-PGA) offset cancellation capacitor automatic level control (ALC) time constant; see FIG. 9 and FIG. 10 automatic level control (ALC) DC blocking capacitor output automatic level control (ALC) DC blocking capacitor input 1. anti-aliasing filter; 2. as an I/O port for AIN (A/D input) P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 4 MX93000A SYMBOL PIN LPFC1 O (A) PIN NBR. TYPE (PLCC) 24 (41) LPFC2 O (A) 25 (42) AUX2 VR SVDD1 SPKP I/O (A) O (A) P (A) O (A) 26 (43) 27 (44) 28 (1) 29 (2) SGND SPKN P (A) O (A) 30 (3) 31 (4) SVDD2 SDENB P (A) I (D) 32 (5) 33 (6) SDATA I/O (D) 34 (7) SCLK I (D) 35 (8) DX DR FS O (D) I (D) I (D) 36 (9) 37 (10) 38 (11) MCLK I (D) 39 (12) VDD DGND RINGO RINGN RINGP P (D) P (D) O (A) I (A) I (A) 40 (13) 41 (14) 42 (15) 43 (16) 44 (17) DESCRIPTION PQFP the option of the external passive L.P.F.(Low Pass Filter); if the pin is NC then it will by-pass L.P.F, where L.P.F. 3dB point : fc = 1/2 * 3Kohm ( 10%)* CLPFC1 the option of the external passive L.P.F.(Low Pass Filter); if the pin is NC then it will by-pass L.P.F, where L.P.F. 3dB point : fc = 1/2 * 3Kohm ( 10%)* CLPFC2 as an I/O port for SWK and SWH external speaker volume control; use a 20Kohm variable resistor analog power supply; 5V power for SPK-DRV the non-inverting output of SPK-DRV with DA-PGA, ATT1 and ATT2; see NOTE 3 and NOTE 5 analog power ground for SPK-DRV the inverting output of SPK-DRV with DA-PGA, ATT1 and ATT2; see NOTE 3 and NOTE 5 analog power supply; 5V power for SPK-DRV the enabled signal for serial control data; active low; to start to Receive/ Transmit serial control data (A2~A0,D7~D0) Bi-directional serial control data port; it is an interface for Microprocessor to Transmit/Receive serial control data serial control data clock; the clock source of serial control data; from micro processor transmit serial data receive serial data frame sync. Input; 8KHz frame sync. clock for the Transmit/Receive serial data master clock input, if MCLK is continuously high or low then the MX93000A will get into power down mode automatically digital power supply; 5V power supply for all internal digital logic digital power ground the output of RING comparator the inverting input of RING comparator; with 7V surge protection the non-inverting input of RING comparator; with 7V surge protection @ PIN TYPE : "I" : Input Port; "O" : Output Port; "I/O" : Bi-direction Port; "P" : Power "(D)" : Digital Pin; "(A)" : Analog Pin P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 5 MX93000A BASIC COMPONENTS REQUIRED REFERANCE R5 R6 R1,R2 R3,R4 C2 C4, C14 C6 C5 C1,C3,C12, C13 C7 *C8 C9,C10 *VR1 PART 2Kohm 560Kohm 0.1uF 0.1uF 0.22uF 0.1uF 0.1uF 10uF 5000pF 20Kohm DESCRIPTION current limit resistor; to limit MIC bias current; please follow MIC specification ALC release time constant; see FIG. 10 to scale down DC power supply(VPOW) for reference to 1.25V to check power-low to scale down battery power (VBAT) for reference to 1.25V to check battery-low De-couple capacitor ( 0.01~10uF); see FUNCTIONAL DESCRIPTION DC blocking capacitor (0.1~10uF) DC blocking capacitor (0.1~10uF); H.P.F. 3dB point : fc U 1/2 * 4.4Kohm * C6 (0.22uF) = 164Hz DC offset canceling compensative capacitor (0.1~1uF, the larger the better) De-couple capacitor ( 0.1~10uF) ALC attack time constant; see FIG. 9 anti-aliasing capacitor passive L.P.F; 3dB point : fc U 1/2 * 3Kohm * C10 (where C10 = C11) to attenuate the input signal from SWH or SWF, if using digital volume control, then it does not need a resistor between VR and SPKP @ where " * " mark shows that the required component cannot be changed. P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 6 MX93000A FUNCTIONAL DESCRIPTION . Clock Rate (REG4 bit(2)) . The clock rate (MCLK) must be set before using functionality of the MX93000A . Programmable clock rate : 1. 2.048MHz (Frame Sync. 8KHz) 2. 1.536MHz (Frame Sync. 8KHz) . Data Format (REG4 bit(1,0)) . The data format must be set before using functionality of the MX93000A . Programmable Data Format 1. 16-bit linear data format (it can get 14-bit resolution and higher linearity than that of u/a-law data format) 2. 8-bit u-law data format 3. 8-bit a-law data format . PCM CODEC . The block includes A/D & D/A converters and all digital filters 1. A/D & D/A Converters A/D Channel : A. Input Range : 0 ~ 3Vpp (3Vpp as A/D 0dB full swing (0dBFS)) B. Digital Filters : For the purpose of out-of-band noise filtering, IIR digital filters are implemented on the same chip ( >26dB / 60Hz; <1dB / 300Hz ~ 3.4KHz; >14dB / 3.6KHz ~ 4.6KHz; >32dB / >4.6KHz ) D/A Channel : A. Output swing : 0 ~ 3Vpp (3Vpp as D/A 0dB full swing (0dBFS)) B. Digital Filters : a. G.711 and CCITT specifications b. The digital input applied to D/A converter can not be a DC signal other than idle (bits all zero), as limit cycles in the embodiment method at a level of -70dBm will present at the analog output. . Smart Power Management . supports system power supply (Adapter and Battery) detection, the function will work well even under 3V power supply . support the automatic power-down control when MCLK keeps high or low . support sleep-Mode for special application . support power-on reset circuit for uP or DSP 1. Normal Mode (Management Engaged) A. VBAT/VPOW Input Range : 0 ~ AVDD-2Vpp (with 7Vpp surge protection) B. VBAT/VPOW signal is compared to internal 1.25V reference and the result will output to BATB/POWB C. If VBG is ready and BATB or POWB is high, PRST will keep 125ms low and then be set to high (AVDD) as a reset signal when user power-on the MX93000A D. When BATB or POWB is high, PRST will keep high (AVDD) E. When BATB and POWB are low, PRST will keep low F. The block is still functional when the MX93000A gets into power-down mode 2. Sleep Mode (Management Disabled) A. User must scale down AVDD and apply the voltage to VBAT or VPOW so that the MX93000A can get into sleep mode accurately B. PRST will keep 125ms low then be set to high (AVDD) as a reset signal when user power on the MX93000A C. PRST will keep high (AVDD) until the MX93000A is power-recovered D. When setting REG4 bit(6) SLEEP = 1, the MX93000A can get more power saving at power-down P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 7 MX93000A . 3-Channel Input (MIC,AUX1,LIN) with PRE-PGA (Pre-Programmable Gain Control) . Input Range : 0 ~ AVDD-2Vpp . PRE-PGA gain step from 21dB to -15dB (see NOTE 1) . Driving Capacity : more than 400uA at FILT and AUX2 output . Input Impedance : more than 25Kohm . THD : more than 70dB at FILT output . There is only one path which can be selected at the same time . The gain setting of the path will be mapped to the PRE-PGA when the input path is changed . ALC (Automatic Level Control) . Input Range : 0 ~ 1.2Vpp (Loop Gain : 40dB) . Output Characteristic : see FIG. 5 ~ FIG. 7 . Loop Gain : 42dB max (with external RC time constant) . Driving Capacity : more than 400uA at FILT and AUX2 output . THD : more than 40dB at FILT output (Loop Gain : 40dB) VOUT ( mVpp ) 3000mVpp 1000mVpp 10mVpp 1200mVpp VIN ( mVpp ) . A/D PGA . Input Range : 0 ~ AVDD-2Vpp . AD-PGA can support gain step from 18dB to 0dB (18, 8, 4, 0dB) . FILT as I/O Port . Input Range : 0 ~ AVDD-2Vpp . Input Impedance : more than 1Kohm . Output Impedance : less than 1Kohm . Load Capacitance : 5000pF . AUX2 as I/O Port . Input Range : 0 ~ AVDD-2Vpp . Input Impedance : more than 15Kohm . Output Impedance : less than 15Kohm . External passive L.P.F. (Low Pass Filter) . External capacitor (LPFC1 and LPFC2) can be changed to attenuate high frequency noise at SPKP and SPKN output . When external capacitor (LPFC1 and LPFC2) are NC (no connection) then passive L.P.F. will be by-passed . The output of the Line Driver (LOUTP and LOUTN) can be chosen to pass or by-pass the L.P.F. . LPFC1/LPFC2 can be a D/A output pin and the output impedance is around 3Kohm/6Kohm . Line Driver (LIN-DRV) . Not only support the programmable gain from 0 to 22.5dB , but also fully differentially drive 6Vpp over 600ohm . If switches SWE, SWJ, SWK and SWL are opened, then the line driver will be muted to -70dB and power-down automatically 1. output swing : Single Ended (only use LOUTP or LOUTN) : 0 ~ 3Vpp (over 600W load, at LIN-DRV = 0dB) Fully differential (use LOUTP+LOUTN ) : 0 ~ 6Vpp (over 600W load, at LIN-DRV = 0dB) 2. LIN-DRV gain step from 0dB to 22.5dB (see NOTE 4) 3. THD : more than 70dB at 6Vpp output over 600W load . D/A PGA . Input Range : 0 ~ AVDD-2Vpp . DA-PGA can support gain step from 0dB to 9dB (3dB/step) P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 8 MX93000A . Attenuator (ATT1 & ATT2) . Speaker output signal can be attenuated either by internal register or external resistor . If switches SWF and SWH are opened, then attenuator will be muted to -70dB automatically 1. ATT1 (internal register) : 16 steps programmable, from -45dB to 0dB (see NOTE 5) 2. ATT2 (external variable resistor) : from -45 ~ 0dB (determined by external 20Kohm potentiometer) 3. THD : more than 70dB 4. input range for AUX2 : 0 ~ AVDD-2Vpp 5. input impedance for AUX2 : more than 15Kohm . Speaker Driver (SPK-DRV) . If switches SWF and SWH are opened, then SPK-DRV will be power-down automatically 1. max. output swing : 6Vpp with 8W load at fully differential output (SPKP+SPKN) 2. THD : more than 60dB (at 6Vpp/8ohm load) . Voltage Reference (VREF & VAG) . Two 2.25V voltage references are on-chip generated, where VREF is for external circuit use and VAG is for internal circuit use . VREF can be used to bias a microphone, level shift circuit or other applications 1. VREF driving capacity : more than 400uA 2. VREF can be used to provide DC bias to external component . Bandgap Reference (VBG) . A bandgap circuit generates a voltage source (VBG) which is around 1.2V .It is with low temperature coefficient and good power supply rejection . If user changes VBG bypass capacitor (C2) then the MX93000A warm up time will be changed; see The Timing Diagram of CODEC Function . Serial Control Interface . Use SCLK for synchronization with SDATA to read/write the internal control registers . All registers will keep original setting when the MX93000A returns from power-down or sleep mode 1. When SDENB (serial data enabled) signal active low, the MX93000A starts to receive serial control data (SDATA) 2. Set SDENB from low to high when transmitting SDATA is completed 3. SDATA format : 2 addresses from A2 to A0, 8 data from D7 to D0 (A2 is MSB and D0 is LSB) . Two Compartors for System Applications (RING and POH) . To detect Ring and POH (parallel telephone off-hook detection) or other applications 1. input range : 0 ~ AVDD-2Vpp (with 7V surge protection) 2. input impedance : more than 10^12ohm 3. input offset voltage : less than 10mV 4. output impedance : less than 10Kohm 5. slew rate : 3V/us max. P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 9 MX93000A . Switches . There are three registers (REG0, REG3 and REG6) which are used to control all of the switches so that user can direct many different signal paths, for examples : 1. Record signal from MIC and play signal to SPKP/N or play signal to LOUTP/N A. Record signal from MIC or record signal from LIN a. System initialization [ set MIC gain (REG2 bit(3~0)), set LIN gain (REG1 bit(7~4), set ALC gain 0/6dB (REG5 bit(1)) and set A/D-PGA gain (REG6 bit(1,0)) ] b. Record signal from MIC : set REG0 = 0X0048 MIC --> SWA --> PRE-PGA --> SWC (ALC on) --> SWD --> AD-PGA --> PCM CODEC AIN c. Record signal from LIN : set REG0 = 0X00C8 LIN --> SWA --> PRE-PGA --> SWC (ALC on) --> SWD --> AD-PGA --> PCM CODEC AIN B. Play signal to SPKP/N or play signal to LOUTP/N a. System initialization [ set L.P.F. on/off (REG6 bit(5)), set DA-PGA gain (REG6 bit(3,2), set ATT1 gain (REG3 bit(3~0)) and LIN-DRV gain (REG1 bit(3~0)) ] b. Play signal to SPKP/N (use digital volume control) : set REG 0 = 0X0003 PCM CODEC AOUT --> L.P.F. --> SWF --> DA-PGA --> SWG (ATT1) --> SPK-DRV --> SPKP/N c. Play signal to LOUTP/N : set REG 0 = 0X0004 PCM CODEC AOUT --> SWE-->LIN-DRV --> LOUTP/N ( --> SWL (L.P.F.) --> LIN-DRV --> LOUTP/N ) d. Play signal to SPKP/N (use digital volume control) and LOUTP/N : set REG 0 = 0X0007 PCM CODEC AOUT --> L.P.F. --> SWF --> DA-PGA --> SWG (ATT1) --> SPK-DRV --> SPKP/N --> LIN-DRV --> LOUTP/N ( --> SWE --> LIN-DRV --> LOUTP/N ) 2. Room Monitor A. System initialization [ set MIC gain (REG2 bit(3~0)), set ALC gain 0/+6dB (REG5 bit(1)), set LIN-DRV gain (REG1 bit(3~0)), set REG3 bit(6,5) and set REG6 bit(1,0) ] B. Switches path a. Remote Monitor MIC --> SWA --> PRE-PGA --> SWC (ALC on) --> SWJ --> LIN-DRV --> LOUTP/N b. Local Detecting DTMF LIN --> SWI --> AD-PGA --> PCM CODEC AIN . Power Consumption (with 600ohm line load and 8ohm speaker load) Max. Power Consumption Operation Stand-by Power-down Power-down whth SLEEP=1 LIN-DRV Dis/Enable SPK-DRV Dis/Enable Analog circuits Digital circuits Unit Disable Disable Enable Disable Enable Disable Disable Disable Disable Disable Enable Enable Disable Disable 18 18 22 264 268 140 10 4 4 4 4 4 1 1 mA mA uA uA @ Test condition : 1. at LIN-DRV (with 600ohm load) / SPK-DRV (with 8ohm load) full swing (0dBFS) output 2. see LIN-DRV and SPK-DRV Descriptions P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 10 MX93000A CONTROL REGISTERS DEFINITION REGISTER 0 ADDRESS BIT DATA A2 0 A1 0 A0 0 DATA BIT POWER-ON DESCRIPTION D7 0 D6 0 D5 0 SWB SWA D4 0 SWC D3 0 SWD D2 0 SWE D1 0 SWF D0 0 SWG ( SWA ) D(7,6) = (1,1) : path of SWA is "c --> A", PRE-PGA setting follows LIN GAIN SETTING = (1,0) : path of SWA is "b --> A", PRE-PGA setting follows AUX1 GAIN SETTING = (0,1) : path of SWA is "a --> A", PRE-PGA setting follows MIC GAIN SETTING = (0,0) : path of SWA is "d --> A", (GROUNDING to VAG ) ( SWB ) D(5) = (1) : path of SWB is "CLOSE" , D(5) = (0) : path of SWB is "OPEN" ( SWC ) D(4) = (1) : path of SWC is "b --> A", D(4) = (0) : path of SWC is "a --> A" ( SWD ) D(3) = (1) : path of SWD is "CLOSE", D(3) = (0) : path of SWD is "OPEN"; see NOTE 6 ( SWE ) D(2) = (1) : path of SWE is "CLOSE", D(2) = (0) : path of SWE is "OPEN"; see NOTE 7 ( SWF ) D(1) = (1) : path of SWF is "CLOSE ", D(1) = (0) : path of SWF is "OPEN " ( SWG ) D(0) = (1) : path of SWG is "a --> A", ATTENUATOR 1 (ATT1) = (0) : path of SWG is "a --> B", ATTENUATOR 2 (ATT2) REGISTER 1 ADDRESS BIT DATA A2 0 A1 0 A0 1 DATA BIT D7 D6 D5 D4 D3 D2 D1 POWER-ON 0 0 0 0 0 0 0 DESCRIPTION LIN GAIN SETTING ( PRE-PGA ) LIN-DRV GAIN SETTING ( LIN GAIN SETTING ) D(7~4) = (F) ~ (0) : 21dB ~ -15dB ; see NOTE 1 ( LIN-DRV GAIN SETTING ) D(3~0) = (F) ~ (0) : 22.5dB ~ 0dB; see NOTE 4 D0 0 REGISTER 2 ADDRESS BIT DATA A2 0 A1 1 A0 0 DATA BIT D7 D6 D5 D4 POWER-ON 0 0 0 0 DESCRIPTION AUX1 GAIN SETTING ( PRE-PGA ) ( AUX1 GAIN SETTING ) D(7~4) = (F) ~ (0) : 21dB ~ -15dB ( MIC GAIN SETTING ) D(3~0) = (F) ~ (0) : 21dB ~ -15dB P/N:PM0391 D3 D2 D1 D0 0 0 0 0 MIC GAIN SETTING ( PRE-PGA ) ; see NOTE 1 ; see NOTE 1 REV. 3.2.1, AUG. 06, 1998 11 MX93000A REGISTER 3 ADDRESS BIT DATA A2 0 A1 1 A0 1 DATA BIT D7 D6 D5 D4 D3 D2 POWER-ON 0 0 0 0 1 1 DESCRIPTION SWH SWI SWJ SWK ATT1 GAIN SETTING ( SWH ) D(7) = (1) : path of SWH is "CLOSE", D(7) = (0) : path of SWH is "OPEN" ( SWI ) D(6) = (1) : path of SWI is "CLOSE", D(6) = (0) : path of SWI is "OPEN"; see NOTE 6 ( SWJ ) D(5) = (1) : path of SWJ is "CLOSE", D(5) = (0) : path of SWJ is "OPEN"; see NOTE 7 ( SWK ) D(4) = (1) : path of SWK is "CLOSE", D(4) = (0) : path of SWK is "OPEN" ( ATT1 GAIN SETTING ) D(3~0) = (F)~(0) : - 45dB ~ 0dB; see NOTE 5 @ where ATT2 (Attenuator 2) adjusted by VR1 10KW D1 1 D0 1 REGISTER 4 ADDRESS BIT DATA A2 1 A1 0 A0 0 DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 POWER_ON 0 0 0 0 0 0 0 0 DESCRIPTION SLEEP RATE DATA FORMAT ( SLEEP ) D(6) : If the MX93000A original setting is SLEEP = 1, then it will turn off VBG, POW and BAT circuits when the MX93000A gets into power down mode. ( RATE ) D(2) = (1) : master clock (MCLK) uses 1.536MHz, D(2) = (0) : master clock (MCLK) uses 2.048MHz ( DATA FORMAT ) D(1,0) = (1,1),(1,0) : Linear Coder/Decoder (16-bit format) = (0,1) : a-Law Coder/Decoder (8-bit format) = (0,0) : u-LAW Coder/Decoder (8-bit format) @ Linear 16-bit format : 14-bit resolution with 2 LSB = 0 SIGN \ SCALE POSITIVE NEGATIVE MIN 0000 0000 0000 0000 1111 1111 1111 1100 MAX 0111 1111 1111 1100 1000 0000 0000 0000 P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 12 MX93000A REGISTER 5 ADDRESS BIT DATA A2 1 A1 0 A0 1 DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 POWER_ON 0 0 0 0 0 0 0 0 DESCRIPTION ALC1 SPKHI ADA AIADID DAYT ADYT ALC0 TDSPCK D ( 5 ~ 2 and 0 ) : reserved ( ALC1 ) D(7) = (0) : internal ALC available = (1) : external ALC option ( PRE-PGA Output : ALCC1; SWC path "a" Input : ALCC2) ( SPKHI ) D(6) = (0) : SPKP/N can drive 8W load when SPK-DRV turns on D(6) = (1) : SPKP/N appear high impedance (10Kohm) and SPK-DRV will keep a quiescent current when SPK-DRV turns on ( ALC0 ) D(1) = (0) : ALC open loop gain is 38dB; = (1) : ALC open loop gain is 42dB REGISTER 6 ADDRESS BIT DATA A2 1 A1 1 DATA BIT POWER_ON DESCRIPTION D7 D6 0 0 SPK-MUTE A0 0 D5 0 SWL D4 0 D3 D2 D1 D0 0 0 0 0 DA-PGA GAIN AD-PGA GAIN SETTING SETTING ( SPK-MUTE ) D(7) = 1 : force speaker driver to be muted (- 70dBFS), D(7) = 0 : force speaker driver to be un-muted ( SWL ) D(5) = 1 : let D/A output signal go to LIN-DRV with passing through passive L.P.F. = 0 : let D/A output signal go to LIN-DRV with getting around passive L.P.F.; see NOTE 7 ( DA-PGA GAIN SETTING ) D(3,2) = (1,1) ~ (0,0) : 9dB ~ 0dB; 3dB/step; see NOTE 3 ( AD-PGA GAIN SETTING ) D(1,0) = (1,1) ~ (0,0) : 18dB ~ 0dB; see NOTE 2 REGISTER 7 ADDRESS BIT DATA A2 1 A1 1 A0 1 DATA BIT POWER_ON DESCRIPTIN D7 0 D6 0 D5 0 D4 0 D3 0 READ D2 D1 D0 0 0 0 REGISTER ADDRESS ( READ ) D(3) = 1 : read data from Register 0 ~ 7, D(3) = 0 : write data to Register 0 ~ 7 ( REGISTER ADDRESS ) D(2~0) : @ When READ = 1, then a. READ will be cleared automatically b. if next uP SDENB signal active low, the MX93000A will dump out the content of REGISTER ADDRESS through CODEC SDATA interface P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 13 MX93000A SPECIFICATION Absolute Maximum Rating PARAMETER AVDD to AGND VDD to DGND Voltage at any Digital Input or Output Current at any Digital Input or Output Operating Ambient Temperature Range Storage Temperature Range MIN -0.3 -0.3 DGND-0.3 TYP MAX 6.0 6.0 VDD+0.3 8 70 150 UNIT V V V mA O C O C MIN TYP MAX UNIT 4.5 5.0 5.5 V 4 20 mA mA 4 255 mA mA 15 120 20 uA uA uA 0 -65 Lead Temperature ( Soldering, 10 seconds ) Power Supply PARAMETER Power Supply Voltage : Digital and Analog Power Supply Current : Stand-by : Digital Analog Operating : Digital Analog ( see Page 11, 12 ) Power-Down : Digital Analog ( at REG4 bit 6 SLEEP = 0 ) Analog ( at REG4 bit 6 SLEEP = 1 ) Electrical Characteristics ( BOLD characters are guaranteed for AVDD = VDD = 5V5%, temperature = 0 ~ 70OC. Typical specified at AVDD = VDD = 5V, temperature = 25OC. "*" mark : guaranteed by design ) Digital Interface PARAMETER High Level Input Voltage ( VIH ) Low Level Input Voltage ( VIL ) High Level Output Voltage ( VOH ) Low Level Output Voltage ( VOL ) Input Low Current ( IIL ) Input High Current ( IIH ) MIN 2.2 TYP MAX UNIT V 0.6 V V V uA uA 2.4 -10 -10 P/N:PM0391 2 0.4 10 10 REV. 3.2.1, AUG. 06, 1998 14 MX93000A Analog Input Ports PARAMETER MIC / LIN / AUX1 : MIN Input Voltage * Input Capacitance * Input Impedance TYP MAX UNIT 15 Vpp pF Kohm 3.0 20 Analog Output Ports PARAMETER Line Driver : Gain Range MIN TYP MAX from 0 to 22.46 10% 6.0 3.0 Step Variation Fully Differential (LOUTP+LOUTN) Full Swing / with 600ohm load Single Ended (LOUTP) Full Swing / with 600ohm load * External Load Capacitance * Output Impedance dB dB 200 600 Speaker Driver : Fully Differential (SPKP+SPKN) Full Swing / with 8ohm load Single Ended (SPKP) Full Swing / with 8ohm load * External Load Capacitance * Output Impedance the Quiescent current (when REG5 bit(6) SPKHI = 1) UNIT 6.0 3.0 100 8 4 Vpp Vpp pF ohm Vpp Vpp pF ohm mA Analog I/O Ports PARAMETER FILT : as Input Port : MIN * Input Capacitance * Input Impedance TYP MAX 5000 1 UNIT pF Kohm as Output Port : * External Load Capacitance * Output Impedance 5000 1 pF Kohm AUX2 : as Input Port : * Input Capacitance * Input Impedance 15 15 pF Kohm as Output Port : * External Load Capacitance * Output Impedance 15 15 P/N:PM0391 pF Kohm REV. 3.2.1, AUG. 06, 1998 15 MX93000A Gain Variation PARAMETER PRE-PGA : Gain Range MIN Step Size Step Variation TYP MAX UNIT from -14.85 to 20.78 1.5, 3 10% dB dB dB from 0 to 9 +4, +8, +18 10% dB dB dB from 0 to 9 +3 10% dB dB dB AD-PGA : Gain Range Step Size Step Variation DA-PGA : Gain Range Step Size Step Variation Attenuator PARAMETER Attenuator 1 ( Digital Volume ) : Gain Range MIN Step Size Step Variation * Mute Attenuation Attenuator 2 ( External Volume ) : Gain Range the Requirement of External Resistor ( from SPKP to VR ) * Mute Attenuation TYP MAX from -44.64 to 0 -6, -3, -1.5 10% -70 -55 dB dB dB dB 0 10 -70 UNIT dB Kohm dB Bandgap ( VBG pin ) PARAMETER Output Voltage * Output Current MIN 1.231 TYP 1.297 Hi-z MAX 1.362 UNIT V V TYP 2.334 Hi-z MAX 2.451 UNIT V Internal Analog Signal Ground ( VAG pin ) PARAMETER Output Voltage * Output Current MIN 2.217 P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 16 MX93000A Voltage Reference ( VREF pin ) PARAMETER Output Voltage * Output Current MIN 2.1 TYP 2.275 450 MAX 2.45 UNIT V uA MAX 10 7 UNIT mV V ohm Kohm dB MHz V/us V Two Operational Amplifier / Comparators ( RING, POH ) PARAMETER * Input Offset Voltage * Input Voltage * Input Impedance * Output Impedance * Open Loop Gain * Unit Band Gain Width * Slew Rate * Input Comm. Mode Range MIN TYP 10^12 10 78 2 3 3.5 Two Comparators ( POW, BAT ) PARAMETER Comparator Transfer Point * Hysteresis * Output Impedance of POWB and BATB pins MIN 1.231 TYP 1.297 15 MAX 1.362 UNIT V mV Kohm TYP 190 MAX 290 UNIT ms Kohm 10 Power-on Reset Timing ( Test condition : VBG bypass = 0.1uF ) PARAMETER * the Delay of PRST from Low to High * Output Impedance of PRST pin MIN 140 10 P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 17 MX93000A A/D Path Characteristics ( 0dBFS : reference to Fin = 1.02KHz and A/D Input is Full Swing ) PARAMETER Dynamic Range ( at -51dBFS ) THD+N ( at Vin = -6dBFS ) Interchannel Isolation of LIN/MIC/AUX1 ( at Vin = 0dBFS ) Gain Variation ( at Vin = -6dBFS ) Max. Overload Level Frequency Response ( Measure Respone from 60Hz to 4000Hz, see FIG. 3 ) : 60Hz 150Hz 200Hz 300 ~ 3200Hz 3400Hz 3600Hz 3800Hz 4000Hz and Up MIN 76 TYP 77 46 0.1 -0.3 MAX 78 0.3 3.0 -23 -7 -3 -0.8 -26 -8 -4 +0.8 -1.6 -4.5 -10 -45 UNIT dB dB dBFS dBFS Vpp dB dB dB dB dB dB dB dB D/A Path Characteristics ( 0dBFS : referred to Fout = 1.02KHz and D/A Output is Full Swing ) PARAMETER Dynamic Range ( at -51dBFS ) THD+N ( at Vin = -6dBFS ) Gain Variation ( at Vin = -6dBFS ) Out of Band Energy ( with 1.02KHz Image ) : 3.8KHz ~ 20KHz Output Level ( at AUX2 ) Frequency Response ( Measure Respone from 60Hz to 3800Hz, see FIG. 4 ) : 60Hz ~ 300Hz 300Hz ~ 3400Hz 3400Hz ~ 3600Hz 3600Hz ~ 3800Hz P/N:PM0391 MIN 76 TYP 77 46 0.1 MAX 78 -50 dBFS 0.2 0.8 -0.26 0.8 -12.4 UNIT dB dB dBFS dB dB dB dB REV. 3.2.1, AUG. 06, 1998 18 MX93000A Noise ( Test Condition : 1. A/D Input signal is 1.02KHz/0dBFS PARAMETER Idle-Channel Noise ( Input Grounded and Measurement Bandwidth from 0 to 4000Hz ) : A/D Path D/A Path VDD Power Supply Rejection ( A/D & D/A Input Grounded and VDD = 5.0VDC+100mVrms ) : A/D Channel : ( Test Condition 1 ) Fin = 0 ~ 4KHz Fin = 4 ~ 25KHz Fin = 25 ~ 50KHz D/A Channel : ( Test Condition 2 ) Fin = 0 ~ 4KHz Fin = 4 ~ 25KHz Fin = 25 ~ 50KHz AVDD Power Supply Rejection ( A/D & D/A Input Grounded and AVDD = 5.0VDC+100mVrms ) : A/D Channel : ( Test Condition 1 ) Fin = 0 ~ 4KHz Fin = 4 ~ 25KHz Fin = 25 ~ 50KHz D/A Channel : ( Test Condition 2 ) Fin = 0 ~ 4KHz Fin = 4 ~ 25KHz Fin = 25 ~ 50KHz Crosstalk : A/D to D/A ( Test Condition 1 ) D/A to A/D ( Test Condition 2 ) P/N:PM0391 2. D/A Output signal is 1.02KHz/0dBFS ) MIN TYP MAX UNIT -76 -83 dBFS dBFS -54 -80 -82 dBFS dBFS dBFS -65 -80 -95 dBFS dBFS dBFS -72 -85 -87 dBFS dBFS dBFS -41 -53 -60 dBFS dBFS dBFS -94 -95 dBFS dBFS REV. 3.2.1, AUG. 06, 1998 19 MX93000A TIMING DESCRIPTION TIMING 1/Tmck Trmck Tfmck Tfs Tfsh Tdxs Tdrh1 Tdrh2 Tupen1 Tupen2 Tups1 Tups2 Tuph Tcdrd Tupo2i Tcdi2o DESCRIPTION frequency of master clock (from Vmckh1 to next Vmckh1) at RATE = 0 rise time of master clock fall time of master clock from Vmckh1 to Vfsh1 holding time for frame sync. From Vfsh1 to Vfsh2 setting time for CODEC transmit data from Vmckh1(n) to DX(n) data ready holding time for CODEC received data from DR(n) data ready to Vmckh2(n) holding time for CODEC received data from Vmckl(n) to DR(n) ending MIN TYP MAX 1.638 2.048 2.560 from Vsclkh1 to Venl from Vsclkh1 to Venh setting time for uP transmitting SDATA from Vupenl to uP SDATA(n) ready ( @ where Tupen1+Tups1 must < SCLK ) setting time for uP transmitting SDATA from Vsclkh1(n+1) to uP SDATA(n+1) ready holding time for uP transmitting SDATA from Vsclkh1(n+1) to uP SDATA(n) ending from Vsclkh1(n+1) to CODEC reading SDATA(n) 40 40 40 SCLK SCLK SLCK ns ns ns 40 SCLK ns 40 Tups2 ns 20 ns FS 20 ns ns 20 ns 20 ns SCLK ns 20 SCLK FS ns ns ns Tcdo2i Tuprd Tupi2o from Vupenl to uP changing its SDATA interface to input port from Vsclkh1 to CODEC changing its SDATA interface to output port setting time for CODEC transmitting SDATA from Vcdi2o to SDATA(n) ready setting time for CODEC transmitting SDATA from Vsclkh1(n+2) to SDATA(n+1) ready holding time for CODEC transmitting SDATA from SDATA(n) ready to Vsclkh1(n+2) from Venh to CODEC changing its SDATA interface to input port from Vsclkh1(n+1) to uP reading SDATA(n) from Vsclkh1 to uP changing its SDATA interface to output port Vmckh1 Vmckh2 Vmckl Vfsh1 Vsclkh1 Vcdi2o Venh Venl logic high when CODEC MCLK rising logic high when CODEC MCLK falling logic low when CODEC MCLK falling logic high when CODEC FS rising logic high when SCLK rising CODEC changes its SDATA interface to output port logic high when uP SDENB rising logic low when uP SDENB falling Tcds1 Tcds2 Tcdh P/N:PM0391 50 50 UNIT MHz 0 MCLK 110 ns ns ns ns ns 0 ns 150 ns 40 40 40 REV. 3.2.1, AUG. 06, 1998 20 MX93000A TIMING DIAGRAM Master Clock, Frame Sync. & Data Timing Diagram MCLK 1 2 3 4 6 5 7 8 1 0 9 1 2 1 1 1 3 1 5 1 4 1 6 FS MSB u/a-law DR / DX LSB 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 MSB Linear DR / DX LSB 1 Vmckh1 MCLK Vmckh2 Vmckl Tfs FS u-law : H , a-law : L 9 10 11 12 13 Vmckh1 (n) (n+1) 1 2 Tfsh 14 15 16 L Vfsh2 Vfsh1 Tdxs Tdxs DX 1(n) 2 (n+1) Tdrh2 Tdrh1 DR 1 (n) 2 (n+1) Control Registers R/W Timing Diagram CODEC READ SDATA Vscl kh1 n SCLK 1 n+1 n+2 2 3 4 5 6 7 8 9 1 0 1 1 1 2 Tupen1 Venl SDENB Venh Tups1 Tuph Tups2 Tuph uP SDATA interface 1 3Tupen2 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 n+1 n CODEC read SDATA Tcdrd CODEC SDATA interface CODEC WRITE SDATA Vscl kh1 n n+1 n+2 1 2 3 SCLK 4 5 6 7 8 Tupen1 SDENB 1 1 1 2 1 3 Tupen2 Tcds2 Tcdh Tcdo2i A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Tupo2i n uP SDATA interface 1 0 Vcdi2o Tcdi2o Tcds1 CODEC SDATA interface 9 n+1 Tuprd uP read SDATA P/N:PM0391 Tupi2o REV. 3.2.1, AUG. 06, 1998 21 MX93000A The Timing Diagram of CODEC Function tA tB tC tD tE tF tG tH tI tJ VDD AVDD *1 VBG *2 VBG PRST Register R /W power -down MCLK keeps Hi or Lo MCLK VAG Analog Function VBG* 1 : VBG turns on when Codec gets into Power-dow n mode (Hi : Stable, not Hi : Un-stable) VBG* 2 : VBG turns off when Codec gets into SLEEP mode (Hi : Stable, not Hi : Unstable) Register R/W : Gain Pre-setting, Clock Rate and Codec Data Format (Hi : Enable, Lo : Disable) Analog Function : A/D, D/A and Switches (Hi : Enable, Lo : Disable) VAG : 2.25V (Hi : Stable, not Hi : Unstable) The Timing Description of CODEC Function TIMING tA tA-->tB tC tC-->tD tD tD-->tE DESCRIPTION VDD / AVDD U 3.0VDC the charge time of VBG (where VBG bypass cap. = 0.1uF) MCLK started and register Read/Write is enabled the charge time of VAG (where VAG bypass cap. = 0.1uF) All the function of MX93000A is enabled MCLK keeps running tE Power-down started (MCLK keeps High or Low) and register Read/Write is disabled the VBG discharge time (where VBG bypass cap. = 0.1uF) the VAG discharge time (where VAG bypass cap. = 0.1uF) Power-down ended (MCLK starts) MCLK keeps High or Low the charge time of VAG (where VAG bypass cap. = 0.1uF) the charge time of VBG (where VBG bypass cap. = 0.1uF) Analog/Digital function is enabled tE-->tF tE-->tG tI tF-->t I tH-->t I tH-->tJ tK MIN TYP MAX UNIT 140 190 290 ms 1.8 2 0.3 2.4 0.8 400 1.8 500 ms 5 1 ms ms 900 ms ms @ when VBG bypass capacitor (C2) is changed : (see FIG. 13) i. from 0.1uF to 1uF : (tA tB)' U 10 * (tA tB) ii. from 0.1uF to 0.01uF : (tA tB)' U 1/10 * (tA tB) and the SNDR of CODEC about decay 1dB P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 22 MX93000A FIG. 1 MX93000A A/D Linear Format SNDR Characteristic 70 60 SNDR(dB) 50 40 30 20 10 0 -80 -70 -60 -50 -40 Vin(dB) -30 -20 -10 0 -10 0 FIG. 2 MX93000A D/A Linear Format SNDR Characteristic 70 60 SNDR(dB) 50 40 30 20 10 0 -80 -70 -60 -50 -40 Vin(dB) P/N:PM0391 -30 -20 REV. 3.2.1, AUG. 06, 1998 23 MX93000A FIG. 3 MX93000A A/D Frequence Response dB (1.02KHz as 0dB reference) 0 -5 -10 -15 -20 -25 0 500 1000 1500 2000 2500 Frequence(Hz) 3000 3500 4000 3500 4000 FIG. 4 MX93000A D/A Frequence Response dB (1.02KHz as 0dB reference) 2 0 -2 -4 -6 -8 -10 -12 0 500 1000 1500 2000 2500 Frequence(Hz) P/N:PM0391 3000 REV. 3.2.1, AUG. 06, 1998 24 MX93000A FIG. 5 3500 MX93000A ALC (R/C=560K/10uF) Characteristic 42.4dB 40dB 38.4dB VOUT(mVpp) 3000 2500 34.1dB 31dB 2000 1500 1000 PATH : MIC => PRE-PGA(0dB) => ALC => AD-PGA(0dB) => AD 500 0 0 500 1000 1500 2000 VIN(mVpp)/1.02KHz 2500 3000 FIG. 6 MX93000A ALC (R/C=560K/10uF) Characteristic 11/6/97 40 35 GAIN (dB) 30 PATH : MIC => PRE-PGA(0dB) => ALC => AD-PGA(0dB) => AD 25 20 15 10 42.4dB 40dB 38.4dB 34.1dB 31dB 5 0 0 500 1000 1500 2000 VIN(mVpp)/1.02KHz P/N:PM0391 2500 3000 REV. 3.2.1, AUG. 06, 1998 25 MX93000A FIG. 7 SNDR(dB) MX93000A ALC (R/C=560K/10uF) Characteristic 60 31dB 50 34.1dB 40 30 38.4dB 40dB 42.4dB 20 10 PATH : MIC => PRE-PGA(0dB) => ALC => AD-PGA(0dB) => AD 0 0 500 1000 1500 2000 VIN(mVpp)/1.02KHz 2500 3000 FIG. 8 MX93000A ALC (C=10uF) Gain VS Resistor Characteristic 44 42 Gain (dB) 40 40dB 42.4dB 38.4dB 38 36 34.1dB 34 32 30 31dB 0 200 400 600 800 Resistor (K Ohms) P/N:PM0391 1000 1200 REV. 3.2.1, AUG. 06, 1998 26 MX93000A FIG. 9 MX93000A 10 3 ALC Attack Time Characteristic Attack Time(ms) Path : DA => LPFC1 => MIC => ALC(40dB Gain) => AD +18dB(3 => 23.8mVpp) +42dB(3 => 378mVpp) +24dB(3 => 47.5mVpp) +30dB(3 => 94.9mVpp) +36dB(3 => 189mVpp) 10 2 10 1 0 1 2 10 10 Capacitor(uF) 3 10 10 FIG. 10 MX93000A ALC Release Time Release Time(ms) 10 3 Characteristic -42dB(378 => 3mVpp) -36dB(189 => 3mVpp) -30dB(94.9 => 3mVpp) -24dB(47.5 => 3mVpp) -18dB(23.8 => 3mVpp) 10 2 10 1 Path : DA => LPFC1 => MIC => ALC(40dB Gain) => AD 10 2 Resistor(K ohms) P/N:PM0391 10 3 REV. 3.2.1, AUG. 06, 1998 27 MX93000A FIG. 11 MX93000A SPK-DRV Total Harmonic Distortion 10 1 THD(%) 10 0 PATH : AUX2 => SWH => SWG => SPKP/N Vout (SPKP/N) = 2*Vin (AUX2) ( AVDD = VDD = 5VDC, RL = 8.2 ) 10 -1 10 -2 -1 10 0 1 10 Vin(Vpp) 10 FIG. 12 10 THD(%) 10 10 1 0 MX93000A LIN-DRV Total Harmonic Distortion PATH : AUX2 => SWK => LOUTP/N Vout (LOUTP/N) = 2*Vin (AUX2) (AVDD = VDD = 5VDC , RL = 600 ) -1 -2 10 10 -3 -1 10 100 Vin(Vpp) P/N:PM0391 101 REV. 3.2.1, AUG. 06, 1998 28 MX93000A FIG. 13 MX93000A VBG C-t Characteristic 1 0.9 0.8 0.7 C (uF) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 200 400 600 800 1000 t (ms) P/N:PM0391 1200 1400 1600 1800 REV. 3.2.1, AUG. 06, 1998 29 MX93000A NOTE : The BOLD characters denote the MX93000A pin-out and BOLD with Italy characters denote Function Block of the MX93000A NOTE 1 : PRE-PGA gain step; from 20.78dB to -14.85dB 1111 20.78dB 1110 17.89dB 1101 15dB 1100 12dB 1011 9dB 1010 7.5dB 1001 6dB 1000 4.5dB 0111 3.0dB 0110 1.5dB 0101 0dB 0100 -3dB 0011 -6dB 0010 -9dB 0001 -11.93dB 0000 -14.85dB NOTE 2 : AD-PGA gain step; from 18dB to 0dB 11 18dB 10 8dB 01 4dB 00 0dB NOTE 3 : DA-PGA gain step; from 9dB to 0dB; 3dB/step 11 9dB 10 6dB 01 3dB 00 0dB NOTE 4 : LIN-DRV gain step; from 22.46dB to 0dB 1111 22.46dB 1110 21.08dB 1101 19.5dB 1100 18dB 1011 16.5dB 1010 15dB 1001 13.5dB 1000 12dB 0111 10.5dB 0110 9dB 0101 7.5dB 0100 6dB 0011 4.5dB 0010 3dB 0001 1.5dB 0000 0dB 1010 -21dB 1001 -18dB 1000 -15dB NOTE 5 : ATT1 (Attenuator 1) gain step; from -44.64dB to 0dB 1111 -44.64dB 1110 -38.08dB 1101 -32.73dB 1100 -27.14dB 1011 -24dB NOTE 6 : SWD and SWI cannot be turned on simultaneously NOTE 7 : SWE, SWJ and SWL cannot be turned on simultaneously NOTE 8 : " " denotes that user should refer to the description of ELECTRICAL CHARACTERISTICS, TIMING DESCRIPTION and NOTE 1 ~ 5 P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 30 MX93000A Physical Dimensions 44-PIN PQFP Item A B C D E F G H I J K L M N O P Millimeters 13.20 0.20 10.00 0.05 10.00 0.05 13.20 0.20 8.00 [ REF ] 1.00 [ REF ] 1.00 [ REF ] .30 [ TYP. ] .80 [ TYP. ] 1.6 .1 [ TYP. ] 0.80 .1 [ TYP. ] 0.15 [ TYP. ] 0.120 MAX. 2.0 0.15 0.05 MIN. 2.15 0.1 MAX. Inches 0.5196 0.008 0.3937 0.002 0.3937 0.002 0.5196 0.008 0.3149 0.0393 [ REF ] 0.0393 [ REF ] 0.0118 [ TYP. ] 0.0314 [ TYP. ] 0.06629 0.004 0.0314 0.004 0.15 [ TYP. ] 0.0040 MAX. 0.0787 0.00590 0.002 0.0846 0.005 A B 33 23 34 22 E C D 44 12 1 F 11 G H I J N P L M K O NOTE : Each lead centerline is located within .25mm [ .01 inch ] of its true position [ TP ] at a maximum material condition . 44-PIN PLCC A B Item A B C D E F G H I J K L M N Millimeters 17.53 0.12 16.59 0.12 16.59 0.12 17.53 0.12 1.95 4.70 MAX. 2.25 0.25 0.51 MIN. 1.27 [ TYP. ] 0.71 0.1 0.46 0.10 15.50 0.51 0.63 R 0.25 [ TYP. ] 1 6 Inches 0.690 0.005 0.653 0.005 0.653 0.005 0.690 0.005 0.077 0.185 MAX. 0.100 0.010 0.020 MIN. 0.050 [ TYP. ] 0.028 0.004 0.018 0.004 0.610 0.020 0.025 R 0.010 [ TYP. ] 40 44 39 7 13 33 17 29 18 C D 28 E F G N H I J K M L NOTE : Each lead centerline is located within .25mm [ .01 inch ] of its true position [ TP ] at a maximum material condition . P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 31 MX93000A Ordering Information MX 93 MXIC Company Prefix 000A Product Number Family Prefix F C Commercial 0 ~ 70 J Package Type F : PQFP Q : PLCC P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 32 MX93000A ECR March 12, 1998 Ver 3.0 ----- change the specification for Pre-release 1. page4 line22,23 "PGA from 0 to 22.5dB; 1.5dB/step --> see NOTE 4 2. page4 line33,34,35 "PGA from -15 to 21dB;" -->" " 3. page5 line15,16,19,20 "PGA from 0 to 9dB; Attenuator 1 & 2 from 0 to -45dB;"-->" " 4. page8 line13 "from 21dB to -15dB (21, 18, 15, 12, 9, 7.5, 6, 4.5, 3, 0, -3, -6, -9, -12, -15dB)" --> "from 21dB to -15dB (see NOTE 1)" 5. page9 line9 "from 0 to 22.5dB "-->" from 0 to 22.5dB " 6. page9 line14 "from 0dB to 22.5dB (1.5dB/step) "-->" from 0dB to 22.5dB (see NOTE 4)" 7. page9 line23,24 "from -45dB to 0dB (-45, -39, -33, -27, -24, -21, -18, -15, -12, -9, -7.5, -6, -4.5, -3, -1.5, 0dB)" --> "from -45dB to 0dB (see NOTE 5)" 8. change page16,17 and all about LIN-DRV, PRE-PGA and ATT1 gain stage (add an LIN-DRV : Gain Range from "0 ~ 22.5 "dB to "0 ~ 22.46 "dB, Step Variation from "-0.3dB " to " 10%" PRE-PGA : Gain Range from "-15 ~ 22.5 "dB to "-14.85 ~ 20.78 "dB, Step Variation from "-0.3dB" to " 10%" ATT1 : Gain Range from "-45 ~ 0 "dB to "-44.64 ~ 0 "dB, Step Variation from "-0.3dB "to " 10%" 9. page13 "ATT2 (Attenuator 2) -->adjusted by VR1 20Kohm --> "ATT2 (Attenuator 2) -->adjusted by VR1 10Kohm" 10. change page17,18 about VBG, VAG, VREF and Comparator Transfer Point VBG : Output Voltage from "1.16,1.2,1.24" to "1.231,1.297,1.362" add VAG : Output Voltage "2.217,2.334,2.451" VREF : Output Voltage from "2.0,2.25,2.5" to "2.217,2.334,2.451" Comparator Transfer Point from "1.10,1.25,1.40" to "1.231,1.297,1.362" March 17, 1998 Ver 3.1 ----- modify the description of "The Timing Diagram of CODEC Function" 1. change page 23 about register R/W 2. page23 line23 "see FIG. 13" 3. add page 31 FIG.13 "VBG C-t Characteristic" 4. change page 22 "Master Clock, Frame Sync. & Data Timing Diagram" May 8, 1998 Ver 3.2 ----- modify the description of "Pin Description" SVDD2 P (A) 32 (5) analog power ground for SPK-DRV SVDD2 P (A) 32 (5) analog power supply; 5V power for SPK-DRV August 6, 1998 Ver 3.21 ----- modify specification of Vref (Voltage Reference) Voltage Reference ( VREF pin ) PARAMETER Output Voltage MIN 2.1 TYP 2.275 MAX 2.45 UNIT V P/N:PM0391 REV. 3.2.1, AUG. 06, 1998 33 MX93000A MACRONIX INTERNATIONAL CO., LTD. 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