1
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
. Single +5V pow er supply PCM CODEC
. Support u/A law and 16-bit format linear data
. Support switch paths for D AM (digital answering
machine) related product applications
. Support 2 OPAMPs f or RING and POH (par allel
telephone off-hook detection) detector or other
application
. Support pow er-low and battery-low detectors
. Support power on reset function for DSP and MCU
use
. Support external L.P.F f or D/A output path
. Support external volume control
FEATURES
. On-chip diff erential line driv er
. On-chip ALC (automatic level control)
. On-chip digital v olume control
. On-chip 8ohm po wer amplifier
. On-chip prog rammab le receive/tr ansmit gain control
. Easy interface to gener al purpose DSP
. Easy Read/Write of control registers by MCU
. Easy interface to FAX or Cordless phone
. A utomatic power-do wn function
. Support 2.048 or 1.536MHz master clock
. Support smart power management
. 44-pin PQFP/PLCC pac kage
PIN CONFIGURATION
C
P
C
O
RINGP
RINGN
RINGO
DGND
VDD
MCLK
FS
DR
DX
SDATA
S
D
E
N
B
F
I
L
T
S
V
D
D
1
S
V
D
D
2
S
P
K
N
S
G
N
D
S
P
K
P
A
U
X
2
V
RL
P
F
C
2
L
P
F
C
1ALCC2
ALCC1
ALCRC
PGAC
AUX1
LIN
VREF
VAG
VBG
C
P
C
N
C
P
C
P
A
V
D
D
L
O
U
T
N
L
O
U
T
P
V
B
A
T
B
A
T
B
V
P
O
W
P
O
W
B
P
R
S
T
1234567891
01
1
12
13
14
16
17
18
19
20
21
22
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
34
35
37
38
39
40
41
42
43
44
44 PINS P QF P
15
36 SCLK
AGND
MIC
C
P
C
O
RINGP
RINGN
RINGO
DGND
VDD
MCLK
FS
DR
DX
S
D
E
N
B
SDATA
F
I
L
T
S
V
D
D
1
S
V
D
D
2
S
P
K
N
S
G
N
D
S
P
K
P
A
U
X
2
V
RL
P
F
C
2
L
P
F
C
1ALCC2
ALCC1
ALCRC
PGAC
AUX1
LIN
MIC
VREF
VAG
VBG
C
P
C
N
C
P
C
P
AGND
A
V
D
D
L
O
U
T
N
L
O
U
T
P
V
B
A
T
B
A
T
B
V
P
O
W
P
O
W
B
P
R
S
T
1
81
92
72
8
29
30
31
33
35
36
37
38
39
4
0
4
1
4
2
4
3
4
4123456
8
10
11
13
14
15
16
17
44 PINS P LCC
32
9
7
12
2
02
12
22
32
42
52
6
34
SCLK
2
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
PR ODUCT OVERVIEW
The MX93000A PCM CODEC integrates key functions of the analog-front-end of DAM related products into an
integrated circuit. The MX93000A PCM CODEC is especially powerful when applied to some DAM models which are
intended to meet different countries' specifications in the same system hardware. User can achieve this goal by
simply setting control firmware. This benefit will help DAM system makers to save developing time and R&D re-
sources.
The MX93000A has one A/D, D/A conver ter so as to meet the requirement of the DAM application. The on-chip
digital filters, which are carried out with 16-bit and 2's complement format, are used to get required frequency
response of a PCM CODEC . The CODEC can support 8-bit u/A law and linear data f ormat. F or the latter , it is 16-bit
f ormat with 14-bit resolution.
Before the A/D digitizing the voice-band analog signal into digital format, the analog signal can be processed by a
built-in A utomatic Lev el Control (ALC) and PRE-Programmable Gain Amplifier (PRE-PGA). The ALC circuit controls
the signal level about 1.2Vpp and AD-PGA can provide 0 ~ 18dB gain to get more larger signal. The PRE-PGA
circuit is used to control the gain of diff erent sources lik e MIC, AUX1 or LIN input.
After the digital data is converted into analog signal by D/A converter , a fully differential line driver and speaker driver
are suppor ted to dr ive the telephone line and 8ohm speaker directly without needing any exter nal amplifiers. Be-
sides, the analog signal can be monitored b y passing the on-chip v olume control or external volume control.
The MX93000A suppor ts many switches as well. User can program the control registers of the PCM CODEC to
accomplish all specific operations of DAM related products.
In order to let MCU (Micro controller) easily Read/Write the control registers of the MX93000A, the sampling clock of
the serial control data is clocked by external SCLK clock and synchronized by SDENB, where SDENB signal is
coming from the MCU output port by detecting one of the rising edge of e xternal SCLK cloc k.
3
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
SWJ
bA
a
SWC
SWB
AIN
PCM CODE C
BATTERY
POWER
FILT
1.2 5V
1.2 5V POWB
BATB
VBATVPOW
39
37
33
34
36
38
5
7
23
SDENB
SDATA
MCL K
FS
DR
DSP
Recei ve
DATA
DSP
Transmit
DATA
DSP
Frame
Sync.
si gn al
DSP
Ma ster
Clock
sig na l
uP
check
SYSTEM
Battery
uP
check
SYSTEM
Power
uP/DSP
Power On
Reset
uP
TX / R X
Control
DATA
uP
Enable
SD A TA
R3
ALC
R4
AVDD
11
AVDD
AGND
SERIAL
CONTROL
UNIT
125 ms
Power-on
Logic-H
DELAY
PRST 4
R1
R2
86
AC/DC
ADAPTOR
RINGP
RINGN
RINGO
44
VBG
AG
14 AG
24 LPFC1
25 LPFC2
12
C1
C9C10
C3
C8
POHP
3POHN
2
1POHO
VREF
MI C
16
R5 15
C4
MIC
AG
A
c
a
b
AG d
18 AUX1
LIN
17
SWA
PGAC
ALCC2
ALCC1
22
20
21
19
+
R6
ALCRC
C5
C6
C7
SWI
SWD
PRE
PGA
FAX RXA
Cor eles sph on e RX A
AUX-I/O
SWE
SWK
LOUTN
9
10
LIN
DRV
TE LE PH ONE LIN E
INTERFACE
LOUTP
SWF
SPKN
VR
SPKP
27
8 ohms
SPK 29
31
VR1
SPK
DRV ATT2
a
SWG
B
A
AOUT
AD
PGA
SWH
OR
FAX RXA
Cor eles sph on e RX A
AUX-I/O
AUX2
26
13
C2
uP chec k POH
uP chec k RING
RING
Dete ctor
CPC
Dete ctor
41
C13
40
VDD
35
SCLK uP
Send
SCLK
DX
C12
SVDD1
SVDD2
SGND
28
32
30
AVDD
43
42
L.P.F.
DGNDAGND
DGND
SWL
POW
BAT
RING
POH
C14
ATT1
DA
PGA
BLOCK DIAGRAM ( PQFP )
4
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
PIN DESCRIPTION
SYMBOL PIN PIN NBR. DESCRIPTION
TYPE PQFP
(PLCC)
POHO O (A) 1 (18) the output of POH comparator
POHN I (A) 2 (19) the inverting input of POH comparator; with 7V surge protection
POHP I (A) 3 (20) the Non-inv erting input of POH comparator; with 7V surge protection
PRST O (A) 4 (21) po wer on reset (activ e high); please refer to the description of pow er man
agement in FUNCTIONAL DESCRIPTION
PO WB O (A) 5 (22) the output of PO W compar ator; active lo w
VPOW I (A) 6 (23) the non-inverting input of POW comparator; the v oltage is divided from sys
tem DC pow er for comparison with 1.25V ; with 7V surge protection
BATB O (A) 7 (24) the output of BAT comparator; active low
VBAT I (A) 8 (25) the non-in v erting input of BAT comparator; the voltage is divided from bat
tery power f or comparison with 1.25V ; with 7V surge protection
LOUTP O (A) 9 (26) the non-in ve rting output of LIN-DR V with PGA; see NOTE 4
LOUTN O (A) 10 (27) the inverting output of LIN-DR V with PGA; see NO TE 4
AVDD P(A) 11 (28) analog pow er supply; 5V power supply for all internal analog circuits
A GND P(A) 12 (29) analog power g round
VBG O (A) 13 (30) band-gap reference; nominal 1.25V and should not be used to sink or
source current
VAG O (A) 14 (31) internal analog signal ground; nominal 2.25V and should not be used to
sink or source current
VREF O (A) 15 (32) voltage ref erence; nominal 2.25VW and can sink 450uA
MIC I (A) 16 (33) microphone input with PRE-PGA; see NOTE 1
LIN I (A) 17 (34) telephone line signal input with PRE-PGA; see NOTE 1
AUX1 I (A) 18 (35) auxiliary signal input with PRE-PGA; see NO TE 1
PGA C O (A) 19 (36) programmab le gain amplifier (PRE-PGA) offset cancellation capacitor
ALCRC O (A) 20 (37) automatic lev el control (ALC) time constant; see FIG. 9 and FIG. 10
ALCC1 O (A) 21 (38) automatic le vel control (ALC) DC b loc king capacitor output
ALCC2 O (A) 22 (39) automatic le v el control (ALC) DC b locking capacitor input
FILT I/O (A) 23 (40) 1. anti-aliasing filter; 2. as an I/O port for AIN (A/D input)
5
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
SYMBOL PIN PIN NBR. DESCRIPTION
TYPE PQFP
(PLCC)
LPFC1 O (A) 24 (41) the option of the external passive L.P.F.(Low Pass Filter); if the pin is NC then
it will by-pass L.P.F, where L.P.F. 3dB point : fc
= 1/2 * 3K ohm ( 10%)* CLPFC1
LPFC2 O (A) 25 (42) the option of the external passive L.P.F.(Low Pass Filter); if the pin is NC then
it will by-pass L.P.F, where L.P.F. 3dB point : fc
= 1/2 * 3K ohm ( 10%)* CLPFC2
AUX2 I/O (A) 26 (43) as an I/O port f or SWK and SWH
VR O (A) 27 (44) e xternal speak er v olume control; use a 20K ohm v ariable resistor
SVDD1 P (A) 28 (1) analog power supply; 5V power for SPK-DR V
SPKP O (A) 29 (2) the non-inv erting output of SPK-DRV with DA-PGA, ATT1 and ATT2; see
NO TE 3 and NOTE 5
SGND P (A) 30 (3) analog po wer g round f or SPK-DRV
SPKN O (A) 31 (4) the inverting output of SPK-DR V with DA-PGA, ATT1 and ATT2; see NO TE 3
and NO TE 5
SVDD2 P (A) 32 (5) analog power supply; 5V power for SPK-DR V
SDENB I (D) 33 (6) the enabled signal f or serial control data; active low; to start to Receive/
Transmit serial control data (A2~A0,D7~D0)
SD ATA I/O (D) 34 (7) Bi-directional serial control data port; it is an interf ace f or Microprocessor to
Transmit/Receiv e serial control data
SCLK I (D) 35 (8) serial control data clock; the clock source of serial control data; from micro
processor
DX O (D) 36 (9) transmit serial data
DR I (D) 37 (10) receiv e serial data
FS I (D) 38 (11) frame sync. Input; 8KHz frame sync. clock for the Transmit/Receive serial
data
MCLK I (D) 39 (12) master clock input, if MCLK is continuously high or low then the MX93000A
will get into pow er down mode automatically
VDD P (D) 40 (13) digital power supply; 5V pow er supply f or all internal digital logic
DGND P (D) 41 (14) digital pow er ground
RINGO O (A) 42 (15) the output of RING comparator
RINGN I (A) 43 (16) the inv erting input of RING comparator; with 7V surge protection
RINGP I (A) 44 (17) the non-inv erting input of RING comparator; with 7V surge protection
@ PIN TYPE : "I" : Input Port; "O" : Output Port; "I/O" : Bi-direction Port; "P" : Po wer
"(D)" : Digital Pin; "(A)" : Analog Pin
±
±
6
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
BASIC COMPONENTS REQUIRED
REFERANCE PART DESCRIPTION
R5 2Kohm current limit resistor; to limit MIC bias current; please follow MIC specification
R6 560K ohm ALC release time constant; see FIG. 10
R1,R2 to scale down DC power supply(VPO W) for reference to 1.25V to check power-low
R3,R4 to scale down battery power (VBAT) for reference to 1.25V to check battery-low
C2 0.1uF De-couple capacitor ( 0.01~10uF); see FUNCTIONAL DESCRIPTION
C4, C14 0.1uF DC blocking capacitor (0.1~10uF)
C6 0.22uF DC bloc king capacitor (0.1~10uF);
H.P.F. 3dB point : fc ¡Ü 1/2 * 4.4K ohm * C6 (0.22uF) = 164Hz
C5 0.1uF DC offset canceling compensativ e capacitor (0.1~1uF, the larger the better)
C1,C3,C12, 0.1uF De-couple capacitor ( 0.1~10uF)
C13
C7 10uF ALC attack time constant; see FIG. 9
*C8 5000pF anti-aliasing capacitor
C9,C10 passiv e L.P.F; 3dB point : fc ¡Ü 1/2 * 3Kohm * C10 (where C10 = C11)
*VR1 20K ohm to attenuate the input signal from SWH or SWF, if using digital volume control, then it
does not need a resistor between VR and SPKP
@ where " * " mark shows that the required component cannot be changed.
7
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
FUNCTIONAL DESCRIPTION
. Clock Rate (REG4 bit(2))
. The clock rate (MCLK) must be set before using functionality of the MX93000A
. Programmable clock rate :
1. 2.048MHz (Frame Sync. 8KHz)
2. 1.536MHz (Frame Sync. 8KHz)
. Data Format (REG4 bit(1,0))
. The data format must be set bef ore using functionality of the MX93000A
. Programmab le Data Format
1. 16-bit linear data f ormat (it can get 14-bit resolution and higher linearity than that of u/a-la w data format)
2. 8-bit u-law data format
3. 8-bit a-law data format
. PCM CODEC
. The block includes A/D & D/A converters and all digital filters
1. A/D & D/A Conv erters
A/D Channel :
A. Input Range : 0 ~ 3Vpp (3Vpp as A/D 0dB full swing (0dBFS))
B. Digital Filters : F or the purpose of out-of-band noise filtering, IIR digital filters are implemented on the
same chip ( >26dB / 60Hz; <1dB / 300Hz ~ 3.4KHz; >14dB / 3.6KHz ~ 4.6KHz; >32dB / >4.6KHz )
D/A Channel :
A. Output s wing : 0 ~ 3Vpp (3Vpp as D/A 0dB full swing (0dBFS))
B. Digital Filters :
a. G.711 and CCITT specifications
b . The digital input applied to D/A con verter can not be a DC signal other than idle (bits all zero), as
limit cycles in the embodiment method at a level of -70dBm will present at the analog output.
. Smart P o wer Mana gement
. supports system power supply (Adapter and Battery) detection, the function will work well ev en under 3V
pow er supply
. support the automatic power-do wn control when MCLK k eeps high or low
. support sleep-Mode for special application
. support power-on reset circuit for uP or DSP
1. Normal Mode (Management Engaged)
A. VBAT/VPOW Input Range : 0 ~ AVDD-2Vpp (with 7Vpp surge protection)
B. VBAT/VPOW signal is compared to internal 1.25V ref erence and the result will output to BATB/POWB
C . If VBG is ready and BATB or PO WB is high, PRST will k eep 125ms low and then be set to high (AVDD)
as a reset signal when user pow er-on the MX93000A
D. When BATB or PO WB is high, PRST will keep high (AVDD)
E. When BATB and POWB are lo w, PRST will keep low
F. The bloc k is still functional when the MX93000A gets into power-down mode
2. Sleep Mode (Management Disabled)
A. User must scale down AVDD and apply the voltage to VBAT or VPOW so that the MX93000A can get
into sleep mode accurately
B. PRST will keep 125ms low then be set to high (AVDD) as a reset signal when user power on the
MX93000A
C. PRST will keep high (AVDD) until the MX93000A is power-recovered
D. When setting REG4 bit(6) SLEEP = 1, the MX93000A can get more power saving at pow er-do w n
8
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
3000mVpp
VO UT ( m Vpp )
1000mVpp
10mVpp 1200mVpp V IN ( mVpp )
. 3-Channel Input (MIC,AUX1,LIN) with PRE-PGA (Pre-Programmable Gain Contr ol)
. Input Range : 0 ~ AVDD-2Vpp
. PRE-PGA gain step from 21dB to -15dB (see NOTE 1)
. Driving Capacity : more than 400uA at FILT and AUX2 output
. Input Impedance : more than 25Kohm
. THD : more than 70dB at FILT output
. There is only one path which can be selected at the same time
. The gain setting of the path will be mapped to the PRE-PGA when the input path is changed
. ALC (Automatic Le v el Control)
. Input Range : 0 ~ 1.2Vpp (Loop Gain : 40dB)
. Output Characteristic : see FIG. 5 ~ FIG. 7
. Loop Gain : 42dB max (with external RC time constant)
. Driving Capacity : more than 400uA at FILT and AUX2 output
. THD : more than 40dB at FILT output (Loop Gain : 40dB)
. A/D PGA
. Input Range : 0 ~ AVDD-2Vpp
. AD-PGA can support gain step from 18dB to 0dB (18, 8, 4, 0dB)
. FILT as I/O Port
. Input Range : 0 ~ AVDD-2Vpp
. Input Impedance : more than 1Kohm
. Output Impedance : less than 1K ohm
. Load Capacitance : 5000pF
. AUX2 as I/O Port
. Input Range : 0 ~ AVDD-2Vpp
. Input Impedance : more than 15Kohm
. Output Impedance : less than 15Kohm
. External passive L.P.F. (Low Pass Filter)
. External capacitor (LPFC1 and LPFC2) can be changed to attenuate high frequency noise at SPKP and
SPKN output
. When external capacitor (LPFC1 and LPFC2) are NC (no connection) then passiv e L.P.F. will be b y-passed
. The output of the Line Driver (LOUTP and LOUTN) can be chosen to pass or by-pass the L.P.F.
. LPFC1/LPFC2 can be a D/A output pin and the output impedance is around 3K ohm/6Kohm
. Line Driver (LIN-DRV)
. Not only support the programmab le gain from 0 to 22.5dB , b ut also fully differentially drive 6Vpp o v er
600ohm
. If switches SWE, SWJ, SWK and SWL are opened, then the line driver will be muted to -70dB and po w er-do wn
automatically
1. output swing : Single Ended (only use LOUTP or LOUTN) : 0 ~ 3Vpp (ov er 600W load, at LIN-DRV = 0dB)
Fully differential (use LOUTP+LOUTN ) : 0 ~ 6Vpp (over 600W load, at LIN-DRV = 0dB)
2. LIN-DRV gain step from 0dB to 22.5dB (see NOTE 4)
3. THD : more than 70dB at 6Vpp output o v er 600W load
. D/A PGA
. Input Range : 0 ~ AVDD-2Vpp
. D A-PGA can support gain step from 0dB to 9dB (3dB/step)
9
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
. Attenuator (
ATT1
&
ATT2
)
. Speaker output signal can be atten uated either b y internal register or external resistor
. If s witches SWF and SWH are opened, then attenuator will be m uted to -70dB automatically
1. ATT1 (internal register) : 16 steps programmable, from -45dB to 0dB (see NOTE 5)
2. ATT2 (external variable resistor) : from -45 ~ 0dB (determined by e xternal 20Kohm potentiometer)
3. THD : more than 70dB
4. input range f or AUX2 : 0 ~ AVDD-2Vpp
5. input impedance for A UX2 : more than 15Kohm
. Speaker Driver (SPK-DRV)
. If switches SWF and SWH are opened, then SPK-DRV will be pow er-do wn automatically
1. max. output s wing : 6Vpp with 8W load at fully diff erential output (SPKP+SPKN)
2. THD : more than 60dB (at 6Vpp/8ohm load)
. Voltage Reference (VREF & VAG)
. Two 2.25V voltage references are on-chip generated, where VREF is for e xternal circuit use and VA G is
for internal circuit use
. VREF can be used to bias a microphone, le vel shift circuit or other applications
1. VREF driving capacity : more than 400uA
2. VREF can be used to provide DC bias to external component
. Bandgap Ref erence (VBG)
. A bandgap circuit generates a v oltage source (VBG) which is around 1.2V .It is with lo w temper ature
coefficient and good pow er supply rejection
. If user changes VBG bypass capacitor (C2) then the MX93000A warm up time will be changed; see The
Timing Diagram of CODEC Function
. Serial Contr ol Interface
. Use SCLK for synchronization with SDATA to read/write the internal control registers
. All registers will k eep original setting when the MX93000A returns from power-do wn or sleep mode
1. When SDENB (serial data enabled) signal activ e low, the MX93000A starts to receive serial control
data (SD ATA)
2. Set SDENB from low to high when transmitting SDATA is completed
3. SDATA format : 2 addresses from A2 to A0, 8 data from D7 to D0 (A2 is MSB and D0 is LSB)
. Two Compartors for System Applications (RING and POH)
. To detect Ring and POH (parallel telephone off-hook detection) or other applications
1. input range : 0 ~ AVDD-2Vpp (with 7V surge protection)
2. input impedance : more than 10^12ohm
3. input offset v oltage : less than 10mV
4. output impedance : less than 10K ohm
5. slew rate : 3V/us max.
10
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
. Switches
. There are three registers (REG0, REG3 and REG6) which are used to control all of the s witches so that user
can direct many different signal paths, for examples :
1. Record signal from MIC and play signal to SPKP/N or play signal to LOUTP/N
A. Record signal from MIC or record signal from LIN
a. System initialization [ set MIC gain (REG2 bit(3~0)), set LIN gain (REG1 bit(7~4), set ALC gain
0/6dB (REG5 bit(1)) and set A/D-PGA gain (REG6 bit(1,0)) ]
b. Record signal from MIC : set REG0 = 0X0048
MIC --> SWA --> PRE-PGA --> SWC (ALC on) --> SWD --> AD-PGA --> PCM CODEC AIN
c. Record signal from LIN : set REG0 = 0X00C8
LIN --> SWA --> PRE-PGA --> SWC (ALC on) --> SWD --> AD-PGA --> PCM CODEC AIN
B. Pla y signal to SPKP/N or play signal to LOUTP/N
a. System initialization [ set L.P.F. on/off (REG6 bit(5)), set DA-PGA gain (REG6 bit(3,2), set ATT1
gain (REG3 bit(3~0)) and LIN-DRV gain (REG1 bit(3~0)) ]
b . Play signal to SPKP/N (use digital v olume control) : set REG 0 = 0X0003
PCM CODEC AOUT --> L.P.F. --> SWF --> DA-PGA --> SWG (ATT1) --> SPK-DR V --> SPKP/N
c. Play signal to LOUTP/N : set REG 0 = 0X0004
PCM CODEC AOUT --> SWE-->LIN-DRV --> LOUTP/N
( --> SWL (L.P.F.) --> LIN-DRV --> LOUTP/N )
d. Play signal to SPKP/N (use digital volume control) and LOUTP/N : set REG 0 = 0X0007
PCM CODEC AOUT --> L.P.F. --> SWF --> DA-PGA --> SWG (ATT1) --> SPK-DR V --> SPKP/N
--> LIN-DRV --> LOUTP/N
( --> SWE --> LIN-DRV --> LOUTP/N )
2. Room Monitor
A. System initialization [ set MIC gain (REG2 bit(3~0)), set ALC gain 0/+6dB (REG5 bit(1)), set LIN-DRV
gain (REG1 bit(3~0)), set REG3 bit(6,5) and set REG6 bit(1,0) ]
B. Switches path
a. Remote Monitor
MIC --> SWA --> PRE-PGA --> SWC (ALC on) --> SWJ --> LIN-DRV --> LOUTP/N
b. Local Detecting DTMF
LIN --> SWI --> AD-PGA --> PCM CODEC AIN
. Power Consumption (with 600ohm line load and 8ohm speaker load)
Max. Power LIN-DR V SPK-DRV Analog Digital Unit
Consumption Dis/Enable Dis/Enabl e circuits circuits
Operation
Stand-by Disable Disab le 18 4 mA
Disable Disable 18 4 mA
Enable Disable 22 4
Disable Enable 264 4
Enable Enable 268 4
Power-down Disable Disable 140 1 uA
P ow er-down whth SLEEP=1 Disable Disab le 10 1 uA
@ Test condition : 1. at LIN-DRV (with 600ohm load) / SPK-DRV (with 8ohm load) full s wing (0dBFS) output
2. see LIN-DRV and SPK-DRV Descriptions
11
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
CONTROL REGISTERS DEFINITION
REGISTER 0
ADDRESS BIT A2 A1 A0
DATA 0 0 0
D ATA BIT D7 D6 D5 D4 D3 D2 D1 D0
POWER-ON 0 0 0 0 0 0 0 0
DESCRIPTION SWA SWB SWC SWD SWE SWF SWG
( SWA ) D(7,6) = (1,1) : path of SW A is "c --> A", PRE-PGA setting f ollo ws LIN GAIN SETTING
= (1,0) : path of SWA is "b --> A", PRE-PGA setting f ollows AUX1 GAIN SETTING
= (0,1) : path of SWA is "a --> A", PRE-PGA setting f ollows MIC GAIN SETTING
= (0,0) : path of SWA is "d --> A", (GROUNDING to VAG )
( SWB ) D(5) = (1) : path of SWB is "CLOSE" , D(5) = (0) : path of SWB is "OPEN"
( SWC ) D(4) = (1) : path of SWC is "b --> A", D(4) = (0) : path of SWC is "a --> A"
( SWD ) D(3) = (1) : path of SWD is "CLOSE", D(3) = (0) : path of SWD is "OPEN"; see NOTE 6
( SWE ) D(2) = (1) : path of SWE is "CLOSE", D(2) = (0) : path of SWE is "OPEN"; see NOTE 7
( SWF ) D(1) = (1) : path of SWF is "CLOSE ", D(1) = (0) : path of SWF is "OPEN “
( SWG ) D(0) = (1) : path of SWG is "a --> A", ATTENUATOR 1 (ATT1)
= (0) : path of SWG is "a --> B", ATTENUATOR 2 (ATT2)
REGISTER 1
ADDRESS BIT A2 A 1 A0
DATA 0 0 1
D ATA BIT D7 D6 D5 D4 D3 D2 D1 D0
POWER-ON 0 0 0 0 0 0 0 0
DESCRIPTION LIN GAIN SETTING ( PRE-PGA ) LIN-DRV GAIN SETTING
( LIN GAIN SETTING ) D(7~4) = (F) ~ (0) : 21dB ~ -15dB ; see NOTE 1
( LIN-DR V GAIN SETTING ) D(3~0) = (F) ~ (0) : 22.5dB ~ 0dB; see NOTE 4
REGISTER 2
ADDRESS BIT A2 A 1 A0
DATA 0 1 0
D ATA BIT D7 D6 D5 D4 D3 D2 D1 D0
POWER-ON 0 0 0 0 0 0 0 0
DESCRIPTION A UX1 GAIN SETTING ( PRE-PGA ) MIC GAIN SETTING ( PRE-PGA )
( AUX1 GAIN SETTING ) D(7~4) = (F) ~ (0) : 21dB ~ -15dB ; see NOTE 1
( MIC GAIN SETTING ) D(3~0) = (F) ~ (0) : 21dB ~ -15dB ; see NOTE 1
12
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
REGISTER 3
ADDRESS BIT A2 A1 A 0
DATA 0 1 1
D ATA BIT D7 D6 D5 D4 D3 D2 D1 D0
POWER-ON 0 0 0 0 1 1 1 1
DESCRIPTION SWH SWI SWJ SWK ATT1 GAIN SETTING
( SWH ) D(7) = (1) : path of SWH is "CLOSE", D(7) = (0) : path of SWH is "OPEN”
( SWI ) D(6) = (1) : path of SWI is "CLOSE", D(6) = (0) : path of SWI is "OPEN"; see NOTE 6
( SWJ ) D(5) = (1) : path of SWJ is "CLOSE", D(5) = (0) : path of SWJ is "OPEN"; see NOTE 7
( SWK ) D(4) = (1) : path of SWK is "CLOSE", D(4) = (0) : path of SWK is "OPEN”
( ATT1 GAIN SETTING ) D(3~0) = (F)~(0) : - 45dB ~ 0dB; see NOTE 5
@ where ATT2 (Attenuator 2) Þ adjusted b y VR1 10KW
REGISTER 4
ADDRESS BIT A2 A1 A0
DATA 1 0 0
D ATA BIT D7 D6 D5 D4 D3 D2 D1 D0
POWER_ON 0 0 0 0 0 0 0 0
DESCRIPTION SLEEP RATE DATA FORMAT
( SLEEP ) D(6) : If the MX93000A original setting is SLEEP = 1, then it will turn off VBG, POW and BAT
circuits when the MX93000A gets into pow er do wn mode.
( RATE ) D(2) = (1) : master cloc k (MCLK) uses 1.536MHz, D(2) = (0) : master clock (MCLK) uses 2.048MHz
( D ATA FORMAT ) D(1,0) = (1,1),(1,0) : Linear Coder/Decoder (16-bit format)
= (0,1) : a-Law Coder/Decoder (8-bit format)
= (0,0) : u-LAW Coder/Decoder (8-bit format)
@ Linear 16-bit f ormat : 14-bit resolution with 2 LSB = 0
SIGN \ SCALE MIN MAX
POSITIVE 0000 0000 0000 0000 0111 1111 1111 1100
NEGATIVE 1111 1111 1111 1100 1000 0000 0000 0000
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P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
REGISTER 5
ADDRESS BIT A2 A1 A0
DATA 1 0 1
DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
POWER_ON 0 0 0 0 0 0 0 0
DESCRIPTION ALC1 SPKHI ADA AIADID DAYT ADYT ALC0 TDSPCK
D ( 5 ~ 2 and 0 ) : reserve d
( ALC1 ) D(7) = (0) : internal ALC av ailab le
= (1) : external ALC option ( PRE-PGA Output : ALCC1; SWC path "a" Input : ALCC2)
( SPKHI ) D(6) = (0) : SPKP/N can drive 8W load when SPK-DRV turns on
D(6) = (1) : SPKP/N appear high impedance (10K ohm) and SPK-DRV will keep a quiescent current when
SPK-DRV turns on
( ALC0 ) D(1) = (0) : ALC open loop gain is 38dB; = (1) : ALC open loop gain is 42dB
REGISTER 6
ADDRESS BIT A2 A1 A0
DATA 1 1 0
DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
POWER_ON 0 0 0 0 0 0 0 0
DESCRIPTION SPK-MUTE SW L D A-PGA GAIN AD-PGA GAIN
SETTING SETTING
( SPK-MUTE ) D(7) = 1 : force speaker driver to be muted (- 70dBFS), D(7) = 0 : f orce speaker driver to be un-muted
( SWL ) D(5) = 1 : let D/A output signal go to LIN-DR V with passing through passiv e L.P.F.
= 0 : let D/A output signal go to LIN-DR V with getting around passive L.P.F.; see NOTE 7
( D A-PGA GAIN SETTING ) D(3,2) = (1,1) ~ (0,0) : 9dB ~ 0dB; 3dB/step; see NOTE 3
( AD-PGA GAIN SETTING ) D(1,0) = (1,1) ~ (0,0) : 18dB ~ 0dB; see NOTE 2
REGISTER 7
ADDRESS BIT A2 A1 A 0
DATA 1 1 1
D ATA BIT D7 D6 D5 D4 D3 D2 D1 D0
POWER_ON 0 0 0 0 0 0 0 0
DESCRIPTIN READ REGISTER ADDRESS
( READ ) D(3) = 1 : read data from Register 0 ~ 7, D(3) = 0 : write data to Register 0 ~ 7
( REGISTER ADDRESS ) D(2~0) :
@ When READ = 1, then
a. READ will be cleared automatically
b. if next uP SDENB signal active lo w, the MX93000A will dump out the content of REGISTER ADDRESS
through CODEC SDATA interface
14
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
SPECIFICATION
Absolute Maximum Rating
PARAMETER MIN TYP MAX UNIT
AVDD to AGND -0.3 6.0 V
VDD to DGND -0.3 6.0 V
Voltage at an y Digital Input or Output DGND-0.3 VDD+0.3 V
Current at any Digital Input or Output 8 mA
Operating Ambient Temperature Range 0 70 OC
Storage T emperature Range -65 150 OC
Lead Temperature ( Soldering, 10 seconds )
P ower Suppl y
PARAMETER MIN TYP MAX UNIT
Power Supply Voltage :
Digital and Analog 4.5 5.0 5.5 V
Power Supply Current :
Stand-by : Digital 4 mA
Analog 20 mA
Operating : Digital 4 mA
Analog ( see P age 11, 12 ) 255 mA
Power-Down : Digital 15 uA
Analog ( at REG4 bit 6 SLEEP = 0 ) 120 uA
Analog ( at REG4 bit 6 SLEEP = 1 ) 20 uA
Electrical Characteristics ( BOLD characters are guaranteed f or AVDD = VDD = 5V±5%, temperature =
0 ~ 70OC. Typical specified at AVDD = VDD = 5V, temperature = 25OC. "*" mark : guaranteed by design )
Digital Interface
PARAMETER MIN TYP MAX UNIT
High Le v el Input Voltage ( VIH ) 2.2 V
Low Le vel Input Voltage ( VIL ) 0.6 V
High Le v el Output Voltage ( VOH ) 2.4 V
Low Level Output V oltage ( VOL ) 0.4 V
Input Low Current ( IIL ) -10 ±210 uA
Input High Current ( IIH ) -10 10 uA
15
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
Analog Input Ports
PARAMETER MIN TYP MAX UNIT
MIC / LIN / AUX1 : Input Voltage 3.0 Vpp
* Input Capacitance 15 pF
* Input Impedance 20 K ohm
Analog Output Ports
PARAMETER MIN TYP MAX UNIT
Line Driver :
Gain Range from 0 dB
to 22.46 dB
Step Variation ±10%
Fully Differential (LOUTP+LOUTN) Full Swing / with 600ohm load 6.0 Vpp
Single Ended (LOUTP) Full Swing / with 600ohm load 3.0 200 Vpp
* External Load Capacitance pF
* Output Impedance 600 ohm
Speaker Driver :
Fully Differential (SPKP+SPKN) Full Swing / with 8ohm load 6.0 Vpp
Single Ended (SPKP) Full Swing / with 8ohm load 3.0 Vpp
* External Load Capacitance 100 pF
* Output Impedance 8 ohm
the Quiescent current (when REG5 bit(6) SPKHI = 1) 4 mA
Analog I/O P orts
PARAMETER MIN TYP MAX UNIT
FILT :
as Input Port : * Input Capacitance 5000 pF
* Input Impedance 1 K ohm
as Output Port :* External Load Capacitance 5000 pF
* Output Impedance 1 K ohm
AUX2 :
as Input Port : * Input Capacitance 15 pF
* Input Impedance 15 K ohm
as Output Port :* External Load Capacitance 15 pF
* Output Impedance 15 K ohm
16
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
Gain Variation
PARAMETER MIN TYP MAX UNIT
PRE-PGA :
Gain Range from -14.85 dB
to 20.78 dB
Step Size 1.5, 3 dB
Step Variation 10%
AD-PGA :
Gain Range from 0 to 9 dB
Step Size +4, +8, +18 dB
Step Variation 10% dB
D A-PGA :
Gain Range from 0 to 9 dB
Step Size +3 dB
Step Variation 10% dB
±±
±
±
±
Attenuator
PARAMETER MIN TYP MAX UNIT
Attenuator 1 ( Digital Volume ) :
Gain Range from -44.64 dB
to 0 dB
Step Size -6, -3, -1.5 dB
Step Variation 10% dB
* Mute Attenuation -70
Attenuator 2 ( External Volume ) :
Gain Range -55 0 dB
the Requirement of External Resistor ( from SPKP to VR ) 10 K o hm
* Mute Attenuation -70 dB
±
Bandgap ( VBG pin )
PARAMETER MIN TYP MAX UNIT
Output Voltage 1.231 1.297 1.362 V
* Output Current Hi-z V
Internal Analog Signal Ground ( VAG pin )
PARAMETER MIN TYP MAX UNIT
Output Voltage 2.217 2.334 2.451 V
* Output Current Hi-z
17
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
Voltage Reference ( VREF pin )
PARAMETER MIN TYP MAX UNIT
Output Voltage 2.1 2.275 2.45 V
* Output Current 450 uA
Two Operational Amplifier / Comparators ( RING, POH )
PARAMETER MIN TYP MAX UNIT
* Input Offset Voltage 10 mV
* Input Voltage 7 V
* Input Impedance 10^12 ohm
* Output Impedance 10 K ohm
* Open Loop Gain 78 dB
* Unit Band Gain Width 2 MHz
* Slew Rate 3 V/us
* Input Comm. Mode Range 3.5 V
Two Comparators ( PO W, BAT )
PARAMETER MIN TYP MAX UNIT
Comparator Transfer Point 1.231 1.297 1.362 V
* Hysteresis 15 mV
* Output Impedance of POWB and BATB pins 10 Kohm
Power-on Reset Timing ( Test condition : VBG bypass = 0.1uF )
PARAMETER MIN TYP MAX UNIT
* the Dela y of PRST from Lo w to High 14 0 190 290 ms
* Output Impedance of PRST pin 10 Kohm
18
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
A/D Path Characteristics ( 0dBFS : reference to Fin = 1.02KHz and A/D Input is Full Swing )
PARAMETER MIN TYP MAX UNIT
Dynamic Range ( at -51dBFS ) 76 7 7 78 dB
THD+N ( at Vin = -6dBFS ) 46 dB
Interchannel Isolation of LIN/MIC/A UX1 ( at Vin = 0dBFS ) 0.1 dBFS
Gain Variation ( at Vin = -6dBFS ) -0.3 0.3 dBFS
Max. Overload Le vel 3.0 Vpp
Frequency Response ( Measure Respone from 60Hz to
4000Hz, see FIG. 3 ) :
60Hz -23 -26 dB
150Hz -7 -8 dB
200Hz -3 -4 dB
300 ~ 3200Hz -0.8 +0.8 dB
3400Hz -1.6 dB
3600Hz -4.5 dB
3800Hz -10 dB
4000Hz and Up -45 dB
D/A Path Characteristics ( 0dBFS : referred to Fout = 1.02KHz and D/A Output is Full Swing )
PARAMETER MIN TYP MAX UNIT
Dynamic Range ( at -51dBFS ) 76 77 78 dB
THD+N ( at Vin = -6dBFS ) 46 dB
Gain Variation ( at Vin = -6dBFS ) 0.1 dBFS
Out of Band Energy ( with 1.02KHz Image ) :
3.8KHz ~ 20KHz -50 dBFS
Output Le v e l ( at AUX2 )
Frequency Response ( Measure Respone from 60Hz to
3800Hz, see FIG. 4 ) :
60Hz ~ 300Hz 0.2 dB
300Hz ~ 3400Hz 0. 8 dB
3400Hz ~ 3600Hz -0.26 0.8 dB
3600Hz ~ 3800Hz -12.4 dB
±
±
19
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
Noise ( Test Condition : 1. A/D Input signal is 1.02KHz/0dBFS 2. D/A Output signal is 1.02KHz/0dBFS )
PARAMETER MIN TYP MAX UNIT
Idle-Channel Noise ( Input Grounded and Measurement
Bandwidth from 0 to 4000Hz ) :
A/D Path -76 dBFS
D/A Path -83 dBFS
VDD Power Supply Rejection ( A/D & D/A Input Grounded
and VDD = 5.0VDC+100mVrms ) :
A/D Channel : ( Test Condition 1 )
Fin = 0 ~ 4KHz -54 dBFS
Fin = 4 ~ 25KHz -80 dBFS
Fin = 25 ~ 50KHz -82 dBFS
D/A Channel : ( Test Condition 2 )
Fin = 0 ~ 4KHz -65 dBFS
Fin = 4 ~ 25KHz -80 dBFS
Fin = 25 ~ 50KHz -95 dBFS
AVDD Power Supply Rejection ( A/D & D/A Input Grounded
and AVDD = 5.0VDC+100mVrms ) :
A/D Channel : ( Test Condition 1 )
Fin = 0 ~ 4KHz -72 dBFS
Fin = 4 ~ 25KHz -85 dBFS
Fin = 25 ~ 50KHz -87 dBFS
D/A Channel : ( Test Condition 2 )
Fin = 0 ~ 4KHz -41 dBFS
Fin = 4 ~ 25KHz -53 dBFS
Fin = 25 ~ 50KHz -60 dBFS
Crosstalk :
A/D to D/A ( Test Condition 1 ) -94 dBFS
D/A to A/D ( Test Condition 2 ) -95 dBFS
20
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
TIMING DESCRIPTION
TIMING DESCRIPTION MIN TYP MAX UNIT
1/Tmck frequency of master clock (from Vmckh1 to ne xt Vmc kh1) 1.638 2.048 2.560 MHz
at RATE = 0
Trmck rise time of master clock 50 ns
Tfmck fall time of master clock 50 ns
Tfs from Vmckh1 to Vfsh1 0 ns
Tfsh holding time f or frame sync. From Vfsh1 to Vfsh2 MCLK ns
Tdxs setting time for CODEC transmit data from Vmckh1(n) 11 0 ns
to DX(n) data ready
Tdrh1 holding time for CODEC receiv ed data from DR(n) data 0 ns
ready to Vmckh2(n)
Tdrh2 holding time for CODEC receiv ed data from Vmc kl(n) 150 ns
to DR(n) ending
Tupen1 from Vsclkh1 to V enl 40 SCLK ns
Tupen2 from Vsclkh1 to V enh 40 SCLK ns
Tups1 setting time for uP transmitting SD ATA from Vupenl to 40 SLCK ns
uP SDATA(n) ready ( @ where Tupen1+Tups1 must < SCLK )
Tups2 setting time for uP transmitting SDATA from Vsclkh1(n+1) to uP 40 SCLK ns
SD ATA(n+1) ready
Tuph holding time f or uP transmitting SD ATA from Vsclkh1(n+1) 40 Tups2 ns
to uP SD ATA(n) ending
Tcdrd from Vsclkh1(n+1) to CODEC reading SDATA(n) 20 ns
Tupo2i from Vupenl to uP changing its SDATA interf ace to input port 40 FS ns
Tcdi2o from Vsclkh1 to CODEC changing its SDATA interface 2 0 ns
to output port
Tcds1 setting time for CODEC transmitting SDATA from Vcdi2o 20 ns
to SD ATA(n) ready
Tcds2 setting time for CODEC transmitting SD ATA from Vsclkh1(n+2) to 20 ns
SD ATA(n+1) ready
Tcdh holding time for CODEC transmitting SDATA from SD ATA(n) SCLK ns
ready to Vsclkh1(n+2)
Tcdo2i from Venh to CODEC changing its SD ATA interface to input port 20 ns
Tuprd from Vsclkh1(n+1) to uP reading SD ATA(n) 40 SCLK ns
Tupi2o from Vsclkh1 to uP changing its SD ATA interf ace to output port 4 0 FS ns
Vmckh1 logic high when CODEC MCLK rising
Vmckh2 logic high when CODEC MCLK falling
Vmckl logic lo w when CODEC MCLK f alling
Vfsh1 logic high when CODEC FS rising
Vsclkh1 logic high when SCLK rising
Vcdi2o CODEC changes its SD ATA interface to output port
Venh logic high when uP SDENB rising
Venl logic lo w when uP SDENB f alling
21
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
TIMING DIAGRAM
Master Clock, Frame Sync. & Data Timing Diagram
1234 678
Tfs Tfsh
Tdxs Tdxs
MCLK
FS
DX
12
12
91
01
11
21
31
41
51
6
1234 56 78
12345678910 11 12 13 14 15 16
MCLK
FS
u/a-law
DR / DX
Linear
DR / DX
DR
12
Tdrh2
Tdrh1
MSB LSB
LSBMSB
Vmckh1 Vm ckh2
Vmckl
Vfsh1
Vfsh2
Vmckh1
(n) (n+1)
(n) (n+1)
(n) (n+1)
5
L
u-law : H , a-law : L
Control Register s R/W Timing Diagram
SCLK
SDENB
1234567
A2 A1 A0 D7 D6 D5 D4 D3 D2 D0
89
1
01
11
21
3
Vsclkh1
uP SDATA
interface
Tupen1
Tcds1
u P read SDATA
Tuprd
CODEC SDATA
interface
Tupen2
CODEC WRITE SDATA
Tcdo2i
Tupi2o
Tcdi2o
Tupo2i
Vcdi2o
Tcdh
n+2
n+1
n+1
SCLK
SDENB
123456789
1
01
11
21
3
Vsclkh1
uP SDATA
interface
Tupen1
Tups1
CO DEC re ad SDATA
CODEC S DATA
interface
Tupen2
CODEC READ SDATA
Tcdrd
Tups2
Venl Venh
Tuph Tuph
n+1
n+2
D1
A2 A1 A0 D7 D6 D5 D4 D3 D2 D0D1
Tcds2
n
n
n
n+1n
22
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
The Timing Diagram of CODEC Function
The Timing Description of CODEC Function
TIMING DESCRIPTION MIN TYP MAX UNIT
tA VDD / AVDD ¡Ü 3.0VDC
tA-->tB the charge time of VBG (where VBG bypass cap . = 0.1uF) 140 190 290 ms
tC MCLK started and register Read/Write is enab led
tC-->tD the charge time of VAG (where VAG bypass cap . = 0.1uF) 1.8 ms
tD All the function of MX93000A is enabled
tD-->tE MCLK keeps running
tE Po wer-do wn started (MCLK k eeps High or Low) and
register Read/Write is disabled
tE-->tF the VBG discharge time (where VBG bypass cap. = 0.1uF) 2 2.4 5 ms
tE-->tG the VA G discharge time (where VAG b ypass cap. = 0.1uF) 0.3 0.8 1 ms
t I Pow er-down ended (MCLK starts)
tF-->t I MCLK keeps High or Lo w
tH-->t I the charge time of VA G (where VAG b ypass cap. = 0.1uF) 1.8 ms
tH-->tJ the charge time of VBG (where VBG bypass cap . = 0.1uF) 400 500 900 ms
tK Analog/Digital function is enabled
@ when VBG bypass capacitor (C2) is changed : (see FIG. 13)
i. from 0.1uF to 1uF : (tA Þ tB)’ ¡Ü 10 * (tA Þ tB)
ii. from 0.1uF to 0.01uF : (tA Þ tB)’ ¡Ü 1/10 * (tA Þ tB) and the SNDR of CODEC about decay 1dB
Register
R / W
tA tB tC tD tE tF tG t I
VBG
MCLK
Analog
Function
VAG
power-down
MCL K keeps Hi or Lo
tJ
VBG
VDD
AVDD
*1
*2
tH
PRST
VBG*1 : VBG turn s on w h en C o dec g ets into Po wer-d own m o de (Hi : Stab le, n o t Hi : Un -stable)
VBG*2 : VBG turn s off w h en Co d ec g ets into S LE EP m o d e (Hi : Stable, n o t H i : U n stab le)
Analog Function : A/ D, D/A a nd Switche s (Hi : Ena ble, L o : Di sabl e)
R egist er R/W : Gain Pre-settin g, C lo ck Rate and C odec Data Format (Hi : Enab le, L o : Disable)
VAG : 2.25 V (Hi : Sta ble, not Hi : Unst able )
23
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
-80 -70 -60 -50 -40 -30 -20 -10 0
0
10
20
30
40
50
60
70 M X93000A A/ D L inear Form at SND R C har acteri s ti c
Vin(dB)
SNDR(dB)
FIG. 1
-80 -70 -60 -50 -40 -30 -20 -10 0
0
10
20
30
40
50
60
70 M X93000A D/A Linear Form at SND R C haract e ri s tic
Vin(dB)
SNDR(dB)
FIG. 2
24
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
0500 1000 1500 2000 2500 3000 3500 4000
-25
-20
-15
-10
-5
0M X93000A A/D Frequenc e R e sponse
Frequence(Hz)
dB ( 1.02KHz as 0dB refer ence)
FIG. 3
0500 1000 1500 2000 2500 3000 3500 4000
-12
-10
-8
-6
-4
-2
0
2M X93000A D /A Freque nce R e spons e
Frequence(Hz)
dB ( 1.02KHz as 0dB referenc e)
FIG. 4
25
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
0500 1000 1500 2000 2500 3000
0
500
1000
1500
2000
2500
3000
3500 MX93000A ALC (R/C= 560K/10uF) Charact erist ic
VIN(mVpp)/1.02KHz
VOUT(mVpp)
42.4dB
40dB
38.4dB
34.1dB
31dB
PATH : M IC = > PRE-PGA(0d B) => AL C = > AD-PGA(0dB) = > AD
FIG. 5
0500 1000 1500 2000 2500 3000
0
5
10
15
20
25
30
35
40
M X9300 0A ALC (R /C =560 K/ 10uF) C har acteri s ti c
11/6/97
VIN(mVpp)/1.02KHz
GAIN (dB)
42.4dB
40 dB
38.4dB
34.1 dB
31 dB
PATH : MI C => PR E-PGA(0dB) = > ALC => AD- PGA( 0dB) => AD
FIG. 6
26
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
0500 1000 1500 2000 2500 3000
0
10
20
30
40
50
60
M X9300 0A ALC (R /C =560 K/ 10uF) C har acteri s ti c
VIN(mVpp)/1.02KHz
SNDR(dB)
42.4dB
40dB
38.4dB
34.1dB
31dB
P ATH : MIC => P RE-PGA( 0dB) => ALC => AD -PGA(0dB) => AD
FIG. 7
0200 400 600 800 1000 1200
30
32
34
36
38
40
42
44 M X93000A ALC (C =10uF) Gai n VS Resi stor
Characteristic
Resistor (K Ohms)
Gain (dB )
42.4dB
40 dB
38.4dB
34.1dB
31 dB
FIG. 8
27
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
100101102103
101
102
103MX93000A ALC Attack Time Characteristic
Capacitor(uF)
Attack Time(ms)
Path : DA => LPFC1 => MIC => ALC(40dB Gain) => AD
+18dB(3 => 23.8mVpp)
+24dB(3 => 47.5mVpp)
+30dB(3 => 94.9mVpp)
+36dB(3 => 189mVpp)
+42dB(3 => 378mVpp)
FIG. 9
102103
101
102
103
MX93000A ALC Release Time Characteristic
Resistor(K ohms)
Release Time(ms)
Path : DA => LPFC1 => MIC => ALC(40dB Gain) => AD
-18dB(23.8 => 3mVpp)
-24dB(47.5 => 3mVpp)
-30dB(94.9 => 3mVpp)
-36dB(189 => 3mVpp)
-42dB(378 => 3mVpp)
FIG. 10
28
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
10-1 100101
10-2
10-1
100
101 MX93000A SPK-DRV Total Harmonic Distortion
Vin(Vpp)
THD(%)
PATH : AUX2 => SWH => SWG => SPKP/N
Vout (SPKP/N) = 2*Vin (AUX2)
( AVDD = VDD = 5VDC, RL = 8.2Ω )
FIG. 11
10-1 100101
10-3
10-2
10-1
100
101
(AVDD = VDD = 5VDC , RL = 600 Ω)
Vin
(
Vpp
)
THD(%)
PATH : AUX2 => SWK => LOUTP/N
Vout (LOUTP/N) = 2*Vin (AUX2)
MX93000A LIN-DRV Total Harmonic Distortion
FIG. 12
29
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
0200 400 600 800 1000 1200 1400 1600 1800
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1MX 93000A VBG C- t Character ist ic
t (ms )
C (u F)
FIG. 13
30
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
NOTE : The BOLD characters denote the MX93000A pin-out and BOLD with
Italy
characters denote Function
Block of the MX93000A
NO TE 1 :
PRE-PGA
gain step; from 20.78dB to -14.85dB
1111 1110 1101 1100 1011 1010 1001 1000
20.78dB 17.89dB 15dB 12dB 9dB 7.5dB 6dB 4.5dB
0111 0110 0101 0100 0011 0010 0001 0000
3.0dB 1.5dB 0dB -3dB -6dB -9dB -11.93dB -14.85dB
NO TE 2 :
AD-PGA
gain step; from 18dB to 0dB
11 10 01 00
18dB 8dB 4dB 0dB
NO TE 3 :
DA-PGA
gain step; from 9dB to 0dB; 3dB/step
11 10 01 00
9dB 6dB 3dB 0dB
NO TE 4 :
LIN-DRV
gain step; from 22.46dB to 0dB
1111 1110 1101 1100 1011 1010 1001 1000
22.46dB 21.08dB 19.5dB 18dB 16.5dB 15dB 13.5dB 12dB
0111 0110 0101 0100 0011 0010 0001 0000
10.5dB 9dB 7.5dB 6dB 4.5dB 3dB 1.5dB 0dB
NO TE 5 :
ATT1
(Attenuator 1) gain step; from -44.64dB to 0dB
1111 1110 1101 1100 1011 1010 1001 1000
-44.64dB -38.08dB -32.73dB -27.14dB -24dB -21dB -18dB -15dB
NO TE 6 :
SWD
and
SWI
cannot be turned on simultaneously
NOTE 7 :
SWE
,
SWJ
and
SWL
cannot be turned on simultaneously
NO TE 8 : " " denotes that user should refer to the description of ELECTRICAL CHARACTERISTICS,
TIMING DESCRIPTION and NOTE 1 ~ 5
31
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
Physical Dimensions
44-PIN PQFP
Item Millimeters Inches
A 13.20 ± 0.20 0.5196 ± 0.008
B 10.00 ± 0.05 0.3937 ± 0.002
C 10.00 ± 0.05 0.3937 ± 0.002
D 13.20 ± 0.20 0.5196 ± 0.008
E 8.00 [ REF ] 0.3149
F 1.00 [ REF ] 0.0393 [ REF ]
G 1.00 [ REF ] 0.0393 [ REF ]
H .30 [ TYP. ] 0.0118 [ TYP. ]
I .80 [ TYP. ] 0.0314 [ TYP. ]
J 1.6 ± .1 [ TYP. ] 0.06629 ± 0.004
K 0.80 ± .1 [ TYP. ] 0.0314 ± 0.004
L 0.15 [ TYP. ] 0.15 [ TYP. ]
M 0.120 MAX. 0.0040 MAX.
N 2.0 0.0787
O 0.15 ± 0.05 MIN. 0.00590 ± 0.002
P 2.15 ± 0.1 MAX. 0.0846 ± 0.005
NO TE : Each lead centerline is located within .25mm [ .01 inch ] of its
true position [ TP ] at a maximum material condition .
44-PIN PLCC
Item Millimeters Inches
A 17.53 ± 0.12 0.690 ± 0.005
B 16.59 ± 0.12 0.653 ± 0.005
C 16.59 ± 0.12 0.653 ± 0.005
D 17.53 ± 0.12 0.690 ± 0.005
E 1.95 0.077
F 4.70 MAX. 0.185 MAX.
G 2.25 ± 0.25 0.100 ± 0.010
H 0.51 MIN. 0.020 MIN.
I 1.27 [ TYP. ] 0.050 [ TYP. ]
J 0.71 ± 0.1 0.028 ± 0.004
K 0.46 ± 0.10 0.018 ± 0.004
L 15.50 ± 0.51 0.610 ± 0.020
M 0.63 R 0.025 R
N 0.25 [ TYP. ] 0.010 [ TYP. ]
NO TE : Each lead centerline is located within .25mm [ .01 inch ] of its true
position [ TP ] at a maximum material condition .
44
1
12
11
23
22
33
34
E C D
A
B
F
GH
IJ
L
K
P
O
M
N
A
6
HN
2818
17 29
40
739
CD
B
G
J
I
E
L
M
F
13 33
144
K
32
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
MX 93 F C000A
C om mercial 0 ~ 70 ¢J
Package
Type
F : PQFP
Q : PLCC
Family
Prefix
MX I C C ompan y
Prefix Product
Number
Ordering Information
33
P/N:PM0391 REV. 3.2.1, AUG. 06, 1998
MX93000A
ECR
March 12, 1998 Ver 3.0 ----- change the specification f or Pre-release
1. page4 line22,23 "PGA from 0 to 22.5dB; 1.5dB/step --> see NO TE 4
2. page4 line33,34,35 "PGA from -15 to 21dB;" -->" "
3. page5 line15,16,19,20 "PGA from 0 to 9dB; Attenuator 1 & 2 from 0 to -45dB;"-->" "
4. page8 line13 "from 21dB to -15dB (21, 18, 15, 12, 9, 7.5, 6, 4.5, 3, 0, -3, -6, -9, -12, -15dB)”
--> "from 21dB to -15dB (see NOTE 1)“
5. page9 line9 "from 0 to 22.5dB "-->" from 0 to 22.5dB ”
6. page9 line14 "from 0dB to 22.5dB (1.5dB/step) "-->" from 0dB to 22.5dB (see NO TE 4)”
7. page9 line23,24 "from -45dB to 0dB (-45, -39, -33, -27, -24, -21, -18, -15, -12, -9, -7.5, -6, -4.5, -3, -1.5, 0dB)”
--> "from -45dB to 0dB (see NOTE 5)“
8. change page16,17 and all about LIN-DR V, PRE-PGA and ATT1 gain stage (add an
LIN-DRV : Gain Range from "0 ~ 22.5 "dB to "0 ~ 22.46 "dB, Step Variation from "-0.3dB " to " 10%”
PRE-PGA : Gain Range from "-15 ~ 22.5 "dB to "-14.85 ~ 20.78 "dB , Step Variation from "-0.3dB" to " 10%”
ATT1 : Gain Range from "-45 ~ 0 "dB to "-44.64 ~ 0 "dB, Step Variation from "-0.3dB "to " 10%”
9. page13 "ATT2 (Attenuator 2) -->adjusted b y VR1 20K ohm --> "ATT2 (Attenuator 2) -->adjusted by VR1 10K ohm”
10. change page17,18 about VBG, VA G, VREF and Comparator Transfer Point
VBG : Output Voltage from "1.16,1.2,1.24" to "1.231,1.297,1.362”
add VA G : Output Voltage "2.217,2.334,2.451”
VREF : Output Voltage from "2.0,2.25,2.5" to "2.217,2.334,2.451”
Comparator Transf er P oint from "1.10,1.25,1.40" to "1.231,1.297,1.362”
March 17, 1998 Ver 3.1 ----- modify the description of "The Timing Diag r am of CODEC Function”
1. change page 23 about register R/W
2. page23 line23 "see FIG. 13”
3. add page 31 FIG.13 "VBG C-t Characteristic”
4. change page 22 "Master Clock, Frame Sync. & Data Timing Diagram”
Ma y 8, 1998 Ver 3.2 ----- modify the description of "Pin Description”
±±
±
SVDD2 P (A) 32 (5) analog power ground f or SPK-DRV
SVDD2 P (A) 32 (5) analog pow er supply; 5V power for SPK-DR V
A ugust 6, 1998 Ver 3.21 ----- modify specification of Vref (Voltage Ref erence)
Voltage Reference ( VREF pin )
PARAMETER MIN TYP MAX UNIT
Output Voltage 2.1 2.275 2.45 V
MACRONIX INTERNATIONAL CO., LTD.
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TEL:+886-3-578-8888
FAX:+886-3-578-8887
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MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
MX93000A
