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P/N:PM1398 REV. 0.01, MAY 20, 2008
KH29LV320D T/B
KH29LV320D T/B
DATASHEET
ADVANCED INFORMATION
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KH29LV320D T/B
Contents
FEATURES............................................................................................................................................................ 5
GENERAL DESCRIPTION .................................................................................................................................... 6
PIN CONFIGURA TION........................................................................................................................................... 7
PIN DESCRIPTION ............................................................................................................................................... 7
BLOCK DIAGRAM ................................................................................................................................................. 8
BLOCK DIAGRAM DESCRIPTION ........................................................................................................................ 9
BLOCK STRUCTURE .......................................................................................................................................... 10
Table 1.a: KH29L V320DT SECTOR GROUP ARCHITECTURE .................................................................. 10
Table 1.b: KH29L V320DB SECTOR GROUP ARCHITECTURE .................................................................. 12
BUS OPERA TION ............................................................................................................................................... 14
Table 2-1. BUS OPERATION...................................................................................................................... 14
Table 2-2. BUS OPERATION...................................................................................................................... 15
FUNCTIONAL OPERA TION DESCRIPTION........................................................................................................ 16
READ OPERATION ................................................................................................................................... 16
WRITE OPERATION.................................................................................................................................. 16
DEVICE RESET ........................................................................................................................................ 16
STANDBY MODE ...................................................................................................................................... 16
OUTPUT DISABLE.................................................................................................................................... 16
BYTE/WORD SELECTION ........................................................................................................................ 16
HARDWARE WRITE PROTECT ................................................................................................................. 17
ACCELERA TED PROGRAMMING OPERA TION........................................................................................ 17
TEMPORARY SECTOR GROUP UNPRO TECT OPERA TION.................................................................... 17
SECTOR GROUP PROTECT OPERATION................................................................................................ 17
CHIP UNPROTECT OPERATION .............................................................................................................. 17
A UTOMATIC SELECT BUS OPERATIONS................................................................................................ 18
SECTOR LOCK STATUS VERIFICATION................................................................................................... 18
READ SILICON ID MANUF ACTURER CODE ............................................................................................ 1 8
READ SILICON ID KH29LV320DT CODE .................................................................................................. 18
READ SILICON ID KH29LV320DB CODE.................................................................................................. 18
READ INDICAT OR BIT (Q7) FOR SECURITY SECTOR ............................................................................ 1 8
INHERENT DATA PROTECTION................................................................................................................ 19
COMMAND COMPLETION........................................................................................................................ 19
LOW VCC WRITE INHIBIT ........................................................................................................................ 19
WRITE PULSE "GLITCH" PRO TECTION .................................................................................................. 19
LOGICAL INHIBIT ..................................................................................................................................... 19
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KH29LV320D T/B
POWER-UP SEQUENCE .......................................................................................................................... 19
POWER-UP WRITE INHIBIT ..................................................................................................................... 19
POWER SUPPLY DECOUPLING............................................................................................................... 19
COMMAND OPERA TIONS .................................................................................................................................. 20
TABLE 3. KH29LV320D T/B COMMAND DEFINITIONS............................................................................. 2 0
A UTOMATIC PROGRAMMING OF THE MEMOR Y ARRA Y ....................................................................... 2 1
SECTOR ERASE....................................................................................................................................... 22
SECTOR ERASE SUSPEND..................................................................................................................... 23
CHIP ERASE............................................................................................................................................ 23
A UTOMATIC SELECT COMMAND SEQUENCE........................................................................................ 24
SECT OR ERASE RESUME....................................................................................................................... 24
A UTOMATIC SELECT OPERA TIONS ........................................................................................................ 24
READ MANUF ACTURER ID OR DEVICE ID ............................................................................................. 25
SECURITY SECTOR LOCK ST ATUS......................................................................................................... 25
VERIFY SECTOR GROUP PROTECTION................................................................................................. 25
SECURITY SECTOR FLASH MEMORY REGION ..................................................................................... 2 5
F ACTOR Y LOCKED: SECURITY SECTOR PROGRAMMED AND PRO TECTED A T THE F ACTOR Y ......... 2 5
F ACTOR Y LOCKED: SECURITY SECTOR PROGRAMMED AND PRO TECTED A T THE F ACTOR Y ......... 2 6
CUSTOMER LOCKABLE: SECURITY SECTOR NO T PROGRAMMED OR PROTECTED AT THE F ACTOR Y
.................................................................................................................................................................. 26
ENTER AND EXIT SECURITY SECTOR................................................................................................... 26
RESET OPERATION ................................................................................................................................. 27
COMMON FLASH MEMORY INTERF ACE (CFI) MODE ...................................................................................... 28
QUER Y COMMAND AND COMMAND FLASH MEMORY INTERF ACE (CFI) MODE ................................. 2 8
Table 4-1. CFI mo de: Identificatio n Data V alues .......................................................................................... 28
Tab le 4-2. CFI Mo de: System Interface Data V alues................................................................................... 28
Table 4-3. CFI Mo de: Device Geo metry Data V alues ................................................................................... 29
Table 4-4. CFI Mode: Primary V endo r-Specific Extended Query Data Values............................................... 3 0
ELECTRICAL CHARACTERISTICS .................................................................................................................... 31
OPERA TING TEMPERA TURE AND VOL TAGE .......................................................................................... 31
ABSOLUTE MAXIMUM STRESS RATINGS.............................................................................................. 3 1
DC CHARACTERISTICS ........................................................................................................................... 32
SWITCHING TEST CIRCUIT ..................................................................................................................... 33
SWITCHING TEST WAVEFORM .............................................................................................................. 33
AC CHARACTERISTICS ........................................................................................................................... 34
WRITE COMMAND OPERA TION ........................................................................................................................ 35
Figure 1. COMMAND WRITE OPERATION ................................................................................................ 35
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KH29LV320D T/B
READ/RESET OPERA TION ................................................................................................................................36
Figure 2. READ TIMING W A VEFORM ........................................................................................................ 36
Figure 3. RESET# TIMING WAVEFORM................................................................................................... 37
ERASE/PROGRAM OPERA TION........................................................................................................................ 38
Figure 4. AUT OMATIC CHIP ERASE TIMING W A VEFORM ....................................................................... 3 8
Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART ............................................................. 39
Figure 6. AUTOMA TIC SECTOR ERASE TIMING WAVEFORM.................................................................. 40
Figure 7. AUTOMATIC SECT OR ERASE ALGORITHM FLOWCHART ...................................................... 41
Figure 8. ERASE SUSPEND/RESUME FLOWCHART............................................................................... 42
Figure 9. AUTOMATIC PROGRAM TIMING WA VEFORM ........................................................................... 43
Figure 10. ACCELERATED PROGRAM TIMING DIAGRAM...................................................................... 4 3
Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM..................................................................... 44
Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLO WCHART...................................................... 45
SECTOR GROUP PROTECT/CHIP UNPROTECT ............................................................................................... 46
Figure 13. SECTOR GROUP PROTECT/CHIP UNPRO TECT WA VEFORM (RESET# Control).................... 46
Figure 14. IN-SYSTEM SECTOR GROUP PROTECT WITH RESET#=Vhv ............................................... 4 7
Figure 15. CHIP UNPROTECT ALGORITHM WITH RESET#=Vhv............................................................. 48
Figure 16. TEMPORARY SECT OR GROUP UNPROTECT WA VEFORM .................................................... 49
Table 5. TEMPORAR Y SECTOR GROUP UNPROTECT ............................................................................ 49
Figure 17. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART .................................................. 50
Figure 18. SILICON ID READ TIMING W AVEFORM .................................................................................. 5 1
WRITE OPERA TION STA TUS ............................................................................................................................. 52
Figure 19. DATA# POLLING TIMING WA VEFORM (DURING AUT OMATIC ALGORITHM)........................... 52
Figure 20. DATA# POLLING ALGORITHM .................................................................................................. 53
Figure 21. TOGGLE BIT TIMING WA VEFORM (DURING A UTOMATIC ALGORITHM) ............................... 54
Figure 22. TOGGLE BIT ALGORITHM ....................................................................................................... 55
Figure 23. BYTE# TIMING W A VEFORM FOR READ OPERATIONS (BYTE# s witching fro m byte mo de to...
wo rd mo de)................................................................................................................................................. 56
RECOMMENDED OPERA TING CONDITIONS .................................................................................................... 57
TSOP PIN CAP A CIT ANCE .................................................................................................................................. 58
ERASE AND PROGRAMMING PERFORMANCE................................................................................................ 58
LA TCH-UP CHARACTERISTICS ......................................................................................................................... 58
ORDERING INFORMA TION ................................................................................................................................59
PART NAME DESCRIPTION............................................................................................................................... 60
P ACKAGE INFORMA TION................................................................................................................................... 61
REVISION HISTORY ........................................................................................................................................... 62
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KH29LV320D T/B
32M-BIT [4M x 8 / 2M x 16] 3V SUPPLY FLASH MEMORY
FEATURES
GENERAL FEA TURES
• Byte/Wo rd switchable
- 4,194,304 x 8 / 2,097,152 x 16
• Secto r Structure
- 8K-Byte x 8 and 64K-Byte x 63
• Extra 64K-Byte sector f or security
- Features f acto ry lo c ked and identifiab le, and custo mer lo c kable
• Twenty-F our Sector Gro ups
- Pro vides secto r gro up pro tect function to prevent program or erase o peratio n in the pro tected secto r gro up
- Pro vides chip unpro tect functio n to allow co de changing
- Pro vides tempo rary secto r gro up unprotect functio n fo r code changing in previo usly protected secto r gro ups
• Power Supply Operatio n
- Vcc 2.7 to 3.6 v o lt for read, er ase, and pro gram o perations
• Latch-up protected to 100mA fro m -1V to 1.5 x Vcc
• Low Vcc write inhibit : Vcc <= Vlko
• Co mpatible with JEDEC standard
- Pino ut and so ftware co mpatible to single power supply Flash
PERFORMANCE
• High Performance
- Fast access time: 70ns
- F ast pro gram time: 11us/wo rd typical utilizing accelerate functio n
- Fast erase time: 0.7s/sector , 35s/chip (typical)
• Low Power Co nsumption
- Low active read current: 10mA (typical) at 5MHz
- Low standby current: 5uA (typical)
• Typical 100,000 erase/pro gram cycle
• 10 years data retentio n
SOFTW ARE FEA TURES
• Erase Suspend/ Erase Resume
- Suspends secto r erase o peration to read data fro m o r program data to ano ther secto r which is not being erased
• Status Reply
- Data# Po lling & To ggle bits pro vide detectio n o f program and erase o peratio n completion
• Suppo rt Co mmon Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (R Y/BY#) Output
- Pro vides a hardware metho d of detecting pro gram and erase o peratio n completio n
• Hardware Reset (RESET#) Input
- Pro vides a hardware metho d to reset the internal state machine to read mode
• WP#/ACC input pin
- Pro vides accelerated pro gram capability
PACKAGE
• 48-Pin TSOP
•All Pb-free devices are RoHS Compliant
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KH29LV320D T/B
GENERAL DESCRIPTION
KH29LV320DT/B is a 32Mbit flash memo ry that can be o rganized as 4Mb ytes of 8 bits each o r as 2Mbytes o f 16 bits
each. These devices o perate o ver a vo ltage range of 2.7V to 3.6V typically using a 3V power supply input. The memo ry
array is divided into 64 equal 64 Kilo byte blocks. However, depending on the device being used as a Top-Boot or
Botto m-Boot device , the top o r the bottom first block is further subdivided into 8 equal 8Kbyte b locks . The outermo st
two secto rs at the top o r at the bo ttom are respectively the bo ot blocks fo r this device. This flash memory also pro vides
an additio nal f acto ry lo ckab le o r custo mer lo c kable 64Kbyte sector to provide security feature .
The KH29LV320DT/B is offered in a 48-pin TSOPJEDEC standard package. These packages are o ffered in leaded, as
well as lead-free v ersio ns that are co mpliant to the RoHS specifications. The software algorithm used for this de vice
also adheres to the JEDEC standard for single power supply devices. These flash par ts can be programmed in
system o r on co mmercially available EPROM/Flash pro grammers.
Separate OE# and CE# (Output Enable and Chip Enable) signals are pro vided to simplify system design. When used
with high speed pro cessors, the 70ns read access time o f this flash memo ry permits o peration with minimal time lo st
due to system timing delays.
The automatic write algorithm provided on Macronix flash memo ries perfo rm an automatic erase prio r to write. The user
o nly needs to provide a write command to the command register . The on-chip state machine automatically co ntrols the
program and erase functions including all necessary internal timings. Since erase and write operations take much
longer time than read operations, erase/wr ite can be interrupted to perfor m read operations in other sectors of the
device. Fo r this, Erase Suspend o peration along with Erase Resume o peratio n are pro vided. Data# polling or T o ggle bits
are used to indicate the end o f the erase/write o peration.
These devices are manufactured at the Macro nix fabricatio n facility using the time tested and pro ven MXIC advanced
techno lo gy . This proprietary non-epi pro cess pro vides a very high degree o f latch-up protectio n fo r stresses up to 100
milliamperes o n address and data pins fro m -1V to 1.5xVCC.
With low power co nsumption and enhanced hardware and so ftware features, this flash memo ry retains data reliably for
at least ten years. Erase and programming functions have been tested to meet a typical specification of 100,000
cycles o f o peratio n.
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KH29LV320D T/B
PIN CONFIGURATION
48 TSOP
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
NC
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SYMBOL PIN NAME
A0~A20 Address Input
Q0~Q14 15 Data Inputs/Outputs
Q15/A-1 Q15(Data Input/Output, wo rd mode);
A-1(LSB Address Input, byte mo de)
CE# Chip Enable Input
WE# Write Enable Input
OE# Output Enable Input
BYTE# Wo rd/Byte Selection Input
RESET# Hardware Reset Pin, Active Low
R Y/BY# Ready/Busy Output
Vcc 3.0 vo lt-o nly single power supply
WP#/ACC Hardware Write Protect/Acceleration
Pin
GND Device Gro und
N C Pin No t Connected Internally
PIN DESCRIPTION LOGIC SYMBOL
16 or 8
Q0-Q15
(A-1)
RY/BY#
A0-A20
VCC
GND
CE#
OE#
WE#
RESET#
WP#/ACC
BYTE#
21
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KH29LV320D T/B
BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH V OLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q15/A-1
A0-AM
AM: MSB address
CE#
OE#
WE#
RESET#
BYTE#
WP#/ACC
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KH29LV320D T/B
BLOCK DIAGRAM DESCRIPTION
The blo ck diagram o n Page 9 illustrates a simplified architecture of KH29LV320D T/B. Each blo ck in the blo ck diagram
represents o ne o r mo re circuit mo dules in the real chip used to access, erase, pro gram, and read the memo ry arra y ..
The "CONTROL INPUT LOGIC" block receives input pins CE#, OE#, WE#, RESET#, BYTE#, and WP#/ACC. It
creates internal timing contro l signals according to the input pins and outputs to the "ADDRESS LA TCH AND BUFFER"
to latch the external address pins A0-AM(A20). The internal addresses are output from this blo ck to the main array and
decoders co mposed of "X-DECODER", "Y-DECODER", "Y-PASS GATE", and "FLASH ARRAY". The X-DECODER
deco des the wo rd-lines o f the flash array, while the Y-DECODER deco des the bit-lines o f the flash array. The bit lines
are electrically connected to the "SENSE AMPLIFIER" and "PGM DATA HV" selectively through the y-pass gates.
Sense amplifiers are used to read out the co ntents of the flash memory, while the "PGM DATA HV" bloc k is used to
selectively deliver high power to bit-lines during pro gramming. The "I/O BUFFER" co ntrols the input and output on the
Q0-Q15/A-1 pads. During read operatio n, the I/O buffer receives data from sense amplifiers and drives the o utput pads
accordingly. In the last cycle of program command, the I/O buff er tr ansmits the data o n Q0-Q15/A-1 to "PR OGRAM
D ATA LATCH", which co ntrols the high po wer drivers in "PGM D ATA HV" to selectively program the bits in a w o rd or
byte acco rding to the user input pattern.
The "PROGRAM/ERASE HIGH V OLTA GE" bloc k co mprises the circuits to generate and deliv er the necessary high
v o ltage to the X-DECODER, FLASH ARRAY, and "PGM D ATA HV" blo c k. The logic co ntrol mo dule comprises o f the
"WRITE STATE MACHINE (WSM)", "STATE REGISTER", "COMMAND DATA DECODER", and "COMMAND D ATA
LATCH". When the user issues a co mmand by to ggling WE#, the co mmand o n Q0-A15/A-1 is latched in the command
data latch and is deco ded b y the co mmand data deco der . The state register receiv es the co mmand and reco rds the
current state o f the device. The WSM implements the internal algo rithms fo r program o r erase acco rding to the current
command state by contro lling each b lock in the b loc k diagram.
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KH29LV320D T/B
Sector Sector Size Sector Sector Address Address Range
Group Byte Mode Word Mode A20-A12 Byte Mode (x8) W ord Mode (x16)
(Kbytes) (Kwords)
1 64 32 SA0 000000xxx 000000h-00FFFFh 000000h-07FFFh
1 64 32 SA1 000001xxx 010000h-01FFFFh 008000h-0FFFFh
1 64 32 SA2 000010xxx 020000h-02FFFFh 010000h-17FFFh
1 64 32 SA3 000011xxx 030000h-03FFFFh 018000h-01FFFFh
2 64 32 SA4 000100xxx 040000h-04FFFFh 020000h-027FFFh
2 64 32 SA5 000101xxx 050000h-05FFFFh 028000h-02FFFFh
2 64 32 SA6 000110xxx 060000h-06FFFFh 030000h-037FFFh
2 64 32 SA7 000111xxx 070000h-07FFFFh 038000h-03FFFFh
3 64 32 SA8 001000xxx 080000h-08FFFFh 040000h-047FFFh
3 64 32 SA9 001001xxx 090000h-09FFFFh 048000h-04FFFFh
3 64 32 SA10 001010xxx 0A0000h-0AFFFFh 050000h-057FFFh
3 64 32 SA11 001011xxx 0B0000h-0BFFFFh 058000h-05FFFFh
4 64 32 SA12 001100xxx 0C0000h-0CFFFFh 060000h-067FFFh
4 64 32 SA13 001101xxx 0D0000h-0DFFFFh 068000h-06FFFFh
4 64 32 SA14 001110xxx 0E0000h-0EFFFFh 070000h-077FFFh
4 64 32 SA15 001111xxx 0F0000h-0FFFFFh 078000h-07FFFFh
5 64 32 SA16 010000xxx 100000h-10FFFFh 080000h-087FFFh
5 64 32 SA17 010001xxx 110000h-11FFFFh 088000h-08FFFFh
5 64 32 SA18 010010xxx 120000h-12FFFFh 090000h-097FFFh
5 64 32 SA19 010011xxx 130000h-13FFFFh 098000h-09FFFFh
6 64 32 SA20 010100xxx 140000h-14FFFFh 0A0000h-0A7FFFh
6 64 32 SA21 010101xxx 150000h-15FFFFh 0A8000h-0AFFFFh
6 64 32 SA22 010110xxx 160000h-16FFFFh 0B0000h-0B7FFFh
6 64 32 SA23 010111xxx 170000h-17FFFFh 0B8000h-0BFFFFh
7 64 32 SA24 011000xxx 180000h-18FFFFh 0C0000h-0C7FFFh
7 64 32 SA25 011001xxx 190000h-19FFFFh 0C8000h-0CFFFFh
7 64 32 SA26 011010xxx 1A0000h-1AFFFFh 0D0000h-0D7FFFh
7 64 32 SA27 011011xxx 1B0000h-1BFFFFh 0D8000h-0DFFFFh
8 64 32 SA28 011100xxx 1C0000h-1CFFFFh 0E0000h-0E7FFFh
8 64 32 SA29 011101xxx 1D0000h-1DFFFFh 0E8000h-0EFFFFh
8 64 32 SA30 011110xxx 1E0000h-1EFFFFh 0F0000h-0F7FFFh
8 64 32 SA31 011111xxx 1F0000h-1FFFFFh 0F8000h-0FFFFFh
9 64 32 SA32 100000xxx 200000h-20FFFFh 100000h-107FFFh
9 64 32 SA33 100001xxx 210000h-21FFFFh 108000h-10FFFFh
9 64 32 SA34 100010xxx 220000h-22FFFFh 110000h-117FFFh
9 64 32 SA35 100011xxx 230000h-23FFFFh 118000h-11FFFFh
T able 1.a: KH29L V320DT SECTOR GROUP ARCHITECTURE
BLOCK STRUCTURE
The main flash memory array can be organized as 4M Bytes x 8 or as 2M Words x 16. The details of the address
ranges and the co rresponding sector addresses are shown in Table 1. Table 1.a shows the secto r group architecture fo r
the Top Boot part, whereas Table 1.b shows the sector group architecture for the Bottom Boot part. The specific
security secto r addresses are sho wn at the bo ttom o ff each of these tables .
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KH29LV320D T/B
Sector Sector Size Sector Sector Address Address Range
Group Byte Mode Word Mode A20-A12 Byte Mode (x8) W ord Mode (x16)
(Kbytes) (Kwords)
10 64 32 SA36 100100xxx 240000h-24FFFFh 120000h-127FFFh
10 64 32 SA37 100101xxx 250000h-25FFFFh 128000h-12FFFFh
10 64 32 SA38 100110xxx 260000h-26FFFFh 130000h-137FFFh
10 64 32 SA39 100111xxx 270000h-27FFFFh 138000h-13FFFFh
11 64 32 SA40 101000xxx 280000h-28FFFFh 140000h-147FFFh
11 64 32 SA41 101001xxx 290000h-29FFFFh 148000h-14FFFFh
11 64 32 SA42 101010xxx 2A0000h-2AFFFFh 150000h-157FFFh
11 64 32 SA43 101011xxx 2B0000h-2BFFFFh 158000h-15FFFFh
12 64 32 SA44 101100xxx 2C0000h-2CFFFFh 160000h-147FFFh
12 64 32 SA45 101101xxx 2D0000h-2DFFFFh 168000h-14FFFFh
12 64 32 SA46 101110xxx 2E0000h-2EFFFFh 170000h-177FFFh
12 64 32 SA47 101111xxx 2F0000h-2FFFFFh 178000h-17FFFFh
13 64 32 SA48 110000xxx 300000h-30FFFFh 180000h-187FFFh
13 64 32 SA49 110001xxx 310000h-31FFFFh 188000h-18FFFFh
13 64 32 SA50 110010xxx 320000h-32FFFFh 190000h-197FFFh
13 64 32 SA51 110011xxx 330000h-33FFFFh 198000h-19FFFFh
14 64 32 SA52 110100xxx 340000h-34FFFFh 1A0000h-1A7FFFh
14 64 32 SA53 110101xxx 350000h-35FFFFh 1A8000h-1AFFFFh
14 64 32 SA54 110110xxx 360000h-36FFFFh 1B0000h-1B7FFFh
14 64 32 SA55 110111xxx 370000h-37FFFFh 1B8000h-1BFFFFh
15 64 32 SA56 111000xxx 380000h-38FFFFh 1C0000h-1C7FFFh
15 64 32 SA57 111001xxx 390000h-39FFFFh 1C8000h-1CFFFFh
15 64 32 SA58 111010xxx 3A0000h-3AFFFFh 1D0000h-1D7FFFh
15 64 32 SA59 111011xxx 3B0000h-3BFFFFh 1D8000h-1DFFFFh
16 64 32 SA60 111100xxx 3C0000h-3CFFFFh 1E0000h-1E7FFFh
16 64 32 SA61 111101xxx 3D0000h-3DFFFFh 1E8000h-1EFFFFh
16 64 32 SA62 111110xxx 3E0000h-3EFFFFh 1F0000h-1F7FFFh
17 8 4 SA63 111111000 3F0000h-3F1FFFh 1F8000h-1F8FFFh
18 8 4 SA64 111111001 3F2000h-3F3FFFh 1F9000h-1F9FFFh
19 8 4 SA65 111111010 3F4000h-3F5FFFh 1FA000h-1FAFFFh
20 8 4 SA66 111111011 3F6000h-3F7FFFh 1FB000h-1FBFFFh
21 8 4 SA67 111111100 3F8000h-3F9FFFh 1FC000h-1FCFFFh
22 8 4 SA68 111111101 3FA000h-3FBFFFh 1FD000h-1FDFFFh
23 8 4 SA69 111111110 3FC000h-3FDFFFh 1FE000h-1FEFFFh
24 8 4 SA70 111111111 3FE000h-3FFFFFh 1FF000h-1FFFFFh
T op Boot Security Sector Addresses
Sector Size Sector Address Address Range
Byte Mode W ord Mode A20~A12 Byte Mode (x8) Word Mode (x16)
(Kbytes) (Kwords)
64 32 111111xxx 3F0000h-3FFFFFh 1F8000h-1FFFFFh
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Sector Sector Size Sector Sector Address Address Range
Group Byte Mode Word Mode A20-A12 Byte Mode (x8) Word Mode (x16)
(Kbytes) (Kwords)
1 8 4 SA0 000000000 000000h-001FFFh 000000h-000FFFh
2 8 4 SA1 000000001 002000h-003FFFh 001000h-001FFFh
3 8 4 SA2 000000010 004000h-005FFFh 002000h-002FFFh
4 8 4 SA3 000000011 006000h-007FFFh 003000h-003FFFh
5 8 4 SA4 000000100 008000h-009FFFh 004000h-004FFFh
6 8 4 SA5 000000101 00A000h-00BFFFh 005000h-005FFFh
7 8 4 SA6 000000110 00C000h-00DFFFh 006000h-006FFFh
8 8 4 SA7 000000111 00E000h-00FFFFh 007000h-007FFFh
9 64 32 SA8 000001xxx 010000h-01FFFFh 008000h-00FFFFh
9 64 32 SA9 000010xxx 020000h-02FFFFh 010000h-017FFFh
9 64 32 SA10 000011xxx 030000h-03FFFFh 018000h-01FFFFh
10 64 32 SA11 000100xxx 040000h-04FFFFh 020000h-027FFFh
10 64 32 SA12 000101xxx 050000h-05FFFFh 028000h-02FFFFh
10 64 32 SA13 000110xxx 060000h-06FFFFh 030000h-037FFFh
10 64 32 SA14 000111xxx 070000h-07FFFFh 038000h-03FFFFh
11 64 32 SA15 001000xxx 080000h-08FFFFh 040000h-047FFFh
11 64 32 SA16 001001xxx 090000h-09FFFFh 048000h-04FFFFh
11 64 32 SA17 001010xxx 0A0000h-0AFFFFh 050000h-057FFFh
11 64 32 SA18 001011xxx 0B0000h-0BFFFFh 058000h-05FFFFh
12 64 32 SA19 001100xxx 0C0000h-0CFFFFh 060000h-067FFFh
12 64 32 SA20 001101xxx 0D0000h-0DFFFFh 068000h-06FFFFh
12 64 32 SA21 001110xxx 0E0000h-0EFFFFh 070000h-077FFFh
12 64 32 SA22 001111xxx 0F0000h-0FFFFFh 078000h-07FFFFh
13 64 32 SA23 010000xxx 100000h-10FFFFh 080000h-087FFFh
13 64 32 SA24 010001xxx 110000h-11FFFFh 088000h-08FFFFh
13 64 32 SA25 010010xxx 120000h-12FFFFh 090000h-097FFFh
13 64 32 SA26 010011xxx 130000h-13FFFFh 098000h-09FFFFh
14 64 32 SA27 010100xxx 140000h-14FFFFh 0A0000h-0A7FFFh
14 64 32 SA28 010101xxx 150000h-15FFFFh 0A8000h-0AFFFFh
14 64 32 SA29 010110xxx 160000h-16FFFFh 0B0000h-0B7FFFh
14 64 32 SA30 010111xxx 170000h-17FFFFh 0B8000h-0BFFFFh
15 64 32 SA31 011000xxx 180000h-18FFFFh 0C0000h-0C7FFFh
15 64 32 SA32 011001xxx 190000h-19FFFFh 0C8000h-0CFFFFh
15 64 32 SA33 011010xxx 1A0000h-1AFFFFh 0D0000h-0D7FFFh
15 64 32 SA34 011011xxx 1B0000h-1BFFFFh 0D8000h-0DFFFFh
16 64 32 SA35 011100xxx 1C0000h-1CFFFFh 0E0000h-0E7FFFh
16 64 32 SA36 011101xxx 1D0000h-1DFFFFh 0E8000h-0EFFFFh
16 64 32 SA37 011110xxx 1E0000h-1EFFFFh 0F0000h-0F7FFFh
16 64 32 SA38 011111xxx 1F0000h-1FFFFFh 0F8000h-0FFFFFh
T able 1.b: KH29L V320DB SECTOR GROUP ARCHITECTURE
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Sector Sector Size Sector Sector Address Address Range
Group Byte Mode Word Mode A20-A12 Byte Mode (x8) W ord Mode (x16)
(Kbytes) (Kwords)
17 64 32 SA39 100000xxx 200000h-20FFFFh 100000h-107FFFh
17 64 32 SA40 100001xxx 210000h-21FFFFh 108000h-10FFFFh
17 64 32 SA41 100010xxx 220000h-22FFFFh 110000h-117FFFh
17 64 32 SA42 100011xxx 230000h-23FFFFh 118000h-11FFFFh
18 64 32 SA43 100100xxx 240000h-24FFFFh 120000h-127FFFh
18 64 32 SA44 100101xxx 250000h-25FFFFh 128000h-12FFFFh
18 64 32 SA45 100110xxx 260000h-26FFFFh 130000h-137FFFh
18 64 32 SA46 100111xxx 270000h-27FFFFh 138000h-13FFFFh
19 64 32 SA47 101000xxx 280000h-28FFFFh 140000h-147FFFh
19 64 32 SA48 101001xxx 290000h-29FFFFh 148000h-14FFFFh
19 64 32 SA49 101010xxx 2A0000h-2AFFFFh 150000h-157FFFh
19 64 32 SA50 101011xxx 2B0000h-2BFFFFh 158000h-15FFFFh
20 64 32 SA51 101100xxx 2C0000h-2CFFFFh 160000h-167FFFh
20 64 32 SA52 101101xxx 2D0000h-2DFFFFh 168000h-16FFFFh
20 64 32 SA53 101110xxx 2E0000h-2EFFFFh 170000h-177FFFh
20 64 32 SA54 101111xxx 2F0000h-2FFFFFh 178000h-17FFFFh
21 64 32 SA55 110000xxx 300000h-30FFFFh 180000h-187FFFh
21 64 32 SA56 110001xxx 310000h-31FFFFh 188000h-18FFFFh
21 64 32 SA57 110010xxx 320000h-32FFFFh 190000h-197FFFh
21 64 32 SA58 110011xxx 330000h-33FFFFh 198000h-19FFFFh
22 64 32 SA59 110100xxx 340000h-34FFFFh 1A0000h-1A7FFFh
22 64 32 SA60 110101xxx 350000h-35FFFFh 1A8000h-1AFFFFh
22 64 32 SA61 110110xxx 360000h-36FFFFh 1B0000h-1B7FFFh
22 64 32 SA62 110111xxx 370000h-37FFFFh 1B8000h-1BFFFFh
23 64 32 SA63 111000xxx 380000h-38FFFFh 1C0000h-1C7FFFh
23 64 32 SA64 111001xxx 390000h-39FFFFh 1C8000h-1CFFFFh
23 64 32 SA65 111010xxx 3A0000h-3AFFFFh 1D0000h-1D7FFFh
23 64 32 SA66 111011xxx 3B0000h-3BFFFFh 1D8000h-1DFFFFh
24 64 32 SA67 111100xxx 3C0000h-3CFFFFh 1E0000h-1E7FFFh
24 64 32 SA68 111101xxx 3D0000h-3DFFFFh 1E8000h-1EFFFFh
24 64 32 SA69 111110xxx 3E0000h-3EFFFFh 1F0000h-1F7FFFh
24 64 32 SA70 111111xxx 3F0000h-3FFFFFh 1F8000h-1FFFFFh
Bottom Boot Security Sector Addresses
Sector Size Sector Address Address Range
Byte Mode W ord Mode A20~A12 Byte Mode (x8) Word Mode (x16)
(Kbytes) (Kwords)
64 32 111111xxx 000000h-00FFFFh 00000h-07FFFh
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Notes:
1. All secto rs will be unprotected if WP#/ACC=Vhv.
2. The two o utmo st bo o t secto rs are pro tected if WP#/ACC=Vil.
3. When WP#/ACC = Vih, the protection conditions of the two outmost boot sectors depend on previous protection
co nditions."Secto r/Secto r Blo ck Protectio n and Unprotectio n" describes the protect and unprotect method.
4. Q0~Q15 are input (DIN) or o utput (DOUT) pins according to the requests o f command sequence, sector pro tection,
o r data polling algorithm.
5. In Word Mo de (Byte#=Vih), the addresses are AM to A0.
In Byte Mo de (Byte#=Vil), the addresses are AM to A-1 (Q15).
6. AM: MSB o f address .
Mode Select RE- CE# WE# OE# Address Data Byte# WP#/
SET# (I/O) Vil Vih ACC
Q0~Q7 Data (I/O)
Q8~Q15
Device Reset L X X X X Hig hZ HighZ HighZ L/H
Standby Mo de Vcc±Vcc±X X X HighZ HighZ HighZ H
0.3V 0.3V
Output H L H H X HighZ HighZ HighZ L/H
Disable
Read Mode H L H L AIN DOUT Q8-Q14= DOUT L/H
Write(Note1) H L L H AIN DIN HighZ DIN Note3
Accelerate H L L H AIN DIN Q15= DIN Vhv
Program A-1
Temporary Vhv X X X AIN DIN HighZ DIN Note3
Sector-Group
Unprotect
Se cto r-Gro up Vhv L L H Secto r Address, DIN, DOUT X X L/H
Protect (Note2) A6=L, A1=H,
A0=L
Chip Vhv L L H Secto r Address, DIN, DOUT X X No te3
Unprotect A6=H, A1=H,
(Note2) A0=L
BUS OPERATION
T able 2-1. BUS OPERA TION
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Item Control Input AM A11 A 8 A 5
CE# WE# OE# to to A9 to A6 to A1 A0 Q0~Q7 Q8~Q15
A12 A10 A7 A2
Sector Lock Status L H L SA x Vhv x L x H L 01h or x
Verification 00h
(Note1)
Read Silico n ID L H L x x Vhv x L x L L C2h x
Manufacturer Code
Read Silico n ID L H L x x Vhv x L x L H A7h 22h(Word)
KH29LV320DT x (Byte)
Read Silico n ID L H L x x Vhv x L x L H A8h 22h(Word)
KH29LV320DB x (Byte)
Read Indicator Bit L H L x x Vhv x L x H H 99h o r x
(Q7) Fo r Security 19h
Sector (Note2)
Notes:
1. Secto r unprotected co de:00h. Secto r pro tected code:01h.
2. F actory lo cked co de: 99h. Facto ry unlo cked co de: 19h.
3. AM: MSB of address.
T able 2-2. BUS OPERA TION
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FUNCTIONAL OPERATION DESCRIPTION
READ OPERA TION
To perfo rm a read operatio n, the system addresses the desired memory array o r status register locatio n by pro viding its
address o n the address pins and simultaneously enabling the chip by driving CE# & OE# LOW , and WE# HIGH. After
the Tce and To a timing requirements ha ve been met, the system can read the co ntents o f the addressed lo cation b y
reading the Data (I/O) pins. If either the CE# or OE# is held HIGH, the o utputs will remain tri-stated and no data will
appear o n the output pins.
WRITE OPERA TION
To perfor m a write operation, the system provides the desired address on the address pins, enables the chip by
asser ting CE# LOW, and disables the Data (I/O) pins by holding OE# HIGH. The system then places data to be
written on the Data (I/O) pins and pulses WE# LO W . The device captures the address info rmation o n the falling edge
o f WE# and the data o n the rising edge o f WE#. To see an example, please ref er to the timing diagram in Figure 1 o n
Page 32. The system is not allowed to write invalid commands (commands not defined in this datasheet) to the
de vice. Writing an in valid command ma y put the de vice in an undefined state .
DEVICE RESET
Driving the RESET# pin LOW for a period of Trp or more will return the device to Read mode . If the de vice is in the
middle of a program or erase operation, the reset operation will take at most a per iod of Tready1 before the device
returns to Read mo de. Until the de vice do es returns to Read mo de, the R Y/BY# pin will remain Low (Busy Status).
When the RESET# pin is held at GND±0.3V, the de vice only consumes standby (Isbr) current. Ho we v er , the de vice
dra ws larger current if the RESET# pin is held at a vo ltage g reater than GND+0.3V and less than o r equal to Vil.
It is reco mmended to tie the system reset signal to the RESET# pin of the flash memo ry . This allows the device to be
reset with the system and puts it in a state where the system can immediately begin reading boo t code fro m it.
ST ANDBY MODE
The device enters Standby mo de whenev er the RESET# and CE# pins are bo th held High. While in this mode, WE#
and OE# will be ignored, all Data Output pins will be in a high impedance state, and the device will draw minimal (Isb)
current.
OUTPUT DISABLE
While in active mo de (RESET# HIGH and CE# LOW), the OE# pin co ntrols the state o f the o utput pins. If OE# is held
HIGH, all Data (I/O) pins will remain tri-stated. If held LO W, the Byte or Word Data (I/O) pins will drive data.
BYTE/WORD SELECTION
The BYTE# input pin is used to select the o rganizatio n o f the array data and how the data is input/o utput o n the Data
(I/O) pins. If the BYTE# pin is held HIGH, Wo rd mode will be selected and all 16 data lines (Q0 to Q15) will be active.
If BYTE# is forced LO W, Byte mo de will be activ e and only data lines Q0 to Q7 will be active. Data lines Q8 to Q14
will remain in a high impedance state and Q15 beco mes the A-1 address input pin.
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FUNCTIONAL OPERA TION DESCRIPTION (cont'd)
HARDWARE WRITE PROTECT
By driving the WP#/ACC pin LO W , the outermo st two boo t secto rs are protected from all erase/pro gram o perations. If
WP#/ACC is held HIGH (Vih to VCC), these two outermost sectors re vert to their previously protected/unprotected
status.
ACCELERA TED PROGRAMMING OPERA TION
By applying high v o ltage (Vhv) to the WP#/ACC pin, the de vice will enter the Accelerated Programming mode. This
mode permits the system to skip the normal co mmand unlock sequences and program b yte/w ord lo cations directly.
Typically, this mode provides a 30% reduction in ov er all programming times. During accelerated programming, the
current dra wn from the WP#/ACC pin is no mo re than Icp1.
TEMPORAR Y SECTOR GROUP UNPROTECT OPERATION
The system can apply Vhv to the RESET# pin to place the device in Temporary Unprotect mode. In this mode,
previo usly protected secto rs can be programmed/erased just as tho ugh they were unpro tected. The device returns to
nor mal operation once Vhv is removed from the RESET# pin and previously protected sectors will once again be
protected.
SECTOR GROUP PROTECT OPERA TION
The KH29LV320D T/B pro vides user programmable protection against pro gram/erase o peratio ns fo r selected sectors.
Most sectors cannot protected individually. Instead, they are bound in groups of four or less called Sector-Groups.
Pro tectio n is a vailable f o r individual Secto r-Gro ups, which includes all member secto rs. Bo o t secto rs are the e xcep-
tio n to this rule as they are assigned unique Secto r-Group addresses and can be pro tected individually without pro tect-
ing any adjacent sectors or Sector-Groups. The three sectors adjacent to the boo t sectors fo rm a no n-standard Sector-
Gro up. Please refer to Table 1a and Table 1b which show all Secto r-Gro up assignments.
During the pro tection operation, the sector address of any sector within a Sector-Gro up may be used to specify the
Secto r-Group being pro tected.
There are two metho ds available to pro tect Sector-Gro ups. The first and preferred metho d is activated by applying Vhv
on the RESET# pin and f ollowing the timing in Figure 13 and the algorithm shown in Figure 14. This is a command
operatio n that can be perf ormed either o n an external pro gr ammer o r in-circuit b y the system co ntroller. The seco nd
method is strictly a bus o peration and is entered by asserting Vhv on A9 and OE# pins, with A6 and CE# at Vil. The
protectio n operation begins at the falling edge of WE# and terminates at the rising edge. Co ntact Macronix f or mo re
details o n this metho d.
CHIP UNPROTECT OPERA TION
The Chip Unprotect operation unprotects all sectors within the device. It is standard procedure and highly recom-
mended to pro tect all Sector-Gro ups prior using the Chip Unpro tect operatio n. This will prevent possible damage to the
Secto r-Gro up pro tection lo gic. All Secto r Gro ups are unpro tected when shipped fro m the f acto ry, so this o peratio n is
o nly necessary if the user has pre viously pro tected any Secto r-Gro ups and wishes to unpro tect them now .
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FUNCTIONAL OPERA TION DESCRIPTION (cont'd)
CHIP UNPRO TECT OPERA TION (cont'd)
KH29LV320D T/B pro vides two metho ds fo r unpro tecting the entire chip. The first and preferred metho d is entered by
applying Vhv on RESET# pin and following the timing diagram in Figure 13 and using the algo rithm shown in Figure 15.
The second metho d is entered by asserting Vhv on A9 and OE# pins , with A6 at Vih and CE# at Vil. The protection
o peration begins at the falling edge o f WE# and terminates at the rising edge. Contact Macro nix fo r mo re details on this
method.
AUTOMA TIC SELECT BUS OPERA TIONS
The following five bus operations require A9 to be raised to Vhv. Please see AUTOMATIC SELECT COMMAND
SEQUENCE in the COMMAND OPERATIONS section for details of equivalent command operations that do not
require the use o f Vhv .
SECTOR LOCK ST ATUS VERIFICA TION
To determine the protected state o f any secto r using bus o perations, the system perf orms a READ OPERATION with
A9 raised to Vhv, the sector address applied to address pins A20 to A12, address pins A6 & A0 held LOW, and
address pin A1 held HIGH. If data bit Q0 is LOW, the sector is not protected, and if Q0 is HIGH, the sector is
protected.
READ SILICON ID MANUF ACTURER CODE
To determine the Silicon ID Manufacturer Code, the system perfo rms a READ OPERA TION with A9 raised to Vhv and
address pins A6, A1, & A0 held LOW. The Macronix ID co de of C2h should be present o n data bits Q0 to Q7.
READ SILICON ID KH29LV320DT CODE
To verify the Silicon ID KH29LV320DT Code, the system performs a READ OPERATION with A9 raised to Vhv,
address pins A6 & A1 held LOW , and address pin A0 held HIGH. The KH29LV320DT code of A7h should be present
o n data bits Q0 to Q7. Q15 to Q8 will be tri-stated unless Wo rd mo de is selected. In this case , Q15 to Q8 will output
the value 22h.
READ SILICON ID KH29LV320DB CODE
To verify the Silicon ID KH29LV320DB Code, the system performs a READ OPERATION with A9 raised to Vhv,
address pins A6 & A1 held LOW , and address pin A0 held HIGH. The KH29LV320DT code of A8h should be present
o n data bits Q0 to Q7. Q15 to Q8 will be tri-stated unless Wo rd mo de is selected. In this case , Q15 to Q8 will output
the co de 22h.
READ INDICA TOR BIT (Q7) FOR SECURITY SECTOR
To determine if the Security Sector has been lo c k ed at the facto ry, the system perf orms a READ OPERATION with
A9raised to Vhv, address pin A6 held LO W, and address pins A1 & A0 held HIGH. If the Security Secto r has been
lo cked at the facto ry , the co de 99h will be present o n data bits Q0 to Q7. Otherwise, the facto ry unlo cked co de o f 19h
will be present.
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FUNCTIONAL OPERA TION DESCRIPTION (cont'd)
INHERENT DA T A PROTECTION
To avoid accidental erasure or programming of the device, the device is automatically reset to Read mode dur ing
power up. Additio nally , the f o llowing design features pro tect the de vice from unintended data co rruption.
COMMAND COMPLETION
Only after the successful completion of the specified command sets will the device begin its erase or program
o peration. If an y co mmand sequence is interrupted o r given an in valid co mmand, the de vice immediately returns to
Read mode.
LOW VCC WRITE INHIBIT
The device refuses to accept any wr ite command when Vcc is less than Vlko. This prevents data from spuriously
being altered during power-up , power-down, o r temporary power interruptio ns. The device auto matically resets itself
when Vcc is lower than Vlko and write cycles are ignored until Vcc is greater than Vlko. The system must provide
pro per signals o n contro l pins after Vcc rises abo ve Vlko to avo id unintentional pro gram o r erase o peratio ns.
WRITE PULSE "GLITCH" PRO TECTION
CE#, WE#, OE# pulses sho rter than 5ns are treated as glitches and will no t be regarded as an effectiv e write cycle.
LOGICAL INHIBIT
A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is igno red when either CE# at Vih,
WE# a Vih, o r OE# at Vil.
POWER-UP SEQUENCE
Upo n power up, the KH29LV320D T/B is placed in Read mo de. Furthermore, program o r erase operation will begin o nly
after successful co mpletio n o f specified co mmand sequences .
POWER-UP WRITE INHIBIT
When WE#, CE# is held at Vil and OE# is held at Vih during pow er up , the device igno res the first co mmand on the
rising edge of WE#.
PO WER SUPPLY DECOUPLING
A 0.1uF capacito r sho uld be connected between the Vcc and GND to reduce the no ise eff ect.
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Notes:
1. ID 22A7h(T o p), 22A8h(Bo ttom).
2. It is not allowed to adopt any other code which is not in the above command definition table.
T ABLE 3. KH29L V320D T/B COMMAND DEFINITIONS
COMMAND OPERATIONS
Hex Word Byte Word Byte Word Byte Word Byte Word Byte
1s t B us Address Address XXX 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA
Cycle Data Data F0 AA AA AA AA AA AA AA AA AA AA
2nd B us Address 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555
Cycle Data 55 55 55 55 55 55 55 55 55 55
3rd Bus Address 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA
Cycle Data 90 90 90 90 90 90 90 90 88 88
4th Bus Address X00 X00 X01 X02 X03 X06 (Sector)
X02 (Sector)X
04
Cycle Data C2h C2h ID ID 99/19 99/19 00/01 00/01
5th Bus Address
Cycle Data
6th Bus Address
Cycle Data
Automatic Select Enter Security
S ec t or Region
Enable
Command Read
Mode Reset
Mode Silicon ID Device ID Sector
Factory S ect or Protect
Verify
Hex Word Byte Word Byte Word Byte Word Byte Word Byte Byte/Word Byte/Word
1s t B us Address 555 AAA 555 AAA 555 AAA 555 AAA 55 AA XXX XXX
Cycle Data AA AA AA AA AA AA AA AA 98 98 B0 30
2nd B us Address 2AA 555 2AA 555 2AA 555 2AA 555
Cycle Data 55 55 55 55 55 55 55 55
3rd Bus Address 555 AAA 555 AAA 555 AAA 555 AAA
Cycle Data 90 90 A0 A0 80 80 80 80
4t h B us Address XXX XXX Address Address 555 AAA 555 AAA
Cycle Data 00 00 Data Data AA AA AA AA
5t h Bus Address 2AA 555 2AA 555
Cycle Data 55 55 55 55
6t h B us Address 555 AAA Sector Sector
Cycle Data 10 10 30 30
Command CF I Read Erase
Suspend Erase
Resume
Exit Security
Sector P rogram Chi p Eras e Sector E ras e
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COMMAND OPERA TIONS (cont'd)
A UTOMATIC PROGRAMMING OF THE MEMOR Y ARRAY
The KH29LV320D T/B pro vides the user the ability to program the memo ry array in Byte mo de o r Wo rd mo de. As long
as the users enters the co rrect cycle defined in the Table 3 (including 2 unlock cycles and the A0H program co mmand),
any byte o r wo rd data pro vided on the data lines by the system will auto matically be pro grammed into the array at the
specified lo cation.
After the program command sequence has been executed, the internal wr ite state machine (WSM) automatically
executes the algo rithms and timings necessary fo r programming and verification, which includes generating suitab le
program pulses, checking cell threshold voltage margins, and repeating the program pulse if any cells do not pass
v erificatio n or ha ve lo w margins. The internal co ntro ller protects cells that do pass v erificatio n and margin tests fro m
being over-programmed by inhibiting fur ther program pulses to these passing cells as weaker cells continue to be
programmed.
With the internal WSM auto matically contro lling the pro g ramming pro cess, the user o nly needs to enter the prog ram
co mmand and data o nce.
Programming will only change the bit status from "1" to "0". It is not possible to change the bit status from "0" to "1"
by pro gramming. This can only be do ne by an erase o peration. Furthermore, the internal write verification o nly checks
and detects errors in cases where a "1" is no t successfully progr ammed to "0".
Any co mmands written to the device during pro gramming will be igno red except hardware reset, which will terminate
the pro gram operation after a period o f time no more than Tready1. When the embedded program algo rithm is complete
o r the program o peratio n is terminated by a hardware reset, the device will return to Read mode.
The typical chip pro gram time at roo m temper ature o f the KH29LV320D T/B is less than 36 seco nds.
After the embedded pro gr am o peratio n has begun, the user can check f o r co mpletio n by reading the f o llowing bits in
the status register:
Status Q7*1 Q6*1 Q5 RY/BY#*2
In pro gress Q7# To ggling 0 0
Finished Q7 Stop toggling 0 1
Exceed time limit Q7# Toggling 1 0
*1: When an attempt is made to pro gram a pro tected sector , the pro gram o peratio n will abort thus preventing any data
changes in the pro tected sector. Q7 will output complement data and Q6 will toggle briefly (1us or less) before aborting
and returning the device to Read mode.
*2: R Y/BY# is an open drain o utput pin and sho uld be co nnected to VCC thro ugh a high value pull-up resisto r .
ERASING THE MEMORY ARRAY
There are two types o f erase operations perfo rmed o n the memory array -- Secto r Erase and Chip Erase. In the Sector
Erase operation, one or more selected sectors may be erased simultaneously. In the Chip Erase operation, the
co mplete memo ry arra y is erased e xcept fo r an y pro tected secto rs .
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SECTOR ERASE
The secto r erase o peratio n is used to clear data within a sector by returning all o f its memory lo cations to the "1" state.
It requires six command cycles to initiate the erase operation. The first two cycles are "unlock cycles", the third is a
configuration cycle, the fourth and fifth are also "unlock cycles", and the sixth cycle is the Sector Erase command.
After the sector erase co mmand sequence has been issued, an internal 50us time-out co unter is started. Until this
co unter reaches zero, additio nal secto r addresses and Sector Erase co mmands may be issued thus allowing multiple
sectors to be selected and erased simultaneously. After the 50us time-out counter has expired, no ne w commands
will be accepted and the embedded secto r erase o peration will begin. Note that the 50us timer-o ut counter is restarted
after e v ery erase command sequence. If the user enters any command o ther than Sector Erase or Erase Suspend
during the time-out period, the erase o peratio n will abo rt and the device will return to Read mo de.
After the embedded sector erase operation begins, all commands except Erase Suspend will be igno red. The only way
to interrupt the operation is with an Erase Suspend command or with a hardware reset. The hardware reset will
co mpletely abort the operatio n and return the device to Read mo de.
The system can determine the status o f the embedded secto r erase o peratio n by the fo llo wing metho ds:
Status Q 7 Q 6 Q 5 Q3 (note 1) Q2 RY/BY#(note 2)
Time-out period 0 To ggling 0 0 Toggling 0
In pro gress 0 To ggling 0 1 Toggling 0
Finished 1 Stop toggling 0 1 1 1
Exceeded time limit 0 Toggling 1 1 Toggling 0
No te :
1. The Q3 status bit is the time-o ut indicator . When Q3=0, the time-out co unter has not yet reached z ero and a new
Sector Erase command may be issued to specify the address of another sector to be erased. When Q3=1, the
time-o ut co unter has e xpired and the Secto r Erase o per atio n has already begun. Erase Suspend is the o nly v alid
co mmand that may be issued o nce the embedded erase o peratio n is underway.
2 . RY/BY# is an o pen drain o utput pin and should be co nnected to VCC thro ugh a high value pull-up resisto r .
3. When an attempt is made to erase only protected secto r(s), the program operatio n will abort thus prev enting an y
data changes in the protected sector(s). Q7 will output its complement data and Q6 will toggle briefly (100us or less)
before aborting and returning the device to Read mo de. If unprotected sectors are also specified, however, they will
be erased no rmally and the protected secto r(s) will remain unchanged.
4. Q2 is a lo calized indicator sho wing a specified secto r is undergo ing er ase o peratio n or no t. Q2 to ggles when user
reads at addresses where the secto rs are actively being erased (in erase mo de) or to be erased (in erase suspend
mo de). When a secto r has been co mpletely erased, Q2 sto ps to ggling at the sector even when the de vice is still in
erase o peratio n fo r remaining selected sectors. At that circumstance, Q2 will still to ggle when device is read at any
o ther secto r that remains to be erased.
COMMAND OPERA TIONS (cont'd)
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KH29LV320D T/B
CHIP ERASE
The Chip Erase o peratio n is used erase all the data within the memo ry array. All memo ry cells co ntaining a "0" will be
returned to the erased state of "1". This operatio n requires 6 write cycles to initiate the actio n. The first two cycles are
"unlock" cycles, the third is a configuration cycle, the four th and fifth are also "unlock" cycles, and the sixth cycle
initiates the chip erase o peratio n.
During the chip erase o peratio n, no other so ftware co mmands will be accepted, but if a hardware reset is received o r
the wo rking vo ltage is to o low, that chip erase will be terminated. After Chip Erase, the chip will auto matically return to
Read mode.
The system can determine the status o f the embedded chip erase o peratio n by the f o llowing metho ds:
Status Q7 Q6 Q5 Q2 RY/BY#*1
In pro gress 0 To ggling 0 Toggling 0
Finished 1 Stop toggling 0 1 1
Exceed time limit 0 Toggling 1 Toggling 0
*1: R Y/BY# is an open drain o utput pin and sho uld be co nnected to VCC thro ugh a high v alue pull-up resisto r.
After beginning a sector erase operation, Erase Suspend is the only valid command that may be issued. If system
issues an Erase Suspend co mmand during the 50us time-out perio d fo llowing a Sector Erase co mmand, the time-out
period will terminate immediately and the device will enter Erase-Suspended Read mode. If the system issues an
Erase Suspend command after the sector erase o peration has already begun, the de vice will not enter Erase-Sus-
pended Read mo de until Tready1 time has elapsed. The system can determine if the device has entered the Erase-
Suspended Read mo de through Q6, Q7, and R Y/BY#.
After the device has entered Erase-Suspended Read mode, the system can read or program any sector(s) except
tho se being erased by the suspended erase o peratio n. Reading any sector being erased o r programmed will return the
contents o f the status register. Whenever a suspend command is issued, user must issue a resume command and
check Q6 to ggle bit status, before issue another erase co mmand. The system can use the status register bits shown
in the f o llo wing table to determine the current state o f the de vice:
Status Q7 Q6 Q5 Q3 Q2 RY/BY#
Erase suspend read in erase suspended secto r 1 No to ggle 0 N/A Toggle 1
Erase suspend read in no n-erase suspended secto r Data Data Data Data Data 1
Erase suspend pro gram in no n-erase suspended sector Q7 # Toggle 0 N/A N/A 0
SECTOR ERASE SUSPEND
When the device has suspended er asing, user can e x ecute the co mmand sets e xcept secto r erase and chip erase ,
such as read silico n ID, secto r protect v erify, program, CFI query and erase resume.
COMMAND OPERA TIONS (cont'd)
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COMMAND OPERA TIONS (cont'd)
SECTOR ERASE RESUME
The sector Erase Resume command is valid only when the device is in Erase-Suspended Read mode . After erase
resumes, the user can issue another Ease Suspend command, but there should be a 4ms interval between Ease
Resume and the next Erase Suspend command. If the user enters an infinite suspend-resume loop, or suspend-
resume e xceeds 1024 times, er ase times will increase dramatically.
AUTOMATIC SELECT OPERA TIONS
When the device is in Read mode, Erase-Suspended Read mode, or CFI mode, the user can issue the Automatic
Select command shown in Table 3 (two unlock cycles followed by the Automatic Select command 90h) to enter
A utomatic Select mode. After entering Automatic Select mode, the user can query the Manufacturer ID, Device ID,
Security Sector lo cked status, o r Sector-Group pro tected status multiple times witho ut issuing a new A utomatic Select
command.
While In Automatic Select mode, issuing a Reset command (F0h) will retur n the device to Read mode (or Ease-
Suspended Read mode if Erase-Suspend was active).
Another way to enter Auto matic Select mode is to use one o f the bus o perations shown in Table 2-2. BUS OPERATION.
After the high voltage (Vhv) is remov ed fro m the A9 pin, the de vice will auto matically return to Read mo de o r Erase-
Suspended Read mode.
AUTOMA TIC SELECT COMMAND SEQUENCE
A uto matic Select mo de is used to access the manuf acturer ID , de vice ID and to verify whether o r no t secured silico n
is lo cked and whether o r not a secto r is protected. The automatic select mode has fo ur command cycles. The first two
are unlo ck cycles, and fo llowed by a specific co mmand. The fo urth cycle is a no rmal read cycle, and user can read at
any address any number o f times witho ut entering another co mmand sequence. The Reset command is necessary to
e xit the A utomatic Select mo de and bac k to read arra y. The f o llo wing table sho ws the identificatio n code with corre-
sponding address.
Address (Hex) Data (Hex) Representatio n
Manufacturer ID Wo r d X00 C 2
Byte X00 C2
Device ID W or d X 01 22A7/22A8 Top/Bottom Boo t Secto r
Byte X02 A7/A8 To p/Bo ttom Boo t Sector
Secured Silicon W o rd X03 99/19 Facto ry lock ed/unlocked
Byte X06 99/19 Facto ry lo cked/unlo cked
Secto r Protect V erify W or d (Sector address) X 02 00/01 Unprotected/protected
Byte (Secto r address) X 04 00/01 Unprotected/protected
After entering auto matic select mo de, no o ther co mmands are allowed except the reset co mmand.
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KH29LV320D T/B
READ MANUF ACTURER ID OR DEVICE ID
The Manuf acturer ID (identificatio n) is a unique hexadecimal number assigned to each man uf acturer by the JEDEC
committee. Each company has its own manufacturer ID, which is different from the ID of all other companies. The
number assigned to Macro nix is C2h.
The Device ID is a unique hexadecimal number assigned by the manufacturer fo r each one of the flash devices made
by that manufacturer .
The above two ID types are stored in a 16-bit register on the flash device -- eight bits for each ID. This register is
no rmally read by the user o r b y the pro gramming machine to identify the man ufacturer and the specific de vice.
After entering Automatic Select mode, perf orming a read o per ation with A1 & A0 held LOW will cause the de vice to
o utput the Manuf acturer ID on the Data I/O (Q7 to Q0) pins. P erfo rming a read o peration with A1 LOW and A0 HIGH
will cause the de vice to output the Device ID.
SECURITY SECTOR LOCK ST ATUS
After entering Auto matic Select mo de, the custo mer can check the lo ck status o f the Security Secto r by perfo rming a
read o perations with A0 and A1 held HIGH. If the co de 99h is read from data pins Q7 to Q0, the secto r has been locked
at the f actory. If the code 19h is read, the sector has no t been loc k ed at the factory.
VERIFY SECTOR GROUP PROTECTION
After entering Automatic Select mode, perfor ming a read operation with A1 held HIGH and A0 held LOW and the
address of the sector to be checked applied to A20 to A12, data bit Q0 will indicate the protected status of the
addressed sector. If Q0 is HIGH, the sector is pro tected. Conv ersely, if Q0 is LO W, the sector is unpro tected.
SECURITY SECTOR FLASH MEMOR Y REGION
The Security Sector regio n is an extra memory space of 64KBytes (32KWo rds) in length. The Security Secto r can be
lock ed b y the f acto ry prio r to shipping, or it can be lock ed by the customer later .
F ACTORY LOCKED: SECURITY SECTOR PROGRAMMED AND PROTECTED A T THE F A CTOR Y
In a facto ry locked device, the Security Secto r is permanently locked befo re shipping fro m the facto ry. The device will
ha ve a 16-b yte (8-wo rd) ESN in the security regio n. In bo ttom bo ot de vices, the ESN o ccupies addresses 00000h to
0000Fh in byte mo de o r 00000h to 00007h in wo rd mo de. In to p boo t devices, the EXN o ccupies addresses 3F0000h
to 3F000Fh in byte mo de o r 1F800h to 1F8007h in wo rd mo de.
COMMAND OPERA TIONS (cont'd)
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F ACTORY LOCKED: SECURITY SECTOR PROGRAMMED AND PROTECTED A T THE F A CTOR Y
In a facto ry locked device, the Security Secto r is permanently locked befo re shipping fro m the facto ry. The device will
ha ve a 16-b yte (8-wo rd) ESN in the security regio n. In bo ttom bo ot de vices, the ESN o ccupies addresses 00000h to
0000Fh in byte mo de o r 00000h to 00007h in wo rd mo de. In to p boo t devices, the EXN o ccupies addresses 3F0000h
to 3F000Fh in byte mo de o r 1F800h to 1F8007h in wo rd mo de.
CUSTOMER LOCKABLE: SECURITY SECTOR NOT PROGRAMMED OR PROTECTED A T THE F ACTOR Y
When the security feature is not required, the Security Secto r can provide an extr a sector o f memory, which can be
read, pro grammed, and erased with the same endurance limitatio ns specified fo r no rmal sectors.
Two metho ds are available fo r pro tecting the Security Sector . No te that once the Security Sector is pro tected, there is
NO wa y to unprotect it and its co ntents can no longer be altered.
The first pro tection metho d requires writing the three-cycle Enter Security Regio n command followed by the use o f the
Sector-Gro up protect algo rithm as illustrated in Figure 14-1 with the f o llo wing e xceptio n: the RESET# pin ma y be at
either Vih or Vhv . Unlike no rmal Sector-Gro ups, which do require Vhv on the RESET# pin, the Security Sector may be
permanently loc ked in-circuit witho ut the use o f high v o ltage.
The second protectio n method also uses the three-cycle Enter Security Regio n command, but uses b us operations
that applies Vhv to the A9 and OE# pins with A6, CE#, and WE# held LOW and the SA address applied to A20 to A12.
The pro tection operation begins at the falling edge o f WE# and terminates at the rising edge. Contact Macronix for more
details o n using this method.
After the Security Secto r is lo c ked and v erified, the system must write an Exit Security Secto r Regio n command, go
thro ugh a power cycle, o r issue a hardware reset to return the device to read no rmal array mo de.
ENTER AND EXIT SECURITY SECTOR
The de vice allows the user to access the extr a 64K-Byte secto r identified as the Security Secto r , which may co ntain
a rando m, 128-bits electro nic serial number (ESN), o r it may co ntain user data.
To access the Security Secto r, the user must issue a three-cycle "Enter Security Secto r" command sequence. To exit
the Security Sector and return to normal o peration, the user issues the f our-cycle "Exit Security Sector" co mmand.
Bef o re issuing the "Exit Security Secto r" co mmand, please ensure the entering o f security secto r regio n.
COMMAND OPERA TIONS (cont'd)
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KH29LV320D T/B
COMMAND OPERA TIONS (cont'd)
RESET OPERA TION
In the f ollowing situatio ns , e x ecuting reset command will reset de vice bac k to Read mode:
•Amo ng erase co mmand sequence (befo re the full command set is co mpleted)
•Secto r erase time-o ut perio d
•Erase fail (while Q5 is high)
•Among program command sequence (before the full command set is completed, erase-suspended program in-
cluded)
•Pro gram fail (while Q5 is high, and erase-suspended pro gram fail is included)
•Read silico n ID mo de
•Secto r protect verify
•CFI mo de
While de vice is at the status of pro gram fail o r erase f ail (Q5 is high), user must issue reset co mmand to reset device
back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode, user must
issue reset co mmand to reset de vice bac k to read arra y mo d e.
When the device is in the progress of programming (no t program fail) o r erasing (no t erase fail), device will igno re reset
command.
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T able 4-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
T able 4-2. CFI Mode: System Interface Data V alues
Description Address (h) Address (h) Data (h)
(Word Mode) (Byte Mode)
Query-unique ASCII string "QRY" 1 0 2 0 0051
11 22 0052
12 24 0059
Primary vendor command set and control interface ID code 1 3 2 6 0002
14 28 0000
Address for primary algorithm extended query table 1 5 2A 0040
16 2C 0000
Alternate vendor command set and control interface ID code 1 7 2E 0000
18 30 0000
Address for alternate algorithm extended query table 19 32 0000
1A 34 0000
Description Address (h) Address (h) Data (h)
(Word Mode) (Byte Mode)
Vcc supply minimum program/erase voltage 1B 3 6 0027
Vcc supply maximum program/erase voltage 1 C 38 0036
VPP supply minimum program/erase voltage 1 D 3A 0000
VPP supply maximum program/erase voltage 1E 3 C 0000
Typical timeout per single word/byte write, 2n us 1F 3E 0004
Typical timeout for maximum-size buffer write, 2n us 2 0 4 0 0000
Typical timeout per individual block erase, 2n ms 2 1 4 2 000A
Typical timeout for full chip erase, 2n ms 2 2 44 0000
Maximum timeout for word/byte write, 2n times typical 23 4 6 0005
Maximum timeout for buffer write, 2n times typical 24 4 8 0000
Maximum timeout per individual block erase, 2n times typical 25 4 A 0004
Maximum timeout for chip erase, 2n times typical 26 4C 0000
COMMON FLASH MEMORY INTERFACE (CFI) MODE
QUER Y COMMAND AND COMMAND FLASH MEMORY INTERF A CE (CFI) MODE
KH29LV320D T/B f eatures CFI mode. Host system can retriev e the operating characteristics, structure and vendor-
specified informatio n such as identifying info rmation, memo ry size, b yte/w ord configuration, o perating vo ltages and
timing info rmation o f this device by CFI mo de. The device enters the CFI Query mode when the system writes the CFI
Query co mmand, 98H, to address 55h/AAh (depending on Word/Byte mode) any time the device is ready to read array
data. The system can read CFI inf o rmatio n at the addresses given in Ta ble 4.
Once user enters CFI query mode, user can not issue any other commands except reset command. The reset
command is required to exit CFI mode and go back to the mode bef ore entering CFI. The system can write the CFI
Query co mmand o nly when the device is in read mo de, erase suspend, standby mo de o r auto matic select mo de.
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T able 4-3. CFI Mode: Device Geometry Data V alues
Description Address (h) Address (h) Data (h)
(Word Mode) (Byte Mode)
Device size = 2n in number of bytes 27 4E 0016
Flash device interface description (02=asynchronous x8/x16) 2 8 50 0002
29 52 0000
Maximum number of bytes in buffer write = 2n (not support) 2A 5 4 0000
2B 56 0000
Number of erase regions within device 2 C 5 8 0002
Index for Erase Bank Area 1 2D 5A 0007
[2E,2D] = # of same-size sectors in region 1-1 2E 5C 0000
[30, 2F] = sector size in multiples of 256-bytes 2F 5E 0020
30 60 0000
Index for Erase Bank Area 2 31 6 2 003E
32 64 0000
33 66 0000
34 68 0001
Index for Erase Bank Area 3 35 6 A 0000
36 6C 0000
37 6E 0000
38 70 0000
Index for Erase Bank Area 4 39 7 2 0000
3A 74 0000
3B 76 0000
3C 78 0000
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T able 4-4. CFI Mode: Primary V endor-Specific Extended Query Data V alues
Description Address (h) Address (h) Data (h)
(Word Mode) (Byte Mode)
Query - Primary extended table, unique ASCII string, PRI 4 0 8 0 0050
41 82 0052
42 84 0049
Major version number, ASCII 4 3 8 6 0031
Minor version number, ASCII 4 4 8 8 0031
Unlock recognizes address (0= recognize, 1= don't recognize) 45 8A 0000
Erase suspend (2= to both read and program) 4 6 8 C 0002
Sector protect (N= # of sectors/group) 4 7 8E 0004
Temporary sector unprotect (1=supported) 48 90 0001
Sector protect/Chip unprotect scheme 49 92 0004
Simultaneous R/W operation (0=not supported) 4A 94 0000
Burst mode (0=not supported) 4B 96 0000
Page mode (0=not supported) 4C 98 0000
Minimum ACC (acceleration) supply (0= not supported), [D7:D4] for volt, 4 D 9A 00A5
[D3:D0] for 100mV
Maximum ACC (acceleration) supply (0= not supported), [D7:D4] for volt, 4E 9 C 00B5
[D3:D0] for 100mV
Top/Bottom boot block indicator 4 F 9E 0002/
02h=bottom boot device 03h=top boot device 0003
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ABSOLUTE MAXIMUM STRESS RA TINGS
Surrounding Temper ature with Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +125oC
Storage Temperature . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65oC to +150oC
V oltage Range
Vcc . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
RESET#, A9 and OE# . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +11.5 V
The other pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to Vcc +0.5 V
Output Short Circuit Current (less than one second) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA
OPERATING TEMPERATURE AND VOLTAGE
Commercial (C) Grade
Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial (I) Grade
Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4 0°C to +85°C
VCC Supply Voltages
VCC range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to 3.6 V
ELECTRICAL CHARACTERISTICS
Note:
1. Minimum v o ltage may undersho o t to -2V during transitio n and f o r less than 20ns during transitio ns.
2. Maximum v oltage may oversho ot to Vcc+2V during transitio n and f o r less than 20ns during transitio ns .
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Symbol Description Min Typ Max Remark
Iilk Input Leak ± 1.0uA
Iilk9 A9 Leak 35uA A9=10.5V
Iolk Output Leak ± 1.0uA
Icr1 Read Current(5MHz) 10mA 16mA CE#=Vil,
OE#=Vih
Icr2 Read Current(1MHz) 2mA 4mA CE#=Vil,
OE#=Vih
Icw Write Current 15mA 30mA CE#=Vil,
OE#=Vih,
WE#=Vil
Isb Standby Current 5uA 15uA Vcc=Vcc max,
o ther pin disable
Isbr Reset Current 5uA 15uA Vcc=Vccmax,
Reset# enable,
o ther pin disable
Isbs Sleep Mo de Current 5uA 15uA
Icp1 Accelerated Pgm Current, 5mA 10mA CE#=Vil,
WP#/Acc pin(Wo rd/Byte) OE#=Vih,
Icp2 Accelerated Pgm Current, 15mA 30mA CE#=Vil,
Vcc pin,(Wo rd/Byte) OE#=Vih,
Vil Input Low V oltage -0.5V 0.8V
Vih Input High V o ltage 0.7xVcc Vcc+0.3V
Vhv V ery High V o ltage fo r hardware 9.5V 10.5V
Protect/Unprotect/Accelerated
Program/Auto Select/Tempo rary
Unprotect
V o l Output Low Voltage 0.45V Iol=4.0mA
V oh1 Ouput High V o ltage 0.85xVcc Ioh1=-2mA
V oh2 Ouput High V oltage Vcc-0.4V Io h2=-100uA
Vlko Low Vcc Lock-out Voltage 2.3V 2.5V
DC CHARACTERISTICS
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Test Condition
Output Lo ad : 1 TTL gate
Output Lo ad Capacitance,CL : 30pF
Rise/Fall Times : 5ns
In/Out reference levels :1.5V
SWITCHING TEST WAVEFORM
1.5V 1.5V
Test Points
3.0V
0.0V OUTPUT
INPUT
R1=6.2K ohm
R2=1.6K ohm
SWITCHING TEST CIRCUIT
TESTED DEVICE
DIODES=IN3064
OR EQUIVALENT
CL
R1
Vcc
0.1uF R2 +3.3V
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AC CHARACTERISTICS
Symbol Description Min Typ Max Unit
Ta a V alid data o utput after address 7 0 ns
Tce V alid data o utput after CE# low 7 0 n s
Toe V alid data o utput after OE# lo w 3 0 ns
Tdf Data o utput flo ating after OE# high 3 0 ns
Toh Output ho ld time fro m the earliest rising edge o f address, 0 ns
CE#, OE#
Trc Read period time 7 0 ns
Twc Write period time 7 0 ns
Tcwc Co mmand write period time 7 0 ns
Tas Address setup time 0 ns
Ta h Address ho ld time 4 5 ns
Tds Data setup time 4 5 ns
Tdh Data hold time 0 ns
Tvcs Vcc setup time 200 us
Tcs Chip enable Setup time 0 ns
Tch Chip enable ho ld time 0 ns
To es Output enable setup time 0 ns
Toeh Read 0 ns
Toe h Output enable ho ld time To ggle & 10 ns
Data# Polling
Tws WE# setup time 0 ns
Tw h WE# ho ld time 0 ns
Tcep CE# pulse width 4 5 ns
Tceph CE# pulse width high 3 0 ns
Tw p WE# pulse width 3 5 ns
Tw ph WE# pulse width high 3 0 ns
Tbusy Pro g ram/Erase activ e time b y R Y/BY# 90 ns
Tghwl Read reco ver time befo re write 0 ns
Tghel Read reco ver time bef ore write 0 ns
T whwh1 Program operation Byte 9 300 us
T whwh1 Program operation Word 11 360 us
Twhwh1 Acc pro gram o peration (Wo rd/Byte) 7 21 0 us
Twhwh2 Sector erase operation 0.7 2 sec
Tbal Secto r add hold time 3 5 5 0 us
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Figure 1. COMMAND WRITE OPERATION
Addresses
CE#
OE#
WE#
DIN
Tds
Tah
Data
Tdh
Tcs Tch
Tcwc
Twph
Twp
Toes
Tas
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
VA
V A: Valid Address
WRITE COMMAND OPERATION
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READ/RESET OPERATION
Figure 2. READ TIMING W A VEFORM
Addresses
CE#
OE#
Taa
WE#
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Voh
Vol
HIGH Z HIGH Z
D ATA V alid
Toe
Toeh Tdf
Tce
Trc
Outputs
Toh
ADD V alid
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Figure 3. RESET# TIMING W AVEFORM
AC CHARACTERISTICS
Item Description Setup Speed Unit
Trp 1 RESET# Pulse Width (During Auto matic Algorithms) MIN 1 0 us
Trp 2 RESET# Pulse Width (NOT During Auto matic Algorithms) MIN 5 00 ns
Tr h RESET# High Time Before Read MIN 7 0 ns
Tr b 1 R Y/BY# Reco very Time (to CE#, OE# go low) MI N 0 ns
Tr b2 RY/BY# Reco very Time (to WE# go low) MIN 5 0 ns
Tready1 RESET# PIN Low (During Auto matic Algorithms) MAX 2 0 us
to Read or Write
Tready2 RESET# PIN Low (NOT During Auto matic MAX 500 ns
Algo rithms) to Read or Write
Trh
Trb1
Trp2
Trp1
Tready2
Tready1
RY/BY#
CE#, OE#
RESET#
Reset Timing NOT during Automatic Algorithms
Reset Timing during Automatic Algorithms
RY/BY#
CE#, OE#
Trb2
WE#
RESET#
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ERASE/PROGRAM OPERATION
Figure 4. AUTOMA TIC CHIP ERASE TIMING W A VEFORM
Twc
Address
OE#
CE#
55h
2AAh SA
10h
In
Progress Complete
VA VA
Tas Tah
SA: 555h for chip erase
Tghwl
Tch
Twp
Tds Tdh
Read Status
Last 2 Erase Command Cycle
Tbusy Trb
Tcs Twph
WE#
Data
RY/BY#
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Figure 5. AUTOMA TIC CHIP ERASE ALGORITHM FLO WCHART
START
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data AAh Address 555h
Write Data 80h Address 555h
YES
NO Data=FFh ?
Write Data 10h Address 555h
Write Data 55h Address 2AAh
Data# Polling Algorithm or
Toggle Bit Algorithm
Auto Chip Erase Completed
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KH29LV320D T/B
Figure 6. A UTOMATIC SECTOR ERASE TIMING W A VEFORM
Twc
Address
OE#
CE#
55h
2AAh Sector
Address 1
Sector
Address 0
30h
In
Progress Complete
VA VA
30h
Sector
Address n
Tas
Tah
Tbal
Tghwl
Tch
Twp
Tds Tdh
Twhwh2
Read Status
Last 2 Erase Command Cycle
Tbusy Trb
Tcs Twph
WE#
Data
RY/BY#
30h
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Figure 7. A UTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data AAh Address 555h
Write Data 80h Address 555h
Write Data 30h Sector Address
Write Data 55h Address 2AAh
Data# Polling Algorithm or
Toggle Bit Algorithm
Auto Sector Erase Completed
NO
Last Sector
to Erase ?
YES
YES
NO
Data=FFh ?
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Figure 8. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0h
Toggle Bit checking Q6
not toggled ?
ERASE SUSPEND
YES
NO
Write Data 30h
Continue Erase
Reading or
Programming End
Read Array or
Program
Another
Erase Suspend ? NO
YES
YES
NO
ERASE RESUME
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Figure 9. A UTOMATIC PROGRAM TIMING W A VEFORM
Address
OE#
CE#
A0h
555h PA
PD Status DOUT
VA VA
Tas Tah
Tghwl
Tch
Twp
Tds Tdh
Twhwh1
Last 2 Read Status CycleLast 2 Program Command Cycle
Tbusy Trb
Tcs Twph
WE#
Data
RY/BY#
Figure 10. ACCELERA TED PROGRAM TIMING DIA GRAM
WP#/ACC
250ns 250ns
Vhv (9.5V ~ 10.5V)
Vil or Vih Vil or Vih
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Figure 11. CE# CONTROLLED WRITE TIMING W A VEFORM
Address
OE#
CE#
A0h
555h PA
PD Status DOUT
VA VA
Tas Tah
Tghwl
Tcep
Tds Tdh
Twhwh1 or Twhwh2
Tbusy
Tceph
WE#
Data
RY/BY#
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Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLO WCHART
START
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Program Data/Address
Write Data A0h Address 555h
YES
Read Again Data:
Program Data ?
YES
Auto Program Completed
Data# Polling Algorithm or
Toggle Bit Algorithm
next address
Last Word to be
Programed ?
No
No
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SECTOR GROUP PROTECT/CHIP UNPROTECT
Figure 13. SECTOR GROUP PROTECT/CHIP UNPROTECT W A VEFORM (RESET# Control)
150us: Sector Protect
15ms: Chip Unprotect
1us
Vhv
Vih
Data
SA, A6
A1, A0
CE#
WE#
OE#
VA VA VA
Status
VA: valid address
40h60h60h
Verification
RESET#
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Figure 14. IN-SYSTEM SECTOR GROUP PROTECT WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 60h
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 40h
Read at Sector Address
with [A6,A1,A0]:[0,1,0]
Wait 150us
Reset
PLSCNT=1
Temporary Unprotect Mode
RESET#=Vih
Write RESET CMD
Sector Protect Done
Device fail
Temporary Unprotect Mode
Retry Count +1
First CMD=60h?
Data=01h?
Retry Count=25?
Yes
YesYes
Yes
No
No
No
No
Protect another
sector?
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Figure 15. CHIP UNPROTECT ALGORITHM WITH RESET#=Vhv
Write [A6,A1,A0]:[1,1,0]
data: 60h
Write [A6,A1,A0]:[1,1,0]
data: 40h
Read [A6,A1,A0]:[1,1,0]
Wait 15ms
Temporary Unprotect
RESET#=Vih
Write reset CMD
Chip Unprotect Done
Retry Count +1
Device fail
All sectors
protected?
Data=00h?
Last sector
verified?
Retry Count=1000?
Yes
Yes
Yes
No
No
No
Yes
Protect All Sectors
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect
First CMD=60h?
Yes
No
No
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Figure 16. TEMPORAR Y SECTOR GROUP UNPRO TECT WA VEFORM
T able 5. TEMPORARY SECT OR GROUP UNPROTECT
Parameter Alt Description Condition Speed Unit
Trpvhh Tvidr RESET# Rise Time to Vhv and Vhv Fall Time to RESET# MIN 500 ns
Tvhhwl Trsp RESET# Vhv to WE# Low MIN 4 us
RESET#
CE#
WE#
RY/BY#
Trpvhh
10V
Vhv
0 or Vih Vil or Vih
Tvhhwl
Trpvhh
Program or Erase Command Sequence
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Figure 17. TEMPORAR Y SECTOR GROUP UNPROTECT FLOWCHART
Start
Apply Reset# pin Vhv Volt
Enter Program or Erase Mode
(1) Remove Vhv Volt from Reset#
(2) RESET# = Vih
Completed Temporary Sector
Unprotected Mode
Mode Operation Completed
Notes:
1. Tempo rary unprotect all pro tected sectors Vhv=9.5~10.5V.
2. After leaving tempo rary unprotect mo de, the previo usly protected secto rs are again protected.
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Figure 18. SILICON ID READ TIMING W A VEFORM
Taa
Tce
Taa
Toe
Toh Toh
Tdf
DATA OUT
C2h A7h (Top boot)
A8h (Bottom boot)
Vhv
Vih
Vil
A9
ADD
CE#
A1, A6
OE#
WE#
A0
DATA OUT
DATA
Q0-Q7
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
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KH29LV320D T/B
WRITE OPERATION STATUS
Figure 19. DAT A# POLLING TIMING W A VEFORM (DURING AUTOMATIC ALGORITHM)
Tdf
Tce
Tch
Toe
Toeh
Toh
CE#
OE#
WE#
Q7
Q0-Q6
RY/BY#
Tbusy
Status Data Status Data
Status Data Complement True Valid Data
Taa
Trc
Address
VAVA
High Z
High Z
Valid DataTrue
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Figure 20. DAT A# POLLING ALGORITHM
Read Q7~Q0 at valid address
(Note 1)
Read Q7~Q0 at valid address
Start
Q7 = Data# ?
Q5 = 1 ?
Q7 = Data# ?
(Note 2)
FAIL Pass
No
No
No
Yes
Yes
Yes
Notes:
1 . Fo r programming, valid address means pro gram address.
F o r erasing, valid address means erase secto rs address .
2. Q7 sho uld be rechec ked e ven Q5="1" because Q7 ma y change simultaneo usly with Q5.
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KH29LV320D T/B
Figure 21. T OGGLE BIT TIMING W A VEFORM (DURING AUTOMA TIC ALGORITHM)
Tdf
Tce
Tch
Toe
Toeh
Taa
Trc
Toh
Address
CE#
OE#
WE#
Q6/Q2
RY/BY#
Tbusy
Valid Status
(first read)
Valid Status
(second read) (stops toggling)
Valid Data
VA VA
VA
VA : Valid Address
VA
Valid Data
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KH29LV320D T/B
Figure 22. TOGGLE BIT ALGORITHM
Notes:
1. Read to ggle bit twice to determine whether or no t it is to ggling.
2. Recheck toggle bit because it may stop to ggling as Q5 changes to "1".
Read Q7-Q0 Twice
Q5 = 1?
Read Q7~Q0 Twice
Program/Erase fail
Write Reset CMD Program/Erase Complete
Q6 Toggle ?
Q6 Toggle ?
NO
(Note 1)
YES
NO
NO
YES
YES
Start
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Figure 23. BYTE# TIMING W AVEFORM FOR READ OPERATIONS (BYTE# switching fr om byte mode to word
mode)
AC CHARACTERISTICS
WORD/BYTE CONFIGURA TION (BYTE#)
Parameter Description Speed Options Unit
70
Telfl/Telfh CE# to BYTE# fro m L/H MAX 5 ns
Tflqz BYTE# from L to Output Hiz MAX 25 ns
Tfhq v BYTE# from H to Output Active MIN 70 ns
Tfhqv
Telfh
DOUT
(Q0-Q7) DOUT
(Q0-Q14)
VA DOUT
(Q15)
CE#
OE#
BYTE#
Q0~Q14
Q15/A-1
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RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is reco mmended fo r the supply v o ltages and the co ntro l signals at device po wer-up.
If the timing in the figure is igno red, the device may not o per ate correctly.
Figure A. AC Timing at Device P ower-Up
Symbol Parameter Min. Max. Unit
Tvr Vcc Rise Time 20 500000 us/V
Tr Input Signal Rise Time 2 0 us/V
Tf Input Signal F all Time 2 0 us/V
Tvcs Vcc Setup Time 200 us
Vcc
ADDRESS
CE#
WE#
OE#
DATA
Tvr
Taa
Tr or Tf Tr or Tf
Tce
Tf
Vcc(min)
GND
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Voh High Z
Vol
WP#/ACC
Valid
Ouput
Valid
Address
Tvcs
Tr
Toe
Tf Tr
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KH29LV320D T/B
MIN. MAX.
Input voltage difference with GND on all pins except I/O pins -1.0V 11.5V
Input voltage difference with GND on all I/O pins -1.0V 1.5 x V cc
Vcc Current -100mA +100mA
All pins included except Vcc. Test conditions: Vcc = 3.0V, one pin per testing
LIMITS
PARAMETER MIN. TYP. MAX. UNITS
Chip Erase Time 3 5 50 sec
Sector Erase Time 0. 7 2 sec
Erase/Program Cycles 100,000 Cycles
Chip Programming Time Byte Mode 3 6 1 0 8 sec
Word Mode 24 72 sec
Accelerated Byte/Word Program Time 7 21 0 us
Word Program Time 1 1 360 us
Byte Programming Time 9 30 0 us
LATCH-UP CHARACTERISTICS
ERASE AND PROGRAMMING PERFORMANCE
Parameter Symbol Parameter Description Test Set TYP MAX UNIT
CIN2 Control Pin Capacitance VIN=0 7.5 9 pF
COUT Output Capacitance VOUT=0 8.5 1 2 pF
CIN Input Capacitance VIN=0 6 7.5 pF
TSOP PIN CAPACITANCE
Notes:
1. Typical program and er ase times assume the f ollowing conditio ns: 25°C , 3.0V VCC . Pro g ramming specifications
assume checkbo ard data pattern.
2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and
including 100,000 program/erase cycles.
3. Erase/Pro gram cycles co mply with JEDEC JESD-47E & A117A standard.
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PART NO. ACCESS TIME Ball Pitch/ PACKAGE Remark
(ns) Ball Size
KH29LV320DTTC-70G 70 - 48 Pin TSOP Pb-free
KH29LV320DBTC-70G 70 - 48 Pin TSOP Pb-free
ORDERING INFORMATION
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KH29LV320D T/B
PART NAME DESCRIPTION
KH 29 LV 70D T T C G
OPTION:
G: Pb-free package
SPEED:
70: 70ns
TEMPERATURE RANGE:
C: Commercial (0ËšC to 70ËšC)
PACKAGE:
BOOT BLOCK TYPE:
T: Top Boot
B: Bottom Boot
REVISION:
D
DENSITY & MODE:
320: 32Mb, x8/x16 Boot Block
TYPE:
LV: 3V
DEVICE:
29:Flash
320
T: TSOP
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PACKAGE INFORMATION
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P/N:PM1398 REV. 0.01, MAY 20, 2008
KH29LV320D T/B
REVISION HISTORY
Revision No. Description Page Date
0.01 1. Changed Toe spec from 40ns to 30ns P 34 MAY/20/2008
2. Re vised Vhv data from 10.5V~11.5V to 9.5V~10.5V P32,43,49,50
KH29LV320D T/B
63
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Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure
of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or
proper ty, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix
and its suppliers will not be liable to y ou and/o r any third party for any claims, injuries or damages that may be incurred due
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